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-rw-r--r--drivers/extcon/extcon-max77693.c35
-rw-r--r--drivers/gpio/Kconfig13
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-crystalcove.c380
-rw-r--r--drivers/mfd/Kconfig13
-rw-r--r--drivers/mfd/Makefile5
-rw-r--r--drivers/mfd/intel_soc_pmic_core.c168
-rw-r--r--drivers/mfd/intel_soc_pmic_core.h32
-rw-r--r--drivers/mfd/intel_soc_pmic_crc.c158
-rw-r--r--drivers/mfd/max77693-irq.c336
-rw-r--r--drivers/mfd/max77693.c210
-rw-r--r--drivers/regulator/max77693.c12
-rw-r--r--include/linux/mfd/intel_soc_pmic.h30
-rw-r--r--include/linux/mfd/max77693-private.h54
14 files changed, 1014 insertions, 433 deletions
diff --git a/drivers/extcon/extcon-max77693.c b/drivers/extcon/extcon-max77693.c
index 2c7c3e191591..c7278b1649da 100644
--- a/drivers/extcon/extcon-max77693.c
+++ b/drivers/extcon/extcon-max77693.c
@@ -255,10 +255,10 @@ static int max77693_muic_set_debounce_time(struct max77693_muic_info *info,
255 case ADC_DEBOUNCE_TIME_10MS: 255 case ADC_DEBOUNCE_TIME_10MS:
256 case ADC_DEBOUNCE_TIME_25MS: 256 case ADC_DEBOUNCE_TIME_25MS:
257 case ADC_DEBOUNCE_TIME_38_62MS: 257 case ADC_DEBOUNCE_TIME_38_62MS:
258 ret = max77693_update_reg(info->max77693->regmap_muic, 258 ret = regmap_update_bits(info->max77693->regmap_muic,
259 MAX77693_MUIC_REG_CTRL3, 259 MAX77693_MUIC_REG_CTRL3,
260 time << CONTROL3_ADCDBSET_SHIFT, 260 CONTROL3_ADCDBSET_MASK,
261 CONTROL3_ADCDBSET_MASK); 261 time << CONTROL3_ADCDBSET_SHIFT);
262 if (ret) { 262 if (ret) {
263 dev_err(info->dev, "failed to set ADC debounce time\n"); 263 dev_err(info->dev, "failed to set ADC debounce time\n");
264 return ret; 264 return ret;
@@ -286,15 +286,15 @@ static int max77693_muic_set_path(struct max77693_muic_info *info,
286 u8 val, bool attached) 286 u8 val, bool attached)
287{ 287{
288 int ret = 0; 288 int ret = 0;
289 u8 ctrl1, ctrl2 = 0; 289 unsigned int ctrl1, ctrl2 = 0;
290 290
291 if (attached) 291 if (attached)
292 ctrl1 = val; 292 ctrl1 = val;
293 else 293 else
294 ctrl1 = CONTROL1_SW_OPEN; 294 ctrl1 = CONTROL1_SW_OPEN;
295 295
296 ret = max77693_update_reg(info->max77693->regmap_muic, 296 ret = regmap_update_bits(info->max77693->regmap_muic,
297 MAX77693_MUIC_REG_CTRL1, ctrl1, COMP_SW_MASK); 297 MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1);
298 if (ret < 0) { 298 if (ret < 0) {
299 dev_err(info->dev, "failed to update MUIC register\n"); 299 dev_err(info->dev, "failed to update MUIC register\n");
300 return ret; 300 return ret;
@@ -305,9 +305,9 @@ static int max77693_muic_set_path(struct max77693_muic_info *info,
305 else 305 else
306 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ 306 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */
307 307
308 ret = max77693_update_reg(info->max77693->regmap_muic, 308 ret = regmap_update_bits(info->max77693->regmap_muic,
309 MAX77693_MUIC_REG_CTRL2, ctrl2, 309 MAX77693_MUIC_REG_CTRL2,
310 CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK); 310 CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK, ctrl2);
311 if (ret < 0) { 311 if (ret < 0) {
312 dev_err(info->dev, "failed to update MUIC register\n"); 312 dev_err(info->dev, "failed to update MUIC register\n");
313 return ret; 313 return ret;
@@ -969,8 +969,8 @@ static void max77693_muic_irq_work(struct work_struct *work)
969 if (info->irq == muic_irqs[i].virq) 969 if (info->irq == muic_irqs[i].virq)
970 irq_type = muic_irqs[i].irq; 970 irq_type = muic_irqs[i].irq;
971 971
972 ret = max77693_bulk_read(info->max77693->regmap_muic, 972 ret = regmap_bulk_read(info->max77693->regmap_muic,
973 MAX77693_MUIC_REG_STATUS1, 2, info->status); 973 MAX77693_MUIC_REG_STATUS1, info->status, 2);
974 if (ret) { 974 if (ret) {
975 dev_err(info->dev, "failed to read MUIC register\n"); 975 dev_err(info->dev, "failed to read MUIC register\n");
976 mutex_unlock(&info->mutex); 976 mutex_unlock(&info->mutex);
@@ -1042,8 +1042,8 @@ static int max77693_muic_detect_accessory(struct max77693_muic_info *info)
1042 mutex_lock(&info->mutex); 1042 mutex_lock(&info->mutex);
1043 1043
1044 /* Read STATUSx register to detect accessory */ 1044 /* Read STATUSx register to detect accessory */
1045 ret = max77693_bulk_read(info->max77693->regmap_muic, 1045 ret = regmap_bulk_read(info->max77693->regmap_muic,
1046 MAX77693_MUIC_REG_STATUS1, 2, info->status); 1046 MAX77693_MUIC_REG_STATUS1, info->status, 2);
1047 if (ret) { 1047 if (ret) {
1048 dev_err(info->dev, "failed to read MUIC register\n"); 1048 dev_err(info->dev, "failed to read MUIC register\n");
1049 mutex_unlock(&info->mutex); 1049 mutex_unlock(&info->mutex);
@@ -1095,7 +1095,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1095 int delay_jiffies; 1095 int delay_jiffies;
1096 int ret; 1096 int ret;
1097 int i; 1097 int i;
1098 u8 id; 1098 unsigned int id;
1099 1099
1100 info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info), 1100 info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info),
1101 GFP_KERNEL); 1101 GFP_KERNEL);
@@ -1154,7 +1154,8 @@ static int max77693_muic_probe(struct platform_device *pdev)
1154 struct max77693_muic_irq *muic_irq = &muic_irqs[i]; 1154 struct max77693_muic_irq *muic_irq = &muic_irqs[i];
1155 unsigned int virq = 0; 1155 unsigned int virq = 0;
1156 1156
1157 virq = irq_create_mapping(max77693->irq_domain, muic_irq->irq); 1157 virq = regmap_irq_get_virq(max77693->irq_data_muic,
1158 muic_irq->irq);
1158 if (!virq) { 1159 if (!virq) {
1159 ret = -EINVAL; 1160 ret = -EINVAL;
1160 goto err_irq; 1161 goto err_irq;
@@ -1204,7 +1205,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1204 enum max77693_irq_source irq_src 1205 enum max77693_irq_source irq_src
1205 = MAX77693_IRQ_GROUP_NR; 1206 = MAX77693_IRQ_GROUP_NR;
1206 1207
1207 max77693_write_reg(info->max77693->regmap_muic, 1208 regmap_write(info->max77693->regmap_muic,
1208 init_data[i].addr, 1209 init_data[i].addr,
1209 init_data[i].data); 1210 init_data[i].data);
1210 1211
@@ -1262,7 +1263,7 @@ static int max77693_muic_probe(struct platform_device *pdev)
1262 max77693_muic_set_path(info, info->path_uart, true); 1263 max77693_muic_set_path(info, info->path_uart, true);
1263 1264
1264 /* Check revision number of MUIC device*/ 1265 /* Check revision number of MUIC device*/
1265 ret = max77693_read_reg(info->max77693->regmap_muic, 1266 ret = regmap_read(info->max77693->regmap_muic,
1266 MAX77693_MUIC_REG_ID, &id); 1267 MAX77693_MUIC_REG_ID, &id);
1267 if (ret < 0) { 1268 if (ret < 0) {
1268 dev_err(&pdev->dev, "failed to read revision number\n"); 1269 dev_err(&pdev->dev, "failed to read revision number\n");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 4a1b5113e527..4a065b45330f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -450,6 +450,19 @@ config GPIO_ARIZONA
450 help 450 help
451 Support for GPIOs on Wolfson Arizona class devices. 451 Support for GPIOs on Wolfson Arizona class devices.
452 452
453config GPIO_CRYSTAL_COVE
454 tristate "GPIO support for Crystal Cove PMIC"
455 depends on INTEL_SOC_PMIC
456 select GPIOLIB_IRQCHIP
457 help
458 Support for GPIO pins on Crystal Cove PMIC.
459
460 Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
461 inside.
462
463 This driver can also be built as a module. If so, the module will be
464 called gpio-crystalcove.
465
453config GPIO_LP3943 466config GPIO_LP3943
454 tristate "TI/National Semiconductor LP3943 GPIO expander" 467 tristate "TI/National Semiconductor LP3943 GPIO expander"
455 depends on MFD_LP3943 468 depends on MFD_LP3943
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index d10f6a9d875a..e18e9564b073 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
20obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o 20obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
21obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o 21obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
22obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o 22obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
23obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o
23obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o 24obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
24obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o 25obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
25obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o 26obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c
new file mode 100644
index 000000000000..934462f5bd22
--- /dev/null
+++ b/drivers/gpio/gpio-crystalcove.c
@@ -0,0 +1,380 @@
1/*
2 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
3 *
4 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 */
17
18#include <linux/interrupt.h>
19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/seq_file.h>
22#include <linux/bitops.h>
23#include <linux/regmap.h>
24#include <linux/mfd/intel_soc_pmic.h>
25
26#define CRYSTALCOVE_GPIO_NUM 16
27
28#define UPDATE_IRQ_TYPE BIT(0)
29#define UPDATE_IRQ_MASK BIT(1)
30
31#define GPIO0IRQ 0x0b
32#define GPIO1IRQ 0x0c
33#define MGPIO0IRQS0 0x19
34#define MGPIO1IRQS0 0x1a
35#define MGPIO0IRQSX 0x1b
36#define MGPIO1IRQSX 0x1c
37#define GPIO0P0CTLO 0x2b
38#define GPIO0P0CTLI 0x33
39#define GPIO1P0CTLO 0x3b
40#define GPIO1P0CTLI 0x43
41
42#define CTLI_INTCNT_DIS (0)
43#define CTLI_INTCNT_NE (1 << 1)
44#define CTLI_INTCNT_PE (2 << 1)
45#define CTLI_INTCNT_BE (3 << 1)
46
47#define CTLO_DIR_IN (0)
48#define CTLO_DIR_OUT (1 << 5)
49
50#define CTLO_DRV_CMOS (0)
51#define CTLO_DRV_OD (1 << 4)
52
53#define CTLO_DRV_REN (1 << 3)
54
55#define CTLO_RVAL_2KDW (0)
56#define CTLO_RVAL_2KUP (1 << 1)
57#define CTLO_RVAL_50KDW (2 << 1)
58#define CTLO_RVAL_50KUP (3 << 1)
59
60#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
61#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
62
63enum ctrl_register {
64 CTRL_IN,
65 CTRL_OUT,
66};
67
68/**
69 * struct crystalcove_gpio - Crystal Cove GPIO controller
70 * @buslock: for bus lock/sync and unlock.
71 * @chip: the abstract gpio_chip structure.
72 * @regmap: the regmap from the parent device.
73 * @update: pending IRQ setting update, to be written to the chip upon unlock.
74 * @intcnt_value: the Interrupt Detect value to be written.
75 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
76 */
77struct crystalcove_gpio {
78 struct mutex buslock; /* irq_bus_lock */
79 struct gpio_chip chip;
80 struct regmap *regmap;
81 int update;
82 int intcnt_value;
83 bool set_irq_mask;
84};
85
86static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
87{
88 return container_of(gc, struct crystalcove_gpio, chip);
89}
90
91static inline int to_reg(int gpio, enum ctrl_register reg_type)
92{
93 int reg;
94
95 if (reg_type == CTRL_IN) {
96 if (gpio < 8)
97 reg = GPIO0P0CTLI;
98 else
99 reg = GPIO1P0CTLI;
100 } else {
101 if (gpio < 8)
102 reg = GPIO0P0CTLO;
103 else
104 reg = GPIO1P0CTLO;
105 }
106
107 return reg + gpio % 8;
108}
109
110static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
111 int gpio)
112{
113 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
114 int mask = BIT(gpio % 8);
115
116 if (cg->set_irq_mask)
117 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
118 else
119 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
120}
121
122static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
123{
124 int reg = to_reg(gpio, CTRL_IN);
125
126 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
127}
128
129static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
130{
131 struct crystalcove_gpio *cg = to_cg(chip);
132
133 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
134 CTLO_INPUT_SET);
135}
136
137static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
138 int value)
139{
140 struct crystalcove_gpio *cg = to_cg(chip);
141
142 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
143 CTLO_OUTPUT_SET | value);
144}
145
146static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
147{
148 struct crystalcove_gpio *cg = to_cg(chip);
149 int ret;
150 unsigned int val;
151
152 ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
153 if (ret)
154 return ret;
155
156 return val & 0x1;
157}
158
159static void crystalcove_gpio_set(struct gpio_chip *chip,
160 unsigned gpio, int value)
161{
162 struct crystalcove_gpio *cg = to_cg(chip);
163
164 if (value)
165 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
166 else
167 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
168}
169
170static int crystalcove_irq_type(struct irq_data *data, unsigned type)
171{
172 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
173
174 switch (type) {
175 case IRQ_TYPE_NONE:
176 cg->intcnt_value = CTLI_INTCNT_DIS;
177 break;
178 case IRQ_TYPE_EDGE_BOTH:
179 cg->intcnt_value = CTLI_INTCNT_BE;
180 break;
181 case IRQ_TYPE_EDGE_RISING:
182 cg->intcnt_value = CTLI_INTCNT_PE;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 cg->intcnt_value = CTLI_INTCNT_NE;
186 break;
187 default:
188 return -EINVAL;
189 }
190
191 cg->update |= UPDATE_IRQ_TYPE;
192
193 return 0;
194}
195
196static void crystalcove_bus_lock(struct irq_data *data)
197{
198 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
199
200 mutex_lock(&cg->buslock);
201}
202
203static void crystalcove_bus_sync_unlock(struct irq_data *data)
204{
205 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
206 int gpio = data->hwirq;
207
208 if (cg->update & UPDATE_IRQ_TYPE)
209 crystalcove_update_irq_ctrl(cg, gpio);
210 if (cg->update & UPDATE_IRQ_MASK)
211 crystalcove_update_irq_mask(cg, gpio);
212 cg->update = 0;
213
214 mutex_unlock(&cg->buslock);
215}
216
217static void crystalcove_irq_unmask(struct irq_data *data)
218{
219 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
220
221 cg->set_irq_mask = false;
222 cg->update |= UPDATE_IRQ_MASK;
223}
224
225static void crystalcove_irq_mask(struct irq_data *data)
226{
227 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
228
229 cg->set_irq_mask = true;
230 cg->update |= UPDATE_IRQ_MASK;
231}
232
233static struct irq_chip crystalcove_irqchip = {
234 .name = "Crystal Cove",
235 .irq_mask = crystalcove_irq_mask,
236 .irq_unmask = crystalcove_irq_unmask,
237 .irq_set_type = crystalcove_irq_type,
238 .irq_bus_lock = crystalcove_bus_lock,
239 .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
240};
241
242static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
243{
244 struct crystalcove_gpio *cg = data;
245 unsigned int p0, p1;
246 int pending;
247 int gpio;
248 unsigned int virq;
249
250 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
251 regmap_read(cg->regmap, GPIO1IRQ, &p1))
252 return IRQ_NONE;
253
254 regmap_write(cg->regmap, GPIO0IRQ, p0);
255 regmap_write(cg->regmap, GPIO1IRQ, p1);
256
257 pending = p0 | p1 << 8;
258
259 for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
260 if (pending & BIT(gpio)) {
261 virq = irq_find_mapping(cg->chip.irqdomain, gpio);
262 generic_handle_irq(virq);
263 }
264 }
265
266 return IRQ_HANDLED;
267}
268
269static void crystalcove_gpio_dbg_show(struct seq_file *s,
270 struct gpio_chip *chip)
271{
272 struct crystalcove_gpio *cg = to_cg(chip);
273 int gpio, offset;
274 unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
275
276 for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
277 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
278 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
279 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
280 &mirqs0);
281 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
282 &mirqsx);
283 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
284 &irq);
285
286 offset = gpio % 8;
287 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
288 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
289 ctli & 0x1 ? "hi" : "lo",
290 ctli & CTLI_INTCNT_NE ? "fall" : " ",
291 ctli & CTLI_INTCNT_PE ? "rise" : " ",
292 ctlo,
293 mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
294 mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
295 irq & BIT(offset) ? "pending" : " ");
296 }
297}
298
299static int crystalcove_gpio_probe(struct platform_device *pdev)
300{
301 int irq = platform_get_irq(pdev, 0);
302 struct crystalcove_gpio *cg;
303 int retval;
304 struct device *dev = pdev->dev.parent;
305 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
306
307 if (irq < 0)
308 return irq;
309
310 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
311 if (!cg)
312 return -ENOMEM;
313
314 platform_set_drvdata(pdev, cg);
315
316 mutex_init(&cg->buslock);
317 cg->chip.label = KBUILD_MODNAME;
318 cg->chip.direction_input = crystalcove_gpio_dir_in;
319 cg->chip.direction_output = crystalcove_gpio_dir_out;
320 cg->chip.get = crystalcove_gpio_get;
321 cg->chip.set = crystalcove_gpio_set;
322 cg->chip.base = -1;
323 cg->chip.ngpio = CRYSTALCOVE_GPIO_NUM;
324 cg->chip.can_sleep = true;
325 cg->chip.dev = dev;
326 cg->chip.dbg_show = crystalcove_gpio_dbg_show;
327 cg->regmap = pmic->regmap;
328
329 retval = gpiochip_add(&cg->chip);
330 if (retval) {
331 dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
332 return retval;
333 }
334
335 gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
336 handle_simple_irq, IRQ_TYPE_NONE);
337
338 retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
339 IRQF_ONESHOT, KBUILD_MODNAME, cg);
340
341 if (retval) {
342 dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
343 goto out_remove_gpio;
344 }
345
346 return 0;
347
348out_remove_gpio:
349 WARN_ON(gpiochip_remove(&cg->chip));
350 return retval;
351}
352
353static int crystalcove_gpio_remove(struct platform_device *pdev)
354{
355 struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
356 int irq = platform_get_irq(pdev, 0);
357 int err;
358
359 err = gpiochip_remove(&cg->chip);
360
361 if (irq >= 0)
362 free_irq(irq, cg);
363
364 return err;
365}
366
367static struct platform_driver crystalcove_gpio_driver = {
368 .probe = crystalcove_gpio_probe,
369 .remove = crystalcove_gpio_remove,
370 .driver = {
371 .name = "crystal_cove_gpio",
372 .owner = THIS_MODULE,
373 },
374};
375
376module_platform_driver(crystalcove_gpio_driver);
377
378MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
379MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
380MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6cc4b6acc22a..637501e826f9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -253,6 +253,18 @@ config LPC_SCH
253 LPC bridge function of the Intel SCH provides support for 253 LPC bridge function of the Intel SCH provides support for
254 System Management Bus and General Purpose I/O. 254 System Management Bus and General Purpose I/O.
255 255
256config INTEL_SOC_PMIC
257 bool "Support for Intel Atom SoC PMIC"
258 depends on I2C=y
259 select MFD_CORE
260 select REGMAP_I2C
261 select REGMAP_IRQ
262 help
263 Select this option to enable support for the PMIC device
264 on some Intel SoC systems. The PMIC provides ADC, GPIO,
265 thermal, charger and related power management functions
266 on these systems.
267
256config MFD_INTEL_MSIC 268config MFD_INTEL_MSIC
257 bool "Intel MSIC" 269 bool "Intel MSIC"
258 depends on INTEL_SCU_IPC 270 depends on INTEL_SCU_IPC
@@ -384,6 +396,7 @@ config MFD_MAX77693
384 depends on I2C=y 396 depends on I2C=y
385 select MFD_CORE 397 select MFD_CORE
386 select REGMAP_I2C 398 select REGMAP_I2C
399 select REGMAP_IRQ
387 help 400 help
388 Say yes here to add support for Maxim Semiconductor MAX77693. 401 Say yes here to add support for Maxim Semiconductor MAX77693.
389 This is a companion Power Management IC with Flash, Haptic, Charger, 402 This is a companion Power Management IC with Flash, Haptic, Charger,
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8afedba535c7..4e2bc255b8b0 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -116,7 +116,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
116 116
117obj-$(CONFIG_MFD_MAX14577) += max14577.o 117obj-$(CONFIG_MFD_MAX14577) += max14577.o
118obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o 118obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o
119obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o 119obj-$(CONFIG_MFD_MAX77693) += max77693.o
120obj-$(CONFIG_MFD_MAX8907) += max8907.o 120obj-$(CONFIG_MFD_MAX8907) += max8907.o
121max8925-objs := max8925-core.o max8925-i2c.o 121max8925-objs := max8925-core.o max8925-i2c.o
122obj-$(CONFIG_MFD_MAX8925) += max8925.o 122obj-$(CONFIG_MFD_MAX8925) += max8925.o
@@ -169,3 +169,6 @@ obj-$(CONFIG_MFD_AS3711) += as3711.o
169obj-$(CONFIG_MFD_AS3722) += as3722.o 169obj-$(CONFIG_MFD_AS3722) += as3722.o
170obj-$(CONFIG_MFD_STW481X) += stw481x.o 170obj-$(CONFIG_MFD_STW481X) += stw481x.o
171obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o 171obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
172
173intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
174obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
new file mode 100644
index 000000000000..cddbf5a72f89
--- /dev/null
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -0,0 +1,168 @@
1/*
2 * intel_soc_pmic_core.c - Intel SoC PMIC MFD Driver
3 *
4 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
17 */
18
19#include <linux/module.h>
20#include <linux/mfd/core.h>
21#include <linux/i2c.h>
22#include <linux/interrupt.h>
23#include <linux/gpio/consumer.h>
24#include <linux/acpi.h>
25#include <linux/regmap.h>
26#include <linux/mfd/intel_soc_pmic.h>
27#include "intel_soc_pmic_core.h"
28
29/*
30 * On some boards the PMIC interrupt may come from a GPIO line.
31 * Try to lookup the ACPI table and see if such connection exists. If not,
32 * return -ENOENT and use the IRQ provided by I2C.
33 */
34static int intel_soc_pmic_find_gpio_irq(struct device *dev)
35{
36 struct gpio_desc *desc;
37 int irq;
38
39 desc = devm_gpiod_get_index(dev, "intel_soc_pmic", 0);
40 if (IS_ERR(desc))
41 return -ENOENT;
42
43 irq = gpiod_to_irq(desc);
44 if (irq < 0)
45 dev_warn(dev, "Can't get irq: %d\n", irq);
46
47 return irq;
48}
49
50static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
51 const struct i2c_device_id *i2c_id)
52{
53 struct device *dev = &i2c->dev;
54 const struct acpi_device_id *id;
55 struct intel_soc_pmic_config *config;
56 struct intel_soc_pmic *pmic;
57 int ret;
58 int irq;
59
60 id = acpi_match_device(dev->driver->acpi_match_table, dev);
61 if (!id || !id->driver_data)
62 return -ENODEV;
63
64 config = (struct intel_soc_pmic_config *)id->driver_data;
65
66 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
67 dev_set_drvdata(dev, pmic);
68
69 pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
70
71 irq = intel_soc_pmic_find_gpio_irq(dev);
72 pmic->irq = (irq < 0) ? i2c->irq : irq;
73
74 ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
75 config->irq_flags | IRQF_ONESHOT,
76 0, config->irq_chip,
77 &pmic->irq_chip_data);
78 if (ret)
79 return ret;
80
81 ret = enable_irq_wake(pmic->irq);
82 if (ret)
83 dev_warn(dev, "Can't enable IRQ as wake source: %d\n", ret);
84
85 ret = mfd_add_devices(dev, -1, config->cell_dev,
86 config->n_cell_devs, NULL, 0,
87 regmap_irq_get_domain(pmic->irq_chip_data));
88 if (ret)
89 goto err_del_irq_chip;
90
91 return 0;
92
93err_del_irq_chip:
94 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
95 return ret;
96}
97
98static int intel_soc_pmic_i2c_remove(struct i2c_client *i2c)
99{
100 struct intel_soc_pmic *pmic = dev_get_drvdata(&i2c->dev);
101
102 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
103
104 mfd_remove_devices(&i2c->dev);
105
106 return 0;
107}
108
109static void intel_soc_pmic_shutdown(struct i2c_client *i2c)
110{
111 struct intel_soc_pmic *pmic = dev_get_drvdata(&i2c->dev);
112
113 disable_irq(pmic->irq);
114
115 return;
116}
117
118static int intel_soc_pmic_suspend(struct device *dev)
119{
120 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
121
122 disable_irq(pmic->irq);
123
124 return 0;
125}
126
127static int intel_soc_pmic_resume(struct device *dev)
128{
129 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
130
131 enable_irq(pmic->irq);
132
133 return 0;
134}
135
136static SIMPLE_DEV_PM_OPS(intel_soc_pmic_pm_ops, intel_soc_pmic_suspend,
137 intel_soc_pmic_resume);
138
139static const struct i2c_device_id intel_soc_pmic_i2c_id[] = {
140 { }
141};
142MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id);
143
144static struct acpi_device_id intel_soc_pmic_acpi_match[] = {
145 {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_crc},
146 { },
147};
148MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match);
149
150static struct i2c_driver intel_soc_pmic_i2c_driver = {
151 .driver = {
152 .name = "intel_soc_pmic_i2c",
153 .owner = THIS_MODULE,
154 .pm = &intel_soc_pmic_pm_ops,
155 .acpi_match_table = ACPI_PTR(intel_soc_pmic_acpi_match),
156 },
157 .probe = intel_soc_pmic_i2c_probe,
158 .remove = intel_soc_pmic_i2c_remove,
159 .id_table = intel_soc_pmic_i2c_id,
160 .shutdown = intel_soc_pmic_shutdown,
161};
162
163module_i2c_driver(intel_soc_pmic_i2c_driver);
164
165MODULE_DESCRIPTION("I2C driver for Intel SoC PMIC");
166MODULE_LICENSE("GPL v2");
167MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
168MODULE_AUTHOR("Zhu, Lejun <lejun.zhu@linux.intel.com>");
diff --git a/drivers/mfd/intel_soc_pmic_core.h b/drivers/mfd/intel_soc_pmic_core.h
new file mode 100644
index 000000000000..33aacd9baddc
--- /dev/null
+++ b/drivers/mfd/intel_soc_pmic_core.h
@@ -0,0 +1,32 @@
1/*
2 * intel_soc_pmic_core.h - Intel SoC PMIC MFD Driver
3 *
4 * Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
17 */
18
19#ifndef __INTEL_SOC_PMIC_CORE_H__
20#define __INTEL_SOC_PMIC_CORE_H__
21
22struct intel_soc_pmic_config {
23 unsigned long irq_flags;
24 struct mfd_cell *cell_dev;
25 int n_cell_devs;
26 struct regmap_config *regmap_config;
27 struct regmap_irq_chip *irq_chip;
28};
29
30extern struct intel_soc_pmic_config intel_soc_pmic_config_crc;
31
32#endif /* __INTEL_SOC_PMIC_CORE_H__ */
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
new file mode 100644
index 000000000000..7107cab832e6
--- /dev/null
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -0,0 +1,158 @@
1/*
2 * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
3 *
4 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
17 */
18
19#include <linux/mfd/core.h>
20#include <linux/interrupt.h>
21#include <linux/regmap.h>
22#include <linux/mfd/intel_soc_pmic.h>
23#include "intel_soc_pmic_core.h"
24
25#define CRYSTAL_COVE_MAX_REGISTER 0xC6
26
27#define CRYSTAL_COVE_REG_IRQLVL1 0x02
28#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
29
30#define CRYSTAL_COVE_IRQ_PWRSRC 0
31#define CRYSTAL_COVE_IRQ_THRM 1
32#define CRYSTAL_COVE_IRQ_BCU 2
33#define CRYSTAL_COVE_IRQ_ADC 3
34#define CRYSTAL_COVE_IRQ_CHGR 4
35#define CRYSTAL_COVE_IRQ_GPIO 5
36#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
37
38static struct resource gpio_resources[] = {
39 {
40 .name = "GPIO",
41 .start = CRYSTAL_COVE_IRQ_GPIO,
42 .end = CRYSTAL_COVE_IRQ_GPIO,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47static struct resource pwrsrc_resources[] = {
48 {
49 .name = "PWRSRC",
50 .start = CRYSTAL_COVE_IRQ_PWRSRC,
51 .end = CRYSTAL_COVE_IRQ_PWRSRC,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56static struct resource adc_resources[] = {
57 {
58 .name = "ADC",
59 .start = CRYSTAL_COVE_IRQ_ADC,
60 .end = CRYSTAL_COVE_IRQ_ADC,
61 .flags = IORESOURCE_IRQ,
62 },
63};
64
65static struct resource thermal_resources[] = {
66 {
67 .name = "THERMAL",
68 .start = CRYSTAL_COVE_IRQ_THRM,
69 .end = CRYSTAL_COVE_IRQ_THRM,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct resource bcu_resources[] = {
75 {
76 .name = "BCU",
77 .start = CRYSTAL_COVE_IRQ_BCU,
78 .end = CRYSTAL_COVE_IRQ_BCU,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct mfd_cell crystal_cove_dev[] = {
84 {
85 .name = "crystal_cove_pwrsrc",
86 .num_resources = ARRAY_SIZE(pwrsrc_resources),
87 .resources = pwrsrc_resources,
88 },
89 {
90 .name = "crystal_cove_adc",
91 .num_resources = ARRAY_SIZE(adc_resources),
92 .resources = adc_resources,
93 },
94 {
95 .name = "crystal_cove_thermal",
96 .num_resources = ARRAY_SIZE(thermal_resources),
97 .resources = thermal_resources,
98 },
99 {
100 .name = "crystal_cove_bcu",
101 .num_resources = ARRAY_SIZE(bcu_resources),
102 .resources = bcu_resources,
103 },
104 {
105 .name = "crystal_cove_gpio",
106 .num_resources = ARRAY_SIZE(gpio_resources),
107 .resources = gpio_resources,
108 },
109};
110
111static struct regmap_config crystal_cove_regmap_config = {
112 .reg_bits = 8,
113 .val_bits = 8,
114
115 .max_register = CRYSTAL_COVE_MAX_REGISTER,
116 .cache_type = REGCACHE_NONE,
117};
118
119static const struct regmap_irq crystal_cove_irqs[] = {
120 [CRYSTAL_COVE_IRQ_PWRSRC] = {
121 .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
122 },
123 [CRYSTAL_COVE_IRQ_THRM] = {
124 .mask = BIT(CRYSTAL_COVE_IRQ_THRM),
125 },
126 [CRYSTAL_COVE_IRQ_BCU] = {
127 .mask = BIT(CRYSTAL_COVE_IRQ_BCU),
128 },
129 [CRYSTAL_COVE_IRQ_ADC] = {
130 .mask = BIT(CRYSTAL_COVE_IRQ_ADC),
131 },
132 [CRYSTAL_COVE_IRQ_CHGR] = {
133 .mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
134 },
135 [CRYSTAL_COVE_IRQ_GPIO] = {
136 .mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
137 },
138 [CRYSTAL_COVE_IRQ_VHDMIOCP] = {
139 .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
140 },
141};
142
143static struct regmap_irq_chip crystal_cove_irq_chip = {
144 .name = "Crystal Cove",
145 .irqs = crystal_cove_irqs,
146 .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
147 .num_regs = 1,
148 .status_base = CRYSTAL_COVE_REG_IRQLVL1,
149 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
150};
151
152struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
153 .irq_flags = IRQF_TRIGGER_RISING,
154 .cell_dev = crystal_cove_dev,
155 .n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
156 .regmap_config = &crystal_cove_regmap_config,
157 .irq_chip = &crystal_cove_irq_chip,
158};
diff --git a/drivers/mfd/max77693-irq.c b/drivers/mfd/max77693-irq.c
deleted file mode 100644
index 66b58fe77094..000000000000
--- a/drivers/mfd/max77693-irq.c
+++ /dev/null
@@ -1,336 +0,0 @@
1/*
2 * max77693-irq.c - Interrupt controller support for MAX77693
3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * This driver is based on max8997-irq.c
24 */
25
26#include <linux/err.h>
27#include <linux/irq.h>
28#include <linux/interrupt.h>
29#include <linux/module.h>
30#include <linux/irqdomain.h>
31#include <linux/mfd/max77693.h>
32#include <linux/mfd/max77693-private.h>
33
34static const u8 max77693_mask_reg[] = {
35 [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK,
36 [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
37 [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK,
38 [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1,
39 [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2,
40 [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3,
41};
42
43static struct regmap *max77693_get_regmap(struct max77693_dev *max77693,
44 enum max77693_irq_source src)
45{
46 switch (src) {
47 case LED_INT ... CHG_INT:
48 return max77693->regmap;
49 case MUIC_INT1 ... MUIC_INT3:
50 return max77693->regmap_muic;
51 default:
52 return ERR_PTR(-EINVAL);
53 }
54}
55
56struct max77693_irq_data {
57 int mask;
58 enum max77693_irq_source group;
59};
60
61#define DECLARE_IRQ(idx, _group, _mask) \
62 [(idx)] = { .group = (_group), .mask = (_mask) }
63static const struct max77693_irq_data max77693_irqs[] = {
64 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0),
65 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1),
66 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2),
67 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3),
68 DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),
69
70 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0),
71 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1),
72 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3),
73
74 DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
75 DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2),
76 DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
77 DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
78 DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
79
80 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
81 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1),
82 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2),
83 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
84
85 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
86 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
87 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
88 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
89 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
90 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5),
91
92 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0),
93 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1),
94 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2),
95 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3),
96 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4),
97 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5),
98};
99
100static void max77693_irq_lock(struct irq_data *data)
101{
102 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
103
104 mutex_lock(&max77693->irqlock);
105}
106
107static void max77693_irq_sync_unlock(struct irq_data *data)
108{
109 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
110 int i;
111
112 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
113 u8 mask_reg = max77693_mask_reg[i];
114 struct regmap *map = max77693_get_regmap(max77693, i);
115
116 if (mask_reg == MAX77693_REG_INVALID ||
117 IS_ERR_OR_NULL(map))
118 continue;
119 max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i];
120
121 max77693_write_reg(map, max77693_mask_reg[i],
122 max77693->irq_masks_cur[i]);
123 }
124
125 mutex_unlock(&max77693->irqlock);
126}
127
128static const inline struct max77693_irq_data *
129irq_to_max77693_irq(struct max77693_dev *max77693, int irq)
130{
131 struct irq_data *data = irq_get_irq_data(irq);
132 return &max77693_irqs[data->hwirq];
133}
134
135static void max77693_irq_mask(struct irq_data *data)
136{
137 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
138 const struct max77693_irq_data *irq_data =
139 irq_to_max77693_irq(max77693, data->irq);
140
141 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
142 return;
143
144 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
145 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
146 else
147 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
148}
149
150static void max77693_irq_unmask(struct irq_data *data)
151{
152 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
153 const struct max77693_irq_data *irq_data =
154 irq_to_max77693_irq(max77693, data->irq);
155
156 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
157 return;
158
159 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
160 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
161 else
162 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
163}
164
165static struct irq_chip max77693_irq_chip = {
166 .name = "max77693",
167 .irq_bus_lock = max77693_irq_lock,
168 .irq_bus_sync_unlock = max77693_irq_sync_unlock,
169 .irq_mask = max77693_irq_mask,
170 .irq_unmask = max77693_irq_unmask,
171};
172
173#define MAX77693_IRQSRC_CHG (1 << 0)
174#define MAX77693_IRQSRC_TOP (1 << 1)
175#define MAX77693_IRQSRC_FLASH (1 << 2)
176#define MAX77693_IRQSRC_MUIC (1 << 3)
177static irqreturn_t max77693_irq_thread(int irq, void *data)
178{
179 struct max77693_dev *max77693 = data;
180 u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
181 u8 irq_src;
182 int ret;
183 int i, cur_irq;
184
185 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
186 &irq_src);
187 if (ret < 0) {
188 dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
189 ret);
190 return IRQ_NONE;
191 }
192
193 if (irq_src & MAX77693_IRQSRC_CHG)
194 /* CHG_INT */
195 ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
196 &irq_reg[CHG_INT]);
197
198 if (irq_src & MAX77693_IRQSRC_TOP)
199 /* TOPSYS_INT */
200 ret = max77693_read_reg(max77693->regmap,
201 MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
202
203 if (irq_src & MAX77693_IRQSRC_FLASH)
204 /* LED_INT */
205 ret = max77693_read_reg(max77693->regmap,
206 MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
207
208 if (irq_src & MAX77693_IRQSRC_MUIC)
209 /* MUIC INT1 ~ INT3 */
210 max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
211 MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
212
213 /* Apply masking */
214 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
215 if (i >= MUIC_INT1 && i <= MUIC_INT3)
216 irq_reg[i] &= max77693->irq_masks_cur[i];
217 else
218 irq_reg[i] &= ~max77693->irq_masks_cur[i];
219 }
220
221 /* Report */
222 for (i = 0; i < MAX77693_IRQ_NR; i++) {
223 if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
224 cur_irq = irq_find_mapping(max77693->irq_domain, i);
225 if (cur_irq)
226 handle_nested_irq(cur_irq);
227 }
228 }
229
230 return IRQ_HANDLED;
231}
232
233int max77693_irq_resume(struct max77693_dev *max77693)
234{
235 if (max77693->irq)
236 max77693_irq_thread(0, max77693);
237
238 return 0;
239}
240
241static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
242 irq_hw_number_t hw)
243{
244 struct max77693_dev *max77693 = d->host_data;
245
246 irq_set_chip_data(irq, max77693);
247 irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
248 irq_set_nested_thread(irq, 1);
249#ifdef CONFIG_ARM
250 set_irq_flags(irq, IRQF_VALID);
251#else
252 irq_set_noprobe(irq);
253#endif
254 return 0;
255}
256
257static struct irq_domain_ops max77693_irq_domain_ops = {
258 .map = max77693_irq_domain_map,
259};
260
261int max77693_irq_init(struct max77693_dev *max77693)
262{
263 struct irq_domain *domain;
264 int i;
265 int ret = 0;
266 u8 intsrc_mask;
267
268 mutex_init(&max77693->irqlock);
269
270 /* Mask individual interrupt sources */
271 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
272 struct regmap *map;
273 /* MUIC IRQ 0:MASK 1:NOT MASK */
274 /* Other IRQ 1:MASK 0:NOT MASK */
275 if (i >= MUIC_INT1 && i <= MUIC_INT3) {
276 max77693->irq_masks_cur[i] = 0x00;
277 max77693->irq_masks_cache[i] = 0x00;
278 } else {
279 max77693->irq_masks_cur[i] = 0xff;
280 max77693->irq_masks_cache[i] = 0xff;
281 }
282 map = max77693_get_regmap(max77693, i);
283
284 if (IS_ERR_OR_NULL(map))
285 continue;
286 if (max77693_mask_reg[i] == MAX77693_REG_INVALID)
287 continue;
288 if (i >= MUIC_INT1 && i <= MUIC_INT3)
289 max77693_write_reg(map, max77693_mask_reg[i], 0x00);
290 else
291 max77693_write_reg(map, max77693_mask_reg[i], 0xff);
292 }
293
294 domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR,
295 &max77693_irq_domain_ops, max77693);
296 if (!domain) {
297 dev_err(max77693->dev, "could not create irq domain\n");
298 ret = -ENODEV;
299 goto err_irq;
300 }
301 max77693->irq_domain = domain;
302
303 /* Unmask max77693 interrupt */
304 ret = max77693_read_reg(max77693->regmap,
305 MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask);
306 if (ret < 0) {
307 dev_err(max77693->dev, "fail to read PMIC register\n");
308 goto err_irq;
309 }
310
311 intsrc_mask &= ~(MAX77693_IRQSRC_CHG);
312 intsrc_mask &= ~(MAX77693_IRQSRC_FLASH);
313 intsrc_mask &= ~(MAX77693_IRQSRC_MUIC);
314 ret = max77693_write_reg(max77693->regmap,
315 MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask);
316 if (ret < 0) {
317 dev_err(max77693->dev, "fail to write PMIC register\n");
318 goto err_irq;
319 }
320
321 ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread,
322 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
323 "max77693-irq", max77693);
324 if (ret)
325 dev_err(max77693->dev, "Failed to request IRQ %d: %d\n",
326 max77693->irq, ret);
327
328err_irq:
329 return ret;
330}
331
332void max77693_irq_exit(struct max77693_dev *max77693)
333{
334 if (max77693->irq)
335 free_irq(max77693->irq, max77693);
336}
diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index 7e05428c756d..249c139ef04a 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -49,62 +49,62 @@ static const struct mfd_cell max77693_devs[] = {
49 { .name = "max77693-haptic", }, 49 { .name = "max77693-haptic", },
50}; 50};
51 51
52int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest) 52static const struct regmap_config max77693_regmap_config = {
53{ 53 .reg_bits = 8,
54 unsigned int val; 54 .val_bits = 8,
55 int ret; 55 .max_register = MAX77693_PMIC_REG_END,
56 56};
57 ret = regmap_read(map, reg, &val);
58 *dest = val;
59
60 return ret;
61}
62EXPORT_SYMBOL_GPL(max77693_read_reg);
63
64int max77693_bulk_read(struct regmap *map, u8 reg, int count, u8 *buf)
65{
66 int ret;
67
68 ret = regmap_bulk_read(map, reg, buf, count);
69
70 return ret;
71}
72EXPORT_SYMBOL_GPL(max77693_bulk_read);
73
74int max77693_write_reg(struct regmap *map, u8 reg, u8 value)
75{
76 int ret;
77
78 ret = regmap_write(map, reg, value);
79
80 return ret;
81}
82EXPORT_SYMBOL_GPL(max77693_write_reg);
83
84int max77693_bulk_write(struct regmap *map, u8 reg, int count, u8 *buf)
85{
86 int ret;
87 57
88 ret = regmap_bulk_write(map, reg, buf, count); 58static const struct regmap_irq max77693_led_irqs[] = {
59 { .mask = LED_IRQ_FLED2_OPEN, },
60 { .mask = LED_IRQ_FLED2_SHORT, },
61 { .mask = LED_IRQ_FLED1_OPEN, },
62 { .mask = LED_IRQ_FLED1_SHORT, },
63 { .mask = LED_IRQ_MAX_FLASH, },
64};
89 65
90 return ret; 66static const struct regmap_irq_chip max77693_led_irq_chip = {
91} 67 .name = "max77693-led",
92EXPORT_SYMBOL_GPL(max77693_bulk_write); 68 .status_base = MAX77693_LED_REG_FLASH_INT,
69 .mask_base = MAX77693_LED_REG_FLASH_INT_MASK,
70 .mask_invert = false,
71 .num_regs = 1,
72 .irqs = max77693_led_irqs,
73 .num_irqs = ARRAY_SIZE(max77693_led_irqs),
74};
93 75
94int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask) 76static const struct regmap_irq max77693_topsys_irqs[] = {
95{ 77 { .mask = TOPSYS_IRQ_T120C_INT, },
96 int ret; 78 { .mask = TOPSYS_IRQ_T140C_INT, },
79 { .mask = TOPSYS_IRQ_LOWSYS_INT, },
80};
97 81
98 ret = regmap_update_bits(map, reg, mask, val); 82static const struct regmap_irq_chip max77693_topsys_irq_chip = {
83 .name = "max77693-topsys",
84 .status_base = MAX77693_PMIC_REG_TOPSYS_INT,
85 .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
86 .mask_invert = false,
87 .num_regs = 1,
88 .irqs = max77693_topsys_irqs,
89 .num_irqs = ARRAY_SIZE(max77693_topsys_irqs),
90};
99 91
100 return ret; 92static const struct regmap_irq max77693_charger_irqs[] = {
101} 93 { .mask = CHG_IRQ_BYP_I, },
102EXPORT_SYMBOL_GPL(max77693_update_reg); 94 { .mask = CHG_IRQ_THM_I, },
95 { .mask = CHG_IRQ_BAT_I, },
96 { .mask = CHG_IRQ_CHG_I, },
97 { .mask = CHG_IRQ_CHGIN_I, },
98};
103 99
104static const struct regmap_config max77693_regmap_config = { 100static const struct regmap_irq_chip max77693_charger_irq_chip = {
105 .reg_bits = 8, 101 .name = "max77693-charger",
106 .val_bits = 8, 102 .status_base = MAX77693_CHG_REG_CHG_INT,
107 .max_register = MAX77693_PMIC_REG_END, 103 .mask_base = MAX77693_CHG_REG_CHG_INT_MASK,
104 .mask_invert = false,
105 .num_regs = 1,
106 .irqs = max77693_charger_irqs,
107 .num_irqs = ARRAY_SIZE(max77693_charger_irqs),
108}; 108};
109 109
110static const struct regmap_config max77693_regmap_muic_config = { 110static const struct regmap_config max77693_regmap_muic_config = {
@@ -113,11 +113,42 @@ static const struct regmap_config max77693_regmap_muic_config = {
113 .max_register = MAX77693_MUIC_REG_END, 113 .max_register = MAX77693_MUIC_REG_END,
114}; 114};
115 115
116static const struct regmap_irq max77693_muic_irqs[] = {
117 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
118 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
119 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
120 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
121
122 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
123 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
124 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
125 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
126 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
127 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
128
129 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },
130 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },
131 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, },
132 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, },
133 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, },
134 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, },
135};
136
137static const struct regmap_irq_chip max77693_muic_irq_chip = {
138 .name = "max77693-muic",
139 .status_base = MAX77693_MUIC_REG_INT1,
140 .mask_base = MAX77693_MUIC_REG_INTMASK1,
141 .mask_invert = true,
142 .num_regs = 3,
143 .irqs = max77693_muic_irqs,
144 .num_irqs = ARRAY_SIZE(max77693_muic_irqs),
145};
146
116static int max77693_i2c_probe(struct i2c_client *i2c, 147static int max77693_i2c_probe(struct i2c_client *i2c,
117 const struct i2c_device_id *id) 148 const struct i2c_device_id *id)
118{ 149{
119 struct max77693_dev *max77693; 150 struct max77693_dev *max77693;
120 u8 reg_data; 151 unsigned int reg_data;
121 int ret = 0; 152 int ret = 0;
122 153
123 max77693 = devm_kzalloc(&i2c->dev, 154 max77693 = devm_kzalloc(&i2c->dev,
@@ -139,7 +170,7 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
139 return ret; 170 return ret;
140 } 171 }
141 172
142 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2, 173 ret = regmap_read(max77693->regmap, MAX77693_PMIC_REG_PMIC_ID2,
143 &reg_data); 174 &reg_data);
144 if (ret < 0) { 175 if (ret < 0) {
145 dev_err(max77693->dev, "device not found on this channel\n"); 176 dev_err(max77693->dev, "device not found on this channel\n");
@@ -176,9 +207,45 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
176 goto err_regmap_muic; 207 goto err_regmap_muic;
177 } 208 }
178 209
179 ret = max77693_irq_init(max77693); 210 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
180 if (ret < 0) 211 IRQF_ONESHOT | IRQF_SHARED |
181 goto err_irq; 212 IRQF_TRIGGER_FALLING, 0,
213 &max77693_led_irq_chip,
214 &max77693->irq_data_led);
215 if (ret) {
216 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
217 goto err_regmap_muic;
218 }
219
220 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
221 IRQF_ONESHOT | IRQF_SHARED |
222 IRQF_TRIGGER_FALLING, 0,
223 &max77693_topsys_irq_chip,
224 &max77693->irq_data_topsys);
225 if (ret) {
226 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
227 goto err_irq_topsys;
228 }
229
230 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
231 IRQF_ONESHOT | IRQF_SHARED |
232 IRQF_TRIGGER_FALLING, 0,
233 &max77693_charger_irq_chip,
234 &max77693->irq_data_charger);
235 if (ret) {
236 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
237 goto err_irq_charger;
238 }
239
240 ret = regmap_add_irq_chip(max77693->regmap, max77693->irq,
241 IRQF_ONESHOT | IRQF_SHARED |
242 IRQF_TRIGGER_FALLING, 0,
243 &max77693_muic_irq_chip,
244 &max77693->irq_data_muic);
245 if (ret) {
246 dev_err(max77693->dev, "failed to add irq chip: %d\n", ret);
247 goto err_irq_muic;
248 }
182 249
183 pm_runtime_set_active(max77693->dev); 250 pm_runtime_set_active(max77693->dev);
184 251
@@ -190,8 +257,14 @@ static int max77693_i2c_probe(struct i2c_client *i2c,
190 return ret; 257 return ret;
191 258
192err_mfd: 259err_mfd:
193 max77693_irq_exit(max77693); 260 mfd_remove_devices(max77693->dev);
194err_irq: 261 regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
262err_irq_muic:
263 regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger);
264err_irq_charger:
265 regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
266err_irq_topsys:
267 regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
195err_regmap_muic: 268err_regmap_muic:
196 i2c_unregister_device(max77693->haptic); 269 i2c_unregister_device(max77693->haptic);
197err_i2c_haptic: 270err_i2c_haptic:
@@ -204,7 +277,12 @@ static int max77693_i2c_remove(struct i2c_client *i2c)
204 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 277 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
205 278
206 mfd_remove_devices(max77693->dev); 279 mfd_remove_devices(max77693->dev);
207 max77693_irq_exit(max77693); 280
281 regmap_del_irq_chip(max77693->irq, max77693->irq_data_muic);
282 regmap_del_irq_chip(max77693->irq, max77693->irq_data_charger);
283 regmap_del_irq_chip(max77693->irq, max77693->irq_data_topsys);
284 regmap_del_irq_chip(max77693->irq, max77693->irq_data_led);
285
208 i2c_unregister_device(max77693->muic); 286 i2c_unregister_device(max77693->muic);
209 i2c_unregister_device(max77693->haptic); 287 i2c_unregister_device(max77693->haptic);
210 288
@@ -222,8 +300,11 @@ static int max77693_suspend(struct device *dev)
222 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 300 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
223 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 301 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
224 302
225 if (device_may_wakeup(dev)) 303 if (device_may_wakeup(dev)) {
226 irq_set_irq_wake(max77693->irq, 1); 304 enable_irq_wake(max77693->irq);
305 disable_irq(max77693->irq);
306 }
307
227 return 0; 308 return 0;
228} 309}
229 310
@@ -232,9 +313,12 @@ static int max77693_resume(struct device *dev)
232 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); 313 struct i2c_client *i2c = container_of(dev, struct i2c_client, dev);
233 struct max77693_dev *max77693 = i2c_get_clientdata(i2c); 314 struct max77693_dev *max77693 = i2c_get_clientdata(i2c);
234 315
235 if (device_may_wakeup(dev)) 316 if (device_may_wakeup(dev)) {
236 irq_set_irq_wake(max77693->irq, 0); 317 disable_irq_wake(max77693->irq);
237 return max77693_irq_resume(max77693); 318 enable_irq(max77693->irq);
319 }
320
321 return 0;
238} 322}
239 323
240static const struct dev_pm_ops max77693_pm = { 324static const struct dev_pm_ops max77693_pm = {
diff --git a/drivers/regulator/max77693.c b/drivers/regulator/max77693.c
index 653a58b49cdf..c67ff05fc1dd 100644
--- a/drivers/regulator/max77693.c
+++ b/drivers/regulator/max77693.c
@@ -31,6 +31,7 @@
31#include <linux/mfd/max77693.h> 31#include <linux/mfd/max77693.h>
32#include <linux/mfd/max77693-private.h> 32#include <linux/mfd/max77693-private.h>
33#include <linux/regulator/of_regulator.h> 33#include <linux/regulator/of_regulator.h>
34#include <linux/regmap.h>
34 35
35#define CHGIN_ILIM_STEP_20mA 20000 36#define CHGIN_ILIM_STEP_20mA 20000
36 37
@@ -39,9 +40,9 @@
39static int max77693_chg_is_enabled(struct regulator_dev *rdev) 40static int max77693_chg_is_enabled(struct regulator_dev *rdev)
40{ 41{
41 int ret; 42 int ret;
42 u8 val; 43 unsigned int val;
43 44
44 ret = max77693_read_reg(rdev->regmap, rdev->desc->enable_reg, &val); 45 ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
45 if (ret) 46 if (ret)
46 return ret; 47 return ret;
47 48
@@ -57,12 +58,11 @@ static int max77693_chg_get_current_limit(struct regulator_dev *rdev)
57{ 58{
58 unsigned int chg_min_uA = rdev->constraints->min_uA; 59 unsigned int chg_min_uA = rdev->constraints->min_uA;
59 unsigned int chg_max_uA = rdev->constraints->max_uA; 60 unsigned int chg_max_uA = rdev->constraints->max_uA;
60 u8 reg, sel; 61 unsigned int reg, sel;
61 unsigned int val; 62 unsigned int val;
62 int ret; 63 int ret;
63 64
64 ret = max77693_read_reg(rdev->regmap, 65 ret = regmap_read(rdev->regmap, MAX77693_CHG_REG_CHG_CNFG_09, &reg);
65 MAX77693_CHG_REG_CHG_CNFG_09, &reg);
66 if (ret < 0) 66 if (ret < 0)
67 return ret; 67 return ret;
68 68
@@ -96,7 +96,7 @@ static int max77693_chg_set_current_limit(struct regulator_dev *rdev,
96 /* the first four codes for charger current are all 60mA */ 96 /* the first four codes for charger current are all 60mA */
97 sel += 3; 97 sel += 3;
98 98
99 return max77693_write_reg(rdev->regmap, 99 return regmap_write(rdev->regmap,
100 MAX77693_CHG_REG_CHG_CNFG_09, sel); 100 MAX77693_CHG_REG_CHG_CNFG_09, sel);
101} 101}
102/* end of CHARGER regulator ops */ 102/* end of CHARGER regulator ops */
diff --git a/include/linux/mfd/intel_soc_pmic.h b/include/linux/mfd/intel_soc_pmic.h
new file mode 100644
index 000000000000..abcbfcf32d10
--- /dev/null
+++ b/include/linux/mfd/intel_soc_pmic.h
@@ -0,0 +1,30 @@
1/*
2 * intel_soc_pmic.h - Intel SoC PMIC Driver
3 *
4 * Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
17 */
18
19#ifndef __INTEL_SOC_PMIC_H__
20#define __INTEL_SOC_PMIC_H__
21
22#include <linux/regmap.h>
23
24struct intel_soc_pmic {
25 int irq;
26 struct regmap *regmap;
27 struct regmap_irq_chip_data *irq_chip_data;
28};
29
30#endif /* __INTEL_SOC_PMIC_H__ */
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 3e050b933dd0..c466ff3e16b8 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -262,6 +262,41 @@ enum max77693_irq_source {
262 MAX77693_IRQ_GROUP_NR, 262 MAX77693_IRQ_GROUP_NR,
263}; 263};
264 264
265#define LED_IRQ_FLED2_OPEN BIT(0)
266#define LED_IRQ_FLED2_SHORT BIT(1)
267#define LED_IRQ_FLED1_OPEN BIT(2)
268#define LED_IRQ_FLED1_SHORT BIT(3)
269#define LED_IRQ_MAX_FLASH BIT(4)
270
271#define TOPSYS_IRQ_T120C_INT BIT(0)
272#define TOPSYS_IRQ_T140C_INT BIT(1)
273#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
274
275#define CHG_IRQ_BYP_I BIT(0)
276#define CHG_IRQ_THM_I BIT(2)
277#define CHG_IRQ_BAT_I BIT(3)
278#define CHG_IRQ_CHG_I BIT(4)
279#define CHG_IRQ_CHGIN_I BIT(6)
280
281#define MUIC_IRQ_INT1_ADC BIT(0)
282#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
283#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
284#define MUIC_IRQ_INT1_ADC1K BIT(3)
285
286#define MUIC_IRQ_INT2_CHGTYP BIT(0)
287#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
288#define MUIC_IRQ_INT2_DCDTMR BIT(2)
289#define MUIC_IRQ_INT2_DXOVP BIT(3)
290#define MUIC_IRQ_INT2_VBVOLT BIT(4)
291#define MUIC_IRQ_INT2_VIDRM BIT(5)
292
293#define MUIC_IRQ_INT3_EOC BIT(0)
294#define MUIC_IRQ_INT3_CGMBC BIT(1)
295#define MUIC_IRQ_INT3_OVP BIT(2)
296#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
297#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
298#define MUIC_IRQ_INT3_BAT_DET BIT(5)
299
265enum max77693_irq { 300enum max77693_irq {
266 /* PMIC - FLASH */ 301 /* PMIC - FLASH */
267 MAX77693_LED_IRQ_FLED2_OPEN, 302 MAX77693_LED_IRQ_FLED2_OPEN,
@@ -282,6 +317,10 @@ enum max77693_irq {
282 MAX77693_CHG_IRQ_CHG_I, 317 MAX77693_CHG_IRQ_CHG_I,
283 MAX77693_CHG_IRQ_CHGIN_I, 318 MAX77693_CHG_IRQ_CHGIN_I,
284 319
320 MAX77693_IRQ_NR,
321};
322
323enum max77693_irq_muic {
285 /* MUIC INT1 */ 324 /* MUIC INT1 */
286 MAX77693_MUIC_IRQ_INT1_ADC, 325 MAX77693_MUIC_IRQ_INT1_ADC,
287 MAX77693_MUIC_IRQ_INT1_ADC_LOW, 326 MAX77693_MUIC_IRQ_INT1_ADC_LOW,
@@ -304,7 +343,7 @@ enum max77693_irq {
304 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, 343 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
305 MAX77693_MUIC_IRQ_INT3_BAT_DET, 344 MAX77693_MUIC_IRQ_INT3_BAT_DET,
306 345
307 MAX77693_IRQ_NR, 346 MAX77693_MUIC_IRQ_NR,
308}; 347};
309 348
310struct max77693_dev { 349struct max77693_dev {
@@ -319,7 +358,10 @@ struct max77693_dev {
319 struct regmap *regmap_muic; 358 struct regmap *regmap_muic;
320 struct regmap *regmap_haptic; 359 struct regmap *regmap_haptic;
321 360
322 struct irq_domain *irq_domain; 361 struct regmap_irq_chip_data *irq_data_led;
362 struct regmap_irq_chip_data *irq_data_topsys;
363 struct regmap_irq_chip_data *irq_data_charger;
364 struct regmap_irq_chip_data *irq_data_muic;
323 365
324 int irq; 366 int irq;
325 int irq_gpio; 367 int irq_gpio;
@@ -332,14 +374,6 @@ enum max77693_types {
332 TYPE_MAX77693, 374 TYPE_MAX77693,
333}; 375};
334 376
335extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
336extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
337 u8 *buf);
338extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
339extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
340 u8 *buf);
341extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
342
343extern int max77693_irq_init(struct max77693_dev *max77686); 377extern int max77693_irq_init(struct max77693_dev *max77686);
344extern void max77693_irq_exit(struct max77693_dev *max77686); 378extern void max77693_irq_exit(struct max77693_dev *max77686);
345extern int max77693_irq_resume(struct max77693_dev *max77686); 379extern int max77693_irq_resume(struct max77693_dev *max77686);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 20:11:18 -0500