297 files changed, 20490 insertions, 3332 deletions

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index c554ed3d44fb..556c8665fdbf 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -92,3 +92,68 @@ Required nodes:
 - core-module: the root node to the Versatile platforms must have
   a core-module with regs and the compatible strings
   "arm,core-module-versatile", "syscon"
+
+ARM RealView Boards
+-------------------
+The RealView boards cover tailored evaluation boards that are used to explore
+the ARM11 and Cortex A-8 and Cortex A-9 processors.
+
+Required properties (in root node):
+        /* RealView Emulation Baseboard */
+        compatible = "arm,realview-eb";
+         /* RealView Platform Baseboard for ARM1176JZF-S */
+        compatible = "arm,realview-pb1176";
+        /* RealView Platform Baseboard for ARM11 MPCore */
+        compatible = "arm,realview-pb11mp";
+        /* RealView Platform Baseboard for Cortex A-8 */
+        compatible = "arm,realview-pba8";
+        /* RealView Platform Baseboard Explore for Cortex A-9 */
+        compatible = "arm,realview-pbx";
+
+Required nodes:
+
+- soc: some node of the RealView platforms must be the SoC
+  node that contain the SoC-specific devices, withe the compatible
+  string set to one of these tuples:
+   "arm,realview-eb-soc", "simple-bus"
+   "arm,realview-pb1176-soc", "simple-bus"
+   "arm,realview-pb11mp-soc", "simple-bus"
+   "arm,realview-pba8-soc", "simple-bus"
+   "arm,realview-pbx-soc", "simple-bus"
+
+- syscon: some subnode of the RealView SoC node must be a
+  system controller node pointing to the control registers,
+  with the compatible string set to one of these tuples:
+   "arm,realview-eb-syscon", "syscon"
+   "arm,realview-pb1176-syscon", "syscon"
+   "arm,realview-pb11mp-syscon", "syscon"
+   "arm,realview-pba8-syscon", "syscon"
+   "arm,realview-pbx-syscon", "syscon"
+
+  Required properties for the system controller:
+  - regs: the location and size of the system controller registers,
+    one range of 0x1000 bytes.
+
+Example:
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+        model = "ARM RealView PB1176 with device tree";
+        compatible = "arm,realview-pb1176";
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,realview-pb1176-soc", "simple-bus";
+                ranges;
+
+                syscon: syscon@10000000 {
+                        compatible = "arm,realview-syscon", "syscon";
+                        reg = <0x10000000 0x1000>;
+                };
+
+        };
+};
diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 000000000000..4c77169bb534
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index e935d7d4ac43..4e8b7df7fc62 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -74,3 +74,41 @@ Required root node properties:
 i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
+
+
+Freescale LS1021A Platform Device Tree Bindings
+------------------------------------------------
+
+Required root node compatible properties:
+  - compatible = "fsl,ls1021a";
+
+Freescale LS1021A SoC-specific Device Tree Bindings
+-------------------------------------------
+
+Freescale SCFG
+  SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-scfg"
+  - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+        scfg: scfg@1570000 {
+                compatible = "fsl,ls1021a-scfg";
+                reg = <0x0 0x1570000 0x0 0x10000>;
+        };
+
+Freescale DCFG
+  DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+  Required properties:
+  - compatible: should be "fsl,ls1021a-dcfg"
+  - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+        dcfg: dcfg@1ee0000 {
+                compatible = "fsl,ls1021a-dcfg";
+                reg = <0x0 0x1ee0000 0x0 0x10000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index c7d2fa156678..b38608af66db 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -17,6 +17,7 @@ Main node required properties:
         "arm,cortex-a7-gic"
         "arm,arm11mp-gic"
         "brcm,brahma-b15-gic"
+        "arm,arm1176jzf-devchip-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 904de5781f44..a99eb9eb14c0 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -106,11 +106,21 @@ Required subnode-properties:
 - groups: a list of strings describing the group names.
 - function: a string describing the function used to mux the groups.
 
+* Reset controller binding
+
+A reset controller is part of the chip control registers set. The chip control
+node also provides the reset. The register set is not at the same offset between
+Berlin SoCs.
+
+Required property:
+- #reset-cells: must be set to 2
+
 Example:
 
 chip: chip-control@ea0000 {
         compatible = "marvell,berlin2-chip-ctrl";
         #clock-cells = <1>;
+        #reset-cells = <2>;
         reg = <0xea0000 0x400>;
         clocks = <&refclk>, <&externaldev 0>;
         clock-names = "refclk", "video_ext0";
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index fa252261dfaf..3be40139cfbb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -1,10 +1,14 @@
-Mediatek MT6589 Platforms Device Tree Bindings
+MediaTek mt65xx & mt81xx Platforms Device Tree Bindings
 
-Boards with a SoC of the Mediatek MT6589 shall have the following property:
+Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
 
 Required root node property:
 
-compatible: must contain "mediatek,mt6589"
+compatible: Must contain one of
+   "mediatek,mt6589"
+   "mediatek,mt6592"
+   "mediatek,mt8127"
+   "mediatek,mt8135"
 
 
 Supported boards:
@@ -12,3 +16,12 @@ Supported boards:
 - bq Aquaris5 smart phone:
     Required root node properties:
       - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
+- Evaluation board for MT6592:
+    Required root node properties:
+      - compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+- MTK mt8127 tablet moose EVB:
+    Required root node properties:
+      - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+- MTK mt8135 tablet EVB:
+    Required root node properties:
+      - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index ddd9bcdf889c..4f6a82cef1d1 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -132,6 +132,9 @@ Boards:
 - AM335X Bone : Low cost community board
   compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
 
+- AM335X OrionLXm : Substation Automation Platform
+  compatible = "novatech,am335x-lxm", "ti,am33xx"
+
 - OMAP5 EVM : Evaluation Module
   compatible = "ti,omap5-evm", "ti,omap5"
 
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 857f12636eb2..eaa3d1a0eb05 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,6 +1,10 @@
 Rockchip platforms device tree bindings
 ---------------------------------------
 
+- MarsBoard RK3066 board:
+    Required root node properties:
+      - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
+
 - bq Curie 2 tablet:
     Required root node properties:
       - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
index 2168ed31e1b0..43589d2466a7 100644
--- a/Documentation/devicetree/bindings/arm/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -1,11 +1,20 @@
-* Samsung's Exynos4210 based SMDKV310 evaluation board
-
-SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC.
+* Samsung's Exynos SoC based boards
 
 Required root node properties:
     - compatible = should be one or more of the following.
-        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
-        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
+        - "samsung,monk"        - for Exynos3250-based Samsung Simband board.
+        - "samsung,rinato"      - for Exynos3250-based Samsung Gear2 board.
+        - "samsung,smdkv310"    - for Exynos4210-based Samsung SMDKV310 eval board.
+        - "samsung,trats"       - for Exynos4210-based Tizen Reference board.
+        - "samsung,universal_c210" - for Exynos4210-based Samsung board.
+        - "samsung,smdk4412",   - for Exynos4412-based Samsung SMDK4412 eval board.
+        - "samsung,trats2"      - for Exynos4412-based Tizen Reference board.
+        - "samsung,smdk5250"    - for Exynos5250-based Samsung SMDK5250 eval board.
+        - "samsung,xyref5260"   - for Exynos5260-based Samsung board.
+        - "samsung,smdk5410"    - for Exynos5410-based Samsung SMDK5410 eval board.
+        - "samsung,smdk5420"    - for Exynos5420-based Samsung SMDK5420 eval board.
+        - "samsung,sd5v1"       - for Exynos5440-based Samsung board.
+        - "samsung,ssdk5440"    - for Exynos5440-based Samsung board.
 
 Optional:
     - firmware node, specifying presence and type of secure firmware:
diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
index 6256ec31666d..2fdff5a806cf 100644
--- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt
+++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
@@ -10,6 +10,12 @@ Required root node property: src
 
 Boards with the Nomadik SoC include:
 
+Nomadik NHK-15 board manufactured by ST Microelectronics:
+
+Required root node property:
+
+compatible="st,nomadik-nhk-15";
+
 S8815 "MiniKit" manufactured by Calao Systems:
 
 Required root node property:
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 000000000000..00d26edec8bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                osc: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <1>;
+                        clock-frequency = <25000000>;
+                };
+
+                apb_clk: apb_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000000>;
+                };
+
+                periph_clk: periph_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <500000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
index c80863d344ac..63f9f1ac3439 100644
--- a/Documentation/devicetree/bindings/clock/vf610-clock.txt
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -5,6 +5,19 @@ Required properties:
 - reg: Address and length of the register set
 - #clock-cells: Should be <1>
 
+Optional properties:
+- clocks: list of clock identifiers which are external input clocks to the
+        given clock controller. Please refer the next section to find
+        the input clocks for a given controller.
+- clock-names: list of names of clocks which are exteral input clocks to the
+        given clock controller.
+
+Input clocks for top clock controller:
+        - sxosc (external crystal oscillator 32KHz, recommended)
+        - fxosc (external crystal oscillator 24MHz, recommended)
+        - audio_ext
+        - enet_ext
+
 The clock consumer should specify the desired clock by having the clock
 ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
 for the full list of VF610 clock IDs.
@@ -15,6 +28,8 @@ clks: ccm@4006b000 {
         compatible = "fsl,vf610-ccm";
         reg = <0x4006b000 0x1000>;
         #clock-cells = <1>;
+        clocks = <&sxosc>, <&fxosc>;
+        clock-names = "sxosc", "fxosc";
 };
 
 uart1: serial@40028000 {
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
index 1405ed071bb4..e4c4d47f8137 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt
@@ -25,7 +25,7 @@ Required child node properties:
 - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
         "xlnx,axi-vdma-s2mm-channel".
 - interrupts: Should contain per channel VDMA interrupts.
-- xlnx,data-width: Should contain the stream data width, take values
+- xlnx,datawidth: Should contain the stream data width, take values
         {32,64...1024}.
 
 Optional child node properties:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index 278de8e64bbf..89b3250f049b 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
@@ -32,6 +32,7 @@ Optional properties:
     specified, default value is 0.
   - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
     specified, the default value in Hz is 100000.
+  - samsung,sysreg-phandle - handle to syscon used to control the system registers
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index fbde415078e6..605dcca5dbec 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -56,6 +56,8 @@ gmt,g751		G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In
 infineon,slb9635tt      Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
 infineon,slb9645tt      Infineon SLB9645 I2C TPM (new protocol, max 400khz)
 isl,isl12057            Intersil ISL12057 I2C RTC Chip
+isil,isl29028           (deprecated, use isl)
+isl,isl29028            Intersil ISL29028 Ambient Light and Proximity Sensor
 maxim,ds1050            5 Bit Programmable, Pulse-Width Modulator
 maxim,max1237           Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
 maxim,max6625           9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
index d9a8d5af1a21..ba0a34d97eb8 100644
--- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
@@ -1,4 +1,4 @@
-* Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2)
+* Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
 
 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable
 clock inputs and programmable compare match.
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
index 7db89fb25444..cd5f20bf2582 100644
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
@@ -1,4 +1,4 @@
-* Renesas R-Car Timer Unit (TMU)
+* Renesas R-Mobile/R-Car Timer Unit (TMU)
 
 The TMU is a 32-bit timer/counter with configurable clock inputs and
 programmable compare match.
@@ -9,6 +9,8 @@ are independent. The TMU hardware supports up to three channels.
 Required Properties:
 
   - compatible: must contain one or more of the following:
+    - "renesas,tmu-r8a7740" for the r8a7740 TMU
+    - "renesas,tmu-r8a7778" for the r8a7778 TMU
     - "renesas,tmu-r8a7779" for the r8a7779 TMU
     - "renesas,tmu" for any TMU.
       This is a fallback for the above renesas,tmu-* entries
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ecaf2035c2fe..0d354625299c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -41,6 +41,7 @@ dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
 davicom DAVICOM Semiconductor, Inc.
 denx    Denx Software Engineering
 digi    Digi International Inc.
+digilent        Diglent, Inc.
 dlg     Dialog Semiconductor
 dlink   D-Link Corporation
 dmo     Data Modul AG
@@ -78,6 +79,7 @@ innolux	Innolux Corporation
 intel   Intel Corporation
 intercontrol    Inter Control Group
 isee    ISEE 2007 S.L.
+isil    Intersil (deprecated, use isl)
 isl     Intersil
 karo    Ka-Ro electronics GmbH
 keymile Keymile GmbH
@@ -150,6 +152,7 @@ st	STMicroelectronics
 ste     ST-Ericsson
 stericsson      ST-Ericsson
 synology        Synology, Inc.
+tbs     TBS Technologies
 thine   THine Electronics, Inc.
 ti      Texas Instruments
 tlm     Trusted Logic Mobility
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fe92f5df9d3c..6a3d9a6c4497 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,8 +54,17 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb
+dtb-$(CONFIG_ARCH_BCM_5301X) += \
+        bcm4708-buffalo-wzr-1750dhp.dtb \
+        bcm4708-netgear-r6250.dtb \
+        bcm4708-netgear-r6300-v2.dtb \
+        bcm47081-asus-rt-n18u.dtb \
+        bcm47081-buffalo-wzr-600dhp2.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \
+        bcm911360k.dtb \
+        bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
         bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -67,7 +76,9 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
         da850-evm.dtb
 dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
+        exynos3250-rinato.dtb \
+        exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
         exynos4210-universal_c210.dtb \
@@ -81,6 +92,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
+        exynos5250-spring.dtb \
         exynos5260-xyref5260.dtb \
         exynos5410-smdk5410.dtb \
         exynos5420-arndale-octa.dtb \
@@ -104,6 +116,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
         kirkwood-d2net.dtb \
         kirkwood-db-88f6281.dtb \
         kirkwood-db-88f6282.dtb \
+        kirkwood-dir665.dtb \
         kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
         kirkwood-dockstar.dtb \
@@ -240,6 +253,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6q-sabrelite.dtb \
         imx6q-sabresd.dtb \
         imx6q-sbc6x.dtb \
+        imx6q-tbs2910.dtb \
         imx6q-udoo.dtb \
         imx6q-wandboard.dtb \
         imx6q-wandboard-revb1.dtb \
@@ -250,6 +264,9 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6q-tx6q-1110.dtb \
         imx6sl-evk.dtb \
         imx6sx-sdb.dtb \
+        ls1021a-qds.dtb \
+        ls1021a-twr.dtb \
+        vf500-colibri-eval-v3.dtb \
         vf610-colibri-eval-v3.dtb \
         vf610-cosmic.dtb \
         vf610-twr.dtb
@@ -274,7 +291,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx28-m28evk.dtb \
         imx28-sps1.dtb \
         imx28-tx28.dtb
-dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \
+        ste-nomadik-nhk15.dtb
 dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
         nspire-tp.dtb \
         nspire-clp.dtb
@@ -302,7 +320,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
         omap3-ha.dtb \
         omap3-ha-lcd.dtb \
         omap3-igep0020.dtb \
+        omap3-igep0020-rev-f.dtb \
         omap3-igep0030.dtb \
+        omap3-igep0030-rev-g.dtb \
         omap3-ldp.dtb \
         omap3-lilly-dbb056.dtb \
         omap3-n900.dtb \
@@ -331,7 +351,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
         am335x-evm.dtb \
         am335x-evmsk.dtb \
         am335x-nano.dtb \
-        am335x-pepper.dtb
+        am335x-pepper.dtb \
+        am335x-lxm.dtb
 dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
         omap4-panda.dtb \
         omap4-panda-a4.dtb \
@@ -347,6 +368,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
         omap5-sbc-t54.dtb \
         omap5-uevm.dtb
 dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
+        am57xx-beagle-x15.dtb \
         dra72-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
         orion5x-lacie-ethernet-disk-mini-v2.dtb \
@@ -363,8 +385,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \
         qcom-msm8660-surf.dtb \
         qcom-msm8960-cdp.dtb \
         qcom-msm8974-sony-xperia-honami.dtb
+dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
         rk3066a-bqcurie2.dtb \
+        rk3066a-marsboard.dtb \
         rk3188-radxarock.dtb \
         rk3288-evb-act8846.dtb \
         rk3288-evb-rk808.dtb
@@ -396,6 +420,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
         r8a7791-koelsch.dtb \
         r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
+        socfpga_arria10_socdk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_sockit.dtb \
         socfpga_cyclone5_socrates.dtb \
@@ -408,6 +433,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
         spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
 dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
+        stih410-b2120.dtb \
         stih415-b2000.dtb \
         stih415-b2020.dtb \
         stih416-b2000.dtb \
@@ -434,15 +460,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \
         sun6i-a31-hummingbird.dtb \
         sun6i-a31-m9.dtb
 dtb-$(CONFIG_MACH_SUN7I) += \
+        sun7i-a20-bananapi.dtb \
         sun7i-a20-cubieboard2.dtb \
         sun7i-a20-cubietruck.dtb \
         sun7i-a20-hummingbird.dtb \
         sun7i-a20-i12-tvbox.dtb \
+        sun7i-a20-m3.dtb \
         sun7i-a20-olinuxino-lime.dtb \
+        sun7i-a20-olinuxino-lime2.dtb \
         sun7i-a20-olinuxino-micro.dtb \
         sun7i-a20-pcduino3.dtb
 dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-a23-ippo-q8h-v5.dtb
+dtb-$(CONFIG_MACH_SUN9I) += \
+        sun9i-a80-optimus.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-iris-512.dtb \
         tegra20-medcom-wide.dtb \
@@ -488,13 +519,15 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
         zynq-parallella.dtb \
         zynq-zc702.dtb \
         zynq-zc706.dtb \
-        zynq-zed.dtb
+        zynq-zed.dtb \
+        zynq-zybo.dtb
 dtb-$(CONFIG_MACH_ARMADA_370) += \
         armada-370-db.dtb \
         armada-370-mirabox.dtb \
         armada-370-netgear-rn102.dtb \
         armada-370-netgear-rn104.dtb \
-        armada-370-rd.dtb
+        armada-370-rd.dtb \
+        armada-370-synology-ds213j.dtb
 dtb-$(CONFIG_MACH_ARMADA_375) += \
         armada-375-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_38X) += \
@@ -507,14 +540,18 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
         armada-xp-lenovo-ix4-300d.dtb \
         armada-xp-matrix.dtb \
         armada-xp-netgear-rn2120.dtb \
-        armada-xp-openblocks-ax3-4.dtb
+        armada-xp-openblocks-ax3-4.dtb \
+        armada-xp-synology-ds414.dtb
 dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
         dove-cubox.dtb \
         dove-cubox-es.dtb \
         dove-d2plug.dtb \
         dove-d3plug.dtb \
         dove-dove-db.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \
+        mt6592-evb.dtb \
+        mt8127-moose.dtb \
+        mt8135-evbp1.dtb
 
 endif
 
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index c4b968f0feb5..54f118c08db8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -307,6 +307,13 @@
                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                 >;
         };
+
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+                        0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+                >;
+        };
 };
 
 &uart0 {
@@ -437,9 +444,9 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&nandflash_pins_s0>;
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 ti,nand-ecc-opt = "bch8";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
@@ -664,3 +671,9 @@
 &aes {
         status = "okay";
 };
+
+&dcan1 {
+        status = "disabled";    /* Enable only if Profile 1 is selected */
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a1a0cc5eb35c..c0e1135256cc 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -126,10 +126,10 @@
         pinctrl-names = "default";
         pinctrl-0 = <&nandflash_pins>;
 
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <8>;
                 ti,nand-ecc-opt = "bch8";
                 gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
new file mode 100644
index 000000000000..7266a00aab2e
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -0,0 +1,362 @@
+/*
+ * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+        model = "NovaTech OrionLXm";
+        compatible = "novatech,am335x-lxm", "ti,am33xx";
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd1_reg>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+
+        /* Power supply provides a fixed 5V @2A */
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+
+        /* Power supply provides a fixed 3.3V @3A */
+        vmmcsd_fixed: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+};
+
+&am33xx_pinmux {
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat3 */
+                        0xf4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat2 */
+                        0xf8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat1 */
+                        0xfc (PIN_INPUT_PULLUP | MUX_MODE0)     /* mmc0_dat0 */
+                        0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk */
+                        0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd */
+                >;
+        };
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT | MUX_MODE0)   /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT | MUX_MODE0)   /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii1_int */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_crs_dv */
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rxer */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rd1 */
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii1_rd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk */
+
+                        /* Slave 2 */
+                        0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_txen */
+                        0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td1 */
+                        0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)  /* rmii2_td0 */
+                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd1 */
+                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rd0 */
+                        0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_crs_dv */
+                        0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* rmii2_rxer */
+                        0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_int */
+                        0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* rmii2_refclk */
+                >;
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii1_int */
+                        0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_crs_dv */
+                        0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rxer */
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_txen */
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td1 */
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_td0 */
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd1 */
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_rd0 */
+                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii1_refclk */
+
+                        /* Slave 2 reset value*/
+                        0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_txen */
+                        0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td1 */
+                        0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_td0 */
+                        0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd1 */
+                        0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rd0 */
+                        0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_crs_dv */
+                        0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_rxer */
+                        0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* rmii2_int */
+                        0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* rmii2_refclk */
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+
+        emmc_pins: pinmux_emmc_pins {
+                pinctrl-single,pins = <
+                        0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                        0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                        0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                        0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                        0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                        0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                        0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+                        0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+                        0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+                        0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                        0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                >;
+        };
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        serial_config1: serial_config1@20 {
+                compatible = "nxp,pca9539";
+                reg = <0x20>;
+        };
+
+        serial_config2: serial_config2@21 {
+                compatible = "nxp,pca9539";
+                reg = <0x21>;
+        };
+
+        tps: tps@2d {
+                compatible = "ti,tps65910";
+                reg = <0x2d>;
+        };
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+
+        regulators {
+                /* vrtc - unused */
+
+                vio_reg: regulator@1 {
+                        regulator-name = "vio_1v5,ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd1_reg: regulator@2 {
+                        regulator-name = "vdd1,mpu";
+                        regulator-min-microvolt = <600000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd2_reg: regulator@3 {
+                        regulator-name = "vdd2_1v1,core";
+                        regulator-min-microvolt = <1100000>;
+                        regulator-max-microvolt = <1100000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                /* vdd3 - unused */
+
+                /* vdig1 - unused */
+
+                vdig2_reg: regulator@6 {
+                        regulator-name = "vdig2_1v8,vdds_pll";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                /* vpll - unused */
+
+                vdac_reg: regulator@8 {
+                        regulator-name = "vdac_1v8,vdds";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vaux1_reg: regulator@9 {
+                        regulator-name = "vaux1_1v8,usb";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vaux2_reg: regulator@10 {
+                        regulator-name = "vaux2_3v3,io";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vaux33_reg: regulator@11 {
+                        regulator-name = "vaux33_3v3,usb";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vmmc_reg: regulator@12 {
+                        regulator-name = "vmmc_3v3,io";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
+};
+
+&sham {
+        status = "okay";
+};
+
+&aes {
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+
+        status = "okay";
+};
+
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb0_phy {
+        status = "okay";
+};
+
+&usb1_phy {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&usb1 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <5>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <2>;
+};
+
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <4>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <3>;
+};
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac = <1>;
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+        status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 831810583823..befe713b3e1b 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,6 +83,11 @@
                 };
         };
 
+        am33xx_control_module: control_module@4a002000 {
+                compatible = "syscon";
+                reg = <0x44e10000 0x7fc>;
+        };
+
         am33xx_pinmux: pinmux@44e10800 {
                 compatible = "pinctrl-single";
                 reg = <0x44e10800 0x0238>;
@@ -204,6 +209,8 @@
                         reg = <0x44e09000 0x2000>;
                         interrupts = <72>;
                         status = "disabled";
+                        dmas = <&edma 26>, <&edma 27>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart1: serial@48022000 {
@@ -213,6 +220,8 @@
                         reg = <0x48022000 0x2000>;
                         interrupts = <73>;
                         status = "disabled";
+                        dmas = <&edma 28>, <&edma 29>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart2: serial@48024000 {
@@ -222,6 +231,8 @@
                         reg = <0x48024000 0x2000>;
                         interrupts = <74>;
                         status = "disabled";
+                        dmas = <&edma 30>, <&edma 31>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart3: serial@481a6000 {
@@ -333,20 +344,24 @@
                         interrupts = <91>;
                 };
 
-                dcan0: d_can@481cc000 {
-                        compatible = "bosch,d_can";
+                dcan0: can@481cc000 {
+                        compatible = "ti,am3352-d_can";
                         ti,hwmods = "d_can0";
-                        reg = <0x481cc000 0x2000
-                                0x44e10644 0x4>;
+                        reg = <0x481cc000 0x2000>;
+                        clocks = <&dcan0_fck>;
+                        clock-names = "fck";
+                        syscon-raminit = <&am33xx_control_module 0x644 0>;
                         interrupts = <52>;
                         status = "disabled";
                 };
 
-                dcan1: d_can@481d0000 {
-                        compatible = "bosch,d_can";
+                dcan1: can@481d0000 {
+                        compatible = "ti,am3352-d_can";
                         ti,hwmods = "d_can1";
-                        reg = <0x481d0000 0x2000
-                                0x44e10644 0x4>;
+                        reg = <0x481d0000 0x2000>;
+                        clocks = <&dcan1_fck>;
+                        clock-names = "fck";
+                        syscon-raminit = <&am33xx_control_module 0x644 1>;
                         interrupts = <55>;
                         status = "disabled";
                 };
@@ -356,6 +371,7 @@
                         reg = <0x480C8000 0x200>;
                         interrupts = <77>;
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <8>;
                         mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 46660ffd2b65..d42d7865dd53 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,6 +57,11 @@
                 cache-level = <2>;
         };
 
+        am43xx_control_module: control_module@4a002000 {
+                compatible = "syscon";
+                reg = <0x44e10000 0x7f4>;
+        };
+
         am43xx_pinmux: pinmux@44e10800 {
                 compatible = "ti,am437-padconf", "pinctrl-single";
                 reg = <0x44e10800 0x31c>;
@@ -168,6 +173,7 @@
                         reg = <0x480C8000 0x200>;
                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <8>;
                         mbox_wkupm3: wkup_m3 {
@@ -667,6 +673,26 @@
                         };
                 };
 
+                tscadc: tscadc@44e0d000 {
+                        compatible = "ti,am3359-tscadc";
+                        reg = <0x44e0d000 0x1000>;
+                        ti,hwmods = "adc_tsc";
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&adc_tsc_fck>;
+                        clock-names = "fck";
+                        status = "disabled";
+
+                        tsc {
+                                compatible = "ti,am3359-tsc";
+                        };
+
+                        adc {
+                                #io-channel-cells = <1>;
+                                compatible = "ti,am3359-adc";
+                        };
+
+                };
+
                 sham: sham@53100000 {
                         compatible = "ti,omap5-sham";
                         ti,hwmods = "sham";
@@ -896,6 +922,28 @@
                         compatible = "mmio-sram";
                         reg = <0x40300000 0x40000>; /* 256k */
                 };
+
+                dcan0: can@481cc000 {
+                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                        ti,hwmods = "d_can0";
+                        clocks = <&dcan0_fck>;
+                        clock-names = "fck";
+                        reg = <0x481cc000 0x2000>;
+                        syscon-raminit = <&am43xx_control_module 0x644 0>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                dcan1: can@481d0000 {
+                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                        ti,hwmods = "d_can1";
+                        clocks = <&dcan1_fck>;
+                        clock-names = "fck";
+                        reg = <0x481d0000 0x2000>;
+                        syscon-raminit = <&am43xx_control_module 0x644 1>;
+                        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a521ac0a7d5a..7eaae4cf9f89 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -254,6 +254,20 @@
                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
                 >;
         };
+
+        dcan0_default: dcan0_default_pins {
+                pinctrl-single,pins = <
+                        0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
+                        0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
+                >;
+        };
+
+        dcan1_default: dcan1_default_pins {
+                pinctrl-single,pins = <
+                        0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
+                        0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
+                >;
+        };
 };
 
 &i2c0 {
@@ -343,6 +357,14 @@
         status = "okay";
 };
 
+&tscadc {
+        status = "okay";
+
+        adc {
+                ti,adc-channels = <0 1 2 3 4 5 6 7>;
+        };
+};
+
 &ecap0 {
         status = "okay";
         pinctrl-names = "default";
@@ -511,3 +533,15 @@
                 };
         };
 };
+
+&dcan0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan0_default>;
+        status = "okay";
+};
+
+&dcan1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan1_default>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index f7e9bba10bd6..662261d6b2ca 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -438,9 +438,9 @@
         status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
         pinctrl-names = "default";
         pinctrl-0 = <&nand_flash_x8>;
-        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 ti,nand-ecc-opt = "bch16";
                 ti,elm-id = <&elm>;
                 nand-bus-width = <8>;
@@ -519,6 +519,14 @@
         status = "okay";
 };
 
+&tscadc {
+        status = "okay";
+
+        adc {
+                ti,adc-channels = <0 1 2 3 4 5 6 7>;
+        };
+};
+
 &ecap0 {
                 status = "okay";
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
new file mode 100644
index 000000000000..49edbda68cd5
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -0,0 +1,405 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        model = "TI AM5728 BeagleBoard-X15";
+        compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+        aliases {
+                rtc0 = &mcp_rtc;
+                rtc1 = &tps659038_rtc;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
+
+        vdd_3v3: fixedregulator-vdd_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd_3v3";
+                vin-supply = <&regen1>;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        vtt_fixed: fixedregulator-vtt {
+                /* TPS51200 */
+                compatible = "regulator-fixed";
+                regulator-name = "vtt_fixed";
+                vin-supply = <&smps3_reg>;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&leds_pins_default>;
+
+                led@0 {
+                        label = "beagle-x15:usr0";
+                        gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+
+                led@1 {
+                        label = "beagle-x15:usr1";
+                        gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu0";
+                        default-state = "off";
+                };
+
+                led@2 {
+                        label = "beagle-x15:usr2";
+                        gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+
+                led@3 {
+                        label = "beagle-x15:usr3";
+                        gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "ide-disk";
+                        default-state = "off";
+                };
+        };
+};
+
+&dra7_pmx_core {
+        leds_pins_default: leds_pins_default {
+                pinctrl-single,pins = <
+                        0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
+                        0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
+                        0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
+                        0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
+                >;
+        };
+
+        i2c1_pins_default: i2c1_pins_default {
+                pinctrl-single,pins = <
+                        0x400 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda.sda */
+                        0x404 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl.scl */
+                >;
+        };
+
+        i2c3_pins_default: i2c3_pins_default {
+                pinctrl-single,pins = <
+                        0x2a4 (PIN_INPUT| MUX_MODE10)   /* mcasp1_aclkx.i2c3_sda */
+                        0x2a8 (PIN_INPUT| MUX_MODE10)   /* mcasp1_fsx.i2c3_scl */
+                >;
+        };
+
+        uart3_pins_default: uart3_pins_default {
+                pinctrl-single,pins = <
+                        0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
+                        0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
+                >;
+        };
+
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
+                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc2_pins_default: mmc2_pins_default {
+                pinctrl-single,pins = <
+                        0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+
+        tps659038_pins_default: tps659038_pins_default {
+                pinctrl-single,pins = <
+                        0x418 (PIN_INPUT_PULLUP | MUX_MODE14)   /* wakeup0.gpio1_0 */
+                >;
+        };
+
+        tmp102_pins_default: tmp102_pins_default {
+                pinctrl-single,pins = <
+                        0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14)   /* spi2_d0.gpio7_16 */
+                >;
+        };
+
+        mcp79410_pins_default: mcp79410_pins_default {
+                pinctrl-single,pins = <
+                        0x424 (PIN_INPUT_PULLUP | MUX_MODE1)    /* wakeup3.sys_nirq1 */
+                >;
+        };
+
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+
+};
+
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins_default>;
+        clock-frequency = <400000>;
+
+        tps659038: tps659038@58 {
+                compatible = "ti,tps659038";
+                reg = <0x58>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&tps659038_pins_default>;
+
+                #interrupt-cells = <2>;
+                interrupt-controller;
+
+                ti,system-power-controller;
+
+                tps659038_pmic {
+                        compatible = "ti,tps659038-pmic";
+
+                        regulators {
+                                smps12_reg: smps12 {
+                                        /* VDD_MPU */
+                                        regulator-name = "smps12";
+                                        regulator-min-microvolt = < 850000>;
+                                        regulator-max-microvolt = <1250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps3_reg: smps3 {
+                                        /* VDD_DDR */
+                                        regulator-name = "smps3";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps45_reg: smps45 {
+                                        /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 850000>;
+                                        regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps6_reg: smps6 {
+                                        /* VDD_CORE */
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1030000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                /* SMPS7 unused */
+
+                                smps8_reg: smps8 {
+                                        /* VDD_1V8 */
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                /* SMPS9 unused */
+
+                                ldo1_reg: ldo1 {
+                                        /* VDD_SD  */
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+
+                                ldo2_reg: ldo2 {
+                                        /* VDD_SHV5 */
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo3_reg: ldo3 {
+                                        /* VDDA_1V8_PHY */
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo9_reg: ldo9 {
+                                        /* VDD_RTC */
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldoln_reg: ldoln {
+                                        /* VDDA_1V8_PLL */
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldousb_reg: ldousb {
+                                        /* VDDA_3V_USB: VDDA_USBHS33 */
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                };
+
+                                regen1: regen1 {
+                                        /* VDD_3V3_ON */
+                                        regulator-name = "regen1";
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
+                tps659038_rtc: tps659038_rtc {
+                        compatible = "ti,palmas-rtc";
+                        interrupt-parent = <&tps659038>;
+                        interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                };
+
+                tps659038_pwr_button: tps659038_pwr_button {
+                        compatible = "ti,palmas-pwrbutton";
+                        interrupt-parent = <&tps659038>;
+                        interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                        wakeup-source;
+                        ti,palmas-long-press-seconds = <12>;
+                };
+        };
+
+        tmp102: tmp102@48 {
+                compatible = "ti,tmp102";
+                reg = <0x48>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tmp102_pins_default>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+&i2c3 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins_default>;
+        clock-frequency = <400000>;
+
+        mcp_rtc: rtc@6f {
+                compatible = "microchip,mcp7941x";
+                reg = <0x6f>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>;  /* IRQ_SYS_1N */
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&mcp79410_pins_default>;
+
+                vcc-supply = <&vdd_3v3>;
+                wakeup-source;
+        };
+};
+
+&gpio7 {
+        ti,no-reset-on-init;
+        ti,no-idle-on-init;
+};
+
+&cpu0 {
+        cpu0-supply = <&smps12_reg>;
+        voltage-tolerance = <1>;
+};
+
+&uart3 {
+        status = "okay";
+        interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                              <&dra7_pmx_core 0x248>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins_default>;
+};
+
+&mmc1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_default>;
+
+        vmmc-supply = <&ldo1_reg>;
+        vmmc_aux-supply = <&vdd_3v3>;
+        pbias-supply = <&pbias_mmc_reg>;
+        bus-width = <4>;
+        cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+};
+
+&mmc2 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_default>;
+
+        vmmc-supply = <&vdd_3v3>;
+        bus-width = <8>;
+        ti,non-removable;
+        cap-mmc-dual-data-rate;
+};
+
+&sata {
+        status = "okay";
+};
+
+&usb2_phy1 {
+        phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+        dr_mode = "host";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
new file mode 100644
index 000000000000..ff26c7ed8c41
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -0,0 +1,412 @@
+/*
+ * Copyright 2014 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+        model = "ARM RealView PB1176";
+        compatible = "arm,realview-pb1176";
+
+        chosen { };
+
+        aliases {
+                serial0 = &pb1176_serial0;
+                serial1 = &pb1176_serial1;
+                serial2 = &pb1176_serial2;
+                serial3 = &pb1176_serial3;
+                serial4 = &fpga_serial;
+        };
+
+        memory {
+                /* 128 MiB memory @ 0x0 */
+                reg = <0x00000000 0x08000000>;
+        };
+
+        /* The voltage to the MMC card is hardwired at 3.3V */
+        vmmc: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        timclk: timclk@1M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <24>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+
+        mclk: mclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+
+        kmiclk: kmiclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+
+        sspclk: sspclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+
+        uartclk: uartclk@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+
+        /* FIXME: this actually hangs off the PLL clocks */
+        pclk: pclk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,realview-pb1176-soc", "simple-bus";
+                regmap = <&syscon>;
+                ranges;
+
+                syscon: syscon@10000000 {
+                        compatible = "arm,realview-pb1176-syscon", "syscon";
+                        reg = <0x10000000 0x1000>;
+
+                        led@08.0 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x01>;
+                                label = "versatile:0";
+                                linux,default-trigger = "heartbeat";
+                                default-state = "on";
+                        };
+                        led@08.1 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x02>;
+                                label = "versatile:1";
+                                linux,default-trigger = "mmc0";
+                                default-state = "off";
+                        };
+                        led@08.2 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x04>;
+                                label = "versatile:2";
+                                linux,default-trigger = "cpu0";
+                                default-state = "off";
+                        };
+                        led@08.3 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x08>;
+                                label = "versatile:3";
+                                default-state = "off";
+                        };
+                        led@08.4 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x10>;
+                                label = "versatile:4";
+                                default-state = "off";
+                        };
+                        led@08.5 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x20>;
+                                label = "versatile:5";
+                                default-state = "off";
+                        };
+                        led@08.6 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x40>;
+                                label = "versatile:6";
+                                default-state = "off";
+                        };
+                        led@08.7 {
+                                compatible = "register-bit-led";
+                                offset = <0x08>;
+                                mask = <0x80>;
+                                label = "versatile:7";
+                                default-state = "off";
+                        };
+                };
+
+                /* Primary DevChip GIC synthesized with the CPU */
+                intc_dc1176: interrupt-controller@10120000 {
+                        compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        reg = <0x10121000 0x1000>,
+                              <0x10120000 0x100>;
+                };
+
+                L2: l2-cache {
+                        compatible = "arm,l220-cache";
+                        reg = <0x10110000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+                        cache-unified;
+                        cache-level = <2>;
+                        /*
+                         * Override default cache size, sets and
+                         * associativity as these may be erroneously set
+                         * up by boot loader(s).
+                         */
+                        arm,override-auxreg;
+                        cache-size = <131072>; // 128kB
+                        cache-sets = <512>;
+                        cache-line-size = <32>;
+                };
+
+                pmu {
+                        compatible = "arm,arm1176-pmu";
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                timer01: timer@10104000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x10104000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer1", "timer2", "apb_pclk";
+                };
+
+                timer23: timer@10105000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        reg = <0x10105000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+                        arm,sp804-has-irq = <1>;
+                        clocks = <&timclk>, <&timclk>, <&pclk>;
+                        clock-names = "timer1", "timer2", "apb_pclk";
+                };
+
+                pb1176_rtc: rtc@10108000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0x10108000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                pb1176_gpio0: gpio@1010a000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x1010a000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                pb1176_ssp: ssp@1010b000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x1010b000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sspclk>, <&pclk>;
+                        clock-names = "SSPCLK", "apb_pclk";
+                };
+
+                pb1176_serial0: serial@1010c000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010c000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+
+                pb1176_serial1: serial@1010d000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010d000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+
+                pb1176_serial2: serial@1010e000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010e000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+
+                pb1176_serial3: serial@1010f000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x1010f000 0x1000>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+        };
+
+        /* These peripherals are inside the FPGA rather than the DevChip */
+        fpga {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+
+                fpga_mci: mmcsd@10005000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0x10005000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0 2 IRQ_TYPE_LEVEL_HIGH>;
+                        /* Due to frequent FIFO overruns, use just 500 kHz */
+                        max-frequency = <500000>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        clocks = <&mclk>, <&pclk>;
+                        clock-names = "mclk", "apb_pclk";
+                        vmmc-supply = <&vmmc>;
+                        cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
+                };
+
+                fpga_kmi0: kmi@10006000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        reg = <0x10006000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
+                };
+
+                fpga_kmi1: kmi@10007000 {
+                        compatible = "arm,pl050", "arm,primecell";
+                        reg = <0x10007000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
+                };
+
+                fpga_charlcd: charlcd@10008000 {
+                        compatible = "arm,versatile-lcd";
+                        reg = <0x10008000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                fpga_serial: serial@10009000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x10009000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
+                };
+
+                /* This GIC on the board is cascaded off the DevChip GIC */
+                intc_fpga1176: interrupt-controller@10040000 {
+                        compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        interrupt-controller;
+                        reg = <0x10041000 0x1000>,
+                              <0x10040000 0x100>;
+                        interrupt-parent = <&intc_dc1176>;
+                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                fpga_gpio0: gpio@10014000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x10014000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                fpga_gpio1: gpio@10015000 {
+                        compatible = "arm,pl061", "arm,primecell";
+                        reg = <0x10015000 0x1000>;
+                        gpio-controller;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                fpga_rtc: rtc@10017000 {
+                        compatible = "arm,pl031", "arm,primecell";
+                        reg = <0x10017000 0x1000>;
+                        interrupt-parent = <&intc_fpga1176>;
+                        interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index a495e5821ab8..1466580be295 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -75,6 +75,7 @@
                                 clock-frequency = <100000>;
                                 status = "okay";
                                 audio_codec: audio-codec@4a {
+                                        #sound-dai-cells = <0>;
                                         compatible = "cirrus,cs42l51";
                                         reg = <0x4a>;
                                 };
@@ -102,30 +103,6 @@
                                 broken-cd;
                         };
 
-                        pinctrl {
-                                /*
-                                 * These pins might be muxed as I2S by
-                                 * the bootloader, but it conflicts
-                                 * with the real I2S pins that are
-                                 * muxed using i2s_pins. We must mux
-                                 * those pins to a function other than
-                                 * I2S.
-                                 */
-                                pinctrl-0 = <&hog_pins1 &hog_pins2>;
-                                pinctrl-names = "default";
-
-                                hog_pins1: hog-pins1 {
-                                        marvell,pins = "mpp6",  "mpp8", "mpp10",
-                                                       "mpp12", "mpp13";
-                                        marvell,function = "gpio";
-                                };
-
-                                hog_pins2: hog-pins2 {
-                                        marvell,pins = "mpp5", "mpp7", "mpp9";
-                                        marvell,function = "gpo";
-                                };
-                        };
-
                         usb@50000 {
                                 status = "okay";
                         };
@@ -135,6 +112,8 @@
                         };
 
                         spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins2>;
+                                pinctrl-names = "default";
                                 status = "okay";
 
                                 spi-flash@0 {
@@ -167,17 +146,84 @@
         };
 
         sound {
-              compatible = "marvell,a370db-audio";
-              marvell,audio-controller = <&audio_controller>;
-              marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
-              status = "okay";
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "Armada 370 DB Audio";
+                simple-audio-card,mclk-fs = <256>;
+                simple-audio-card,widgets =
+                        "Headphone", "Out Jack",
+                        "Line", "In Jack";
+                simple-audio-card,routing =
+                        "Out Jack", "HPL",
+                        "Out Jack", "HPR",
+                        "AIN1L", "In Jack",
+                        "AIN1L", "In Jack";
+                status = "okay";
+
+                simple-audio-card,dai-link@0 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 0>;
+                        };
+
+                        codec {
+                                sound-dai = <&audio_codec>;
+                        };
+                };
+
+                simple-audio-card,dai-link@1 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 1>;
+                        };
+
+                        codec {
+                                sound-dai = <&spdif_out>;
+                        };
+                };
+
+                simple-audio-card,dai-link@2 {
+                        format = "i2s";
+                        cpu {
+                                sound-dai = <&audio_controller 1>;
+                        };
+
+                        codec {
+                                sound-dai = <&spdif_in>;
+                        };
+                };
         };
 
         spdif_out: spdif-out {
-              compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dit";
         };
 
         spdif_in: spdif-in {
-              compatible = "linux,spdif-dir";
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dir";
+        };
+};
+
+&pinctrl {
+        /*
+         * These pins might be muxed as I2S by
+         * the bootloader, but it conflicts
+         * with the real I2S pins that are
+         * muxed using i2s_pins. We must mux
+         * those pins to a function other than
+         * I2S.
+         */
+        pinctrl-0 = <&hog_pins1 &hog_pins2>;
+        pinctrl-names = "default";
+
+        hog_pins1: hog-pins1 {
+                marvell,pins = "mpp6",  "mpp8", "mpp10",
+                               "mpp12", "mpp13";
+                marvell,function = "gpio";
+        };
+
+        hog_pins2: hog-pins2 {
+                marvell,pins = "mpp5", "mpp7", "mpp9";
+                marvell,function = "gpo";
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2b6d24e0d1e8..e1b0eb6b091f 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,18 +54,6 @@
                                 status = "okay";
                         };
 
-                        pinctrl {
-                                pwr_led_pin: pwr-led-pin {
-                                        marvell,pins = "mpp63";
-                                        marvell,function = "gpo";
-                                };
-
-                                stat_led_pins: stat-led-pins {
-                                        marvell,pins = "mpp64", "mpp65";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         gpio_leds {
                                 compatible = "gpio-leds";
                                 pinctrl-names = "default";
@@ -169,3 +157,16 @@
                 };
         };
 };
+
+&pinctrl {
+        pwr_led_pin: pwr-led-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+
+        stat_led_pins: stat-led-pins {
+                marvell,pins = "mpp64", "mpp65";
+                marvell,function = "gpio";
+        };
+};
+
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3aebd93cc33c..4e24932c6e30 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -35,7 +35,7 @@
                 pcie-controller {
                         status = "okay";
 
-                        /* Connected to Marvell SATA controller */
+                        /* Connected to Marvell 88SE9170 SATA controller */
                         pcie@1,0 {
                                 /* Port 0, Lane 0 */
                                 status = "okay";
@@ -53,53 +53,12 @@
                                 status = "okay";
                         };
 
+                        /* eSATA interface */
                         sata@a0000 {
-                                nr-ports = <2>;
+                                nr-ports = <1>;
                                 status = "okay";
                         };
 
-                        pinctrl {
-                                power_led_pin: power-led-pin {
-                                        marvell,pins = "mpp57";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata1_led_pin: sata1-led-pin {
-                                        marvell,pins = "mpp15";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata2_led_pin: sata2-led-pin {
-                                        marvell,pins = "mpp14";
-                                        marvell,function = "gpio";
-                                };
-
-                                backup_led_pin: backup-led-pin {
-                                        marvell,pins = "mpp56";
-                                        marvell,function = "gpio";
-                                };
-
-                                backup_button_pin: backup-button-pin {
-                                        marvell,pins = "mpp58";
-                                        marvell,function = "gpio";
-                                };
-
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp62";
-                                        marvell,function = "gpio";
-                                };
-
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp6";
-                                        marvell,function = "gpio";
-                                };
-
-                                poweroff: poweroff {
-                                        marvell,pins = "mpp8";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         mdio {
                                 pinctrl-0 = <&mdio_pins>;
                                 pinctrl-names = "default";
@@ -204,20 +163,20 @@
                         default-state = "keep";
                 };
 
-                green-sata1-led {
-                        label = "rn102:green:sata1";
+                blue-sata1-led {
+                        label = "rn102:blue:sata1";
                         gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green-sata2-led {
-                        label = "rn102:green:sata2";
+                blue-sata2-led {
+                        label = "rn102:blue:sata2";
                         gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
 
-                green-backup-led {
-                        label = "rn102:green:backup";
+                blue-backup-led {
+                        label = "rn102:blue:backup";
                         gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                         default-state = "on";
                 };
@@ -256,3 +215,45 @@
                 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
         };
 };
+
+&pinctrl {
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp57";
+                marvell,function = "gpio";
+        };
+
+        sata1_led_pin: sata1-led-pin {
+                marvell,pins = "mpp15";
+                marvell,function = "gpio";
+        };
+
+        sata2_led_pin: sata2-led-pin {
+                marvell,pins = "mpp14";
+                marvell,function = "gpio";
+        };
+
+        backup_led_pin: backup-led-pin {
+                marvell,pins = "mpp56";
+                marvell,function = "gpio";
+        };
+
+        backup_button_pin: backup-button-pin {
+                marvell,pins = "mpp58";
+                marvell,function = "gpio";
+        };
+
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp6";
+                marvell,function = "gpio";
+        };
+
+        poweroff: poweroff {
+                marvell,pins = "mpp8";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c2f414bb9aba..30586e47986a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -53,38 +53,6 @@
                                 status = "okay";
                         };
 
-                        pinctrl {
-                                poweroff: poweroff {
-                                        marvell,pins = "mpp60";
-                                        marvell,function = "gpio";
-                                };
-
-                                backup_button_pin: backup-button-pin {
-                                        marvell,pins = "mpp52";
-                                        marvell,function = "gpio";
-                                };
-
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp62";
-                                        marvell,function = "gpio";
-                                };
-
-                                backup_led_pin: backup-led-pin {
-                                        marvell,pins = "mpp63";
-                                        marvell,function = "gpo";
-                                };
-
-                                power_led_pin: power-led-pin {
-                                        marvell,pins = "mpp64";
-                                        marvell,function = "gpio";
-                                };
-
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp65";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         mdio {
                                 pinctrl-0 = <&mdio_pins>;
                                 pinctrl-names = "default";
@@ -269,3 +237,35 @@
                 gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
         };
 };
+
+&pinctrl {
+        poweroff: poweroff {
+                marvell,pins = "mpp60";
+                marvell,function = "gpio";
+        };
+
+        backup_button_pin: backup-button-pin {
+                marvell,pins = "mpp52";
+                marvell,function = "gpio";
+        };
+
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+
+        backup_led_pin: backup-led-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+
+        power_led_pin: power-led-pin {
+                marvell,pins = "mpp64";
+                marvell,function = "gpio";
+        };
+
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp65";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index f57a8f841498..394308951ed9 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -59,18 +59,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                fan_pins: fan-pins {
-                                        marvell,pins = "mpp8";
-                                        marvell,function = "gpio";
-                                };
-
-                                led_pins: led-pins {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         serial@12000 {
                                 status = "okay";
                         };
@@ -85,10 +73,6 @@
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
-
-                                phy1: ethernet-phy@1 {
-                                        reg = <1>;
-                                };
                         };
 
                         ethernet@70000 {
@@ -100,8 +84,11 @@
                                 pinctrl-0 = <&ge1_rgmii_pins>;
                                 pinctrl-names = "default";
                                 status = "okay";
-                                phy = <&phy1>;
                                 phy-mode = "rgmii-id";
+                                fixed-link {
+                                           speed = <1000>;
+                                           full-duplex;
+                                };
                         };
 
                         mvsdio@d4000 {
@@ -173,4 +160,56 @@
                         };
                 };
         };
+
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                dsa,ethernet = <&eth1>;
+                dsa,mii-bus = <&mdio>;
+
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
+
+                        port@0 {
+                                reg = <0>;
+                                label = "lan0";
+                        };
+
+                        port@1 {
+                               reg = <1>;
+                               label = "lan1";
+                        };
+
+                        port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                        };
+
+                        port@3 {
+                               reg = <3>;
+                               label = "lan3";
+                        };
+
+                        port@5 {
+                              reg = <5>;
+                              label = "cpu";
+                        };
+                };
+         };
  };
+
+&pinctrl {
+        fan_pins: fan-pins {
+                marvell,pins = "mpp8";
+                marvell,function = "gpio";
+        };
+
+        led_pins: led-pins {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
new file mode 100644
index 000000000000..70fecde76ccb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -0,0 +1,316 @@
+/*
+ * Device Tree file for Synology DS213j
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-370.dtsi"
+
+/ {
+        model = "Synology DS213j";
+        compatible = "synology,ds213j", "marvell,armada370",
+                     "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = &uart0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+                internal-regs {
+
+                        /* RTC provided by Seiko S-35390A I2C RTC chip below */
+                        rtc@10300 {
+                                status = "disabled";
+                        };
+
+                        spi0: spi@10600 {
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "micron,n25q064";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <20000000>;
+
+                                        /*
+                                         * Warning!
+                                         *
+                                         * Synology u-boot uses its compiled-in environment
+                                         * and it seems Synology did not care to change u-boot
+                                         * default configuration in order to allow saving a
+                                         * modified environment at a sensible location. So,
+                                         * if you do a 'saveenv' under u-boot, your modified
+                                         * environment will be saved at 1MB after the start
+                                         * of the flash, i.e. in the middle of the uImage.
+                                         * For that reason, it is strongly advised not to
+                                         * change the default environment, unless you know
+                                         * what you are doing.
+                                         */
+                                        partition@00000000 { /* u-boot */
+                                                label = "RedBoot";
+                                                reg = <0x00000000 0x000c0000>; /* 768KB */
+                                        };
+
+                                        partition@000c0000 { /* uImage */
+                                                label = "zImage";
+                                                reg = <0x000c0000 0x002d0000>; /* 2880KB */
+                                        };
+
+                                        partition@00390000 { /* uInitramfs */
+                                                label = "rd.gz";
+                                                reg = <0x00390000 0x00440000>; /* 4250KB */
+                                        };
+
+                                        partition@007d0000 { /* MAC address and serial number */
+                                                label = "vendor";
+                                                reg = <0x007d0000 0x00010000>; /* 64KB */
+                                        };
+
+                                        partition@007e0000 {
+                                                label = "RedBoot config";
+                                                reg = <0x007e0000 0x00010000>; /* 64KB */
+                                        };
+
+                                        partition@007f0000 {
+                                                label = "FIS directory";
+                                                reg = <0x007f0000 0x00010000>; /* 64KB */
+                                        };
+                                };
+                        };
+
+                        i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                                clock-frequency = <400000>;
+                                status = "okay";
+
+                                /* Main device RTC chip */
+                                s35390a: s35390a@30 {
+                                         compatible = "sii,s35390a";
+                                         reg = <0x30>;
+                                };
+                        };
+
+                        /* Connected to a header on device's PCB */
+                        serial@12000 {
+                                status = "okay";
+                        };
+
+                        /* Connected to a TI MSP430F2111 for power control */
+                        serial@12100 {
+                                status = "okay";
+                        };
+
+                        poweroff@12100 {
+                                compatible = "synology,power-off";
+                                reg = <0x12100 0x100>;
+                                clocks = <&coreclk 0>;
+                        };
+
+                        /* rear USB port, near reset button */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        /* rear USB port, near RJ45 port */
+                        usb@51000 {
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                               status = "okay";
+                               phy = <&phy1>;
+                               phy-mode = "sgmii";
+                        };
+
+                        sata@a0000 {
+                                nr-ports = <2>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio-fan-32-38 {
+                status = "okay";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin
+                             &fan_ctrl_high_pin &fan_alarm_pin>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 31 GPIO_ACTIVE_HIGH
+                         &gpio2  0 GPIO_ACTIVE_HIGH
+                         &gpio2  1 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       1000 1
+                                       1150 2
+                                       1350 4
+                                       1500 3
+                                       1650 5
+                                       1750 6
+                                       1900 7 >;
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&disk1_led_pin
+                             &disk2_led_pin>;
+                pinctrl-names = "default";
+
+                disk1-led-amber {
+                        label = "synology:amber:disk1";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+
+                disk2-led-amber {
+                        label = "synology:amber:disk2";
+                        gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+                        default-state = "keep";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
+                pinctrl-names = "default";
+
+                sata1_regulator: sata1-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <2000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                };
+
+                sata2_regulator: sata2-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA2 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <4000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&pinctrl {
+        disk1_led_pin: disk1-led-pin {
+                marvell,pins = "mpp31";
+                marvell,function = "gpio";
+        };
+
+        disk2_led_pin: disk2-led-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+
+        sata1_pwr_pin: sata1-pwr-pin {
+                marvell,pins = "mpp37";
+                marvell,function = "gpio";
+        };
+
+        sata2_pwr_pin: sata2-pwr-pin {
+                marvell,pins = "mpp62";
+                marvell,function = "gpio";
+        };
+
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp60";
+                marvell,function = "gpio";
+        };
+
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp48";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit0_pin: syno-id-bit0-pin {
+                marvell,pins = "mpp55";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit1_pin: syno-id-bit1-pin {
+                marvell,pins = "mpp56";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit2_pin: syno-id-bit2-pin {
+                marvell,pins = "mpp57";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit3_pin: syno-id-bit3-pin {
+                marvell,pins = "mpp58";
+                marvell,function = "gpio";
+        };
+
+        fan_ctrl_low_pin: fan-ctrl-low-pin {
+                marvell,pins = "mpp65";
+                marvell,function = "gpio";
+        };
+
+        fan_ctrl_mid_pin: fan-ctrl-mid-pin {
+                marvell,pins = "mpp64";
+                marvell,function = "gpio";
+        };
+
+        fan_ctrl_high_pin: fan-ctrl-high-pin {
+                marvell,pins = "mpp63";
+                marvell,function = "gpo";
+        };
+
+        fan_alarm_pin: fan-alarm-pin {
+                marvell,pins = "mpp38";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90dba78554c8..1af428602748 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -151,7 +151,7 @@
                                 status = "disabled";
                         };
 
-                        serial@12000 {
+                        uart0: serial@12000 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12000 0x100>;
                                 reg-shift = <2>;
@@ -160,7 +160,8 @@
                                 clocks = <&coreclk 0>;
                                 status = "disabled";
                         };
-                        serial@12100 {
+
+                        uart1: serial@12100 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12100 0x100>;
                                 reg-shift = <2>;
@@ -170,6 +171,10 @@
                                 status = "disabled";
                         };
 
+                        pinctrl: pin-ctrl@18000 {
+                                reg = <0x18000 0x38>;
+                        };
+
                         coredivclk: corediv-clock@18740 {
                                 compatible = "marvell,armada-370-corediv-clock";
                                 reg = <0x18740 0xc>;
@@ -233,7 +238,7 @@
                                 status = "disabled";
                         };
 
-                        mdio {
+                        mdio: mdio {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 6b3c23b1e138..fdb3c12a6139 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -95,81 +95,30 @@
                                 compatible = "marvell,aurora-outer-cache";
                                 reg = <0x08000 0x1000>;
                                 cache-id-part = <0x100>;
+                                cache-unified;
                                 wt-override;
                         };
 
-                        i2c0: i2c@11000 {
-                                reg = <0x11000 0x20>;
+                        /*
+                         * Default SPI pinctrl setting, can be overwritten on
+                         * board level if a different configuration is used.
+                         */
+                        spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins1>;
+                                pinctrl-names = "default";
                         };
 
-                        i2c1: i2c@11100 {
-                                reg = <0x11100 0x20>;
+                        spi1: spi@10680 {
+                                pinctrl-0 = <&spi1_pins>;
+                                pinctrl-names = "default";
                         };
 
-                        system-controller@18200 {
-                                compatible = "marvell,armada-370-xp-system-controller";
-                                reg = <0x18200 0x100>;
+                        i2c0: i2c@11000 {
+                                reg = <0x11000 0x20>;
                         };
 
-                        pinctrl {
-                                compatible = "marvell,mv88f6710-pinctrl";
-                                reg = <0x18000 0x38>;
-
-                                sdio_pins1: sdio-pins1 {
-                                        marvell,pins = "mpp9",  "mpp11", "mpp12",
-                                                        "mpp13", "mpp14", "mpp15";
-                                        marvell,function = "sd0";
-                                };
-
-                                sdio_pins2: sdio-pins2 {
-                                        marvell,pins = "mpp47", "mpp48", "mpp49",
-                                                        "mpp50", "mpp51", "mpp52";
-                                        marvell,function = "sd0";
-                                };
-
-                                sdio_pins3: sdio-pins3 {
-                                        marvell,pins = "mpp48", "mpp49", "mpp50",
-                                                        "mpp51", "mpp52", "mpp53";
-                                        marvell,function = "sd0";
-                                };
-
-                                i2c0_pins: i2c0-pins {
-                                        marvell,pins = "mpp2", "mpp3";
-                                        marvell,function = "i2c0";
-                                };
-
-                                i2s_pins1: i2s-pins1 {
-                                        marvell,pins = "mpp5", "mpp6", "mpp7",
-                                                       "mpp8", "mpp9", "mpp10",
-                                                       "mpp12", "mpp13";
-                                        marvell,function = "audio";
-                                };
-
-                                i2s_pins2: i2s-pins2 {
-                                        marvell,pins = "mpp49", "mpp47", "mpp50",
-                                                       "mpp59", "mpp57", "mpp61",
-                                                       "mpp62", "mpp60", "mpp58";
-                                        marvell,function = "audio";
-                                };
-
-                                mdio_pins: mdio-pins {
-                                        marvell,pins = "mpp17", "mpp18";
-                                        marvell,function = "ge";
-                                };
-
-                                ge0_rgmii_pins: ge0-rgmii-pins {
-                                        marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
-                                                       "mpp9", "mpp10", "mpp11", "mpp12",
-                                                       "mpp13", "mpp14", "mpp15", "mpp16";
-                                        marvell,function = "ge0";
-                                };
-
-                                ge1_rgmii_pins: ge1-rgmii-pins {
-                                        marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
-                                                       "mpp23", "mpp24", "mpp25", "mpp26",
-                                                       "mpp27", "mpp28", "mpp29", "mpp30";
-                                        marvell,function = "ge1";
-                                };
+                        i2c1: i2c@11100 {
+                                reg = <0x11100 0x20>;
                         };
 
                         gpio0: gpio@18100 {
@@ -205,6 +154,26 @@
                                 interrupts = <91>;
                         };
 
+                        /*
+                         * Default UART pinctrl setting without RTS/CTS, can
+                         * be overwritten on board level if a different
+                         * configuration is used.
+                         */
+                        uart0: serial@12000 {
+                                pinctrl-0 = <&uart0_pins>;
+                                pinctrl-names = "default";
+                        };
+
+                        uart1: serial@12100 {
+                                pinctrl-0 = <&uart1_pins>;
+                                pinctrl-names = "default";
+                        };
+
+                        system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
+
                         gateclk: clock-gating-control@18220 {
                                 compatible = "marvell,armada-370-gating-clock";
                                 reg = <0x18220 0x4>;
@@ -249,6 +218,7 @@
                         };
 
                         audio_controller: audio-controller@30000 {
+                                #sound-dai-cells = <1>;
                                 compatible = "marvell,armada370-audio";
                                 reg = <0x30000 0x4000>;
                                 interrupts = <93>;
@@ -305,3 +275,91 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv88f6710-pinctrl";
+
+        spi0_pins1: spi0-pins1 {
+                marvell,pins = "mpp33", "mpp34",
+                               "mpp35", "mpp36";
+                marvell,function = "spi0";
+        };
+
+        spi0_pins2: spi0_pins2 {
+                marvell,pins = "mpp32", "mpp63",
+                               "mpp64", "mpp65";
+                marvell,function = "spi0";
+        };
+
+        spi1_pins: spi1-pins {
+                marvell,pins = "mpp49", "mpp50",
+                               "mpp51", "mpp52";
+                marvell,function = "spi1";
+        };
+
+        uart0_pins: uart0-pins {
+                marvell,pins = "mpp0", "mpp1";
+                marvell,function = "uart0";
+        };
+
+        uart1_pins: uart1-pins {
+                marvell,pins = "mpp41", "mpp42";
+                marvell,function = "uart1";
+        };
+
+        sdio_pins1: sdio-pins1 {
+                marvell,pins = "mpp9",  "mpp11", "mpp12",
+                                "mpp13", "mpp14", "mpp15";
+                marvell,function = "sd0";
+        };
+
+        sdio_pins2: sdio-pins2 {
+                marvell,pins = "mpp47", "mpp48", "mpp49",
+                                "mpp50", "mpp51", "mpp52";
+                marvell,function = "sd0";
+        };
+
+        sdio_pins3: sdio-pins3 {
+                marvell,pins = "mpp48", "mpp49", "mpp50",
+                                "mpp51", "mpp52", "mpp53";
+                marvell,function = "sd0";
+        };
+
+        i2c0_pins: i2c0-pins {
+                marvell,pins = "mpp2", "mpp3";
+                marvell,function = "i2c0";
+        };
+
+        i2s_pins1: i2s-pins1 {
+                marvell,pins = "mpp5", "mpp6", "mpp7",
+                               "mpp8", "mpp9", "mpp10",
+                               "mpp12", "mpp13";
+                marvell,function = "audio";
+        };
+
+        i2s_pins2: i2s-pins2 {
+                marvell,pins = "mpp49", "mpp47", "mpp50",
+                               "mpp59", "mpp57", "mpp61",
+                               "mpp62", "mpp60", "mpp58";
+                marvell,function = "audio";
+        };
+
+        mdio_pins: mdio-pins {
+                marvell,pins = "mpp17", "mpp18";
+                marvell,function = "ge";
+        };
+
+        ge0_rgmii_pins: ge0-rgmii-pins {
+                marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
+                               "mpp9", "mpp10", "mpp11", "mpp12",
+                               "mpp13", "mpp14", "mpp15", "mpp16";
+                marvell,function = "ge0";
+        };
+
+        ge1_rgmii_pins: ge1-rgmii-pins {
+                marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
+                               "mpp23", "mpp24", "mpp25", "mpp26",
+                               "mpp27", "mpp28", "mpp29", "mpp30";
+                marvell,function = "ge1";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index de6571445cef..9721e55384ce 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -36,6 +36,12 @@
                         #clock-cells = <0>;
                         clock-frequency = <2000000000>;
                 };
+                /* 25 MHz reference crystal */
+                refclk: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
         };
 
         cpus {
@@ -366,13 +372,15 @@
                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                                                       <&mpic 5>,
                                                       <&mpic 6>;
-                                clocks = <&coreclk 0>;
+                                clocks = <&coreclk 0>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
                         };
 
                         watchdog@20300 {
                                 compatible = "marvell,armada-375-wdt";
                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
-                                clocks = <&coreclk 0>;
+                                clocks = <&coreclk 0>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
                         };
 
                         cpurst@20800 {
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 1af886f1e486..2aaa9d2ac284 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -116,11 +116,11 @@
                         };
 
                         sdhci@d8000 {
-                                clock-frequency = <200000000>;
                                 broken-cd;
                                 wp-inverted;
                                 bus-width = <8>;
                                 status = "okay";
+                                no-1-8-v;
                         };
 
                         usb3@f0000 {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 242d0ecc99f3..74391dace9e7 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -25,9 +25,9 @@
         aliases {
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
-                eth0 = &eth0;
-                eth1 = &eth1;
-                eth2 = &eth2;
+                ethernet0 = &eth0;
+                ethernet1 = &eth1;
+                ethernet2 = &eth2;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index a55a97a70505..ca0200e20751 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,40 +60,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                pinctrl-0 = <&pmx_phy_int>;
-                                pinctrl-names = "default";
-
-                                pmx_ge0: pmx-ge0 {
-                                        marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                                       "mpp4", "mpp5", "mpp6", "mpp7",
-                                                       "mpp8", "mpp9", "mpp10", "mpp11";
-                                        marvell,function = "ge0";
-                                };
-
-                                pmx_ge1: pmx-ge1 {
-                                        marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
-                                                       "mpp16", "mpp17", "mpp18", "mpp19",
-                                                       "mpp20", "mpp21", "mpp22", "mpp23";
-                                        marvell,function = "ge1";
-                                };
-
-                                pmx_keys: pmx-keys {
-                                        marvell,pins = "mpp33";
-                                        marvell,function = "gpio";
-                                };
-
-                                pmx_spi: pmx-spi {
-                                        marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
-                                        marvell,function = "spi";
-                                };
-
-                                pmx_phy_int: pmx-phy-int {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         serial@12000 {
                                 status = "okay";
                         };
@@ -118,14 +84,14 @@
                         };
 
                         ethernet@70000 {
-                                pinctrl-0 = <&pmx_ge0>;
+                                pinctrl-0 = <&ge0_rgmii_pins>;
                                 pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
                         ethernet@74000 {
-                                pinctrl-0 = <&pmx_ge1>;
+                                pinctrl-0 = <&ge1_rgmii_pins>;
                                 pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
@@ -134,8 +100,6 @@
 
                         spi0: spi@10600 {
                                 status = "okay";
-                                pinctrl-0 = <&pmx_spi>;
-                                pinctrl-names = "default";
 
                                 spi-flash@0 {
                                         #address-cells = <1>;
@@ -152,7 +116,7 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
-                pinctrl-0 = <&pmx_keys>;
+                pinctrl-0 = <&keys_pin>;
                 pinctrl-names = "default";
 
                 button@1 {
@@ -162,3 +126,18 @@
                 };
         };
 };
+
+&pinctrl {
+        pinctrl-0 = <&phy_int_pin>;
+        pinctrl-names = "default";
+
+        keys_pin: keys-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+
+        phy_int_pin: phy-int-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 469cf7137595..a2ef93c1eb10 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -22,7 +22,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
-                stdout-path = "/soc/internal-regs/serial@12000";
+                stdout-path = &uart0;
         };
 
         memory {
@@ -51,37 +51,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                poweroff_pin: poweroff-pin {
-                                        marvell,pins = "mpp24";
-                                        marvell,function = "gpio";
-                                };
-
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp44";
-                                        marvell,function = "gpio";
-                                };
-
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp45";
-                                        marvell,function = "gpio";
-                                };
-                                select_button_pin: select-button-pin {
-                                        marvell,pins = "mpp41";
-                                        marvell,function = "gpio";
-                                };
-
-                                scroll_button_pin: scroll-button-pin {
-                                        marvell,pins = "mpp42";
-                                        marvell,function = "gpio";
-                                };
-
-                                hdd_led_pin: hdd-led-pin {
-                                        marvell,pins = "mpp26";
-                                        marvell,function = "gpio";
-                                };
-                        };
-
                         serial@12000 {
                                 status = "okay";
                         };
@@ -97,12 +66,16 @@
                         };
 
                         ethernet@70000 {
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy0>;
                                 phy-mode = "rgmii-id";
                         };
 
                         ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
                                 status = "okay";
                                 phy = <&phy1>;
                                 phy-mode = "rgmii-id";
@@ -125,6 +98,11 @@
                                         reg = <0x2e>;
                                 };
 
+                                eeprom@50 {
+                                        compatible = "atmel,24c64";
+                                        reg = <0x50>;
+                                };
+
                                 pcf8563@51 {
                                         compatible = "nxp,pcf8563";
                                         reg = <0x51>;
@@ -226,7 +204,7 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                         reg = <0>;
-                        registers-number = <2>;
+                        registers-number = <1>;
                         spi-max-frequency = <100000>;
                 };
         };
@@ -282,3 +260,34 @@
                 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
         };
 };
+
+&pinctrl {
+        poweroff_pin: poweroff-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+        select_button_pin: select-button-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+
+        scroll_button_pin: scroll-button-pin {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+
+        hdd_led_pin: hdd-led-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 2592e1c13560..281ccd24295c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -167,17 +167,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78230-pinctrl";
-                                reg = <0x18000 0x38>;
-
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
-
                         gpio0: gpio@18100 {
                                 compatible = "marvell,orion-gpio";
                                 reg = <0x18100 0x40>;
@@ -202,3 +191,7 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv78230-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 480e237a870f..d7a8d0b0f385 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -251,17 +251,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78260-pinctrl";
-                                reg = <0x18000 0x38>;
-
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
-
                         gpio0: gpio@18100 {
                                 compatible = "marvell,orion-gpio";
                                 reg = <0x18100 0x40>;
@@ -305,3 +294,7 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv78260-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 2c7b1fef4703..9c40c130d11a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -289,17 +289,6 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                compatible = "marvell,mv78460-pinctrl";
-                                reg = <0x18000 0x38>;
-
-                                sdio_pins: sdio-pins {
-                                        marvell,pins = "mpp30", "mpp31", "mpp32",
-                                                       "mpp33", "mpp34", "mpp35";
-                                        marvell,function = "sd0";
-                                };
-                        };
-
                         gpio0: gpio@18100 {
                                 compatible = "marvell,orion-gpio";
                                 reg = <0x18100 0x40>;
@@ -343,3 +332,7 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv78460-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 7d8f32873e82..d81430aa4ab3 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -55,86 +55,10 @@
                 };
 
                 internal-regs {
-                        pinctrl {
-                                poweroff: poweroff {
-                                        marvell,pins = "mpp42";
-                                        marvell,function = "gpio";
-                                };
-
-                                power_button_pin: power-button-pin {
-                                        marvell,pins = "mpp27";
-                                        marvell,function = "gpio";
-                                };
-
-                                reset_button_pin: reset-button-pin {
-                                        marvell,pins = "mpp41";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata1_led_pin: sata1-led-pin {
-                                        marvell,pins = "mpp31";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata2_led_pin: sata2-led-pin {
-                                        marvell,pins = "mpp40";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata3_led_pin: sata3-led-pin {
-                                        marvell,pins = "mpp44";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata4_led_pin: sata4-led-pin {
-                                        marvell,pins = "mpp47";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata1_power_pin: sata1-power-pin {
-                                        marvell,pins = "mpp24";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata2_power_pin: sata2-power-pin {
-                                        marvell,pins = "mpp25";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata3_power_pin: sata3-power-pin {
-                                        marvell,pins = "mpp26";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata4_power_pin: sata4-power-pin {
-                                        marvell,pins = "mpp28";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata1_pres_pin: sata1-pres-pin {
-                                        marvell,pins = "mpp32";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata2_pres_pin: sata2-pres-pin {
-                                        marvell,pins = "mpp33";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata3_pres_pin: sata3-pres-pin {
-                                        marvell,pins = "mpp34";
-                                        marvell,function = "gpio";
-                                };
-
-                                sata4_pres_pin: sata4-pres-pin {
-                                        marvell,pins = "mpp35";
-                                        marvell,function = "gpio";
-                                };
-
-                                err_led_pin: err-led-pin {
-                                        marvell,pins = "mpp45";
-                                        marvell,function = "gpio";
-                                };
+                        /* Two rear eSATA ports */
+                        sata@a0000 {
+                                nr-ports = <2>;
+                                status = "okay";
                         };
 
                         serial@12000 {
@@ -328,3 +252,85 @@
                 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
         };
 };
+
+&pinctrl {
+        poweroff: poweroff {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+
+        power_button_pin: power-button-pin {
+                marvell,pins = "mpp27";
+                marvell,function = "gpio";
+        };
+
+        reset_button_pin: reset-button-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+
+        sata1_led_pin: sata1-led-pin {
+                marvell,pins = "mpp31";
+                marvell,function = "gpio";
+        };
+
+        sata2_led_pin: sata2-led-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+
+        sata3_led_pin: sata3-led-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+
+        sata4_led_pin: sata4-led-pin {
+                marvell,pins = "mpp47";
+                marvell,function = "gpio";
+        };
+
+        sata1_power_pin: sata1-power-pin {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+
+        sata2_power_pin: sata2-power-pin {
+                marvell,pins = "mpp25";
+                marvell,function = "gpio";
+        };
+
+        sata3_power_pin: sata3-power-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+
+        sata4_power_pin: sata4-power-pin {
+                marvell,pins = "mpp28";
+                marvell,function = "gpio";
+        };
+
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+
+        sata3_pres_pin: sata3-pres-pin {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+
+        sata4_pres_pin: sata4-pres-pin {
+                marvell,pins = "mpp35";
+                marvell,function = "gpio";
+        };
+
+        err_led_pin: err-led-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 4e5a59ee1501..6f6b0916df48 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -77,12 +77,7 @@
                         serial@12100 {
                                 status = "okay";
                         };
-                        pinctrl {
-                                led_pins: led-pins-0 {
-                                        marvell,pins = "mpp49", "mpp51", "mpp53";
-                                        marvell,function = "gpio";
-                                };
-                        };
+
                         leds {
                                 compatible = "gpio-leds";
                                 pinctrl-names = "default";
@@ -187,3 +182,10 @@
                 };
         };
 };
+
+&pinctrl {
+        led_pins: led-pins-0 {
+                marvell,pins = "mpp49", "mpp51", "mpp53";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
new file mode 100644
index 000000000000..749fdba5a642
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -0,0 +1,330 @@
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "Synology DS414";
+        compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+                     "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = &uart0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * Connected to Marvell 88SX7042 SATA-II controller
+                         * handling the four disks.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /*
+                         * Connected to EtronTech EJ168A XHCI controller
+                         * providing the two rear USB 3.0 ports.
+                         */
+                        pcie@5,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+
+                        /* RTC is provided by Seiko S-35390A below */
+                        rtc@10300 {
+                                status = "disabled";
+                        };
+
+                        spi0: spi@10600 {
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "micron,n25q064";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <20000000>;
+
+                                        /*
+                                         * Warning!
+                                         *
+                                         * Synology u-boot uses its compiled-in environment
+                                         * and it seems Synology did not care to change u-boot
+                                         * default configuration in order to allow saving a
+                                         * modified environment at a sensible location. So,
+                                         * if you do a 'saveenv' under u-boot, your modified
+                                         * environment will be saved at 1MB after the start
+                                         * of the flash, i.e. in the middle of the uImage.
+                                         * For that reason, it is strongly advised not to
+                                         * change the default environment, unless you know
+                                         * what you are doing.
+                                         */
+                                        partition@00000000 { /* u-boot */
+                                                label = "RedBoot";
+                                                reg = <0x00000000 0x000d0000>; /* 832KB */
+                                        };
+
+                                        partition@000c0000 { /* uImage */
+                                                label = "zImage";
+                                                reg = <0x000d0000 0x002d0000>; /* 2880KB */
+                                        };
+
+                                        partition@003a0000 { /* uInitramfs */
+                                                label = "rd.gz";
+                                                reg = <0x003a0000 0x00430000>; /* 4250KB */
+                                        };
+
+                                        partition@007d0000 { /* MAC address and serial number */
+                                                label = "vendor";
+                                                reg = <0x007d0000 0x00010000>; /* 64KB */
+                                        };
+
+                                        partition@007e0000 {
+                                                label = "RedBoot config";
+                                                reg = <0x007e0000 0x00010000>; /* 64KB */
+                                        };
+
+                                        partition@007f0000 {
+                                                label = "FIS directory";
+                                                reg = <0x007f0000 0x00010000>; /* 64KB */
+                                        };
+                                };
+                        };
+
+                        i2c@11000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+
+                                s35390a: s35390a@30 {
+                                         compatible = "sii,s35390a";
+                                         reg = <0x30>;
+                                };
+                        };
+
+                        /* Connected to a header on device's PCB. This
+                         * provides the main console for the device.
+                         *
+                         * Warning: the device may not boot with a 3.3V
+                         * USB-serial converter connected when the power
+                         * button is pressed. The converter needs to be
+                         * connected a few seconds after pressing the
+                         * power button. This is possibly due to UART0_TXD
+                         * pin being sampled at reset (bit 0 of SAR).
+                         */
+                        serial@12000 {
+                                status = "okay";
+                        };
+
+                        /* Connected to a Microchip PIC16F883 for power control */
+                        serial@12100 {
+                                status = "okay";
+                        };
+
+                        poweroff@12100 {
+                                compatible = "synology,power-off";
+                                reg = <0x12100 0x100>;
+                                clocks = <&coreclk 0>;
+                        };
+
+                        /* Front USB 2.0 port */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                                status = "okay";
+                                pinctrl-0 = <&ge0_rgmii_pins>;
+                                pinctrl-names = "default";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        ethernet@74000 {
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+                             &sata3_pwr_pin &sata4_pwr_pin>;
+                pinctrl-names = "default";
+
+                sata1_regulator: sata1-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <2000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                };
+
+                sata2_regulator: sata2-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA2 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <4000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                };
+
+                sata3_regulator: sata3-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "SATA3 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <6000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+
+                sata4_regulator: sata4-regulator {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "SATA4 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        startup-delay-us = <8000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+&pinctrl {
+        sata1_pwr_pin: sata1-pwr-pin {
+                marvell,pins = "mpp42";
+                marvell,function = "gpio";
+        };
+
+        sata2_pwr_pin: sata2-pwr-pin {
+                marvell,pins = "mpp44";
+                marvell,function = "gpio";
+        };
+
+        sata3_pwr_pin: sata3-pwr-pin {
+                marvell,pins = "mpp45";
+                marvell,function = "gpio";
+        };
+
+        sata4_pwr_pin: sata4-pwr-pin {
+                marvell,pins = "mpp46";
+                marvell,function = "gpio";
+        };
+
+        sata1_pres_pin: sata1-pres-pin {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+
+        sata2_pres_pin: sata2-pres-pin {
+                marvell,pins = "mpp35";
+                marvell,function = "gpio";
+        };
+
+        sata3_pres_pin: sata3-pres-pin {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+
+        sata4_pres_pin: sata4-pres-pin {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit0_pin: syno-id-bit0-pin {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit1_pin: syno-id-bit1-pin {
+                marvell,pins = "mpp28";
+                marvell,function = "gpio";
+        };
+
+        syno_id_bit2_pin: syno-id-bit2-pin {
+                marvell,pins = "mpp29";
+                marvell,function = "gpio";
+        };
+
+        fan1_alarm_pin: fan1-alarm-pin {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+
+        fan2_alarm_pin: fan2-alarm-pin {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 2be244a96edf..62c3ba958b39 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -44,9 +44,15 @@
                                 compatible = "marvell,aurora-system-cache";
                                 reg = <0x08000 0x1000>;
                                 cache-id-part = <0x100>;
+                                cache-unified;
                                 wt-override;
                         };
 
+                        spi0: spi@10600 {
+                                pinctrl-0 = <&spi0_pins>;
+                                pinctrl-names = "default";
+                        };
+
                         i2c0: i2c@11000 {
                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
                                 reg = <0x11000 0x100>;
@@ -57,8 +63,10 @@
                                 reg = <0x11100 0x100>;
                         };
 
-                        serial@12200 {
+                        uart2: serial@12200 {
                                 compatible = "snps,dw-apb-uart";
+                                pinctrl-0 = <&uart2_pins>;
+                                pinctrl-names = "default";
                                 reg = <0x12200 0x100>;
                                 reg-shift = <2>;
                                 interrupts = <43>;
@@ -66,8 +74,11 @@
                                 clocks = <&coreclk 0>;
                                 status = "disabled";
                         };
-                        serial@12300 {
+
+                        uart3: serial@12300 {
                                 compatible = "snps,dw-apb-uart";
+                                pinctrl-0 = <&uart3_pins>;
+                                pinctrl-names = "default";
                                 reg = <0x12300 0x100>;
                                 reg-shift = <2>;
                                 interrupts = <44>;
@@ -204,3 +215,54 @@
                 };
         };
 };
+
+&pinctrl {
+        ge0_gmii_pins: ge0-gmii-pins {
+                marvell,pins =
+                     "mpp0",  "mpp1",  "mpp2",  "mpp3",
+                     "mpp4",  "mpp5",  "mpp6",  "mpp7",
+                     "mpp8",  "mpp9",  "mpp10", "mpp11",
+                     "mpp12", "mpp13", "mpp14", "mpp15",
+                     "mpp16", "mpp17", "mpp18", "mpp19",
+                     "mpp20", "mpp21", "mpp22", "mpp23";
+                marvell,function = "ge0";
+        };
+
+        ge0_rgmii_pins: ge0-rgmii-pins {
+                marvell,pins =
+                     "mpp0", "mpp1", "mpp2", "mpp3",
+                     "mpp4", "mpp5", "mpp6", "mpp7",
+                     "mpp8", "mpp9", "mpp10", "mpp11";
+                marvell,function = "ge0";
+        };
+
+        ge1_rgmii_pins: ge1-rgmii-pins {
+                marvell,pins =
+                     "mpp12", "mpp13", "mpp14", "mpp15",
+                     "mpp16", "mpp17", "mpp18", "mpp19",
+                     "mpp20", "mpp21", "mpp22", "mpp23";
+                marvell,function = "ge1";
+        };
+
+        sdio_pins: sdio-pins {
+                marvell,pins = "mpp30", "mpp31", "mpp32",
+                               "mpp33", "mpp34", "mpp35";
+                marvell,function = "sd0";
+        };
+
+        spi0_pins: spi0-pins {
+                marvell,pins = "mpp36", "mpp37",
+                               "mpp38", "mpp39";
+                marvell,function = "spi";
+        };
+
+        uart2_pins: uart2-pins {
+                marvell,pins = "mpp42", "mpp43";
+                marvell,function = "uart2";
+        };
+
+        uart3_pins: uart3-pins {
+                marvell,pins = "mpp44", "mpp45";
+                marvell,function = "uart3";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 51416c7d0625..653e4395b7cb 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -677,6 +677,14 @@
                                         };
                                 };
 
+                                can {
+                                        pinctrl_can_rx_tx: can_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* CANRX, conflicts with IRQ0 */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -905,6 +913,17 @@
                                 clock-names = "pwm_clk";
                                 status = "disabled";
                         };
+
+                        can: can@fffac000 {
+                                compatible = "atmel,at91sam9263-can";
+                                reg = <0xfffac000 0x300>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can_rx_tx>;
+                                clocks = <&can_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
                 };
 
                 fb0: fb@0x00700000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index c2554219f7a4..3c5fa3388997 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,6 +10,7 @@
 #include "at91sam9x5_usart3.dtsi"
 #include "at91sam9x5_macb0.dtsi"
 #include "at91sam9x5_macb1.dtsi"
+#include "at91sam9x5_can.dtsi"
 
 / {
         model = "Atmel AT91SAM9X25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 8eac66ce0ab7..499cdc81f4c0 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -8,6 +8,7 @@
 
 #include "at91sam9x5.dtsi"
 #include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_can.dtsi"
 
 / {
         model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 726274f7959b..bbb3ba65165f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,6 +860,9 @@
                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 clocks = <&mck>;
                                 clock-names = "usart";
                                 status = "disabled";
@@ -871,6 +874,9 @@
                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 clocks = <&usart0_clk>;
                                 clock-names = "usart";
                                 status = "disabled";
@@ -882,6 +888,9 @@
                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
+                                       <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 clocks = <&usart1_clk>;
                                 clock-names = "usart";
                                 status = "disabled";
@@ -893,6 +902,9 @@
                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 clocks = <&usart2_clk>;
                                 clock-names = "usart";
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index f44ab7702a12..8eb2f9c1b978 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -1,5 +1,5 @@
 /*
- * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
  * Ethernet interface.
  *
  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -20,10 +20,50 @@
                                                 reg = <29>;
                                         };
 
-                                        can1_clk: can1_clk {
-                                                #clock-cells = <0>;
-                                                reg = <30>;
-                                        };
+                                        can1_clk: can1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <30>;
+                                        };
+                                };
+                        };
+
+                        can0: can@f8000000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8000000 0x300>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                clocks = <&can0_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
+
+                        can1: can@f8004000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8004000 0x300>;
+                                interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                                clocks = <&can1_clk>;
+                                clock-names = "can_clk";
+                                status = "disabled";
+                        };
+
+                        pinctrl@fffff400 {
+                                can0 {
+                                        pinctrl_can0_rx_tx: can0_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX0, conflicts with DRXD */
+                                                        AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* CANTX0, conflicts with DTXD */
+                                        };
+                                };
+
+                                can1 {
+                                        pinctrl_can1_rx_tx: can1_rx_tx {
+                                                atmel,pins =
+                                                        <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX1, conflicts with RXD1 */
+                                                        AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;   /* CANTX1, conflicts with TXD1 */
+                                        };
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 140217a54384..43bb5b51caa6 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -57,6 +57,9 @@
                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart3>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
+                                       <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+                                dma-names = "tx", "rx";
                                 clocks = <&usart3_clk>;
                                 clock-names = "usart";
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index bb22842a0826..29598667420b 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -131,6 +131,7 @@
                                 reg = <0x90020000 0x10000>;
                                 interrupts = <31>;
                                 clocks = <&clks 35>;
+                                resets = <&rstc 6>;
                         };
                 };
 
@@ -312,6 +313,7 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 clocks = <&clks 19>;
+                                resets = <&rstc 26>;
                                 status = "disabled";
                         };
 
@@ -327,6 +329,7 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 clocks = <&clks 20>;
+                                resets = <&rstc 27>;
                                 status = "disabled";
                         };
 
@@ -522,6 +525,18 @@
                                                 sirf,function = "sdmmc5";
                                         };
                                 };
+                                i2s_mclk_pins_a: i2s_mclk@0 {
+                                        i2s_mclk {
+                                                sirf,pins = "i2smclkgrp";
+                                                sirf,function = "i2s_mclk";
+                                        };
+                                };
+                                i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
+                                        i2s_ext_clk_input {
+                                                sirf,pins = "i2s_ext_clk_inputgrp";
+                                                sirf,function = "i2s_ext_clk_input";
+                                        };
+                                };
                                 i2s_pins_a: i2s@0 {
                                         i2s {
                                                 sirf,pins = "i2sgrp";
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 000000000000..60d8389fdb6c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,91 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+clocks {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        osc: oscillator {
+                compatible = "fixed-clock";
+                #clock-cells = <1>;
+                clock-frequency = <25000000>;
+        };
+
+        apb_clk: apb_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1000000000>;
+        };
+
+        periph_clk: periph_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <500000000>;
+        };
+
+        sdio_clk: lcpll_ch2 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <200000000>;
+        };
+
+        axi81_clk: axi81_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
+
+        keypad_clk: keypad_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <31806>;
+        };
+
+        adc_clk: adc_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1562500>;
+        };
+
+        pwm_clk: pwm_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1000000>;
+        };
+
+        lcd_clk: mipipll_ch1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 000000000000..5126f9e77a98
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "brcm,cygnus";
+        model = "Broadcom Cygnus SoC";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+        };
+
+        /include/ "bcm-cygnus-clock.dtsi"
+
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus", "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                wdt@18009000 {
+                         compatible = "arm,sp805" , "arm,primecell";
+                         reg = <0x18009000 0x1000>;
+                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                         clocks = <&axi81_clk>;
+                         clock-names = "apb_pclk";
+                };
+        };
+
+        uart0: serial@18020000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18020000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+
+        uart1: serial@18021000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18021000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+
+        uart2: serial@18022000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18020000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+
+        uart3: serial@18023000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x18023000 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&axi81_clk>;
+                clock-frequency = <100000000>;
+                status = "disabled";
+        };
+
+        gic: interrupt-controller@19021000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x19021000 0x1000>,
+                      <0x19020100 0x100>;
+        };
+
+        L2: l2-cache {
+                compatible = "arm,pl310-cache";
+                reg = <0x19022000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
+        timer@19020200 {
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0x19020200 0x100>;
+                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&periph_clk>;
+        };
+
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
new file mode 100644
index 000000000000..e479515099c3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/include/ "bcm2835-rpi.dtsi"
+
+/ {
+        compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
+        model = "Raspberry Pi Model B+";
+
+        leds {
+                act {
+                        gpios = <&gpio 47 0>;
+                };
+
+                pwr {
+                        label = "PWR";
+                        gpios = <&gpio 35 0>;
+                        default-state = "keep";
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+
+&gpio {
+        pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+
+        /* I2S interface */
+        i2s_alt0: i2s_alt0 {
+                brcm,pins = <18 19 20 21>;
+                brcm,function = <4>; /* alt0 */
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 58a0d60b95f1..bafa46fc226a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,63 +1,23 @@
 /dts-v1/;
-/include/ "bcm2835.dtsi"
+/include/ "bcm2835-rpi.dtsi"
 
 / {
         compatible = "raspberrypi,model-b", "brcm,bcm2835";
         model = "Raspberry Pi Model B";
 
-        memory {
-                reg = <0 0x10000000>;
-        };
-
         leds {
-                compatible = "gpio-leds";
-
                 act {
-                        label = "ACT";
                         gpios = <&gpio 16 1>;
-                        default-state = "keep";
-                        linux,default-trigger = "heartbeat";
                 };
         };
 };
 
 &gpio {
-        pinctrl-names = "default";
-        pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
-
-        gpioout: gpioout {
-                brcm,pins = <6>;
-                brcm,function = <1>; /* GPIO out */
-        };
-
-        alt0: alt0 {
-                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
-                brcm,function = <4>; /* alt0 */
-        };
-
-        alt3: alt3 {
-                brcm,pins = <48 49 50 51 52 53>;
-                brcm,function = <7>; /* alt3 */
-        };
+        pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
 
         /* I2S interface */
-        alt2: alt2 {
+        i2s_alt2: i2s_alt2 {
                 brcm,pins = <28 29 30 31>;
                 brcm,function = <6>; /* alt2 */
         };
 };
-
-&i2c0 {
-        status = "okay";
-        clock-frequency = <100000>;
-};
-
-&i2c1 {
-        status = "okay";
-        clock-frequency = <100000>;
-};
-
-&sdhci {
-        status = "okay";
-        bus-width = <4>;
-};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
new file mode 100644
index 000000000000..c7064487017d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -0,0 +1,51 @@
+/include/ "bcm2835.dtsi"
+
+/ {
+        memory {
+                reg = <0 0x10000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                act {
+                        label = "ACT";
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&gpio {
+        pinctrl-names = "default";
+
+        gpioout: gpioout {
+                brcm,pins = <6>;
+                brcm,function = <1>; /* GPIO out */
+        };
+
+        alt0: alt0 {
+                brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
+                brcm,function = <4>; /* alt0 */
+        };
+
+        alt3: alt3 {
+                brcm,pins = <48 49 50 51 52 53>;
+                brcm,function = <7>; /* alt3 */
+        };
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
+
+&sdhci {
+        status = "okay";
+        bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
new file mode 100644
index 000000000000..5fc0fae03092
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -0,0 +1,64 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-1750DHP
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+        compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
+        model = "Buffalo WZR-1750DHP (BCM4708)";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+
+                aoss {
+                        label = "AOSS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
+                };
+
+                /* Commit mode set by switch? */
+                mode {
+                        label = "Mode";
+                        linux,code = <KEY_SETUP>;
+                        gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+                };
+
+                /* Switch: AP mode */
+                sw_ap {
+                        label = "AP";
+                        linux,code = <BTN_0>;
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                };
+
+                eject {
+                        label = "USB eject";
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 3b5259de5a38..4ed7de1058b7 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -32,4 +32,63 @@
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                logo {
+                        label = "bcm53xx:white:logo";
+                        gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                power0 {
+                        label = "bcm53xx:green:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                usb {
+                        label = "bcm53xx:blue:usb";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                wireless {
+                        label = "bcm53xx:blue:wireless";
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
new file mode 100644
index 000000000000..12fc2a01e6ab
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -0,0 +1,84 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Netgear R6300 V2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+        compatible = "netgear,r6300v2", "brcm,bcm4708";
+        model = "Netgear R6300 V2 (BCM4708)";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                logo {
+                        label = "bcm53xx:white:logo";
+                        gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                power0 {
+                        label = "bcm53xx:green:power";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                power1 {
+                        label = "bcm53xx:amber:power";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                usb {
+                        label = "bcm53xx:blue:usb";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                wireless {
+                        label = "bcm53xx:blue:wireless";
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+                };
+
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
new file mode 100644
index 000000000000..fb76378bd511
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -0,0 +1,78 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Asus RT-N18U
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm47081.dtsi"
+
+/ {
+        compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708";
+        model = "Asus RT-N18U (BCM47081)";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                power {
+                        label = "bcm53xx:blue:power";
+                        gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                usb2 {
+                        label = "bcm53xx:blue:usb2";
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+
+                wan {
+                        label = "bcm53xx:blue:wan";
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                lan {
+                        label = "bcm53xx:blue:lan";
+                        gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                usb3 {
+                        label = "bcm53xx:blue:usb3";
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-off";
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+                };
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
new file mode 100644
index 000000000000..bbb414fbad65
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -0,0 +1,57 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Buffalo WZR-600DHP2
+ *
+ * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm47081.dtsi"
+
+/ {
+        compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708";
+        model = "Buffalo WZR-600DHP2 (BCM47081)";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <200>;
+
+                aoss {
+                        label = "AOSS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+
+                /* Switch device mode? */
+                mode {
+                        label = "Mode";
+                        linux,code = <KEY_SETUP>;
+                        gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+                };
+
+                eject {
+                        label = "USB eject";
+                        linux,code = <KEY_EJECTCD>;
+                        gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi
new file mode 100644
index 000000000000..f720012ee5ed
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for BCM47081 SoC.
+ *
+ * Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include "bcm5301x.dtsi"
+
+/ {
+        compatible = "brcm,bcm47081";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 53c624f766b4..78aec6270c2f 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,8 @@
  * Licensed under the GNU/GPL. See COPYING for details.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "skeleton.dtsi"
@@ -92,4 +94,53 @@
                         clock-frequency = <400000000>;
                 };
         };
+
+        axi@18000000 {
+                compatible = "brcm,bus-axi";
+                reg = <0x18000000 0x1000>;
+                ranges = <0x00000000 0x18000000 0x00100000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0x000fffff 0xffff>;
+                interrupt-map = 
+                        /* ChipCommon */
+                        <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* USB 2.0 Controller */
+                        <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* USB 3.0 Controller */
+                        <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* Ethernet Controller 0 */
+                        <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* Ethernet Controller 1 */
+                        <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* Ethernet Controller 2 */
+                        <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* Ethernet Controller 3 */
+                        <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+
+                        /* NAND Controller */
+                        <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+
+                chipcommon: chipcommon@0 {
+                        reg = <0x00000000 0x1000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 000000000000..d2ee95280548
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+        model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+        compatible = "brcm,bcm11360", "brcm,cygnus";
+
+        aliases {
+                serial0 = &uart3;
+        };
+
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 000000000000..9658d4f62d59
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+        model = "Cygnus SVK (BCM911360K)";
+        compatible = "brcm,bcm11360", "brcm,cygnus";
+
+        aliases {
+                serial0 = &uart3;
+        };
+
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 000000000000..f1bb36f3975c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,53 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+        model = "Cygnus SVK (BCM958300K)";
+        compatible = "brcm,bcm58300", "brcm,cygnus";
+
+        aliases {
+                serial0 = &uart3;
+        };
+
+        chosen {
+                stdout-path = &uart3;
+                bootargs = "console=ttyS0,115200";
+        };
+
+        uart3: serial@18023000 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..86d85d8896a3 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,20 @@
         };
 };
 
+&ahci { status = "okay"; };
+
+&eth1 { status = "okay"; };
+
+/* Unpopulated SATA plug on solder side */
+&sata0 { status = "okay"; };
+
+&sata_phy { status = "okay"; };
+
+/* Samsung M8G2FA 8GB eMMC */
+&sdhci2 {
+        non-removable;
+        bus-width = <8>;
+        status = "okay";
+};
+
 &uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 9d7c810ebd0b..015a06c67c91 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -53,6 +53,35 @@
 
                 ranges = <0 0xf7000000 0x1000000>;
 
+                sdhci0: sdhci@ab0000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0000 0x200>;
+                        clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                sdhci1: sdhci@ab0800 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0800 0x200>;
+                        clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                sdhci2: sdhci@ab1000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab1000 0x200>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
+                        clock-names = "io", "core";
+                        pinctrl-0 = <&emmc_pmux>;
+                        pinctrl-names = "default";
+                        status = "disabled";
+                };
+
                 l2: l2-cache-controller@ac0000 {
                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
                         reg = <0xac0000 0x1000>;
@@ -79,11 +108,47 @@
                         clocks = <&chip CLKID_TWD>;
                 };
 
+                eth1: ethernet@b90000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xb90000 0x10000>;
+                        clocks = <&chip CLKID_GETH1>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy1>;
+                        status = "disabled";
+
+                        ethphy1: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
                 cpu-ctrl@dd0000 {
                         compatible = "marvell,berlin-cpu-ctrl";
                         reg = <0xdd0000 0x10000>;
                 };
 
+                eth0: ethernet@e50000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xe50000 0x10000>;
+                        clocks = <&chip CLKID_GETH0>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy0>;
+                        status = "disabled";
+
+                        ethphy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
                 apb@e80000 {
                         compatible = "simple-bus";
                         #address-cells = <1>;
@@ -246,12 +311,57 @@
                         };
                 };
 
+                ahci: sata@e90000 {
+                        compatible = "marvell,berlin2-ahci", "generic-ahci";
+                        reg = <0xe90000 0x1000>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy 0>;
+                                status = "disabled";
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy 1>;
+                                status = "disabled";
+                        };
+                };
+
+                sata_phy: phy@e900a0 {
+                        compatible = "marvell,berlin2-sata-phy";
+                        reg = <0xe900a0 0x200>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #phy-cells = <1>;
+                        status = "disabled";
+
+                        sata-phy@0 {
+                                reg = <0>;
+                        };
+
+                        sata-phy@1 {
+                                reg = <1>;
+                        };
+                };
+
                 chip: chip-control@ea0000 {
                         compatible = "marvell,berlin2-chip-ctrl";
                         #clock-cells = <1>;
+                        #reset-cells = <2>;
                         reg = <0xea0000 0x400>;
                         clocks = <&refclk>;
                         clock-names = "refclk";
+
+                        emmc_pmux: emmc-pmux {
+                                groups = "G26";
+                                function = "emmc";
+                        };
                 };
 
                 apb@fc0000 {
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
index bcd81ffc495d..30270be4d0c9 100644
--- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 
 #include "berlin2cd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Google Chromecast";
@@ -24,6 +25,35 @@
                 device_type = "memory";
                 reg = <0x00000000 0x20000000>; /* 512 MB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                white {
+                        label = "white";
+                        gpios = <&portc 1 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+
+                red {
+                        label = "red";
+                        gpios = <&portc 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+        };
+};
+
+/*
+ * AzureWave AW-NH387 (Marvell 88W8787)
+ * 802.11b/g/n + Bluetooth 2.1
+ */
+&sdhci0 {
+        non-removable;
+        status = "okay";
 };
 
 &uart0 { status = "okay"; };
+
+&usb_phy1 { status = "okay"; };
+
+&usb1 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index cc1df65da504..230df3b1770e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,15 @@
 
                 ranges = <0 0xf7000000 0x1000000>;
 
+                sdhci0: sdhci@ab0000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0000 0x200>;
+                        clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+                        clock-names = "io", "core";
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
                 l2: l2-cache-controller@ac0000 {
                         compatible = "arm,pl310-cache";
                         reg = <0xac0000 0x1000>;
@@ -66,6 +75,58 @@
                         clocks = <&chip CLKID_TWD>;
                 };
 
+                usb_phy0: usb-phy@b74000 {
+                        compatible = "marvell,berlin2cd-usb-phy";
+                        reg = <0xb74000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x178 23>;
+                        status = "disabled";
+                };
+
+                usb_phy1: usb-phy@b78000 {
+                        compatible = "marvell,berlin2cd-usb-phy";
+                        reg = <0xb78000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x178 24>;
+                        status = "disabled";
+                };
+
+                eth1: ethernet@b90000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xb90000 0x10000>;
+                        clocks = <&chip CLKID_GETH1>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy1>;
+                        status = "disabled";
+
+                        ethphy1: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
+                eth0: ethernet@e50000 {
+                        compatible = "marvell,pxa168-eth";
+                        reg = <0xe50000 0x10000>;
+                        clocks = <&chip CLKID_GETH0>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        /* set by bootloader */
+                        local-mac-address = [00 00 00 00 00 00];
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy-connection-type = "mii";
+                        phy-handle = <&ethphy0>;
+                        status = "disabled";
+
+                        ethphy0: ethernet-phy@0 {
+                                reg = <0>;
+                        };
+                };
+
                 apb@e80000 {
                         compatible = "simple-bus";
                         #address-cells = <1>;
@@ -231,6 +292,7 @@
                 chip: chip-control@ea0000 {
                         compatible = "marvell,berlin2cd-chip-ctrl";
                         #clock-cells = <1>;
+                        #reset-cells = <2>;
                         reg = <0xea0000 0x400>;
                         clocks = <&refclk>;
                         clock-names = "refclk";
@@ -241,6 +303,26 @@
                         };
                 };
 
+                usb0: usb@ed0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xed0000 0x200>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB0>;
+                        phys = <&usb_phy0>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+
+                usb1: usb@ee0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xee0000 0x200>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB1>;
+                        phys = <&usb_phy1>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+
                 apb@fc0000 {
                         compatible = "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index ea1f99b8eed6..28e7e2060c33 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -7,6 +7,8 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
 #include "berlin2q.dtsi"
 
 / {
@@ -21,6 +23,39 @@
         choosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
         };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reg_usb0_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                reg_usb1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                reg_usb2_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
 };
 
 &sdhci1 {
@@ -46,6 +81,32 @@
         status = "okay";
 };
 
+&usb_phy0 {
+        status = "okay";
+};
+
+&usb_phy2 {
+        status = "okay";
+};
+
+&usb0 {
+        vbus-supply = <&reg_usb0_vbus>;
+        status = "okay";
+};
+
+&usb2 {
+        vbus-supply = <&reg_usb2_vbus>;
+        status = "okay";
+};
+
 &eth0 {
         status = "okay";
 };
+
+&sata0 {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..35253c947a7c 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,40 @@
                         #interrupt-cells = <3>;
                 };
 
+                usb_phy2: phy@a2f400 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xa2f400 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 14>;
+                        status = "disabled";
+                };
+
+                usb2: usb@a30000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xa30000 0x10000>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB2>;
+                        phys = <&usb_phy2>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+
+                usb_phy0: phy@b74000 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xb74000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 12>;
+                        status = "disabled";
+                };
+
+                usb_phy1: phy@b78000 {
+                        compatible = "marvell,berlin2-usb-phy";
+                        reg = <0xb78000 0x128>;
+                        #phy-cells = <0>;
+                        resets = <&chip 0x104 13>;
+                        status = "disabled";
+                };
+
                 eth0: ethernet@b90000 {
                         compatible = "marvell,pxa168-eth";
                         reg = <0xb90000 0x10000>;
@@ -123,6 +157,7 @@
                         local-mac-address = [00 00 00 00 00 00];
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        phy-connection-type = "mii";
                         phy-handle = <&ethphy0>;
                         status = "disabled";
 
@@ -255,7 +290,6 @@
                                 reg = <0x2c14 0x14>;
                                 clocks = <&chip CLKID_CFG>;
                                 clock-names = "timer";
-                                status = "disabled";
                         };
 
                         timer2: timer@2c28 {
@@ -349,6 +383,7 @@
                 chip: chip-control@ea0000 {
                         compatible = "marvell,berlin2q-chip-ctrl";
                         #clock-cells = <1>;
+                        #reset-cells = <2>;
                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
                         clocks = <&refclk>;
                         clock-names = "refclk";
@@ -364,6 +399,65 @@
                         };
                 };
 
+                ahci: sata@e90000 {
+                        compatible = "marvell,berlin2q-ahci", "generic-ahci";
+                        reg = <0xe90000 0x1000>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        sata0: sata-port@0 {
+                                reg = <0>;
+                                phys = <&sata_phy 0>;
+                                status = "disabled";
+                        };
+
+                        sata1: sata-port@1 {
+                                reg = <1>;
+                                phys = <&sata_phy 1>;
+                                status = "disabled";
+                        };
+                };
+
+                sata_phy: phy@e900a0 {
+                        compatible = "marvell,berlin2q-sata-phy";
+                        reg = <0xe900a0 0x200>;
+                        clocks = <&chip CLKID_SATA>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #phy-cells = <1>;
+                        status = "disabled";
+
+                        sata-phy@0 {
+                                reg = <0>;
+                        };
+
+                        sata-phy@1 {
+                                reg = <1>;
+                        };
+                };
+
+                usb0: usb@ed0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xed0000 0x10000>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB0>;
+                        phys = <&usb_phy0>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+
+                usb1: usb@ee0000 {
+                        compatible = "chipidea,usb2";
+                        reg = <0xee0000 0x10000>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_USB1>;
+                        phys = <&usb_phy1>;
+                        phy-names = "usb-phy";
+                        status = "disabled";
+                };
+
                 apb@fc0000 {
                         compatible = "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce6258434f..736092b1a535 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,101 @@
                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
                 >;
         };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
+                        0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
+                        0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
+                        0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
+                        0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
+                        0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
+                        0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
+                        0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
+                        0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
+                        0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
+                        0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
+                        0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
+
+                        /* Slave 2 */
+                        0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
+                        0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
+                        0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
+                        0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
+                        0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
+                        0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
+                        0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
+                        0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
+                        0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
+                        0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
+                        0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
+                        0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
+                >;
+
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x250 (MUX_MODE15)
+                        0x254 (MUX_MODE15)
+                        0x258 (MUX_MODE15)
+                        0x25c (MUX_MODE15)
+                        0x260 (MUX_MODE15)
+                        0x264 (MUX_MODE15)
+                        0x268 (MUX_MODE15)
+                        0x26c (MUX_MODE15)
+                        0x270 (MUX_MODE15)
+                        0x274 (MUX_MODE15)
+                        0x278 (MUX_MODE15)
+                        0x27c (MUX_MODE15)
+
+                        /* Slave 2 */
+                        0x198 (MUX_MODE15)
+                        0x19c (MUX_MODE15)
+                        0x1a0 (MUX_MODE15)
+                        0x1a4 (MUX_MODE15)
+                        0x1a8 (MUX_MODE15)
+                        0x1ac (MUX_MODE15)
+                        0x1b0 (MUX_MODE15)
+                        0x1b4 (MUX_MODE15)
+                        0x1b8 (MUX_MODE15)
+                        0x1bc (MUX_MODE15)
+                        0x1c0 (MUX_MODE15)
+                        0x1c4 (MUX_MODE15)
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
+                        0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        0x23c (MUX_MODE15)
+                        0x240 (MUX_MODE15)
+                >;
+        };
+
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
+                        0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
+                        0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
+                >;
+        };
+
+        dcan1_pins_sleep: dcan1_pins_sleep {
+                pinctrl-single,pins = <
+                        0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
+                        0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
+                        0x418   (MUX_MODE15)    /* wakeup0.off */
+                >;
+        };
 };
 
 &i2c1 {
@@ -201,6 +296,7 @@
                                         regulator-name = "smps45";
                                         regulator-min-microvolt = < 850000>;
                                         regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
@@ -209,6 +305,7 @@
                                         regulator-name = "smps6";
                                         regulator-min-microvolt = <850000>;
                                         regulator-max-microvolt = <12500000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
@@ -226,6 +323,7 @@
                                         regulator-name = "smps8";
                                         regulator-min-microvolt = < 850000>;
                                         regulator-max-microvolt = <1250000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
@@ -252,6 +350,7 @@
                                         regulator-name = "ldo2";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
@@ -269,6 +368,7 @@
                                         regulator-name = "ldo9";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
+                                        regulator-always-on;
                                         regulator-boot-on;
                                 };
 
@@ -528,3 +628,36 @@
         ti,no-reset-on-init;
         ti,no-idle-on-init;
 };
+
+&mac {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac;
+};
+
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <2>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <3>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
+&dcan1 {
+        status = "ok";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&dcan1_pins_default>;
+        pinctrl-1 = <&dcan1_pins_sleep>;
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc98436a982..63bf99be1762 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,14 @@
                 serial3 = &uart4;
                 serial4 = &uart5;
                 serial5 = &uart6;
+                serial6 = &uart7;
+                serial7 = &uart8;
+                serial8 = &uart9;
+                serial9 = &uart10;
+                ethernet0 = &cpsw_emac0;
+                ethernet1 = &cpsw_emac1;
+                d_can0 = &dcan1;
+                d_can1 = &dcan2;
         };
 
         timer {
@@ -201,6 +209,11 @@
                         ti,hwmods = "counter_32k";
                 };
 
+                dra7_ctrl_core: ctrl_core@4a002000 {
+                        compatible = "syscon";
+                        reg = <0x4a002000 0x6d0>;
+                };
+
                 dra7_ctrl_general: tisyscon@4a002e00 {
                         compatible = "syscon";
                         reg = <0x4a002e00 0x7c>;
@@ -335,6 +348,8 @@
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 49>, <&sdma 50>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart2: serial@4806c000 {
@@ -344,6 +359,8 @@
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 51>, <&sdma 52>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart3: serial@48020000 {
@@ -353,6 +370,8 @@
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 53>, <&sdma 54>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart4: serial@4806e000 {
@@ -362,6 +381,8 @@
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 55>, <&sdma 56>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart5: serial@48066000 {
@@ -371,6 +392,8 @@
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 63>, <&sdma 64>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart6: serial@48068000 {
@@ -380,6 +403,8 @@
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                         status = "disabled";
+                        dmas = <&sdma 79>, <&sdma 80>;
+                        dma-names = "tx", "rx";
                 };
 
                 uart7: serial@48420000 {
@@ -421,7 +446,11 @@
                 mailbox1: mailbox@4a0f4000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x4a0f4000 0x200>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox1";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <3>;
                         ti,mbox-num-fifos = <8>;
                         status = "disabled";
@@ -430,7 +459,12 @@
                 mailbox2: mailbox@4883a000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x4883a000 0x200>;
+                        interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox2";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -439,7 +473,12 @@
                 mailbox3: mailbox@4883c000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x4883c000 0x200>;
+                        interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox3";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -448,7 +487,12 @@
                 mailbox4: mailbox@4883e000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x4883e000 0x200>;
+                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox4";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -457,7 +501,12 @@
                 mailbox5: mailbox@48840000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48840000 0x200>;
+                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox5";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -466,7 +515,12 @@
                 mailbox6: mailbox@48842000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48842000 0x200>;
+                        interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox6";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -475,7 +529,12 @@
                 mailbox7: mailbox@48844000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48844000 0x200>;
+                        interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox7";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -484,7 +543,12 @@
                 mailbox8: mailbox@48846000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48846000 0x200>;
+                        interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox8";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -493,7 +557,12 @@
                 mailbox9: mailbox@4885e000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x4885e000 0x200>;
+                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox9";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -502,7 +571,12 @@
                 mailbox10: mailbox@48860000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48860000 0x200>;
+                        interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox10";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -511,7 +585,12 @@
                 mailbox11: mailbox@48862000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48862000 0x200>;
+                        interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox11";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -520,7 +599,12 @@
                 mailbox12: mailbox@48864000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48864000 0x200>;
+                        interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox12";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -529,7 +613,12 @@
                 mailbox13: mailbox@48802000 {
                         compatible = "ti,omap4-mailbox";
                         reg = <0x48802000 0x200>;
+                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox13";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <12>;
                         status = "disabled";
@@ -1075,6 +1164,15 @@
                         status = "disabled";
                 };
 
+                rtc@48838000 {
+                        compatible = "ti,am3352-rtc";
+                        reg = <0x48838000 0x100>;
+                        interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "rtcss";
+                        clocks = <&sys_32k_ck>;
+                };
+
                 omap_control_usb2phy1: control-phy@4a002300 {
                         compatible = "ti,control-phy-usb2";
                         reg = <0x4a002300 0x4>;
@@ -1141,7 +1239,7 @@
                         };
                 };
 
-                omap_dwc3_1@48880000 {
+                omap_dwc3_1: omap_dwc3_1@48880000 {
                         compatible = "ti,dwc3";
                         ti,hwmods = "usb_otg_ss1";
                         reg = <0x48880000 0x10000>;
@@ -1162,7 +1260,7 @@
                         };
                 };
 
-                omap_dwc3_2@488c0000 {
+                omap_dwc3_2: omap_dwc3_2@488c0000 {
                         compatible = "ti,dwc3";
                         ti,hwmods = "usb_otg_ss2";
                         reg = <0x488c0000 0x10000>;
@@ -1184,7 +1282,7 @@
                 };
 
                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
-                omap_dwc3_3@48900000 {
+                omap_dwc3_3: omap_dwc3_3@48900000 {
                         compatible = "ti,dwc3";
                         ti,hwmods = "usb_otg_ss3";
                         reg = <0x48900000 0x10000>;
@@ -1204,26 +1302,6 @@
                         };
                 };
 
-                omap_dwc3_4@48940000 {
-                        compatible = "ti,dwc3";
-                        ti,hwmods = "usb_otg_ss4";
-                        reg = <0x48940000 0x10000>;
-                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        utmi-mode = <2>;
-                        ranges;
-                        status = "disabled";
-                        usb4: usb@48950000 {
-                                compatible = "snps,dwc3";
-                                reg = <0x48950000 0x17000>;
-                                interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                                tx-fifo-resize;
-                                maximum-speed = "high-speed";
-                                dr_mode = "otg";
-                        };
-                };
-
                 elm: elm@48078000 {
                         compatible = "ti,am3352-elm";
                         reg = <0x48078000 0xfc0>;      /* device IO registers */
@@ -1265,6 +1343,84 @@
                         ti,irqs-skip = <10 133 139 140>;
                         ti,irqs-safe-map = <0>;
                 };
+
+                mac: ethernet@4a100000 {
+                        compatible = "ti,cpsw";
+                        ti,hwmods = "gmac";
+                        clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+                        clock-names = "fck", "cpts";
+                        cpdma_channels = <8>;
+                        ale_entries = <1024>;
+                        bd_ram_size = <0x2000>;
+                        no_bd_ram = <0>;
+                        rx_descs = <64>;
+                        mac_control = <0x20>;
+                        slaves = <2>;
+                        active_slave = <0>;
+                        cpts_clock_mult = <0x80000000>;
+                        cpts_clock_shift = <29>;
+                        reg = <0x48484000 0x1000
+                               0x48485200 0x2E00>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /*
+                         * rx_thresh_pend
+                         * rx_pend
+                         * tx_pend
+                         * misc_pend
+                         */
+                        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+                        ranges;
+                        status = "disabled";
+
+                        davinci_mdio: mdio@48485000 {
+                                compatible = "ti,davinci_mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ti,hwmods = "davinci_mdio";
+                                bus_freq = <1000000>;
+                                reg = <0x48485000 0x100>;
+                        };
+
+                        cpsw_emac0: slave@48480200 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+
+                        cpsw_emac1: slave@48480300 {
+                                /* Filled in by U-Boot */
+                                mac-address = [ 00 00 00 00 00 00 ];
+                        };
+
+                        phy_sel: cpsw-phy-sel@4a002554 {
+                                compatible = "ti,dra7xx-cpsw-phy-sel";
+                                reg= <0x4a002554 0x4>;
+                                reg-names = "gmii-sel";
+                        };
+                };
+
+                dcan1: can@481cc000 {
+                        compatible = "ti,dra7-d_can";
+                        ti,hwmods = "dcan1";
+                        reg = <0x4ae3c000 0x2000>;
+                        syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&dcan1_sys_clk_mux>;
+                        status = "disabled";
+                };
+
+                dcan2: can@481d0000 {
+                        compatible = "ti,dra7-d_can";
+                        ti,hwmods = "dcan2";
+                        reg = <0x48480000 0x2000>;
+                        syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sys_clkin1>;
+                        status = "disabled";
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 41074288adfa..afc74fd4bb5e 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,6 +17,13 @@
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1024 MB */
         };
+
+        evm_3v3: fixedregulator-evm_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "evm_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 
 &dra7_pmx_core {
@@ -26,6 +33,94 @@
                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
                 >;
         };
+
+        nand_default: nand_default {
+                pinctrl-single,pins = <
+                        0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
+                        0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
+                        0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
+                        0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
+                        0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
+                        0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
+                        0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
+                        0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
+                        0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
+                        0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
+                        0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
+                        0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
+                        0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
+                        0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
+                        0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
+                        0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
+                        0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+                        0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+                        0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+                        0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+                        0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+                        0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
+                >;
+        };
+
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+
+        usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+                        0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+                >;
+        };
+
+        tps65917_pins_default: tps65917_pins_default {
+                pinctrl-single,pins = <
+                        0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+                >;
+        };
+
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
+                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc2_pins_default: mmc2_pins_default {
+                pinctrl-single,pins = <
+                        0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        0x3d0   (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
+                        0x3d4   (MUX_MODE15)            /* dcan1_rx.off */
+                        0x418   (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
+                >;
+        };
+
+        dcan1_pins_sleep: dcan1_pins_sleep {
+                pinctrl-single,pins = <
+                        0x3d0   (MUX_MODE15)    /* dcan1_tx.off */
+                        0x3d4   (MUX_MODE15)    /* dcan1_rx.off */
+                        0x418   (MUX_MODE15)    /* wakeup0.off */
+                >;
+        };
 };
 
 &i2c1 {
@@ -38,6 +133,9 @@
                 compatible = "ti,tps65917";
                 reg = <0x58>;
 
+                pinctrl-names = "default";
+                pinctrl-0 = <&tps65917_pins_default>;
+
                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
                 interrupt-parent = <&gic>;
                 interrupt-controller;
@@ -136,9 +234,230 @@
                                 };
                         };
                 };
+
+                tps65917_power_button {
+                        compatible = "ti,palmas-pwrbutton";
+                        interrupt-parent = <&tps65917>;
+                        interrupts = <1 IRQ_TYPE_NONE>;
+                        wakeup-source;
+                        ti,palmas-long-press-seconds = <6>;
+                };
         };
 };
 
 &uart1 {
         status = "okay";
 };
+
+&elm {
+        status = "okay";
+};
+
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_default>;
+        ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+        nand@0,0 {
+                /* To use NAND, DIP switch SW5 must be set like so:
+                 * SW5.1 (NAND_SELn) = ON (LOW)
+                 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+                 */
+                reg = <0 0 4>;          /* device IO registers */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <80>;
+                gpmc,cs-wr-off-ns = <80>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <60>;
+                gpmc,adv-wr-off-ns = <60>;
+                gpmc,we-on-ns = <10>;
+                gpmc,we-off-ns = <50>;
+                gpmc,oe-on-ns = <4>;
+                gpmc,oe-off-ns = <40>;
+                gpmc,access-ns = <40>;
+                gpmc,wr-access-ns = <80>;
+                gpmc,rd-cycle-ns = <80>;
+                gpmc,wr-cycle-ns = <80>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x000020000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00020000 0x00020000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00040000 0x00020000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x00060000 0x00020000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x000c0000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001c0000 0x00020000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env.backup1";
+                        reg = <0x001e0000 0x00020000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00200000 0x00800000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00a00000 0x0f600000>;
+                };
+        };
+};
+
+&usb2_phy1 {
+        phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+        phy-supply = <&ldo4_reg>;
+};
+
+&usb1 {
+        dr_mode = "peripheral";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+        dr_mode = "host";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb2_pins>;
+};
+
+&mmc1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_default>;
+
+        vmmc-supply = <&ldo1_reg>;
+        bus-width = <4>;
+        /*
+         * SDCD signal is not being used here - using the fact that GPIO mode
+         * is a viable alternative
+         */
+        cd-gpios = <&gpio6 27 0>;
+};
+
+&mmc2 {
+        /* SW5-3 in ON position */
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_default>;
+
+        vmmc-supply = <&evm_3v3>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+
+&dra7_pmx_core {
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 2 */
+                        0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
+                        0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
+                        0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
+                        0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
+                        0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
+                        0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
+                        0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
+                        0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
+                        0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
+                        0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
+                        0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
+                        0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
+                >;
+
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 2 */
+                        0x198 (MUX_MODE15)
+                        0x19c (MUX_MODE15)
+                        0x1a0 (MUX_MODE15)
+                        0x1a4 (MUX_MODE15)
+                        0x1a8 (MUX_MODE15)
+                        0x1ac (MUX_MODE15)
+                        0x1b0 (MUX_MODE15)
+                        0x1b4 (MUX_MODE15)
+                        0x1b8 (MUX_MODE15)
+                        0x1bc (MUX_MODE15)
+                        0x1c0 (MUX_MODE15)
+                        0x1c4 (MUX_MODE15)
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
+                        0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        0x23c (MUX_MODE15)
+                        0x240 (MUX_MODE15)
+                >;
+        };
+};
+
+&mac {
+        status = "okay";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <3>;
+        phy-mode = "rgmii";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        active_slave = <1>;
+};
+
+&dcan1 {
+        status = "ok";
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&dcan1_pins_default>;
+        pinctrl-1 = <&dcan1_pins_sleep>;
+};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c4891f..10173fab1a15 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -44,4 +44,26 @@
                 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
         };
+
+        ocp {
+                omap_dwc3_4: omap_dwc3_4@48940000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss4";
+                        reg = <0x48940000 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        status = "disabled";
+                        usb4: usb@48950000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x48950000 0x17000>;
+                                interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                                tx-fifo-resize;
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
new file mode 100644
index 000000000000..24822aa98057
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -0,0 +1,579 @@
+/*
+ * Samsung's Exynos3250 based Monk board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Monk board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Samsung Monk board";
+        compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3";
+
+        aliases {
+                i2c7 = &i2c_max77836;
+        };
+
+        memory {
+                reg =  <0x40000000 0x1ff00000>;
+        };
+
+        firmware@0205F000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x0205F000 0x1000>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                power_key {
+                        interrupt-parent = <&gpx2>;
+                        interrupts = <7 0>;
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power key";
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        vemmc_reg: voltage-regulator-0 {
+                compatible = "regulator-fixed";
+                regulator-name = "V_EMMC_2.8V-fixed";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpk0 2 0>;
+                enable-active-high;
+        };
+
+        i2c_max77836: i2c-gpio-0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                max77836: subpmic@25 {
+                        compatible = "maxim,max77836";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 0>;
+                        reg = <0x25>;
+                        wakeup;
+
+                        muic: max77836-muic {
+                                compatible = "maxim,max77836-muic";
+                        };
+
+                        regulators {
+                                compatible = "maxim,max77836-regulator";
+                                safeout_reg: SAFEOUT {
+                                        regulator-name = "SAFEOUT";
+                                };
+
+                                charger_reg: CHARGER {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <45000>;
+                                        regulator-max-microamp = <475000>;
+                                        regulator-boot-on;
+                                };
+
+                                motor_reg: LDO1 {
+                                        regulator-name = "MOT_2.7V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <2700000>;
+                                };
+
+                                LDO2 {
+                                        regulator-name = "UNUSED_LDO2";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <3950000>;
+                                };
+                        };
+
+                        charger {
+                                compatible = "maxim,max77836-charger";
+
+                                maxim,constant-uvolt = <4350000>;
+                                maxim,fast-charge-uamp = <225000>;
+                                maxim,eoc-uamp = <7500>;
+                                maxim,ovp-uvolt = <6500000>;
+                        };
+                };
+        };
+};
+
+&adc {
+        vdd-supply = <&ldo3_reg>;
+        status = "okay";
+        assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+        assigned-clock-rates = <6000000>;
+
+        thermistor-ap {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 0>;
+        };
+
+        thermistor-battery {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 1>;
+        };
+};
+
+&i2c_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        status = "okay";
+
+        s2mps14_pmic@66 {
+                compatible = "samsung,s2mps14-pmic";
+                interrupt-parent = <&gpx0>;
+                interrupts = <7 0>;
+                reg = <0x66>;
+                wakeup;
+
+                s2mps14_osc: clocks {
+                        compatible = "samsung,s2mps14-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "s2mps14_ap", "unused",
+                                "s2mps14_bt";
+                };
+
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VAP_ALIVE_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VAP_M1_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VCC_AP_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VAP_AVDD_PLL1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VAP_PLL_ISO_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VAP_MIPI_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VAP_AVDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VAP_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "V_LPDDR_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "UNUSED_LDO10";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "V_EMMC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "V_EMMC_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "VSENSOR_2.85V";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                regulator-always-on;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "UNUSED_LDO14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "TSP_AVDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "LCD_VDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "UNUSED_LDO17";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "UNUSED_LDO18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "TSP_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "LCD_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                regulator-name = "UNUSED_LDO21";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                regulator-name = "UNUSED_LDO22";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "UNUSED_LDO23";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo24_reg: LDO24 {
+                                regulator-name = "UNUSED_LDO24";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "UNUSED_LDO25";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VAP_MIF_1.0V";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-always-on;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "VAP_ARM_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "VAP_INT3D_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "VCC_SUB_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VCC_SUB_1.35V";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&i2c_1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        status = "okay";
+
+        fuelgauge@36 {
+                compatible = "maxim,max77836-battery";
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 8>;
+                reg = <0x36>;
+        };
+};
+
+&i2s2 {
+        status = "okay";
+};
+
+&mshc_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-slots = <1>;
+        broken-cd;
+        non-removable;
+        cap-mmc-highspeed;
+        desc-num = <4>;
+        mmc-hs200-1_8v;
+        card-detect-delay = <200>;
+        vmmc-supply = <&vemmc_reg>;
+        clock-frequency = <100000000>;
+        clock-freq-min-max = <400000 100000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&serial_0 {
+        assigned-clocks = <&cmu CLK_SCLK_UART0>;
+        assigned-clock-rates = <100000000>;
+        status = "okay";
+};
+
+&serial_1 {
+        status = "okay";
+};
+
+&tmu {
+        vtmu-supply = <&ldo7_reg>;
+        status = "okay";
+};
+
+&rtc {
+        clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
+        clock-names = "rtc", "rtc_src";
+        status = "okay";
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+
+        sleep0: sleep-state {
+                PIN_SLP(gpa0-0, INPUT, DOWN);
+                PIN_SLP(gpa0-1, INPUT, DOWN);
+                PIN_SLP(gpa0-2, INPUT, DOWN);
+                PIN_SLP(gpa0-3, INPUT, DOWN);
+                PIN_SLP(gpa0-4, INPUT, DOWN);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, DOWN);
+
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+
+                PIN_SLP(gpb-0, PREV, NONE);
+                PIN_SLP(gpb-1, PREV, NONE);
+                PIN_SLP(gpb-2, PREV, NONE);
+                PIN_SLP(gpb-3, PREV, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, DOWN);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+
+                PIN_SLP(gpc1-0, INPUT, DOWN);
+                PIN_SLP(gpc1-1, INPUT, DOWN);
+                PIN_SLP(gpc1-2, INPUT, DOWN);
+                PIN_SLP(gpc1-3, INPUT, DOWN);
+                PIN_SLP(gpc1-4, INPUT, DOWN);
+
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+
+                PIN_SLP(gpd1-0, INPUT, NONE);
+                PIN_SLP(gpd1-1, INPUT, NONE);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+        };
+};
+
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+
+        sleep1: sleep-state {
+                PIN_SLP(gpe0-0, PREV, NONE);
+                PIN_SLP(gpe0-1, PREV, NONE);
+                PIN_SLP(gpe0-2, INPUT, DOWN);
+                PIN_SLP(gpe0-3, INPUT, DOWN);
+                PIN_SLP(gpe0-4, PREV, NONE);
+                PIN_SLP(gpe0-5, INPUT, DOWN);
+                PIN_SLP(gpe0-6, INPUT, DOWN);
+                PIN_SLP(gpe0-7, INPUT, DOWN);
+
+                PIN_SLP(gpe1-0, INPUT, DOWN);
+                PIN_SLP(gpe1-1, PREV, NONE);
+                PIN_SLP(gpe1-2, INPUT, DOWN);
+                PIN_SLP(gpe1-3, INPUT, DOWN);
+                PIN_SLP(gpe1-4, INPUT, DOWN);
+                PIN_SLP(gpe1-5, INPUT, DOWN);
+                PIN_SLP(gpe1-6, INPUT, DOWN);
+                PIN_SLP(gpe1-7, INPUT, NONE);
+
+                PIN_SLP(gpe2-0, INPUT, NONE);
+                PIN_SLP(gpe2-1, INPUT, NONE);
+                PIN_SLP(gpe2-2, INPUT, NONE);
+
+                PIN_SLP(gpk0-0, INPUT, DOWN);
+                PIN_SLP(gpk0-1, INPUT, DOWN);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, INPUT, DOWN);
+                PIN_SLP(gpk0-4, INPUT, DOWN);
+                PIN_SLP(gpk0-5, INPUT, DOWN);
+                PIN_SLP(gpk0-6, INPUT, DOWN);
+                PIN_SLP(gpk0-7, INPUT, DOWN);
+
+                PIN_SLP(gpk1-0, PREV, NONE);
+                PIN_SLP(gpk1-1, PREV, NONE);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, PREV, NONE);
+                PIN_SLP(gpk1-4, PREV, NONE);
+                PIN_SLP(gpk1-5, PREV, NONE);
+                PIN_SLP(gpk1-6, PREV, NONE);
+
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, DOWN);
+                PIN_SLP(gpm1-3, INPUT, DOWN);
+                PIN_SLP(gpm1-4, INPUT, DOWN);
+                PIN_SLP(gpm1-5, INPUT, DOWN);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+
+                PIN_SLP(gpm2-0, INPUT, DOWN);
+                PIN_SLP(gpm2-1, INPUT, DOWN);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+
+                PIN_SLP(gpm3-0, INPUT, DOWN);
+                PIN_SLP(gpm3-1, INPUT, DOWN);
+                PIN_SLP(gpm3-2, INPUT, DOWN);
+                PIN_SLP(gpm3-3, INPUT, DOWN);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c150f4e..5ab81c39e2c9 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -12,6 +12,22 @@
  * published by the Free Software Foundation.
 */
 
+#define PIN_PULL_NONE           0
+#define PIN_PULL_DOWN           1
+#define PIN_PULL_UP             3
+
+#define PIN_PDN_OUT0            0
+#define PIN_PDN_OUT1            1
+#define PIN_PDN_INPUT           2
+#define PIN_PDN_PREV            3
+
+#define PIN_SLP(_pin, _mode, _pull)                             \
+        _pin {                                                  \
+                samsung,pins = #_pin;                           \
+                samsung,pin-con-pdn = <PIN_PDN_ ##_mode>;       \
+                samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>;      \
+        }
+
 &pinctrl_0 {
         gpa0: gpa0 {
                 gpio-controller;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
new file mode 100644
index 000000000000..80aa8b4c4a3d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -0,0 +1,682 @@
+/*
+ * Samsung's Exynos3250 based Rinato board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Rinato board which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Samsung Rinato board";
+        compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
+
+        aliases {
+                i2c7 = &i2c_max77836;
+        };
+
+        memory {
+                reg =  <0x40000000 0x1ff00000>;
+        };
+
+        firmware@0205F000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x0205F000 0x1000>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                power_key {
+                        interrupt-parent = <&gpx2>;
+                        interrupts = <7 0>;
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <KEY_POWER>;
+                        label = "power key";
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c_max77836: i2c-gpio-0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpd0 2 0>, <&gpd0 3 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                max77836: subpmic@25 {
+                        compatible = "maxim,max77836";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 0>;
+                        reg = <0x25>;
+                        wakeup;
+
+                        muic: max77836-muic {
+                                compatible = "maxim,max77836-muic";
+                        };
+
+                        regulators {
+                                compatible = "maxim,max77836-regulator";
+                                safeout_reg: SAFEOUT {
+                                        regulator-name = "SAFEOUT";
+                                };
+
+                                charger_reg: CHARGER {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <45000>;
+                                        regulator-max-microamp = <475000>;
+                                        regulator-boot-on;
+                                };
+
+                                motor_reg: LDO1 {
+                                        regulator-name = "MOT_2.7V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <2700000>;
+                                };
+
+                                LDO2 {
+                                        regulator-name = "UNUSED_LDO2";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <3950000>;
+                                };
+                        };
+
+                        charger {
+                                compatible = "maxim,max77836-charger";
+
+                                maxim,constant-uvolt = <4350000>;
+                                maxim,fast-charge-uamp = <225000>;
+                                maxim,eoc-uamp = <7500>;
+                                maxim,ovp-uvolt = <6500000>;
+                        };
+                };
+        };
+};
+
+&adc {
+        vdd-supply = <&ldo3_reg>;
+        status = "okay";
+        assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+        assigned-clock-rates = <6000000>;
+
+        thermistor-ap {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 0>;
+        };
+
+        thermistor-battery {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;
+                pullup-ohm = <100000>;
+                pulldown-ohm = <100000>;
+                io-channels = <&adc 1>;
+        };
+};
+
+&i2c_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        status = "okay";
+
+        s2mps14_pmic@66 {
+                compatible = "samsung,s2mps14-pmic";
+                interrupt-parent = <&gpx0>;
+                interrupts = <7 0>;
+                reg = <0x66>;
+                wakeup;
+
+                s2mps14_osc: clocks {
+                        compatible = "samsung,s2mps14-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "s2mps14_ap", "unused",
+                                "s2mps14_bt";
+                };
+
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VAP_ALIVE_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VAP_M1_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VCC_AP_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VAP_AVDD_PLL1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VAP_PLL_ISO_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VAP_VMIPI_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VAP_AVDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VAP_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "V_LPDDR_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "UNUSED_LDO10";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "V_EMMC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "V_EMMC_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                samsung,ext-control-gpios = <&gpk0 2 0>;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "CAM_AVDD_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "UNUSED_LDO14";
+                                regulator-min-microvolt = <2700000>;
+                                regulator-max-microvolt = <2700000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "TSP_AVDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "LCD_VDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "V_IRLED_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "CAM_AF_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "TSP_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "LCD_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo21_reg: LDO21 {
+                                regulator-name = "CAM_IO_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo22_reg: LDO22 {
+                                regulator-name = "CAM_DVDD_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "HRM_VCC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo24_reg: LDO24 {
+                                regulator-name = "HRM_VCC_3.3V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "UNUSED_LDO25";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VAP_MIF_1.0V";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "VAP_ARM_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "VAP_INT3D_1.0V";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "VCC_SUB_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VCC_SUB_1.35V";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c_1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        status = "okay";
+
+        fuelgauge@36 {
+                compatible = "maxim,max77836-battery";
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 8>;
+                reg = <0x36>;
+        };
+};
+
+&i2s2 {
+        status = "okay";
+};
+
+&mfc {
+        status = "okay";
+};
+
+&mshc_0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-slots = <1>;
+        broken-cd;
+        non-removable;
+        cap-mmc-highspeed;
+        desc-num = <4>;
+        mmc-hs200-1_8v;
+        card-detect-delay = <200>;
+        vmmc-supply = <&ldo12_reg>;
+        clock-frequency = <100000000>;
+        clock-freq-min-max = <400000 100000000>;
+        samsung,dw-mshc-ciu-div = <1>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&serial_0 {
+        assigned-clocks = <&cmu CLK_SCLK_UART0>;
+        assigned-clock-rates = <100000000>;
+        status = "okay";
+};
+
+&serial_1 {
+        status = "okay";
+};
+
+&tmu {
+        vtmu-supply = <&ldo7_reg>;
+        status = "okay";
+};
+
+&rtc {
+        clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
+        clock-names = "rtc", "rtc_src";
+        status = "okay";
+};
+
+&xusbxti {
+        clock-frequency = <24000000>;
+};
+
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+
+        sleep0: sleep-state {
+                PIN_SLP(gpa0-0, INPUT, DOWN);
+                PIN_SLP(gpa0-1, INPUT, DOWN);
+                PIN_SLP(gpa0-2, INPUT, DOWN);
+                PIN_SLP(gpa0-3, INPUT, DOWN);
+                PIN_SLP(gpa0-4, INPUT, DOWN);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, DOWN);
+
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+
+                PIN_SLP(gpb-0, PREV, NONE);
+                PIN_SLP(gpb-1, PREV, NONE);
+                PIN_SLP(gpb-2, PREV, NONE);
+                PIN_SLP(gpb-3, PREV, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, DOWN);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+
+                PIN_SLP(gpc1-0, INPUT, DOWN);
+                PIN_SLP(gpc1-1, INPUT, DOWN);
+                PIN_SLP(gpc1-2, INPUT, DOWN);
+                PIN_SLP(gpc1-3, INPUT, DOWN);
+                PIN_SLP(gpc1-4, INPUT, DOWN);
+
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+
+                PIN_SLP(gpd1-0, INPUT, NONE);
+                PIN_SLP(gpd1-1, INPUT, NONE);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+        };
+};
+
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+
+        sleep1: sleep-state {
+                PIN_SLP(gpe0-0, PREV, NONE);
+                PIN_SLP(gpe0-1, PREV, NONE);
+                PIN_SLP(gpe0-2, INPUT, DOWN);
+                PIN_SLP(gpe0-3, INPUT, UP);
+                PIN_SLP(gpe0-4, INPUT, DOWN);
+                PIN_SLP(gpe0-5, INPUT, DOWN);
+                PIN_SLP(gpe0-6, INPUT, DOWN);
+                PIN_SLP(gpe0-7, INPUT, DOWN);
+
+                PIN_SLP(gpe1-0, INPUT, DOWN);
+                PIN_SLP(gpe1-1, PREV, NONE);
+                PIN_SLP(gpe1-2, INPUT, DOWN);
+                PIN_SLP(gpe1-3, INPUT, DOWN);
+                PIN_SLP(gpe1-4, INPUT, DOWN);
+                PIN_SLP(gpe1-5, INPUT, DOWN);
+                PIN_SLP(gpe1-6, INPUT, DOWN);
+                PIN_SLP(gpe1-7, INPUT, NONE);
+
+                PIN_SLP(gpe2-0, INPUT, NONE);
+                PIN_SLP(gpe2-1, INPUT, NONE);
+                PIN_SLP(gpe2-2, INPUT, NONE);
+
+                PIN_SLP(gpk0-0, INPUT, DOWN);
+                PIN_SLP(gpk0-1, INPUT, DOWN);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, INPUT, DOWN);
+                PIN_SLP(gpk0-4, INPUT, DOWN);
+                PIN_SLP(gpk0-5, INPUT, DOWN);
+                PIN_SLP(gpk0-6, INPUT, DOWN);
+                PIN_SLP(gpk0-7, INPUT, DOWN);
+
+                PIN_SLP(gpk1-0, INPUT, DOWN);
+                PIN_SLP(gpk1-1, INPUT, DOWN);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, INPUT, DOWN);
+                PIN_SLP(gpk1-4, INPUT, DOWN);
+                PIN_SLP(gpk1-5, INPUT, DOWN);
+                PIN_SLP(gpk1-6, INPUT, DOWN);
+
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, DOWN);
+                PIN_SLP(gpm1-3, INPUT, DOWN);
+                PIN_SLP(gpm1-4, INPUT, DOWN);
+                PIN_SLP(gpm1-5, INPUT, DOWN);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+
+                PIN_SLP(gpm2-0, INPUT, DOWN);
+                PIN_SLP(gpm2-1, INPUT, DOWN);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+
+                PIN_SLP(gpm3-0, INPUT, DOWN);
+                PIN_SLP(gpm3-1, INPUT, DOWN);
+                PIN_SLP(gpm3-2, INPUT, DOWN);
+                PIN_SLP(gpm3-3, INPUT, DOWN);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 693a3275606f..242ddda0a8cd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -320,6 +320,16 @@
                         status = "disabled";
                 };
 
+                mfc: codec@13400000 {
+                        compatible = "samsung,mfc-v7";
+                        reg = <0x13400000 0x10000>;
+                        interrupts = <0 102 0>;
+                        clock-names = "mfc", "sclk_mfc";
+                        clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
+                        samsung,power-domain = <&pd_mfc>;
+                        status = "disabled";
+                };
+
                 serial_0: serial@13800000 {
                         compatible = "samsung,exynos4210-uart";
                         reg = <0x13800000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e0278ecbc816..b8168f1f8139 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -392,8 +392,8 @@
                 reg = <0x13400000 0x10000>;
                 interrupts = <0 94 0>;
                 samsung,power-domain = <&pd_mfc>;
-                clocks = <&clock CLK_MFC>;
-                clock-names = "mfc";
+                clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
+                clock-names = "mfc", "sclk_mfc";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9e8b3a..720836205546 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -431,18 +431,34 @@
 
                 fimc_0: fimc@11800000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_1: fimc@11810000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_2: fimc@11820000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_3: fimc@11830000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3aa708e..aaf0cae4f5e8 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -473,18 +473,34 @@
 
                 fimc_0: fimc@11800000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_1: fimc@11810000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_2: fimc@11820000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
 
                 fimc_3: fimc@11830000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                        assigned-clock-rates = <0>, <160000000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 807bb5bf91fc..bcc9e63c8070 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,23 @@
                 pinctrl2 = &pinctrl_2;
         };
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@900 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x900>;
+                };
+
+                cpu@901 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x901>;
+                };
+        };
+
         pmu_system_controller: system-controller@10020000 {
                 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
                                 "clkout4", "clkout8", "clkout9";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 3c00e6ec9302..dd0a43ec56da 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,6 +22,23 @@
 / {
         compatible = "samsung,exynos4212", "samsung,exynos4";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@A00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA00>;
+                };
+
+                cpu@A01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA01>;
+                };
+        };
+
         combiner: interrupt-controller@10440000 {
                 samsung,combiner-nr = <18>;
         };
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index c697ff01ae8d..3fbf588682b9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -45,6 +45,16 @@
                 compatible = "samsung,odroidx2-audio";
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&max98090>;
+                assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
+                                <&clock_audss EXYNOS_MOUT_I2S>,
+                                <&clock_audss EXYNOS_DOUT_SRP>,
+                                <&clock_audss EXYNOS_DOUT_AUD_BUS>;
+                assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+                                <&clock_audss EXYNOS_MOUT_AUDSS>;
+                assigned-clock-rates = <0>,
+                                <0>,
+                                <192000000>,
+                                <19200000>;
         };
 
         mmc@12550000 {
@@ -82,18 +92,34 @@
 
                 fimc_0: fimc@11800000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_1: fimc@11810000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_2: fimc@11820000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_3: fimc@11830000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 5e066cd87f66..29231b452643 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Samsung Trats 2 based on Exynos4412";
@@ -22,6 +23,7 @@
         aliases {
                 i2c9 = &i2c_ak8975;
                 i2c10 = &i2c_cm36651;
+                i2c11 = &i2c_max77693;
         };
 
         memory {
@@ -399,8 +401,6 @@
                                         regulator-name = "VMEM_VDD_2.8V";
                                         regulator-min-microvolt = <2800000>;
                                         regulator-max-microvolt = <2800000>;
-                                        regulator-always-on;
-                                        regulator-mem-off;
                                 };
 
                                 ldo23_reg: ldo23 {
@@ -503,8 +503,6 @@
                                         regulator-name = "VMEM_VDDF_3.0V";
                                         regulator-min-microvolt = <2850000>;
                                         regulator-max-microvolt = <2850000>;
-                                        regulator-always-on;
-                                        regulator-mem-off;
                                 };
 
                                 buck9_reg: buck9 {
@@ -518,6 +516,42 @@
                 };
         };
 
+        i2c_max77693: i2c-gpio-1 {
+                compatible = "i2c-gpio";
+                gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+
+                max77693@66 {
+                        compatible = "maxim,max77693";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 2>;
+                        reg = <0x66>;
+
+                        regulators {
+                                esafeout1_reg: ESAFEOUT1@1 {
+                                        regulator-name = "ESAFEOUT1";
+                                };
+                                esafeout2_reg: ESAFEOUT2@2 {
+                                        regulator-name = "ESAFEOUT2";
+                                };
+                                charger_reg: CHARGER@0 {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <60000>;
+                                        regulator-max-microamp = <2580000>;
+                                };
+                        };
+
+                        max77693_haptic {
+                                compatible = "maxim,max77693-haptic";
+                                haptic-supply = <&ldo26_reg>;
+                                pwms = <&pwm 0 38022 0>;
+                        };
+                };
+        };
+
         mmc@12550000 {
                 num-slots = <1>;
                 broken-cd;
@@ -535,6 +569,16 @@
                 cap-mmc-highspeed;
         };
 
+        sdhci@12530000 {
+                bus-width = <4>;
+                cd-gpios = <&gpx3 4 0>;
+                cd-inverted;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+                pinctrl-names = "default";
+                vmmc-supply = <&ldo21_reg>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -551,6 +595,11 @@
                 status = "okay";
         };
 
+        tmu@100C0000 {
+                vtmu-supply = <&ldo10_reg>;
+                status = "okay";
+        };
+
         i2c_ak8975: i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&gpy2 4 0>, <&gpy2 5 0>;
@@ -598,6 +647,13 @@
                 };
         };
 
+        pwm: pwm@139D0000 {
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+                samsung,pwm-outputs = <0>;
+                status = "okay";
+        };
+
         dsi_0: dsi@11C80000 {
                 vddcore-supply = <&ldo8_reg>;
                 vddio-supply = <&ldo10_reg>;
@@ -663,28 +719,51 @@
                 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
                 pinctrl-names = "default";
                 status = "okay";
+                assigned-clocks = <&clock CLK_MOUT_CAM0>,
+                                  <&clock CLK_MOUT_CAM1>;
+                assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>,
+                                         <&clock CLK_MOUT_MPLL_USER_T>;
 
                 fimc_0: fimc@11800000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                                        <&clock CLK_SCLK_FIMC0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_1: fimc@11810000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                                        <&clock CLK_SCLK_FIMC1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_2: fimc@11820000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                                        <&clock CLK_SCLK_FIMC2>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 fimc_3: fimc@11830000 {
                         status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                                        <&clock CLK_SCLK_FIMC3>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
                 };
 
                 csis_0: csis@11880000 {
                         status = "okay";
                         vddcore-supply = <&ldo8_reg>;
                         vddio-supply = <&ldo10_reg>;
-                        clock-frequency = <176000000>;
+                        assigned-clocks = <&clock CLK_MOUT_CSIS0>,
+                                        <&clock CLK_SCLK_CSIS0>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
 
                         /* Camera C (3) MIPI CSI-2 (CSIS0) */
                         port@3 {
@@ -698,10 +777,13 @@
                 };
 
                 csis_1: csis@11890000 {
+                        status = "okay";
                         vddcore-supply = <&ldo8_reg>;
                         vddio-supply = <&ldo10_reg>;
-                        clock-frequency = <160000000>;
-                        status = "okay";
+                        assigned-clocks = <&clock CLK_MOUT_CSIS1>,
+                                        <&clock CLK_SCLK_CSIS1>;
+                        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+                        assigned-clock-rates = <0>, <176000000>;
 
                         /* Camera D (4) MIPI CSI-2 (CSIS1) */
                         port@4 {
@@ -782,3 +864,319 @@
                 io-channels = <&adc 2>;  /* Battery temperature */
         };
 };
+
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+
+        sleep0: sleep-states {
+                PIN_SLP(gpa0-0, INPUT, NONE);
+                PIN_SLP(gpa0-1, OUT0, NONE);
+                PIN_SLP(gpa0-2, INPUT, NONE);
+                PIN_SLP(gpa0-3, INPUT, UP);
+                PIN_SLP(gpa0-4, INPUT, NONE);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, UP);
+
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+
+                PIN_SLP(gpb-0, INPUT, NONE);
+                PIN_SLP(gpb-1, INPUT, NONE);
+                PIN_SLP(gpb-2, INPUT, NONE);
+                PIN_SLP(gpb-3, INPUT, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, UP);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+
+                PIN_SLP(gpc1-0, INPUT, NONE);
+                PIN_SLP(gpc1-1, PREV, NONE);
+                PIN_SLP(gpc1-2, INPUT, NONE);
+                PIN_SLP(gpc1-3, INPUT, NONE);
+                PIN_SLP(gpc1-4, INPUT, NONE);
+
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+
+                PIN_SLP(gpd1-0, INPUT, DOWN);
+                PIN_SLP(gpd1-1, INPUT, DOWN);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+
+                PIN_SLP(gpf0-0, INPUT, NONE);
+                PIN_SLP(gpf0-1, INPUT, NONE);
+                PIN_SLP(gpf0-2, INPUT, DOWN);
+                PIN_SLP(gpf0-3, INPUT, DOWN);
+                PIN_SLP(gpf0-4, INPUT, NONE);
+                PIN_SLP(gpf0-5, INPUT, DOWN);
+                PIN_SLP(gpf0-6, INPUT, NONE);
+                PIN_SLP(gpf0-7, INPUT, DOWN);
+
+                PIN_SLP(gpf1-0, INPUT, DOWN);
+                PIN_SLP(gpf1-1, INPUT, DOWN);
+                PIN_SLP(gpf1-2, INPUT, DOWN);
+                PIN_SLP(gpf1-3, INPUT, DOWN);
+                PIN_SLP(gpf1-4, INPUT, NONE);
+                PIN_SLP(gpf1-5, INPUT, NONE);
+                PIN_SLP(gpf1-6, INPUT, DOWN);
+                PIN_SLP(gpf1-7, PREV, NONE);
+
+                PIN_SLP(gpf2-0, PREV, NONE);
+                PIN_SLP(gpf2-1, INPUT, DOWN);
+                PIN_SLP(gpf2-2, INPUT, DOWN);
+                PIN_SLP(gpf2-3, INPUT, DOWN);
+                PIN_SLP(gpf2-4, INPUT, DOWN);
+                PIN_SLP(gpf2-5, INPUT, DOWN);
+                PIN_SLP(gpf2-6, INPUT, NONE);
+                PIN_SLP(gpf2-7, INPUT, NONE);
+
+                PIN_SLP(gpf3-0, INPUT, NONE);
+                PIN_SLP(gpf3-1, PREV, NONE);
+                PIN_SLP(gpf3-2, PREV, NONE);
+                PIN_SLP(gpf3-3, PREV, NONE);
+                PIN_SLP(gpf3-4, OUT1, NONE);
+                PIN_SLP(gpf3-5, INPUT, DOWN);
+
+                PIN_SLP(gpj0-0, PREV, NONE);
+                PIN_SLP(gpj0-1, PREV, NONE);
+                PIN_SLP(gpj0-2, PREV, NONE);
+                PIN_SLP(gpj0-3, INPUT, DOWN);
+                PIN_SLP(gpj0-4, PREV, NONE);
+                PIN_SLP(gpj0-5, PREV, NONE);
+                PIN_SLP(gpj0-6, INPUT, DOWN);
+                PIN_SLP(gpj0-7, INPUT, DOWN);
+
+                PIN_SLP(gpj1-0, INPUT, DOWN);
+                PIN_SLP(gpj1-1, PREV, NONE);
+                PIN_SLP(gpj1-2, PREV, NONE);
+                PIN_SLP(gpj1-3, INPUT, DOWN);
+                PIN_SLP(gpj1-4, INPUT, DOWN);
+        };
+};
+
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+
+        sleep1: sleep-states {
+                PIN_SLP(gpk0-0, PREV, NONE);
+                PIN_SLP(gpk0-1, PREV, NONE);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, PREV, NONE);
+                PIN_SLP(gpk0-4, PREV, NONE);
+                PIN_SLP(gpk0-5, PREV, NONE);
+                PIN_SLP(gpk0-6, PREV, NONE);
+
+                PIN_SLP(gpk1-0, INPUT, DOWN);
+                PIN_SLP(gpk1-1, INPUT, DOWN);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, PREV, NONE);
+                PIN_SLP(gpk1-4, PREV, NONE);
+                PIN_SLP(gpk1-5, PREV, NONE);
+                PIN_SLP(gpk1-6, PREV, NONE);
+
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+
+                PIN_SLP(gpk3-0, OUT0, NONE);
+                PIN_SLP(gpk3-1, INPUT, NONE);
+                PIN_SLP(gpk3-2, INPUT, DOWN);
+                PIN_SLP(gpk3-3, INPUT, NONE);
+                PIN_SLP(gpk3-4, INPUT, NONE);
+                PIN_SLP(gpk3-5, INPUT, NONE);
+                PIN_SLP(gpk3-6, INPUT, NONE);
+
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+                PIN_SLP(gpl0-4, PREV, NONE);
+                PIN_SLP(gpl0-6, PREV, NONE);
+
+                PIN_SLP(gpl1-0, INPUT, DOWN);
+                PIN_SLP(gpl1-1, INPUT, DOWN);
+                PIN_SLP(gpl2-0, INPUT, DOWN);
+                PIN_SLP(gpl2-1, INPUT, DOWN);
+                PIN_SLP(gpl2-2, INPUT, DOWN);
+                PIN_SLP(gpl2-3, INPUT, DOWN);
+                PIN_SLP(gpl2-4, INPUT, DOWN);
+                PIN_SLP(gpl2-5, INPUT, DOWN);
+                PIN_SLP(gpl2-6, PREV, NONE);
+                PIN_SLP(gpl2-7, INPUT, DOWN);
+
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, NONE);
+                PIN_SLP(gpm1-3, INPUT, NONE);
+                PIN_SLP(gpm1-4, INPUT, NONE);
+                PIN_SLP(gpm1-5, INPUT, NONE);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+
+                PIN_SLP(gpm2-0, INPUT, NONE);
+                PIN_SLP(gpm2-1, INPUT, NONE);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+
+                PIN_SLP(gpm3-0, PREV, NONE);
+                PIN_SLP(gpm3-1, PREV, NONE);
+                PIN_SLP(gpm3-2, PREV, NONE);
+                PIN_SLP(gpm3-3, OUT1, NONE);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+
+                PIN_SLP(gpy0-0, INPUT, DOWN);
+                PIN_SLP(gpy0-1, INPUT, DOWN);
+                PIN_SLP(gpy0-2, INPUT, DOWN);
+                PIN_SLP(gpy0-3, INPUT, DOWN);
+                PIN_SLP(gpy0-4, INPUT, DOWN);
+                PIN_SLP(gpy0-5, INPUT, DOWN);
+
+                PIN_SLP(gpy1-0, INPUT, DOWN);
+                PIN_SLP(gpy1-1, INPUT, DOWN);
+                PIN_SLP(gpy1-2, INPUT, DOWN);
+                PIN_SLP(gpy1-3, INPUT, DOWN);
+
+                PIN_SLP(gpy2-0, PREV, NONE);
+                PIN_SLP(gpy2-1, INPUT, DOWN);
+                PIN_SLP(gpy2-2, INPUT, NONE);
+                PIN_SLP(gpy2-3, INPUT, NONE);
+                PIN_SLP(gpy2-4, INPUT, NONE);
+                PIN_SLP(gpy2-5, INPUT, NONE);
+
+                PIN_SLP(gpy3-0, INPUT, DOWN);
+                PIN_SLP(gpy3-1, INPUT, DOWN);
+                PIN_SLP(gpy3-2, INPUT, DOWN);
+                PIN_SLP(gpy3-3, INPUT, DOWN);
+                PIN_SLP(gpy3-4, INPUT, DOWN);
+                PIN_SLP(gpy3-5, INPUT, DOWN);
+                PIN_SLP(gpy3-6, INPUT, DOWN);
+                PIN_SLP(gpy3-7, INPUT, DOWN);
+
+                PIN_SLP(gpy4-0, INPUT, DOWN);
+                PIN_SLP(gpy4-1, INPUT, DOWN);
+                PIN_SLP(gpy4-2, INPUT, DOWN);
+                PIN_SLP(gpy4-3, INPUT, DOWN);
+                PIN_SLP(gpy4-4, INPUT, DOWN);
+                PIN_SLP(gpy4-5, INPUT, DOWN);
+                PIN_SLP(gpy4-6, INPUT, DOWN);
+                PIN_SLP(gpy4-7, INPUT, DOWN);
+
+                PIN_SLP(gpy5-0, INPUT, DOWN);
+                PIN_SLP(gpy5-1, INPUT, DOWN);
+                PIN_SLP(gpy5-2, INPUT, DOWN);
+                PIN_SLP(gpy5-3, INPUT, DOWN);
+                PIN_SLP(gpy5-4, INPUT, DOWN);
+                PIN_SLP(gpy5-5, INPUT, DOWN);
+                PIN_SLP(gpy5-6, INPUT, DOWN);
+                PIN_SLP(gpy5-7, INPUT, DOWN);
+
+                PIN_SLP(gpy6-0, INPUT, DOWN);
+                PIN_SLP(gpy6-1, INPUT, DOWN);
+                PIN_SLP(gpy6-2, INPUT, DOWN);
+                PIN_SLP(gpy6-3, INPUT, DOWN);
+                PIN_SLP(gpy6-4, INPUT, DOWN);
+                PIN_SLP(gpy6-5, INPUT, DOWN);
+                PIN_SLP(gpy6-6, INPUT, DOWN);
+                PIN_SLP(gpy6-7, INPUT, DOWN);
+        };
+};
+
+&pinctrl_2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep2>;
+
+        sleep2: sleep-states {
+                PIN_SLP(gpz-0, INPUT, DOWN);
+                PIN_SLP(gpz-1, INPUT, DOWN);
+                PIN_SLP(gpz-2, INPUT, DOWN);
+                PIN_SLP(gpz-3, INPUT, DOWN);
+                PIN_SLP(gpz-4, INPUT, DOWN);
+                PIN_SLP(gpz-5, INPUT, DOWN);
+                PIN_SLP(gpz-6, INPUT, DOWN);
+        };
+};
+
+&pinctrl_3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep3>;
+
+        sleep3: sleep-states {
+                PIN_SLP(gpv0-0, INPUT, DOWN);
+                PIN_SLP(gpv0-1, INPUT, DOWN);
+                PIN_SLP(gpv0-2, INPUT, DOWN);
+                PIN_SLP(gpv0-3, INPUT, DOWN);
+                PIN_SLP(gpv0-4, INPUT, DOWN);
+                PIN_SLP(gpv0-5, INPUT, DOWN);
+                PIN_SLP(gpv0-6, INPUT, DOWN);
+                PIN_SLP(gpv0-7, INPUT, DOWN);
+
+                PIN_SLP(gpv1-0, INPUT, DOWN);
+                PIN_SLP(gpv1-1, INPUT, DOWN);
+                PIN_SLP(gpv1-2, INPUT, DOWN);
+                PIN_SLP(gpv1-3, INPUT, DOWN);
+                PIN_SLP(gpv1-4, INPUT, DOWN);
+                PIN_SLP(gpv1-5, INPUT, DOWN);
+                PIN_SLP(gpv1-6, INPUT, DOWN);
+                PIN_SLP(gpv1-7, INPUT, DOWN);
+
+                PIN_SLP(gpv2-0, INPUT, DOWN);
+                PIN_SLP(gpv2-1, INPUT, DOWN);
+                PIN_SLP(gpv2-2, INPUT, DOWN);
+                PIN_SLP(gpv2-3, INPUT, DOWN);
+                PIN_SLP(gpv2-4, INPUT, DOWN);
+                PIN_SLP(gpv2-5, INPUT, DOWN);
+                PIN_SLP(gpv2-6, INPUT, DOWN);
+                PIN_SLP(gpv2-7, INPUT, DOWN);
+
+                PIN_SLP(gpv3-0, INPUT, DOWN);
+                PIN_SLP(gpv3-1, INPUT, DOWN);
+                PIN_SLP(gpv3-2, INPUT, DOWN);
+                PIN_SLP(gpv3-3, INPUT, DOWN);
+                PIN_SLP(gpv3-4, INPUT, DOWN);
+                PIN_SLP(gpv3-5, INPUT, DOWN);
+                PIN_SLP(gpv3-6, INPUT, DOWN);
+                PIN_SLP(gpv3-7, INPUT, DOWN);
+
+                PIN_SLP(gpv4-0, INPUT, DOWN);
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d8bc059e172f..0f6ec93bb1d8 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,6 +22,35 @@
 / {
         compatible = "samsung,exynos4412", "samsung,exynos4";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@A00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA00>;
+                };
+
+                cpu@A01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA01>;
+                };
+
+                cpu@A02 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA02>;
+                };
+
+                cpu@A03 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xA03>;
+                };
+        };
+
         combiner: interrupt-controller@10440000 {
                 samsung,combiner-nr = <20>;
         };
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
new file mode 100644
index 000000000000..75af9c56123e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
@@ -0,0 +1,573 @@
+/*
+ * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf2: gpf2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <0x2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb-0", "gpb-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb-2", "gpb-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpc1-3", "gpc1-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
+                samsung,pin-function = <5>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpd0-2", "gpd0-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_1 {
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk1: gpk1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk2: gpk2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk3: gpk3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl0: gpl0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm0: gpm0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm1: gpm1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm2: gpm2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm3: gpm3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm4: gpm4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
+                                <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
+                                <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_rdqs: sd0-rdqs {
+                samsung,pins = "gpk0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpk1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpk1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpk1-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpk1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpk2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <4>;
+        };
+
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpk2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <4>;
+        };
+
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpk2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpk2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <4>;
+        };
+
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <4>;
+        };
+
+        cam_port_b_io: cam-port-b-io {
+                samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+                                "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+                                "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        cam_port_b_clk_active: cam-port-b-clk-active {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        cam_port_b_clk_idle: cam-port-b-clk-idle {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        fimc_is_i2c0: fimc-is-i2c0 {
+                samsung,pins = "gpm4-0", "gpm4-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        fimc_is_i2c1: fimc-is-i2c1 {
+                samsung,pins = "gpm4-2", "gpm4-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        fimc_is_uart: fimc-is-uart {
+                samsung,pins = "gpm3-5", "gpm3-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_2 {
+        gpz: gpz {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        i2s0_bus: i2s0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4", "gpz-5", "gpz-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
new file mode 100644
index 000000000000..c1c9b37340d9
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -0,0 +1,604 @@
+/*
+ * Samsung's Exynos4415 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
+ * based board files can include this file and provide values for board
+ * specific bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos4415.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
+
+/ {
+        compatible = "samsung,exynos4415";
+        interrupt-parent = <&gic>;
+
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                mshc0 = &mshc_0;
+                mshc1 = &mshc_1;
+                mshc2 = &mshc_2;
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
+                i2c4 = &i2c_4;
+                i2c5 = &i2c_5;
+                i2c6 = &i2c_6;
+                i2c7 = &i2c_7;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@a00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa00>;
+                        clock-frequency = <1600000000>;
+                };
+
+                cpu1: cpu@a01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa01>;
+                        clock-frequency = <1600000000>;
+                };
+
+                cpu2: cpu@a02 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa02>;
+                        clock-frequency = <1600000000>;
+                };
+
+                cpu3: cpu@a03 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0xa03>;
+                        clock-frequency = <1600000000>;
+                };
+        };
+
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x50000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x50000>;
+
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
+
+                        smp-sysram@4f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x4f000 0x1000>;
+                        };
+                };
+
+                pinctrl_2: pinctrl@03860000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                        interrupts = <0 242 0>;
+                };
+
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
+
+                sysreg_system_controller: syscon@10010000 {
+                        compatible = "samsung,exynos4-sysreg", "syscon";
+                        reg = <0x10010000 0x400>;
+                };
+
+                pmu_system_controller: system-controller@10020000 {
+                        compatible = "samsung,exynos4415-pmu", "syscon";
+                        reg = <0x10020000 0x4000>;
+                };
+
+                mipi_phy: video-phy@10020710 {
+                        compatible = "samsung,s5pv210-mipi-video-phy";
+                        reg = <0x10020710 8>;
+                        #phy-cells = <1>;
+                };
+
+                pd_cam: cam-power-domain@10024000 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024000 0x20>;
+                };
+
+                pd_tv: tv-power-domain@10024020 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024020 0x20>;
+                };
+
+                pd_mfc: mfc-power-domain@10024040 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024040 0x20>;
+                };
+
+                pd_g3d: g3d-power-domain@10024060 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024060 0x20>;
+                };
+
+                pd_lcd0: lcd0-power-domain@10024080 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10024080 0x20>;
+                };
+
+                pd_isp0: isp0-power-domain@100240A0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100240A0 0x20>;
+                };
+
+                pd_isp1: isp1-power-domain@100240E0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100240E0 0x20>;
+                };
+
+                cmu: clock-controller@10030000 {
+                        compatible = "samsung,exynos4415-cmu";
+                        reg = <0x10030000 0x18000>;
+                        #clock-cells = <1>;
+                };
+
+                rtc: rtc@10070000 {
+                        compatible = "samsung,exynos3250-rtc";
+                        reg = <0x10070000 0x100>;
+                        interrupts = <0 73 0>, <0 74 0>;
+                        status = "disabled";
+                };
+
+                mct@10050000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x10050000 0x800>;
+                        interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
+                                     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+                        clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+                };
+
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x10481000 0x1000>,
+                              <0x10482000 0x1000>,
+                              <0x10484000 0x2000>,
+                              <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
+
+                l2c: l2-cache-controller@10502000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10502000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <2 2 1>;
+                        arm,data-latency = <3 2 1>;
+                        arm,double-linefill = <1>;
+                        arm,double-linefill-incr = <0>;
+                        arm,double-linefill-wrap = <1>;
+                        arm,prefetch-drop = <1>;
+                        arm,prefetch-offset = <7>;
+                };
+
+                cmu_dmc: clock-controller@105C0000 {
+                        compatible = "samsung,exynos4415-cmu-dmc";
+                        reg = <0x105C0000 0x3000>;
+                        #clock-cells = <1>;
+                };
+
+                pinctrl_1: pinctrl@11000000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x11000000 0x1000>;
+                        interrupts = <0 225 0>;
+
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 48 0>;
+                        };
+                };
+
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos4415-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <0 240 0>;
+                };
+
+                hsotg: hsotg@12480000 {
+                        compatible = "samsung,s3c6400-hsotg";
+                        reg = <0x12480000 0x20000>;
+                        interrupts = <0 141 0>;
+                        clocks = <&cmu CLK_USBDEVICE>;
+                        clock-names = "otg";
+                        phys = <&exynos_usbphy 0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+
+                mshc_0: mshc@12510000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12510000 0x1000>;
+                        interrupts = <0 142 0>;
+                        clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mshc_1: mshc@12520000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12520000 0x1000>;
+                        interrupts = <0 143 0>;
+                        clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                mshc_2: mshc@12530000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12530000 0x1000>;
+                        interrupts = <0 144 0>;
+                        clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                ehci: ehci@12580000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0x12580000 0x100>;
+                        interrupts = <0 140 0>;
+                        clocks = <&cmu CLK_USBHOST>;
+                        clock-names = "usbhost";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                phys = <&exynos_usbphy 2>;
+                                status = "disabled";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                phys = <&exynos_usbphy 3>;
+                                status = "disabled";
+                        };
+                };
+
+                ohci: ohci@12590000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0x12590000 0x100>;
+                        interrupts = <0 140 0>;
+                        clocks = <&cmu CLK_USBHOST>;
+                        clock-names = "usbhost";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                };
+
+                exynos_usbphy: exynos-usbphy@125B0000 {
+                        compatible = "samsung,exynos4x12-usb2-phy";
+                        reg = <0x125B0000 0x100>;
+                        samsung,pmureg-phandle = <&pmu_system_controller>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
+                        clock-names = "phy", "ref";
+                        #phy-cells = <1>;
+                        status = "disabled";
+                };
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&gic>;
+                        ranges;
+
+                        pdma0: pdma@12680000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12680000 0x1000>;
+                                interrupts = <0 138 0>;
+                                clocks = <&cmu CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        pdma1: pdma@12690000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12690000 0x1000>;
+                                interrupts = <0 139 0>;
+                                clocks = <&cmu CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+
+                adc: adc@126C0000 {
+                        compatible = "samsung,exynos3250-adc",
+                                     "samsung,exynos-adc-v2";
+                        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+                        interrupts = <0 137 0>;
+                        clock-names = "adc", "sclk";
+                        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        status = "disabled";
+                };
+
+                serial_0: serial@13800000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13800000 0x100>;
+                        interrupts = <0 109 0>;
+                        clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+
+                serial_1: serial@13810000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13810000 0x100>;
+                        interrupts = <0 110 0>;
+                        clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+
+                serial_2: serial@13820000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13820000 0x100>;
+                        interrupts = <0 111 0>;
+                        clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+
+                serial_3: serial@13830000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13830000 0x100>;
+                        interrupts = <0 112 0>;
+                        clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+
+                i2c_0: i2c@13860000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13860000 0x100>;
+                        interrupts = <0 113 0>;
+                        clocks = <&cmu CLK_I2C0>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_bus>;
+                        status = "disabled";
+                };
+
+                i2c_1: i2c@13870000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13870000 0x100>;
+                        interrupts = <0 114 0>;
+                        clocks = <&cmu CLK_I2C1>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_bus>;
+                        status = "disabled";
+                };
+
+                i2c_2: i2c@13880000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13880000 0x100>;
+                        interrupts = <0 115 0>;
+                        clocks = <&cmu CLK_I2C2>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_bus>;
+                        status = "disabled";
+                };
+
+                i2c_3: i2c@13890000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13890000 0x100>;
+                        interrupts = <0 116 0>;
+                        clocks = <&cmu CLK_I2C3>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_bus>;
+                        status = "disabled";
+                };
+
+                i2c_4: i2c@138A0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138A0000 0x100>;
+                        interrupts = <0 117 0>;
+                        clocks = <&cmu CLK_I2C4>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c4_bus>;
+                        status = "disabled";
+                };
+
+                i2c_5: i2c@138B0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138B0000 0x100>;
+                        interrupts = <0 118 0>;
+                        clocks = <&cmu CLK_I2C5>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c5_bus>;
+                        status = "disabled";
+                };
+
+                i2c_6: i2c@138C0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138C0000 0x100>;
+                        interrupts = <0 119 0>;
+                        clocks = <&cmu CLK_I2C6>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c6_bus>;
+                        status = "disabled";
+                };
+
+                i2c_7: i2c@138D0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138D0000 0x100>;
+                        interrupts = <0 120 0>;
+                        clocks = <&cmu CLK_I2C7>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c7_bus>;
+                        status = "disabled";
+                };
+
+                spi_0: spi@13920000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13920000 0x100>;
+                        interrupts = <0 121 0>;
+                        dmas = <&pdma0 7>, <&pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        status = "disabled";
+                };
+
+                spi_1: spi@13930000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13930000 0x100>;
+                        interrupts = <0 122 0>;
+                        dmas = <&pdma1 7>, <&pdma1 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        status = "disabled";
+                };
+
+                spi_2: spi@13940000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13940000 0x100>;
+                        interrupts = <0 123 0>;
+                        dmas = <&pdma0 9>, <&pdma0 8>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_bus>;
+                        status = "disabled";
+                };
+
+                clock_audss: clock-controller@03810000 {
+                        compatible = "samsung,exynos4210-audss-clock";
+                        reg = <0x03810000 0x0C>;
+                        #clock-cells = <1>;
+                };
+
+                i2s0: i2s@3830000 {
+                        compatible = "samsung,s5pv210-i2s";
+                        reg = <0x03830000 0x100>;
+                        interrupts = <0 124 0>;
+                        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_SCLK_I2S>;
+                        clock-names = "iis", "i2s_opclk0";
+                        dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
+                        dma-names = "tx", "rx", "tx-sec";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s0_bus>;
+                        samsung,idma-addr = <0x03000000>;
+                        status = "disabled";
+                };
+
+                pwm: pwm@139D0000 {
+                        compatible = "samsung,exynos4210-pwm";
+                        reg = <0x139D0000 0x1000>;
+                        interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+                                     <0 107 0>, <0 108 0>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
+                };
+        };
+};
+
+#include "exynos4415-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 0865a2e33f97..c141931378e7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -12,6 +12,22 @@
  * published by the Free Software Foundation.
 */
 
+#define PIN_PULL_NONE           0
+#define PIN_PULL_DOWN           1
+#define PIN_PULL_UP             3
+
+#define PIN_PDN_OUT0            0
+#define PIN_PDN_OUT1            1
+#define PIN_PDN_INPUT           2
+#define PIN_PDN_PREV            3
+
+#define PIN_SLP(_pin, _mode, _pull)                             \
+        _pin {                                                  \
+                samsung,pins = #_pin;                           \
+                samsung,pin-con-pdn = <PIN_PDN_ ##_mode>;       \
+                samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>;      \
+        }
+
 / {
         pinctrl@11400000 {
                 gpa0: gpa0 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 861bb919f6d3..2e9f1f7be77b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -271,4 +271,14 @@
                 compatible = "samsung,exynos4x12-usb2-phy";
                 samsung,sysreg-phandle = <&sys_reg>;
         };
+
+        tmu@100C0000 {
+                compatible = "samsung,exynos4412-tmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 4>;
+                reg = <0x100C0000 0x100>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3acd97eb6630..7e728a1b5559 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -7,12 +7,13 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 /dts-v1/;
-#include "exynos5250.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/input.h>
+#include "exynos5250.dtsi"
 
 / {
         model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -26,465 +27,52 @@
                 bootargs = "console=ttySAC2,115200";
         };
 
-        rtc@101E0000 {
-                status = "okay";
-        };
-
-        codec@11000000 {
-                samsung,mfc-r = <0x43000000 0x800000>;
-                samsung,mfc-l = <0x51000000 0x800000>;
-        };
-
-        i2c@12C60000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                samsung,i2c-slave-addr = <0x66>;
-                status = "okay";
-
-                s5m8767_pmic@66 {
-                        compatible = "samsung,s5m8767-pmic";
-                        reg = <0x66>;
-                        interrupt-parent = <&gpx3>;
-                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
-                        vinb1-supply = <&main_dc_reg>;
-                        vinb2-supply = <&main_dc_reg>;
-                        vinb3-supply = <&main_dc_reg>;
-                        vinb4-supply = <&main_dc_reg>;
-                        vinb5-supply = <&main_dc_reg>;
-                        vinb6-supply = <&main_dc_reg>;
-                        vinb7-supply = <&main_dc_reg>;
-                        vinb8-supply = <&main_dc_reg>;
-                        vinb9-supply = <&main_dc_reg>;
-
-                        vinl1-supply = <&buck7_reg>;
-                        vinl2-supply = <&buck7_reg>;
-                        vinl3-supply = <&buck7_reg>;
-                        vinl4-supply = <&main_dc_reg>;
-                        vinl5-supply = <&main_dc_reg>;
-                        vinl6-supply = <&main_dc_reg>;
-                        vinl7-supply = <&main_dc_reg>;
-                        vinl8-supply = <&buck8_reg>;
-                        vinl9-supply = <&buck8_reg>;
-
-                        s5m8767,pmic-buck2-dvs-voltage = <1300000>;
-                        s5m8767,pmic-buck3-dvs-voltage = <1100000>;
-                        s5m8767,pmic-buck4-dvs-voltage = <1200000>;
-                        s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
-                                                        <&gpd1 1 0>,
-                                                        <&gpd1 2 0>;
-                        s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
-                                                        <&gpx2 4 0>,
-                                                        <&gpx2 5 0>;
-                        regulators {
-                                ldo1_reg: LDO1 {
-                                        regulator-name = "VDD_ALIVE_1.0V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo2_reg: LDO2 {
-                                        regulator-name = "VDD_28IO_DP_1.35V";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo3_reg: LDO3 {
-                                        regulator-name = "VDD_COMMON1_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo4_reg: LDO4 {
-                                        regulator-name = "VDD_IOPERI_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo5_reg: LDO5 {
-                                        regulator-name = "VDD_EXT_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo6_reg: LDO6 {
-                                        regulator-name = "VDD_MPLL_1.1V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo7_reg: LDO7 {
-                                        regulator-name = "VDD_XPLL_1.1V";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo8_reg: LDO8 {
-                                        regulator-name = "VDD_COMMON2_1.0V";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo9_reg: LDO9 {
-                                        regulator-name = "VDD_33ON_3.0V";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        op_mode = <1>;
-                                };
-
-                                ldo10_reg: LDO10 {
-                                        regulator-name = "VDD_COMMON3_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo11_reg: LDO11 {
-                                        regulator-name = "VDD_ABB2_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo12_reg: LDO12 {
-                                        regulator-name = "VDD_USB_3.0V";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo13_reg: LDO13 {
-                                        regulator-name = "VDDQ_C2C_W_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo14_reg: LDO14 {
-                                        regulator-name = "VDD18_ABB0_3_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo15_reg: LDO15 {
-                                        regulator-name = "VDD10_COMMON4_1.0V";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo16_reg: LDO16 {
-                                        regulator-name = "VDD18_HSIC_1.8V";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo17_reg: LDO17 {
-                                        regulator-name = "VDDQ_MMC2_3_2.8V";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                ldo18_reg: LDO18 {
-                                        regulator-name = "VDD_33ON_2.8V";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        op_mode = <1>;
-                                };
-
-                                ldo22_reg: LDO22 {
-                                        regulator-name = "EXT_33_OFF";
-                                        regulator-min-microvolt = <3300000>;
-                                        regulator-max-microvolt = <3300000>;
-                                        op_mode = <1>;
-                                };
-
-                                ldo23_reg: LDO23 {
-                                        regulator-name = "EXT_28_OFF";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                        op_mode = <1>;
-                                };
-
-                                ldo25_reg: LDO25 {
-                                        regulator-name = "PVDD_LDO25";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        op_mode = <1>;
-                                };
-
-                                ldo26_reg: LDO26 {
-                                        regulator-name = "EXT_18_OFF";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        op_mode = <1>;
-                                };
-
-                                buck1_reg: BUCK1 {
-                                        regulator-name = "vdd_mif";
-                                        regulator-min-microvolt = <950000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck2_reg: BUCK2 {
-                                        regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <912500>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck3_reg: BUCK3 {
-                                        regulator-name = "vdd_int";
-                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck4_reg: BUCK4 {
-                                        regulator-name = "vdd_g3d";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck5_reg: BUCK5 {
-                                        regulator-name = "VDD_MEM_1.35V";
-                                        regulator-min-microvolt = <750000>;
-                                        regulator-max-microvolt = <1355000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck7_reg: BUCK7 {
-                                        regulator-name = "PVDD_BUCK7";
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck8_reg: BUCK8 {
-                                        regulator-name = "PVDD_BUCK8";
-                                        regulator-always-on;
-                                        op_mode = <1>;
-                                };
-
-                                buck9_reg: BUCK9 {
-                                        regulator-name = "VDD_33_OFF_EXT1";
-                                        regulator-min-microvolt = <750000>;
-                                        regulator-max-microvolt = <3000000>;
-                                        op_mode = <1>;
-                                };
-                        };
-                };
-        };
-
-        i2c@12C80000 {
-                status = "okay";
-
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                samsung,i2c-slave-addr = <0x50>;
-
-                hdmiddc@50 {
-                        compatible = "samsung,exynos4210-hdmiddc";
-                        reg = <0x50>;
-                };
-        };
-
-        i2c@12C90000 {
-                status = "okay";
-
-                wm1811a@1a {
-
-                        compatible = "wlf,wm1811";
-                        reg = <0x1a>;
-
-                        AVDD2-supply = <&main_dc_reg>;
-                        CPVDD-supply = <&main_dc_reg>;
-                        DBVDD1-supply = <&main_dc_reg>;
-                        DBVDD2-supply = <&main_dc_reg>;
-                        DBVDD3-supply = <&main_dc_reg>;
-                        LDO1VDD-supply = <&main_dc_reg>;
-                        SPKVDD1-supply = <&main_dc_reg>;
-                        SPKVDD2-supply = <&main_dc_reg>;
-
-                        wlf,ldo1ena = <&gpb0 0 0>;
-                        wlf,ldo2ena = <&gpb0 1 0>;
-                };
-        };
-
-        i2c@12CE0000 {
-                status = "okay";
-
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                samsung,i2c-slave-addr = <0x38>;
-
-                hdmiphy@38 {
-                        compatible = "samsung,exynos4212-hdmiphy";
-                        reg = <0x38>;
-                };
-        };
-
-        i2c@121D0000 {
-                status = "okay";
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <40000>;
-                samsung,i2c-slave-addr = <0x38>;
-
-                sata_phy_i2c:sata-phy@38 {
-                        compatible = "samsung,exynos-sataphy-i2c";
-                        reg = <0x38>;
-                };
-        };
-
-        sata@122F0000 {
-                status = "okay";
-        };
-
-        sata-phy@12170000 {
-                status = "okay";
-                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
-        };
-
-        mmc_0: mmc@12200000 {
-                status = "okay";
-                num-slots = <1>;
-                broken-cd;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                vmmc-supply = <&mmc_reg>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-                bus-width = <8>;
-                cap-mmc-highspeed;
-        };
-
-        mmc_2: mmc@12220000 {
-                status = "okay";
-                num-slots = <1>;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                vmmc-supply = <&mmc_reg>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-                bus-width = <4>;
-                disable-wp;
-                cap-sd-highspeed;
-        };
-
-        i2s0: i2s@03830000 {
-                status = "okay";
-        };
-
         gpio_keys {
                 compatible = "gpio-keys";
 
                 menu {
                         label = "SW-TACT2";
-                        gpios = <&gpx1 4 1>;
+                        gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_MENU>;
                         gpio-key,wakeup;
                 };
 
                 home {
                         label = "SW-TACT3";
-                        gpios = <&gpx1 5 1>;
+                        gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_HOME>;
                         gpio-key,wakeup;
                 };
 
                 up {
                         label = "SW-TACT4";
-                        gpios = <&gpx1 6 1>;
+                        gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_UP>;
                         gpio-key,wakeup;
                 };
 
                 down {
                         label = "SW-TACT5";
-                        gpios = <&gpx1 7 1>;
+                        gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_DOWN>;
                         gpio-key,wakeup;
                 };
 
                 back {
                         label = "SW-TACT6";
-                        gpios = <&gpx2 0 1>;
+                        gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_BACK>;
                         gpio-key,wakeup;
                 };
 
                 wakeup {
                         label = "SW-TACT7";
-                        gpios = <&gpx2 1 1>;
+                        gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_WAKEUP>;
                         gpio-key,wakeup;
                 };
         };
 
-        hdmi {
-                hpd-gpio = <&gpx3 7 2>;
-                vdd_osc-supply = <&ldo10_reg>;
-                vdd_pll-supply = <&ldo8_reg>;
-                vdd-supply = <&ldo8_reg>;
-        };
-
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -502,7 +90,7 @@
                         regulator-name = "VDD_33ON_2.8V";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpx1 1 1>;
+                        gpio = <&gpx1 1 GPIO_ACTIVE_LOW>;
                         enable-active-high;
                 };
 
@@ -520,46 +108,455 @@
                 };
         };
 
-        dp-controller@145B0000 {
-                samsung,color-space = <0>;
-                samsung,dynamic-range = <0>;
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
-                samsung,lane-count = <4>;
-                status = "okay";
+        // SMSC USB3503 connected in hardware only mode as a PHY
+        usb_hub: usb-hub {
+                compatible = "smsc,usb3503a";
+
+                reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
+                connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
         };
+};
 
-        fimd: fimd@14400000 {
-                status = "okay";
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: timing@0 {
-                                /* 2560x1600 DP panel */
-                                clock-frequency = <50000>;
-                                hactive = <2560>;
-                                vactive = <1600>;
-                                hfront-porch = <48>;
-                                hback-porch = <80>;
-                                hsync-len = <32>;
-                                vback-porch = <16>;
-                                vfront-porch = <8>;
-                                vsync-len = <6>;
-                        };
+&dp {
+        status = "okay";
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <4>;
+};
+
+&fimd {
+        status = "okay";
+
+        display-timings {
+                native-mode = <&timing0>;
+
+                timing0: timing@0 {
+                        /* 2560x1600 DP panel */
+                        clock-frequency = <50000>;
+                        hactive = <2560>;
+                        vactive = <1600>;
+                        hfront-porch = <48>;
+                        hback-porch = <80>;
+                        hsync-len = <32>;
+                        vback-porch = <16>;
+                        vfront-porch = <8>;
+                        vsync-len = <6>;
                 };
         };
+};
 
-        usb_hub_bus {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
+        vdd-supply = <&ldo8_reg>;
+};
+
+&i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <20000>;
+        samsung,i2c-slave-addr = <0x66>;
+
+        s5m8767_pmic@66 {
+                compatible = "samsung,s5m8767-pmic";
+                reg = <0x66>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+                vinb1-supply = <&main_dc_reg>;
+                vinb2-supply = <&main_dc_reg>;
+                vinb3-supply = <&main_dc_reg>;
+                vinb4-supply = <&main_dc_reg>;
+                vinb5-supply = <&main_dc_reg>;
+                vinb6-supply = <&main_dc_reg>;
+                vinb7-supply = <&main_dc_reg>;
+                vinb8-supply = <&main_dc_reg>;
+                vinb9-supply = <&main_dc_reg>;
+
+                vinl1-supply = <&buck7_reg>;
+                vinl2-supply = <&buck7_reg>;
+                vinl3-supply = <&buck7_reg>;
+                vinl4-supply = <&main_dc_reg>;
+                vinl5-supply = <&main_dc_reg>;
+                vinl6-supply = <&main_dc_reg>;
+                vinl7-supply = <&main_dc_reg>;
+                vinl8-supply = <&buck8_reg>;
+                vinl9-supply = <&buck8_reg>;
+
+                s5m8767,pmic-buck2-dvs-voltage = <1300000>;
+                s5m8767,pmic-buck3-dvs-voltage = <1100000>;
+                s5m8767,pmic-buck4-dvs-voltage = <1200000>;
+                s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
+                                              <&gpd1 1 GPIO_ACTIVE_HIGH>,
+                                              <&gpd1 2 GPIO_ACTIVE_HIGH>;
+                s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
+                                             <&gpx2 4 GPIO_ACTIVE_HIGH>,
+                                             <&gpx2 5 GPIO_ACTIVE_HIGH>;
+
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ALIVE_1.0V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
 
-                // SMSC USB3503 connected in hardware only mode as a PHY
-                usb_hub: usb_hub {
-                        compatible = "smsc,usb3503a";
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VDD_28IO_DP_1.35V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VDD_COMMON1_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VDD_IOPERI_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VDD_EXT_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VDD_MPLL_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
 
-                        reset-gpios = <&gpx3 5 1>;
-                        connect-gpios = <&gpd1 7 1>;
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VDD_XPLL_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VDD_COMMON2_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "VDD_33ON_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                op_mode = <1>;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "VDD_COMMON3_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "VDD_ABB2_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "VDD_USB_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "VDDQ_C2C_W_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "VDD18_ABB0_3_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "VDD10_COMMON4_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "VDD18_HSIC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "VDDQ_MMC2_3_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "VDD_33ON_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                op_mode = <1>;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                regulator-name = "EXT_33_OFF";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                op_mode = <1>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "EXT_28_OFF";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                op_mode = <1>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "PVDD_LDO25";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                op_mode = <1>;
+                        };
+
+                        ldo26_reg: LDO26 {
+                                regulator-name = "EXT_18_OFF";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                op_mode = <1>;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <912500>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VDD_MEM_1.35V";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1355000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck7_reg: BUCK7 {
+                                regulator-name = "PVDD_BUCK7";
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+
+                        buck8_reg: BUCK8 {
+                                regulator-name = "PVDD_BUCK8";
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "VDD_33_OFF_EXT1";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <3000000>;
+                                op_mode = <1>;
+                        };
                 };
         };
 };
+
+&i2c_2 {
+        status = "okay";
+
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x50>;
+
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
+        };
+};
+
+&i2c_3 {
+        status = "okay";
+
+        wm1811a@1a {
+                compatible = "wlf,wm1811";
+                reg = <0x1a>;
+
+                AVDD2-supply = <&main_dc_reg>;
+                CPVDD-supply = <&main_dc_reg>;
+                DBVDD1-supply = <&main_dc_reg>;
+                DBVDD2-supply = <&main_dc_reg>;
+                DBVDD3-supply = <&main_dc_reg>;
+                LDO1VDD-supply = <&main_dc_reg>;
+                SPKVDD1-supply = <&main_dc_reg>;
+                SPKVDD2-supply = <&main_dc_reg>;
+
+                wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>;
+                wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&i2c_8 {
+        status = "okay";
+
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x38>;
+
+        hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
+        };
+};
+
+&i2c_9 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <40000>;
+        samsung,i2c-slave-addr = <0x38>;
+
+        sata_phy_i2c:sata-phy@38 {
+                compatible = "samsung,exynos-sataphy-i2c";
+                reg = <0x38>;
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&mfc {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
+
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        vmmc-supply = <&mmc_reg>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        vmmc-supply = <&mmc_reg>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        bus-width = <4>;
+        disable-wp;
+        cap-sd-highspeed;
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+        samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6a0f4c0ff763..bc27cc2558fe 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -7,9 +7,11 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "exynos5250.dtsi"
 
 / {
@@ -27,165 +29,6 @@
                 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
         };
 
-        rtc@101E0000 {
-                status = "okay";
-        };
-
-        i2c@12C60000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                status = "okay";
-
-                eeprom@50 {
-                        compatible = "samsung,s524ad0xd1";
-                        reg = <0x50>;
-                };
-
-                max77686@09 {
-                        compatible = "maxim,max77686";
-                        reg = <0x09>;
-                        interrupt-parent = <&gpx3>;
-                        interrupts = <2 0>;
-
-                        voltage-regulators {
-                                ldo1_reg: LDO1 {
-                                        regulator-name = "P1.0V_LDO_OUT1";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                        regulator-always-on;
-                                };
-
-                                ldo2_reg: LDO2 {
-                                        regulator-name = "P1.2V_LDO_OUT2";
-                                        regulator-min-microvolt = <1200000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                };
-
-                                ldo3_reg: LDO3 {
-                                        regulator-name = "P1.8V_LDO_OUT3";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                };
-
-                                ldo4_reg: LDO4 {
-                                        regulator-name = "P2.8V_LDO_OUT4";
-                                        regulator-min-microvolt = <2800000>;
-                                        regulator-max-microvolt = <2800000>;
-                                };
-
-                                ldo5_reg: LDO5 {
-                                        regulator-name = "P1.8V_LDO_OUT5";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo6_reg: LDO6 {
-                                        regulator-name = "P1.1V_LDO_OUT6";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                };
-
-                                ldo7_reg: LDO7 {
-                                        regulator-name = "P1.1V_LDO_OUT7";
-                                        regulator-min-microvolt = <1100000>;
-                                        regulator-max-microvolt = <1100000>;
-                                        regulator-always-on;
-                                };
-
-                                ldo8_reg: LDO8 {
-                                        regulator-name = "P1.0V_LDO_OUT8";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                };
-
-                                ldo10_reg: LDO10 {
-                                        regulator-name = "P1.8V_LDO_OUT10";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo11_reg: LDO11 {
-                                        regulator-name = "P1.8V_LDO_OUT11";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo12_reg: LDO12 {
-                                        regulator-name = "P3.0V_LDO_OUT12";
-                                        regulator-min-microvolt = <3000000>;
-                                        regulator-max-microvolt = <3000000>;
-                                };
-
-                                ldo13_reg: LDO13 {
-                                        regulator-name = "P1.8V_LDO_OUT13";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo14_reg: LDO14 {
-                                        regulator-name = "P1.8V_LDO_OUT14";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                ldo15_reg: LDO15 {
-                                        regulator-name = "P1.0V_LDO_OUT15";
-                                        regulator-min-microvolt = <1000000>;
-                                        regulator-max-microvolt = <1000000>;
-                                };
-
-                                ldo16_reg: LDO16 {
-                                        regulator-name = "P1.8V_LDO_OUT16";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                };
-
-                                buck1_reg: BUCK1 {
-                                        regulator-name = "vdd_mif";
-                                        regulator-min-microvolt = <950000>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                buck2_reg: BUCK2 {
-                                        regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <850000>;
-                                        regulator-max-microvolt = <1350000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                buck3_reg: BUCK3 {
-                                        regulator-name = "vdd_int";
-                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                buck4_reg: BUCK4 {
-                                        regulator-name = "vdd_g3d";
-                                        regulator-min-microvolt = <850000>;
-                                        regulator-max-microvolt = <1300000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-
-                                buck5_reg: BUCK5 {
-                                        regulator-name = "P1.8V_BUCK_OUT5";
-                                        regulator-min-microvolt = <1800000>;
-                                        regulator-max-microvolt = <1800000>;
-                                        regulator-always-on;
-                                        regulator-boot-on;
-                                };
-                        };
-                };
-        };
-
         vdd: fixed-regulator@0 {
                 compatible = "regulator-fixed";
                 regulator-name = "vdd-supply";
@@ -210,199 +53,360 @@
                 regulator-always-on;
         };
 
-        i2c@12C70000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                status = "okay";
+        sound {
+                compatible = "samsung,smdk-wm8994";
 
-                eeprom@51 {
-                        compatible = "samsung,s524ad0xd1";
-                        reg = <0x51>;
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&wm8994>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
                 };
 
-                wm8994: wm8994@1a {
-                        compatible = "wlf,wm8994";
-                        reg = <0x1a>;
+                codec_mclk: codec-mclk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <16934000>;
+                };
+        };
+};
 
-                        gpio-controller;
-                        #gpio-cells = <2>;
+&dp {
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <4>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd>;
+        status = "okay";
+};
 
-                        clocks = <&codec_mclk>;
-                        clock-names = "MCLK1";
+&ehci {
+        samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+};
 
-                        AVDD2-supply = <&vdd>;
-                        CPVDD-supply = <&vdd>;
-                        DBVDD-supply = <&dbvdd>;
-                        SPKVDD1-supply = <&spkvdd>;
-                        SPKVDD2-supply = <&spkvdd>;
+&fimd {
+        status = "okay";
+
+        display-timings {
+                native-mode = <&timing0>;
+
+                timing0: timing@0 {
+                        /* 1280x800 */
+                        clock-frequency = <50000>;
+                        hactive = <1280>;
+                        vactive = <800>;
+                        hfront-porch = <4>;
+                        hback-porch = <4>;
+                        hsync-len = <4>;
+                        vback-porch = <4>;
+                        vfront-porch = <4>;
+                        vsync-len = <4>;
                 };
         };
+};
 
-        i2c@121D0000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <40000>;
-                samsung,i2c-slave-addr = <0x38>;
-                status = "okay";
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+};
 
-                sata_phy_i2c:sata-phy@38 {
-                        compatible = "samsung,exynos-sataphy-i2c";
-                        reg = <0x38>;
-                };
+&i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <20000>;
+
+        eeprom@50 {
+                compatible = "samsung,s524ad0xd1";
+                reg = <0x50>;
         };
 
-        i2c@12C80000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                status = "okay";
+        max77686@09 {
+                compatible = "maxim,max77686";
+                reg = <0x09>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_NONE>;
+
+                voltage-regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "P1.0V_LDO_OUT1";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
 
-                hdmiddc@50 {
-                        compatible = "samsung,exynos4210-hdmiddc";
-                        reg = <0x50>;
-                };
-        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "P1.2V_LDO_OUT2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
 
-        i2c@12CE0000 {
-                samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <66000>;
-                status = "okay";
+                        ldo3_reg: LDO3 {
+                                regulator-name = "P1.8V_LDO_OUT3";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
 
-                hdmiphy@38 {
-                        compatible = "samsung,exynos4212-hdmiphy";
-                        reg = <0x38>;
-                };
-        };
+                        ldo4_reg: LDO4 {
+                                regulator-name = "P2.8V_LDO_OUT4";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
 
-        sata@122F0000 {
-                status = "okay";
-        };
+                        ldo5_reg: LDO5 {
+                                regulator-name = "P1.8V_LDO_OUT5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
 
-        sata-phy@12170000 {
-                status = "okay";
-                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
-        };
+                        ldo6_reg: LDO6 {
+                                regulator-name = "P1.1V_LDO_OUT6";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
 
-        mmc@12200000 {
-                status = "okay";
-                num-slots = <1>;
-                broken-cd;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
-                bus-width = <8>;
-                cap-mmc-highspeed;
-        };
+                        ldo7_reg: LDO7 {
+                                regulator-name = "P1.1V_LDO_OUT7";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
 
-        mmc@12220000 {
-                status = "okay";
-                num-slots = <1>;
-                card-detect-delay = <200>;
-                samsung,dw-mshc-ciu-div = <3>;
-                samsung,dw-mshc-sdr-timing = <2 3>;
-                samsung,dw-mshc-ddr-timing = <1 2>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
-                bus-width = <4>;
-                disable-wp;
-                cap-sd-highspeed;
-        };
+                        ldo8_reg: LDO8 {
+                                regulator-name = "P1.0V_LDO_OUT8";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "P1.8V_LDO_OUT10";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
 
-        spi_1: spi@12d30000 {
-                cs-gpios = <&gpa2 5 0>;
-                status = "okay";
+                        ldo11_reg: LDO11 {
+                                regulator-name = "P1.8V_LDO_OUT11";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
 
-                w25q80bw@0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "w25x80";
-                        reg = <0>;
-                        spi-max-frequency = <1000000>;
+                        ldo12_reg: LDO12 {
+                                regulator-name = "P3.0V_LDO_OUT12";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
 
-                        controller-data {
-                                samsung,spi-feedback-delay = <0>;
+                        ldo13_reg: LDO13 {
+                                regulator-name = "P1.8V_LDO_OUT13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
                         };
 
-                        partition@0 {
-                                label = "U-Boot";
-                                reg = <0x0 0x40000>;
-                                read-only;
+                        ldo14_reg: LDO14 {
+                                regulator-name = "P1.8V_LDO_OUT14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
                         };
 
-                        partition@40000 {
-                                label = "Kernel";
-                                reg = <0x40000 0xc0000>;
+                        ldo15_reg: LDO15 {
+                                regulator-name = "P1.0V_LDO_OUT15";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "P1.8V_LDO_OUT16";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "P1.8V_BUCK_OUT5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
                         };
                 };
         };
+};
 
-        hdmi {
-                hpd-gpio = <&gpx3 7 0>;
-        };
+&i2c_1 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <20000>;
 
-        codec@11000000 {
-                samsung,mfc-r = <0x43000000 0x800000>;
-                samsung,mfc-l = <0x51000000 0x800000>;
+        eeprom@51 {
+                compatible = "samsung,s524ad0xd1";
+                reg = <0x51>;
         };
 
-        i2s0: i2s@03830000 {
-                status = "okay";
+        wm8994: wm8994@1a {
+                compatible = "wlf,wm8994";
+                reg = <0x1a>;
+
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                clocks = <&codec_mclk>;
+                clock-names = "MCLK1";
+
+                AVDD2-supply = <&vdd>;
+                CPVDD-supply = <&vdd>;
+                DBVDD-supply = <&dbvdd>;
+                SPKVDD1-supply = <&spkvdd>;
+                SPKVDD2-supply = <&spkvdd>;
         };
+};
 
-        sound {
-                compatible = "samsung,smdk-wm8994";
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
 
-                samsung,i2s-controller = <&i2s0>;
-                samsung,audio-codec = <&wm8994>;
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
         };
+};
+
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
 
-        usb@12110000 {
-                samsung,vbus-gpio = <&gpx2 6 0>;
+        hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
         };
+};
+
+&i2c_9 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <40000>;
+        samsung,i2c-slave-addr = <0x38>;
 
-        dp-controller@145B0000 {
-                samsung,color-space = <0>;
-                samsung,dynamic-range = <0>;
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
-                samsung,lane-count = <4>;
-
-                pinctrl-names = "default";
-                pinctrl-0 = <&dp_hpd>;
-                status = "okay";
+        sata_phy_i2c: sata-phy@38 {
+                compatible = "samsung,exynos-sataphy-i2c";
+                reg = <0x38>;
         };
+};
 
-        fimd@14400000 {
-                status = "okay";
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: timing@0 {
-                                /* 1280x800 */
-                                clock-frequency = <50000>;
-                                hactive = <1280>;
-                                vactive = <800>;
-                                hfront-porch = <4>;
-                                hback-porch = <4>;
-                                hsync-len = <4>;
-                                vback-porch = <4>;
-                                vfront-porch = <4>;
-                                vsync-len = <4>;
-                        };
+&i2s0 {
+        status = "okay";
+};
+
+&mfc {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
+
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        bus-width = <4>;
+        disable-wp;
+        cap-sd-highspeed;
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+        samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+};
+
+&spi_1 {
+        status = "okay";
+        cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
+
+        w25q80bw@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "w25x80";
+                reg = <0>;
+                spi-max-frequency = <1000000>;
+
+                controller-data {
+                        samsung,spi-feedback-delay = <0>;
                 };
-        };
 
-        fixed-rate-clocks {
-                xxti {
-                        compatible = "samsung,clock-xxti";
-                        clock-frequency = <24000000>;
+                partition@0 {
+                        label = "U-Boot";
+                        reg = <0x0 0x40000>;
+                        read-only;
                 };
 
-                codec_mclk: codec-mclk {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <16934000>;
+                partition@40000 {
+                        label = "Kernel";
+                        reg = <0x40000 0xc0000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 60429ad1c5d8..effaf2af41bc 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -6,10 +6,13 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/maxim,max77686.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
 #include "exynos5250.dtsi"
 
 / {
@@ -25,76 +28,7 @@
         };
 
         chosen {
-        };
-
-        rtc@101E0000 {
-                status = "okay";
-        };
-
-        pinctrl@11400000 {
-                ec_irq: ec-irq {
-                        samsung,pins = "gpx1-6";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                sd3_clk: sd3-clk {
-                        samsung,pin-drv = <0>;
-                };
-
-                sd3_cmd: sd3-cmd {
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-
-                sd3_bus4: sd3-bus-width4 {
-                        samsung,pin-drv = <0>;
-                };
-
-                max98095_en: max98095-en {
-                        samsung,pins = "gpx1-7";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-
-                tps65090_irq: tps65090-irq {
-                        samsung,pins = "gpx2-6";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                usb3_vbus_en: usb3-vbus-en {
-                        samsung,pins = "gpx2-7";
-                        samsung,pin-function = <1>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                hdmi_hpd_irq: hdmi-hpd-irq {
-                        samsung,pins = "gpx3-7";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <1>;
-                        samsung,pin-drv = <0>;
-                };
-        };
-
-        pinctrl@13400000 {
-                arb_their_claim: arb-their-claim {
-                        samsung,pins = "gpe0-4";
-                        samsung,pin-function = <0>;
-                        samsung,pin-pud = <3>;
-                        samsung,pin-drv = <0>;
-                };
-
-                arb_our_claim: arb-our-claim {
-                        samsung,pins = "gpf0-3";
-                        samsung,pin-function = <1>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
+                bootargs = "console=tty1";
         };
 
         gpio-keys {
@@ -102,14 +36,14 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpx1 3 1>;
-                        linux,code = <116>; /* KEY_POWER */
+                        gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
                         gpio-key,wakeup;
                 };
 
                 lid-switch {
                         label = "Lid";
-                        gpios = <&gpx3 5 1>;
+                        gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
                         linux,input-type = <5>; /* EV_SW */
                         linux,code = <0>; /* SW_LID */
                         debounce-interval = <1>;
@@ -130,8 +64,8 @@
 
                 i2c-parent = <&{/i2c@12CA0000}>;
 
-                our-claim-gpio = <&gpf0 3 1>;
-                their-claim-gpios = <&gpe0 4 1>;
+                our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
+                their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
                 slew-delay-us = <10>;
                 wait-retry-us = <3000>;
                 wait-free-us = <50000>;
@@ -154,7 +88,7 @@
                         cros_ec: embedded-controller {
                                 compatible = "google,cros-ec-i2c";
                                 reg = <0x1e>;
-                                interrupts = <6 0>;
+                                interrupts = <6 IRQ_TYPE_NONE>;
                                 interrupt-parent = <&gpx1>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&ec_irq>;
@@ -241,13 +175,6 @@
         };
 
         i2c@12CD0000 {
-                max98095: codec@11 {
-                        compatible = "maxim,max98095";
-                        reg = <0x11>;
-                        pinctrl-0 = <&max98095_en>;
-                        pinctrl-names = "default";
-                };
-
                 ptn3460: lvds-bridge@20 {
                         compatible = "nxp,ptn3460";
                         reg = <0x20>;
@@ -258,10 +185,6 @@
                 };
         };
 
-        i2s0: i2s@03830000 {
-                status = "okay";
-        };
-
         sound {
                 compatible = "google,snow-audio-max98095";
 
@@ -275,20 +198,12 @@
                 regulator-name = "P5.0V_USB3CON";
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
-                gpio = <&gpx2 7 0>;
+                gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&usb3_vbus_en>;
                 enable-active-high;
         };
 
-        phy@12100000 {
-                vbus-supply = <&usb3_vbus_reg>;
-        };
-
-        usb@12110000 {
-                samsung,vbus-gpio = <&gpx1 1 0>;
-        };
-
         fixed-rate-clocks {
                 xxti {
                         compatible = "samsung,clock-xxti";
@@ -296,18 +211,6 @@
                 };
         };
 
-        hdmi {
-                hpd-gpio = <&gpx3 7 0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&hdmi_hpd_irq>;
-                phy = <&hdmiphy>;
-                ddc = <&i2c_2>;
-                hdmi-en-supply = <&tps65090_fet7>;
-                vdd-supply = <&ldo8_reg>;
-                vdd_osc-supply = <&ldo10_reg>;
-                vdd_pll-supply = <&ldo8_reg>;
-        };
-
         backlight: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm 0 1000000 0>;
@@ -319,30 +222,46 @@
                 pinctrl-names = "default";
         };
 
-        fimd@14400000 {
-                status = "okay";
-                samsung,invert-vclk;
-        };
-
         panel: panel {
                 compatible = "auo,b116xw03";
                 power-supply = <&fet6>;
                 backlight = <&backlight>;
         };
+};
 
-        dp-controller@145B0000 {
-                status = "okay";
-                pinctrl-names = "default";
-                pinctrl-0 = <&dp_hpd>;
-                samsung,color-space = <0>;
-                samsung,dynamic-range = <0>;
-                samsung,ycbcr-coeff = <0>;
-                samsung,color-depth = <1>;
-                samsung,link-rate = <0x0a>;
-                samsung,lane-count = <2>;
-                samsung,hpd-gpio = <&gpx0 7 0>;
-                bridge = <&ptn3460>;
-        };
+&dp {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <2>;
+        samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+        bridge = <&ptn3460>;
+};
+
+&ehci {
+        samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+};
+
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        phy = <&hdmiphy>;
+        ddc = <&i2c_2>;
+        hdmi-en-supply = <&tps65090_fet7>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
 };
 
 &i2c_0 {
@@ -350,10 +269,10 @@
         samsung,i2c-sda-delay = <100>;
         samsung,i2c-max-bus-freq = <378000>;
 
-        max77686@09 {
+        max77686: max77686@09 {
                 compatible = "maxim,max77686";
                 interrupt-parent = <&gpx3>;
-                interrupts = <2 0>;
+                interrupts = <2 IRQ_TYPE_NONE>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&max77686_irq>;
                 wakeup-source;
@@ -503,7 +422,7 @@
         trackpad {
                 reg = <0x67>;
                 compatible = "cypress,cyapa";
-                interrupts = <2 0>;
+                interrupts = <2 IRQ_TYPE_NONE>;
                 interrupt-parent = <&gpx1>;
                 wakeup-source;
         };
@@ -550,6 +469,13 @@
         status = "okay";
         samsung,i2c-sda-delay = <100>;
         samsung,i2c-max-bus-freq = <66000>;
+
+        max98095: codec@11 {
+                compatible = "maxim,max98095";
+                reg = <0x11>;
+                pinctrl-0 = <&max98095_en>;
+                pinctrl-names = "default";
+        };
 };
 
 &i2c_8 {
@@ -563,6 +489,10 @@
         };
 };
 
+&i2s0 {
+        status = "okay";
+};
+
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
@@ -587,7 +517,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
         bus-width = <4>;
-        wp-gpios = <&gpc2 1 0>;
+        wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>;
         cap-sd-highspeed;
 };
 
@@ -610,12 +540,82 @@
 };
 
 &pinctrl_0 {
+        ec_irq: ec-irq {
+                samsung,pins = "gpx1-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        max98095_en: max98095-en {
+                samsung,pins = "gpx1-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        tps65090_irq: tps65090-irq {
+                samsung,pins = "gpx2-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        usb3_vbus_en: usb3-vbus-en {
+                samsung,pins = "gpx2-7";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
         max77686_irq: max77686-irq {
                 samsung,pins = "gpx3-2";
                 samsung,pin-function = <0>;
                 samsung,pin-pud = <0>;
                 samsung,pin-drv = <0>;
         };
+
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_1 {
+        arb_their_claim: arb-their-claim {
+                samsung,pins = "gpe0-4";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        arb_our_claim: arb-our-claim {
+                samsung,pins = "gpf0-3";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&rtc {
+        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+        clock-names = "rtc", "rtc_src";
+};
+
+&sd3_bus4 {
+        samsung,pin-drv = <0>;
+};
+
+&sd3_clk {
+        samsung,pin-drv = <0>;
+};
+
+&sd3_cmd {
+        samsung,pin-pud = <3>;
+        samsung,pin-drv = <0>;
 };
 
 &spi_1 {
@@ -628,4 +628,8 @@
         dr_mode = "host";
 };
 
+&usbdrd_phy {
+        vbus-supply = <&usb3_vbus_reg>;
+};
+
 #include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
new file mode 100644
index 000000000000..f02775487cd4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -0,0 +1,566 @@
+/*
+ * Google Spring board device tree source
+ *
+ * Copyright (c) 2013 Google, Inc
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include "exynos5250.dtsi"
+
+/ {
+        model = "Google Spring";
+        compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=tty1";
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&power_key_irq>, <&lid_irq>;
+
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+
+                lid-switch {
+                        label = "Lid";
+                        gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <0>; /* SW_LID */
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        usb-hub {
+                compatible = "smsc,usb3503a";
+                reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&hsic_reset>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
+
+&dp {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd_gpio>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <1>;
+        samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+};
+
+&ehci {
+        samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+};
+
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+
+&hdmi {
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        phy = <&hdmiphy>;
+        ddc = <&i2c_2>;
+        hdmi-en-supply = <&ldo8_reg>;
+        vdd-supply = <&ldo8_reg>;
+        vdd_osc-supply = <&ldo10_reg>;
+        vdd_pll-supply = <&ldo8_reg>;
+};
+
+&i2c_0 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
+        s5m8767-pmic@66 {
+                compatible = "samsung,s5m8767-pmic";
+                reg = <0x66>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <2 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>;
+                wakeup-source;
+
+                s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
+                                              <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
+                                              <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
+
+                s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
+                                             <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
+                                             <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
+
+                /*
+                 * The following arrays of DVS voltages are not used, since we are
+                 * not using GPIOs to control PMIC bucks, but they must be defined
+                 * to please the driver.
+                 */
+                s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
+                                                 <1250000>, <1200000>,
+                                                 <1150000>, <1100000>,
+                                                 <1000000>, <950000>;
+
+                s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                 <1100000>, <1100000>,
+                                                 <1000000>, <1000000>,
+                                                 <1000000>, <1000000>;
+
+                s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>;
+
+                clocks {
+                        compatible = "samsung,s5m8767-clk";
+                        #clock-cells = <1>;
+                        clock-output-names = "en32khz_ap",
+                                             "en32khz_cp",
+                                             "en32khz_bt";
+                };
+
+                regulators {
+                        ldo4_reg: LDO4 {
+                                regulator-name = "P1.0V_LDO_OUT4";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "P1.0V_LDO_OUT5";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "vdd_mydp";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "P1.1V_LDO_OUT7";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "P1.0V_LDO_OUT8";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "P1.8V_LDO_OUT10";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "P1.8V_LDO_OUT11";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "P3.0V_LDO_OUT12";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "P1.8V_LDO_OUT13";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "P1.8V_LDO_OUT14";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "P1.0V_LDO_OUT15";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "P1.8V_LDO_OUT16";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                op_mode = <3>;
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "P2.8V_LDO_OUT17";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                op_mode = <0>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "vdd_bridge";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                op_mode = <1>;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "P1.8V_BUCK_OUT5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <1>;
+                        };
+
+                        buck6_reg: BUCK6 {
+                                regulator-name = "P1.2V_BUCK_OUT6";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <0>;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "vdd_ummc";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                op_mode = <3>;
+                        };
+                };
+        };
+};
+
+&i2c_1 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
+        trackpad@4b {
+                compatible = "atmel,maxtouch";
+                reg = <0x4b>;
+                interrupt-parent = <&gpx1>;
+                interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&trackpad_irq>;
+                linux,gpio-keymap = <KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     KEY_RESERVED
+                                     BTN_LEFT>;
+                wakeup-source;
+        };
+};
+
+/*
+ * Disabled pullups since external part has its own pullups and
+ * double-pulling gets us out of spec in some cases.
+ */
+&i2c2_bus {
+        samsung,pin-pud = <0>;
+};
+
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+
+        hdmiddc@50 {
+                compatible = "samsung,exynos4210-hdmiddc";
+                reg = <0x50>;
+        };
+};
+
+&i2c_3 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_4 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+
+        cros_ec: embedded-controller {
+                compatible = "google,cros-ec-i2c";
+                reg = <0x1e>;
+                interrupts = <6 IRQ_TYPE_NONE>;
+                interrupt-parent = <&gpx1>;
+                wakeup-source;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ec_irq>;
+        };
+};
+
+&i2c_5 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+};
+
+&i2c_7 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+
+        temperature-sensor@4c {
+                compatible = "gmt,g781";
+                reg = <0x4c>;
+        };
+};
+
+&i2c_8 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <378000>;
+
+        hdmiphy: hdmiphy@38 {
+                compatible = "samsung,exynos4212-hdmiphy";
+                reg = <0x38>;
+        };
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&mfc {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
+
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
+
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+
+/*
+ * On Spring we've got SIP WiFi and so can keep drive strengths low to
+ * reduce EMI.
+ */
+&mmc_1 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
+
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+        };
+};
+
+&pinctrl_0 {
+        s5m8767_dvs: s5m8767-dvs {
+                samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+
+        dp_hpd_gpio: dp-hpd-gpio {
+                samsung,pins = "gpc3-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        trackpad_irq: trackpad-irq {
+                samsung,pins = "gpx1-2";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        power_key_irq: power-key-irq {
+                samsung,pins = "gpx1-3";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        ec_irq: ec-irq {
+                samsung,pins = "gpx1-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        s5m8767_ds: s5m8767-ds {
+                samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+
+        s5m8767_irq: s5m8767-irq {
+                samsung,pins = "gpx3-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        lid_irq: lid-irq {
+                samsung,pins = "gpx3-5";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pinctrl_1 {
+        hsic_reset: hsic-reset {
+                samsung,pins = "gpe1-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&sd1_bus4 {
+        samsung,pin-drv = <0>;
+};
+
+&sd1_cd {
+        samsung,pin-drv = <0>;
+};
+
+&sd1_clk {
+        samsung,pin-drv = <0>;
+};
+
+&sd1_cmd {
+        samsung,pin-pud = <3>;
+        samsung,pin-drv = <0>;
+};
+
+&spi_1 {
+        status = "okay";
+        samsung,spi-src-clk = <0>;
+        num-cs = <1>;
+};
+
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d55c1a2eb798..d45a07ea3402 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -218,7 +218,7 @@
                 clock-names = "fimg2d";
         };
 
-        codec@11000000 {
+        mfc: codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
@@ -227,7 +227,7 @@
                 clock-names = "mfc";
         };
 
-        rtc@101E0000 {
+        rtc: rtc@101E0000 {
                 clocks = <&clock CLK_RTC>;
                 clock-names = "rtc";
                 status = "disabled";
@@ -261,7 +261,7 @@
                 clock-names = "uart", "clk_uart_baud0";
         };
 
-        sata@122F0000 {
+        sata: sata@122F0000 {
                 compatible = "snps,dwc-ahci";
                 samsung,sata-freq = <66>;
                 reg = <0x122F0000 0x1ff>;
@@ -293,6 +293,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c0_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -306,6 +307,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c1_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -319,6 +321,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c2_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -332,6 +335,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c3_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -573,7 +577,7 @@
                 #phy-cells = <1>;
         };
 
-        usb@12110000 {
+        ehci: usb@12110000 {
                 compatible = "samsung,exynos4210-ehci";
                 reg = <0x12110000 0x100>;
                 interrupts = <0 71 0>;
@@ -588,7 +592,7 @@
                 };
         };
 
-        usb@12120000 {
+        ohci: usb@12120000 {
                 compatible = "samsung,exynos4210-ohci";
                 reg = <0x12120000 0x100>;
                 interrupts = <0 71 0>;
@@ -710,7 +714,7 @@
                 clock-names = "gscl";
         };
 
-        hdmi {
+        hdmi: hdmi {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
@@ -736,14 +740,14 @@
                 #phy-cells = <0>;
         };
 
-        dp-controller@145B0000 {
+        dp: dp-controller@145B0000 {
                 clocks = <&clock CLK_DP>;
                 clock-names = "dp";
                 phys = <&dp_phy>;
                 phy-names = "dp";
         };
 
-        fimd@14400000 {
+        fimd: fimd@14400000 {
                 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                 clock-names = "sclk_fimd", "fimd";
         };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 82cdb74484cc..9a050e19a4dc 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -12,6 +12,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77802.h>
 #include "exynos5420.dtsi"
 
 / {
@@ -151,7 +152,7 @@
         status = "okay";
         clock-frequency = <400000>;
 
-        max77802-pmic@9 {
+        max77802: max77802-pmic@9 {
                 compatible = "maxim,max77802";
                 interrupt-parent = <&gpx3>;
                 interrupts = <1 IRQ_TYPE_NONE>;
@@ -560,7 +561,7 @@
         status = "okay";
         num-slots = <1>;
         broken-cd;
-        caps2-mmc-hs200-1_8v;
+        mmc-hs200-1_8v;
         cap-mmc-highspeed;
         non-removable;
         card-detect-delay = <200>;
@@ -727,6 +728,8 @@
 
 &rtc {
         status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+        clock-names = "rtc", "rtc_src";
 };
 
 &spi_2 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8617a031cbc0..90bf4011e319 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -560,6 +560,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c0_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -573,6 +574,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c1_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -586,6 +588,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c2_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
@@ -599,6 +602,7 @@
                 clock-names = "i2c";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c3_bus>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7bb1c8dd42dd..e8fdda827fc9 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77802.h>
 #include "exynos5800.dtsi"
 
 / {
@@ -150,7 +151,7 @@
         status = "okay";
         clock-frequency = <400000>;
 
-        max77802-pmic@9 {
+        max77802: max77802-pmic@9 {
                 compatible = "maxim,max77802";
                 interrupt-parent = <&gpx3>;
                 interrupts = <1 IRQ_TYPE_NONE>;
@@ -548,7 +549,7 @@
         status = "okay";
         num-slots = <1>;
         broken-cd;
-        caps2-mmc-hs200-1_8v;
+        mmc-hs200-1_8v;
         cap-mmc-highspeed;
         non-removable;
         card-detect-delay = <200>;
@@ -715,6 +716,8 @@
 
 &rtc {
         status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+        clock-names = "rtc", "rtc_src";
 };
 
 &spi_2 {
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 05b44c272c9a..721b09238f58 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,3 +51,36 @@
 &uart0 {
         status = "okay";
 };
+
+&gmac0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy-handle = <&phy2>;
+        phy-mode = "mii";
+        /* Placeholder, overwritten by bootloader */
+        mac-address = [00 00 00 00 00 00];
+        status = "okay";
+
+        phy2: ethernet-phy@2 {
+                reg = <2>;
+        };
+};
+
+&gmac1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy-handle = <&phy1>;
+        phy-mode = "rgmii";
+        /* Placeholder, overwritten by bootloader */
+        mac-address = [00 00 00 00 00 00];
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
+&ahci {
+        phys = <&sata_phy>;
+        phy-names = "sata-phy";
+};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index f85ba2924ff7..c52722b14e4a 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,6 +131,249 @@
                                 clock-names = "apb_pclk";
                                 status = "disabled";
                         };
+
+                        gpio0: gpio@b20000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb20000 0x1000>;
+                                interrupts = <0 108 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio1: gpio@b21000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb21000 0x1000>;
+                                interrupts = <0 109 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio2: gpio@b22000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb22000 0x1000>;
+                                interrupts = <0 110 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio3: gpio@b23000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb23000 0x1000>;
+                                interrupts = <0 111 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio4: gpio@b24000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb24000 0x1000>;
+                                interrupts = <0 112 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio5: gpio@004000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0x004000 0x1000>;
+                                interrupts = <0 113 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio6: gpio@b26000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb26000 0x1000>;
+                                interrupts = <0 114 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio7: gpio@b27000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb27000 0x1000>;
+                                interrupts = <0 115 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio8: gpio@b28000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb28000 0x1000>;
+                                interrupts = <0 116 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio9: gpio@b29000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb29000 0x1000>;
+                                interrupts = <0 117 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio10: gpio@b2a000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2a000 0x1000>;
+                                interrupts = <0 118 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio11: gpio@b2b000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2b000 0x1000>;
+                                interrupts = <0 119 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio12: gpio@b2c000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2c000 0x1000>;
+                                interrupts = <0 120 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio13: gpio@b2d000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2d000 0x1000>;
+                                interrupts = <0 121 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio14: gpio@b2e000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2e000 0x1000>;
+                                interrupts = <0 122 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio15: gpio@b2f000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb2f000 0x1000>;
+                                interrupts = <0 123 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio16: gpio@b30000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb30000 0x1000>;
+                                interrupts = <0 124 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio17: gpio@b31000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xb31000 0x1000>;
+                                interrupts = <0 125 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                clocks = <&clock HIX5HD2_FIXED_100M>;
+                                clock-names = "apb_pclk";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        wdt0: watchdog@a2c000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                arm,primecell-periphid = <0x00141805>;
+                                reg = <0xa2c000 0x1000>;
+                                interrupts = <0 29 4>;
+                                clocks = <&clock HIX5HD2_WDG0_RST>;
+                                clock-names = "apb_pclk";
+                        };
                 };
 
                 local_timer@00a00600 {
@@ -148,9 +391,15 @@
                 };
 
                 sysctrl: system-controller@00000000 {
-                        compatible = "hisilicon,sysctrl";
+                        compatible = "hisilicon,sysctrl", "syscon";
                         reg = <0x00000000 0x1000>;
-                        reboot-offset = <0x4>;
+                };
+
+                reboot {
+                        compatible = "syscon-reboot";
+                        regmap = <&sysctrl>;
+                        offset = <0x4>;
+                        mask = <0xdeadbeef>;
                 };
 
                 cpuctrl@00a22000 {
@@ -166,5 +415,142 @@
                                 #clock-cells = <1>;
                         };
                 };
+
+                /* unremovable emmc as mmcblk0 */
+                mmc: mmc@1830000 {
+                        compatible = "snps,dw-mshc";
+                        reg = <0x1830000 0x1000>;
+                        interrupts = <0 35 4>;
+                        clocks = <&clock HIX5HD2_MMC_CIU_RST>,
+                                 <&clock HIX5HD2_MMC_BIU_CLK>;
+                        clock-names = "ciu", "biu";
+                };
+
+                sd: mmc@1820000 {
+                        compatible = "snps,dw-mshc";
+                        reg = <0x1820000 0x1000>;
+                        interrupts = <0 34 4>;
+                        clocks = <&clock HIX5HD2_SD_CIU_RST>,
+                                 <&clock HIX5HD2_SD_BIU_CLK>;
+                        clock-names = "ciu","biu";
+                };
+
+                gmac0: ethernet@1840000 {
+                        compatible = "hisilicon,hix5hd2-gmac";
+                        reg = <0x1840000 0x1000>,<0x184300c 0x4>;
+                        interrupts = <0 71 4>;
+                        clocks = <&clock HIX5HD2_MAC0_CLK>;
+                        status = "disabled";
+                };
+
+                gmac1: ethernet@1841000 {
+                        compatible = "hisilicon,hix5hd2-gmac";
+                        reg = <0x1841000 0x1000>,<0x1843010 0x4>;
+                        interrupts = <0 72 4>;
+                        clocks = <&clock HIX5HD2_MAC1_CLK>;
+                        status = "disabled";
+                };
+
+                usb0: ehci@1890000 {
+                        compatible = "generic-ehci";
+                        reg = <0x1890000 0x1000>;
+                        interrupts = <0 66 4>;
+                        clocks = <&clock HIX5HD2_USB_CLK>;
+                };
+
+                usb1: ohci@1880000 {
+                        compatible = "generic-ohci";
+                        reg = <0x1880000 0x1000>;
+                        interrupts = <0 67 4>;
+                        clocks = <&clock HIX5HD2_USB_CLK>;
+                };
+
+                peripheral_ctrl: syscon@a20000 {
+                        compatible = "syscon";
+                        reg = <0xa20000 0x1000>;
+                };
+
+                sata_phy: phy@1900000 {
+                        compatible = "hisilicon,hix5hd2-sata-phy";
+                        reg = <0x1900000 0x10000>;
+                        #phy-cells = <0>;
+                        hisilicon,peripheral-syscon = <&peripheral_ctrl>;
+                        hisilicon,power-reg = <0x8 10>;
+                };
+
+                ahci: sata@1900000 {
+                        compatible = "hisilicon,hisi-ahci";
+                        reg = <0x1900000 0x10000>;
+                        interrupts = <0 70 4>;
+                        clocks = <&clock HIX5HD2_SATA_CLK>;
+                };
+
+                ir: ir@001000 {
+                        compatible = "hisilicon,hix5hd2-ir";
+                        reg = <0x001000 0x1000>;
+                        interrupts = <0 47 4>;
+                        clocks = <&clock HIX5HD2_FIXED_24M>;
+                        hisilicon,power-syscon = <&sysctrl>;
+                };
+
+                i2c0: i2c@b10000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb10000 0x1000>;
+                        interrupts = <0 38 4>;
+                        clocks = <&clock HIX5HD2_I2C0_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@b11000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb11000 0x1000>;
+                        interrupts = <0 39 4>;
+                        clocks = <&clock HIX5HD2_I2C1_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@b12000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb12000 0x1000>;
+                        interrupts = <0 40 4>;
+                        clocks = <&clock HIX5HD2_I2C2_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@b13000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb13000 0x1000>;
+                        interrupts = <0 41 4>;
+                        clocks = <&clock HIX5HD2_I2C3_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@b16000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb16000 0x1000>;
+                        interrupts = <0 43 4>;
+                        clocks = <&clock HIX5HD2_I2C4_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c5: i2c@b17000 {
+                        compatible = "hisilicon,hix5hd2-i2c";
+                        reg = <0xb17000 0x1000>;
+                        interrupts = <0 44 4>;
+                        clocks = <&clock HIX5HD2_I2C5_RST>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 92660e1fe1fc..c0116cffc513 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -214,7 +214,9 @@
                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                         reg = <0x70014000 0x4000>;
                                         interrupts = <30>;
-                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 24 1 0>,
                                                <&sdma 25 1 0>;
                                         dma-names = "rx", "tx";
@@ -504,7 +506,9 @@
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fcc000 0x4000>;
                                 interrupts = <29>;
-                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                 dmas = <&sdma 28 0 0>,
                                        <&sdma 29 0 0>;
                                 dma-names = "rx", "tx";
@@ -560,7 +564,9 @@
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fe8000 0x4000>;
                                 interrupts = <96>;
-                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                 dmas = <&sdma 46 0 0>,
                                        <&sdma 47 0 0>;
                                 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index f91725b2e8ab..a30bddfdbdb6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -46,10 +46,21 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a8";
                         reg = <0x0>;
+                        clocks = <&clks IMX5_CLK_ARM>;
+                        clock-latency = <61036>;
+                        voltage-tolerance = <5>;
+                        operating-points = <
+                                /* kHz */
+                                 166666  850000
+                                 400000  900000
+                                 800000 1050000
+                                1000000 1200000
+                                1200000 1300000
+                        >;
                 };
         };
 
@@ -227,7 +238,9 @@
                                                         "fsl,imx21-ssi";
                                         reg = <0x50014000 0x4000>;
                                         interrupts = <30>;
-                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+                                        clock-names = "ipg", "baud";
                                         dmas = <&sdma 24 1 0>,
                                                <&sdma 25 1 0>;
                                         dma-names = "rx", "tx";
@@ -675,7 +688,9 @@
                                                 "fsl,imx21-ssi";
                                 reg = <0x63fcc000 0x4000>;
                                 interrupts = <29>;
-                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                 dmas = <&sdma 28 0 0>,
                                        <&sdma 29 0 0>;
                                 dma-names = "rx", "tx";
@@ -703,7 +718,9 @@
                                                 "fsl,imx21-ssi";
                                 reg = <0x63fe8000 0x4000>;
                                 interrupts = <96>;
-                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+                                         <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+                                clock-names = "ipg", "baud";
                                 dmas = <&sdma 46 0 0>,
                                        <&sdma 47 0 0>;
                                 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b453e0e28aee..1ac2fe732867 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -13,6 +13,10 @@
 #include "imx6qdl.dtsi"
 
 / {
+        aliases {
+                i2c3 = &i2c4;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -114,3 +118,7 @@
                       "di0_sel", "di1_sel",
                       "di0", "di1";
 };
+
+&vpu {
+        compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
new file mode 100644
index 000000000000..a43abfa21e33
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2014 Soeren Moch <smoch@web.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "TBS2910 Matrix ARM mini PC";
+        compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+
+        fan {
+                compatible = "gpio-fan";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_fan>;
+                gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1>;
+        };
+
+        ir_recv {
+                compatible = "gpio-ir-receiver";
+                gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ir>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+
+                blue {
+                        label = "blue_status_led";
+                        gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "keep";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reg_2p5v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                };
+
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+
+                reg_5p0v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "5P0V";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
+
+        sound-sgtl5000 {
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "On-board Codec";
+                mux-ext-port = <3>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
+
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif";
+                model = "On-board SPDIF";
+                spdif-controller = <&spdif>;
+                spdif-out;
+        };
+};
+
+&audmux {
+        status = "okay";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        sgtl5000: sgtl5000@0a {
+                clocks = <&clks 201>;
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_sgtl5000>;
+                reg = <0x0a>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+
+        rtc: ds1307@68 {
+                compatible = "dallas,ds1307";
+                reg = <0x68>;
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spdif>;
+        status = "okay";
+};
+
+&ssi1 {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_5p0v>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_5p0v>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        no-1-8-v;
+        status = "okay";
+};
+
+&iomuxc {
+        imx6q-tbs2910 {
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
+                        >;
+                };
+
+                pinctrl_hdmi: hdmigrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                        >;
+                };
+
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
+                                MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
+                        >;
+                };
+
+                pinctrl_ir: irgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
+                        >;
+                };
+
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
+                        >;
+                };
+
+                pinctrl_sgtl5000: sgtl5000grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
+                        >;
+                };
+
+                pinctrl_spdif: spdifgrp {
+                        fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
+                        >;
+                };
+
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
+                        >;
+                };
+
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
+                        >;
+                };
+
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
+                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
+                        >;
+                };
+
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
+                        >;
+                };
+        };
+
+        gpio_fan {
+                pinctrl_gpio_fan: gpiofangrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
+                        >;
+                };
+        };
+
+        gpio_leds {
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646d1760..85f72e6b5bad 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -308,3 +308,7 @@
                 };
         };
 };
+
+&vpu {
+        compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..585b4f6986c1 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,17 +9,103 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
 / {
         chosen {
                 linux,stdout-path = &uart4;
         };
+
+        regulators {
+                sound_1v8: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "i2s-audio-1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+
+                sound_3v3: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "i2s-audio-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+        };
+
+        tlv320_mclk: oscillator {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <19200000>;
+                clock-output-names = "tlv320-mclk";
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "OnboardTLV320AIC3007";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink_master>;
+                simple-audio-card,frame-master = <&dailink_master>;
+                simple-audio-card,widgets =
+                        "Microphone", "Mic Jack",
+                        "Line", "Line In",
+                        "Line", "Line Out",
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Line Out", "LLOUT",
+                        "Line Out", "RLOUT",
+                        "Speaker", "SPOP",
+                        "Speaker", "SPOM",
+                        "Headphone Jack", "HPLOUT",
+                        "Headphone Jack", "HPROUT",
+                        "MIC3L", "Mic Jack",
+                        "MIC3R", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "LINE1L", "Line In",
+                        "LINE1R", "Line In";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&ssi2>;
+                };
+
+                dailink_master: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                        clocks = <&tlv320_mclk>;
+                };
+        };
+
 };
 
-&fec {
+&audmux {
         status = "okay";
+
+        ssi2 {
+                fsl,audmux-port = <1>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                        IMX_AUDMUX_V2_PTCR_TFSEL(4) |
+                        IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_TCSEL(4))
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+                >;
+        };
+
+        pins5 {
+                fsl,audmux-port = <4>;
+                fsl,port-config = <
+                        0x00000000
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(1)
+                >;
+        };
 };
 
-&gpmi {
+&can1 {
+        status = "okay";
+};
+
+&fec {
         status = "okay";
 };
 
@@ -28,14 +114,18 @@
 };
 
 &i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2>;
-        clock-frequency = <100000>;
         status = "okay";
 
-        tlv320@18 {
-                compatible = "ti,tlv320aic3x";
+        codec: tlv320@18 {
+                compatible = "ti,tlv320aic3007";
+                #sound-dai-cells = <0>;
                 reg = <0x18>;
+                ai3x-micbias-vg = <2>;
+
+                AVDD-supply = <&sound_3v3>;
+                IOVDD-supply = <&sound_3v3>;
+                DRVDD-supply = <&sound_3v3>;
+                DVDD-supply = <&sound_1v8>;
         };
 
         stmpe@41 {
@@ -55,9 +145,14 @@
 };
 
 &i2c3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c3>;
-        clock-frequency = <100000>;
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&ssi2 {
         status = "okay";
 };
 
@@ -84,19 +179,3 @@
 &usdhc3 {
         status = "okay";
 };
-
-&iomuxc {
-        pinctrl_i2c2: i2c2grp {
-                fsl,pins = <
-                        MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
-                        MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
-                >;
-        };
-
-        pinctrl_i2c3: i2c3grp {
-                fsl,pins = <
-                        MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
-                        MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
-                >;
-        };
-};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..19cc269a08d4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,18 @@
         };
 };
 
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "disabled";
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        status = "disabled";
+};
+
 &ecspi3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_ecspi3>;
@@ -72,6 +84,22 @@
         };
 };
 
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+        phy-supply = <&vdd_eth_io_reg>;
+        status = "disabled";
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "okay";
+};
+
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c1>;
@@ -85,8 +113,8 @@
         pmic@58 {
                 compatible = "dlg,da9063";
                 reg = <0x58>;
-                interrupt-parent = <&gpio4>;
-                interrupts = <17 0x8>; /* active-low GPIO4_17 */
+                interrupt-parent = <&gpio2>;
+                interrupts = <9 0x8>; /* active-low GPIO2_9 */
 
                 regulators {
                         vddcore_reg: bcore1 {
@@ -162,6 +190,18 @@
         };
 };
 
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <100000>;
+};
+
 &iomuxc {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
@@ -171,7 +211,7 @@
                         fsl,pins = <
                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
-                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
+                                MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
                         >;
@@ -206,6 +246,13 @@
                         >;
                 };
 
+                pinctrl_flexcan1: flexcan1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
+                        >;
+                };
+
                 pinctrl_gpmi_nand: gpminandgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
@@ -235,6 +282,24 @@
                         >;
                 };
 
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
+                        >;
+                };
+
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
+                        >;
+                };
+
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
+                };
+
                 pinctrl_uart3: uart3grp {
                         fsl,pins = <
                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
@@ -293,22 +358,22 @@
                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
                         >;
                 };
-        };
-};
 
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
-        phy-supply = <&vdd_eth_io_reg>;
-        status = "disabled";
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
+                                MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
+                                MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
+                        >;
+                };
+        };
 };
 
-&gpmi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand>;
-        nand-on-flash-bbt;
+&pcie {
+        pinctrl-name = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio4 17 0>;
         status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 5db4a2417d94..f1cd2147421d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -529,6 +529,10 @@
         status = "okay";
 };
 
+&snvs_poweroff {
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5867e6..4fc03b7f1cee 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -333,9 +333,17 @@
                         };
 
                         vpu: vpu@02040000 {
+                                compatible = "cnm,coda960";
                                 reg = <0x02040000 0x3c000>;
                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "bit", "jpeg";
+                                clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+                                         <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+                                         <&clks IMX6QDL_CLK_OCRAM>;
+                                clock-names = "per", "ahb", "ocram";
+                                resets = <&src 1>;
+                                iram = <&ocram>;
                         };
 
                         aipstz@0207c000 { /* AIPSTZ1 */
@@ -657,6 +665,12 @@
                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                 };
+
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                         };
 
                         epit1: epit@020d0000 { /* EPIT1 */
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 898d14fd765f..fda4932faefd 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -580,6 +580,10 @@
         status = "okay";
 };
 
+&snvs_poweroff {
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index dfd83e6d8087..36ab8e054cee 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -574,6 +574,12 @@
                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                 };
+
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                         };
 
                         epit1: epit@020d0000 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34527b7..1e6e5cc1c14c 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -105,6 +105,30 @@
                         gpio = <&gpio3 27 0>;
                         enable-active-high;
                 };
+
+                reg_peri_3v3: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_peri_3v3>;
+                        regulator-name = "peri_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+
+                reg_enet_3v3: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_enet_3v3>;
+                        regulator-name = "enet_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                };
         };
 
         sound {
@@ -133,6 +157,14 @@
 &fec1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet1>;
+        phy-supply = <&reg_enet_3v3>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
         phy-mode = "rgmii";
         status = "okay";
 };
@@ -304,6 +336,10 @@
         status = "okay";
 };
 
+&snvs_poweroff {
+        status = "okay";
+};
+
 &ssi2 {
         status = "okay";
 };
@@ -394,6 +430,30 @@
                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
+                        >;
+                };
+
+                pinctrl_enet_3v3: enet3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
+                        >;
+                };
+
+                pinctrl_enet2: enet2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
                         >;
                 };
 
@@ -452,6 +512,12 @@
                         >;
                 };
 
+                pinctrl_peri_3v3: peri3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
+                        >;
+                };
+
                 pinctrl_pwm3: pwm3grp-1 {
                         fsl,pins = <
                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f3e88c03b1e4..7a24fee1e7ae 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -671,6 +671,12 @@
                                         reg = <0x34 0x58>;
                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                                 };
+
+                                snvs_poweroff: snvs-poweroff@38 {
+                                        compatible = "fsl,sec-v4.0-poweroff";
+                                        reg = <0x38 0x4>;
+                                        status = "disabled";
+                                };
                         };
 
                         epit1: epit@020d0000 {
@@ -877,7 +883,7 @@
                         };
 
                         fec2: ethernet@021b4000 {
-                                compatible = "fsl,imx6sx-fec";
+                                compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
                                 reg = <0x021b4000 0x4000>;
                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
index c568f067604d..560d62150ade 100644
--- a/arch/arm/boot/dts/k2e-evm.dts
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -139,3 +139,15 @@
                 };
         };
 };
+
+&mdio {
+        ethphy0: ethernet-phy@0 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index c358b4b9a073..5fc14683d6df 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -85,6 +85,51 @@
                         #gpio-cells = <2>;
                         gpio,syscon-dev = <&devctrl 0x240>;
                 };
+
+                pcie@21020000 {
+                        compatible = "ti,keystone-pcie","snps,dw-pcie";
+                        clocks = <&clkpcie1>;
+                        clock-names = "pcie";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+                        ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
+                                0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+
+                        device_type = "pci";
+                        num-lanes = <2>;
+
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
+                                        <0 0 0 2 &pcie_intc1 1>, /* INT B */
+                                        <0 0 0 3 &pcie_intc1 2>, /* INT C */
+                                        <0 0 0 4 &pcie_intc1 3>; /* INT D */
+
+                        pcie_msi_intc1: msi-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
+                        };
+
+                        pcie_intc1: legacy-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
index fec43128a2e0..85cc7f2872d7 100644
--- a/arch/arm/boot/dts/k2l-evm.dts
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -116,3 +116,15 @@
                 };
         };
 };
+
+&mdio {
+        ethphy0: ethernet-phy@0 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 5d3e83fa2242..c06542b2c954 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -285,5 +285,50 @@
                         #interrupt-cells = <1>;
                         ti,syscon-dev = <&devctrl 0x2a0>;
                 };
+
+                pcie@21800000 {
+                        compatible = "ti,keystone-pcie", "snps,dw-pcie";
+                        clocks = <&clkpcie>;
+                        clock-names = "pcie";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
+                        ranges = <0x81000000 0 0 0x23250000 0 0x4000
+                                0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
+
+                        device_type = "pci";
+                        num-lanes = <2>;
+
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
+                                        <0 0 0 2 &pcie_intc0 1>, /* INT B */
+                                        <0 0 0 3 &pcie_intc0 2>, /* INT C */
+                                        <0 0 0 4 &pcie_intc0 3>; /* INT D */
+
+                        pcie_msi_intc0: msi-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
+                        };
+
+                        pcie_intc0: legacy-interrupt-controller {
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
new file mode 100644
index 000000000000..786959ee9cbe
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2014 Claudio Leite <leitec@staticky.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+        model = "D-Link DIR-665";
+        compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>; /* 128 MB */
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
+        };
+
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ocp@f1000000 {
+                pinctrl: pin-controller@10000 {
+                        pinctrl-0 =< &pmx_led_usb
+                                     &pmx_led_internet_blue
+                                     &pmx_led_internet_amber
+                                     &pmx_led_5g &pmx_led_status_blue
+                                     &pmx_led_wps &pmx_led_status_amber
+                                     &pmx_led_24g
+                                     &pmx_btn_restart &pmx_btn_wps>;
+                        pinctrl-names = "default";
+
+                        pmx_led_usb: pmx-led-usb {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_internet_blue: pmx-led-internet-blue {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_internet_amber: pmx-led-internet-amber {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_5g: pmx-led-5g {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_status_blue: pmx-led-status-blue {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_wps: pmx-led-wps {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_status_amber: pmx-led-status-amber {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_24g: pmx-led-24g {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_restart: pmx-btn-restart {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_wps: pmx-btn-wps {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                spi@10600 {
+                        status = "okay";
+                        m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mxicy,mx25l12805d";
+                                spi-max-frequency = <50000000>;
+                                reg = <0>;
+
+                                partition@0 {
+                                        label = "uboot";
+                                        reg = <0x0 0x30000>;
+                                        read-only;
+                                };
+
+                                partition@30000 {
+                                        label = "nvram";
+                                        reg = <0x30000 0x10000>;
+                                        read-only;
+                                };
+
+                                partition@40000 {
+                                        label = "kernel";
+                                        reg = <0x40000 0x180000>;
+                                };
+
+                                partition@1c0000 {
+                                        label = "rootfs";
+                                        reg = <0x1c0000 0xe00000>;
+                                };
+
+                                cal_data: partition@fc0000 {
+                                        label = "cal_data";
+                                        reg = <0xfc0000 0x10000>;
+                                        read-only;
+                                };
+
+                                partition@fd0000 {
+                                        label = "lang_pack";
+                                        reg = <0xfd0000 0x30000>;
+                                        read-only;
+                                };
+                        };
+                };
+
+                serial@12000 {
+                        status = "okay";
+                };
+
+                i2c@11000 {
+                        status = "okay";
+                };
+
+                ehci@50000 {
+                        status = "okay";
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                blue-usb {
+                        label = "dir665:blue:usb";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+                blue-internet {
+                        /* Can only be turned on if the Internet
+                         * Ethernet port has Link
+                         */
+                        label = "dir665:blue:internet";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+                };
+                amber-internet {
+                        label = "dir665:amber:internet";
+                        gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+                };
+                blue-wifi5g {
+                        label = "dir665:blue:5g";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                };
+                blue-status {
+                        label = "dir665:blue:status";
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+                blue-wps {
+                        label = "dir665:blue:wps";
+                        gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+                };
+                amber-status {
+                        label = "dir665:amber:status";
+                        gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+                };
+                blue-24g {
+                        label = "dir665:blue:24g";
+                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                reset {
+                        label = "reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+                };
+                wps {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                dsa,ethernet = <&eth0port>;
+                dsa,mii-bus = <&mdio>;
+
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
+
+                        port@0 {
+                                reg = <0>;
+                                label = "lan4";
+                        };
+
+                        port@1 {
+                               reg = <1>;
+                               label = "lan3";
+                        };
+
+                        port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                        };
+
+                        port@3 {
+                               reg = <3>;
+                               label = "lan1";
+                        };
+
+                        port@4 {
+                                reg = <4>;
+                                label = "wan";
+                        };
+
+                        port@6 {
+                               reg = <6>;
+                               label = "cpu";
+                        };
+                };
+        };
+};
+
+&mdio {
+        status = "okay";
+};
+
+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
+ * fixed speed and duplex. */
+&eth0 {
+        status = "okay";
+
+        ethernet0-port@0 {
+                speed = <1000>;
+                duplex = <1>;
+        };
+};
+
+/* eth1 is connected to the switch as well. However DSA only supports a
+ * single CPU port. So leave this port disabled to avoid confusion. */
+
+&eth1 {
+        status = "disabled";
+};
+
+/* There is no battery on the boards, so the RTC does not keep time
+ * when there is no power, making it useless. */
+&rtc {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 811e0971fc58..8be5b2e4626e 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -266,7 +266,7 @@
 
                         s35390a: s35390a@30 {
                                 status = "disabled";
-                                compatible = "ssi,s35390a";
+                                compatible = "sii,s35390a";
                                 reg = <0x30>;
                         };
                 };
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 000000000000..9c5e16ba8c95
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+        model = "LS1021A QDS Board";
+
+        aliases {
+                enet0_rgmii_phy = &rgmii_phy1;
+                enet1_rgmii_phy = &rgmii_phy2;
+                enet2_rgmii_phy = &rgmii_phy3;
+                enet0_sgmii_phy = &sgmii_phy1c;
+                enet1_sgmii_phy = &sgmii_phy1d;
+        };
+};
+
+&dspi0 {
+        bus-num = <0>;
+        status = "okay";
+
+        dspiflash: at45db021d@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
+                spi-max-frequency = <16000000>;
+                spi-cpol;
+                spi-cpha;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+        status = "okay";
+
+        pca9547: mux@77 {
+                reg = <0x77>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0>;
+
+                        ds3232: rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x2>;
+
+                        ina220@40 {
+                                compatible = "ti,ina220";
+                                reg = <0x40>;
+                                shunt-resistor = <1000>;
+                        };
+
+                        ina220@41 {
+                                compatible = "ti,ina220";
+                                reg = <0x41>;
+                                shunt-resistor = <1000>;
+                        };
+                };
+
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x3>;
+
+                        eeprom@56 {
+                                compatible = "atmel,24c512";
+                                reg = <0x56>;
+                        };
+
+                        eeprom@57 {
+                                compatible = "atmel,24c512";
+                                reg = <0x57>;
+                        };
+
+                        adt7461a@4c {
+                                compatible = "adi,adt7461a";
+                                reg = <0x4c>;
+                        };
+                };
+        };
+};
+
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        /* NOR, NAND Flashes and FPGA on board */
+        ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+                  0x2 0x0 0x0 0x7e800000 0x00010000
+                  0x3 0x0 0x0 0x7fb00000 0x00000100>;
+        status = "okay";
+
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+        };
+
+        fpga: board-control@3,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                reg = <0x3 0x0 0x0000100>;
+                bank-width = <1>;
+                device-width = <1>;
+                ranges = <0 3 0 0x100>;
+
+                mdio-mux-emi1 {
+                        compatible = "mdio-mux-mmioreg";
+                        mdio-parent-bus = <&mdio0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x54 1>; /* BRDCFG4 */
+                        mux-mask = <0xe0>; /* EMI1[2:0] */
+
+                        /* Onboard PHYs */
+                        ls1021amdio0: mdio@0 {
+                                reg = <0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy1: ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
+                        };
+
+                        ls1021amdio1: mdio@20 {
+                                reg = <0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy2: ethernet-phy@2 {
+                                        reg = <0x2>;
+                                };
+                        };
+
+                        ls1021amdio2: mdio@40 {
+                                reg = <0x40>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rgmii_phy3: ethernet-phy@3 {
+                                        reg = <0x3>;
+                                };
+                        };
+
+                        ls1021amdio3: mdio@60 {
+                                reg = <0x60>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sgmii_phy1c: ethernet-phy@1c {
+                                        reg = <0x1c>;
+                                };
+                        };
+
+                        ls1021amdio4: mdio@80 {
+                                reg = <0x80>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                sgmii_phy1d: ethernet-phy@1d {
+                                        reg = <0x1d>;
+                                };
+                        };
+                };
+        };
+};
+
+&lpuart0 {
+        status = "okay";
+};
+
+&mdio0 {
+        tbi0: tbi-phy@8 {
+                reg = <0x8>;
+                device_type = "tbi-phy";
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100644
index 000000000000..a2c591e2d918
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+        model = "LS1021A TWR Board";
+
+        aliases {
+                enet2_rgmii_phy = &rgmii_phy1;
+                enet0_sgmii_phy = &sgmii_phy2;
+                enet1_sgmii_phy = &sgmii_phy0;
+        };
+};
+
+&dspi1 {
+        bus-num = <0>;
+        status = "okay";
+
+        dspiflash: s25fl064k@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl064k";
+                spi-max-frequency = <16000000>;
+                spi-cpol;
+                spi-cpha;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        /* NOR Flash on board */
+        ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
+        status = "okay";
+
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+        };
+};
+
+&lpuart0 {
+        status = "okay";
+};
+
+&mdio0 {
+        sgmii_phy0: ethernet-phy@0 {
+                reg = <0x0>;
+        };
+        rgmii_phy1: ethernet-phy@1 {
+                reg = <0x1>;
+        };
+        sgmii_phy2: ethernet-phy@2 {
+                reg = <0x2>;
+        };
+        tbi1: tbi-phy@1f {
+                reg = <0x1f>;
+                device_type = "tbi-phy";
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 000000000000..657da14cb4b5
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "fsl,ls1021a";
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &lpuart0;
+                serial1 = &lpuart1;
+                serial2 = &lpuart2;
+                serial3 = &lpuart3;
+                serial4 = &lpuart4;
+                serial5 = &lpuart5;
+                sysclk = &sysclk;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@f00 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0xf00>;
+                        clocks = <&cluster1_clk>;
+                };
+
+                cpu@f01 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0xf01>;
+                        clocks = <&cluster1_clk>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                device_type = "soc";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                gic: interrupt-controller@1400000 {
+                        compatible = "arm,cortex-a7-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x0 0x1401000 0x0 0x1000>,
+                              <0x0 0x1402000 0x0 0x1000>,
+                              <0x0 0x1404000 0x0 0x2000>,
+                              <0x0 0x1406000 0x0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+                };
+
+                ifc: ifc@1530000 {
+                        compatible = "fsl,ifc", "simple-bus";
+                        reg = <0x0 0x1530000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                dcfg: dcfg@1ee0000 {
+                        compatible = "fsl,ls1021a-dcfg", "syscon";
+                        reg = <0x0 0x1ee0000 0x0 0x10000>;
+                        big-endian;
+                };
+
+                esdhc: esdhc@1560000 {
+                        compatible = "fsl,esdhc";
+                        reg = <0x0 0x1560000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        voltage-ranges = <1800 1800 3300 3300>;
+                        sdhci,auto-cmd12;
+                        big-endian;
+                        bus-width = <4>;
+                        status = "disabled";
+                };
+
+                scfg: scfg@1570000 {
+                        compatible = "fsl,ls1021a-scfg", "syscon";
+                        reg = <0x0 0x1570000 0x0 0x10000>;
+                };
+
+                clockgen: clocking@1ee1000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x1ee1000 0x10000>;
+
+                        sysclk: sysclk {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-output-names = "sysclk";
+                        };
+
+                        cga_pll1: pll@800 {
+                                compatible = "fsl,qoriq-core-pll-2.0";
+                                #clock-cells = <1>;
+                                reg = <0x800 0x10>;
+                                clocks = <&sysclk>;
+                                clock-output-names = "cga-pll1", "cga-pll1-div2",
+                                                     "cga-pll1-div4";
+                        };
+
+                        platform_clk: pll@c00 {
+                                compatible = "fsl,qoriq-core-pll-2.0";
+                                #clock-cells = <1>;
+                                reg = <0xc00 0x10>;
+                                clocks = <&sysclk>;
+                                clock-output-names = "platform-clk", "platform-clk-div2";
+                        };
+
+                        cluster1_clk: clk0c0@0 {
+                                compatible = "fsl,qoriq-core-mux-2.0";
+                                #clock-cells = <0>;
+                                reg = <0x0 0x10>;
+                                clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+                                clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+                                clock-output-names = "cluster1-clk";
+                        };
+                };
+
+                dspi0: dspi@2100000 {
+                        compatible = "fsl,vf610-dspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2100000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "dspi";
+                        clocks = <&platform_clk 1>;
+                        spi-num-chipselects = <5>;
+                        big-endian;
+                        status = "disabled";
+                };
+
+                dspi1: dspi@2110000 {
+                        compatible = "fsl,vf610-dspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2110000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "dspi";
+                        clocks = <&platform_clk 1>;
+                        spi-num-chipselects = <5>;
+                        big-endian;
+                        status = "disabled";
+                };
+
+                i2c0: i2c@2180000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2180000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@2190000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2190000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@21a0000 {
+                        compatible = "fsl,vf610-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x21a0000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "i2c";
+                        clocks = <&platform_clk 1>;
+                        status = "disabled";
+                };
+
+                uart0: serial@21c0500 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21c0500 0x0 0x100>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+
+                uart1: serial@21c0600 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21c0600 0x0 0x100>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+
+                uart2: serial@21d0500 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21d0500 0x0 0x100>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+
+                uart3: serial@21d0600 {
+                        compatible = "fsl,16550-FIFO64", "ns16550a";
+                        reg = <0x0 0x21d0600 0x0 0x100>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <0>;
+                        fifo-size = <15>;
+                        status = "disabled";
+                };
+
+                lpuart0: serial@2950000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2950000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sysclk>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                lpuart1: serial@2960000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2960000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                lpuart2: serial@2970000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2970000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                lpuart3: serial@2980000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2980000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                lpuart4: serial@2990000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x2990000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                lpuart5: serial@29a0000 {
+                        compatible = "fsl,ls1021a-lpuart";
+                        reg = <0x0 0x29a0000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "ipg";
+                        status = "disabled";
+                };
+
+                wdog0: watchdog@2ad0000 {
+                        compatible = "fsl,imx21-wdt";
+                        reg = <0x0 0x2ad0000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "wdog-en";
+                        big-endian;
+                };
+
+                sai1: sai@2b50000 {
+                        compatible = "fsl,vf610-sai";
+                        reg = <0x0 0x2b50000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "sai";
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 47>,
+                               <&edma0 1 46>;
+                        big-endian;
+                        status = "disabled";
+                };
+
+                sai2: sai@2b60000 {
+                        compatible = "fsl,vf610-sai";
+                        reg = <0x0 0x2b60000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&platform_clk 1>;
+                        clock-names = "sai";
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 45>,
+                               <&edma0 1 44>;
+                        big-endian;
+                        status = "disabled";
+                };
+
+                edma0: edma@2c00000 {
+                        #dma-cells = <2>;
+                        compatible = "fsl,vf610-edma";
+                        reg = <0x0 0x2c00000 0x0 0x10000>,
+                              <0x0 0x2c10000 0x0 0x10000>,
+                              <0x0 0x2c20000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "edma-tx", "edma-err";
+                        dma-channels = <32>;
+                        big-endian;
+                        clock-names = "dmamux0", "dmamux1";
+                        clocks = <&platform_clk 1>,
+                                 <&platform_clk 1>;
+                };
+
+                mdio0: mdio@2d24000 {
+                        compatible = "gianfar";
+                        device_type = "mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2d24000 0x0 0x4000>;
+                };
+
+                usb@8600000 {
+                        compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+                        reg = <0x0 0x8600000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+
+                usb3@3100000 {
+                        compatible = "snps,dwc3";
+                        reg = <0x0 0x3100000 0x0 0x10000>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                        dr_mode = "host";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711..03bcff87bd27 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
 / {
         interrupt-parent = <&gic>;
 
+        L2: l2-cache-controller@c4200000 {
+                compatible = "arm,pl310-cache";
+                reg = <0xc4200000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
         gic: interrupt-controller@c4301000 {
                 compatible = "arm,cortex-a9-gic";
                 reg = <0xc4301000 0x1000>,
@@ -106,5 +113,35 @@
                         clocks = <&clk81>;
                         status = "disabled";
                 };
+
+                i2c_AO: i2c@c8100500 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc8100500 0x20>;
+                        interrupts = <0 92 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c_A: i2c@c1108500 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc1108500 0x20>;
+                        interrupts = <0 21 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c_B: i2c@c11087c0 {
+                        compatible = "amlogic,meson6-i2c";
+                        reg = <0xc11087c0 0x20>;
+                        interrupts = <0 128 1>;
+                        clocks = <&clk81>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
         };
 }; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541faf1ec..d7d351a68944 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -50,7 +50,7 @@
 
 / {
         model = "Geniatech ATV1200";
-        compatible = "geniatech,atv1200";
+        compatible = "geniatech,atv1200", "amlogic,meson6";
 
         aliases {
                 serial0 = &uart_AO;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
                 cpu@200 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                         reg = <0x200>;
                 };
 
                 cpu@201 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                         reg = <0x201>;
                 };
         };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000000000000..1f442a7fe03b
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public License
+ *     along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "meson.dtsi"
+
+/ {
+        model = "Amlogic Meson8 SoC";
+        compatible = "amlogic,meson8";
+
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x200>;
+                };
+
+                cpu@201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x201>;
+                };
+
+                cpu@202 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x202>;
+                };
+
+                cpu@203 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x203>;
+                };
+        };
+
+        clk81: clk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <141666666>;
+        };
+}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts
new file mode 100644
index 000000000000..b57237e6394a
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592-evb.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Howard Chen <ibanezchen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt6592.dtsi"
+
+/ {
+        model = "mt6592 evb";
+        compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
+
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
new file mode 100644
index 000000000000..31e5a0979d78
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Howard Chen <ibanezchen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "mediatek,mt6592";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x3>;
+                };
+                cpu@4 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x4>;
+                };
+                cpu@5 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x5>;
+                };
+                cpu@6 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x6>;
+                };
+                cpu@7 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x7>;
+                };
+        };
+
+        system_clk: dummy13m {
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+                #clock-cells = <0>;
+        };
+
+        rtc_clk: dummy32k {
+                compatible = "fixed-clock";
+                clock-frequency = <32000>;
+                #clock-cells = <0>;
+        };
+
+        timer: timer@10008000 {
+                compatible = "mediatek,mt6577-timer";
+                reg = <0x10008000 0x80>;
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&system_clk>, <&rtc_clk>;
+                clock-names = "system-clk", "rtc-clk";
+        };
+
+        gic: interrupt-controller@10211000 {
+                compatible = "arm,cortex-a7-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x10211000 0x1000>,
+                      <0x10212000 0x1000>;
+        };
+
+};
+
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
new file mode 100644
index 000000000000..13cba0e77e08
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt8127.dtsi"
+
+/ {
+        model = "MediaTek MT8127 Moose Board";
+        compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+
+        memory {
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
new file mode 100644
index 000000000000..b24c0a2f3c44
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+
+/ {
+        compatible = "mediatek,mt8127";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x3>;
+                };
+
+        };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+
+                system_clk: dummy13m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                rtc_clk: dummy32k {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                        #clock-cells = <0>;
+                };
+        };
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+
+                timer: timer@10008000 {
+                        compatible = "mediatek,mt8127-timer",
+                                        "mediatek,mt6577-timer";
+                        reg = <0 0x10008000 0 0x80>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&system_clk>, <&rtc_clk>;
+                        clock-names = "system-clk", "rtc-clk";
+                };
+
+                gic: interrupt-controller@10211000 {
+                        compatible = "arm,cortex-a7-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0 0x10211000 0 0x1000>,
+                              <0 0x10212000 0 0x1000>,
+                              <0 0x10214000 0 0x2000>,
+                              <0 0x10216000 0 0x2000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
new file mode 100644
index 000000000000..a5adf9742308
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt8135.dtsi"
+
+/ {
+        model = "MediaTek MT8135 evaluation board";
+        compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
+
+        memory {
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
new file mode 100644
index 000000000000..7d56a986358e
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+
+/ {
+        compatible = "mediatek,mt8135";
+        interrupt-parent = <&gic>;
+
+        cpu-map {
+                cluster0 {
+                        core0 {
+                                cpu = <&cpu0>;
+                        };
+                        core1 {
+                                cpu = <&cpu1>;
+                        };
+                };
+
+                cluster1 {
+                        core0 {
+                                cpu = <&cpu2>;
+                        };
+                        core1 {
+                                cpu = <&cpu3>;
+                        };
+                };
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x000>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x001>;
+                };
+
+                cpu2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x100>;
+                };
+
+                cpu3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x101>;
+                };
+        };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+
+                system_clk: dummy13m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+
+                rtc_clk: dummy32k {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                        #clock-cells = <0>;
+                };
+        };
+
+        soc {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "simple-bus";
+                ranges;
+
+                timer: timer@10008000 {
+                        compatible = "mediatek,mt8135-timer",
+                                        "mediatek,mt6577-timer";
+                        reg = <0 0x10008000 0 0x80>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&system_clk>, <&rtc_clk>;
+                        clock-names = "system-clk", "rtc-clk";
+                };
+
+                gic: interrupt-controller@10211000 {
+                        compatible = "arm,cortex-a15-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0 0x10211000 0 0x1000>,
+                              <0 0x10212000 0 0x1000>,
+                              <0 0x10214000 0 0x2000>,
+                              <0 0x10216000 0 0x2000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 521c587acaee..445fafc73254 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -23,24 +23,29 @@
         ethernet@gpmc {
                 compatible = "smsc,lan9221", "smsc,lan9115";
                 bank-width = <2>;
-                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <1>;
-                gpmc,cs-rd-off-ns = <180>;
-                gpmc,cs-wr-off-ns = <180>;
-                gpmc,adv-rd-off-ns = <18>;
-                gpmc,adv-wr-off-ns = <48>;
-                gpmc,oe-on-ns = <54>;
-                gpmc,oe-off-ns = <168>;
-                gpmc,we-on-ns = <54>;
-                gpmc,we-off-ns = <168>;
-                gpmc,rd-cycle-ns = <186>;
-                gpmc,wr-cycle-ns = <186>;
-                gpmc,access-ns = <144>;
-                gpmc,page-burst-access-ns = <24>;
-                gpmc,bus-turnaround-ns = <90>;
-                gpmc,cycle2cycle-delay-ns = <90>;
-                gpmc,cycle2cycle-samecsen;
-                gpmc,cycle2cycle-diffcsen;
+                gpmc,device-width = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <5>;
+                gpmc,cs-rd-off-ns = <150>;
+                gpmc,cs-wr-off-ns = <150>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <15>;
+                gpmc,adv-wr-off-ns = <40>;
+                gpmc,oe-on-ns = <45>;
+                gpmc,oe-off-ns = <140>;
+                gpmc,we-on-ns = <45>;
+                gpmc,we-off-ns = <140>;
+                gpmc,rd-cycle-ns = <155>;
+                gpmc,wr-cycle-ns = <155>;
+                gpmc,access-ns = <120>;
+                gpmc,page-burst-access-ns = <20>;
+                gpmc,bus-turnaround-ns = <75>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
                 vddvario-supply = <&vddvario>;
                 vdd33a-supply = <&vdd33a>;
                 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 68221fab978d..46ef3e443861 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -5,7 +5,7 @@
 #include "omap-gpmc-smsc911x.dtsi"
 
 &gpmc {
-        ranges = <3 0 0x10000000 0x00000400>,
+        ranges = <3 0 0x10000000 0x1000000>,    /* CS3: 16MB for UART */
                  <7 0 0x2c000000 0x01000000>;
 
         /*
@@ -15,7 +15,65 @@
          */
         uart@3,0 {
                 compatible = "ns16550a";
-                reg = <3 0 0x100>;
+                reg = <3 0 8>;  /* CS3, offset 0, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+                gpmc,mux-add-data = <0>;
+                gpmc,device-width = <1>;
+                gpmc,wait-pin = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <5>;
+                gpmc,cs-rd-off-ns = <155>;
+                gpmc,cs-wr-off-ns = <155>;
+                gpmc,adv-on-ns = <15>;
+                gpmc,adv-rd-off-ns = <40>;
+                gpmc,adv-wr-off-ns = <40>;
+                gpmc,oe-on-ns = <45>;
+                gpmc,oe-off-ns = <145>;
+                gpmc,we-on-ns = <45>;
+                gpmc,we-off-ns = <145>;
+                gpmc,rd-cycle-ns = <155>;
+                gpmc,wr-cycle-ns = <155>;
+                gpmc,access-ns = <145>;
+                gpmc,page-burst-access-ns = <20>;
+                gpmc,bus-turnaround-ns = <20>;
+                gpmc,cycle2cycle-delay-ns = <20>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <45>;
+                gpmc,wr-access-ns = <145>;
+        };
+        uart@3,1 {
+                compatible = "ns16550a";
+                reg = <3 0x100 8>;      /* CS3, offset 0x100, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+        };
+        uart@3,2 {
+                compatible = "ns16550a";
+                reg = <3 0x200 8>;      /* CS3, offset 0x200, IO size 8 */
+                bank-width = <2>;
+                reg-shift = <1>;
+                reg-io-width = <1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <6 IRQ_TYPE_EDGE_RISING>;  /* gpio102 */
+                clock-frequency = <1843200>;
+                current-speed = <115200>;
+        };
+        uart@3,3 {
+                compatible = "ns16550a";
+                reg = <3 0x300 8>;      /* CS3, offset 0x300, IO size 8 */
                 bank-width = <2>;
                 reg-shift = <1>;
                 reg-io-width = <1>;
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 24c50db2a478..c9f1e93a95ae 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -40,14 +40,14 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x04000000 0x10000000>;
+        ranges = <0 0 0x04000000 0x1000000>;    /* CS0: 16MB for OneNAND */
 
         /* gpio-irq for dma: 26 */
 
         onenand@0,0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0 0 0x10000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
 
                 gpmc,sync-read;
                 gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index ae89aad01595..e2b2e93d7b61 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,7 @@
                         interrupts = <26>, <34>;
                         interrupt-names = "dsp", "iva";
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <6>;
                         mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index 2c90d29b4cad..05eca2e4430f 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -43,7 +43,31 @@
                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;   /* gpio149 */
                 reg = <5 0x300 0xf>;
                 bank-width = <2>;
-                gpmc,mux-add-data;
-        };
+                gpmc,sync-clk-ps = <0>;
+                gpmc,mux-add-data = <2>;
+                gpmc,device-width = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <7>;
+                gpmc,cs-rd-off-ns = <233>;
+                gpmc,cs-wr-off-ns = <233>;
+                gpmc,adv-on-ns = <22>;
+                gpmc,adv-rd-off-ns = <60>;
+                gpmc,adv-wr-off-ns = <60>;
+                gpmc,oe-on-ns = <67>;
+                gpmc,oe-off-ns = <210>;
+                gpmc,we-on-ns = <67>;
+                gpmc,we-off-ns = <210>;
+                gpmc,rd-cycle-ns = <233>;
+                gpmc,wr-cycle-ns = <233>;
+                gpmc,access-ns = <233>;
+                gpmc,page-burst-access-ns = <30>;
+                gpmc,bus-turnaround-ns = <30>;
+                gpmc,cycle2cycle-delay-ns = <30>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
+        };
 };
 
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index b56d71611026..0dc8de2782b1 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,7 @@
                         reg = <0x48094000 0x200>;
                         interrupts = <26>;
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <4>;
                         ti,mbox-num-fifos = <6>;
                         mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index d00502f4fd9b..0ab748cf7749 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -134,3 +134,14 @@
         bus-width = <4>;
         cap-power-off-card;
 };
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t35x
+        >;
+};
+
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index d1458496520e..8dd14fcf6825 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -46,3 +46,14 @@
         bus-width = <4>;
         cap-power-off-card;
 };
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t35x
+        >;
+};
+
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index b3f9a50b3bc8..46eadb21b5ef 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -31,6 +31,19 @@
         };
 };
 
+&omap3_pmx_wkup {
+        dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3)   /* sys_boot0.dss_data18 */
+                        OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3)   /* sys_boot1.dss_data19 */
+                        OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3)   /* sys_boot3.dss_data20 */
+                        OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3)   /* sys_boot4.dss_data21 */
+                        OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3)   /* sys_boot5.dss_data22 */
+                        OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3)   /* sys_boot6.dss_data23 */
+                >;
+        };
+};
+
 &omap3_pmx_core {
 
         mmc2_pins: pinmux_mmc2_pins {
@@ -61,3 +74,14 @@
         bus-width = <4>;
         cap-power-off-card;
 };
+
+&dss {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins_common
+                &dss_dpi_pins_cm_t3730
+        >;
+};
+
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index c671a2299ea8..6ea6d460db30 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -49,6 +49,24 @@
                 compatible = "usb-nop-xceiv";
                 vcc-supply = <&hsusb2_power>;
         };
+
+        ads7846reg: ads7846-reg {
+                compatible = "regulator-fixed";
+                regulator-name = "ads7846-reg";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        tv0: connector@1 {
+                compatible = "svideo-connector";
+                label = "tv";
+
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
 };
 
 &omap3_pmx_core {
@@ -76,6 +94,76 @@
                         OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4)       /* sys_clkout2.gpio_186 */
                 >;
         };
+
+        dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
+
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)       /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)       /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)       /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)       /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)       /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)       /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)       /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)       /* dss_data23.dss_data23 */
+                >;
+        };
+
+        dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
+                >;
+        };
+
+        ads7846_pins: pinmux_ads7846_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
+                >;
+        };
+
+        mcspi1_pins: pinmux_mcspi1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk */
+                        OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0)        /* mcspi1_simo */
+                        OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0)        /* mcspi1_somi */
+                        OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
+                >;
+        };
+
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
+                >;
+        };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
+                        OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
+                        OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
+                        OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
+                >;
+        };
 };
 
 &uart3 {
@@ -94,12 +182,22 @@
 };
 
 &i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+
         clock-frequency = <400000>;
+
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
 };
 
 &i2c3 {
         clock-frequency = <400000>;
 };
+
 &usbhshost {
         port1-mode = "ehci-phy";
         port2-mode = "ehci-phy";
@@ -108,3 +206,56 @@
 &usbhsehci {
         phys = <&hsusb1_phy &hsusb2_phy>;
 };
+
+&mcspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi1_pins>;
+
+        /* touch controller */
+        ads7846@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&ads7846_pins>;
+
+                compatible = "ti,ads7846";
+                vcc-supply = <&ads7846reg>;
+
+                reg = <0>;                      /* CS0 */
+                spi-max-frequency = <1500000>;
+
+                interrupt-parent = <&gpio2>;
+                interrupts = <25 0>;            /* gpio_57 */
+                pendown-gpio = <&gpio2 25 0>;
+
+                ti,x-min = /bits/ 16 <0x0>;
+                ti,x-max = /bits/ 16 <0x0fff>;
+                ti,y-min = /bits/ 16 <0x0>;
+                ti,y-max = /bits/ 16 <0x0fff>;
+
+                ti,x-plate-ohms = /bits/ 16 <180>;
+                ti,pressure-max = /bits/ 16 <255>;
+
+                ti,debounce-max = /bits/ 16 <30>;
+                ti,debounce-tol = /bits/ 16 <10>;
+                ti,debounce-rep = /bits/ 16 <1>;
+
+                linux,wakeup;
+        };
+};
+
+&venc {
+        status = "ok";
+
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
+
+&mcbsp2 {
+        status = "ok";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 3cbaf98c1372..9a4a3ab9af78 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -10,6 +10,14 @@
                         cpu0-supply = <&vcc>;
                 };
         };
+
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "cm-t35";
+
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 
 &omap3_pmx_core {
@@ -59,6 +67,12 @@
                 reg = <0x48>;
                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                 interrupt-parent = <&intc>;
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
         };
 };
 
@@ -66,6 +80,10 @@
 #include "twl4030_omap3.dtsi"
 #include <dt-bindings/input/input.h>
 
+&venc {
+        vdda-supply = <&vdac>;
+};
+
 &mmc1 {
         vmmc-supply = <&vmmc1>;
 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index da402f0fdab4..169037e5ff53 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -106,10 +106,10 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x30000000 0x04>;       /* CS0: NAND */
+        ranges = <0 0 0x30000000 0x1000000>;       /* CS0: 16MB for NAND */
 
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
 
                 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index a8bd4349c7d2..16e8ce350dda 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,13 +154,14 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x00000000 0x20000000>,
+        ranges = <0 0 0x00000000 0x1000000>,    /* CS0: 16MB for NAND */
                  <5 0 0x2c000000 0x01000000>;
 
         nand@0,0 {
                 linux,mtd-name= "hynix,h8kds0un0mer-4em";
-                reg = <0 0 0>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
+                gpmc,device-width = <2>;
                 ti,nand-ecc-opt = "bch8";
 
                 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fd34f913ace3..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
 
         uart1_pins: pinmux_uart1_pins {
                 pinctrl-single,pins = <
-                        0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
-                        0x14c (PIN_OUTPUT |MUX_MODE0)           /* uart1_tx.uart1_tx */
+                        OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)                /* uart1_rx.uart1_rx */
+                        OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)               /* uart1_tx.uart1_tx */
                 >;
         };
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
-                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)                /* uart2_rx.uart2_rx */
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)               /* uart2_tx.uart2_tx */
                 >;
         };
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
-                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx.uart3_tx */
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)                /* uart3_rx.uart3_rx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* uart3_tx.uart3_tx */
                 >;
         };
 
         mmc1_pins: pinmux_mmc1_pins {
                 pinctrl-single,pins = <
-                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk.sdmmc1_clk */
-                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
-                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
-                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
-                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
-                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
                 >;
         };
 
         dss_dpi_pins: pinmux_dss_dpi_pins {
                pinctrl-single,pins = <
-                       0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
-                       0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
-                       0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
-                       0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
-                       0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
-                       0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
-                       0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
-                       0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
-                       0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
-                       0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
-                       0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-                       0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-                       0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-                       0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-                       0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-                       0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-                       0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-                       0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-                       0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-                       0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-                       0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-                       0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-                       0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
-                       0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
-                       0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
-                       0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
-                       0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
-                       0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
-               >;
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                >;
        };
 };
 
@@ -397,10 +397,10 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
+        ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
 
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
                 ti,nand-ecc-opt = "bch8";
 
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e2d163bf0619..8a63ad2286aa 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -31,18 +31,6 @@
                 regulator-always-on;
         };
 
-        lbee1usjyc_vmmc: lbee1usjyc_vmmc {
-                pinctrl-names = "default";
-                pinctrl-0 = <&lbee1usjyc_pins>;
-                compatible = "regulator-fixed";
-                regulator-name = "regulator-lbee1usjyc";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 WIFI_PDN */
-                startup-delay-us = <10000>;
-                enable-active-high;
-                vin-supply = <&vdd33>;
-        };
 };
 
 &omap3_pmx_core {
@@ -53,13 +41,6 @@
                 >;
         };
 
-        uart2_pins: pinmux_uart2_pins {
-                pinctrl-single,pins = <
-                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
-                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
-                >;
-        };
-
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
                         0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
@@ -67,15 +48,6 @@
                 >;
         };
 
-        /* WiFi/BT combo */
-        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
-                pinctrl-single,pins = <
-                        0x136 (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat5.gpio_137 */
-                        0x138 (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat6.gpio_138 */
-                        0x13a (PIN_OUTPUT | MUX_MODE4)  /* sdmmc2_dat7.gpio_139 */
-                >;
-        };
-
         mcbsp2_pins: pinmux_mcbsp2_pins {
                 pinctrl-single,pins = <
                         0x10c (PIN_INPUT | MUX_MODE0)           /* mcbsp2_fsx.mcbsp2_fsx */
@@ -120,13 +92,6 @@
                 >;
         };
 
-        i2c2_pins: pinmux_i2c2_pins {
-                pinctrl-single,pins = <
-                        0x18e (PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
-                        0x190 (PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
-                >;
-        };
-
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
                         0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
@@ -135,6 +100,55 @@
         };
 };
 
+&gpmc {
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+};
+
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c1_pins>;
@@ -156,12 +170,6 @@
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
 
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-        clock-frequency = <400000>;
-};
-
 &i2c3 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c3_pins>;
@@ -181,14 +189,6 @@
       bus-width = <4>;
 };
 
-&mmc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_pins>;
-        vmmc-supply = <&lbee1usjyc_vmmc>;
-        bus-width = <4>;
-        non-removable;
-};
-
 &mmc3 {
         status = "disabled";
 };
@@ -198,11 +198,6 @@
        pinctrl-0 = <&uart1_pins>;
 };
 
-&uart2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart2_pins>;
-};
-
 &uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
new file mode 100644
index 000000000000..e458c2185e3c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -0,0 +1,246 @@
+/*
+ * Common Device Tree Source for IGEPv2
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-igep.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
+
+/ {
+
+        leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&leds_pins>;
+                compatible = "gpio-leds";
+
+                boot {
+                         label = "omap3:green:boot";
+                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                         default-state = "on";
+                };
+
+                user0 {
+                         label = "omap3:red:user0";
+                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+                         default-state = "off";
+                };
+
+                user1 {
+                         label = "omap3:red:user1";
+                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+                         default-state = "off";
+                };
+
+                user2 {
+                        label = "omap3:green:user1";
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>;  /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
+                vcc-supply = <&hsusb1_power>;
+        };
+
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+
+                digital;
+
+                ddc-i2c-bus = <&i2c3>;
+
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &tfp410_pins
+                &dss_dpi_pins
+        >;
+
+        tfp410_pins: pinmux_tfp410_pins {
+                pinctrl-single,pins = <
+                        0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
+                >;
+        };
+
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
+                        0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
+                        0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
+                        0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
+                        0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
+                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                >;
+        };
+
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
+                >;
+        };
+};
+
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb1_pins
+        >;
+
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)            /* etk_ctl.hsusb1_clk */
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)            /* etk_clk.hsusb1_stp */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d8.hsusb1_dir */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d9.hsusb1_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d0.hsusb1_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d1.hsusb1_data1 */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d2.hsusb1_data2 */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d3.hsusb1_data7 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d4.hsusb1_data4 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d5.hsusb1_data5 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d6.hsusb1_data6 */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d7.hsusb1_data3 */
+                >;
+        };
+
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
+                >;
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+
+        /*
+         * Display monitor features are burnt in the EEPROM
+         * as EDID data.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>,
+                 <5 0 0x2c000000 0x01000000>;
+
+        ethernet@gpmc {
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc9221_pins>;
+                reg = <5 0 0xff>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
+
+&vpll2 {
+        /* Needed for DSS */
+        regulator-name = "vdds_dsi";
+};
+
+&dss {
+        status = "ok";
+
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
new file mode 100644
index 000000000000..cc8bd0cd8cf8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -0,0 +1,45 @@
+/*
+ * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
+ *
+ * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-igep0020-common.dtsi"
+
+/ {
+        model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
+        compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
+
+        /* Regulator to trigger the WL_EN signal of the Wifi module */
+        lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbep5clwmc-wlen";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;            /* gpio_139 - WL_EN */
+                enable-active-high;
+        };
+};
+
+&omap3_pmx_core {
+        lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4)        /* mcspi1_cs3.gpio_177 - W_IRQ */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - BT_EN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - WL_EN */
+                >;
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
+        vmmc-supply = <&lbep5clwmc_wlen>;
+        bus-width = <4>;
+        non-removable;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index b22caaaf774b..fea7f7edb45d 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
+ * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
  *
  * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,272 +9,59 @@
  * published by the Free Software Foundation.
  */
 
-#include "omap3-igep.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
+#include "omap3-igep0020-common.dtsi"
 
 / {
-        model = "IGEPv2 (TI OMAP AM/DM37x)";
+        model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
         compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
 
-        leds {
-                pinctrl-names = "default";
-                pinctrl-0 = <&leds_pins>;
-                compatible = "gpio-leds";
-
-                boot {
-                         label = "omap3:green:boot";
-                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-                         default-state = "on";
-                };
-
-                user0 {
-                         label = "omap3:red:user0";
-                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-                         default-state = "off";
-                };
-
-                user1 {
-                         label = "omap3:red:user1";
-                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-                         default-state = "off";
-                };
-
-                user2 {
-                        label = "omap3:green:user1";
-                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
-                };
+        /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
+        lbee1usjyc_pdn: lbee1usjyc_pdn {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbee1usjyc-pdn";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 - WIFI_PDN */
+                startup-delay-us = <10000>;
+                enable-active-high;
         };
 
-       /* HS USB Port 1 Power */
-       hsusb1_power: hsusb1_power_reg {
-               compatible = "regulator-fixed";
-               regulator-name = "hsusb1_vbus";
-               regulator-min-microvolt = <3300000>;
-               regulator-max-microvolt = <3300000>;
-               gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>;   /* GPIO LEDA */
-               startup-delay-us = <70000>;
-       };
-
-        /* HS USB Host PHY on PORT 1 */
-        hsusb1_phy: hsusb1_phy {
-                compatible = "usb-nop-xceiv";
-                reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
-                vcc-supply = <&hsusb1_power>;
-        };
-
-        tfp410: encoder@0 {
-                compatible = "ti,tfp410";
-                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-
-                                tfp410_in: endpoint@0 {
-                                        remote-endpoint = <&dpi_out>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-
-                                tfp410_out: endpoint@0 {
-                                        remote-endpoint = <&dvi_connector_in>;
-                                };
-                        };
-                };
-        };
-
-        dvi0: connector@0 {
-                compatible = "dvi-connector";
-                label = "dvi";
-
-                digital;
-
-                ddc-i2c-bus = <&i2c3>;
-
-                port {
-                        dvi_connector_in: endpoint {
-                                remote-endpoint = <&tfp410_out>;
-                        };
-                };
+        /* Regulator to trigger the RESET_N_W signal of the Wifi module */
+        lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbee1usjyc-reset-n-w";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;    /* gpio_139 - RESET_N_W */
+                enable-active-high;
         };
 };
 
 &omap3_pmx_core {
-        pinctrl-names = "default";
-        pinctrl-0 = <
-                &tfp410_pins
-                &dss_dpi_pins
-        >;
-
-        tfp410_pins: pinmux_tfp410_pins {
+        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
                 pinctrl-single,pins = <
-                        0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - RESET_N_W */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - RST_N_B */
                 >;
         };
 
-        dss_dpi_pins: pinmux_dss_dpi_pins {
+        uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
-                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
-                        0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
-                        0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
-                        0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
-                        0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
-                        0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
-                        0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
-                        0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
-                        0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
-                        0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-                        0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-                        0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-                        0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-                        0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-                        0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-                        0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-                        0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-                        0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-                        0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-                        0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-                        0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-                        0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
-                        0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
-                        0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
-                        0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
-                        0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
-                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
                 >;
         };
 };
 
-&omap3_pmx_core2 {
+/* On board Wifi module */
+&mmc2 {
         pinctrl-names = "default";
-        pinctrl-0 = <
-                &hsusbb1_pins
-        >;
-
-        hsusbb1_pins: pinmux_hsusbb1_pins {
-                pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)            /* etk_ctl.hsusb1_clk */
-                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)            /* etk_clk.hsusb1_stp */
-                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d8.hsusb1_dir */
-                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d9.hsusb1_nxt */
-                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d0.hsusb1_data0 */
-                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d1.hsusb1_data1 */
-                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d2.hsusb1_data2 */
-                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d3.hsusb1_data7 */
-                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d4.hsusb1_data4 */
-                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d5.hsusb1_data5 */
-                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d6.hsusb1_data6 */
-                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d7.hsusb1_data3 */
-                >;
-        };
-
-        leds_pins: pinmux_leds_pins {
-                pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
-                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
-                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
-                >;
-        };
-};
-
-&i2c3 {
-        clock-frequency = <100000>;
-
-        /*
-         * Display monitor features are burnt in the EEPROM
-         * as EDID data.
-         */
-        eeprom@50 {
-                compatible = "ti,eeprom";
-                reg = <0x50>;
-        };
-};
-
-&gpmc {
-        ranges = <0 0 0x00000000 0x20000000>,
-                 <5 0 0x2c000000 0x01000000>;
-
-        nand@0,0 {
-                linux,mtd-name= "micron,mt29c4g96maz";
-                reg = <0 0 0>;
-                nand-bus-width = <16>;
-                ti,nand-ecc-opt = "bch8";
-
-                gpmc,sync-clk-ps = <0>;
-                gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <44>;
-                gpmc,cs-wr-off-ns = <44>;
-                gpmc,adv-on-ns = <6>;
-                gpmc,adv-rd-off-ns = <34>;
-                gpmc,adv-wr-off-ns = <44>;
-                gpmc,we-off-ns = <40>;
-                gpmc,oe-off-ns = <54>;
-                gpmc,access-ns = <64>;
-                gpmc,rd-cycle-ns = <82>;
-                gpmc,wr-cycle-ns = <82>;
-                gpmc,wr-access-ns = <40>;
-                gpmc,wr-data-mux-bus-ns = <0>;
-
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                partition@0 {
-                        label = "SPL";
-                        reg = <0 0x100000>;
-                };
-                partition@80000 {
-                        label = "U-Boot";
-                        reg = <0x100000 0x180000>;
-                };
-                partition@1c0000 {
-                        label = "Environment";
-                        reg = <0x280000 0x100000>;
-                };
-                partition@280000 {
-                        label = "Kernel";
-                        reg = <0x380000 0x300000>;
-                };
-                partition@780000 {
-                        label = "Filesystem";
-                        reg = <0x680000 0x1f980000>;
-                };
-        };
-
-        ethernet@gpmc {
-                pinctrl-names = "default";
-                pinctrl-0 = <&smsc9221_pins>;
-                reg = <5 0 0xff>;
-                interrupt-parent = <&gpio6>;
-                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-        };
-};
-
-&usbhshost {
-        port1-mode = "ehci-phy";
-};
-
-&usbhsehci {
-        phys = <&hsusb1_phy>;
-};
-
-&vpll2 {
-        /* Needed for DSS */
-        regulator-name = "vdds_dsi";
-};
-
-&dss {
-        status = "ok";
-
-        port {
-                dpi_out: endpoint {
-                        remote-endpoint = <&tfp410_in>;
-                        data-lines = <24>;
-                };
-        };
+        pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
+        vmmc-supply = <&lbee1usjyc_pdn>;
+        vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
+        bus-width = <4>;
+        non-removable;
 };
diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
new file mode 100644
index 000000000000..0cb1527c39d4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Common Device Tree Source for IGEP COM MODULE
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-igep.dtsi"
+
+/ {
+        leds: gpio_leds {
+                compatible = "gpio-leds";
+
+                user0 {
+                         label = "omap3:red:user0";
+                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;        /* LEDA */
+                         default-state = "off";
+                };
+
+                user1 {
+                         label = "omap3:green:user1";
+                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;        /* LEDB */
+                         default-state = "off";
+                };
+
+                user2 {
+                         label = "omap3:red:user1";
+                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;           /* gpio_16 */
+                         default-state = "off";
+                };
+        };
+};
+
+&omap3_pmx_core {
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)        /* mcbsp3_dx.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_dr.uart2_rts */
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_clk.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)        /* mcbsp3_fsx.uart2_rx */
+                >;
+        };
+};
+
+&omap3_pmx_core2 {
+        leds_core2_pins: pinmux_leds_core2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)    /* etk_d2.gpio_16 */
+                >;
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
new file mode 100644
index 000000000000..9326b282c94a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
+ *
+ * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
+ * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-igep0030-common.dtsi"
+
+/ {
+        model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
+        compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
+
+        /* Regulator to trigger the WL_EN signal of the Wifi module */
+        lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbep5clwmc-wlen";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;            /* gpio_139 - WL_EN */
+                enable-active-high;
+        };
+};
+
+&omap3_pmx_core {
+        lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4)        /* sdmmc2_dat4.gpio_136 - W_IRQ */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - BT_EN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - WL_EN */
+                >;
+        };
+
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)       /* i2c2_scl.gpio_168 */
+                >;
+        };
+
+};
+
+&i2c2 {
+        status = "disabled";
+};
+
+&leds {
+        pinctrl-names = "default";
+        pinctrl-0 = <&leds_pins &leds_core2_pins>;
+
+        boot {
+                label = "omap3:green:boot";
+                gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+                default-state = "on";
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
+        vmmc-supply = <&lbep5clwmc_wlen>;
+        bus-width = <4>;
+        non-removable;
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 2793749eb1ba..8150f47ccdf5 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
+ * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
  *
  * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
  * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,97 +9,62 @@
  * published by the Free Software Foundation.
  */
 
-#include "omap3-igep.dtsi"
+#include "omap3-igep0030-common.dtsi"
 
 / {
-        model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
+        model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
         compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
 
-        leds {
-                pinctrl-names = "default";
-                pinctrl-0 = <&leds_pins>;
-                compatible = "gpio-leds";
-
-                boot {
-                         label = "omap3:green:boot";
-                         gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
-                         default-state = "on";
-                };
-
-                user0 {
-                         label = "omap3:red:user0";
-                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
-                         default-state = "off";
-                };
-
-                user1 {
-                         label = "omap3:green:user1";
-                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
-                         default-state = "off";
-                };
+        /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
+        lbee1usjyc_pdn: lbee1usjyc_pdn {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbee1usjyc-pdn";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* gpio_138 - WIFI_PDN */
+                startup-delay-us = <10000>;
+                enable-active-high;
+        };
 
-                user2 {
-                         label = "omap3:red:user1";
-                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-                         default-state = "off";
-                };
+        /* Regulator to trigger the RESET_N_W signal of the Wifi module */
+        lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-lbee1usjyc-reset-n-w";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;    /* gpio_139 - RESET_N_W */
+                enable-active-high;
         };
 };
 
-&omap3_pmx_core2 {
-        leds_pins: pinmux_leds_pins {
+&omap3_pmx_core {
+        lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
                 pinctrl-single,pins = <
-                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat5.gpio_137 - RESET_N_W */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)       /* sdmmc2_dat7.gpio_139 - RST_N_B */
                 >;
         };
 };
 
-&gpmc {
-        ranges = <0 0 0x00000000 0x20000000>;
-
-        nand@0,0 {
-                linux,mtd-name= "micron,mt29c4g96maz";
-                reg = <0 0 0>;
-                nand-bus-width = <16>;
-                ti,nand-ecc-opt = "bch8";
+&leds {
+        pinctrl-names = "default";
+        pinctrl-0 = <&leds_core2_pins>;
 
-                gpmc,sync-clk-ps = <0>;
-                gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <44>;
-                gpmc,cs-wr-off-ns = <44>;
-                gpmc,adv-on-ns = <6>;
-                gpmc,adv-rd-off-ns = <34>;
-                gpmc,adv-wr-off-ns = <44>;
-                gpmc,we-off-ns = <40>;
-                gpmc,oe-off-ns = <54>;
-                gpmc,access-ns = <64>;
-                gpmc,rd-cycle-ns = <82>;
-                gpmc,wr-cycle-ns = <82>;
-                gpmc,wr-access-ns = <40>;
-                gpmc,wr-data-mux-bus-ns = <0>;
-
-                #address-cells = <1>;
-                #size-cells = <1>;
-
-                partition@0 {
-                        label = "SPL";
-                        reg = <0 0x100000>;
-                };
-                partition@80000 {
-                        label = "U-Boot";
-                        reg = <0x100000 0x180000>;
-                };
-                partition@1c0000 {
-                        label = "Environment";
-                        reg = <0x280000 0x100000>;
-                };
-                partition@280000 {
-                        label = "Kernel";
-                        reg = <0x380000 0x300000>;
-                };
-                partition@780000 {
-                        label = "Filesystem";
-                        reg = <0x680000 0x1f980000>;
-                };
+        boot {
+                label = "omap3:green:boot";
+                gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
+                default-state = "on";
         };
 };
+
+/* On board Wifi module */
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
+        vmmc-supply = <&lbee1usjyc_pdn>;
+        vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
+        bus-width = <4>;
+        non-removable;
+};
+
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 77fee3fb7515..b699bc48f242 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -102,8 +102,9 @@
 
         nand@0,0 {
                 linux,mtd-name= "micron,nand";
-                reg = <0 0 0>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
+                gpmc,device-width = <2>;
                 ti,nand-ecc-opt = "bch8";
 
                 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index d97308896f0c..e81fb651d5d0 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -363,7 +363,7 @@
                 <7 0 0x15000000 0x01000000>;
 
         nand@0,0 {
-                reg = <0 0 0x1000000>;
+                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
                 ti,nand-ecc-opt = "bch8";
                 /* no elm on omap3 */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index bc82a12d4c2c..53f3ca064140 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -115,6 +115,12 @@
                 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
                 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
         };
+
+        battery: n900-battery {
+                compatible = "nokia,n900-battery";
+                io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
+                io-channel-names = "temp", "bsi", "vbat";
+        };
 };
 
 &omap3_pmx_core {
@@ -142,6 +148,33 @@
                 >;
         };
 
+        gpmc_pins: pinmux_gpmc_pins {
+                pinctrl-single,pins = <
+
+                        /* address lines */
+                        OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
+                        OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
+                        OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
+
+                        /* data lines, gpmc_d0..d7 not muxable according to TRM */
+                        OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
+                        OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
+                        OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
+                        OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
+                        OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */
+                        OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0)        /* gpmc_d13.gpmc_d13 */
+                        OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0)        /* gpmc_d14.gpmc_d14 */
+                        OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0)        /* gpmc_d15.gpmc_d15 */
+
+                        /*
+                         * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
+                         * according to TRM. OneNAND seems to require PIN_INPUT on clock.
+                         */
+                        OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
+                >;
+        };
+
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
                         0x18a (PIN_INPUT | MUX_MODE0)           /* i2c1_scl */
@@ -540,6 +573,16 @@
                 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
         };
 
+        si4713: si4713@63 {
+                compatible = "silabs,si4713";
+                reg = <0x63>;
+
+                interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
+                reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
+                vio-supply = <&vio>;
+                vdd-supply = <&vaux1>;
+        };
+
         bq24150a: bq24150a@6b {
                 compatible = "ti,bq24150a";
                 reg = <0x6b>;
@@ -585,16 +628,16 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
         ranges = <0 0 0x01000000 0x01000000>,   /* 16 MB for OneNAND */
                  <1 0 0x02000000 0x01000000>;   /* 16 MB for smc91c96 */
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpmc_pins>;
 
-        /* gpio-irq for dma: 65 */
-
+        /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
         onenand@0,0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0 0 0x10000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
 
                 gpmc,sync-read;
                 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 70addcba37c5..1e49dfe7e212 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -115,12 +115,12 @@
 };
 
 &gpmc {
-        ranges = <0 0 0x04000000 0x20000000>;
+        ranges = <0 0 0x04000000 0x1000000>;    /* CS0: 16MB for OneNAND */
 
         onenand@0,0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0 0 0x20000000>;
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
 
                 gpmc,sync-read;
                 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index d59e3de1441e..827f614261f6 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,6 +2,59 @@
  * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
  */
 
+/ {
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+
+                powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;  /* gpio_54 */
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&tfp410_pins>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+
+        audio_amp: audio_amp {
+                compatible = "regulator-fixed";
+                regulator-name = "audio_amp";
+                pinctrl-names = "default";
+                pinctrl-0 = <&sb_t35_audio_amp>;
+                gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;   /* gpio_61 */
+                enable-active-low;
+                regulator-always-on;
+        };
+};
+
 &omap3_pmx_core {
         smsc2_pins: pinmux_smsc2_pins {
                 pinctrl-single,pins = <
@@ -9,6 +62,38 @@
                         OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
                 >;
         };
+
+        tfp410_pins: pinmux_tfp410_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4)       /* gpmc_ncs3.gpio_54 */
+                >;
+        };
+
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
+                >;
+        };
+
+        sb_t35_audio_amp: pinmux_sb_t35_audio_amp {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */
+                >;
+        };
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+
+        clock-frequency = <400000>;
+
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
 };
 
 &gpmc {
@@ -22,24 +107,29 @@
                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                 reg = <4 0 0xff>;
                 bank-width = <2>;
-                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <1>;
-                gpmc,cs-rd-off-ns = <180>;
-                gpmc,cs-wr-off-ns = <180>;
-                gpmc,adv-rd-off-ns = <18>;
-                gpmc,adv-wr-off-ns = <48>;
-                gpmc,oe-on-ns = <54>;
-                gpmc,oe-off-ns = <168>;
-                gpmc,we-on-ns = <54>;
-                gpmc,we-off-ns = <168>;
-                gpmc,rd-cycle-ns = <186>;
-                gpmc,wr-cycle-ns = <186>;
-                gpmc,access-ns = <144>;
-                gpmc,page-burst-access-ns = <24>;
-                gpmc,bus-turnaround-ns = <90>;
-                gpmc,cycle2cycle-delay-ns = <90>;
-                gpmc,cycle2cycle-samecsen;
-                gpmc,cycle2cycle-diffcsen;
+                gpmc,device-width = <1>;
+                gpmc,cycle2cycle-samecsen = <1>;
+                gpmc,cycle2cycle-diffcsen = <1>;
+                gpmc,cs-on-ns = <5>;
+                gpmc,cs-rd-off-ns = <150>;
+                gpmc,cs-wr-off-ns = <150>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <15>;
+                gpmc,adv-wr-off-ns = <40>;
+                gpmc,oe-on-ns = <45>;
+                gpmc,oe-off-ns = <140>;
+                gpmc,we-on-ns = <45>;
+                gpmc,we-off-ns = <140>;
+                gpmc,rd-cycle-ns = <155>;
+                gpmc,wr-cycle-ns = <155>;
+                gpmc,access-ns = <120>;
+                gpmc,page-burst-access-ns = <20>;
+                gpmc,bus-turnaround-ns = <75>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                gpmc,wr-access-ns = <0>;
                 vddvario-supply = <&vddvario>;
                 vdd33a-supply = <&vdd33a>;
                 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 42189b65d393..17986536c61f 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -9,6 +9,11 @@
         model = "CompuLab SBC-T3517 with CM-T3517";
         compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
 
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
+
         /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
         vddvario: regulator-vddvario-sb-t35 {
                 compatible = "regulator-fixed";
@@ -54,3 +59,13 @@
         wp-gpios =  <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59  */
         cd-gpios =  <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
 };
+
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index bbbeea6b1988..c994f0f7e38a 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,6 +8,11 @@
 / {
         model = "CompuLab SBC-T3530 with CM-T3530";
         compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
 };
 
 &omap3_pmx_core {
@@ -34,3 +39,13 @@
 &mmc1 {
         cd-gpios =  <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
 };
+
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 08e4a7086f22..5bdddf29341d 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,6 +8,11 @@
 / {
         model = "CompuLab SBC-T3730 with CM-T3730";
         compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
 };
 
 &omap3_pmx_core {
@@ -25,3 +30,13 @@
         ranges = <5 0 0x2c000000 0x01000000>,
                  <4 0 0x2d000000 0x01000000>;
 };
+
+&dss {
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index b30f387d3a83..e89820a6776e 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -270,7 +270,7 @@
         ranges = <0 0 0x00000000 0x01000000>;
 
         nand@0,0 {
-                reg = <0 0 0>; /* CS0, offset 0 */
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
                 nand-bus-width = <16>;
                 gpmc,device-width = <2>;        /* GPMC_DEVWIDTH_16BIT */
                 ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index e602e75ce5b7..01b71111bd55 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -332,6 +332,7 @@
                         ti,hwmods = "mailbox";
                         reg = <0x48094000 0x200>;
                         interrupts = <26>;
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <2>;
                         ti,mbox-num-fifos = <2>;
                         mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 9bad94efe1c8..16b0cdfbee9c 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -51,8 +51,8 @@
 
 &gpmc {
         ranges = <0 0 0x10000000 0x08000000>,
-                 <1 0 0x28000000 0x08000000>,
-                 <2 0 0x20000000 0x10000000>;
+                 <1 0 0x28000000 0x1000000>,    /* CS1: 16MB for NAND */
+                 <2 0 0x20000000 0x1000000>;    /* CS2: 16MB for OneNAND */
 
         nor@0,0 {
                 compatible = "cfi-flash";
@@ -106,7 +106,7 @@
                 linux,mtd-name= "micron,mt29f1g08abb";
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <1 0 0x08000000>;
+                reg = <1 0 4>;  /* CS1, offset 0, IO size 4 */
                 ti,nand-ecc-opt = "sw";
                 nand-bus-width = <8>;
                 gpmc,cs-on-ns = <0>;
@@ -150,7 +150,7 @@
                 linux,mtd-name= "samsung,kfm2g16q2m-deb8";
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <2 0 0x10000000>;
+                reg = <2 0 0x20000>;    /* CS2, offset 0, IO size 4 */
 
                 gpmc,device-width = <2>;
                 gpmc,mux-add-data = <2>;
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 6dc84d9f9b4c..1a78f013f37a 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -177,6 +177,7 @@
 
 &hdmi {
         status = "ok";
+        vdda-supply = <&vdac>;
 
         pinctrl-names = "default";
         pinctrl-0 = <&dss_hdmi_pins>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 84045a5c3ce8..074147cebae4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -661,6 +661,7 @@
                         reg = <0x4a0f4000 0x200>;
                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <3>;
                         ti,mbox-num-fifos = <8>;
                         mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f69e45b..b321fdf42c9f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -651,6 +651,7 @@
                         reg = <0x4a0f4000 0x200>;
                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mailbox";
+                        #mbox-cells = <1>;
                         ti,mbox-num-users = <3>;
                         ti,mbox-num-fifos = <8>;
                         mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 963b7e54ab15..1ca1a9aa953f 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -41,6 +41,11 @@
                 };
         };
 
+        arm-pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <29>;
+        };
+
         axi {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -132,6 +137,7 @@
                                 reg = <0x90020000 0x10000>;
                                 interrupts = <31>;
                                 clocks = <&clks 35>;
+                                resets = <&rstc 6>;
                         };
                 };
 
@@ -173,6 +179,7 @@
                                 compatible = "sirf,prima2-dspif";
                                 reg = <0xa8000000 0x10000>;
                                 interrupts = <9>;
+                                resets = <&rstc 1>;
                         };
 
                         gps@a8010000 {
@@ -180,6 +187,7 @@
                                 reg = <0xa8010000 0x10000>;
                                 interrupts = <7>;
                                 clocks = <&clks 9>;
+                                resets = <&rstc 2>;
                         };
 
                         dsp@a9000000 {
@@ -187,6 +195,7 @@
                                 reg = <0xa9000000 0x1000000>;
                                 interrupts = <8>;
                                 clocks = <&clks 8>;
+                                resets = <&rstc 0>;
                         };
                 };
 
@@ -524,12 +533,36 @@
                                                 sirf,function = "sdmmc5";
                                         };
                                 };
+                                i2s_mclk_pins_a: i2s_mclk@0 {
+                                        i2s_mclk {
+                                                sirf,pins = "i2smclkgrp";
+                                                sirf,function = "i2s_mclk";
+                                        };
+                                };
+                                i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
+                                        i2s_ext_clk_input {
+                                                sirf,pins = "i2s_ext_clk_inputgrp";
+                                                sirf,function = "i2s_ext_clk_input";
+                                        };
+                                };
                                 i2s_pins_a: i2s@0 {
                                         i2s {
                                                 sirf,pins = "i2sgrp";
                                                 sirf,function = "i2s";
                                         };
                                 };
+                                i2s_no_din_pins_a: i2s_no_din@0 {
+                                        i2s_no_din {
+                                                sirf,pins = "i2s_no_dingrp";
+                                                sirf,function = "i2s_no_din";
+                                        };
+                                };
+                                i2s_6chn_pins_a: i2s_6chn@0 {
+                                        i2s_6chn {
+                                                sirf,pins = "i2s_6chngrp";
+                                                sirf,function = "i2s_6chn";
+                                        };
+                                };
                                 ac97_pins_a: ac97@0 {
                                         ac97 {
                                                 sirf,pins = "ac97grp";
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 2bcf69124a6a..84e05f713c54 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -94,6 +94,10 @@
         voltage-tolerance = <1>; /* 1% */
 };
 
+&cmt1 {
+        status = "okay";
+};
+
 &pfc {
         scifa0_pins: serial0 {
                 renesas,groups = "scifa0_data";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index c17afef92e8d..5ac57babc3b9 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -106,9 +106,20 @@
         i2c5: i2c@e60b0000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe60b0000 0 0x428>;
                 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
+
+                status = "disabled";
+        };
+
+        cmt1: timer@e6130000 {
+                compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
+                reg = <0 0xe6130000 0 0x1004>;
+                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+
+                renesas,channels-mask = <0xff>;
+
                 status = "disabled";
         };
 
@@ -194,7 +205,7 @@
         i2c0: i2c@e6500000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6500000 0 0x428>;
                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -203,7 +214,7 @@
         i2c1: i2c@e6510000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6510000 0 0x428>;
                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -212,7 +223,7 @@
         i2c2: i2c@e6520000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6520000 0 0x428>;
                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -221,7 +232,7 @@
         i2c3: i2c@e6530000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6530000 0 0x428>;
                 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -230,7 +241,7 @@
         i2c4: i2c@e6540000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6540000 0 0x428>;
                 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -239,7 +250,7 @@
         i2c6: i2c@e6550000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6550000 0 0x428>;
                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -248,7 +259,7 @@
         i2c7: i2c@e6560000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6560000 0 0x428>;
                 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
@@ -257,20 +268,20 @@
         i2c8: i2c@e6570000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
                 reg = <0 0xe6570000 0 0x428>;
                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        scifb2: serial@e6c20000 {
+        scifb0: serial@e6c20000 {
                 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                 reg = <0 0xe6c20000 0 0x100>;
                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        scifb3: serial@e6c30000 {
+        scifb1: serial@e6c30000 {
                 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                 reg = <0 0xe6c30000 0 0x100>;
                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
@@ -291,14 +302,14 @@
                 status = "disabled";
         };
 
-        scifb4: serial@e6ce0000 {
+        scifb2: serial@e6ce0000 {
                 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                 reg = <0 0xe6ce0000 0 0x100>;
                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
                 status = "disabled";
         };
 
-        scifb5: serial@e6cf0000 {
+        scifb3: serial@e6cf0000 {
                 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
                 reg = <0 0xe6cf0000 0 0x100>;
                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 2703428557fc..d4af4d86c6b0 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -78,7 +78,7 @@
                 regulator-boot-on;
         };
 
-        gpio-keys {
+        keyboard {
                 compatible = "gpio-keys";
 
                 power-key {
@@ -299,3 +299,7 @@
 
         status = "okay";
 };
+
+&tmu0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index eed697a6bd6b..a8a674bafa67 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -71,6 +71,7 @@
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
         };
 
         /* irqpin1: IRQ8 - IRQ15 */
@@ -91,6 +92,7 @@
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
         };
 
         /* irqpin2: IRQ16 - IRQ23 */
@@ -111,6 +113,7 @@
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
         };
 
         /* irqpin3: IRQ24 - IRQ31 */
@@ -131,6 +134,7 @@
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH
                               0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
         };
 
         ether: ethernet@e9a00000 {
@@ -193,7 +197,7 @@
                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
                 reg = <0xe6c60000 0x100>;
                 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+                clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
                 clock-names = "sci_ick";
                 status = "disabled";
         };
@@ -331,6 +335,34 @@
                 status = "disabled";
         };
 
+        tmu0: timer@fff80000 {
+                compatible = "renesas,tmu-r8a7740", "renesas,tmu";
+                reg = <0xfff80000 0x2c>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 200 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
+                clock-names = "fck";
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
+        tmu1: timer@fff90000 {
+                compatible = "renesas,tmu-r8a7740", "renesas,tmu";
+                reg = <0xfff90000 0x2c>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
+                clock-names = "fck";
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
         clocks {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -448,8 +480,8 @@
                 mstp2_clks: mstp2_clks@e6150138 {
                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0xe6150138 4>, <0xe6150040 4>;
-                        clocks = <&sub_clk>, <&sub_clk>,
-                                 <&cpg_clocks R8A7740_CLK_HP>,
+                        clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
+                                 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
                                  <&cpg_clocks R8A7740_CLK_HP>,
                                  <&cpg_clocks R8A7740_CLK_HP>,
                                  <&cpg_clocks R8A7740_CLK_HP>,
@@ -458,7 +490,8 @@
                                  <&sub_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
+                                R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
+                                R8A7740_CLK_SCIFA7
                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
@@ -467,7 +500,8 @@
                                 R8A7740_CLK_SCIFA4
                         >;
                         clock-output-names =
-                                "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
+                                "scifa6", "intca",
+                                "scifa7", "dmac1", "dmac2", "dmac3",
                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
                                 "scifa2", "scifa3", "scifa4";
                 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index fba294905ff4..04c0c37bb784 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -74,6 +74,10 @@
         status = "okay";
 };
 
+&tmu0 {
+        status = "okay";
+};
+
 &pfc {
         scif0_pins: serial0 {
                 renesas,groups = "scif0_data_a", "scif0_ctrl";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 315ec62cb96b..ef8533910029 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -162,6 +162,42 @@
                 status = "disabled";
         };
 
+        tmu0: timer@ffd80000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd80000 0x30>;
+                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 34 IRQ_TYPE_LEVEL_HIGH>;
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
+        tmu1: timer@ffd81000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd81000 0x30>;
+                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
+        tmu2: timer@ffd82000 {
+                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
+                reg = <0xffd82000 0x30>;
+                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 42 IRQ_TYPE_LEVEL_HIGH>;
+
+                #renesas,channels = <3>;
+
+                status = "disabled";
+        };
+
         scif0: serial@ffe40000 {
                 compatible = "renesas,scif-r8a7778", "renesas,scif";
                 reg = <0xffe40000 0x100>;
@@ -215,8 +251,6 @@
                 compatible = "renesas,sdhi-r8a7778";
                 reg = <0xffe4c000 0x100>;
                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
@@ -224,8 +258,6 @@
                 compatible = "renesas,sdhi-r8a7778";
                 reg = <0xffe4d000 0x100>;
                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
@@ -233,8 +265,6 @@
                 compatible = "renesas,sdhi-r8a7778";
                 reg = <0xffe4f000 0x100>;
                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index fda814ed191d..ede9a29e4bc6 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -303,7 +303,7 @@
         };
 
         sata: sata@fc600000 {
-                compatible = "renesas,rcar-sata";
+                compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
                 reg = <0xfc600000 0x2000>;
                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
@@ -314,8 +314,6 @@
                 reg = <0xffe4c000 0x100>;
                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
@@ -324,8 +322,6 @@
                 reg = <0xffe4d000 0x100>;
                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
@@ -334,8 +330,6 @@
                 reg = <0xffe4e000 0x100>;
                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
@@ -344,8 +338,6 @@
                 reg = <0xffe4f000 0x100>;
                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
-                cap-sd-highspeed;
-                cap-sdio-irq;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index acab2e153382..636d53bb87a2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,6 +9,34 @@
  * kind, whether express or implied.
  */
 
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *      amixer set "LINEOUT Mixer DACL" on
+ *      amixer set "DVC Out" 100%
+ *      amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *      amixer set "DVC Out Mute" on
+ *      amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *      amixer set "DVC Out Ramp" on
+ *      aplay xxx.wav &
+ *      amixer set "DVC Out"  80%  // Volume Down
+ *      amixer set "DVC Out" 100%  // Volume Up
+ */
+
 /dts-v1/;
 #include "r8a7790.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -19,8 +47,8 @@
         compatible = "renesas,lager", "renesas,r8a7790";
 
         aliases {
-                serial6 = &scif0;
-                serial7 = &scif1;
+                serial6 = &scifa0;
+                serial7 = &scifa1;
         };
 
         chosen {
@@ -43,7 +71,7 @@
                 #size-cells = <1>;
         };
 
-        gpio_keys {
+        keyboard {
                 compatible = "gpio-keys";
 
                 button@1 {
@@ -146,6 +174,23 @@
                           1800000 0>;
         };
 
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,format = "left_j";
+                simple-audio-card,bitclock-master = <&sndcodec>;
+                simple-audio-card,frame-master = <&sndcodec>;
+
+                sndcpu: simple-audio-card,cpu {
+                        sound-dai = <&rcar_sound>;
+                };
+
+                sndcodec: simple-audio-card,codec {
+                        sound-dai = <&ak4643>;
+                        system-clock-frequency = <11289600>;
+                };
+        };
+
         vga-encoder {
                 compatible = "adi,adv7123";
 
@@ -207,9 +252,9 @@
                 renesas,function = "du";
         };
 
-        scif0_pins: serial0 {
-                renesas,groups = "scif0_data";
-                renesas,function = "scif0";
+        scifa0_pins: serial0 {
+                renesas,groups = "scifa0_data";
+                renesas,function = "scifa0";
         };
 
         ether_pins: ether {
@@ -222,9 +267,9 @@
                 renesas,function = "intc";
         };
 
-        scif1_pins: serial1 {
-                renesas,groups = "scif1_data";
-                renesas,function = "scif1";
+        scifa1_pins: serial1 {
+                renesas,groups = "scifa1_data";
+                renesas,function = "scifa1";
         };
 
         sdhi0_pins: sd0 {
@@ -268,6 +313,11 @@
                 renesas,function = "iic3";
         };
 
+        hsusb_pins: hsusb {
+                renesas,groups = "usb0_ovc_vbus";
+                renesas,function = "usb0";
+        };
+
         usb0_pins: usb0 {
                 renesas,groups = "usb0";
                 renesas,function = "usb0";
@@ -287,6 +337,16 @@
                 renesas,groups = "vin1_data8", "vin1_clk";
                 renesas,function = "vin1";
         };
+
+        sound_pins: sound {
+                renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+                renesas,function = "ssi";
+        };
+
+        sound_clk_pins: sound_clk {
+                renesas,groups = "audio_clk_a";
+                renesas,function = "audio_clk";
+        };
 };
 
 &ether {
@@ -356,15 +416,15 @@
         };
 };
 
-&scif0 {
-        pinctrl-0 = <&scif0_pins>;
+&scifa0 {
+        pinctrl-0 = <&scifa0_pins>;
         pinctrl-names = "default";
 
         status = "okay";
 };
 
-&scif1 {
-        pinctrl-0 = <&scif1_pins>;
+&scifa1 {
+        pinctrl-0 = <&scifa1_pins>;
         pinctrl-names = "default";
 
         status = "okay";
@@ -424,6 +484,14 @@
         pinctrl-0 = <&iic2_pins>;
         pinctrl-names = "default";
 
+        clock-frequency = <100000>;
+
+        ak4643: sound-codec@12 {
+                compatible = "asahi-kasei,ak4643";
+                #sound-dai-cells = <0>;
+                reg = <0x12>;
+        };
+
         composite-in@20 {
                 compatible = "adi,adv7180";
                 reg = <0x20>;
@@ -466,12 +534,29 @@
         pinctrl-names = "default";
 };
 
+&xhci {
+        status = "okay";
+        pinctrl-0 = <&usb2_pins>;
+        pinctrl-names = "default";
+};
+
 &pci2 {
         status = "okay";
         pinctrl-0 = <&usb2_pins>;
         pinctrl-names = "default";
 };
 
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&hsusb_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+        status = "okay";
+};
+
 /* composite video input */
 &vin1 {
         pinctrl-0 = <&vin1_pins>;
@@ -489,3 +574,23 @@
                 };
         };
 };
+
+&rcar_sound {
+        pinctrl-0 = <&sound_pins &sound_clk_pins>;
+        pinctrl-names = "default";
+
+        #sound-dai-cells = <0>;
+
+        status = "okay";
+
+        rcar_sound,dai {
+                dai0 {
+                        playback = <&ssi0 &src2 &dvc0>;
+                        capture  = <&ssi1 &src3 &dvc1>;
+                };
+        };
+};
+
+&ssi1 {
+        shared-pin;
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0c20c90d8c06..af7e255f629e 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -312,6 +312,70 @@
                 #dma-cells = <1>;
                 dma-channels = <15>;
         };
+
+        audma0: dma-controller@ec700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec700000 0 0x10000>;
+                interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
+                                 0 320 IRQ_TYPE_LEVEL_HIGH
+                                 0 321 IRQ_TYPE_LEVEL_HIGH
+                                 0 322 IRQ_TYPE_LEVEL_HIGH
+                                 0 323 IRQ_TYPE_LEVEL_HIGH
+                                 0 324 IRQ_TYPE_LEVEL_HIGH
+                                 0 325 IRQ_TYPE_LEVEL_HIGH
+                                 0 326 IRQ_TYPE_LEVEL_HIGH
+                                 0 327 IRQ_TYPE_LEVEL_HIGH
+                                 0 328 IRQ_TYPE_LEVEL_HIGH
+                                 0 329 IRQ_TYPE_LEVEL_HIGH
+                                 0 330 IRQ_TYPE_LEVEL_HIGH
+                                 0 331 IRQ_TYPE_LEVEL_HIGH
+                                 0 332 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+
+        audma1: dma-controller@ec720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec720000 0 0x10000>;
+                interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
+                                 0 333 IRQ_TYPE_LEVEL_HIGH
+                                 0 334 IRQ_TYPE_LEVEL_HIGH
+                                 0 335 IRQ_TYPE_LEVEL_HIGH
+                                 0 336 IRQ_TYPE_LEVEL_HIGH
+                                 0 337 IRQ_TYPE_LEVEL_HIGH
+                                 0 338 IRQ_TYPE_LEVEL_HIGH
+                                 0 339 IRQ_TYPE_LEVEL_HIGH
+                                 0 340 IRQ_TYPE_LEVEL_HIGH
+                                 0 341 IRQ_TYPE_LEVEL_HIGH
+                                 0 342 IRQ_TYPE_LEVEL_HIGH
+                                 0 343 IRQ_TYPE_LEVEL_HIGH
+                                 0 344 IRQ_TYPE_LEVEL_HIGH
+                                 0 345 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+
+        audmapp: dma-controller@ec740000 {
+                compatible = "renesas,rcar-audmapp";
+                #dma-cells = <1>;
+
+                reg = <0 0xec740000 0 0x200>;
+        };
+
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -359,6 +423,8 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -369,6 +435,8 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -379,6 +447,8 @@
                 reg = <0 0xe6520000 0 0x425>;
                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
+                dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -389,14 +459,18 @@
                 reg = <0 0xe60b0000 0 0x425>;
                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
-        mmcif0: mmcif@ee200000 {
+        mmcif0: mmc@ee200000 {
                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
+                dma-names = "tx", "rx";
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -406,6 +480,8 @@
                 reg = <0 0xee220000 0 0x80>;
                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
+                dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
+                dma-names = "tx", "rx";
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -420,7 +496,6 @@
                 reg = <0 0xee100000 0 0x200>;
                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
-                cap-sd-highspeed;
                 status = "disabled";
         };
 
@@ -429,7 +504,6 @@
                 reg = <0 0xee120000 0 0x200>;
                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
-                cap-sd-highspeed;
                 status = "disabled";
         };
 
@@ -438,7 +512,6 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
-                cap-sd-highspeed;
                 status = "disabled";
         };
 
@@ -447,7 +520,6 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
-                cap-sd-highspeed;
                 status = "disabled";
         };
 
@@ -568,6 +640,36 @@
                 status = "disabled";
         };
 
+        hsusb: usb@e6590000 {
+                compatible = "renesas,usbhs-r8a7790";
+                reg = <0 0xe6590000 0 0x100>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                renesas,buswait = <4>;
+                phys = <&usb0 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+
+        usbphy: usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7790";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                clock-names = "usbhs";
+                status = "disabled";
+
+                usb0: usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb2: usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
+
         vin0: video@e6ef0000 {
                 compatible = "renesas,vin-r8a7790";
                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
@@ -958,18 +1060,25 @@
                 mstp1_clks: mstp1_clks@e6150134 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
-                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
-                                 <&zs_clk>;
+                        clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
+                                 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
-                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
-                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
+                                R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
+                                R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
+                                R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
+                                R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
+                                R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
+                                R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
+                                R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                         >;
                         clock-output-names =
-                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
-                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                                "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
+                                "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
+                                "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
+                                "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
                 };
                 mstp2_clks: mstp2_clks@e6150138 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -994,25 +1103,29 @@
                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
-                                 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+                                 <&hp_clk>, <&hp_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
+                                R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
                         >;
                         clock-output-names =
                                 "iic2", "tpu0", "mmcif1", "sdhi3",
                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
-                                "iic0", "pciec", "iic1", "ssusb", "cmt1";
+                                "iic0", "pciec", "iic1", "ssusb", "cmt1",
+                                "usbdmac0", "usbdmac1";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
                         #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
-                        clock-output-names = "thermal", "pwm";
+                        renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
+                                                 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
                 };
                 mstp7_clks: mstp7_clks@e615014c {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1160,6 +1273,16 @@
                 status = "disabled";
         };
 
+        xhci: usb@ee000000 {
+                compatible = "renesas,xhci-r8a7790";
+                reg = <0 0xee000000 0 0xc00>;
+                interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+                phys = <&usb2 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+
         pci0: pci@ee090000 {
                 compatible = "renesas,pci-r8a7790";
                 device_type = "pci";
@@ -1178,6 +1301,20 @@
                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
+
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
         };
 
         pci1: pci@ee0b0000 {
@@ -1218,6 +1355,20 @@
                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
+
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
         };
 
         pciec: pcie@fe000000 {
@@ -1245,7 +1396,7 @@
                 status = "disabled";
         };
 
-        rcar_sound: rcar_sound@0xec500000 {
+        rcar_sound: rcar_sound@ec500000 {
                 #sound-dai-cells = <1>;
                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 0868899882e3..740e38678032 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -272,6 +272,17 @@
         pinctrl-names = "default";
 };
 
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&usb0_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+        status = "okay";
+};
+
 &pcie_bus_clk {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 924183817b02..990af167c551 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,6 +10,34 @@
  * kind, whether express or implied.
  */
 
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *      amixer set "LINEOUT Mixer DACL" on
+ *      amixer set "DVC Out" 100%
+ *      amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *      amixer set "DVC Out Mute" on
+ *      amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *      amixer set "DVC Out Ramp" on
+ *      aplay xxx.wav &
+ *      amixer set "DVC Out"  80%  // Volume Down
+ *      amixer set "DVC Out" 100%  // Volume Up
+ */
+
 /dts-v1/;
 #include "r8a7791.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -44,7 +72,7 @@
                 #size-cells = <1>;
         };
 
-        gpio-keys {
+        keyboard {
                 compatible = "gpio-keys";
 
                 key-1 {
@@ -130,12 +158,15 @@
                 compatible = "gpio-leds";
                 led6 {
                         gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                        label = "LED6";
                 };
                 led7 {
                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                        label = "LED7";
                 };
                 led8 {
                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+                        label = "LED8";
                 };
         };
 
@@ -210,6 +241,23 @@
                 states = <3300000 1
                           1800000 0>;
         };
+
+        sound {
+                compatible = "simple-audio-card";
+
+                simple-audio-card,format = "left_j";
+                simple-audio-card,bitclock-master = <&sndcodec>;
+                simple-audio-card,frame-master = <&sndcodec>;
+
+                sndcpu: simple-audio-card,cpu {
+                        sound-dai = <&rcar_sound>;
+                };
+
+                sndcodec: simple-audio-card,codec {
+                        sound-dai = <&ak4643>;
+                        system-clock-frequency = <11289600>;
+                };
+        };
 };
 
 &du {
@@ -300,6 +348,16 @@
                 renesas,groups = "vin1_data8", "vin1_clk";
                 renesas,function = "vin1";
         };
+
+        sound_pins: sound {
+                renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+                renesas,function = "ssi";
+        };
+
+        sound_clk_pins: sound_clk {
+                renesas,groups = "audio_clk_a";
+                renesas,function = "audio_clk";
+        };
 };
 
 &ether {
@@ -425,7 +483,13 @@
         pinctrl-names = "default";
 
         status = "okay";
-        clock-frequency = <400000>;
+        clock-frequency = <100000>;
+
+        ak4643: sound-codec@12 {
+                compatible = "asahi-kasei,ak4643";
+                #sound-dai-cells = <0>;
+                reg = <0x12>;
+        };
 
         composite-in@20 {
                 compatible = "adi,adv7180";
@@ -474,6 +538,17 @@
         pinctrl-names = "default";
 };
 
+&hsusb {
+        status = "okay";
+        pinctrl-0 = <&usb0_pins>;
+        pinctrl-names = "default";
+        renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+        status = "okay";
+};
+
 &pcie_bus_clk {
         status = "okay";
 };
@@ -502,3 +577,23 @@
                 };
         };
 };
+
+&rcar_sound {
+        pinctrl-0 = <&sound_pins &sound_clk_pins>;
+        pinctrl-names = "default";
+
+        #sound-dai-cells = <0>;
+
+        status = "okay";
+
+        rcar_sound,dai {
+                dai0 {
+                        playback = <&ssi0 &src2 &dvc0>;
+                        capture  = <&ssi1 &src3 &dvc1>;
+                };
+        };
+};
+
+&ssi1 {
+        shared-pin;
+};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e4a7170f368b..77c0beeb8d7c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for the r8a7791 SoC
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
  * Copyright (C) 2014 Cogent Embedded Inc.
  *
@@ -301,6 +301,69 @@
                 dma-channels = <15>;
         };
 
+        audma0: dma-controller@ec700000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec700000 0 0x10000>;
+                interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
+                                 0 320 IRQ_TYPE_LEVEL_HIGH
+                                 0 321 IRQ_TYPE_LEVEL_HIGH
+                                 0 322 IRQ_TYPE_LEVEL_HIGH
+                                 0 323 IRQ_TYPE_LEVEL_HIGH
+                                 0 324 IRQ_TYPE_LEVEL_HIGH
+                                 0 325 IRQ_TYPE_LEVEL_HIGH
+                                 0 326 IRQ_TYPE_LEVEL_HIGH
+                                 0 327 IRQ_TYPE_LEVEL_HIGH
+                                 0 328 IRQ_TYPE_LEVEL_HIGH
+                                 0 329 IRQ_TYPE_LEVEL_HIGH
+                                 0 330 IRQ_TYPE_LEVEL_HIGH
+                                 0 331 IRQ_TYPE_LEVEL_HIGH
+                                 0 332 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+
+        audma1: dma-controller@ec720000 {
+                compatible = "renesas,rcar-dmac";
+                reg = <0 0xec720000 0 0x10000>;
+                interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
+                                 0 333 IRQ_TYPE_LEVEL_HIGH
+                                 0 334 IRQ_TYPE_LEVEL_HIGH
+                                 0 335 IRQ_TYPE_LEVEL_HIGH
+                                 0 336 IRQ_TYPE_LEVEL_HIGH
+                                 0 337 IRQ_TYPE_LEVEL_HIGH
+                                 0 338 IRQ_TYPE_LEVEL_HIGH
+                                 0 339 IRQ_TYPE_LEVEL_HIGH
+                                 0 340 IRQ_TYPE_LEVEL_HIGH
+                                 0 341 IRQ_TYPE_LEVEL_HIGH
+                                 0 342 IRQ_TYPE_LEVEL_HIGH
+                                 0 343 IRQ_TYPE_LEVEL_HIGH
+                                 0 344 IRQ_TYPE_LEVEL_HIGH
+                                 0 345 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error",
+                                "ch0", "ch1", "ch2", "ch3",
+                                "ch4", "ch5", "ch6", "ch7",
+                                "ch8", "ch9", "ch10", "ch11",
+                                "ch12";
+                clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
+                clock-names = "fck";
+                #dma-cells = <1>;
+                dma-channels = <13>;
+        };
+
+        audmapp: dma-controller@ec740000 {
+                compatible = "renesas,rcar-audmapp";
+                #dma-cells = <1>;
+
+                reg = <0 0xec740000 0 0x200>;
+        };
+
         /* The memory map in the User's Manual maps the cores to bus numbers */
         i2c0: i2c@e6508000 {
                 #address-cells = <1>;
@@ -371,6 +434,8 @@
                 reg = <0 0xe60b0000 0 0x425>;
                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -381,6 +446,8 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -391,6 +458,8 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -400,6 +469,17 @@
                 #gpio-range-cells = <3>;
         };
 
+        mmcif0: mmc@ee200000 {
+                compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
+                dma-names = "tx", "rx";
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
         sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7791";
                 reg = <0 0xee100000 0 0x200>;
@@ -613,6 +693,36 @@
                 status = "disabled";
         };
 
+        hsusb: usb@e6590000 {
+                compatible = "renesas,usbhs-r8a7791";
+                reg = <0 0xe6590000 0 0x100>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+                renesas,buswait = <4>;
+                phys = <&usb0 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+
+        usbphy: usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7791";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+                clock-names = "usbhs";
+                status = "disabled";
+
+                usb0: usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb2: usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
+
         vin0: video@e6ef0000 {
                 compatible = "renesas,vin-r8a7791";
                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
@@ -958,17 +1068,23 @@
                 mstp1_clks: mstp1_clks@e6150134 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
-                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                        clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
+                                 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                                 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
-                                R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
-                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
+                                R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
+                                R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
+                                R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
+                                R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
+                                R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
+                                R8A7791_CLK_VSP1_S
                         >;
                         clock-output-names =
-                                "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
-                                "vsp1-du0", "vsp1-sy";
+                                "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
+                                "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
+                                "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
                 };
                 mstp2_clks: mstp2_clks@e6150138 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -992,24 +1108,28 @@
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-                                 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
+                                 <&hp_clk>, <&hp_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
+                                R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
                         >;
                         clock-output-names =
                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
-                                "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
+                                "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+                                "usbdmac0", "usbdmac1";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-                        clocks = <&extal_clk>, <&p_clk>;
+                        clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
                         #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
-                        clock-output-names = "thermal", "pwm";
+                        renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
+                                                 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
+                        clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
                 };
                 mstp7_clks: mstp7_clks@e615014c {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1157,6 +1277,16 @@
                 status = "disabled";
         };
 
+        xhci: usb@ee000000 {
+                compatible = "renesas,xhci-r8a7791";
+                reg = <0 0xee000000 0 0xc00>;
+                interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+                phys = <&usb2 1>;
+                phy-names = "usb";
+                status = "disabled";
+        };
+
         pci0: pci@ee090000 {
                 compatible = "renesas,pci-r8a7791";
                 device_type = "pci";
@@ -1175,6 +1305,20 @@
                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
+
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb0 0>;
+                        phy-names = "usb";
+                };
         };
 
         pci1: pci@ee0d0000 {
@@ -1195,6 +1339,20 @@
                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                usb@0,1 {
+                        reg = <0x800 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
+
+                usb@0,2 {
+                        reg = <0x1000 0 0 0 0>;
+                        device_type = "pci";
+                        phys = <&usb2 0>;
+                        phy-names = "usb";
+                };
         };
 
         pciec: pcie@fe000000 {
@@ -1222,7 +1380,7 @@
                 status = "disabled";
         };
 
-        rcar_sound: rcar_sound@0xec500000 {
+        rcar_sound: rcar_sound@ec500000 {
                 #sound-dai-cells = <1>;
                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8aec51268b7d..f2cf7576bf3f 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -20,7 +20,7 @@
         };
 
         chosen {
-                bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                 stdout-path = &scif2;
         };
 
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d4e8bce1e0b7..19c9de3f2a5a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -82,6 +82,14 @@
                 status = "disabled";
         };
 
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
         irqc0: interrupt-controller@e61c0000 {
                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
                 #interrupt-cells = <2>;
@@ -453,16 +461,19 @@
                 mstp1_clks: mstp1_clks@e6150134 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
-                                 <&cp_clk>,
-                                 <&zs_clk>, <&zs_clk>, <&zs_clk>;
+                        clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
+                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+                                 <&zs_clk>, <&zs_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2
-                                R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
+                                R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
+                                R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
+                                R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
+                                R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
                         >;
                         clock-output-names =
-                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0";
+                                "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
+                                "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
                 };
                 mstp2_clks: mstp2_clks@e6150138 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -509,13 +520,13 @@
                 mstp8_clks: mstp8_clks@e6150990 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&p_clk>;
+                        clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
                         #clock-cells = <1>;
                         renesas,clock-indices = <
-                                R8A7794_CLK_ETHER
+                                R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
                         >;
                         clock-output-names =
-                                "ether";
+                                "vin1", "vin0", "ether";
                 };
                 mstp11_clks: mstp11_clks@e615099c {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index d5344510c676..baf21ac6ce7f 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -60,6 +60,10 @@
         };
 };
 
+&cpu0 {
+        cpu0-supply = <&vdd_arm>;
+};
+
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
new file mode 100644
index 000000000000..0a7304beb417
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3066a.dtsi"
+
+/ {
+        model = "MarsBoard RK3066";
+        compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
+
+        memory {
+                reg = <0x60000000 0x40000000>;
+        };
+
+        vcc_sd0: sdmmc-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "sdmmc-supply";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+                startup-delay-us = <100000>;
+                vin-supply = <&vcc_io>;
+        };
+
+        vsys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vsys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tps: tps@2d {
+                reg = <0x2d>;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+                vcc1-supply = <&vsys>;
+                vcc2-supply = <&vsys>;
+                vcc3-supply = <&vsys>;
+                vcc4-supply = <&vsys>;
+                vcc5-supply = <&vcc_io>;
+                vcc6-supply = <&vcc_io>;
+                vcc7-supply = <&vsys>;
+                vccio-supply = <&vsys>;
+
+                regulators {
+                        vcc_rtc: regulator@0 {
+                                regulator-name = "vcc_rtc";
+                                regulator-always-on;
+                        };
+
+                        vcc_io: regulator@1 {
+                                regulator-name = "vcc_io";
+                                regulator-always-on;
+                        };
+
+                        vdd_arm: regulator@2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vcc_ddr: regulator@3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vcc18_cif: regulator@5 {
+                                regulator-name = "vcc18_cif";
+                                regulator-always-on;
+                        };
+
+                        vdd_11: regulator@6 {
+                                regulator-name = "vdd_11";
+                                regulator-always-on;
+                        };
+
+                        vcc_25: regulator@7 {
+                                regulator-name = "vcc_25";
+                                regulator-always-on;
+                        };
+
+                        vcc_18: regulator@8 {
+                                regulator-name = "vcc_18";
+                                regulator-always-on;
+                        };
+
+                        vcc25_hdmi: regulator@9 {
+                                regulator-name = "vcc25_hdmi";
+                                regulator-always-on;
+                        };
+
+                        vcca_33: regulator@10 {
+                                regulator-name = "vcca_33";
+                                regulator-always-on;
+                        };
+
+                        vcc_rmii: regulator@11 {
+                                regulator-name = "vcc_rmii";
+                        };
+
+                        vcc28_cif: regulator@12 {
+                                regulator-name = "vcc28_cif";
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+/* must be included after &tps gets defined */
+#include "tps65910.dtsi"
+
+&emac {
+        status = "okay";
+
+        phy = <&phy0>;
+        phy-supply = <&vcc_rmii>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+&pinctrl {
+        lan8720a {
+                phy_int: phy-int {
+                        rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&wdt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..41ffd4951ef3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
                 #size-cells = <0>;
                 enable-method = "rockchip,rk3066-smp";
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1008000 1075000
+                                 816000 1025000
+                                 600000 1025000
+                                 504000 1000000
+                                 312000  975000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -53,6 +63,51 @@
                 };
         };
 
+        i2s0: i2s@10118000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x10118000 0x2000>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                dmas = <&dmac1_s 4>, <&dmac1_s 5>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+                status = "disabled";
+        };
+
+        i2s1: i2s@1011a000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x1011a000 0x2000>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_bus>;
+                dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
+                status = "disabled";
+        };
+
+        i2s2: i2s@1011c000 {
+                compatible = "rockchip,rk3066-i2s";
+                reg = <0x1011c000 0x2000>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s2_bus>;
+                dmas = <&dmac1_s 9>, <&dmac1_s 10>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
+                status = "disabled";
+        };
+
         cru: clock-controller@20000000 {
                 compatible = "rockchip,rk3066a-cru";
                 reg = <0x20000000 0x1000>;
@@ -179,6 +234,24 @@
                         bias-disable;
                 };
 
+                emac {
+                        emac_xfer: emac-xfer {
+                                rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
+                                                <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
+                                                <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
+                                                <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
+                                                <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
+                                                <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
+                                                <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
+                                                <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
+                        };
+
+                        emac_mdio: emac-mdio {
+                                rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
+                                                <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
+                        };
+                };
+
                 emmc {
                         emmc_clk: emmc-clk {
                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
@@ -405,6 +478,42 @@
                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
                         };
                 };
+
+                i2s0 {
+                        i2s0_bus: i2s0-bus {
+                                rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
+
+                i2s1 {
+                        i2s1_bus: i2s1-bus {
+                                rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
+
+                i2s2 {
+                        i2s2_bus: i2s2-bus {
+                                rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
+                                                <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
+                        };
+                };
         };
 };
 
@@ -496,3 +605,7 @@
 &wdt {
         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 };
+
+&emac {
+        compatible = "rockchip,rk3066-emac";
+};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 15910c9ddbc7..9a09579b8309 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -43,16 +43,19 @@
                 compatible = "gpio-leds";
 
                 green {
+                        label = "rock:green:user1";
                         gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
                         default-state = "off";
                 };
 
-                yellow {
+                blue {
+                        label = "rock:blue:user2";
                         gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
                         default-state = "off";
                 };
 
                 sleep {
+                        label = "rock:red:power";
                         gpios = <&gpio0 15 0>;
                         default-state = "off";
                 };
@@ -118,6 +121,10 @@
         };
 };
 
+&cpu0 {
+        cpu0-supply = <&vdd_arm>;
+};
+
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
@@ -159,7 +166,7 @@
                         vdd_arm: REG3 {
                                 regulator-name = "VDD_ARM";
                                 regulator-min-microvolt = <875000>;
-                                regulator-max-microvolt = <1300000>;
+                                regulator-max-microvolt = <1350000>;
                                 regulator-always-on;
                         };
 
@@ -239,6 +246,18 @@
         disable-wp;
 };
 
+&pwm1 {
+        status = "okay";
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&pwm3 {
+        status = "okay";
+};
+
 &pinctrl {
         pcfg_output_low: pcfg-output-low {
                 output-low;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b45..1d4d79c6688d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
                 #size-cells = <0>;
                 enable-method = "rockchip,rk3066-smp";
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1608000 1350000
+                                1416000 1250000
+                                1200000 1150000
+                                1008000 1075000
+                                 816000  975000
+                                 600000  950000
+                                 504000  925000
+                                 312000  875000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -65,6 +78,21 @@
                 };
         };
 
+        i2s0: i2s@1011a000 {
+                compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
+                reg = <0x1011a000 0x2000>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+                dma-names = "tx", "rx";
+                clock-names = "i2s_hclk", "i2s_clk";
+                clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+                status = "disabled";
+        };
+
         cru: clock-controller@20000000 {
                 compatible = "rockchip,rk3188-cru";
                 reg = <0x20000000 0x1000>;
@@ -83,7 +111,7 @@
                 #size-cells = <1>;
                 ranges;
 
-                gpio0: gpio0@0x2000a000 {
+                gpio0: gpio0@2000a000 {
                         compatible = "rockchip,rk3188-gpio-bank0";
                         reg = <0x2000a000 0x100>;
                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -96,7 +124,7 @@
                         #interrupt-cells = <2>;
                 };
 
-                gpio1: gpio1@0x2003c000 {
+                gpio1: gpio1@2003c000 {
                         compatible = "rockchip,gpio-bank";
                         reg = <0x2003c000 0x100>;
                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,6 +423,17 @@
                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
                         };
                 };
+
+                i2s0 {
+                        i2s0_bus: i2s0-bus {
+                                rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
+                                                <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8e3df4..d8c775e6d5fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -17,6 +17,10 @@
         compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
 };
 
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
+
 &i2c0 {
         clock-frequency = <400000>;
         status = "okay";
@@ -44,7 +48,7 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-min-microvolt = <750000>;
-                                regulator-max-microvolt = <1300000>;
+                                regulator-max-microvolt = <1350000>;
                                 regulator-name = "vdd_arm";
                         };
 
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea52fa1..3e067dd65d0c 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -148,6 +148,12 @@
         status = "okay";
 };
 
+&tsadc {
+        rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+        status = "okay";
+};
+
 &pinctrl {
         backlight {
                 bl_en: bl-en {
diff --git a/arch/arm/boot/dts/rk3288-thermal.dtsi b/arch/arm/boot/dts/rk3288-thermal.dtsi
new file mode 100644
index 000000000000..2695200c0af7
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-thermal.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Device Tree Source for RK3288 SoC thermal
+ *
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+reserve_thermal: reserve_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+
+        thermal-sensors = <&tsadc 0>;
+};
+
+cpu_thermal: cpu_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+
+        thermal-sensors = <&tsadc 1>;
+
+        trips {
+                cpu_alert0: cpu_alert0 {
+                        temperature = <70000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "passive";
+                };
+                cpu_crit: cpu_crit {
+                        temperature = <90000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+
+        cooling-maps {
+                map0 {
+                        trip = <&cpu_alert0>;
+                        cooling-device =
+                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                };
+        };
+};
+
+gpu_thermal: gpu_thermal {
+        polling-delay-passive = <1000>; /* milliseconds */
+        polling-delay = <5000>; /* milliseconds */
+
+        thermal-sensors = <&tsadc 2>;
+
+        trips {
+                gpu_alert0: gpu_alert0 {
+                        temperature = <70000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "passive";
+                };
+                gpu_crit: gpu_crit {
+                        temperature = <90000>; /* millicelsius */
+                        hysteresis = <2000>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+
+        cooling-maps {
+                map0 {
+                        trip = <&gpu_alert0>;
+                        cooling-device =
+                                <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..fd19f00784bd 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "skeleton.dtsi"
 
 / {
@@ -46,26 +47,50 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "rockchip,rk3066-smp";
+                rockchip,pmu = <&pmu>;
 
-                cpu@500 {
+                cpu0: cpu@500 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x500>;
+                        resets = <&cru SRST_CORE0>;
+                        operating-points = <
+                                /* KHz    uV */
+                                1608000 1350000
+                                1512000 1300000
+                                1416000 1200000
+                                1200000 1100000
+                                1008000 1050000
+                                 816000 1000000
+                                 696000  950000
+                                 600000  900000
+                                 408000  900000
+                                 312000  900000
+                                 216000  900000
+                                 126000  900000
+                        >;
+                        #cooling-cells = <2>; /* min followed by max */
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                 };
                 cpu@501 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x501>;
+                        resets = <&cru SRST_CORE1>;
                 };
                 cpu@502 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x502>;
+                        resets = <&cru SRST_CORE2>;
                 };
                 cpu@503 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x503>;
+                        resets = <&cru SRST_CORE3>;
                 };
         };
 
@@ -116,6 +141,7 @@
 
         timer {
                 compatible = "arm,armv7-timer";
+                arm,cpu-registers-not-fw-configured;
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -177,6 +203,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 11>, <&dmac_peri 12>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +218,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 13>, <&dmac_peri 14>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +233,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 15>, <&dmac_peri 16>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -329,6 +361,25 @@
                 status = "disabled";
         };
 
+        thermal-zones {
+                #include "rk3288-thermal.dtsi"
+        };
+
+        tsadc: tsadc@ff280000 {
+                compatible = "rockchip,rk3288-tsadc";
+                reg = <0xff280000 0x100>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+                clock-names = "tsadc", "apb_pclk";
+                resets = <&cru SRST_TSADC>;
+                reset-names = "tsadc-apb";
+                pinctrl-names = "default";
+                pinctrl-0 = <&otp_out>;
+                #thermal-sensor-cells = <1>;
+                rockchip,hw-tshut-temp = <95000>;
+                status = "disabled";
+        };
+
         usb_host0_ehci: usb@ff500000 {
                 compatible = "generic-ehci";
                 reg = <0xff500000 0x100>;
@@ -439,6 +490,18 @@
                 status = "disabled";
         };
 
+        bus_intmem@ff700000 {
+                compatible = "mmio-sram";
+                reg = <0xff700000 0x18000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xff700000 0x18000>;
+                smp-sram@0 {
+                        compatible = "rockchip,rk3066-smp-sram";
+                        reg = <0x00 0x10>;
+                };
+        };
+
         pmu: power-management@ff730000 {
                 compatible = "rockchip,rk3288-pmu", "syscon";
                 reg = <0xff730000 0x100>;
@@ -455,6 +518,16 @@
                 rockchip,grf = <&grf>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
+                assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                  <&cru PCLK_PERI>;
+                assigned-clock-rates = <594000000>, <400000000>,
+                                       <500000000>, <300000000>,
+                                       <150000000>, <75000000>,
+                                       <300000000>, <150000000>,
+                                       <75000000>;
         };
 
         grf: syscon@ff770000 {
@@ -484,6 +557,24 @@
                 status = "disabled";
         };
 
+        vopb_mmu: iommu@ff930300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff930300 0x100>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopb_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
+        vopl_mmu: iommu@ff940300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff940300 0x100>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopl_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
         gic: interrupt-controller@ffc01000 {
                 compatible = "arm,gic-400";
                 interrupt-controller;
@@ -948,6 +1039,12 @@
                         };
                 };
 
+                tsadc {
+                        otp_out: otp-out {
+                                rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
                 pwm0 {
                         pwm0_pin: pwm0-pin {
                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 499468d42ada..c54a9715dcfa 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -29,6 +29,10 @@
                 mshc0 = &emmc;
                 mshc1 = &mmc0;
                 mshc2 = &mmc1;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
                 spi0 = &spi0;
                 spi1 = &spi1;
         };
@@ -173,10 +177,9 @@
                 compatible = "rockchip,rk2928-dw-mshc";
                 reg = <0x10214000 0x1000>;
                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-
                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
                 clock-names = "biu", "ciu";
-
+                fifo-depth = <256>;
                 status = "disabled";
         };
 
@@ -184,10 +187,9 @@
                 compatible = "rockchip,rk2928-dw-mshc";
                 reg = <0x10218000 0x1000>;
                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
                 clock-names = "biu", "ciu";
-
+                fifo-depth = <256>;
                 status = "disabled";
         };
 
@@ -195,10 +197,9 @@
                 compatible = "rockchip,rk2928-dw-mshc";
                 reg = <0x1021c000 0x1000>;
                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-
                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
                 clock-names = "biu", "ciu";
-
+                fifo-depth = <256>;
                 status = "disabled";
         };
 
@@ -367,6 +368,8 @@
                 reg = <0x20070000 0x1000>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                dmas = <&dmac2 10>, <&dmac2 11>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 
@@ -378,6 +381,8 @@
                 reg = <0x20074000 0x1000>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                dmas = <&dmac2 12>, <&dmac2 13>;
+                dma-names = "tx", "rx";
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
index 57e00f9bce99..a25debb50401 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -198,10 +198,6 @@
         status = "okay";
 };
 
-&pwm {
-        status = "okay";
-};
-
 &pinctrl0 {
         gpio_leds: gpio-leds {
                 samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index ff5bdaac987a..0ccb414cd268 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -172,7 +172,6 @@
                         clocks = <&clocks PCLK_PWM>;
                         samsung,pwm-outputs = <0>, <1>;
                         #pwm-cells = <3>;
-                        status = "disabled";
                 };
 
                 pinctrl0: pinctrl@7f008000 {
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 0dac0e66ccad..939be1299ca6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -101,19 +101,23 @@
                 compatible = "gpio-leds";
                 led1 {
                         gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
+                        label = "LED1";
                 };
                 led2 {
                         gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
+                        label = "LED2";
                 };
                 led3 {
                         gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
+                        label = "LED3";
                 };
                 led4 {
                         gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
+                        label = "LED4";
                 };
         };
 
-        gpio-keys {
+        keyboard {
                 compatible = "gpio-keys";
 
                 back-key {
@@ -251,7 +255,7 @@
                 };
         };
 
-        ak4648: ak4648@0x12 {
+        ak4648: ak4648@12 {
                 #sound-dai-cells = <0>;
                 compatible = "asahi-kasei,ak4648";
                 reg = <0x12>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 030a5920312f..d8def5a529da 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -138,7 +138,7 @@
         i2c0: i2c@e6820000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                 reg = <0xe6820000 0x425>;
                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
                               0 168 IRQ_TYPE_LEVEL_HIGH
@@ -150,7 +150,7 @@
         i2c1: i2c@e6822000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                 reg = <0xe6822000 0x425>;
                 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
                               0 52 IRQ_TYPE_LEVEL_HIGH
@@ -162,7 +162,7 @@
         i2c2: i2c@e6824000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                 reg = <0xe6824000 0x425>;
                 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
                               0 172 IRQ_TYPE_LEVEL_HIGH
@@ -174,7 +174,7 @@
         i2c3: i2c@e6826000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                 reg = <0xe6826000 0x425>;
                 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
                               0 184 IRQ_TYPE_LEVEL_HIGH
@@ -186,7 +186,7 @@
         i2c4: i2c@e6828000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
                 reg = <0xe6828000 0x425>;
                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
                               0 188 IRQ_TYPE_LEVEL_HIGH
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4472fd92685c..252c3d1bda50 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -639,6 +639,33 @@
                         clock-names = "biu", "ciu";
                 };
 
+                ocram: sram@ffff0000 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff0000 0x10000>;
+                };
+
+                spi0: spi@fff00000 {
+                        compatible = "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 154 4>;
+                        num-cs = <4>;
+                        clocks = <&spi_m_clk>;
+                        status = "disabled";
+                };
+
+                spi1: spi@fff01000 {
+                        compatible = "snps,dw-apb-ssi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0xfff01000 0x1000>;
+                        interrupts = <0 156 4>;
+                        num-cs = <4>;
+                        clocks = <&spi_m_clk>;
+                        status = "disabled";
+                };
+
                 /* Local timer */
                 timer@fffec600 {
                         compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
new file mode 100644
index 000000000000..8a05c47fd57f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -0,0 +1,374 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
+                ethernet2 = &gmac2;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                timer0 = &timer0;
+                timer1 = &timer1;
+                timer2 = &timer2;
+                timer3 = &timer3;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: intc@ffffd000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xffffd000 0x1000>,
+                      <0xffffc100 0x100>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                device_type = "soc";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pdma: pdma@ffda1000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xffda1000 0x1000>;
+                                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 84 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 85 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 86 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 87 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 88 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 89 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+
+                clkmgr@ffd04000 {
+                                compatible = "altr,clk-mgr";
+                                reg = <0xffd04000 0x1000>;
+
+                                clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        osc1: osc1 {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                        };
+
+                                        main_pll: main_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc1>;
+                                        };
+
+                                        periph_pll: periph_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc1>;
+                                        };
+                                };
+                };
+
+                gmac0: ethernet@ff800000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff800000 0x2000>;
+                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+
+                gmac1: ethernet@ff802000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff802000 0x2000>;
+                        interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+
+                gmac2: ethernet@ff804000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+                        reg = <0xff804000 0x2000>;
+                        interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        /* Filled in by bootloader */
+                        mac-address = [00 00 00 00 00 00];
+                        status = "disabled";
+                };
+
+                gpio0: gpio@ffc02900 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02900 0x100>;
+                        status = "disabled";
+
+                        porta: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                gpio1: gpio@ffc02a00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02a00 0x100>;
+                        status = "disabled";
+
+                        portb: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                gpio2: gpio@ffc02b00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xffc02b00 0x100>;
+                        status = "disabled";
+
+                        portc: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <27>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                i2c0: i2c@ffc02200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02200 0x100>;
+                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@ffc02300 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02300 0x100>;
+                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@ffc02400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02400 0x100>;
+                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@ffc02500 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02500 0x100>;
+                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@ffc02600 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc02600 0x100>;
+                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                L2: l2-cache@fffff000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfffff000 0x1000>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                mmc: dwmmc0@ff808000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "altr,socfpga-dw-mshc";
+                        reg = <0xff808000 0x1000>;
+                        interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+                        fifo-depth = <0x400>;
+                };
+
+                ocram: sram@ffe00000 {
+                        compatible = "mmio-sram";
+                        reg = <0xffe00000 0x40000>;
+                };
+
+                rst: rstmgr@ffd05000 {
+                        #reset-cells = <1>;
+                        compatible = "altr,rst-mgr";
+                        reg = <0xffd05000 0x100>;
+                };
+
+                sysmgr: sysmgr@ffd06000 {
+                        compatible = "altr,sys-mgr", "syscon";
+                        reg = <0xffd06000 0x300>;
+                };
+
+                /* Local timer */
+                timer@ffffc600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xffffc600 0x100>;
+                        interrupts = <1 13 0xf04>;
+                };
+
+                timer0: timer0@ffc02700 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffc02700 0x100>;
+                };
+
+                timer1: timer1@ffc02800 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffc02800 0x100>;
+                };
+
+                timer2: timer2@ffd00000 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffd00000 0x100>;
+                };
+
+                timer3: timer3@ffd00100 {
+                        compatible = "snps,dw-apb-timer";
+                        interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0xffd01000 0x100>;
+                };
+
+                uart0: serial0@ffc02000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02000 0x100>;
+                        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uart1: serial1@ffc02100 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02100 0x100>;
+                        interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                usbphy0: usbphy@0 {
+                        #phy-cells = <0>;
+                        compatible = "usb-nop-xceiv";
+                        status = "okay";
+                };
+
+                usb0: usb@ffb00000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb00000 0xffff>;
+                        interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+
+                usb1: usb@ffb40000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb40000 0xffff>;
+                        interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+
+                watchdog0: watchdog@ffd00200 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd00200 0x100>;
+                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                watchdog1: watchdog@ffd00300 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd00300 0x100>;
+                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
new file mode 100755
index 000000000000..3015ce8d3057
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10.dtsi"
+
+/ {
+        model = "Altera SOCFPGA Arria 10";
+        compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rootwait";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+
+        soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <25000000>;
+                                };
+                        };
+                };
+
+                serial0@ffc02000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 28c05e7a31c9..06db951e06f8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -49,3 +49,7 @@
                 };
         };
 };
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
new file mode 100644
index 000000000000..a8c00ee7522a
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -0,0 +1,151 @@
+/*
+ * Device Tree for the ST-Ericsson Nomadik S8815 board
+ * Produced by Calao Systems
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "ste-nomadik-stn8815.dtsi"
+
+/ {
+        model = "Nomadik STN8815NHK";
+        compatible = "st,nomadik-nhk-15";
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
+        };
+
+        aliases {
+                stmpe-i2c0 = &stmpe0;
+                stmpe-i2c1 = &stmpe1;
+        };
+
+        pinctrl {
+                stmpe2401_1 {
+                        stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
+                                nhk_cfg1 {
+                                        ste,pins = "GPIO76_B20"; // IRQ line
+                                        ste,input = <0>;
+                                };
+                                nhk_cfg2 {
+                                        ste,pins = "GPIO77_B8"; // reset line
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+                stmpe2401_2 {
+                        stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
+                                nhk_cfg1 {
+                                        ste,pins = "GPIO78_A8"; // IRQ line
+                                        ste,input = <0>;
+                                };
+                                nhk_cfg2 {
+                                        ste,pins = "GPIO79_C9"; // reset line
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+        };
+
+        src@101e0000 {
+                /* These chrystal outputs are not used on this board */
+                disable-sxtalo;
+                disable-mxtalo;
+        };
+
+        /* This is where the interrupt is routed on the NHK-15 debug board */
+        external-bus@34000000 {
+                compatible = "simple-bus";
+                reg = <0x34000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x34000000 0x1000000>;
+                ethernet@300 {
+                        compatible = "smsc,lan91c111";
+                        reg = <0x300 0x0fd00>;
+                        reg-io-width = <2>;
+                        reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>;
+                        interrupt-parent = <&stmpe_gpio44>;
+                        interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+                };
+        };
+
+        i2c0 {
+                stmpe0: stmpe2401@43 {
+                        compatible = "st,stmpe2401";
+                        reg = <0x43>;
+                        reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77
+                        interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76
+                        interrupt-parent = <&gpio2>;
+                        interrupt-controller;
+                        wakeup-source;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&stmpe2401_1_nhk_mode>;
+                        stmpe_gpio43: stmpe_gpio {
+                                compatible = "st,stmpe-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                /* Some pins in alternate functions */
+                                st,norequest-mask = <0xf0f002>;
+                        };
+                        stmpe_keypad {
+                                compatible = "st,stmpe-keypad";
+                                debounce-interval = <64>;
+                                st,scan-count = <8>;
+                                st,no-autorepeat;
+                                keypad,num-rows = <8>;
+                                keypad,num-columns = <8>;
+                                linux,keymap = <0x00020072 // Vol down
+                                                0x00030073 // Vol up
+                                                0x0100009e // Back
+                                                0x010100e3 // TV out
+                                                0x01020098 // Lock
+                                                0x0103013b // Start
+                                                0x020000a3 // Next
+                                                0x020100a4 // Play
+                                                0x020200a5 // Prev
+                                                0x02030160 // OK
+                                                0x03000069 // Left
+                                                0x0301006a // Right
+                                                0x03020067 // Up
+                                                0x0303006c>; // Down
+                        };
+                };
+                stmpe1: stmpe2401@44 {
+                        compatible = "st,stmpe2401";
+                        reg = <0x44>;
+                        reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79
+                        interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78
+                        interrupt-parent = <&gpio2>;
+                        interrupt-controller;
+                        wakeup-source;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&stmpe2401_2_nhk_mode>;
+                        stmpe_gpio44: stmpe_gpio {
+                                compatible = "st,stmpe-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                };
+        };
+
+        amba {
+                mmcsd: sdi@101f6000 {
+                        cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>;
+                        wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        /* Custom board node with GPIO pins to active etc */
+        usb-s8815 {
+                /* This will turn off SATA so that MMC/SD can thrive */
+                mmcsd-gpio {
+                        gpios = <&stmpe_gpio44 2 0x1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 90d8b6c7a205..e411ff7769fe 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -4,6 +4,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "ste-nomadik-stn8815.dtsi"
 
 / {
@@ -14,14 +15,6 @@
                 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
         };
 
-        /* This is where the interrupt is routed on the S8815 board */
-        external-bus@34000000 {
-                ethernet@300 {
-                        interrupt-parent = <&gpio3>;
-                        interrupts = <8 0x1>;
-                };
-        };
-
         src@101e0000 {
                 /* These chrystal drivers are not used on this board */
                 disable-sxtalo;
@@ -47,6 +40,14 @@
                                 };
                         };
                 };
+                gpioi2c {
+                        gpioi2c_default_mode: gpioi2c_default {
+                                gpioi2c_default_cfg {
+                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
+                                        ste,input = <0>;
+                                };
+                        };
+                };
                 user-led {
                         user_led_default_mode: user_led_default {
                                 user_led_default_cfg {
@@ -65,6 +66,45 @@
                 };
         };
 
+        /* Ethernet */
+        external-bus@34000000 {
+                compatible = "simple-bus";
+                reg = <0x34000000 0x1000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x34000000 0x1000000>;
+                ethernet@300 {
+                        compatible = "smsc,lan91c111";
+                        reg = <0x300 0x0fd00>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+                };
+        };
+
+        /* GPIO I2C connected to the USB portions of the STw4811 only */
+        gpio-i2c {
+                compatible = "i2c-gpio";
+                gpios = <&gpio2 10 0>, /* sda */
+                        <&gpio2 9 0>; /* scl */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpioi2c_default_mode>;
+
+                stw4811@2d {
+                           compatible = "st,stw4811-usb";
+                           reg = <0x2d>;
+                };
+        };
+
+
+        /* Configure card detect for the uSD slot */
+        amba {
+                mmcsd: sdi@101f6000 {
+                        cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+
         /* Custom board node with GPIO pins to active etc */
         usb-s8815 {
                 /* This will bias the MMC/SD card detect line */
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index dbcf521b017f..f435ff20aefe 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -117,7 +117,7 @@
                         mmcsd_default_mux: mmcsd_mux {
                                 mmcsd_default_mux {
                                         ste,function = "mmcsd";
-                                        ste,pins = "mmcsd_a_1";
+                                        ste,pins = "mmcsd_a_1", "mmcsd_b_1";
                                 };
                         };
                         mmcsd_default_mode: mmcsd_default {
@@ -127,9 +127,9 @@
                                         ste,output = <0>;
                                 };
                                 mmcsd_default_cfg2 {
-                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
                                         ste,pins = "GPIO10_C11", "GPIO15_A12",
-                                        "GPIO16_C13";
+                                        "GPIO16_C13", "GPIO23_D15";
                                         ste,output = <1>;
                                 };
                                 mmcsd_default_cfg3 {
@@ -169,21 +169,11 @@
                                 };
                         };
                 };
-                i2c2 {
-                        i2c2_default_mode: i2c2_default {
-                                i2c2_default_cfg {
-                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
-                                        ste,input = <0>;
-                                };
-                        };
-                };
         };
 
         src: src@101e0000 {
                 compatible = "stericsson,nomadik-src";
                 reg = <0x101e0000 0x1000>;
-                disable-sxtalo;
-                disable-mxtalo;
 
                 /*
                  * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
@@ -683,18 +673,6 @@
                 };
         };
 
-        external-bus@34000000 {
-                compatible = "simple-bus";
-                reg = <0x34000000 0x1000000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x34000000 0x1000000>;
-                ethernet@300 {
-                        compatible = "smsc,lan91c111";
-                        reg = <0x300 0x0fd00>;
-                };
-        };
-
         /* I2C0 connected to the STw4811 power management chip */
         i2c0 {
                 compatible = "st,nomadik-i2c", "arm,primecell";
@@ -749,22 +727,6 @@
                 };
         };
 
-        /* I2C2 connected to the USB portions of the STw4811 only */
-        i2c2 {
-                compatible = "i2c-gpio";
-                gpios = <&gpio2 10 0>, /* sda */
-                        <&gpio2 9 0>; /* scl */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c2_default_mode>;
-
-                stw4811@2d {
-                           compatible = "st,stw4811-usb";
-                           reg = <0x2d>;
-                };
-        };
-
         amba {
                 compatible = "arm,amba-bus";
                 #address-cells = <1>;
@@ -844,7 +806,6 @@
                         bus-width = <4>;
                         cap-mmc-highspeed;
                         cap-sd-highspeed;
-                        cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
                         vmmc-supply = <&vmmc_regulator>;
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92e5f82..261d5e2c48d2 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,13 +7,15 @@
  * published by the Free Software Foundation.
  */
 /dts-v1/;
-#include "stih407.dtsi"
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stihxxx-b2120.dtsi"
 / {
         model = "STiH407 B2120";
         compatible = "st,stih407-b2120", "st,stih407";
 
         chosen {
-                bootargs = "console=ttyAS0,115200";
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
                 linux,stdout-path = &sbc_serial0;
         };
 
@@ -26,53 +28,4 @@
                 ttyAS0 = &sbc_serial0;
         };
 
-        soc {
-                sbc_serial0: serial@9530000 {
-                        status = "okay";
-                };
-
-                leds {
-                        compatible = "gpio-leds";
-                        red {
-                                #gpio-cells = <2>;
-                                label = "Front Panel LED";
-                                gpios = <&pio4 1 0>;
-                                linux,default-trigger = "heartbeat";
-                        };
-                        green {
-                                #gpio-cells = <2>;
-                                gpios = <&pio1 3 0>;
-                                default-state = "off";
-                        };
-                };
-
-                i2c@9842000 {
-                        status = "okay";
-                };
-
-                i2c@9843000 {
-                        status = "okay";
-                };
-
-                i2c@9844000 {
-                        status = "okay";
-                };
-
-                i2c@9845000 {
-                        status = "okay";
-                };
-
-                i2c@9540000 {
-                        status = "okay";
-                };
-
-                /* SSC11 to HDMI */
-                i2c@9541000 {
-                        status = "okay";
-                        /* HDMI V1.3a supports Standard mode only */
-                        clock-frequency = <100000>;
-                        st,i2c-min-scl-pulse-width-us = <0>;
-                        st,i2c-min-sda-pulse-width-us = <5>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f009f3..e65744fc12ab 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,8 +5,13 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <dt-bindings/clock/stih407-clks.h>
 / {
         clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
                 /*
                  * Fixed 30MHz oscillator inputs to SoC
                  */
@@ -19,10 +24,59 @@
                 /*
                  * ARM Peripheral clock for timers
                  */
-                arm_periph_clk: arm-periph-clk {
+                arm_periph_clk: clk-m-a9-periphs {
                         #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <600000000>;
+                        compatible = "fixed-factor-clock";
+
+                        clocks = <&clk_m_a9>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+
+                /*
+                 * A9 PLL.
+                 */
+                clockgen-a9@92b0000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x92b0000 0xffff>;
+
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+
+                /*
+                 * ARM CPU related clocks.
+                 */
+                clk_m_a9: clk-m-a9@92b0000 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+                        reg = <0x92b0000 0x10000>;
+
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_s_c0_flexgen 13>,
+                                 <&clk_m_a9_ext2f_div2>;
+                };
+
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+
+                        clocks = <&clk_s_c0_flexgen 13>;
+
+                        clock-output-names = "clk-m-a9-ext2f-div2";
+
+                        clock-div = <2>;
+                        clock-mult = <1>;
                 };
 
                 /*
@@ -35,5 +89,238 @@
                         clock-frequency = <200000000>;
                         clock-output-names = "clk-s-icn-reg-0";
                 };
+
+                clockgen-a@090ff000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x90ff000 0x1000>;
+
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-a0-pll-ofd-0";
+                        };
+
+                        clk_s_a0_flexgen: clk-s-a0-flexgen {
+                                compatible = "st,flexgen";
+
+                                #clock-cells = <1>;
+
+                                clocks = <&clk_s_a0_pll 0>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-ic-lmi0";
+                        };
+                };
+
+                clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-C", "st,quadfs";
+                        reg = <0x9103000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-c0-fs0-ch0",
+                                             "clk-s-c0-fs0-ch1",
+                                             "clk-s-c0-fs0-ch2",
+                                             "clk-s-c0-fs0-ch3";
+                };
+
+                clk_s_c0: clockgen-c@09103000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9103000 0x1000>;
+
+                        clk_s_c0_pll0: clk-s-c0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-c0-pll0-odf-0";
+                        };
+
+                        clk_s_c0_pll1: clk-s-c0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-c0-pll1-odf-0";
+                        };
+
+                        clk_s_c0_flexgen: clk-s-c0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_c0_pll0 0>,
+                                         <&clk_s_c0_pll1 0>,
+                                         <&clk_s_c0_quadfs 0>,
+                                         <&clk_s_c0_quadfs 1>,
+                                         <&clk_s_c0_quadfs 2>,
+                                         <&clk_s_c0_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-icn-gpu",
+                                                     "clk-fdma",
+                                                     "clk-nand",
+                                                     "clk-hva",
+                                                     "clk-proc-stfe",
+                                                     "clk-proc-tp",
+                                                     "clk-rx-icn-dmu",
+                                                     "clk-rx-icn-hva",
+                                                     "clk-icn-cpu",
+                                                     "clk-tx-icn-dmu",
+                                                     "clk-mmc-0",
+                                                     "clk-mmc-1",
+                                                     "clk-jpegdec",
+                                                     "clk-ext2fa9",
+                                                     "clk-ic-bdisp-0",
+                                                     "clk-ic-bdisp-1",
+                                                     "clk-pp-dmu",
+                                                     "clk-vid-dmu",
+                                                     "clk-dss-lpc",
+                                                     "clk-st231-aud-0",
+                                                     "clk-st231-gp-1",
+                                                     "clk-st231-dmu",
+                                                     "clk-icn-lmi",
+                                                     "clk-tx-icn-disp-1",
+                                                     "clk-icn-sbc",
+                                                     "clk-stfe-frc2",
+                                                     "clk-eth-phy",
+                                                     "clk-eth-ref-phyclk",
+                                                     "clk-flash-promip",
+                                                     "clk-main-disp",
+                                                     "clk-aux-disp",
+                                                     "clk-compo-dvp";
+                        };
+                };
+
+                clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9104000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d0-fs0-ch0",
+                                             "clk-s-d0-fs0-ch1",
+                                             "clk-s-d0-fs0-ch2",
+                                             "clk-s-d0-fs0-ch3";
+                };
+
+                clockgen-d0@09104000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9104000 0x1000>;
+
+                        clk_s_d0_flexgen: clk-s-d0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d0_quadfs 0>,
+                                         <&clk_s_d0_quadfs 1>,
+                                         <&clk_s_d0_quadfs 2>,
+                                         <&clk_s_d0_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-pcm-0",
+                                                     "clk-pcm-1",
+                                                     "clk-pcm-2",
+                                                     "clk-spdiff";
+                        };
+                };
+
+                clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9106000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d2-fs0-ch0",
+                                             "clk-s-d2-fs0-ch1",
+                                             "clk-s-d2-fs0-ch2",
+                                             "clk-s-d2-fs0-ch3";
+                };
+
+                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                clockgen-d2@x9106000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9106000 0x1000>;
+
+                        clk_s_d2_flexgen: clk-s-d2-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d2_quadfs 0>,
+                                         <&clk_s_d2_quadfs 1>,
+                                         <&clk_s_d2_quadfs 2>,
+                                         <&clk_s_d2_quadfs 3>,
+                                         <&clk_sysin>,
+                                         <&clk_sysin>,
+                                         <&clk_tmdsout_hdmi>;
+
+                                clock-output-names = "clk-pix-main-disp",
+                                                     "clk-pix-pip",
+                                                     "clk-pix-gdp1",
+                                                     "clk-pix-gdp2",
+                                                     "clk-pix-gdp3",
+                                                     "clk-pix-gdp4",
+                                                     "clk-pix-aux-disp",
+                                                     "clk-denc",
+                                                     "clk-pix-hddac",
+                                                     "clk-hddac",
+                                                     "clk-sddac",
+                                                     "clk-pix-dvo",
+                                                     "clk-dvo",
+                                                     "clk-pix-hdmi",
+                                                     "clk-tmds-hdmi",
+                                                     "clk-ref-hdmiphy";
+                                                     };
+                };
+
+                clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9107000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d3-fs0-ch0",
+                                             "clk-s-d3-fs0-ch1",
+                                             "clk-s-d3-fs0-ch2",
+                                             "clk-s-d3-fs0-ch3";
+                };
+
+                clockgen-d3@9107000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9107000 0x1000>;
+
+                        clk_s_d3_flexgen: clk-s-d3-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d3_quadfs 0>,
+                                         <&clk_s_d3_quadfs 1>,
+                                         <&clk_s_d3_quadfs 2>,
+                                         <&clk_s_d3_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-stfe-frc1",
+                                                     "clk-tsout-0",
+                                                     "clk-tsout-1",
+                                                     "clk-mchi",
+                                                     "clk-vsens-compo",
+                                                     "clk-frc1-remote",
+                                                     "clk-lpc-0",
+                                                     "clk-lpc-1";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 4f9024f19866..3e31d32133b8 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -6,8 +6,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * publishhed by the Free Software Foundation.
  */
-#include "stih407-clock.dtsi"
 #include "stih407-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih407-resets.h>
 / {
         #address-cells = <1>;
         #size-cells = <1>;
@@ -63,6 +63,21 @@
                 ranges;
                 compatible = "simple-bus";
 
+                powerdown: powerdown-controller {
+                        compatible = "st,stih407-powerdown";
+                        #reset-cells = <1>;
+                };
+
+                softreset: softreset-controller {
+                        compatible = "st,stih407-softreset";
+                        #reset-cells = <1>;
+                };
+
+                picophyreset: picophyreset-controller {
+                        compatible = "st,stih407-picophyreset";
+                        #reset-cells = <1>;
+                };
+
                 syscfg_sbc: sbc-syscfg@9620000 {
                         compatible = "st,stih407-sbc-syscfg", "syscon";
                         reg = <0x9620000 0x1000>;
@@ -104,7 +119,7 @@
                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_serial0>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                         status = "disabled";
                 };
@@ -115,7 +130,7 @@
                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_serial1>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                         status = "disabled";
                 };
@@ -126,7 +141,7 @@
                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_serial2>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 
                         status = "disabled";
                 };
@@ -158,7 +173,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                         reg = <0x9840000 0x110>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
@@ -171,7 +186,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         reg = <0x9841000 0x110>;
                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
@@ -184,7 +199,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         reg = <0x9842000 0x110>;
                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
@@ -197,7 +212,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         reg = <0x9843000 0x110>;
                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
@@ -210,7 +225,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         reg = <0x9844000 0x110>;
                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
@@ -223,7 +238,7 @@
                         compatible = "st,comms-ssc4-i2c";
                         reg = <0x9845000 0x110>;
                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk_ext2f_a9>;
+                        clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
                         clock-names = "ssc";
                         clock-frequency = <400000>;
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 000000000000..2f61a9960dee
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih410.dtsi"
+#include "stihxxx-b2120.dtsi"
+/ {
+        model = "STiH410 B2120";
+        compatible = "st,stih410-b2120", "st,stih410";
+
+        chosen {
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
+                linux,stdout-path = &sbc_serial0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x80000000>;
+        };
+
+        aliases {
+                ttyAS0 = &sbc_serial0;
+        };
+};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 000000000000..6b5803a30096
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih410-clks.h>
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                compatible = "st,stih410-clk", "simple-bus";
+
+                /*
+                 * Fixed 30MHz oscillator inputs to SoC
+                 */
+                clk_sysin: clk-sysin {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                        clock-output-names = "CLK_SYSIN";
+                };
+
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: clk-m-a9-periphs {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&clk_m_a9>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+
+                /*
+                 * A9 PLL.
+                 */
+                clockgen-a9@92b0000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x92b0000 0xffff>;
+
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+
+                /*
+                 * ARM CPU related clocks.
+                 */
+                clk_m_a9: clk-m-a9@92b0000 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+                        reg = <0x92b0000 0x10000>;
+
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_s_c0_flexgen 13>,
+                                 <&clk_m_a9_ext2f_div2>;
+                };
+
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+
+                        clocks = <&clk_s_c0_flexgen 13>;
+
+                        clock-output-names = "clk-m-a9-ext2f-div2";
+
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                clk_ext2f_a9: clockgen-c0@13 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <200000000>;
+                        clock-output-names = "clk-s-icn-reg-0";
+                };
+
+                clockgen-a@090ff000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x90ff000 0x1000>;
+
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-a0-pll-ofd-0";
+                        };
+
+                        clk_s_a0_flexgen: clk-s-a0-flexgen {
+                                compatible = "st,flexgen";
+
+                                #clock-cells = <1>;
+
+                                clocks = <&clk_s_a0_pll 0>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-ic-lmi0",
+                                                     "clk-ic-lmi1";
+                        };
+                };
+
+                clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-C", "st,quadfs";
+                        reg = <0x9103000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-c0-fs0-ch0",
+                                             "clk-s-c0-fs0-ch1",
+                                             "clk-s-c0-fs0-ch2",
+                                             "clk-s-c0-fs0-ch3";
+                };
+
+                clk_s_c0: clockgen-c@09103000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9103000 0x1000>;
+
+                        clk_s_c0_pll0: clk-s-c0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-c0-pll0-odf-0";
+                        };
+
+                        clk_s_c0_pll1: clk-s-c0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+
+                                clocks = <&clk_sysin>;
+
+                                clock-output-names = "clk-s-c0-pll1-odf-0";
+                        };
+
+                        clk_s_c0_flexgen: clk-s-c0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_c0_pll0 0>,
+                                         <&clk_s_c0_pll1 0>,
+                                         <&clk_s_c0_quadfs 0>,
+                                         <&clk_s_c0_quadfs 1>,
+                                         <&clk_s_c0_quadfs 2>,
+                                         <&clk_s_c0_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-icn-gpu",
+                                                     "clk-fdma",
+                                                     "clk-nand",
+                                                     "clk-hva",
+                                                     "clk-proc-stfe",
+                                                     "clk-proc-tp",
+                                                     "clk-rx-icn-dmu",
+                                                     "clk-rx-icn-hva",
+                                                     "clk-icn-cpu",
+                                                     "clk-tx-icn-dmu",
+                                                     "clk-mmc-0",
+                                                     "clk-mmc-1",
+                                                     "clk-jpegdec",
+                                                     "clk-ext2fa9",
+                                                     "clk-ic-bdisp-0",
+                                                     "clk-ic-bdisp-1",
+                                                     "clk-pp-dmu",
+                                                     "clk-vid-dmu",
+                                                     "clk-dss-lpc",
+                                                     "clk-st231-aud-0",
+                                                     "clk-st231-gp-1",
+                                                     "clk-st231-dmu",
+                                                     "clk-icn-lmi",
+                                                     "clk-tx-icn-disp-1",
+                                                     "clk-icn-sbc",
+                                                     "clk-stfe-frc2",
+                                                     "clk-eth-phy",
+                                                     "clk-eth-ref-phyclk",
+                                                     "clk-flash-promip",
+                                                     "clk-main-disp",
+                                                     "clk-aux-disp",
+                                                     "clk-compo-dvp",
+                                                     "clk-tx-icn-hades",
+                                                     "clk-rx-icn-hades",
+                                                     "clk-icn-reg-16",
+                                                     "clk-pp-hades",
+                                                     "clk-clust-hades",
+                                                     "clk-hwpe-hades",
+                                                     "clk-fc-hades";
+                        };
+                };
+
+                clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9104000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d0-fs0-ch0",
+                                             "clk-s-d0-fs0-ch1",
+                                             "clk-s-d0-fs0-ch2",
+                                             "clk-s-d0-fs0-ch3";
+                };
+
+                clockgen-d0@09104000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9104000 0x1000>;
+
+                        clk_s_d0_flexgen: clk-s-d0-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d0_quadfs 0>,
+                                         <&clk_s_d0_quadfs 1>,
+                                         <&clk_s_d0_quadfs 2>,
+                                         <&clk_s_d0_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-pcm-0",
+                                                     "clk-pcm-1",
+                                                     "clk-pcm-2",
+                                                     "clk-spdiff",
+                                                     "clk-pcmr10-master",
+                                                     "clk-usb2-phy";
+                        };
+                };
+
+                clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9106000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d2-fs0-ch0",
+                                             "clk-s-d2-fs0-ch1",
+                                             "clk-s-d2-fs0-ch2",
+                                             "clk-s-d2-fs0-ch3";
+                };
+
+                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                clockgen-d2@x9106000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9106000 0x1000>;
+
+                        clk_s_d2_flexgen: clk-s-d2-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d2_quadfs 0>,
+                                         <&clk_s_d2_quadfs 1>,
+                                         <&clk_s_d2_quadfs 2>,
+                                         <&clk_s_d2_quadfs 3>,
+                                         <&clk_sysin>,
+                                         <&clk_sysin>,
+                                         <&clk_tmdsout_hdmi>;
+
+                                clock-output-names = "clk-pix-main-disp",
+                                                     "clk-pix-pip",
+                                                     "clk-pix-gdp1",
+                                                     "clk-pix-gdp2",
+                                                     "clk-pix-gdp3",
+                                                     "clk-pix-gdp4",
+                                                     "clk-pix-aux-disp",
+                                                     "clk-denc",
+                                                     "clk-pix-hddac",
+                                                     "clk-hddac",
+                                                     "clk-sddac",
+                                                     "clk-pix-dvo",
+                                                     "clk-dvo",
+                                                     "clk-pix-hdmi",
+                                                     "clk-tmds-hdmi",
+                                                     "clk-ref-hdmiphy";
+                                                     };
+                };
+
+                clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih407-quadfs660-D", "st,quadfs";
+                        reg = <0x9107000 0x1000>;
+
+                        clocks = <&clk_sysin>;
+
+                        clock-output-names = "clk-s-d3-fs0-ch0",
+                                             "clk-s-d3-fs0-ch1",
+                                             "clk-s-d3-fs0-ch2",
+                                             "clk-s-d3-fs0-ch3";
+                };
+
+                clockgen-d3@9107000 {
+                        compatible = "st,clkgen-c32";
+                        reg = <0x9107000 0x1000>;
+
+                        clk_s_d3_flexgen: clk-s-d3-flexgen {
+                                #clock-cells = <1>;
+                                compatible = "st,flexgen";
+
+                                clocks = <&clk_s_d3_quadfs 0>,
+                                         <&clk_s_d3_quadfs 1>,
+                                         <&clk_s_d3_quadfs 2>,
+                                         <&clk_s_d3_quadfs 3>,
+                                         <&clk_sysin>;
+
+                                clock-output-names = "clk-stfe-frc1",
+                                                     "clk-tsout-0",
+                                                     "clk-tsout-1",
+                                                     "clk-mchi",
+                                                     "clk-vsens-compo",
+                                                     "clk-frc1-remote",
+                                                     "clk-lpc-0",
+                                                     "clk-lpc-1";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
new file mode 100644
index 000000000000..b3e9dfc81c07
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+        soc {
+                pin-controller-rear {
+
+                        usb0 {
+                                pinctrl_usb0: usb2-0 {
+                                        st,pins {
+                                                usb-oc-detect = <&pio35 0 ALT1 IN>;
+                                                usb-pwr-enable = <&pio35 1 ALT1 OUT>;
+                                        };
+                                };
+                        };
+
+                        usb1 {
+                                pinctrl_usb1: usb2-1 {
+                                        st,pins {
+                                                usb-oc-detect = <&pio35 2 ALT1 IN>;
+                                                usb-pwr-enable = <&pio35 3 ALT1 OUT>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
new file mode 100644
index 000000000000..c05627eb717d
--- /dev/null
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih410-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stih410-pinctrl.dtsi"
+/ {
+
+};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 8509a037ae21..3791ad95dbaf 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -11,33 +11,33 @@
 / {
 
         aliases {
-                gpio0   = &PIO0;
-                gpio1   = &PIO1;
-                gpio2   = &PIO2;
-                gpio3   = &PIO3;
-                gpio4   = &PIO4;
-                gpio5   = &PIO5;
-                gpio6   = &PIO6;
-                gpio7   = &PIO7;
-                gpio8   = &PIO8;
-                gpio9   = &PIO9;
-                gpio10  = &PIO10;
-                gpio11  = &PIO11;
-                gpio12  = &PIO12;
-                gpio13  = &PIO13;
-                gpio14  = &PIO14;
-                gpio15  = &PIO15;
-                gpio16  = &PIO16;
-                gpio17  = &PIO17;
-                gpio18  = &PIO18;
-                gpio19  = &PIO100;
-                gpio20  = &PIO101;
-                gpio21  = &PIO102;
-                gpio22  = &PIO103;
-                gpio23  = &PIO104;
-                gpio24  = &PIO105;
-                gpio25  = &PIO106;
-                gpio26  = &PIO107;
+                gpio0   = &pio0;
+                gpio1   = &pio1;
+                gpio2   = &pio2;
+                gpio3   = &pio3;
+                gpio4   = &pio4;
+                gpio5   = &pio5;
+                gpio6   = &pio6;
+                gpio7   = &pio7;
+                gpio8   = &pio8;
+                gpio9   = &pio9;
+                gpio10  = &pio10;
+                gpio11  = &pio11;
+                gpio12  = &pio12;
+                gpio13  = &pio13;
+                gpio14  = &pio14;
+                gpio15  = &pio15;
+                gpio16  = &pio16;
+                gpio17  = &pio17;
+                gpio18  = &pio18;
+                gpio19  = &pio100;
+                gpio20  = &pio101;
+                gpio21  = &pio102;
+                gpio22  = &pio103;
+                gpio23  = &pio104;
+                gpio24  = &pio105;
+                gpio25  = &pio106;
+                gpio26  = &pio107;
         };
 
         soc {
@@ -52,7 +52,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfe610000 0x5000>;
 
-                        PIO0: gpio@fe610000 {
+                        pio0: gpio@fe610000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -60,7 +60,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO0";
                         };
-                        PIO1: gpio@fe611000 {
+                        pio1: gpio@fe611000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -68,7 +68,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO1";
                         };
-                        PIO2: gpio@fe612000 {
+                        pio2: gpio@fe612000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -76,7 +76,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO2";
                         };
-                        PIO3: gpio@fe613000 {
+                        pio3: gpio@fe613000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -84,7 +84,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO3";
                         };
-                        PIO4: gpio@fe614000 {
+                        pio4: gpio@fe614000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -96,8 +96,8 @@
                         sbc_serial1 {
                                 pinctrl_sbc_serial1:sbc_serial1 {
                                         st,pins {
-                                                tx      = <&PIO2 6 ALT3 OUT>;
-                                                rx      = <&PIO2 7 ALT3 IN>;
+                                                tx      = <&pio2 6 ALT3 OUT>;
+                                                rx      = <&pio2 7 ALT3 IN>;
                                         };
                                 };
                         };
@@ -105,15 +105,15 @@
                         keyscan {
                                 pinctrl_keyscan: keyscan {
                                         st,pins {
-                                                keyin0 = <&PIO0 2 ALT2 IN>;
-                                                keyin1 = <&PIO0 3 ALT2 IN>;
-                                                keyin2 = <&PIO0 4 ALT2 IN>;
-                                                keyin3 = <&PIO2 6 ALT2 IN>;
-
-                                                keyout0 = <&PIO1 6 ALT2 OUT>;
-                                                keyout1 = <&PIO1 7 ALT2 OUT>;
-                                                keyout2 = <&PIO0 6 ALT2 OUT>;
-                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                                keyin0 = <&pio0 2 ALT2 IN>;
+                                                keyin1 = <&pio0 3 ALT2 IN>;
+                                                keyin2 = <&pio0 4 ALT2 IN>;
+                                                keyin3 = <&pio2 6 ALT2 IN>;
+
+                                                keyout0 = <&pio1 6 ALT2 OUT>;
+                                                keyout1 = <&pio1 7 ALT2 OUT>;
+                                                keyout2 = <&pio0 6 ALT2 OUT>;
+                                                keyout3 = <&pio2 7 ALT2 OUT>;
                                         };
                                 };
                         };
@@ -121,8 +121,8 @@
                         sbc_i2c0 {
                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                         st,pins {
-                                                sda = <&PIO4 6 ALT1 BIDIR>;
-                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                                sda = <&pio4 6 ALT1 BIDIR>;
+                                                scl = <&pio4 5 ALT1 BIDIR>;
                                         };
                                 };
                         };
@@ -130,8 +130,8 @@
                         sbc_i2c1 {
                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
                                         st,pins {
-                                                sda = <&PIO3 2 ALT2 BIDIR>;
-                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                                sda = <&pio3 2 ALT2 BIDIR>;
+                                                scl = <&pio3 1 ALT2 BIDIR>;
                                         };
                                 };
                         };
@@ -139,7 +139,7 @@
                         rc{
                                 pinctrl_ir: ir0 {
                                         st,pins {
-                                                ir = <&PIO4 0 ALT2 IN>;
+                                                ir = <&pio4 0 ALT2 IN>;
                                         };
                                 };
                         };
@@ -147,49 +147,49 @@
                         gmac1 {
                                 pinctrl_mii1: mii1 {
                                                 st,pins {
-                                                 txd0   = <&PIO0 0 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd1   = <&PIO0 1 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd2   = <&PIO0 2 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txd3   = <&PIO0 3 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txer   = <&PIO0 4 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txen   = <&PIO0 5 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
-                                                 txclk  = <&PIO0 6 ALT1 IN   NICLK      0       CLK_A>;
-                                                 col    = <&PIO0 7 ALT1 IN   BYPASS     1000>;
-                                                 mdio   = <&PIO1 0 ALT1 OUT  BYPASS     0>;
-                                                 mdc    = <&PIO1 1 ALT1 OUT  NICLK      0       CLK_A>;
-                                                 crs    = <&PIO1 2 ALT1 IN   BYPASS     1000>;
-                                                 mdint  = <&PIO1 3 ALT1 IN   BYPASS     0>;
-                                                 rxd0   = <&PIO1 4 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd1   = <&PIO1 5 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd2   = <&PIO1 6 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxd3   = <&PIO1 7 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxdv   = <&PIO2 0 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rx_er  = <&PIO2 1 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
-                                                 rxclk  = <&PIO2 2 ALT1 IN   NICLK      0       CLK_A>;
-                                                 phyclk = <&PIO2 3 ALT1 IN   NICLK      1000    CLK_A>;
+                                                 txd0   = <&pio0 0 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd1   = <&pio0 1 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd2   = <&pio0 2 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd3   = <&pio0 3 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txer   = <&pio0 4 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txen   = <&pio0 5 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txclk  = <&pio0 6 ALT1 IN   NICLK      0       CLK_A>;
+                                                 col    = <&pio0 7 ALT1 IN   BYPASS     1000>;
+                                                 mdio   = <&pio1 0 ALT1 OUT  BYPASS     0>;
+                                                 mdc    = <&pio1 1 ALT1 OUT  NICLK      0       CLK_A>;
+                                                 crs    = <&pio1 2 ALT1 IN   BYPASS     1000>;
+                                                 mdint  = <&pio1 3 ALT1 IN   BYPASS     0>;
+                                                 rxd0   = <&pio1 4 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd1   = <&pio1 5 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd2   = <&pio1 6 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd3   = <&pio1 7 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxdv   = <&pio2 0 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rx_er  = <&pio2 1 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxclk  = <&pio2 2 ALT1 IN   NICLK      0       CLK_A>;
+                                                 phyclk = <&pio2 3 ALT1 IN   NICLK      1000    CLK_A>;
                                         };
                                 };
 
                                 pinctrl_rgmii1: rgmii1-0 {
                                         st,pins {
-                                                 txd0 =  <&PIO0 0 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd1 =  <&PIO0 1 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd2 =  <&PIO0 2 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txd3 =  <&PIO0 3 ALT1 OUT DE_IO        1000    CLK_A>;
-                                                 txen =  <&PIO0 5 ALT1 OUT DE_IO        0       CLK_A>;
-                                                 txclk = <&PIO0 6 ALT1 IN       NICLK   0       CLK_A>;
-                                                 mdio =  <&PIO1 0 ALT1 OUT      BYPASS  0>;
-                                                 mdc =   <&PIO1 1 ALT1 OUT      NICLK   0       CLK_A>;
-                                                 rxd0 =  <&PIO1 4 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd1 =  <&PIO1 5 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd2 =  <&PIO1 6 ALT1 IN DE_IO 0       CLK_A>;
-                                                 rxd3 =  <&PIO1 7 ALT1 IN DE_IO 0       CLK_A>;
-
-                                                 rxdv =   <&PIO2 0 ALT1 IN DE_IO        500     CLK_A>;
-                                                 rxclk =  <&PIO2 2 ALT1 IN      NICLK   0       CLK_A>;
-                                                 phyclk = <&PIO2 3 ALT4 OUT     NICLK   0       CLK_B>;
-
-                                                 clk125= <&PIO3 7 ALT4 IN       NICLK   0       CLK_A>;
+                                                 txd0 =  <&pio0 0 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd1 =  <&pio0 1 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd2 =  <&pio0 2 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd3 =  <&pio0 3 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txen =  <&pio0 5 ALT1 OUT DE_IO        0       CLK_A>;
+                                                 txclk = <&pio0 6 ALT1 IN       NICLK   0       CLK_A>;
+                                                 mdio =  <&pio1 0 ALT1 OUT      BYPASS  0>;
+                                                 mdc =   <&pio1 1 ALT1 OUT      NICLK   0       CLK_A>;
+                                                 rxd0 =  <&pio1 4 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd1 =  <&pio1 5 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd2 =  <&pio1 6 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd3 =  <&pio1 7 ALT1 IN DE_IO 0       CLK_A>;
+
+                                                 rxdv =   <&pio2 0 ALT1 IN DE_IO        500     CLK_A>;
+                                                 rxclk =  <&pio2 2 ALT1 IN      NICLK   0       CLK_A>;
+                                                 phyclk = <&pio2 3 ALT4 OUT     NICLK   0       CLK_B>;
+
+                                                 clk125= <&pio3 7 ALT4 IN       NICLK   0       CLK_A>;
                                         };
                                 };
                         };
@@ -206,7 +206,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfee00000 0x8000>;
 
-                        PIO5: gpio@fee00000 {
+                        pio5: gpio@fee00000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -214,7 +214,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO5";
                         };
-                        PIO6: gpio@fee01000 {
+                        pio6: gpio@fee01000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -222,7 +222,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO6";
                         };
-                        PIO7: gpio@fee02000 {
+                        pio7: gpio@fee02000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -230,7 +230,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO7";
                         };
-                        PIO8: gpio@fee03000 {
+                        pio8: gpio@fee03000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -238,7 +238,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO8";
                         };
-                        PIO9: gpio@fee04000 {
+                        pio9: gpio@fee04000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -246,7 +246,7 @@
                                 reg             = <0x4000 0x100>;
                                 st,bank-name    = "PIO9";
                         };
-                        PIO10: gpio@fee05000 {
+                        pio10: gpio@fee05000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -254,7 +254,7 @@
                                 reg             = <0x5000 0x100>;
                                 st,bank-name    = "PIO10";
                         };
-                        PIO11: gpio@fee06000 {
+                        pio11: gpio@fee06000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -262,7 +262,7 @@
                                 reg             = <0x6000 0x100>;
                                 st,bank-name    = "PIO11";
                         };
-                        PIO12: gpio@fee07000 {
+                        pio12: gpio@fee07000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -274,8 +274,8 @@
                         i2c0 {
                                 pinctrl_i2c0_default: i2c0-default {
                                         st,pins {
-                                                sda = <&PIO9 3 ALT1 BIDIR>;
-                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                                sda = <&pio9 3 ALT1 BIDIR>;
+                                                scl = <&pio9 2 ALT1 BIDIR>;
                                         };
                                 };
                         };
@@ -283,8 +283,8 @@
                         i2c1 {
                                 pinctrl_i2c1_default: i2c1-default {
                                         st,pins {
-                                                sda = <&PIO12 1 ALT1 BIDIR>;
-                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                                sda = <&pio12 1 ALT1 BIDIR>;
+                                                scl = <&pio12 0 ALT1 BIDIR>;
                                         };
                                 };
                         };
@@ -301,7 +301,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfe820000 0x8000>;
 
-                        PIO13: gpio@fe820000 {
+                        pio13: gpio@fe820000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -309,7 +309,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO13";
                         };
-                        PIO14: gpio@fe821000 {
+                        pio14: gpio@fe821000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -317,7 +317,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO14";
                         };
-                        PIO15: gpio@fe822000 {
+                        pio15: gpio@fe822000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -325,7 +325,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO15";
                         };
-                        PIO16: gpio@fe823000 {
+                        pio16: gpio@fe823000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -333,7 +333,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO16";
                         };
-                        PIO17: gpio@fe824000 {
+                        pio17: gpio@fe824000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -341,7 +341,7 @@
                                 reg             = <0x4000 0x100>;
                                 st,bank-name    = "PIO17";
                         };
-                        PIO18: gpio@fe825000 {
+                        pio18: gpio@fe825000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -353,8 +353,8 @@
                         serial2 {
                                 pinctrl_serial2: serial2-0 {
                                         st,pins {
-                                                tx      = <&PIO17 4 ALT2 OUT>;
-                                                rx      = <&PIO17 5 ALT2 IN>;
+                                                tx      = <&pio17 4 ALT2 OUT>;
+                                                rx      = <&pio17 5 ALT2 IN>;
                                         };
                                 };
                         };
@@ -362,73 +362,94 @@
                         gmac0{
                                 pinctrl_mii0: mii0 {
                                         st,pins {
-                                         mdint =        <&PIO13 6 ALT2  IN      BYPASS          0>;
-                                         txen =         <&PIO13 7 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-
-                                         txd0 =         <&PIO14 0 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         txd1 =         <&PIO14 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         txd2 =         <&PIO14 2 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
-                                         txd3 =         <&PIO14 3 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
-
-                                         txclk =        <&PIO15 0 ALT2  IN      NICLK           0       CLK_A>;
-                                         txer =         <&PIO15 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
-                                         crs =          <&PIO15 2 ALT2  IN      BYPASS          1000>;
-                                         col =          <&PIO15 3 ALT2  IN      BYPASS          1000>;
-                                         mdio  =        <&PIO15 4 ALT2  OUT     BYPASS  3000>;
-                                         mdc   =        <&PIO15 5 ALT2  OUT     NICLK   0       CLK_B>;
-
-                                         rxd0 =         <&PIO16 0 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd1 =         <&PIO16 1 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd2 =         <&PIO16 2 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxd3 =         <&PIO16 3 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxdv =         <&PIO15 6 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rx_er =        <&PIO15 7 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
-                                         rxclk =        <&PIO17 0 ALT2  IN      NICLK           0       CLK_A>;
-                                         phyclk =       <&PIO13 5 ALT2  OUT     NICLK   1000    CLK_A>;
+                                         mdint =        <&pio13 6 ALT2  IN      BYPASS          0>;
+                                         txen =         <&pio13 7 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+
+                                         txd0 =         <&pio14 0 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd1 =         <&pio14 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd2 =         <&pio14 2 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+                                         txd3 =         <&pio14 3 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+
+                                         txclk =        <&pio15 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         txer =         <&pio15 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         crs =          <&pio15 2 ALT2  IN      BYPASS          1000>;
+                                         col =          <&pio15 3 ALT2  IN      BYPASS          1000>;
+                                         mdio  =        <&pio15 4 ALT2  OUT     BYPASS  3000>;
+                                         mdc   =        <&pio15 5 ALT2  OUT     NICLK   0       CLK_B>;
+
+                                         rxd0 =         <&pio16 0 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd1 =         <&pio16 1 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd2 =         <&pio16 2 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd3 =         <&pio16 3 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxdv =         <&pio15 6 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rx_er =        <&pio15 7 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxclk =        <&pio17 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         phyclk =       <&pio13 5 ALT2  OUT     NICLK   1000    CLK_A>;
 
                                         };
                                 };
 
                         pinctrl_gmii0: gmii0 {
                                 st,pins {
-                                         mdint =        <&PIO13 6       ALT2 IN         BYPASS  0>;
-                                         mdio  =        <&PIO15 4       ALT2 OUT        BYPASS  3000>;
-                                         mdc   =        <&PIO15 5       ALT2 OUT        NICLK   0       CLK_B>;
-                                         txen =         <&PIO13 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-
-                                         txd0 =         <&PIO14 0       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         txd1 =         <&PIO14 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         txd2 =         <&PIO14 2       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd3 =         <&PIO14 3       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd4 =         <&PIO14 4       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd5 =         <&PIO14 5       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd6 =         <&PIO14 6       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-                                         txd7 =         <&PIO14 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
-
-                                         txclk =        <&PIO15 0       ALT2 IN         NICLK   0       CLK_A>;
-                                         txer =         <&PIO15 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
-                                         crs =          <&PIO15 2       ALT2 IN         BYPASS  1000>;
-                                         col =          <&PIO15 3       ALT2 IN         BYPASS  1000>;
-                                         rxdv =         <&PIO15 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rx_er =        <&PIO15 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-
-                                         rxd0 =         <&PIO16 0       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd1 =         <&PIO16 1       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd2 =         <&PIO16 2       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd3 =         <&PIO16 3       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd4 =         <&PIO16 4       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd5 =         <&PIO16 5       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd6 =         <&PIO16 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-                                         rxd7 =         <&PIO16 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
-
-                                         rxclk =        <&PIO17 0       ALT2 IN NICLK   0       CLK_A>;
-                                         clk125 =       <&PIO17 6       ALT1 IN NICLK   0       CLK_A>;
-                                         phyclk =       <&PIO13 5       ALT4 OUT NICLK   0       CLK_B>;
+                                         mdint =        <&pio13 6       ALT2 IN         BYPASS  0>;
+                                         mdio  =        <&pio15 4       ALT2 OUT        BYPASS  3000>;
+                                         mdc   =        <&pio15 5       ALT2 OUT        NICLK   0       CLK_B>;
+                                         txen =         <&pio13 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+
+                                         txd0 =         <&pio14 0       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd1 =         <&pio14 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd2 =         <&pio14 2       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd3 =         <&pio14 3       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd4 =         <&pio14 4       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd5 =         <&pio14 5       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd6 =         <&pio14 6       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd7 =         <&pio14 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+
+                                         txclk =        <&pio15 0       ALT2 IN         NICLK   0       CLK_A>;
+                                         txer =         <&pio15 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         crs =          <&pio15 2       ALT2 IN         BYPASS  1000>;
+                                         col =          <&pio15 3       ALT2 IN         BYPASS  1000>;
+                                         rxdv =         <&pio15 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rx_er =        <&pio15 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+
+                                         rxd0 =         <&pio16 0       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd1 =         <&pio16 1       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd2 =         <&pio16 2       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd3 =         <&pio16 3       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd4 =         <&pio16 4       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd5 =         <&pio16 5       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd6 =         <&pio16 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd7 =         <&pio16 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+
+                                         rxclk =        <&pio17 0       ALT2 IN NICLK   0       CLK_A>;
+                                         clk125 =       <&pio17 6       ALT1 IN NICLK   0       CLK_A>;
+                                         phyclk =       <&pio13 5       ALT4 OUT NICLK   0       CLK_B>;
 
 
                                         };
                                 };
                         };
+
+                        mmc0 {
+                                pinctrl_mmc0: mmc0 {
+                                        st,pins {
+                                                mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0  = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data1  = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data2  = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data3  = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                cmd    = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
+                                                wp     = <&pio15 3 ALT4 IN>;
+                                                data4  = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data5  = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data6  = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data7  = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                pwr    = <&pio17 1 ALT4 OUT>;
+                                                cd     = <&pio17 2 ALT4 IN>;
+                                                led    = <&pio17 3 ALT4 OUT>;
+                                        };
+                                };
+                        };
                 };
 
                 pin-controller-left {
@@ -442,7 +463,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfd6b0000 0x3000>;
 
-                        PIO100: gpio@fd6b0000 {
+                        pio100: gpio@fd6b0000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -450,7 +471,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO100";
                         };
-                        PIO101: gpio@fd6b1000 {
+                        pio101: gpio@fd6b1000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -458,7 +479,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO101";
                         };
-                        PIO102: gpio@fd6b2000 {
+                        pio102: gpio@fd6b2000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -479,7 +500,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfd330000 0x5000>;
 
-                        PIO103: gpio@fd330000 {
+                        pio103: gpio@fd330000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -487,7 +508,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO103";
                         };
-                        PIO104: gpio@fd331000 {
+                        pio104: gpio@fd331000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -495,7 +516,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO104";
                         };
-                        PIO105: gpio@fd332000 {
+                        pio105: gpio@fd332000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -503,7 +524,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO105";
                         };
-                        PIO106: gpio@fd333000 {
+                        pio106: gpio@fd333000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -511,7 +532,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO106";
                         };
-                        PIO107: gpio@fd334000 {
+                        pio107: gpio@fd334000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index a0f6f75fe3b5..9198c12765ea 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -218,5 +218,17 @@
                         resets  = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
                                   <&softreset STIH415_KEYSCAN_SOFTRESET>;
                 };
+
+                mmc0: sdhci@fe81e000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81e000 0x1000>;
+                        interrupts      = <GIC_SPI 145 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc0>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 4e2df66b99ea..200a81844765 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -12,4 +12,26 @@
 / {
         model = "STiH416 B2020";
         compatible = "st,stih416-b2020", "st,stih416";
+
+        soc {
+                mmc1: sdhci@fe81f000 {
+                        status       = "okay";
+                        bus-width    = <8>;
+                        non-removable;
+                };
+
+                miphy365x_phy: phy@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
+
+                sata0: sata@fe380000{
+                        status = "okay";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..961799e1dc51 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -19,17 +19,37 @@
                         red {
                                 #gpio-cells             = <1>;
                                 label                   = "Front Panel LED";
-                                gpios                   = <&PIO4 1>;
+                                gpios                   = <&pio4 1>;
                                 linux,default-trigger   = "heartbeat";
                         };
                         green {
-                                gpios                   = <&PIO1 3>;
+                                gpios                   = <&pio1 3>;
                                 default-state           = "off";
                         };
                 };
 
                 ethernet1: dwmac@fef08000 {
-                        snps,reset-gpio = <&PIO0 7>;
+                        snps,reset-gpio = <&pio0 7>;
+                };
+
+                mmc1: sdhci@fe81f000 {
+                        status       = "okay";
+                        bus-width    = <8>;
+                        non-removable;
+                };
+
+                miphy365x_phy: phy@fe382000 {
+                        phy_port0: port@fe382000 {
+                                st,sata-gen = <3>;
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                st,pcie-tx-pol-inv;
+                        };
+                };
+
+                sata0: sata@fe380000{
+                        status = "okay";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index ee6c119e261e..9cccf2d6aa26 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -12,36 +12,36 @@
 / {
 
         aliases {
-                gpio0   = &PIO0;
-                gpio1   = &PIO1;
-                gpio2   = &PIO2;
-                gpio3   = &PIO3;
-                gpio4   = &PIO4;
-                gpio5   = &PIO40;
-                gpio6   = &PIO5;
-                gpio7   = &PIO6;
-                gpio8   = &PIO7;
-                gpio9   = &PIO8;
-                gpio10  = &PIO9;
-                gpio11  = &PIO10;
-                gpio12  = &PIO11;
-                gpio13  = &PIO12;
-                gpio14  = &PIO30;
-                gpio15  = &PIO31;
-                gpio16  = &PIO13;
-                gpio17  = &PIO14;
-                gpio18  = &PIO15;
-                gpio19  = &PIO16;
-                gpio20  = &PIO17;
-                gpio21  = &PIO18;
-                gpio22  = &PIO100;
-                gpio23  = &PIO101;
-                gpio24  = &PIO102;
-                gpio25  = &PIO103;
-                gpio26  = &PIO104;
-                gpio27  = &PIO105;
-                gpio28  = &PIO106;
-                gpio29  = &PIO107;
+                gpio0   = &pio0;
+                gpio1   = &pio1;
+                gpio2   = &pio2;
+                gpio3   = &pio3;
+                gpio4   = &pio4;
+                gpio5   = &pio40;
+                gpio6   = &pio5;
+                gpio7   = &pio6;
+                gpio8   = &pio7;
+                gpio9   = &pio8;
+                gpio10  = &pio9;
+                gpio11  = &pio10;
+                gpio12  = &pio11;
+                gpio13  = &pio12;
+                gpio14  = &pio30;
+                gpio15  = &pio31;
+                gpio16  = &pio13;
+                gpio17  = &pio14;
+                gpio18  = &pio15;
+                gpio19  = &pio16;
+                gpio20  = &pio17;
+                gpio21  = &pio18;
+                gpio22  = &pio100;
+                gpio23  = &pio101;
+                gpio24  = &pio102;
+                gpio25  = &pio103;
+                gpio26  = &pio104;
+                gpio27  = &pio105;
+                gpio28  = &pio106;
+                gpio29  = &pio107;
         };
 
         soc {
@@ -56,7 +56,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfe610000 0x6000>;
 
-                        PIO0: gpio@fe610000 {
+                        pio0: gpio@fe610000 {
                                 gpio-controller;
                                 #gpio-cells = <1>;
                                 interrupt-controller;
@@ -64,7 +64,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO0";
                         };
-                        PIO1: gpio@fe611000 {
+                        pio1: gpio@fe611000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -72,7 +72,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO1";
                         };
-                        PIO2: gpio@fe612000 {
+                        pio2: gpio@fe612000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -80,7 +80,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO2";
                         };
-                        PIO3: gpio@fe613000 {
+                        pio3: gpio@fe613000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -88,7 +88,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO3";
                         };
-                        PIO4: gpio@fe614000 {
+                        pio4: gpio@fe614000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -96,7 +96,7 @@
                                 reg             = <0x4000 0x100>;
                                 st,bank-name    = "PIO4";
                         };
-                        PIO40: gpio@fe615000 {
+                        pio40: gpio@fe615000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -109,15 +109,15 @@
                         rc{
                                 pinctrl_ir: ir0 {
                                         st,pins {
-                                                ir = <&PIO4 0 ALT2 IN>;
+                                                ir = <&pio4 0 ALT2 IN>;
                                         };
                                 };
                         };
                         sbc_serial1 {
                                 pinctrl_sbc_serial1: sbc_serial1 {
                                         st,pins {
-                                                tx      = <&PIO2 6 ALT3 OUT>;
-                                                rx      = <&PIO2 7 ALT3 IN>;
+                                                tx      = <&pio2 6 ALT3 OUT>;
+                                                rx      = <&pio2 7 ALT3 IN>;
                                         };
                                 };
                         };
@@ -125,15 +125,15 @@
                         keyscan {
                                 pinctrl_keyscan: keyscan {
                                         st,pins {
-                                                keyin0 = <&PIO0 2 ALT2 IN>;
-                                                keyin1 = <&PIO0 3 ALT2 IN>;
-                                                keyin2 = <&PIO0 4 ALT2 IN>;
-                                                keyin3 = <&PIO2 6 ALT2 IN>;
-
-                                                keyout0 = <&PIO1 6 ALT2 OUT>;
-                                                keyout1 = <&PIO1 7 ALT2 OUT>;
-                                                keyout2 = <&PIO0 6 ALT2 OUT>;
-                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                                keyin0 = <&pio0 2 ALT2 IN>;
+                                                keyin1 = <&pio0 3 ALT2 IN>;
+                                                keyin2 = <&pio0 4 ALT2 IN>;
+                                                keyin3 = <&pio2 6 ALT2 IN>;
+
+                                                keyout0 = <&pio1 6 ALT2 OUT>;
+                                                keyout1 = <&pio1 7 ALT2 OUT>;
+                                                keyout2 = <&pio0 6 ALT2 OUT>;
+                                                keyout3 = <&pio2 7 ALT2 OUT>;
                                         };
                                 };
                         };
@@ -141,8 +141,17 @@
                         sbc_i2c0 {
                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                         st,pins {
-                                                sda = <&PIO4 6 ALT1 BIDIR>;
-                                                scl = <&PIO4 5 ALT1 BIDIR>;
+                                                sda = <&pio4 6 ALT1 BIDIR>;
+                                                scl = <&pio4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        usb {
+                                pinctrl_usb3: usb3 {
+                                        st,pins {
+                                                oc-detect = <&pio40 0 ALT1 IN>;
+                                                pwr-enable = <&pio40 1 ALT1 OUT>;
                                         };
                                 };
                         };
@@ -150,8 +159,8 @@
                         sbc_i2c1 {
                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
                                         st,pins {
-                                                sda = <&PIO3 2 ALT2 BIDIR>;
-                                                scl = <&PIO3 1 ALT2 BIDIR>;
+                                                sda = <&pio3 2 ALT2 BIDIR>;
+                                                scl = <&pio3 1 ALT2 BIDIR>;
                                         };
                                 };
                         };
@@ -159,51 +168,51 @@
                         gmac1 {
                                 pinctrl_mii1: mii1 {
                                         st,pins {
-                                                txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
-                                                col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
-
-                                                mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
-                                                mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
-                                                crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
-                                                mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
-                                                rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-
-                                                rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
-                                                phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+                                                txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
+                                                col =   <&pio0 7 ALT1 IN BYPASS 1000>;
+
+                                                mdio =  <&pio1 0 ALT1 OUT BYPASS 1500>;
+                                                mdc =   <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                                crs =   <&pio1 2 ALT1 IN BYPASS 1000>;
+                                                mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+                                                rxd0 =  <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+                                                rxdv =  <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
+                                                phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
                                         };
                                 };
                                 pinctrl_rgmii1: rgmii1-0 {
                                         st,pins {
-                                                txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
-                                                txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
-                                                txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
-
-                                                mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
-                                                mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
-                                                rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
-                                                rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
-
-                                                rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
-                                                rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
-                                                phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
-
-                                                clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+                                                txd0 =  <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd1 =  <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd2 =  <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd3 =  <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txen =  <&pio0 5 ALT1 OUT DE_IO 0   CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN  NICLK 0   CLK_A>;
+
+                                                mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
+                                                mdc  = <&pio1 1 ALT1 OUT NICLK  0 CLK_A>;
+                                                rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
+
+                                                rxdv   = <&pio2 0 ALT1 IN  DE_IO 500 CLK_A>;
+                                                rxclk  = <&pio2 2 ALT1 IN  NICLK 0   CLK_A>;
+                                                phyclk = <&pio2 3 ALT4 OUT NICLK 0   CLK_B>;
+
+                                                clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
                                         };
                                 };
                         };
@@ -220,7 +229,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfee00000 0x10000>;
 
-                        PIO5: gpio@fee00000 {
+                        pio5: gpio@fee00000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -228,7 +237,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO5";
                         };
-                        PIO6: gpio@fee01000 {
+                        pio6: gpio@fee01000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -236,7 +245,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO6";
                         };
-                        PIO7: gpio@fee02000 {
+                        pio7: gpio@fee02000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -244,7 +253,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO7";
                         };
-                        PIO8: gpio@fee03000 {
+                        pio8: gpio@fee03000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -252,7 +261,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO8";
                         };
-                        PIO9: gpio@fee04000 {
+                        pio9: gpio@fee04000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -260,7 +269,7 @@
                                 reg             = <0x4000 0x100>;
                                 st,bank-name    = "PIO9";
                         };
-                        PIO10: gpio@fee05000 {
+                        pio10: gpio@fee05000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -268,7 +277,7 @@
                                 reg             = <0x5000 0x100>;
                                 st,bank-name    = "PIO10";
                         };
-                        PIO11: gpio@fee06000 {
+                        pio11: gpio@fee06000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -276,7 +285,7 @@
                                 reg             = <0x6000 0x100>;
                                 st,bank-name    = "PIO11";
                         };
-                        PIO12: gpio@fee07000 {
+                        pio12: gpio@fee07000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -284,7 +293,7 @@
                                 reg             = <0x7000 0x100>;
                                 st,bank-name    = "PIO12";
                         };
-                        PIO30: gpio@fee08000 {
+                        pio30: gpio@fee08000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -292,7 +301,7 @@
                                 reg             = <0x8000 0x100>;
                                 st,bank-name    = "PIO30";
                         };
-                        PIO31: gpio@fee09000 {
+                        pio31: gpio@fee09000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -304,7 +313,7 @@
                         serial2-oe {
                                 pinctrl_serial2_oe: serial2-1 {
                                         st,pins {
-                                                output-enable   = <&PIO11 3 ALT2 OUT>;
+                                                output-enable   = <&pio11 3 ALT2 OUT>;
                                         };
                                 };
                         };
@@ -312,17 +321,27 @@
                         i2c0 {
                                 pinctrl_i2c0_default: i2c0-default {
                                         st,pins {
-                                                sda = <&PIO9 3 ALT1 BIDIR>;
-                                                scl = <&PIO9 2 ALT1 BIDIR>;
+                                                sda = <&pio9 3 ALT1 BIDIR>;
+                                                scl = <&pio9 2 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+
+                        usb {
+                                pinctrl_usb0: usb0 {
+                                        st,pins {
+                                                oc-detect = <&pio9 4 ALT1 IN>;
+                                                pwr-enable = <&pio9 5 ALT1 OUT>;
                                         };
                                 };
                         };
 
+
                         i2c1 {
                                 pinctrl_i2c1_default: i2c1-default {
                                         st,pins {
-                                                sda = <&PIO12 1 ALT1 BIDIR>;
-                                                scl = <&PIO12 0 ALT1 BIDIR>;
+                                                sda = <&pio12 1 ALT1 BIDIR>;
+                                                scl = <&pio12 0 ALT1 BIDIR>;
                                         };
                                 };
                         };
@@ -330,12 +349,12 @@
                         fsm {
                                 pinctrl_fsm: fsm {
                                         st,pins {
-                                                spi-fsm-clk  = <&PIO12 2 ALT1 OUT>;
-                                                spi-fsm-cs   = <&PIO12 3 ALT1 OUT>;
-                                                spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
-                                                spi-fsm-miso = <&PIO12 5 ALT1 IN>;
-                                                spi-fsm-hol  = <&PIO12 6 ALT1 OUT>;
-                                                spi-fsm-wp   = <&PIO12 7 ALT1 OUT>;
+                                                spi-fsm-clk  = <&pio12 2 ALT1 OUT>;
+                                                spi-fsm-cs   = <&pio12 3 ALT1 OUT>;
+                                                spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
+                                                spi-fsm-miso = <&pio12 5 ALT1 IN>;
+                                                spi-fsm-hol  = <&pio12 6 ALT1 OUT>;
+                                                spi-fsm-wp   = <&pio12 7 ALT1 OUT>;
                                         };
                                 };
                         };
@@ -352,7 +371,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfe820000 0x6000>;
 
-                        PIO13: gpio@fe820000 {
+                        pio13: gpio@fe820000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -360,7 +379,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO13";
                         };
-                        PIO14: gpio@fe821000 {
+                        pio14: gpio@fe821000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -368,7 +387,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO14";
                         };
-                        PIO15: gpio@fe822000 {
+                        pio15: gpio@fe822000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -376,7 +395,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO15";
                         };
-                        PIO16: gpio@fe823000 {
+                        pio16: gpio@fe823000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -384,7 +403,7 @@
                                 reg             = <0x3000 0x100>;
                                 st,bank-name    = "PIO16";
                         };
-                        PIO17: gpio@fe824000 {
+                        pio17: gpio@fe824000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -392,7 +411,7 @@
                                 reg             = <0x4000 0x100>;
                                 st,bank-name    = "PIO17";
                         };
-                        PIO18: gpio@fe825000 {
+                        pio18: gpio@fe825000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -405,8 +424,8 @@
                         serial2 {
                                 pinctrl_serial2: serial2-0 {
                                         st,pins {
-                                                tx      = <&PIO17 4 ALT2 OUT>;
-                                                rx      = <&PIO17 5 ALT2 IN>;
+                                                tx      = <&pio17 4 ALT2 OUT>;
+                                                rx      = <&pio17 5 ALT2 IN>;
                                         };
                                 };
                         };
@@ -414,28 +433,28 @@
                         gmac0 {
                                 pinctrl_mii0: mii0 {
                                         st,pins {
-                                                mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
-                                                txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-                                                txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
-
-                                                txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
-                                                txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
-                                                crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
-                                                col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
-                                                mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
-                                                mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
-
-                                                rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
-                                                rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
-                                                phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+                                                mdint = <&pio13 6 ALT2 IN  BYPASS      0>;
+                                                txen =  <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd0 =  <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 =  <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 =  <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                                txd3 =  <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+
+                                                txclk = <&pio15 0 ALT2 IN  NICLK       0 CLK_A>;
+                                                txer =  <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                crs = <&pio15 2 ALT2 IN  BYPASS 1000>;
+                                                col = <&pio15 3 ALT2 IN  BYPASS 1000>;
+                                                mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
+                                                mdc = <&pio15 5 ALT2 OUT NICLK  0    CLK_B>;
+
+                                                rxd0 =  <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv =  <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
+                                                phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
                                         };
                                 };
 
@@ -445,25 +464,79 @@
                                 };
                                 pinctrl_rgmii0: rgmii0 {
                                         st,pins {
-                                                 phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
-                                                 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
-                                                 txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
-                                                 txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
-                                                 txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
-                                                 txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
-                                                 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
-
-                                                 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
-                                                 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
-
-                                                 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
-                                                 rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
-                                                 rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
-                                                 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
-
-                                                 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+                                                 phyclk = <&pio13  5 ALT4 OUT NICLK 0 CLK_B>;
+                                                 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
+                                                 txd0  = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd1  = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd2  = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txd3  = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
+
+                                                 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
+                                                 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
+
+                                                 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxd0 =<&pio16 0 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd1 =<&pio16 1 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd2 =<&pio16 2 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd3  =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
+
+                                                 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
+                                        };
+                                };
+                        };
+
+                        mmc0 {
+                                pinctrl_mmc0: mmc0 {
+                                        st,pins {
+                                                mmcclk  = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0   = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data1   = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data2   = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data3   = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                cmd     = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
+                                                wp      = <&pio15 3 ALT4 IN>;
+                                                data4   = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
+                                                data5   = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
+                                                data6   = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
+                                                data7   = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
+                                                pwr     = <&pio17 1 ALT4 OUT>;
+                                                cd      = <&pio17 2 ALT4 IN>;
+                                                led     = <&pio17 3 ALT4 OUT>;
+                                        };
+                                };
+                        };
+                        mmc1 {
+                                pinctrl_mmc1: mmc1 {
+                                        st,pins {
+                                                mmcclk  = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
+                                                data0   = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
+                                                data1   = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
+                                                data2   = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
+                                                data3   = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
+                                                cmd     = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
+                                                data4   = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
+                                                data5   = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
+                                                data6   = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
+                                                data7   = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
+                                                pwr     = <&pio16 2 ALT3 OUT>;
+                                                nreset  = <&pio13 6 ALT3 OUT>;
+                                        };
+                                };
+                        };
+
+                        usb {
+                                pinctrl_usb1: usb1 {
+                                        st,pins {
+                                                oc-detect = <&pio18 0 ALT1 IN>;
+                                                pwr-enable = <&pio18 1 ALT1 OUT>;
+                                        };
+                                };
+                                pinctrl_usb2: usb2 {
+                                        st,pins {
+                                                oc-detect = <&pio18 2 ALT1 IN>;
+                                                pwr-enable = <&pio18 3 ALT1 OUT>;
                                         };
                                 };
                         };
@@ -480,7 +553,7 @@
                         interrupt-names = "irqmux";
                         ranges          = <0 0xfd6b0000 0x3000>;
 
-                        PIO100: gpio@fd6b0000 {
+                        pio100: gpio@fd6b0000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -488,7 +561,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO100";
                         };
-                        PIO101: gpio@fd6b1000 {
+                        pio101: gpio@fd6b1000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -496,7 +569,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO101";
                         };
-                        PIO102: gpio@fd6b2000 {
+                        pio102: gpio@fd6b2000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -517,7 +590,7 @@
                         interrupt-names = "irqmux";
                         ranges                  = <0 0xfd330000 0x5000>;
 
-                        PIO103: gpio@fd330000 {
+                        pio103: gpio@fd330000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -525,7 +598,7 @@
                                 reg             = <0 0x100>;
                                 st,bank-name    = "PIO103";
                         };
-                        PIO104: gpio@fd331000 {
+                        pio104: gpio@fd331000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -533,7 +606,7 @@
                                 reg             = <0x1000 0x100>;
                                 st,bank-name    = "PIO104";
                         };
-                        PIO105: gpio@fd332000 {
+                        pio105: gpio@fd332000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -541,7 +614,7 @@
                                 reg             = <0x2000 0x100>;
                                 st,bank-name    = "PIO105";
                         };
-                        PIO106: gpio@fd333000 {
+                        pio106: gpio@fd333000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
@@ -550,7 +623,7 @@
                                 st,bank-name    = "PIO106";
                         };
 
-                        PIO107: gpio@fd334000 {
+                        pio107: gpio@fd334000 {
                                 gpio-controller;
                                 #gpio-cells     = <1>;
                                 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 84758d76d064..fad9073ddeed 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
 #include "stih41x.dtsi"
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
+
+#include <dt-bindings/phy/phy-miphy365x.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset-controller/stih416-resets.h>
 / {
@@ -236,5 +238,212 @@
                         resets  = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
                                   <&softreset STIH416_KEYSCAN_SOFTRESET>;
                 };
+
+                temp0 {
+                        compatible = "st,stih416-sas-thermal";
+                        clock-names = "thermal";
+                        clocks = <&clockgen_c_vcc 14>;
+
+                        status = "okay";
+                };
+
+                temp1@fdfe8000 {
+                        compatible = "st,stih416-mpe-thermal";
+                        reg = <0xfdfe8000 0x10>;
+                        clocks = <&clockgen_e 3>;
+                        clock-names = "thermal";
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
+
+                        status = "okay";
+                };
+
+                mmc0: sdhci@fe81e000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81e000 0x1000>;
+                        interrupts      = <GIC_SPI 127 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc0>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 1>;
+                };
+
+                mmc1: sdhci@fe81f000 {
+                        compatible      = "st,sdhci";
+                        status          = "disabled";
+                        reg             = <0xfe81f000 0x1000>;
+                        interrupts      = <GIC_SPI 128 IRQ_TYPE_NONE>;
+                        interrupt-names = "mmcirq";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mmc1>;
+                        clock-names     = "mmc";
+                        clocks          = <&clk_s_a1_ls 8>;
+                };
+
+                miphy365x_phy: phy@fe382000 {
+                        compatible      = "st,miphy365x-phy";
+                        st,syscfg       = <&syscfg_rear>;
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        ranges;
+
+                        phy_port0: port@fe382000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+
+                        phy_port1: port@fe38a000 {
+                                #phy-cells = <1>;
+                                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
+                                reg-names = "sata", "pcie", "syscfg";
+                        };
+                };
+
+                sata0: sata@fe380000 {
+                        compatible      = "st,sti-ahci";
+                        reg             = <0xfe380000 0x1000>;
+                        interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                        interrupt-names = "hostc";
+                        phys            = <&phy_port0 MIPHY_TYPE_SATA>;
+                        phy-names       = "sata-phy";
+                        resets          = <&powerdown STIH416_SATA0_POWERDOWN>,
+                                          <&softreset STIH416_SATA0_SOFTRESET>;
+                        reset-names     = "pwr-dwn", "sw-rst";
+                        clock-names     = "ahci_clk";
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
+
+                        status          = "disabled";
+                };
+
+                usb2_phy: phy@0 {
+                        compatible = "st,stih416-usb-phy";
+                        #phy-cells = <0>;
+                        st,syscfg = <&syscfg_rear>;
+                        clocks = <&clk_sysin>;
+                        clock-names = "osc_phy";
+                };
+
+                ehci0: usb@fe1ffe00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe1ffe00 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB0_POWERDOWN>,
+                                 <&softreset STIH416_USB0_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ohci0: usb@fe1ffc00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe1ffc00 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        status = "okay";
+                        resets = <&powerdown STIH416_USB0_POWERDOWN>,
+                                 <&softreset STIH416_USB0_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ehci1: usb@fe203e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe203e00 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb1>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB1_POWERDOWN>,
+                                 <&softreset STIH416_USB1_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ohci1: usb@fe203c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe203c00 0x100>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB1_POWERDOWN>,
+                                 <&softreset STIH416_USB1_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ehci2: usb@fe303e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe303e00 0x100>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb2>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB2_POWERDOWN>,
+                                 <&softreset STIH416_USB2_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ohci2: usb@fe303c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe303c00 0x100>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB2_POWERDOWN>,
+                                 <&softreset STIH416_USB2_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ehci3: usb@fe343e00 {
+                        compatible = "st,st-ehci-300x";
+                        reg = <0xfe343e00 0x100>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb3>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB3_POWERDOWN>,
+                                 <&softreset STIH416_USB3_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
+
+                ohci3: usb@fe343c00 {
+                        compatible = "st,st-ohci-300x";
+                        reg = <0xfe343c00 0x100>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+                        clocks = <&clk_s_a1_ls 0>,
+                                 <&clockgen_b0 0>;
+                        clock-names = "ic", "clk48";
+                        phys = <&usb2_phy>;
+                        phy-names = "usb";
+                        resets = <&powerdown STIH416_USB3_POWERDOWN>,
+                                 <&softreset STIH416_USB3_SOFTRESET>;
+                        reset-names = "power", "softreset";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index b3dd6ca5c2ae..5f91f455f05b 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -35,7 +35,7 @@
                         fp_led {
                                 #gpio-cells = <1>;
                                 label   = "Front Panel LED";
-                                gpios   = <&PIO105 7>;
+                                gpios   = <&pio105 7>;
                                 linux,default-trigger   = "heartbeat";
                         };
                 };
@@ -55,7 +55,7 @@
                         phy-mode                = "mii";
                         pinctrl-0               = <&pinctrl_mii0>;
 
-                        snps,reset-gpio         = <&PIO106 2>;
+                        snps,reset-gpio         = <&pio106 2>;
                         snps,reset-active-low;
                         snps,reset-delays-us    = <0 10000 10000>;
                 };
@@ -65,7 +65,7 @@
                         phy-mode                = "mii";
                         st,tx-retime-src        = "txclk";
 
-                        snps,reset-gpio         = <&PIO4 7>;
+                        snps,reset-gpio         = <&pio4 7>;
                         snps,reset-active-low;
                         snps,reset-delays-us    = <0 10000 10000>;
                 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index d8a84295c328..487d7d87dbef 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -32,11 +32,11 @@
                         red {
                                 #gpio-cells = <1>;
                                 label   = "Front Panel LED";
-                                gpios   = <&PIO4 1>;
+                                gpios   = <&pio4 1>;
                                 linux,default-trigger   = "heartbeat";
                         };
                         green {
-                                gpios   = <&PIO4 7>;
+                                gpios   = <&pio4 7>;
                                 default-state = "off";
                         };
                 };
@@ -68,11 +68,15 @@
                         phy-mode                = "rgmii-id";
                         max-speed               = <1000>;
                         st,tx-retime-src        = "clk_125";
-                        snps,reset-gpio         = <&PIO3 0>;
+                        snps,reset-gpio         = <&pio3 0>;
                         snps,reset-active-low;
                         snps,reset-delays-us    = <0 10000 10000>;
 
                         pinctrl-0       = <&pinctrl_rgmii1>;
                 };
+
+                mmc0: sdhci@fe81e000 {
+                        bus-width = <8>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
index df01c1211b32..f797a0607382 100644
--- a/arch/arm/boot/dts/stih41x-b2020x.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -8,6 +8,10 @@
  */
 / {
         soc {
+                mmc0: sdhci@fe81e000 {
+                        status = "okay";
+                };
+
                 spifsm: spifsm@fe902000 {
                         #address-cells = <1>;
                         #size-cells    = <1>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 000000000000..0074bd49797c
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        soc {
+                sbc_serial0: serial@9530000 {
+                        status = "okay";
+                };
+
+                leds {
+                        compatible = "gpio-leds";
+                        red {
+                                #gpio-cells = <2>;
+                                label = "Front Panel LED";
+                                gpios = <&pio4 1 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        green {
+                                #gpio-cells = <2>;
+                                gpios = <&pio1 3 0>;
+                                default-state = "off";
+                        };
+                };
+
+                i2c@9842000 {
+                        status = "okay";
+                };
+
+                i2c@9843000 {
+                        status = "okay";
+                };
+
+                i2c@9844000 {
+                        status = "okay";
+                };
+
+                i2c@9845000 {
+                        status = "okay";
+                };
+
+                i2c@9540000 {
+                        status = "okay";
+                };
+
+                /* SSC11 to HDMI */
+                i2c@9541000 {
+                        status = "okay";
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        st,i2c-min-scl-pulse-width-us = <0>;
+                        st,i2c-min-sda-pulse-width-us = <5>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 9e99ade35e37..3bcfd81837f0 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -3,12 +3,48 @@
  *
  * Emilio López <emilio@elopez.com.ar>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 1763cc7ec023..f3f2974658e4 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -1,12 +1,48 @@
 /*
  * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 3ce56bfbc0b5..6a310da53f18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -2,12 +2,48 @@
  * Copyright 2012 Stefan Roese
  * Stefan Roese <sr@denx.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 891ea446abae..efc116287e0f 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 6b0c37812ade..3e25ee4d3248 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -3,12 +3,48 @@
  *
  * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index b9ecce60f2e7..8b3f97470249 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index d046d568f5a1..88cf1a531155 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -1,12 +1,48 @@
 /*
  * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6675bcd7860e..ce5994597407 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -2,12 +2,48 @@
  * Copyright 2014 Zoltan HERPAI
  * Zoltan HERPAI <wigyori@uid0.hu>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 380f914b226d..e3ab942fd148 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -27,6 +27,20 @@
                 serial7 = &uart7;
         };
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index ea9519da5764..fe3c559ca6a8 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 43a93762d4f2..1fa2916eafc2 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -1,12 +1,48 @@
 /*
  * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 531272c0e526..81ad4b94e812 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -24,6 +24,20 @@
                 serial3 = &uart3;
         };
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
+
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a8";
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 8b3cd0907b32..eeed1f236ee8 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -6,18 +6,18 @@
  * licensing only applies to this file, and not this project as a
  * whole.
  *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  *     MA 02110-1301 USA
  *
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fa44b026483b..916ee8bb826f 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -1,15 +1,49 @@
 /*
- * Copyright 2012 Maxime Ripard
+ * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
  * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
  *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 429994e1943e..e31d291d14cb 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index 2bbf8867362b..c74a63a39531 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -3,12 +3,48 @@
  *
  * Boris Brezillon <boris.brezillon@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 546cf6eff5c7..c36b4dc89c13 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index f142065b3c1f..6e924d9d2912 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -3,12 +3,48 @@
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index bc6115da5ae1..3ab544f3af4a 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -1,12 +1,48 @@
 /*
  * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -32,13 +68,40 @@
                         status = "okay";
                 };
 
+                usbphy: phy@01c19400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c1a000 {
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1b000 {
+                        status = "okay";
+                };
+
                 pio: pinctrl@01c20800 {
+                        led_pins_m9: led_pins@0 {
+                                allwinner,pins = "PH13";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         mmc0_cd_pin_m9: mmc0_cd_pin@0 {
                                 allwinner,pins = "PH22";
                                 allwinner,function = "gpio_in";
                                 allwinner,drive = <0>;
                                 allwinner,pull = <1>;
                         };
+
+                        usb1_vbus_pin_m9: usb1_vbus_pin@0 {
+                                allwinner,pins = "PC27";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 uart0: serial@01c28000 {
@@ -46,5 +109,35 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                gmac: ethernet@01c30000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_m9>;
+
+                blue {
+                        label = "m9:blue:usr";
+                        gpios = <&pio 7 13 0>;
+                };
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb1_vbus_pin_m9>;
+                gpio = <&pio 2 27 0>;
+                status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2e652e2339e9..a400172a8a52 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -8,18 +8,18 @@
  * licensing only applies to this file, and not this project as a
  * whole.
  *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  *     MA 02110-1301 USA
  *
@@ -62,6 +62,18 @@
                 ethernet0 = &gmac;
         };
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll6 0>;
+                        status = "disabled";
+                };
+        };
 
         cpus {
                 enable-method = "allwinner,sun6i-a31";
@@ -132,11 +144,11 @@
                 };
 
                 pll6: clk@01c20028 {
-                        #clock-cells = <0>;
+                        #clock-cells = <1>;
                         compatible = "allwinner,sun6i-a31-pll6-clk";
                         reg = <0x01c20028 0x4>;
                         clocks = <&osc24M>;
-                        clock-output-names = "pll6";
+                        clock-output-names = "pll6", "pll6x2";
                 };
 
                 cpu: cpu@01c20050 {
@@ -166,7 +178,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                         clock-output-names = "ahb1_mux";
                 };
 
@@ -221,7 +233,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                         clock-output-names = "apb2_mux";
                 };
 
@@ -248,7 +260,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c20088 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "mmc0";
                 };
 
@@ -256,7 +268,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c2008c 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "mmc1";
                 };
 
@@ -264,7 +276,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c20090 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "mmc2";
                 };
 
@@ -272,7 +284,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c20094 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "mmc3";
                 };
 
@@ -280,7 +292,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c200a0 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "spi0";
                 };
 
@@ -288,7 +300,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c200a4 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "spi1";
                 };
 
@@ -296,7 +308,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c200a8 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "spi2";
                 };
 
@@ -304,7 +316,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod0-clk";
                         reg = <0x01c200ac 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
+                        clocks = <&osc24M>, <&pll6 0>;
                         clock-output-names = "spi3";
                 };
 
@@ -364,7 +376,7 @@
 
                         /* DMA controller requires AHB1 clocked from PLL6 */
                         assigned-clocks = <&ahb1_mux>;
-                        assigned-clock-parents = <&pll6>;
+                        assigned-clock-parents = <&pll6 0>;
                 };
 
                 mmc0: mmc@01c0f000 {
@@ -844,7 +856,7 @@
                         ar100: ar100_clk {
                                 compatible = "allwinner,sun6i-a31-ar100-clk";
                                 #clock-cells = <0>;
-                                clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                                clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                                 clock-output-names = "ar100";
                         };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
new file mode 100644
index 000000000000..1cf1214cc068
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "LeMaker Banana Pi";
+        compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                spi0: spi@01c05000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_pins_a>;
+                        status = "okay";
+                };
+
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 10 0>; /* PH10 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                ahci: sata@01c18000 {
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH10";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+
+                        gmac_power_pin_bananapi: gmac_power_pin@0 {
+                                allwinner,pins = "PH23";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        led_pins_bananapi: led_pins@0 {
+                                allwinner,pins = "PH24";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                ir0: ir@01c21800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ir0_pins_a>;
+                        status = "okay";
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_b>;
+                        status = "okay";
+                };
+
+                uart7: serial@01c29c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart7_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
+
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        phy-supply = <&reg_gmac_3v3>;
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_bananapi>;
+
+                green {
+                        label = "bananapi:green:usr";
+                        gpios = <&pio 7 24 0>;
+                };
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gmac_power_pin_bananapi>;
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+                gpio = <&pio 7 23 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c717bc..a281d259b9b8 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -40,6 +40,7 @@
                 };
 
                 usbphy: phy@01c13400 {
+                        usb0_vbus-supply = <&reg_usb0_vbus>;
                         usb1_vbus-supply = <&reg_usb1_vbus>;
                         usb2_vbus-supply = <&reg_usb2_vbus>;
                         status = "okay";
@@ -92,6 +93,13 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        usb0_vbus_pin_a: usb0_vbus_pin@0 {
+                                allwinner,pins = "PH17";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 pwm: pwm@01c20e00 {
@@ -185,6 +193,12 @@
                 status = "okay";
         };
 
+        reg_usb0_vbus: usb0-vbus {
+                pinctrl-0 = <&usb0_vbus_pin_a>;
+                gpio = <&pio 7 17 0>;
+                status = "okay";
+        };
+
         reg_usb1_vbus: usb1-vbus {
                 status = "okay";
         };
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 6a67712d417a..f38bb1a6656c 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -1,12 +1,48 @@
 /*
  * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
new file mode 100644
index 000000000000..b8e568c55271
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "Mele M3";
+        compatible = "mele,m3", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                mmc2: mmc@01c11000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc2_pins_a>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        led_pins_m3: led_pins@0 {
+                                allwinner,pins = "PH20";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                ir0: ir@01c21800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ir0_pins_a>;
+                        status = "okay";
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_m3>;
+
+                blue {
+                        label = "m3:blue:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 1eb8175959a6..3f3ff9693992 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -4,12 +4,48 @@
  * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
  * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
new file mode 100644
index 000000000000..ed364d5e755e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2014 - Iain Paton <ipaton0@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+
+/ {
+        model = "Olimex A20-OLinuXino-LIME2";
+        compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+
+                pinctrl@01c20800 {
+                        ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+                                allwinner,pins = "PC3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        led_pins_olinuxinolime: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+
+                        axp209: pmic@34 {
+                                compatible = "x-powers,axp209";
+                                reg = <0x34>;
+                                interrupt-parent = <&nmi_intc>;
+                                interrupts = <0 8>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+
+                                acin-supply = <&reg_axp_ipsout>;
+                                vin2-supply = <&reg_axp_ipsout>;
+                                vin3-supply = <&reg_axp_ipsout>;
+                                ldo24in-supply = <&reg_axp_ipsout>;
+                                ldo3in-supply = <&reg_axp_ipsout>;
+
+                                regulators {
+                                        vdd_rtc: ldo1 {
+                                                regulator-min-microvolt = <1300000>;
+                                                regulator-max-microvolt = <1300000>;
+                                                regulator-always-on;
+                                        };
+
+                                        avcc: ldo2 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                        };
+
+                                        vcc_csi0: ldo3 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <3500000>;
+                                                regulator-always-on;
+                                        };
+
+                                        vcc_csi1: ldo4 {
+                                                regulator-min-microvolt = <1250000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                        };
+
+                                        vdd_cpu: dcdc2 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <2275000>;
+                                                regulator-always-on;
+                                        };
+
+                                        vdd_int: dcdc3 {
+                                                regulator-min-microvolt = <700000>;
+                                                regulator-max-microvolt = <3500000>;
+                                                regulator-always-on;
+                                        };
+                                };
+                        };
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinolime>;
+
+                green {
+                        label = "a20-olinuxino-lime2:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
+
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+                gpio = <&pio 2 3 0>;
+                status = "okay";
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+
+        reg_axp_ipsout: axp_ipsout {
+                compatible = "regulator-fixed";
+                regulator-name = "axp-ipsout";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 046dfc0d45d8..8dca49b2477b 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -2,12 +2,48 @@
  * Copyright 2014 Zoltan HERPAI
  * Zoltan HERPAI <wigyori@uid0.hu>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82097c905c48..82a524ce28ad 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -8,18 +8,18 @@
  * licensing only applies to this file, and not this project as a
  * whole.
  *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  *     MA 02110-1301 USA
  *
@@ -64,6 +64,20 @@
                 serial7 = &uart7;
         };
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-hdmi";
+                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>;
+                        status = "disabled";
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -552,8 +566,8 @@
                         reg-names = "phy_ctrl", "pmu1", "pmu2";
                         clocks = <&usb_clk 8>;
                         clock-names = "usb_phy";
-                        resets = <&usb_clk 1>, <&usb_clk 2>;
-                        reset-names = "usb1_reset", "usb2_reset";
+                        resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+                        reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
                         status = "disabled";
                 };
 
@@ -677,6 +691,13 @@
                                 allwinner,pull = <0>;
                         };
 
+                        uart3_pins_b: uart3@1 {
+                                allwinner,pins = "PH0", "PH1";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         uart4_pins_a: uart4@0 {
                                 allwinner,pins = "PG10", "PG11";
                                 allwinner,function = "uart4";
@@ -784,6 +805,13 @@
                                 allwinner,pull = <0>;
                         };
 
+                        spi0_pins_a: spi0@0 {
+                                allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
+                                allwinner,function = "spi0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         spi1_pins_a: spi1@0 {
                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
                                 allwinner,function = "spi1";
@@ -819,6 +847,13 @@
                                 allwinner,pull = <1>;
                         };
 
+                        mmc2_pins_a: mmc2@0 {
+                                allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
+                                allwinner,function = "mmc2";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <1>;
+                        };
+
                         mmc3_pins_a: mmc3@0 {
                                 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
                                 allwinner,function = "mmc3";
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index e9b8cca8dcc1..7f2117ce6985 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -3,12 +3,48 @@
  *
  * Chen-Yu Tsai <wens@csie.org>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6146ef15efbe..6086adbf9d74 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -8,18 +8,18 @@
  * licensing only applies to this file, and not this project as a
  * whole.
  *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  *     MA 02110-1301 USA
  *
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
new file mode 100644
index 000000000000..506948f582ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "sun9i-a80.dtsi"
+
+/ {
+        model = "Merrii A80 Optimus Board";
+        compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc {
+                pio: pinctrl@06000800 {
+                        i2c3_pins_a: i2c3@0 {
+                                /* Enable internal pull-up */
+                                allwinner,pull = <1>;
+                        };
+
+                        led_pins_optimus: led-pins@0 {
+                                allwinner,pins = "PH0", "PH1";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart4_pins_a: uart4@0 {
+                                /* Enable internal pull-up */
+                                allwinner,pull = <1>;
+                        };
+                };
+
+                uart0: serial@07000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart4: serial@07001000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart4_pins_a>;
+                        status = "okay";
+                };
+
+                i2c3: i2c@07003400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_optimus>;
+
+                /* The LED names match those found on the board */
+
+                led2 {
+                        label = "optimus:led2:usr";
+                        gpios = <&pio 7 1 0>;
+                };
+
+                /* led3 is on PM15, in R_PIO */
+
+                led4 {
+                        label = "optimus:led4:usr";
+                        gpios = <&pio 7 0 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
new file mode 100644
index 000000000000..494714f67b57
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -0,0 +1,514 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                serial6 = &r_uart;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x1>;
+                };
+
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x2>;
+                };
+
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0x3>;
+                };
+
+                cpu4: cpu@100 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x100>;
+                };
+
+                cpu5: cpu@101 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x101>;
+                };
+
+                cpu6: cpu@102 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x102>;
+                };
+
+                cpu7: cpu@103 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0x103>;
+                };
+        };
+
+        memory {
+                /* 8GB max. with LPAE */
+                reg = <0 0x20000000 0x02 0>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /*
+                 * map 64 bit address range down to 32 bits,
+                 * as the peripherals are all under 512MB.
+                 */
+                ranges = <0 0 0 0x20000000>;
+
+                osc24M: osc24M_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
+                };
+
+                osc32k: osc32k_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
+                };
+
+                pll4: clk@0600000c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-pll4-clk";
+                        reg = <0x0600000c 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
+                };
+
+                pll12: clk@0600002c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-pll4-clk";
+                        reg = <0x0600002c 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll12";
+                };
+
+                gt_clk: clk@0600005c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-gt-clk";
+                        reg = <0x0600005c 0x4>;
+                        clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "gt";
+                };
+
+                ahb0: clk@06000060 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000060 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb0";
+                };
+
+                ahb1: clk@06000064 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000064 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb1";
+                };
+
+                ahb2: clk@06000068 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-ahb-clk";
+                        reg = <0x06000068 0x4>;
+                        clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "ahb2";
+                };
+
+                apb0: clk@06000070 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-apb0-clk";
+                        reg = <0x06000070 0x4>;
+                        clocks = <&osc24M>, <&pll4>;
+                        clock-output-names = "apb0";
+                };
+
+                apb1: clk@06000074 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-apb1-clk";
+                        reg = <0x06000074 0x4>;
+                        clocks = <&osc24M>, <&pll4>;
+                        clock-output-names = "apb1";
+                };
+
+                cci400_clk: clk@06000078 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun9i-a80-gt-clk";
+                        reg = <0x06000078 0x4>;
+                        clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+                        clock-output-names = "cci400";
+                };
+
+                ahb0_gates: clk@06000580 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
+                        reg = <0x06000580 0x4>;
+                        clocks = <&ahb0>;
+                        clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
+                                        "ahb0_ss", "ahb0_sd", "ahb0_nand1",
+                                        "ahb0_nand0", "ahb0_sdram",
+                                        "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
+                                        "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
+                                        "ahb0_spi3";
+                };
+
+                ahb1_gates: clk@06000584 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
+                        reg = <0x06000584 0x4>;
+                        clocks = <&ahb1>;
+                        clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
+                                        "ahb1_gmac", "ahb1_msgbox",
+                                        "ahb1_spinlock", "ahb1_hstimer",
+                                        "ahb1_dma";
+                };
+
+                ahb2_gates: clk@06000588 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
+                        reg = <0x06000588 0x4>;
+                        clocks = <&ahb2>;
+                        clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
+                                        "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
+                                        "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
+                };
+
+                apb0_gates: clk@06000590 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-apb0-gates-clk";
+                        reg = <0x06000590 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_spdif", "apb0_pio",
+                                        "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
+                                        "apb0_lradc", "apb0_gpadc", "apb0_twd",
+                                        "apb0_cirtx";
+                };
+
+                apb1_gates: clk@06000594 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun9i-a80-apb1-gates-clk";
+                        reg = <0x06000594 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                        "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
+                                        "apb1_uart0", "apb1_uart1",
+                                        "apb1_uart2", "apb1_uart3",
+                                        "apb1_uart4", "apb1_uart5";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /*
+                 * map 64 bit address range down to 32 bits,
+                 * as the peripherals are all under 512MB.
+                 */
+                ranges = <0 0 0 0x20000000>;
+
+                gic: interrupt-controller@01c41000 {
+                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                        reg = <0x01c41000 0x1000>,
+                              <0x01c42000 0x1000>,
+                              <0x01c44000 0x2000>,
+                              <0x01c46000 0x2000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupts = <1 9 0xf04>;
+                };
+
+                ahb0_resets: reset@060005a0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a0 0x4>;
+                };
+
+                ahb1_resets: reset@060005a4 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a4 0x4>;
+                };
+
+                ahb2_resets: reset@060005a8 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005a8 0x4>;
+                };
+
+                apb0_resets: reset@060005b0 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005b0 0x4>;
+                };
+
+                apb1_resets: reset@060005b4 {
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        reg = <0x060005b4 0x4>;
+                };
+
+                timer@06000c00 {
+                        compatible = "allwinner,sun4i-a10-timer";
+                        reg = <0x06000c00 0xa0>;
+                        interrupts = <0 18 4>,
+                                     <0 19 4>,
+                                     <0 20 4>,
+                                     <0 21 4>,
+                                     <0 22 4>,
+                                     <0 23 4>;
+
+                        clocks = <&osc24M>;
+                };
+
+                pio: pinctrl@06000800 {
+                        compatible = "allwinner,sun9i-a80-pinctrl";
+                        reg = <0x06000800 0x400>;
+                        interrupts = <0 11 4>,
+                                     <0 15 4>,
+                                     <0 16 4>,
+                                     <0 17 4>,
+                                     <0 120 4>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        i2c3_pins_a: i2c3@0 {
+                                allwinner,pins = "PG10", "PG11";
+                                allwinner,function = "i2c3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PH12", "PH13";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart4_pins_a: uart4@0 {
+                                allwinner,pins = "PG12", "PG13", "PG14", "PG15";
+                                allwinner,function = "uart4";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@07000000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000000 0x400>;
+                        interrupts = <0 0 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        resets = <&apb1_resets 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@07000400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000400 0x400>;
+                        interrupts = <0 1 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        resets = <&apb1_resets 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@07000800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000800 0x400>;
+                        interrupts = <0 2 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        resets = <&apb1_resets 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@07000c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07000c00 0x400>;
+                        interrupts = <0 3 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        resets = <&apb1_resets 19>;
+                        status = "disabled";
+                };
+
+                uart4: serial@07001000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07001000 0x400>;
+                        interrupts = <0 4 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 20>;
+                        resets = <&apb1_resets 20>;
+                        status = "disabled";
+                };
+
+                uart5: serial@07001400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x07001400 0x400>;
+                        interrupts = <0 5 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 21>;
+                        resets = <&apb1_resets 21>;
+                        status = "disabled";
+                };
+
+                i2c0: i2c@07002800 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07002800 0x400>;
+                        interrupts = <0 6 4>;
+                        clocks = <&apb1_gates 0>;
+                        resets = <&apb1_resets 0>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c1: i2c@07002c00 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07002c00 0x400>;
+                        interrupts = <0 7 4>;
+                        clocks = <&apb1_gates 1>;
+                        resets = <&apb1_resets 1>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c2: i2c@07003000 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003000 0x400>;
+                        interrupts = <0 8 4>;
+                        clocks = <&apb1_gates 2>;
+                        resets = <&apb1_resets 2>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c3: i2c@07003400 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003400 0x400>;
+                        interrupts = <0 9 4>;
+                        clocks = <&apb1_gates 3>;
+                        resets = <&apb1_resets 3>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c4: i2c@07003800 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x07003800 0x400>;
+                        interrupts = <0 10 4>;
+                        clocks = <&apb1_gates 4>;
+                        resets = <&apb1_resets 4>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                r_wdt: watchdog@08001000 {
+                        compatible = "allwinner,sun6i-a31-wdt";
+                        reg = <0x08001000 0x20>;
+                        interrupts = <0 36 4>;
+                };
+
+                r_uart: serial@08002800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x08002800 0x400>;
+                        interrupts = <0 38 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&osc24M>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index c9c5b10e03eb..d8876634f965 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -3,12 +3,48 @@
  *
  * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {
@@ -21,6 +57,13 @@
                                 allwinner,pull = <0>;
                         };
 
+                        usb0_vbus_pin_a: usb0_vbus_pin@0 {
+                                allwinner,pins = "PB9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
                         usb1_vbus_pin_a: usb1_vbus_pin@0 {
                                 allwinner,pins = "PH6";
                                 allwinner,function = "gpio_out";
@@ -44,11 +87,24 @@
                 regulator-name = "ahci-5v";
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
                 enable-active-high;
                 gpio = <&pio 1 8 0>;
                 status = "disabled";
         };
 
+        reg_usb0_vbus: usb0-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb0_vbus_pin_a>;
+                regulator-name = "usb0-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 1 9 0>;
+                status = "disabled";
+        };
+
         reg_usb1_vbus: usb1-vbus {
                 compatible = "regulator-fixed";
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index a1b682ea01bd..cbf5a1ae0ca7 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -189,7 +189,7 @@
 
                 /* ALS and Proximity sensor */
                 isl29028@44 {
-                        compatible = "isil,isl29028";
+                        compatible = "isl,isl29028";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
                         interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..56a452bc326c
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/ {
+        chosen {
+                bootargs = "console=ttyLP0,115200";
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sys_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                /* USBH_PEN */
+                usbh_vbus_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbh1_reg>;
+                        reg = <1>;
+                        regulator-name = "usbh_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+                        vin-supply = <&sys_5v0_reg>;
+                };
+        };
+};
+
+&bl {
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <6>;
+        status  = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+
+        /* M41T0M6 real time clock on carrier board */
+        rtc: m41t0m6@68 {
+                compatible = "st,m41t00";
+                reg = <0x68>;
+        };
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&usbh_vbus_reg>;
+};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
new file mode 100644
index 000000000000..82f5728be5c9
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/ {
+        bl: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm0 0 5000000 0>;
+                status = "disabled";
+        };
+};
+
+&adc0 {
+        status = "okay";
+};
+
+&adc1 {
+        status = "okay";
+};
+
+&edma0 {
+        status = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c0>;
+};
+
+&pwm0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm0>;
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart0>;
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&usbdev0 {
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        disable-over-current;
+        status = "okay";
+};
+
+&usbmisc0 {
+        status = "okay";
+};
+
+&usbmisc1 {
+        status = "okay";
+};
+
+&usbphy0 {
+        status = "okay";
+};
+
+&usbphy1 {
+        status = "okay";
+};
+
+&iomuxc {
+        vf610-colibri {
+                pinctrl_gpio_ext: gpio_ext {
+                        fsl,pins = <
+                                VF610_PAD_PTD10__GPIO_89        0x22ed /* EXT_IO_0 */
+                                VF610_PAD_PTD9__GPIO_88         0x22ed /* EXT_IO_1 */
+                                VF610_PAD_PTD26__GPIO_68        0x22ed /* EXT_IO_2 */
+                        >;
+                };
+
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                VF610_PAD_PTB20__GPIO_42        0x219d
+                        >;
+                };
+
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                        >;
+                };
+
+                pinctrl_i2c0: i2c0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB14__I2C0_SCL               0x37ff
+                                VF610_PAD_PTB15__I2C0_SDA               0x37ff
+                        >;
+                };
+
+                pinctrl_pwm0: pwm0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB0__FTM0_CH0                0x1182
+                                VF610_PAD_PTB1__FTM0_CH1                0x1182
+                        >;
+                };
+
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB8__FTM1_CH0                0x1182
+                                VF610_PAD_PTB9__FTM1_CH1                0x1182
+                        >;
+                };
+
+                pinctrl_uart0: uart0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB10__UART0_TX               0x21a2
+                                VF610_PAD_PTB11__UART0_RX               0x21a1
+                        >;
+                };
+
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB4__UART1_TX                0x21a2
+                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                        >;
+                };
+
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD0__UART2_TX                0x21a2
+                                VF610_PAD_PTD1__UART2_RX                0x21a1
+                                VF610_PAD_PTD2__UART2_RTS               0x21a2
+                                VF610_PAD_PTD3__UART2_CTS               0x21a1
+                        >;
+                };
+
+                pinctrl_usbh1_reg: gpio_usb_vbus {
+                        fsl,pins = <
+                                VF610_PAD_PTD4__GPIO_83                 0x22ed
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fc782c4fc52
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf500-colibri.dtsi"
+#include "vf-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri VF50 on Colibri Evaluation Board";
+        compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
+};
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
new file mode 100644
index 000000000000..cee34a32f25b
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "vf500.dtsi"
+#include "vf-colibri.dtsi"
+
+/ {
+        model = "Toradex Colibri VF50 COM";
+        compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
+
+        memory {
+                reg = <0x80000000 0x8000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
new file mode 100644
index 000000000000..de6700542714
--- /dev/null
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "vfxxx.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                a5_cpu: cpu@0 {
+                        compatible = "arm,cortex-a5";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                };
+        };
+
+        soc {
+                interrupt-parent = <&intc>;
+
+                aips-bus@40000000 {
+
+                        intc: interrupt-controller@40002000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                interrupt-controller;
+                                reg = <0x40003000 0x1000>,
+                                      <0x40002100 0x100>;
+                        };
+
+                        global_timer: timer@40002200 {
+                                compatible = "arm,cortex-a9-global-timer";
+                                reg = <0x40002200 0x20>;
+                                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_PLATFORM_BUS>;
+                        };
+                };
+        };
+};
+
+&adc0 {
+        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&adc1 {
+        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&can0 {
+        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&can1 {
+        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dspi0 {
+        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&edma0 {
+        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "edma-tx", "edma-err";
+};
+
+&edma1 {
+        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "edma-tx", "edma-err";
+};
+
+&esdhc1 {
+        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&fec0 {
+        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&fec1 {
+        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ftm {
+        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio1 {
+        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio2 {
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio3 {
+        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio4 {
+        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio5 {
+        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c0 {
+        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pit {
+        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&qspi0 {
+        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai2 {
+        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart2 {
+        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart3 {
+        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart4 {
+        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart5 {
+        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usbdev0 {
+        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usbh1 {
+        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usbphy0 {
+        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usbphy1 {
+        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
index 7fb306679341..10ebe99e2751 100644
--- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -9,38 +9,9 @@
 
 /dts-v1/;
 #include "vf610-colibri.dtsi"
+#include "vf-colibri-eval-v3.dtsi"
 
 / {
         model = "Toradex Colibri VF61 on Colibri Evaluation Board";
         compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
-
-        chosen {
-                bootargs = "console=ttyLP0,115200";
-        };
-};
-
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1>;
-        bus-width = <4>;
-        status = "okay";
-};
-
-&fec1 {
-        phy-mode = "rmii";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1>;
-        status = "okay";
-};
-
-&uart0 {
-        status = "okay";
-};
-
-&uart1 {
-        status = "okay";
-};
-
-&uart2 {
-        status = "okay";
-};
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 0cd83434b073..19fe045b8334 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include "vf610.dtsi"
+#include "vf-colibri.dtsi"
 
 / {
         model = "Toradex Colibri VF61 COM";
@@ -16,108 +17,9 @@
         memory {
                 reg = <0x80000000 0x10000000>;
         };
-
-        clocks {
-                enet_ext {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <50000000>;
-                };
-        };
-
-};
-
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1>;
-        bus-width = <4>;
-};
-
-&fec1 {
-        phy-mode = "rmii";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1>;
 };
 
 &L2 {
         arm,data-latency = <2 1 2>;
         arm,tag-latency = <3 2 3>;
 };
-
-&uart0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-};
-
-&usbdev0 {
-        disable-over-current;
-        status = "okay";
-};
-
-&usbh1 {
-        disable-over-current;
-        status = "okay";
-};
-
-&iomuxc {
-        vf610-colibri {
-                pinctrl_esdhc1: esdhc1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
-                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
-                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
-                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
-                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
-                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
-                                VF610_PAD_PTB20__GPIO_42        0x219d
-                        >;
-                };
-
-                pinctrl_fec1: fec1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
-                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
-                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
-                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
-                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
-                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
-                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
-                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
-                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
-                        >;
-                };
-
-                pinctrl_uart0: uart0grp {
-                        fsl,pins = <
-                                VF610_PAD_PTB10__UART0_TX               0x21a2
-                                VF610_PAD_PTB11__UART0_RX               0x21a1
-                        >;
-                };
-
-                pinctrl_uart1: uart1grp {
-                        fsl,pins = <
-                                VF610_PAD_PTB4__UART1_TX                0x21a2
-                                VF610_PAD_PTB5__UART1_RX                0x21a1
-                        >;
-                };
-
-                pinctrl_uart2: uart2grp {
-                        fsl,pins = <
-                                VF610_PAD_PTD0__UART2_TX                0x21a2
-                                VF610_PAD_PTD1__UART2_RX                0x21a1
-                                VF610_PAD_PTD2__UART2_RTS               0x21a2
-                                VF610_PAD_PTD3__UART2_CTS               0x21a1
-                        >;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index de1b453c2932..fd8758b639f5 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -23,14 +23,16 @@
                 reg = <0x80000000 0x10000000>;
         };
 
-        clocks {
-                enet_ext {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <50000000>;
-                };
+        enet_ext: enet_ext {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
         };
+};
 
+&clks {
+        clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
+        clock-names = "sxosc", "fxosc", "enet_ext";
 };
 
 &esdhc1 {
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 189b6975fe7d..a0f762159cb2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -22,18 +22,16 @@
                 reg = <0x80000000 0x8000000>;
         };
 
-        clocks {
-                audio_ext {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <24576000>;
-                };
+        audio_ext: mclk_osc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24576000>;
+        };
 
-                enet_ext {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <50000000>;
-                };
+        enet_ext: eth_osc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
         };
 
         regulators {
@@ -95,6 +93,11 @@
         status = "okay";
 };
 
+&clks {
+        clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
+        clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
+};
+
 &dspi0 {
         bus-num = <0>;
         pinctrl-names = "default";
@@ -112,10 +115,15 @@
         };
 };
 
+&edma0 {
+        status = "okay";
+};
+
 &esdhc1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
         bus-width = <4>;
+        cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -285,3 +293,19 @@
         disable-over-current;
         status = "okay";
 };
+
+&usbmisc0 {
+        status = "okay";
+};
+
+&usbmisc1 {
+        status = "okay";
+};
+
+&usbphy0 {
+        status = "okay";
+};
+
+&usbphy1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 4d2ec32de96f..5f8eb1bd782b 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -7,481 +7,19 @@
  * (at your option) any later version.
  */
 
-#include "skeleton.dtsi"
-#include "vf610-pinfunc.h"
-#include <dt-bindings/clock/vf610-clock.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "vf500.dtsi"
 
-/ {
-        aliases {
-                can0 = &can0;
-                can1 = &can1;
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
-                serial3 = &uart3;
-                serial4 = &uart4;
-                serial5 = &uart5;
-                gpio0 = &gpio1;
-                gpio1 = &gpio2;
-                gpio2 = &gpio3;
-                gpio3 = &gpio4;
-                gpio4 = &gpio5;
-                usbphy0 = &usbphy0;
-                usbphy1 = &usbphy1;
-        };
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu@0 {
-                        compatible = "arm,cortex-a5";
-                        device_type = "cpu";
-                        reg = <0x0>;
-                        next-level-cache = <&L2>;
-                };
-        };
-
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                sxosc {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
-
-                fxosc {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <24000000>;
-                };
-        };
-
-        soc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
-
-                aips0: aips-bus@40000000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        interrupt-parent = <&intc>;
-                        reg = <0x40000000 0x70000>;
-                        ranges;
-
-                        intc: interrupt-controller@40002000 {
-                                compatible = "arm,cortex-a9-gic";
-                                #interrupt-cells = <3>;
-                                interrupt-controller;
-                                reg = <0x40003000 0x1000>,
-                                      <0x40002100 0x100>;
-                        };
-
-                        L2: l2-cache@40006000 {
-                                compatible = "arm,pl310-cache";
-                                reg = <0x40006000 0x1000>;
-                                cache-unified;
-                                cache-level = <2>;
-                                arm,data-latency = <1 1 1>;
-                                arm,tag-latency = <2 2 2>;
-                        };
-
-                        edma0: dma-controller@40018000 {
-                                #dma-cells = <2>;
-                                compatible = "fsl,vf610-edma";
-                                reg = <0x40018000 0x2000>,
-                                        <0x40024000 0x1000>,
-                                        <0x40025000 0x1000>;
-                                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
-                                                <0 9 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "edma-tx", "edma-err";
-                                dma-channels = <32>;
-                                clock-names = "dmamux0", "dmamux1";
-                                clocks = <&clks VF610_CLK_DMAMUX0>,
-                                        <&clks VF610_CLK_DMAMUX1>;
-                        };
-
-                        can0: flexcan@40020000 {
-                                compatible = "fsl,vf610-flexcan";
-                                reg = <0x40020000 0x4000>;
-                                interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_FLEXCAN0>,
-                                         <&clks VF610_CLK_FLEXCAN0>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart0: serial@40027000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40027000 0x1000>;
-                                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART0>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 2>,
-                                        <&edma0 0 3>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-
-                        uart1: serial@40028000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40028000 0x1000>;
-                                interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART1>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 4>,
-                                        <&edma0 0 5>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-
-                        uart2: serial@40029000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x40029000 0x1000>;
-                                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART2>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 6>,
-                                        <&edma0 0 7>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-
-                        uart3: serial@4002a000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x4002a000 0x1000>;
-                                interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART3>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 8>,
-                                        <&edma0 0 9>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-
-                        dspi0: dspi0@4002c000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-dspi";
-                                reg = <0x4002c000 0x1000>;
-                                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_DSPI0>;
-                                clock-names = "dspi";
-                                spi-num-chipselects = <5>;
-                                status = "disabled";
-                        };
-
-                        sai2: sai@40031000 {
-                                compatible = "fsl,vf610-sai";
-                                reg = <0x40031000 0x1000>;
-                                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_SAI2>;
-                                clock-names = "sai";
-                                dma-names = "tx", "rx";
-                                dmas = <&edma0 0 21>,
-                                        <&edma0 0 20>;
-                                status = "disabled";
-                        };
-
-                        pit: pit@40037000 {
-                                compatible = "fsl,vf610-pit";
-                                reg = <0x40037000 0x1000>;
-                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_PIT>;
-                                clock-names = "pit";
-                        };
-
-                        pwm0: pwm@40038000 {
-                                compatible = "fsl,vf610-ftm-pwm";
-                                #pwm-cells = <3>;
-                                reg = <0x40038000 0x1000>;
-                                clock-names = "ftm_sys", "ftm_ext",
-                                              "ftm_fix", "ftm_cnt_clk_en";
-                                clocks = <&clks VF610_CLK_FTM0>,
-                                        <&clks VF610_CLK_FTM0_EXT_SEL>,
-                                        <&clks VF610_CLK_FTM0_FIX_SEL>,
-                                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
-                                status = "disabled";
-                        };
-
-                        adc0: adc@4003b000 {
-                                compatible = "fsl,vf610-adc";
-                                reg = <0x4003b000 0x1000>;
-                                interrupts = <0 53 0x04>;
-                                clocks = <&clks VF610_CLK_ADC0>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-
-                        wdog@4003e000 {
-                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
-                                reg = <0x4003e000 0x1000>;
-                                clocks = <&clks VF610_CLK_WDT>;
-                                clock-names = "wdog";
-                        };
-
-                        qspi0: quadspi@40044000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-qspi";
-                                reg = <0x40044000 0x1000>;
-                                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_QSPI0_EN>,
-                                        <&clks VF610_CLK_QSPI0>;
-                                clock-names = "qspi_en", "qspi";
-                                status = "disabled";
-                        };
-
-                        iomuxc: iomuxc@40048000 {
-                                compatible = "fsl,vf610-iomuxc";
-                                reg = <0x40048000 0x1000>;
-                                #gpio-range-cells = <3>;
-                        };
-
-                        gpio1: gpio@40049000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
-                                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 0 32>;
-                        };
-
-                        gpio2: gpio@4004a000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
-                                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 32 32>;
-                        };
-
-                        gpio3: gpio@4004b000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
-                                interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 64 32>;
-                        };
-
-                        gpio4: gpio@4004c000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
-                                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 96 32>;
-                        };
-
-                        gpio5: gpio@4004d000 {
-                                compatible = "fsl,vf610-gpio";
-                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
-                                interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                gpio-ranges = <&iomuxc 0 128 7>;
-                        };
-
-                        anatop: anatop@40050000 {
-                                compatible = "fsl,vf610-anatop", "syscon";
-                                reg = <0x40050000 0x400>;
-                        };
-
-                        usbphy0: usbphy@40050800 {
-                                compatible = "fsl,vf610-usbphy";
-                                reg = <0x40050800 0x400>;
-                                interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBPHY0>;
-                                fsl,anatop = <&anatop>;
-                        };
-
-                        usbphy1: usbphy@40050c00 {
-                                compatible = "fsl,vf610-usbphy";
-                                reg = <0x40050c00 0x400>;
-                                interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBPHY1>;
-                                fsl,anatop = <&anatop>;
-                        };
-
-                        i2c0: i2c@40066000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,vf610-i2c";
-                                reg = <0x40066000 0x1000>;
-                                interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_I2C0>;
-                                clock-names = "ipg";
-                                dmas = <&edma0 0 50>,
-                                        <&edma0 0 51>;
-                                dma-names = "rx","tx";
-                                status = "disabled";
-                        };
-
-                        clks: ccm@4006b000 {
-                                compatible = "fsl,vf610-ccm";
-                                reg = <0x4006b000 0x1000>;
-                                #clock-cells = <1>;
-                        };
-
-                        usbdev0: usb@40034000 {
-                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
-                                reg = <0x40034000 0x800>;
-                                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBC0>;
-                                fsl,usbphy = <&usbphy0>;
-                                fsl,usbmisc = <&usbmisc0 0>;
-                                dr_mode = "peripheral";
-                                status = "disabled";
-                        };
-
-                        usbmisc0: usb@40034800 {
-                                #index-cells = <1>;
-                                compatible = "fsl,vf610-usbmisc";
-                                reg = <0x40034800 0x200>;
-                                clocks = <&clks VF610_CLK_USBC0>;
-                        };
-                };
-
-                aips1: aips-bus@40080000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x40080000 0x80000>;
-                        ranges;
-
-                        edma1: dma-controller@40098000 {
-                                #dma-cells = <2>;
-                                compatible = "fsl,vf610-edma";
-                                reg = <0x40098000 0x2000>,
-                                        <0x400a1000 0x1000>,
-                                        <0x400a2000 0x1000>;
-                                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
-                                                <0 11 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "edma-tx", "edma-err";
-                                dma-channels = <32>;
-                                clock-names = "dmamux0", "dmamux1";
-                                clocks = <&clks VF610_CLK_DMAMUX2>,
-                                        <&clks VF610_CLK_DMAMUX3>;
-                        };
-
-                        uart4: serial@400a9000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x400a9000 0x1000>;
-                                interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART4>;
-                                clock-names = "ipg";
-                                status = "disabled";
-                        };
-
-                        uart5: serial@400aa000 {
-                                compatible = "fsl,vf610-lpuart";
-                                reg = <0x400aa000 0x1000>;
-                                interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_UART5>;
-                                clock-names = "ipg";
-                                status = "disabled";
-                        };
-
-                        adc1: adc@400bb000 {
-                                compatible = "fsl,vf610-adc";
-                                reg = <0x400bb000 0x1000>;
-                                interrupts = <0 54 0x04>;
-                                clocks = <&clks VF610_CLK_ADC1>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-
-                        esdhc1: esdhc@400b2000 {
-                                compatible = "fsl,imx53-esdhc";
-                                reg = <0x400b2000 0x1000>;
-                                interrupts = <0 28 0x04>;
-                                clocks = <&clks VF610_CLK_IPG_BUS>,
-                                        <&clks VF610_CLK_PLATFORM_BUS>,
-                                        <&clks VF610_CLK_ESDHC1>;
-                                clock-names = "ipg", "ahb", "per";
-                                status = "disabled";
-                        };
-
-                        usbh1: usb@400b4000 {
-                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
-                                reg = <0x400b4000 0x800>;
-                                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_USBC1>;
-                                fsl,usbphy = <&usbphy1>;
-                                fsl,usbmisc = <&usbmisc1 0>;
-                                dr_mode = "host";
-                                status = "disabled";
-                        };
-
-                        usbmisc1: usb@400b4800 {
-                                #index-cells = <1>;
-                                compatible = "fsl,vf610-usbmisc";
-                                reg = <0x400b4800 0x200>;
-                                clocks = <&clks VF610_CLK_USBC1>;
-                        };
-
-                        ftm: ftm@400b8000 {
-                                compatible = "fsl,ftm-timer";
-                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
-                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
-                                clock-names = "ftm-evt", "ftm-src",
-                                        "ftm-evt-counter-en", "ftm-src-counter-en";
-                                clocks = <&clks VF610_CLK_FTM2>,
-                                        <&clks VF610_CLK_FTM3>,
-                                        <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
-                                        <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
-                                status = "disabled";
-                        };
-
-                        fec0: ethernet@400d0000 {
-                                compatible = "fsl,mvf600-fec";
-                                reg = <0x400d0000 0x1000>;
-                                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_ENET0>,
-                                        <&clks VF610_CLK_ENET0>,
-                                        <&clks VF610_CLK_ENET>;
-                                clock-names = "ipg", "ahb", "ptp";
-                                status = "disabled";
-                        };
-
-                        fec1: ethernet@400d1000 {
-                                compatible = "fsl,mvf600-fec";
-                                reg = <0x400d1000 0x1000>;
-                                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_ENET1>,
-                                        <&clks VF610_CLK_ENET1>,
-                                        <&clks VF610_CLK_ENET>;
-                                clock-names = "ipg", "ahb", "ptp";
-                                status = "disabled";
-                        };
-
-                        can1: flexcan@400d4000 {
-                                compatible = "fsl,vf610-flexcan";
-                                reg = <0x400d4000 0x4000>;
-                                interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks VF610_CLK_FLEXCAN1>,
-                                         <&clks VF610_CLK_FLEXCAN1>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+&a5_cpu {
+        next-level-cache = <&L2>;
+};
 
-                };
+&aips0 {
+        L2: l2-cache@40006000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x40006000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+                arm,data-latency = <1 1 1>;
+                arm,tag-latency = <2 2 2>;
         };
 };
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
new file mode 100644
index 000000000000..505969ae8093
--- /dev/null
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -0,0 +1,437 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        aliases {
+                can0 = &can0;
+                can1 = &can1;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                usbphy0 = &usbphy0;
+                usbphy1 = &usbphy1;
+        };
+
+        fxosc: fxosc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+        };
+
+        sxosc: sxosc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+
+                aips0: aips-bus@40000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        edma0: dma-controller@40018000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40018000 0x2000>,
+                                        <0x40024000 0x1000>,
+                                        <0x40025000 0x1000>;
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX0>,
+                                        <&clks VF610_CLK_DMAMUX1>;
+                                status = "disabled";
+                        };
+
+                        can0: flexcan@40020000 {
+                                compatible = "fsl,vf610-flexcan";
+                                reg = <0x40020000 0x4000>;
+                                clocks = <&clks VF610_CLK_FLEXCAN0>,
+                                         <&clks VF610_CLK_FLEXCAN0>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart0: serial@40027000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40027000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART0>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 2>,
+                                        <&edma0 0 3>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@40028000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40028000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART1>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 4>,
+                                        <&edma0 0 5>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+
+                        uart2: serial@40029000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40029000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART2>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 6>,
+                                        <&edma0 0 7>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+
+                        uart3: serial@4002a000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x4002a000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART3>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 8>,
+                                        <&edma0 0 9>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+
+                        dspi0: dspi0@4002c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-dspi";
+                                reg = <0x4002c000 0x1000>;
+                                clocks = <&clks VF610_CLK_DSPI0>;
+                                clock-names = "dspi";
+                                spi-num-chipselects = <5>;
+                                status = "disabled";
+                        };
+
+                        sai2: sai@40031000 {
+                                compatible = "fsl,vf610-sai";
+                                reg = <0x40031000 0x1000>;
+                                clocks = <&clks VF610_CLK_SAI2>;
+                                clock-names = "sai";
+                                dma-names = "tx", "rx";
+                                dmas = <&edma0 0 21>,
+                                        <&edma0 0 20>;
+                                status = "disabled";
+                        };
+
+                        pit: pit@40037000 {
+                                compatible = "fsl,vf610-pit";
+                                reg = <0x40037000 0x1000>;
+                                clocks = <&clks VF610_CLK_PIT>;
+                                clock-names = "pit";
+                        };
+
+                        pwm0: pwm@40038000 {
+                                compatible = "fsl,vf610-ftm-pwm";
+                                #pwm-cells = <3>;
+                                reg = <0x40038000 0x1000>;
+                                clock-names = "ftm_sys", "ftm_ext",
+                                              "ftm_fix", "ftm_cnt_clk_en";
+                                clocks = <&clks VF610_CLK_FTM0>,
+                                        <&clks VF610_CLK_FTM0_EXT_SEL>,
+                                        <&clks VF610_CLK_FTM0_FIX_SEL>,
+                                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+
+                        pwm1: pwm@40039000 {
+                                compatible = "fsl,vf610-ftm-pwm";
+                                #pwm-cells = <3>;
+                                reg = <0x40039000 0x1000>;
+                                clock-names = "ftm_sys", "ftm_ext",
+                                              "ftm_fix", "ftm_cnt_clk_en";
+                                clocks = <&clks VF610_CLK_FTM1>,
+                                        <&clks VF610_CLK_FTM1_EXT_SEL>,
+                                        <&clks VF610_CLK_FTM1_FIX_SEL>,
+                                        <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+
+                        adc0: adc@4003b000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x4003b000 0x1000>;
+                                clocks = <&clks VF610_CLK_ADC0>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+
+                        wdog@4003e000 {
+                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+                                reg = <0x4003e000 0x1000>;
+                                clocks = <&clks VF610_CLK_WDT>;
+                                clock-names = "wdog";
+                                status = "disabled";
+                        };
+
+                        qspi0: quadspi@40044000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-qspi";
+                                reg = <0x40044000 0x1000>;
+                                clocks = <&clks VF610_CLK_QSPI0_EN>,
+                                        <&clks VF610_CLK_QSPI0>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+
+                        iomuxc: iomuxc@40048000 {
+                                compatible = "fsl,vf610-iomuxc";
+                                reg = <0x40048000 0x1000>;
+                                #gpio-range-cells = <3>;
+                        };
+
+                        gpio1: gpio@40049000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 0 32>;
+                        };
+
+                        gpio2: gpio@4004a000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 32 32>;
+                        };
+
+                        gpio3: gpio@4004b000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 64 32>;
+                        };
+
+                        gpio4: gpio@4004c000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 96 32>;
+                        };
+
+                        gpio5: gpio@4004d000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 128 7>;
+                        };
+
+                        anatop: anatop@40050000 {
+                                compatible = "fsl,vf610-anatop", "syscon";
+                                reg = <0x40050000 0x400>;
+                        };
+
+                        usbphy0: usbphy@40050800 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050800 0x400>;
+                                clocks = <&clks VF610_CLK_USBPHY0>;
+                                fsl,anatop = <&anatop>;
+                                status = "disabled";
+                        };
+
+                        usbphy1: usbphy@40050c00 {
+                                compatible = "fsl,vf610-usbphy";
+                                reg = <0x40050c00 0x400>;
+                                clocks = <&clks VF610_CLK_USBPHY1>;
+                                fsl,anatop = <&anatop>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@40066000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-i2c";
+                                reg = <0x40066000 0x1000>;
+                                clocks = <&clks VF610_CLK_I2C0>;
+                                clock-names = "ipg";
+                                dmas = <&edma0 0 50>,
+                                        <&edma0 0 51>;
+                                dma-names = "rx","tx";
+                                status = "disabled";
+                        };
+
+                        clks: ccm@4006b000 {
+                                compatible = "fsl,vf610-ccm";
+                                reg = <0x4006b000 0x1000>;
+                                clocks = <&sxosc>, <&fxosc>;
+                                clock-names = "sxosc", "fxosc";
+                                #clock-cells = <1>;
+                        };
+
+                        usbdev0: usb@40034000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x40034000 0x800>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                                fsl,usbphy = <&usbphy0>;
+                                fsl,usbmisc = <&usbmisc0 0>;
+                                dr_mode = "peripheral";
+                                status = "disabled";
+                        };
+
+                        usbmisc0: usb@40034800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x40034800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC0>;
+                                status = "disabled";
+                        };
+                };
+
+                aips1: aips-bus@40080000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        edma1: dma-controller@40098000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40098000 0x2000>,
+                                        <0x400a1000 0x1000>,
+                                        <0x400a2000 0x1000>;
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX2>,
+                                        <&clks VF610_CLK_DMAMUX3>;
+                                status = "disabled";
+                        };
+
+                        uart4: serial@400a9000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400a9000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART4>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart5: serial@400aa000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400aa000 0x1000>;
+                                clocks = <&clks VF610_CLK_UART5>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        adc1: adc@400bb000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x400bb000 0x1000>;
+                                clocks = <&clks VF610_CLK_ADC1>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+
+                        esdhc1: esdhc@400b2000 {
+                                compatible = "fsl,imx53-esdhc";
+                                reg = <0x400b2000 0x1000>;
+                                clocks = <&clks VF610_CLK_IPG_BUS>,
+                                        <&clks VF610_CLK_PLATFORM_BUS>,
+                                        <&clks VF610_CLK_ESDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+
+                        usbh1: usb@400b4000 {
+                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
+                                reg = <0x400b4000 0x800>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc1 0>;
+                                dr_mode = "host";
+                                status = "disabled";
+                        };
+
+                        usbmisc1: usb@400b4800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,vf610-usbmisc";
+                                reg = <0x400b4800 0x200>;
+                                clocks = <&clks VF610_CLK_USBC1>;
+                                status = "disabled";
+                        };
+
+                        ftm: ftm@400b8000 {
+                                compatible = "fsl,ftm-timer";
+                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                clock-names = "ftm-evt", "ftm-src",
+                                        "ftm-evt-counter-en", "ftm-src-counter-en";
+                                clocks = <&clks VF610_CLK_FTM2>,
+                                        <&clks VF610_CLK_FTM3>,
+                                        <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+                                        <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
+
+                        fec0: ethernet@400d0000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d0000 0x1000>;
+                                clocks = <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET0>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+
+                        fec1: ethernet@400d1000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d1000 0x1000>;
+                                clocks = <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET1>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+
+                        can1: flexcan@400d4000 {
+                                compatible = "fsl,vf610-flexcan";
+                                reg = <0x400d4000 0x4000>;
+                                clocks = <&clks VF610_CLK_FLEXCAN1>,
+                                         <&clks VF610_CLK_FLEXCAN1>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ce2ef5bec4f2..ee3e5d675b05 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -243,7 +243,6 @@
                         clkc: clkc@100 {
                                 #clock-cells = <1>;
                                 compatible = "xlnx,ps7-clkc";
-                                ps-clk-frequency = <33333333>;
                                 fclk-enable = <0>;
                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 0429bbd89fba..ab1dc0a56cdd 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -36,6 +36,7 @@
 
 &clkc {
         fclk-enable = <0xf>;
+        ps-clk-frequency = <33333333>;
 };
 
 &gem0 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 94e2cda6f9b6..280f02dd4ddc 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -42,6 +42,10 @@
         status = "okay";
 };
 
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
+
 &gem0 {
         status = "okay";
         phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index a8bbdfbc7093..34f7812d2ee8 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -29,6 +29,10 @@
 
 };
 
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
+
 &gem0 {
         status = "okay";
         phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 697779a353ed..1c7cc990b47a 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -29,6 +29,10 @@
 
 };
 
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
+
 &gem0 {
         status = "okay";
         phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
new file mode 100644
index 000000000000..a9a12ce5023b
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -0,0 +1,52 @@
+/*
+ *  Copyright (C) 2011 - 2014 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq ZYBO Development Board";
+        compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+
+};
+
+&clkc {
+        ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 263ae3869e32..7d2ad30d9e70 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -20,7 +20,6 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -57,14 +56,12 @@ CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
-CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
@@ -83,21 +80,21 @@ CONFIG_PPP_SYNC_TTY=m
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_STMPE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
-CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_STMPE=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_STMPE=y
 CONFIG_REGULATOR=y
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
@@ -125,12 +122,12 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
+CONFIG_DEBUG_INFO=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index f2acf075350d..a9549005097e 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -19,6 +19,9 @@
 
 static const char * const mediatek_board_dt_compat[] = {
         "mediatek,mt6589",
+        "mediatek,mt6592",
+        "mediatek,mt8127",
+        "mediatek,mt8135",
         NULL,
 };
 
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 9116ca476d7c..9bda46f1fab7 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -144,6 +144,7 @@ static int __init cpu8815_mmcsd_init(void)
 device_initcall(cpu8815_mmcsd_init);
 
 static const char * cpu8815_board_compat[] = {
+        "st,nomadik-nhk-15",
         "calaosystems,usb-s8815",
         NULL,
 };
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index cec9d6c6442c..3d7eee1d3cfa 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 
 #include <linux/platform_data/pinctrl-single.h>
@@ -130,17 +131,45 @@ static void __init omap3_sbc_t3730_legacy_init(void)
 {
         omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
         legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
-        omap_ads7846_init(1, 57, 0, NULL);
 }
 
 static void __init omap3_sbc_t3530_legacy_init(void)
 {
         omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
-        omap_ads7846_init(1, 57, 0, NULL);
 }
 
-static void __init omap3_igep0020_legacy_init(void)
+struct ti_st_plat_data wilink_pdata = {
+        .nshutdown_gpio = 137,
+        .dev_name = "/dev/ttyO1",
+        .flow_cntrl = 1,
+        .baud_rate = 300000,
+};
+
+static struct platform_device wl18xx_device = {
+        .name   = "kim",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &wilink_pdata,
+        }
+};
+
+static struct platform_device btwilink_device = {
+        .name   = "btwilink",
+        .id     = -1,
+};
+
+static void __init omap3_igep0020_rev_f_legacy_init(void)
+{
+        legacy_init_wl12xx(0, 0, 177);
+        platform_device_register(&wl18xx_device);
+        platform_device_register(&btwilink_device);
+}
+
+static void __init omap3_igep0030_rev_g_legacy_init(void)
 {
+        legacy_init_wl12xx(0, 0, 136);
+        platform_device_register(&wl18xx_device);
+        platform_device_register(&btwilink_device);
 }
 
 static void __init omap3_evm_legacy_init(void)
@@ -218,7 +247,6 @@ static void __init omap3_sbc_t3517_legacy_init(void)
         hsmmc2_internal_input_clk();
         omap3_sbc_t3517_wifi_init();
         legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
-        omap_ads7846_init(1, 57, 0, NULL);
 }
 
 static void __init am3517_evm_legacy_init(void)
@@ -390,7 +418,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
         { "nokia,omap3-n900", nokia_n900_legacy_init, },
         { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
         { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
-        { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
+        { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
+        { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
         { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
         { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
         { "ti,am3517-evm", am3517_evm_legacy_init, },
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 9db2029aa632..565925f37dc5 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -1,6 +1,19 @@
 menu "RealView platform type"
         depends on ARCH_REALVIEW
 
+config REALVIEW_DT
+        bool "Support RealView(R) Device Tree based boot"
+        select ARM_GIC
+        select MFD_SYSCON
+        select POWER_RESET
+        select POWER_RESET_VERSATILE
+        select POWER_SUPPLY
+        select SOC_REALVIEW
+        select USE_OF
+        help
+          Include support for booting the ARM(R) RealView(R) evaluation
+          boards using a device tree machine description.
+
 config MACH_REALVIEW_EB
         bool "Support RealView(R) Emulation Baseboard"
         select ARM_GIC
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 541fa4c109ef..e07fdf7ae8a7 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-y                                   := core.o
+obj-$(CONFIG_REALVIEW_DT)               += realview-dt.o
 obj-$(CONFIG_MACH_REALVIEW_EB)          += realview_eb.o
 obj-$(CONFIG_MACH_REALVIEW_PB11MP)      += realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c
new file mode 100644
index 000000000000..cc28b89dd48f
--- /dev/null
+++ b/arch/arm/mach-realview/realview-dt.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014 Linaro Ltd.
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "core.h"
+
+static const char *realview_dt_platform_compat[] __initconst = {
+        "arm,realview-eb",
+        "arm,realview-pb1176",
+        "arm,realview-pb11mp",
+        "arm,realview-pba8",
+        "arm,realview-pbx",
+        NULL,
+};
+
+DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)")
+#ifdef CONFIG_ZONE_DMA
+        .dma_zone_size  = SZ_256M,
+#endif
+        .dt_compat      = realview_dt_platform_compat,
+        .l2c_aux_val = 0x0,
+        .l2c_aux_mask = ~0x0,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index 004ed92ee598..3b68370b03a0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -44,7 +44,6 @@ static void __init ape6evm_add_standard_devices(void)
         clk_put(parent);
         clk_put(mp);
 
-        r8a73a4_add_dt_devices();
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index 5fafd6fcedf7..70dcd847a86e 100644
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
@@ -11,7 +11,6 @@ enum {
 };
 
 void r8a73a4_add_standard_devices(void);
-void r8a73a4_add_dt_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
 
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b88b88a40a3c..c27682291cbf 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -176,18 +176,13 @@ static struct resource cmt1_resources[] = {
         DEFINE_RES_IRQ(gic_spi(120)),
 };
 
-#define r8a7790_register_cmt(idx)                                       \
+#define r8a73a4_register_cmt(idx)                                       \
         platform_device_register_resndata(NULL, "sh-cmt-48-gen2",       \
                                           idx, cmt##idx##_resources,    \
                                           ARRAY_SIZE(cmt##idx##_resources), \
                                           &cmt##idx##_platform_data,    \
                                           sizeof(struct sh_timer_config))
 
-void __init r8a73a4_add_dt_devices(void)
-{
-        r8a7790_register_cmt(1);
-}
-
 /* DMA */
 static const struct sh_dmae_slave_config dma_slaves[] = {
         {
@@ -278,7 +273,7 @@ static struct resource dma_resources[] = {
 
 void __init r8a73a4_add_standard_devices(void)
 {
-        r8a73a4_add_dt_devices();
+        r8a73a4_register_cmt(1);
         r8a73a4_register_scif(0);
         r8a73a4_register_scif(1);
         r8a73a4_register_scif(2);
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 45bd3588fa15..170bd146ba17 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -288,8 +288,6 @@ void __init r8a7778_add_dt_devices(void)
                 l2x0_init(base, 0x00400000, 0xc20f0fff);
         }
 #endif
-
-        r8a7778_register_tmu(0);
 }
 
 /* HPB-DMA */
@@ -497,6 +495,7 @@ static void __init r8a7778_register_hpb_dmae(void)
 void __init r8a7778_add_standard_devices(void)
 {
         r8a7778_add_dt_devices();
+        r8a7778_register_tmu(0);
         r8a7778_register_scif(0);
         r8a7778_register_scif(1);
         r8a7778_register_scif(2);
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 878e9ec97d0f..8825bc9e2553 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -42,4 +42,14 @@ config SOC_STIH416
           and other digital audio/video applications using Flattened Device
           Trees.
 
+config SOC_STIH407
+        bool "STiH407 STMicroelectronics Consumer Electronics family"
+        default y
+        select STIH407_RESET
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH407 parts, targetted at set-top-box
+          and other digital audio/video applications using Flattened Device
+          Trees.
+
 endif
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 38493ff28fa5..7f9be0785c6a 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1041,6 +1041,8 @@ gic_of_init(struct device_node *node, struct device_node *parent)
         return 0;
 }
 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
+IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
+IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
diff --git a/drivers/staging/iio/light/isl29028.c b/drivers/staging/iio/light/isl29028.c
index 6014625920b0..e969107ddb47 100644
--- a/drivers/staging/iio/light/isl29028.c
+++ b/drivers/staging/iio/light/isl29028.c
@@ -537,7 +537,8 @@ static const struct i2c_device_id isl29028_id[] = {
 MODULE_DEVICE_TABLE(i2c, isl29028_id);
 
 static const struct of_device_id isl29028_of_match[] = {
-        { .compatible = "isil,isl29028", },
+        { .compatible = "isl,isl29028", },
+        { .compatible = "isil,isl29028", },/* deprecated, don't use */
         { },
 };
 MODULE_DEVICE_TABLE(of, isl29028_of_match);
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
index f6b4b0fe7a43..476135da0f23 100644
--- a/include/dt-bindings/clock/r8a7740-clock.h
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -40,6 +40,7 @@
 
 /* MSTP2 */
 #define R8A7740_CLK_SCIFA6      30
+#define R8A7740_CLK_INTCA       29
 #define R8A7740_CLK_SCIFA7      22
 #define R8A7740_CLK_DMAC1       18
 #define R8A7740_CLK_DMAC2       17
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 8ea7ab0346ad..c27b3b5133b9 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,8 +26,18 @@
 #define R8A7790_CLK_MSIOF0              0
 
 /* MSTP1 */
-#define R8A7790_CLK_JPU         6
+#define R8A7790_CLK_VCP1                0
+#define R8A7790_CLK_VCP0                1
+#define R8A7790_CLK_VPC1                2
+#define R8A7790_CLK_VPC0                3
+#define R8A7790_CLK_JPU                 6
+#define R8A7790_CLK_SSP1                9
 #define R8A7790_CLK_TMU1                11
+#define R8A7790_CLK_3DG                 12
+#define R8A7790_CLK_2DDMAC              15
+#define R8A7790_CLK_FDP1_2              17
+#define R8A7790_CLK_FDP1_1              18
+#define R8A7790_CLK_FDP1_0              19
 #define R8A7790_CLK_TMU3                21
 #define R8A7790_CLK_TMU2                22
 #define R8A7790_CLK_CMT0                24
@@ -68,6 +78,8 @@
 #define R8A7790_CLK_USBDMAC1            31
 
 /* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1         1
+#define R8A7790_CLK_AUDIO_DMAC0         2
 #define R8A7790_CLK_THERMAL             22
 #define R8A7790_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 58c3f49d068c..3ea2bbc0da3f 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,8 +25,15 @@
 #define R8A7791_CLK_MSIOF0              0
 
 /* MSTP1 */
-#define R8A7791_CLK_JPU         6
+#define R8A7791_CLK_VCP0                1
+#define R8A7791_CLK_VPC0                3
+#define R8A7791_CLK_JPU                 6
+#define R8A7791_CLK_SSP1                9
 #define R8A7791_CLK_TMU1                11
+#define R8A7791_CLK_3DG                 12
+#define R8A7791_CLK_2DDMAC              15
+#define R8A7791_CLK_FDP1_1              18
+#define R8A7791_CLK_FDP1_0              19
 #define R8A7791_CLK_TMU3                21
 #define R8A7791_CLK_TMU2                22
 #define R8A7791_CLK_CMT0                24
@@ -62,6 +69,8 @@
 #define R8A7791_CLK_USBDMAC1            31
 
 /* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1         1
+#define R8A7791_CLK_AUDIO_DMAC0         2
 #define R8A7791_CLK_THERMAL             22
 #define R8A7791_CLK_PWM                 23
 
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 9ac1043e25bc..aa9c286e60c0 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -26,11 +26,18 @@
 #define R8A7794_CLK_MSIOF0              0
 
 /* MSTP1 */
+#define R8A7794_CLK_VCP0                1
+#define R8A7794_CLK_VPC0                3
 #define R8A7794_CLK_TMU1                11
+#define R8A7794_CLK_3DG                 12
+#define R8A7794_CLK_2DDMAC              15
+#define R8A7794_CLK_FDP1_0              19
 #define R8A7794_CLK_TMU3                21
 #define R8A7794_CLK_TMU2                22
 #define R8A7794_CLK_CMT0                24
 #define R8A7794_CLK_TMU0                25
+#define R8A7794_CLK_VSP1_DU0            28
+#define R8A7794_CLK_VSP1_S              31
 
 /* MSTP2 */
 #define R8A7794_CLK_SCIFA2              2
@@ -61,6 +68,8 @@
 #define R8A7794_CLK_SCIF0               21
 
 /* MSTP8 */
+#define R8A7794_CLK_VIN1                10
+#define R8A7794_CLK_VIN0                11
 #define R8A7794_CLK_ETHER               13
 
 /* MSTP9 */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000000..7af2b717b3b2
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,86 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU             0
+#define CLK_FDMA                1
+#define CLK_NAND                2
+#define CLK_HVA                 3
+#define CLK_PROC_STFE           4
+#define CLK_PROC_TP             5
+#define CLK_RX_ICN_DMU          6
+#define CLK_RX_ICN_DISP_0       6
+#define CLK_RX_ICN_DISP_1       6
+#define CLK_RX_ICN_HVA          7
+#define CLK_RX_ICN_TS           7
+#define CLK_ICN_CPU             8
+#define CLK_TX_ICN_DMU          9
+#define CLK_TX_ICN_HVA          9
+#define CLK_TX_ICN_TS           9
+#define CLK_ICN_COMPO           9
+#define CLK_MMC_0               10
+#define CLK_MMC_1               11
+#define CLK_JPEGDEC             12
+#define CLK_ICN_REG             13
+#define CLK_TRACE_A9            13
+#define CLK_PTI_STM             13
+#define CLK_EXT2F_A9            13
+#define CLK_IC_BDISP_0          14
+#define CLK_IC_BDISP_1          15
+#define CLK_PP_DMU              16
+#define CLK_VID_DMU             17
+#define CLK_DSS_LPC             18
+#define CLK_ST231_AUD_0         19
+#define CLK_ST231_GP_0          19
+#define CLK_ST231_GP_1          20
+#define CLK_ST231_DMU           21
+#define CLK_ICN_LMI             22
+#define CLK_TX_ICN_DISP_0       23
+#define CLK_TX_ICN_DISP_1       23
+#define CLK_ICN_SBC             24
+#define CLK_STFE_FRC2           25
+#define CLK_ETH_PHY             26
+#define CLK_ETH_REF_PHYCLK      27
+#define CLK_FLASH_PROMIP        28
+#define CLK_MAIN_DISP           29
+#define CLK_AUX_DISP            30
+#define CLK_COMPO_DVP           31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0               0
+#define CLK_PCM_1               1
+#define CLK_PCM_2               2
+#define CLK_SPDIFF              3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP       0
+#define CLK_PIX_PIP             1
+#define CLK_PIX_GDP1            2
+#define CLK_PIX_GDP2            3
+#define CLK_PIX_GDP3            4
+#define CLK_PIX_GDP4            5
+#define CLK_PIX_AUX_DISP        6
+#define CLK_DENC                7
+#define CLK_PIX_HDDAC           8
+#define CLK_HDDAC               9
+#define CLK_SDDAC               10
+#define CLK_PIX_DVO             11
+#define CLK_DVO                 12
+#define CLK_PIX_HDMI            13
+#define CLK_TMDS_HDMI           14
+#define CLK_REF_HDMIPHY         15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1           0
+#define CLK_TSOUT_0             1
+#define CLK_TSOUT_1             2
+#define CLK_MCHI                3
+#define CLK_VSENS_COMPO         4
+#define CLK_FRC1_REMOTE         5
+#define CLK_LPC_0               6
+#define CLK_LPC_1               7
+#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 000000000000..2097a4bbe155
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES        32
+#define CLK_RX_ICN_HADES        33
+#define CLK_ICN_REG_16          34
+#define CLK_PP_HADES            35
+#define CLK_CLUST_HADES         36
+#define CLK_HWPE_HADES          37
+#define CLK_FC_HADES            38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER       4
+#define CLK_USB2_PHY            5
+
+#endif