aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h16
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c98
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c4
3 files changed, 65 insertions, 53 deletions
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
index 28a6b28192e3..bd5030e51240 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
@@ -792,22 +792,6 @@ static const u32 MIU_TEST_READ_DATA[] = {
792#define QLCNIC_FLASH_SEM2_ULK 0x0013C014 792#define QLCNIC_FLASH_SEM2_ULK 0x0013C014
793#define QLCNIC_FLASH_LOCK_ID 0x001B2100 793#define QLCNIC_FLASH_LOCK_ID 0x001B2100
794 794
795#define QLCNIC_RD_DUMP_REG(addr, bar0, data) do { \
796 writel((addr & 0xFFFF0000), (void *) (bar0 + \
797 QLCNIC_FW_DUMP_REG1)); \
798 readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1)); \
799 *data = readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 + \
800 LSW(addr))); \
801} while (0)
802
803#define QLCNIC_WR_DUMP_REG(addr, bar0, data) do { \
804 writel((addr & 0xFFFF0000), (void *) (bar0 + \
805 QLCNIC_FW_DUMP_REG1)); \
806 readl((void *) (bar0 + QLCNIC_FW_DUMP_REG1)); \
807 writel(data, (void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr)));\
808 readl((void *) (bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr))); \
809} while (0)
810
811/* PCI function operational mode */ 795/* PCI function operational mode */
812enum { 796enum {
813 QLCNIC_MGMT_FUNC = 0, 797 QLCNIC_MGMT_FUNC = 0,
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
index fc308c85c062..bd3e76643799 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
@@ -266,6 +266,33 @@ static const unsigned crb_hub_agt[64] = {
266 0, 266 0,
267}; 267};
268 268
269static void qlcnic_read_dump_reg(u32 addr, void __iomem *bar0, u32 *data)
270{
271 u32 dest;
272 void __iomem *window_reg;
273
274 dest = addr & 0xFFFF0000;
275 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
276 writel(dest, window_reg);
277 readl(window_reg);
278 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
279 *data = readl(window_reg);
280}
281
282static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
283{
284 u32 dest;
285 void __iomem *window_reg;
286
287 dest = addr & 0xFFFF0000;
288 window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
289 writel(dest, window_reg);
290 readl(window_reg);
291 window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
292 writel(data, window_reg);
293 readl(window_reg);
294}
295
269/* PCI Windowing for DDR regions. */ 296/* PCI Windowing for DDR regions. */
270 297
271#define QLCNIC_PCIE_SEM_TIMEOUT 10000 298#define QLCNIC_PCIE_SEM_TIMEOUT 10000
@@ -540,7 +567,7 @@ void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
540 } 567 }
541} 568}
542 569
543int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag) 570static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
544{ 571{
545 struct qlcnic_nic_req req; 572 struct qlcnic_nic_req req;
546 int rv; 573 int rv;
@@ -1334,7 +1361,7 @@ qlcnic_dump_crb(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1334 addr = crb->addr; 1361 addr = crb->addr;
1335 1362
1336 for (i = 0; i < crb->no_ops; i++) { 1363 for (i = 0; i < crb->no_ops; i++) {
1337 QLCNIC_RD_DUMP_REG(addr, base, &data); 1364 qlcnic_read_dump_reg(addr, base, &data);
1338 *buffer++ = cpu_to_le32(addr); 1365 *buffer++ = cpu_to_le32(addr);
1339 *buffer++ = cpu_to_le32(data); 1366 *buffer++ = cpu_to_le32(data);
1340 addr += crb->stride; 1367 addr += crb->stride;
@@ -1364,25 +1391,25 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
1364 continue; 1391 continue;
1365 switch (1 << k) { 1392 switch (1 << k) {
1366 case QLCNIC_DUMP_WCRB: 1393 case QLCNIC_DUMP_WCRB:
1367 QLCNIC_WR_DUMP_REG(addr, base, ctr->val1); 1394 qlcnic_write_dump_reg(addr, base, ctr->val1);
1368 break; 1395 break;
1369 case QLCNIC_DUMP_RWCRB: 1396 case QLCNIC_DUMP_RWCRB:
1370 QLCNIC_RD_DUMP_REG(addr, base, &data); 1397 qlcnic_read_dump_reg(addr, base, &data);
1371 QLCNIC_WR_DUMP_REG(addr, base, data); 1398 qlcnic_write_dump_reg(addr, base, data);
1372 break; 1399 break;
1373 case QLCNIC_DUMP_ANDCRB: 1400 case QLCNIC_DUMP_ANDCRB:
1374 QLCNIC_RD_DUMP_REG(addr, base, &data); 1401 qlcnic_read_dump_reg(addr, base, &data);
1375 QLCNIC_WR_DUMP_REG(addr, base, 1402 qlcnic_write_dump_reg(addr, base,
1376 (data & ctr->val2)); 1403 data & ctr->val2);
1377 break; 1404 break;
1378 case QLCNIC_DUMP_ORCRB: 1405 case QLCNIC_DUMP_ORCRB:
1379 QLCNIC_RD_DUMP_REG(addr, base, &data); 1406 qlcnic_read_dump_reg(addr, base, &data);
1380 QLCNIC_WR_DUMP_REG(addr, base, 1407 qlcnic_write_dump_reg(addr, base,
1381 (data | ctr->val3)); 1408 data | ctr->val3);
1382 break; 1409 break;
1383 case QLCNIC_DUMP_POLLCRB: 1410 case QLCNIC_DUMP_POLLCRB:
1384 while (timeout <= ctr->timeout) { 1411 while (timeout <= ctr->timeout) {
1385 QLCNIC_RD_DUMP_REG(addr, base, &data); 1412 qlcnic_read_dump_reg(addr, base, &data);
1386 if ((data & ctr->val2) == ctr->val1) 1413 if ((data & ctr->val2) == ctr->val1)
1387 break; 1414 break;
1388 msleep(1); 1415 msleep(1);
@@ -1397,7 +1424,7 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
1397 case QLCNIC_DUMP_RD_SAVE: 1424 case QLCNIC_DUMP_RD_SAVE:
1398 if (ctr->index_a) 1425 if (ctr->index_a)
1399 addr = t_hdr->saved_state[ctr->index_a]; 1426 addr = t_hdr->saved_state[ctr->index_a];
1400 QLCNIC_RD_DUMP_REG(addr, base, &data); 1427 qlcnic_read_dump_reg(addr, base, &data);
1401 t_hdr->saved_state[ctr->index_v] = data; 1428 t_hdr->saved_state[ctr->index_v] = data;
1402 break; 1429 break;
1403 case QLCNIC_DUMP_WRT_SAVED: 1430 case QLCNIC_DUMP_WRT_SAVED:
@@ -1407,7 +1434,7 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
1407 data = ctr->val1; 1434 data = ctr->val1;
1408 if (ctr->index_a) 1435 if (ctr->index_a)
1409 addr = t_hdr->saved_state[ctr->index_a]; 1436 addr = t_hdr->saved_state[ctr->index_a];
1410 QLCNIC_WR_DUMP_REG(addr, base, data); 1437 qlcnic_write_dump_reg(addr, base, data);
1411 break; 1438 break;
1412 case QLCNIC_DUMP_MOD_SAVE_ST: 1439 case QLCNIC_DUMP_MOD_SAVE_ST:
1413 data = t_hdr->saved_state[ctr->index_v]; 1440 data = t_hdr->saved_state[ctr->index_v];
@@ -1441,8 +1468,8 @@ qlcnic_dump_mux(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1441 1468
1442 val = mux->val; 1469 val = mux->val;
1443 for (loop = 0; loop < mux->no_ops; loop++) { 1470 for (loop = 0; loop < mux->no_ops; loop++) {
1444 QLCNIC_WR_DUMP_REG(mux->addr, base, val); 1471 qlcnic_write_dump_reg(mux->addr, base, val);
1445 QLCNIC_RD_DUMP_REG(mux->read_addr, base, &data); 1472 qlcnic_read_dump_reg(mux->read_addr, base, &data);
1446 *buffer++ = cpu_to_le32(val); 1473 *buffer++ = cpu_to_le32(val);
1447 *buffer++ = cpu_to_le32(data); 1474 *buffer++ = cpu_to_le32(data);
1448 val += mux->val_stride; 1475 val += mux->val_stride;
@@ -1463,10 +1490,10 @@ qlcnic_dump_que(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
1463 cnt = que->read_addr_cnt; 1490 cnt = que->read_addr_cnt;
1464 1491
1465 for (loop = 0; loop < que->no_ops; loop++) { 1492 for (loop = 0; loop < que->no_ops; loop++) {
1466 QLCNIC_WR_DUMP_REG(que->sel_addr, base, que_id); 1493 qlcnic_write_dump_reg(que->sel_addr, base, que_id);
1467 addr = que->read_addr; 1494 addr = que->read_addr;
1468 for (i = 0; i < cnt; i++) { 1495 for (i = 0; i < cnt; i++) {
1469 QLCNIC_RD_DUMP_REG(addr, base, &data); 1496 qlcnic_read_dump_reg(addr, base, &data);
1470 *buffer++ = cpu_to_le32(data); 1497 *buffer++ = cpu_to_le32(data);
1471 addr += que->read_addr_stride; 1498 addr += que->read_addr_stride;
1472 } 1499 }
@@ -1514,9 +1541,9 @@ lock_try:
1514 writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID)); 1541 writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
1515 for (i = 0; i < size; i++) { 1542 for (i = 0; i < size; i++) {
1516 addr = fl_addr & 0xFFFF0000; 1543 addr = fl_addr & 0xFFFF0000;
1517 QLCNIC_WR_DUMP_REG(FLASH_ROM_WINDOW, base, addr); 1544 qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
1518 addr = LSW(fl_addr) + FLASH_ROM_DATA; 1545 addr = LSW(fl_addr) + FLASH_ROM_DATA;
1519 QLCNIC_RD_DUMP_REG(addr, base, &val); 1546 qlcnic_read_dump_reg(addr, base, &val);
1520 fl_addr += 4; 1547 fl_addr += 4;
1521 *buffer++ = cpu_to_le32(val); 1548 *buffer++ = cpu_to_le32(val);
1522 } 1549 }
@@ -1536,12 +1563,12 @@ qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
1536 val = l1->init_tag_val; 1563 val = l1->init_tag_val;
1537 1564
1538 for (i = 0; i < l1->no_ops; i++) { 1565 for (i = 0; i < l1->no_ops; i++) {
1539 QLCNIC_WR_DUMP_REG(l1->addr, base, val); 1566 qlcnic_write_dump_reg(l1->addr, base, val);
1540 QLCNIC_WR_DUMP_REG(l1->ctrl_addr, base, LSW(l1->ctrl_val)); 1567 qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
1541 addr = l1->read_addr; 1568 addr = l1->read_addr;
1542 cnt = l1->read_addr_num; 1569 cnt = l1->read_addr_num;
1543 while (cnt) { 1570 while (cnt) {
1544 QLCNIC_RD_DUMP_REG(addr, base, &data); 1571 qlcnic_read_dump_reg(addr, base, &data);
1545 *buffer++ = cpu_to_le32(data); 1572 *buffer++ = cpu_to_le32(data);
1546 addr += l1->read_addr_stride; 1573 addr += l1->read_addr_stride;
1547 cnt--; 1574 cnt--;
@@ -1566,14 +1593,14 @@ qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
1566 poll_to = MSB(MSW(l2->ctrl_val)); 1593 poll_to = MSB(MSW(l2->ctrl_val));
1567 1594
1568 for (i = 0; i < l2->no_ops; i++) { 1595 for (i = 0; i < l2->no_ops; i++) {
1569 QLCNIC_WR_DUMP_REG(l2->addr, base, val); 1596 qlcnic_write_dump_reg(l2->addr, base, val);
1570 if (LSW(l2->ctrl_val)) 1597 if (LSW(l2->ctrl_val))
1571 QLCNIC_WR_DUMP_REG(l2->ctrl_addr, base, 1598 qlcnic_write_dump_reg(l2->ctrl_addr, base,
1572 LSW(l2->ctrl_val)); 1599 LSW(l2->ctrl_val));
1573 if (!poll_mask) 1600 if (!poll_mask)
1574 goto skip_poll; 1601 goto skip_poll;
1575 do { 1602 do {
1576 QLCNIC_RD_DUMP_REG(l2->ctrl_addr, base, &data); 1603 qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
1577 if (!(data & poll_mask)) 1604 if (!(data & poll_mask))
1578 break; 1605 break;
1579 msleep(1); 1606 msleep(1);
@@ -1590,7 +1617,7 @@ skip_poll:
1590 addr = l2->read_addr; 1617 addr = l2->read_addr;
1591 cnt = l2->read_addr_num; 1618 cnt = l2->read_addr_num;
1592 while (cnt) { 1619 while (cnt) {
1593 QLCNIC_RD_DUMP_REG(addr, base, &data); 1620 qlcnic_read_dump_reg(addr, base, &data);
1594 *buffer++ = cpu_to_le32(data); 1621 *buffer++ = cpu_to_le32(data);
1595 addr += l2->read_addr_stride; 1622 addr += l2->read_addr_stride;
1596 cnt--; 1623 cnt--;
@@ -1622,13 +1649,13 @@ qlcnic_read_memory(struct qlcnic_adapter *adapter,
1622 mutex_lock(&adapter->ahw->mem_lock); 1649 mutex_lock(&adapter->ahw->mem_lock);
1623 1650
1624 while (reg_read != 0) { 1651 while (reg_read != 0) {
1625 QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_LO, base, addr); 1652 qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
1626 QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_HI, base, 0); 1653 qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
1627 QLCNIC_WR_DUMP_REG(MIU_TEST_CTR, base, 1654 qlcnic_write_dump_reg(MIU_TEST_CTR, base,
1628 TA_CTL_ENABLE | TA_CTL_START); 1655 TA_CTL_ENABLE | TA_CTL_START);
1629 1656
1630 for (i = 0; i < MAX_CTL_CHECK; i++) { 1657 for (i = 0; i < MAX_CTL_CHECK; i++) {
1631 QLCNIC_RD_DUMP_REG(MIU_TEST_CTR, base, &test); 1658 qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
1632 if (!(test & TA_CTL_BUSY)) 1659 if (!(test & TA_CTL_BUSY))
1633 break; 1660 break;
1634 } 1661 }
@@ -1641,7 +1668,8 @@ qlcnic_read_memory(struct qlcnic_adapter *adapter,
1641 } 1668 }
1642 } 1669 }
1643 for (i = 0; i < 4; i++) { 1670 for (i = 0; i < 4; i++) {
1644 QLCNIC_RD_DUMP_REG(MIU_TEST_READ_DATA[i], base, &data); 1671 qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
1672 &data);
1645 *buffer++ = cpu_to_le32(data); 1673 *buffer++ = cpu_to_le32(data);
1646 } 1674 }
1647 addr += 16; 1675 addr += 16;
@@ -1661,7 +1689,7 @@ qlcnic_dump_nop(struct qlcnic_adapter *adapter,
1661 return 0; 1689 return 0;
1662} 1690}
1663 1691
1664struct qlcnic_dump_operations fw_dump_ops[] = { 1692static const struct qlcnic_dump_operations fw_dump_ops[] = {
1665 { QLCNIC_DUMP_NOP, qlcnic_dump_nop }, 1693 { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
1666 { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb }, 1694 { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
1667 { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux }, 1695 { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
index faae9c5fbd10..a7f5bbe24726 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
@@ -1849,8 +1849,8 @@ static void dump_skb(struct sk_buff *skb, struct qlcnic_adapter *adapter)
1849 } 1849 }
1850} 1850}
1851 1851
1852void qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter, int ring, 1852static void qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter, int ring,
1853 u64 sts_data0) 1853 u64 sts_data0)
1854{ 1854{
1855 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1855 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1856 struct sk_buff *skb; 1856 struct sk_buff *skb;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 23:01:58 -0500