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-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c87
1 files changed, 25 insertions, 62 deletions
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index ec884039b914..a1c80d909cd6 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -21,17 +21,7 @@ static struct resource rtc_resources[] = {
21 .flags = IORESOURCE_IO, 21 .flags = IORESOURCE_IO,
22 }, 22 },
23 [1] = { 23 [1] = {
24 /* Period IRQ */ 24 /* Shared Period/Carry/Alarm IRQ */
25 .start = 21,
26 .flags = IORESOURCE_IRQ,
27 },
28 [2] = {
29 /* Carry IRQ */
30 .start = 22,
31 .flags = IORESOURCE_IRQ,
32 },
33 [3] = {
34 /* Alarm IRQ */
35 .start = 20, 25 .start = 20,
36 .flags = IORESOURCE_IRQ, 26 .flags = IORESOURCE_IRQ,
37 }, 27 },
@@ -50,13 +40,13 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCI, 42 .type = PORT_SCI,
53 .irqs = { 23, 24, 25, 0 }, 43 .irqs = { 23, 23, 23, 0 },
54 }, { 44 }, {
55#endif 45#endif
56 .mapbase = 0xffe80000, 46 .mapbase = 0xffe80000,
57 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 48 .type = PORT_SCIF,
59 .irqs = { 40, 41, 43, 42 }, 49 .irqs = { 40, 40, 40, 40 },
60 }, { 50 }, {
61 .flags = 0, 51 .flags = 0,
62 } 52 }
@@ -87,43 +77,27 @@ enum {
87 77
88 /* interrupt sources */ 78 /* interrupt sources */
89 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 79 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
90 HUDI, GPIOI, 80 HUDI, GPIOI, DMAC,
91 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
92 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
93 DMAC_DMAE,
94 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 81 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
95 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 82 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
96 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 83 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
97 RTC_ATI, RTC_PRI, RTC_CUI,
98 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
99 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
100 WDT,
101 REF_RCMI, REF_ROVI,
102 84
103 /* interrupt groups */ 85 /* interrupt groups */
104 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 86 PCIC1,
105}; 87};
106 88
107static struct intc_vect vectors[] __initdata = { 89static struct intc_vect vectors[] __initdata = {
108 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 90 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
109 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 91 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
110 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 92 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
111 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 93 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
112 INTC_VECT(RTC_CUI, 0x4c0), 94 INTC_VECT(RTC, 0x4c0),
113 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 95 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
114 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 96 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
115 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 97 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
116 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 98 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
117 INTC_VECT(WDT, 0x560), 99 INTC_VECT(WDT, 0x560),
118 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 100 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
119};
120
121static struct intc_group groups[] __initdata = {
122 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
123 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
124 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
125 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
126 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
127}; 101};
128 102
129static struct intc_prio_reg prio_registers[] __initdata = { 103static struct intc_prio_reg prio_registers[] __initdata = {
@@ -136,7 +110,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
136 PCIC1, PCIC0_PCISERR } }, 110 PCIC1, PCIC0_PCISERR } },
137}; 111};
138 112
139static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, 113static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
140 NULL, prio_registers, NULL); 114 NULL, prio_registers, NULL);
141 115
142/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 116/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
@@ -145,39 +119,28 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
145 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 119 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
146 defined(CONFIG_CPU_SUBTYPE_SH7091) 120 defined(CONFIG_CPU_SUBTYPE_SH7091)
147static struct intc_vect vectors_dma4[] __initdata = { 121static struct intc_vect vectors_dma4[] __initdata = {
148 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 122 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
149 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 123 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
150 INTC_VECT(DMAC_DMAE, 0x6c0), 124 INTC_VECT(DMAC, 0x6c0),
151};
152
153static struct intc_group groups_dma4[] __initdata = {
154 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
155 DMAC_DMTE3, DMAC_DMAE),
156}; 125};
157 126
158static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 127static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
159 vectors_dma4, groups_dma4, 128 vectors_dma4, NULL,
160 NULL, prio_registers, NULL); 129 NULL, prio_registers, NULL);
161#endif 130#endif
162 131
163/* SH7750R and SH7751R both have 8-channel DMA controllers */ 132/* SH7750R and SH7751R both have 8-channel DMA controllers */
164#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 133#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
165static struct intc_vect vectors_dma8[] __initdata = { 134static struct intc_vect vectors_dma8[] __initdata = {
166 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 135 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
167 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 136 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
168 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 137 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
169 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 138 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
170 INTC_VECT(DMAC_DMAE, 0x6c0), 139 INTC_VECT(DMAC, 0x6c0),
171};
172
173static struct intc_group groups_dma8[] __initdata = {
174 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
175 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
176 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
177}; 140};
178 141
179static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 142static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
180 vectors_dma8, groups_dma8, 143 vectors_dma8, NULL,
181 NULL, prio_registers, NULL); 144 NULL, prio_registers, NULL);
182#endif 145#endif
183 146