1 files changed, 16 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index e8c0473c7568..579023f59dc1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                         unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
         int i;
+        u32 val;
         struct device_node *np;
 
         clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
@@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         imx_print_silicon_rev("i.MX51", mx51_revision());
         clk_disable_unprepare(clk[iim_gate]);
 
+        /*
+         * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
+         * longer supported. Set to one for better power saving.
+         *
+         * The effect of not setting these bits is that MIPI clocks can't be
+         * enabled without the IPU clock being enabled aswell.
+         */
+        val = readl(MXC_CCM_CCDR);
+        val |= 1 << 18;
+        writel(val, MXC_CCM_CCDR);
+
+        val = readl(MXC_CCM_CLPCR);
+        val |= 1 << 23;
+        writel(val, MXC_CCM_CLPCR);
+
         return 0;
 }