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-rw-r--r--drivers/gpu/drm/i915/i915_drv.c15
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
2 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d783e2b4c914..0694e170a338 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -421,8 +421,10 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
421 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); 421 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
422} 422}
423 423
424void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 424int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
425{ 425{
426 int ret = 0;
427
426 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 428 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
427 int loop = 500; 429 int loop = 500;
428 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 430 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
@@ -430,10 +432,13 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
430 udelay(10); 432 udelay(10);
431 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 433 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
432 } 434 }
433 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES); 435 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
436 ++ret;
434 dev_priv->gt_fifo_count = fifo; 437 dev_priv->gt_fifo_count = fifo;
435 } 438 }
436 dev_priv->gt_fifo_count--; 439 dev_priv->gt_fifo_count--;
440
441 return ret;
437} 442}
438 443
439static int i915_drm_freeze(struct drm_device *dev) 444static int i915_drm_freeze(struct drm_device *dev)
@@ -1001,11 +1006,15 @@ __i915_read(64, q)
1001 1006
1002#define __i915_write(x, y) \ 1007#define __i915_write(x, y) \
1003void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 1008void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1009 u32 __fifo_ret = 0; \
1004 trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 1010 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1005 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 1011 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1006 __gen6_gt_wait_for_fifo(dev_priv); \ 1012 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1007 } \ 1013 } \
1008 write##y(val, dev_priv->regs + reg); \ 1014 write##y(val, dev_priv->regs + reg); \
1015 if (unlikely(__fifo_ret)) { \
1016 gen6_gt_check_fifodbg(dev_priv); \
1017 } \
1009} 1018}
1010__i915_write(8, b) 1019__i915_write(8, b)
1011__i915_write(16, w) 1020__i915_write(16, w)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 922aed33035d..000a9ad17ddd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1401,7 +1401,7 @@ extern void intel_display_print_error_state(struct seq_file *m,
1401 */ 1401 */
1402void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1402void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1403void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1403void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1404void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1404int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1405 1405
1406/* We give fast paths for the really cool registers */ 1406/* We give fast paths for the really cool registers */
1407#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1407#define NEEDS_FORCE_WAKE(dev_priv, reg) \