diff options
-rw-r--r-- | arch/arm/mach-omap2/clock34xx_data.c | 146 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 5 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/clock.h | 5 |
3 files changed, 149 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 60c6140b86af..4dd5926ad980 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c | |||
@@ -237,6 +237,42 @@ static const struct clksel_rate div16_dpll_rates[] = { | |||
237 | { .div = 0 } | 237 | { .div = 0 } |
238 | }; | 238 | }; |
239 | 239 | ||
240 | static const struct clksel_rate div32_dpll4_rates_3630[] = { | ||
241 | { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE }, | ||
242 | { .div = 2, .val = 2, .flags = RATE_IN_36XX }, | ||
243 | { .div = 3, .val = 3, .flags = RATE_IN_36XX }, | ||
244 | { .div = 4, .val = 4, .flags = RATE_IN_36XX }, | ||
245 | { .div = 5, .val = 5, .flags = RATE_IN_36XX }, | ||
246 | { .div = 6, .val = 6, .flags = RATE_IN_36XX }, | ||
247 | { .div = 7, .val = 7, .flags = RATE_IN_36XX }, | ||
248 | { .div = 8, .val = 8, .flags = RATE_IN_36XX }, | ||
249 | { .div = 9, .val = 9, .flags = RATE_IN_36XX }, | ||
250 | { .div = 10, .val = 10, .flags = RATE_IN_36XX }, | ||
251 | { .div = 11, .val = 11, .flags = RATE_IN_36XX }, | ||
252 | { .div = 12, .val = 12, .flags = RATE_IN_36XX }, | ||
253 | { .div = 13, .val = 13, .flags = RATE_IN_36XX }, | ||
254 | { .div = 14, .val = 14, .flags = RATE_IN_36XX }, | ||
255 | { .div = 15, .val = 15, .flags = RATE_IN_36XX }, | ||
256 | { .div = 16, .val = 16, .flags = RATE_IN_36XX }, | ||
257 | { .div = 17, .val = 17, .flags = RATE_IN_36XX }, | ||
258 | { .div = 18, .val = 18, .flags = RATE_IN_36XX }, | ||
259 | { .div = 19, .val = 19, .flags = RATE_IN_36XX }, | ||
260 | { .div = 20, .val = 20, .flags = RATE_IN_36XX }, | ||
261 | { .div = 21, .val = 21, .flags = RATE_IN_36XX }, | ||
262 | { .div = 22, .val = 22, .flags = RATE_IN_36XX }, | ||
263 | { .div = 23, .val = 23, .flags = RATE_IN_36XX }, | ||
264 | { .div = 24, .val = 24, .flags = RATE_IN_36XX }, | ||
265 | { .div = 25, .val = 25, .flags = RATE_IN_36XX }, | ||
266 | { .div = 26, .val = 26, .flags = RATE_IN_36XX }, | ||
267 | { .div = 27, .val = 27, .flags = RATE_IN_36XX }, | ||
268 | { .div = 28, .val = 28, .flags = RATE_IN_36XX }, | ||
269 | { .div = 29, .val = 29, .flags = RATE_IN_36XX }, | ||
270 | { .div = 30, .val = 30, .flags = RATE_IN_36XX }, | ||
271 | { .div = 31, .val = 31, .flags = RATE_IN_36XX }, | ||
272 | { .div = 32, .val = 32, .flags = RATE_IN_36XX }, | ||
273 | { .div = 0 } | ||
274 | }; | ||
275 | |||
240 | /* DPLL1 */ | 276 | /* DPLL1 */ |
241 | /* MPU clock source */ | 277 | /* MPU clock source */ |
242 | /* Type: DPLL */ | 278 | /* Type: DPLL */ |
@@ -606,8 +642,15 @@ static const struct clksel div16_dpll4_clksel[] = { | |||
606 | { .parent = NULL } | 642 | { .parent = NULL } |
607 | }; | 643 | }; |
608 | 644 | ||
645 | static const struct clksel div32_dpll4_clksel[] = { | ||
646 | { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 }, | ||
647 | { .parent = NULL } | ||
648 | }; | ||
649 | |||
609 | /* This virtual clock is the source for dpll4_m2x2_ck */ | 650 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
610 | static struct clk dpll4_m2_ck = { | 651 | static struct clk dpll4_m2_ck; |
652 | |||
653 | static struct clk dpll4_m2_ck_34xx __initdata = { | ||
611 | .name = "dpll4_m2_ck", | 654 | .name = "dpll4_m2_ck", |
612 | .ops = &clkops_null, | 655 | .ops = &clkops_null, |
613 | .parent = &dpll4_ck, | 656 | .parent = &dpll4_ck, |
@@ -619,6 +662,18 @@ static struct clk dpll4_m2_ck = { | |||
619 | .recalc = &omap2_clksel_recalc, | 662 | .recalc = &omap2_clksel_recalc, |
620 | }; | 663 | }; |
621 | 664 | ||
665 | static struct clk dpll4_m2_ck_3630 __initdata = { | ||
666 | .name = "dpll4_m2_ck", | ||
667 | .ops = &clkops_null, | ||
668 | .parent = &dpll4_ck, | ||
669 | .init = &omap2_init_clksel_parent, | ||
670 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | ||
671 | .clksel_mask = OMAP3630_DIV_96M_MASK, | ||
672 | .clksel = div32_dpll4_clksel, | ||
673 | .clkdm_name = "dpll4_clkdm", | ||
674 | .recalc = &omap2_clksel_recalc, | ||
675 | }; | ||
676 | |||
622 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 677 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
623 | static struct clk dpll4_m2x2_ck = { | 678 | static struct clk dpll4_m2x2_ck = { |
624 | .name = "dpll4_m2x2_ck", | 679 | .name = "dpll4_m2x2_ck", |
@@ -679,7 +734,9 @@ static struct clk omap_96m_fck = { | |||
679 | }; | 734 | }; |
680 | 735 | ||
681 | /* This virtual clock is the source for dpll4_m3x2_ck */ | 736 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
682 | static struct clk dpll4_m3_ck = { | 737 | static struct clk dpll4_m3_ck; |
738 | |||
739 | static struct clk dpll4_m3_ck_34xx __initdata = { | ||
683 | .name = "dpll4_m3_ck", | 740 | .name = "dpll4_m3_ck", |
684 | .ops = &clkops_null, | 741 | .ops = &clkops_null, |
685 | .parent = &dpll4_ck, | 742 | .parent = &dpll4_ck, |
@@ -691,6 +748,18 @@ static struct clk dpll4_m3_ck = { | |||
691 | .recalc = &omap2_clksel_recalc, | 748 | .recalc = &omap2_clksel_recalc, |
692 | }; | 749 | }; |
693 | 750 | ||
751 | static struct clk dpll4_m3_ck_3630 __initdata = { | ||
752 | .name = "dpll4_m3_ck", | ||
753 | .ops = &clkops_null, | ||
754 | .parent = &dpll4_ck, | ||
755 | .init = &omap2_init_clksel_parent, | ||
756 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
757 | .clksel_mask = OMAP3630_CLKSEL_TV_MASK, | ||
758 | .clksel = div32_dpll4_clksel, | ||
759 | .clkdm_name = "dpll4_clkdm", | ||
760 | .recalc = &omap2_clksel_recalc, | ||
761 | }; | ||
762 | |||
694 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 763 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
695 | static struct clk dpll4_m3x2_ck = { | 764 | static struct clk dpll4_m3x2_ck = { |
696 | .name = "dpll4_m3x2_ck", | 765 | .name = "dpll4_m3x2_ck", |
@@ -764,7 +833,9 @@ static struct clk omap_12m_fck = { | |||
764 | }; | 833 | }; |
765 | 834 | ||
766 | /* This virstual clock is the source for dpll4_m4x2_ck */ | 835 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
767 | static struct clk dpll4_m4_ck = { | 836 | static struct clk dpll4_m4_ck; |
837 | |||
838 | static struct clk dpll4_m4_ck_34xx __initdata = { | ||
768 | .name = "dpll4_m4_ck", | 839 | .name = "dpll4_m4_ck", |
769 | .ops = &clkops_null, | 840 | .ops = &clkops_null, |
770 | .parent = &dpll4_ck, | 841 | .parent = &dpll4_ck, |
@@ -778,6 +849,20 @@ static struct clk dpll4_m4_ck = { | |||
778 | .round_rate = &omap2_clksel_round_rate, | 849 | .round_rate = &omap2_clksel_round_rate, |
779 | }; | 850 | }; |
780 | 851 | ||
852 | static struct clk dpll4_m4_ck_3630 __initdata = { | ||
853 | .name = "dpll4_m4_ck", | ||
854 | .ops = &clkops_null, | ||
855 | .parent = &dpll4_ck, | ||
856 | .init = &omap2_init_clksel_parent, | ||
857 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | ||
858 | .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, | ||
859 | .clksel = div32_dpll4_clksel, | ||
860 | .clkdm_name = "dpll4_clkdm", | ||
861 | .recalc = &omap2_clksel_recalc, | ||
862 | .set_rate = &omap2_clksel_set_rate, | ||
863 | .round_rate = &omap2_clksel_round_rate, | ||
864 | }; | ||
865 | |||
781 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 866 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
782 | static struct clk dpll4_m4x2_ck = { | 867 | static struct clk dpll4_m4x2_ck = { |
783 | .name = "dpll4_m4x2_ck", | 868 | .name = "dpll4_m4x2_ck", |
@@ -791,7 +876,9 @@ static struct clk dpll4_m4x2_ck = { | |||
791 | }; | 876 | }; |
792 | 877 | ||
793 | /* This virtual clock is the source for dpll4_m5x2_ck */ | 878 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
794 | static struct clk dpll4_m5_ck = { | 879 | static struct clk dpll4_m5_ck; |
880 | |||
881 | static struct clk dpll4_m5_ck_34xx __initdata = { | ||
795 | .name = "dpll4_m5_ck", | 882 | .name = "dpll4_m5_ck", |
796 | .ops = &clkops_null, | 883 | .ops = &clkops_null, |
797 | .parent = &dpll4_ck, | 884 | .parent = &dpll4_ck, |
@@ -805,6 +892,18 @@ static struct clk dpll4_m5_ck = { | |||
805 | .recalc = &omap2_clksel_recalc, | 892 | .recalc = &omap2_clksel_recalc, |
806 | }; | 893 | }; |
807 | 894 | ||
895 | static struct clk dpll4_m5_ck_3630 __initdata = { | ||
896 | .name = "dpll4_m5_ck", | ||
897 | .ops = &clkops_null, | ||
898 | .parent = &dpll4_ck, | ||
899 | .init = &omap2_init_clksel_parent, | ||
900 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | ||
901 | .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, | ||
902 | .clksel = div32_dpll4_clksel, | ||
903 | .clkdm_name = "dpll4_clkdm", | ||
904 | .recalc = &omap2_clksel_recalc, | ||
905 | }; | ||
906 | |||
808 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 907 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
809 | static struct clk dpll4_m5x2_ck = { | 908 | static struct clk dpll4_m5x2_ck = { |
810 | .name = "dpll4_m5x2_ck", | 909 | .name = "dpll4_m5x2_ck", |
@@ -818,7 +917,9 @@ static struct clk dpll4_m5x2_ck = { | |||
818 | }; | 917 | }; |
819 | 918 | ||
820 | /* This virtual clock is the source for dpll4_m6x2_ck */ | 919 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
821 | static struct clk dpll4_m6_ck = { | 920 | static struct clk dpll4_m6_ck; |
921 | |||
922 | static struct clk dpll4_m6_ck_34xx __initdata = { | ||
822 | .name = "dpll4_m6_ck", | 923 | .name = "dpll4_m6_ck", |
823 | .ops = &clkops_null, | 924 | .ops = &clkops_null, |
824 | .parent = &dpll4_ck, | 925 | .parent = &dpll4_ck, |
@@ -830,6 +931,18 @@ static struct clk dpll4_m6_ck = { | |||
830 | .recalc = &omap2_clksel_recalc, | 931 | .recalc = &omap2_clksel_recalc, |
831 | }; | 932 | }; |
832 | 933 | ||
934 | static struct clk dpll4_m6_ck_3630 __initdata = { | ||
935 | .name = "dpll4_m6_ck", | ||
936 | .ops = &clkops_null, | ||
937 | .parent = &dpll4_ck, | ||
938 | .init = &omap2_init_clksel_parent, | ||
939 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | ||
940 | .clksel_mask = OMAP3630_DIV_DPLL4_MASK, | ||
941 | .clksel = div32_dpll4_clksel, | ||
942 | .clkdm_name = "dpll4_clkdm", | ||
943 | .recalc = &omap2_clksel_recalc, | ||
944 | }; | ||
945 | |||
833 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 946 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
834 | static struct clk dpll4_m6x2_ck = { | 947 | static struct clk dpll4_m6x2_ck = { |
835 | .name = "dpll4_m6x2_ck", | 948 | .name = "dpll4_m6x2_ck", |
@@ -3384,6 +3497,19 @@ int __init omap3xxx_clk_init(void) | |||
3384 | } | 3497 | } |
3385 | 3498 | ||
3386 | if (cpu_is_omap3630()) { | 3499 | if (cpu_is_omap3630()) { |
3500 | cpu_mask |= RATE_IN_36XX; | ||
3501 | cpu_clkflg |= CK_36XX; | ||
3502 | |||
3503 | /* | ||
3504 | * XXX This type of dynamic rewriting of the clock tree is | ||
3505 | * deprecated and should be revised soon. | ||
3506 | */ | ||
3507 | dpll4_m2_ck = dpll4_m2_ck_3630; | ||
3508 | dpll4_m3_ck = dpll4_m3_ck_3630; | ||
3509 | dpll4_m4_ck = dpll4_m4_ck_3630; | ||
3510 | dpll4_m5_ck = dpll4_m5_ck_3630; | ||
3511 | dpll4_m6_ck = dpll4_m6_ck_3630; | ||
3512 | |||
3387 | /* | 3513 | /* |
3388 | * For 3630: override clkops_omap2_dflt_wait for the | 3514 | * For 3630: override clkops_omap2_dflt_wait for the |
3389 | * clocks affected from PWRDN reset Limitation | 3515 | * clocks affected from PWRDN reset Limitation |
@@ -3400,6 +3526,16 @@ int __init omap3xxx_clk_init(void) | |||
3400 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | 3526 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
3401 | dpll4_m6x2_ck.ops = | 3527 | dpll4_m6x2_ck.ops = |
3402 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; | 3528 | &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; |
3529 | } else { | ||
3530 | /* | ||
3531 | * XXX This type of dynamic rewriting of the clock tree is | ||
3532 | * deprecated and should be revised soon. | ||
3533 | */ | ||
3534 | dpll4_m2_ck = dpll4_m2_ck_34xx; | ||
3535 | dpll4_m3_ck = dpll4_m3_ck_34xx; | ||
3536 | dpll4_m4_ck = dpll4_m4_ck_34xx; | ||
3537 | dpll4_m5_ck = dpll4_m5_ck_34xx; | ||
3538 | dpll4_m6_ck = dpll4_m6_ck_34xx; | ||
3403 | } | 3539 | } |
3404 | 3540 | ||
3405 | if (cpu_is_omap3630()) | 3541 | if (cpu_is_omap3630()) |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 29cd13b838ca..e6a724cc63f1 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -542,6 +542,7 @@ | |||
542 | /* CM_CLKSEL3_PLL */ | 542 | /* CM_CLKSEL3_PLL */ |
543 | #define OMAP3430_DIV_96M_SHIFT 0 | 543 | #define OMAP3430_DIV_96M_SHIFT 0 |
544 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | 544 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) |
545 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
545 | 546 | ||
546 | /* CM_CLKSEL4_PLL */ | 547 | /* CM_CLKSEL4_PLL */ |
547 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | 548 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 |
@@ -588,8 +589,10 @@ | |||
588 | /* CM_CLKSEL_DSS */ | 589 | /* CM_CLKSEL_DSS */ |
589 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 590 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
590 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | 591 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) |
592 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
591 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 593 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
592 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | 594 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) |
595 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
593 | 596 | ||
594 | /* CM_SLEEPDEP_DSS specific bits */ | 597 | /* CM_SLEEPDEP_DSS specific bits */ |
595 | 598 | ||
@@ -617,6 +620,7 @@ | |||
617 | /* CM_CLKSEL_CAM */ | 620 | /* CM_CLKSEL_CAM */ |
618 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 621 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
619 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | 622 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) |
623 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
620 | 624 | ||
621 | /* CM_SLEEPDEP_CAM specific bits */ | 625 | /* CM_SLEEPDEP_CAM specific bits */ |
622 | 626 | ||
@@ -712,6 +716,7 @@ | |||
712 | /* CM_CLKSEL1_EMU */ | 716 | /* CM_CLKSEL1_EMU */ |
713 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 717 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
714 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | 718 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) |
719 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
715 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 720 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
716 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | 721 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) |
717 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 722 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index f5f30c73db33..63a233490d6d 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
@@ -167,8 +167,9 @@ extern const struct clkops clkops_null; | |||
167 | #define RATE_IN_242X (1 << 1) | 167 | #define RATE_IN_242X (1 << 1) |
168 | #define RATE_IN_243X (1 << 2) | 168 | #define RATE_IN_243X (1 << 2) |
169 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | 169 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ |
170 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | 170 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ |
171 | #define RATE_IN_4430 (1 << 5) | 171 | #define RATE_IN_36XX (1 << 5) |
172 | #define RATE_IN_4430 (1 << 6) | ||
172 | 173 | ||
173 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 174 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
174 | 175 | ||