diff options
-rw-r--r-- | MAINTAINERS | 10 | ||||
-rw-r--r-- | arch/arm/Kconfig | 19 | ||||
-rw-r--r-- | arch/arm/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 147 | ||||
-rw-r--r-- | arch/arm/boot/dts/socfpga_cyclone5.dts | 34 | ||||
-rw-r--r-- | arch/arm/configs/socfpga_defconfig | 83 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/Makefile.boot | 1 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/debug-macro.S | 16 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/timex.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/uncompress.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/socfpga.c | 62 | ||||
-rw-r--r-- | drivers/clk/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/socfpga/Makefile | 1 | ||||
-rw-r--r-- | drivers/clk/socfpga/clk.c | 51 | ||||
-rw-r--r-- | include/linux/dw_apb_timer.h | 1 |
16 files changed, 460 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index b8a65fbf0473..ab55a785d427 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
@@ -1111,6 +1111,16 @@ S: Supported | |||
1111 | F: arch/arm/mach-shmobile/ | 1111 | F: arch/arm/mach-shmobile/ |
1112 | F: drivers/sh/ | 1112 | F: drivers/sh/ |
1113 | 1113 | ||
1114 | ARM/SOCFPGA ARCHITECTURE | ||
1115 | M: Dinh Nguyen <dinguyen@altera.com> | ||
1116 | S: Maintained | ||
1117 | F: arch/arm/mach-socfpga/ | ||
1118 | |||
1119 | ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT | ||
1120 | M: Dinh Nguyen <dinguyen@altera.com> | ||
1121 | S: Maintained | ||
1122 | F: drivers/clk/socfpga/ | ||
1123 | |||
1114 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT | 1124 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT |
1115 | M: Lennert Buytenhek <kernel@wantstofly.org> | 1125 | M: Lennert Buytenhek <kernel@wantstofly.org> |
1116 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 1126 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7e3d9317c0bf..dfeca559d700 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -250,6 +250,25 @@ choice | |||
250 | prompt "ARM system type" | 250 | prompt "ARM system type" |
251 | default ARCH_VERSATILE | 251 | default ARCH_VERSATILE |
252 | 252 | ||
253 | config ARCH_SOCFPGA | ||
254 | bool "Altera SOCFPGA family" | ||
255 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
256 | select ARM_AMBA | ||
257 | select ARM_GIC | ||
258 | select CACHE_L2X0 | ||
259 | select CLKDEV_LOOKUP | ||
260 | select COMMON_CLK | ||
261 | select CPU_V7 | ||
262 | select DW_APB_TIMER | ||
263 | select DW_APB_TIMER_OF | ||
264 | select GENERIC_CLOCKEVENTS | ||
265 | select GPIO_PL061 if GPIOLIB | ||
266 | select HAVE_ARM_SCU | ||
267 | select SPARSE_IRQ | ||
268 | select USE_OF | ||
269 | help | ||
270 | This enables support for Altera SOCFPGA Cyclone V platform | ||
271 | |||
253 | config ARCH_INTEGRATOR | 272 | config ARCH_INTEGRATOR |
254 | bool "ARM Ltd. Integrator family" | 273 | bool "ARM Ltd. Integrator family" |
255 | select ARM_AMBA | 274 | select ARM_AMBA |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f1a1a7170103..4d6d31115cf2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress | |||
187 | machine-$(CONFIG_ARCH_VT8500) := vt8500 | 187 | machine-$(CONFIG_ARCH_VT8500) := vt8500 |
188 | machine-$(CONFIG_ARCH_W90X900) := w90x900 | 188 | machine-$(CONFIG_ARCH_W90X900) := w90x900 |
189 | machine-$(CONFIG_FOOTBRIDGE) := footbridge | 189 | machine-$(CONFIG_FOOTBRIDGE) := footbridge |
190 | machine-$(CONFIG_ARCH_SOCFPGA) := socfpga | ||
190 | machine-$(CONFIG_MACH_SPEAR1310) := spear13xx | 191 | machine-$(CONFIG_MACH_SPEAR1310) := spear13xx |
191 | machine-$(CONFIG_MACH_SPEAR1340) := spear13xx | 192 | machine-$(CONFIG_MACH_SPEAR1340) := spear13xx |
192 | machine-$(CONFIG_MACH_SPEAR300) := spear3xx | 193 | machine-$(CONFIG_MACH_SPEAR300) := spear3xx |
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi new file mode 100644 index 000000000000..0772f5739f59 --- /dev/null +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
@@ -0,0 +1,147 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Altera <www.altera.com> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | |||
18 | /include/ "skeleton.dtsi" | ||
19 | |||
20 | / { | ||
21 | #address-cells = <1>; | ||
22 | #size-cells = <1>; | ||
23 | |||
24 | aliases { | ||
25 | ethernet0 = &gmac0; | ||
26 | serial0 = &uart0; | ||
27 | serial1 = &uart1; | ||
28 | }; | ||
29 | |||
30 | cpus { | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <0>; | ||
33 | |||
34 | cpu@0 { | ||
35 | compatible = "arm,cortex-a9"; | ||
36 | device_type = "cpu"; | ||
37 | reg = <0>; | ||
38 | next-level-cache = <&L2>; | ||
39 | }; | ||
40 | cpu@1 { | ||
41 | compatible = "arm,cortex-a9"; | ||
42 | device_type = "cpu"; | ||
43 | reg = <1>; | ||
44 | next-level-cache = <&L2>; | ||
45 | }; | ||
46 | }; | ||
47 | |||
48 | intc: intc@fffed000 { | ||
49 | compatible = "arm,cortex-a9-gic"; | ||
50 | #interrupt-cells = <3>; | ||
51 | interrupt-controller; | ||
52 | reg = <0xfffed000 0x1000>, | ||
53 | <0xfffec100 0x100>; | ||
54 | }; | ||
55 | |||
56 | soc { | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <1>; | ||
59 | compatible = "simple-bus"; | ||
60 | device_type = "soc"; | ||
61 | interrupt-parent = <&intc>; | ||
62 | ranges; | ||
63 | |||
64 | amba { | ||
65 | compatible = "arm,amba-bus"; | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <1>; | ||
68 | ranges; | ||
69 | |||
70 | pdma: pdma@ffe01000 { | ||
71 | compatible = "arm,pl330", "arm,primecell"; | ||
72 | reg = <0xffe01000 0x1000>; | ||
73 | interrupts = <0 180 4>; | ||
74 | }; | ||
75 | }; | ||
76 | |||
77 | gmac0: stmmac@ff700000 { | ||
78 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | ||
79 | reg = <0xff700000 0x2000>; | ||
80 | interrupts = <0 115 4>; | ||
81 | interrupt-names = "macirq"; | ||
82 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | ||
83 | phy-mode = "gmii"; | ||
84 | }; | ||
85 | |||
86 | L2: l2-cache@fffef000 { | ||
87 | compatible = "arm,pl310-cache"; | ||
88 | reg = <0xfffef000 0x1000>; | ||
89 | interrupts = <0 38 0x04>; | ||
90 | cache-unified; | ||
91 | cache-level = <2>; | ||
92 | }; | ||
93 | |||
94 | /* Local timer */ | ||
95 | timer@fffec600 { | ||
96 | compatible = "arm,cortex-a9-twd-timer"; | ||
97 | reg = <0xfffec600 0x100>; | ||
98 | interrupts = <1 13 0xf04>; | ||
99 | }; | ||
100 | |||
101 | timer0: timer@ffc08000 { | ||
102 | compatible = "snps,dw-apb-timer-sp"; | ||
103 | interrupts = <0 167 4>; | ||
104 | clock-frequency = <200000000>; | ||
105 | reg = <0xffc08000 0x1000>; | ||
106 | }; | ||
107 | |||
108 | timer1: timer@ffc09000 { | ||
109 | compatible = "snps,dw-apb-timer-sp"; | ||
110 | interrupts = <0 168 4>; | ||
111 | clock-frequency = <200000000>; | ||
112 | reg = <0xffc09000 0x1000>; | ||
113 | }; | ||
114 | |||
115 | timer2: timer@ffd00000 { | ||
116 | compatible = "snps,dw-apb-timer-osc"; | ||
117 | interrupts = <0 169 4>; | ||
118 | clock-frequency = <200000000>; | ||
119 | reg = <0xffd00000 0x1000>; | ||
120 | }; | ||
121 | |||
122 | timer3: timer@ffd01000 { | ||
123 | compatible = "snps,dw-apb-timer-osc"; | ||
124 | interrupts = <0 170 4>; | ||
125 | clock-frequency = <200000000>; | ||
126 | reg = <0xffd01000 0x1000>; | ||
127 | }; | ||
128 | |||
129 | uart0: uart@ffc02000 { | ||
130 | compatible = "snps,dw-apb-uart"; | ||
131 | reg = <0xffc02000 0x1000>; | ||
132 | clock-frequency = <7372800>; | ||
133 | interrupts = <0 162 4>; | ||
134 | reg-shift = <2>; | ||
135 | reg-io-width = <4>; | ||
136 | }; | ||
137 | |||
138 | uart1: uart@ffc03000 { | ||
139 | compatible = "snps,dw-apb-uart"; | ||
140 | reg = <0xffc03000 0x1000>; | ||
141 | clock-frequency = <7372800>; | ||
142 | interrupts = <0 163 4>; | ||
143 | reg-shift = <2>; | ||
144 | reg-io-width = <4>; | ||
145 | }; | ||
146 | }; | ||
147 | }; | ||
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts new file mode 100644 index 000000000000..ab7e4a94299f --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | |||
18 | /dts-v1/; | ||
19 | /include/ "socfpga.dtsi" | ||
20 | |||
21 | / { | ||
22 | model = "Altera SOCFPGA Cyclone V"; | ||
23 | compatible = "altr,socfpga-cyclone5"; | ||
24 | |||
25 | chosen { | ||
26 | bootargs = "console=ttyS0,57600"; | ||
27 | }; | ||
28 | |||
29 | memory { | ||
30 | name = "memory"; | ||
31 | device_type = "memory"; | ||
32 | reg = <0x0 0x10000000>; /* 256MB */ | ||
33 | }; | ||
34 | }; | ||
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig new file mode 100644 index 000000000000..0ac1293dba10 --- /dev/null +++ b/arch/arm/configs/socfpga_defconfig | |||
@@ -0,0 +1,83 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSVIPC=y | ||
3 | CONFIG_IKCONFIG=y | ||
4 | CONFIG_IKCONFIG_PROC=y | ||
5 | CONFIG_LOG_BUF_SHIFT=14 | ||
6 | CONFIG_CGROUPS=y | ||
7 | CONFIG_CPUSETS=y | ||
8 | CONFIG_NAMESPACES=y | ||
9 | CONFIG_EMBEDDED=y | ||
10 | CONFIG_PROFILING=y | ||
11 | CONFIG_OPROFILE=y | ||
12 | CONFIG_MODULES=y | ||
13 | CONFIG_MODULE_UNLOAD=y | ||
14 | # CONFIG_LBDAF is not set | ||
15 | # CONFIG_BLK_DEV_BSG is not set | ||
16 | # CONFIG_IOSCHED_DEADLINE is not set | ||
17 | # CONFIG_IOSCHED_CFQ is not set | ||
18 | CONFIG_ARCH_SOCFPGA=y | ||
19 | CONFIG_MACH_SOCFPGA_CYCLONE5=y | ||
20 | CONFIG_ARM_THUMBEE=y | ||
21 | # CONFIG_CACHE_L2X0 is not set | ||
22 | CONFIG_HIGH_RES_TIMERS=y | ||
23 | CONFIG_VMSPLIT_2G=y | ||
24 | CONFIG_NR_CPUS=2 | ||
25 | CONFIG_AEABI=y | ||
26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
28 | CONFIG_CMDLINE="" | ||
29 | CONFIG_VFP=y | ||
30 | CONFIG_NEON=y | ||
31 | CONFIG_NET=y | ||
32 | CONFIG_PACKET=y | ||
33 | CONFIG_UNIX=y | ||
34 | CONFIG_NET_KEY=y | ||
35 | CONFIG_NET_KEY_MIGRATE=y | ||
36 | CONFIG_INET=y | ||
37 | CONFIG_IP_MULTICAST=y | ||
38 | CONFIG_IP_PNP=y | ||
39 | CONFIG_IP_PNP_DHCP=y | ||
40 | CONFIG_IP_PNP_BOOTP=y | ||
41 | CONFIG_IP_PNP_RARP=y | ||
42 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
43 | CONFIG_DEVTMPFS=y | ||
44 | CONFIG_PROC_DEVICETREE=y | ||
45 | CONFIG_BLK_DEV_RAM=y | ||
46 | CONFIG_BLK_DEV_RAM_COUNT=2 | ||
47 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
48 | CONFIG_SCSI=y | ||
49 | # CONFIG_SCSI_PROC_FS is not set | ||
50 | CONFIG_BLK_DEV_SD=y | ||
51 | # CONFIG_SCSI_LOWLEVEL is not set | ||
52 | CONFIG_NETDEVICES=y | ||
53 | CONFIG_STMMAC_ETH=y | ||
54 | # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set | ||
55 | CONFIG_INPUT_EVDEV=y | ||
56 | # CONFIG_SERIO_SERPORT is not set | ||
57 | CONFIG_SERIO_AMBAKMI=y | ||
58 | CONFIG_LEGACY_PTY_COUNT=16 | ||
59 | CONFIG_SERIAL_8250=y | ||
60 | CONFIG_SERIAL_8250_CONSOLE=y | ||
61 | CONFIG_SERIAL_8250_NR_UARTS=2 | ||
62 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | ||
63 | CONFIG_SERIAL_8250_DW=y | ||
64 | # CONFIG_RTC_HCTOSYS is not set | ||
65 | CONFIG_EXT2_FS=y | ||
66 | CONFIG_EXT2_FS_XATTR=y | ||
67 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
68 | # CONFIG_DNOTIFY is not set | ||
69 | # CONFIG_INOTIFY_USER is not set | ||
70 | CONFIG_VFAT_FS=y | ||
71 | CONFIG_NTFS_FS=y | ||
72 | CONFIG_NTFS_RW=y | ||
73 | CONFIG_TMPFS=y | ||
74 | CONFIG_JFFS2_FS=y | ||
75 | CONFIG_NLS_CODEPAGE_437=y | ||
76 | CONFIG_NLS_ISO8859_1=y | ||
77 | CONFIG_MAGIC_SYSRQ=y | ||
78 | CONFIG_DETECT_HUNG_TASK=y | ||
79 | # CONFIG_SCHED_DEBUG is not set | ||
80 | CONFIG_DEBUG_INFO=y | ||
81 | CONFIG_ENABLE_DEFAULT_TRACERS=y | ||
82 | CONFIG_DEBUG_USER=y | ||
83 | CONFIG_XZ_DEC=y | ||
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile new file mode 100644 index 000000000000..4fb93240971d --- /dev/null +++ b/arch/arm/mach-socfpga/Makefile | |||
@@ -0,0 +1,5 @@ | |||
1 | # | ||
2 | # Makefile for the linux kernel. | ||
3 | # | ||
4 | |||
5 | obj-y := socfpga.o | ||
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot new file mode 100644 index 000000000000..dae9661a7689 --- /dev/null +++ b/arch/arm/mach-socfpga/Makefile.boot | |||
@@ -0,0 +1 @@ | |||
zreladdr-y := 0x00008000 | |||
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S new file mode 100644 index 000000000000..d6f26d23374f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1994-1999 Russell King | ||
3 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | .macro addruart, rp, rv, tmp | ||
11 | mov \rp, #DEBUG_LL_UART_OFFSET | ||
12 | orr \rp, \rp, #0x00c00000 | ||
13 | orr \rv, \rp, #0xfe000000 @ virtual base | ||
14 | orr \rp, \rp, #0xff000000 @ physical base | ||
15 | .endm | ||
16 | |||
diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h new file mode 100644 index 000000000000..43df4354e461 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/timex.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2003 ARM Limited | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
18 | |||
19 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h new file mode 100644 index 000000000000..bbe20e696325 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/uncompress.h | |||
@@ -0,0 +1,9 @@ | |||
1 | #ifndef __MACH_UNCOMPRESS_H | ||
2 | #define __MACH_UNCOMPRESS_H | ||
3 | |||
4 | #define putc(c) | ||
5 | #define flush() | ||
6 | #define arch_decomp_setup() | ||
7 | #define arch_decomp_wdog() | ||
8 | |||
9 | #endif | ||
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c new file mode 100644 index 000000000000..f01e1ebf5396 --- /dev/null +++ b/arch/arm/mach-socfpga/socfpga.c | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Altera Corporation | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | #include <linux/dw_apb_timer.h> | ||
18 | #include <linux/of_irq.h> | ||
19 | #include <linux/of_platform.h> | ||
20 | |||
21 | #include <asm/hardware/cache-l2x0.h> | ||
22 | #include <asm/hardware/gic.h> | ||
23 | #include <asm/mach/arch.h> | ||
24 | |||
25 | extern void socfpga_init_clocks(void); | ||
26 | |||
27 | const static struct of_device_id irq_match[] = { | ||
28 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, | ||
29 | {} | ||
30 | }; | ||
31 | |||
32 | static void __init gic_init_irq(void) | ||
33 | { | ||
34 | of_irq_init(irq_match); | ||
35 | } | ||
36 | |||
37 | static void socfpga_cyclone5_restart(char mode, const char *cmd) | ||
38 | { | ||
39 | /* TODO: */ | ||
40 | } | ||
41 | |||
42 | static void __init socfpga_cyclone5_init(void) | ||
43 | { | ||
44 | l2x0_of_init(0, ~0UL); | ||
45 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
46 | socfpga_init_clocks(); | ||
47 | } | ||
48 | |||
49 | static const char *altera_dt_match[] = { | ||
50 | "altr,socfpga", | ||
51 | "altr,socfpga-cyclone5", | ||
52 | NULL | ||
53 | }; | ||
54 | |||
55 | DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") | ||
56 | .init_irq = gic_init_irq, | ||
57 | .handle_irq = gic_handle_irq, | ||
58 | .timer = &dw_apb_timer, | ||
59 | .init_machine = socfpga_cyclone5_init, | ||
60 | .restart = socfpga_cyclone5_restart, | ||
61 | .dt_compat = altera_dt_match, | ||
62 | MACHINE_END | ||
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b9a5158a30b1..96014e89f1ac 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile | |||
@@ -4,4 +4,5 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ | |||
4 | clk-mux.o clk-divider.o clk-fixed-factor.o | 4 | clk-mux.o clk-divider.o clk-fixed-factor.o |
5 | # SoCs specific | 5 | # SoCs specific |
6 | obj-$(CONFIG_ARCH_MXS) += mxs/ | 6 | obj-$(CONFIG_ARCH_MXS) += mxs/ |
7 | obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ | ||
7 | obj-$(CONFIG_PLAT_SPEAR) += spear/ | 8 | obj-$(CONFIG_PLAT_SPEAR) += spear/ |
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile new file mode 100644 index 000000000000..0303c0b99cd0 --- /dev/null +++ b/drivers/clk/socfpga/Makefile | |||
@@ -0,0 +1 @@ | |||
obj-y += clk.o | |||
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c new file mode 100644 index 000000000000..2c855a6394ff --- /dev/null +++ b/drivers/clk/socfpga/clk.c | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | #include <linux/clk.h> | ||
18 | #include <linux/clkdev.h> | ||
19 | #include <linux/clk-provider.h> | ||
20 | |||
21 | #define SOCFPGA_OSC1_CLK 10000000 | ||
22 | #define SOCFPGA_MPU_CLK 800000000 | ||
23 | #define SOCFPGA_MAIN_QSPI_CLK 432000000 | ||
24 | #define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000 | ||
25 | #define SOCFPGA_S2F_USR_CLK 125000000 | ||
26 | |||
27 | void __init socfpga_init_clocks(void) | ||
28 | { | ||
29 | struct clk *clk; | ||
30 | |||
31 | clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK); | ||
32 | clk_register_clkdev(clk, "osc1_clk", NULL); | ||
33 | |||
34 | clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK); | ||
35 | clk_register_clkdev(clk, "mpu_clk", NULL); | ||
36 | |||
37 | clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); | ||
38 | clk_register_clkdev(clk, "main_clk", NULL); | ||
39 | |||
40 | clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); | ||
41 | clk_register_clkdev(clk, "dbg_base_clk", NULL); | ||
42 | |||
43 | clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK); | ||
44 | clk_register_clkdev(clk, "main_qspi_clk", NULL); | ||
45 | |||
46 | clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK); | ||
47 | clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL); | ||
48 | |||
49 | clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK); | ||
50 | clk_register_clkdev(clk, "s2f_usr_clk", NULL); | ||
51 | } | ||
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h index 07261d52a6df..1148575fd134 100644 --- a/include/linux/dw_apb_timer.h +++ b/include/linux/dw_apb_timer.h | |||
@@ -53,4 +53,5 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs); | |||
53 | cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs); | 53 | cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs); |
54 | void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs); | 54 | void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs); |
55 | 55 | ||
56 | extern struct sys_timer dw_apb_timer; | ||
56 | #endif /* __DW_APB_TIMER_H__ */ | 57 | #endif /* __DW_APB_TIMER_H__ */ |