38 files changed, 6792 insertions, 11045 deletions

diff --git a/drivers/atm/he.c b/drivers/atm/he.c
index 29e66d603d3c..70667033a568 100644
--- a/drivers/atm/he.c
+++ b/drivers/atm/he.c
@@ -921,9 +921,9 @@ out_free_rbpq_base:
                         he_dev->rbrq_phys);
         i = CONFIG_RBPL_SIZE;
 out_free_rbpl_virt:
-        while (--i)
-                pci_pool_free(he_dev->rbps_pool, he_dev->rbpl_virt[i].virt,
-                                he_dev->rbps_base[i].phys);
+        while (i--)
+                pci_pool_free(he_dev->rbpl_pool, he_dev->rbpl_virt[i].virt,
+                                he_dev->rbpl_base[i].phys);
         kfree(he_dev->rbpl_virt);
 
 out_free_rbpl_base:
@@ -933,11 +933,11 @@ out_free_rbpl_base:
 out_destroy_rbpl_pool:
         pci_pool_destroy(he_dev->rbpl_pool);
 
-        i = CONFIG_RBPL_SIZE;
+        i = CONFIG_RBPS_SIZE;
 out_free_rbps_virt:
-        while (--i)
-                pci_pool_free(he_dev->rbpl_pool, he_dev->rbps_virt[i].virt,
-                                he_dev->rbpl_base[i].phys);
+        while (i--)
+                pci_pool_free(he_dev->rbps_pool, he_dev->rbps_virt[i].virt,
+                                he_dev->rbps_base[i].phys);
         kfree(he_dev->rbps_virt);
 
 out_free_rbps_base:
diff --git a/drivers/isdn/hardware/mISDN/Kconfig b/drivers/isdn/hardware/mISDN/Kconfig
index bde55d7287fa..eadc1cd34a20 100644
--- a/drivers/isdn/hardware/mISDN/Kconfig
+++ b/drivers/isdn/hardware/mISDN/Kconfig
@@ -78,6 +78,7 @@ config MISDN_NETJET
         depends on PCI
         select MISDN_IPAC
         select ISDN_HDLC
+        select ISDN_I4L
         help
           Enable support for Traverse Technologies NETJet PCI cards.
 
diff --git a/drivers/isdn/i4l/Kconfig b/drivers/isdn/i4l/Kconfig
index dd744ffd240b..07c4e49f9e77 100644
--- a/drivers/isdn/i4l/Kconfig
+++ b/drivers/isdn/i4l/Kconfig
@@ -141,8 +141,7 @@ endmenu
 endif
 
 config ISDN_HDLC
-        tristate 
-        depends on HISAX_ST5481
+        tristate
         select CRC_CCITT
         select BITREVERSE
 
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 1a4f89c66a26..42e2b7e21c29 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -149,7 +149,6 @@ do {									\
 
 #define AUTO_ALL_MODES            0
 #define E1000_EEPROM_82544_APM    0x0004
-#define E1000_EEPROM_ICH8_APME    0x0004
 #define E1000_EEPROM_APME         0x0400
 
 #ifndef E1000_MASTER_SLAVE
@@ -293,7 +292,6 @@ struct e1000_adapter {
 
         u64 hw_csum_err;
         u64 hw_csum_good;
-        u64 rx_hdr_split;
         u32 alloc_rx_buff_failed;
         u32 rx_int_delay;
         u32 rx_abs_int_delay;
@@ -317,7 +315,6 @@ struct e1000_adapter {
         struct e1000_rx_ring test_rx_ring;
 
         int msg_enable;
-        bool have_msi;
 
         /* to not mess up cache alignment, always add to the bottom */
         bool tso_force;
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 27f996a2010f..490b2b7cd3ab 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -82,7 +82,6 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
         { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
         { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
         { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
-        { "rx_header_split", E1000_STAT(rx_hdr_split) },
         { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
         { "tx_smbus", E1000_STAT(stats.mgptc) },
         { "rx_smbus", E1000_STAT(stats.mgprc) },
@@ -114,8 +113,6 @@ static int e1000_get_settings(struct net_device *netdev,
                                    SUPPORTED_1000baseT_Full|
                                    SUPPORTED_Autoneg |
                                    SUPPORTED_TP);
-                if (hw->phy_type == e1000_phy_ife)
-                        ecmd->supported &= ~SUPPORTED_1000baseT_Full;
                 ecmd->advertising = ADVERTISED_TP;
 
                 if (hw->autoneg == 1) {
@@ -178,14 +175,6 @@ static int e1000_set_settings(struct net_device *netdev,
         struct e1000_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
 
-        /* When SoL/IDER sessions are active, autoneg/speed/duplex
-         * cannot be changed */
-        if (e1000_check_phy_reset_block(hw)) {
-                DPRINTK(DRV, ERR, "Cannot change link characteristics "
-                        "when SoL/IDER is active.\n");
-                return -EINVAL;
-        }
-
         while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
                 msleep(1);
 
@@ -330,10 +319,7 @@ static int e1000_set_tso(struct net_device *netdev, u32 data)
         else
                 netdev->features &= ~NETIF_F_TSO;
 
-        if (data && (adapter->hw.mac_type > e1000_82547_rev_2))
-                netdev->features |= NETIF_F_TSO6;
-        else
-                netdev->features &= ~NETIF_F_TSO6;
+        netdev->features &= ~NETIF_F_TSO6;
 
         DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled");
         adapter->tso_force = true;
@@ -441,7 +427,6 @@ static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
         regs_buff[24] = (u32)phy_data;  /* phy local receiver status */
         regs_buff[25] = regs_buff[24];  /* phy remote receiver status */
         if (hw->mac_type >= e1000_82540 &&
-            hw->mac_type < e1000_82571 &&
             hw->media_type == e1000_media_type_copper) {
                 regs_buff[26] = er32(MANC);
         }
@@ -554,10 +539,8 @@ static int e1000_set_eeprom(struct net_device *netdev,
         ret_val = e1000_write_eeprom(hw, first_word,
                                      last_word - first_word + 1, eeprom_buff);
 
-        /* Update the checksum over the first part of the EEPROM if needed
-         * and flush shadow RAM for 82573 conrollers */
-        if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) ||
-                                (hw->mac_type == e1000_82573)))
+        /* Update the checksum over the first part of the EEPROM if needed */
+        if ((ret_val == 0) && (first_word <= EEPROM_CHECKSUM_REG))
                 e1000_update_eeprom_checksum(hw);
 
         kfree(eeprom_buff);
@@ -568,31 +551,12 @@ static void e1000_get_drvinfo(struct net_device *netdev,
                               struct ethtool_drvinfo *drvinfo)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
-        struct e1000_hw *hw = &adapter->hw;
         char firmware_version[32];
-        u16 eeprom_data;
 
         strncpy(drvinfo->driver,  e1000_driver_name, 32);
         strncpy(drvinfo->version, e1000_driver_version, 32);
 
-        /* EEPROM image version # is reported as firmware version # for
-         * 8257{1|2|3} controllers */
-        e1000_read_eeprom(hw, 5, 1, &eeprom_data);
-        switch (hw->mac_type) {
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_82573:
-        case e1000_80003es2lan:
-        case e1000_ich8lan:
-                sprintf(firmware_version, "%d.%d-%d",
-                        (eeprom_data & 0xF000) >> 12,
-                        (eeprom_data & 0x0FF0) >> 4,
-                        eeprom_data & 0x000F);
-                break;
-        default:
-                sprintf(firmware_version, "N/A");
-        }
-
+        sprintf(firmware_version, "N/A");
         strncpy(drvinfo->fw_version, firmware_version, 32);
         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
         drvinfo->regdump_len = e1000_get_regs_len(netdev);
@@ -781,21 +745,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
         /* The status register is Read Only, so a write should fail.
          * Some bits that get toggled are ignored.
          */
-        switch (hw->mac_type) {
+
         /* there are several bits on newer hardware that are r/w */
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_80003es2lan:
-                toggle = 0x7FFFF3FF;
-                break;
-        case e1000_82573:
-        case e1000_ich8lan:
-                toggle = 0x7FFFF033;
-                break;
-        default:
-                toggle = 0xFFFFF833;
-                break;
-        }
+        toggle = 0xFFFFF833;
 
         before = er32(STATUS);
         value = (er32(STATUS) & toggle);
@@ -810,12 +762,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
         /* restore previous status */
         ew32(STATUS, before);
 
-        if (hw->mac_type != e1000_ich8lan) {
-                REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
-                REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
-                REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
-                REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
-        }
+        REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
+        REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
+        REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
+        REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
 
         REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
         REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
@@ -830,8 +780,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
 
         REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
 
-        before = (hw->mac_type == e1000_ich8lan ?
-                  0x06C3B33E : 0x06DFB3FE);
+        before = 0x06DFB3FE;
         REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
         REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
 
@@ -839,12 +788,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
 
                 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
                 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
-                if (hw->mac_type != e1000_ich8lan)
-                        REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
+                REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
                 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
                 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
-                value = (hw->mac_type == e1000_ich8lan ?
-                         E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
+                value = E1000_RAR_ENTRIES;
                 for (i = 0; i < value; i++) {
                         REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
                                          0xFFFFFFFF);
@@ -859,8 +806,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
 
         }
 
-        value = (hw->mac_type == e1000_ich8lan ?
-                        E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
+        value = E1000_MC_TBL_SIZE;
         for (i = 0; i < value; i++)
                 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
 
@@ -933,9 +879,6 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
         /* Test each interrupt */
         for (; i < 10; i++) {
 
-                if (hw->mac_type == e1000_ich8lan && i == 8)
-                        continue;
-
                 /* Interrupt to test */
                 mask = 1 << i;
 
@@ -1289,35 +1232,20 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
                 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140);
                 /* autoneg off */
                 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
-        } else if (hw->phy_type == e1000_phy_gg82563)
-                e1000_write_phy_reg(hw,
-                                    GG82563_PHY_KMRN_MODE_CTRL,
-                                    0x1CC);
+        }
 
         ctrl_reg = er32(CTRL);
 
-        if (hw->phy_type == e1000_phy_ife) {
-                /* force 100, set loopback */
-                e1000_write_phy_reg(hw, PHY_CTRL, 0x6100);
+        /* force 1000, set loopback */
+        e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
 
-                /* Now set up the MAC to the same speed/duplex as the PHY. */
-                ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
-                ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
-                             E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
-                             E1000_CTRL_SPD_100 |/* Force Speed to 100 */
-                             E1000_CTRL_FD);     /* Force Duplex to FULL */
-        } else {
-                /* force 1000, set loopback */
-                e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
-
-                /* Now set up the MAC to the same speed/duplex as the PHY. */
-                ctrl_reg = er32(CTRL);
-                ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
-                ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
-                             E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
-                             E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
-                             E1000_CTRL_FD);     /* Force Duplex to FULL */
-        }
+        /* Now set up the MAC to the same speed/duplex as the PHY. */
+        ctrl_reg = er32(CTRL);
+        ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
+        ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
+                        E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
+                        E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
+                        E1000_CTRL_FD);  /* Force Duplex to FULL */
 
         if (hw->media_type == e1000_media_type_copper &&
            hw->phy_type == e1000_phy_m88)
@@ -1373,14 +1301,8 @@ static int e1000_set_phy_loopback(struct e1000_adapter *adapter)
         case e1000_82541_rev_2:
         case e1000_82547:
         case e1000_82547_rev_2:
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_82573:
-        case e1000_80003es2lan:
-        case e1000_ich8lan:
                 return e1000_integrated_phy_loopback(adapter);
                 break;
-
         default:
                 /* Default PHY loopback work is to read the MII
                  * control register and assert bit 14 (loopback mode).
@@ -1409,14 +1331,6 @@ static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
                 case e1000_82546_rev_3:
                         return e1000_set_phy_loopback(adapter);
                         break;
-                case e1000_82571:
-                case e1000_82572:
-#define E1000_SERDES_LB_ON 0x410
-                        e1000_set_phy_loopback(adapter);
-                        ew32(SCTL, E1000_SERDES_LB_ON);
-                        msleep(10);
-                        return 0;
-                        break;
                 default:
                         rctl = er32(RCTL);
                         rctl |= E1000_RCTL_LBM_TCVR;
@@ -1440,26 +1354,12 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
         ew32(RCTL, rctl);
 
         switch (hw->mac_type) {
-        case e1000_82571:
-        case e1000_82572:
-                if (hw->media_type == e1000_media_type_fiber ||
-                    hw->media_type == e1000_media_type_internal_serdes) {
-#define E1000_SERDES_LB_OFF 0x400
-                        ew32(SCTL, E1000_SERDES_LB_OFF);
-                        msleep(10);
-                        break;
-                }
-                /* Fall Through */
         case e1000_82545:
         case e1000_82546:
         case e1000_82545_rev_3:
         case e1000_82546_rev_3:
         default:
                 hw->autoneg = true;
-                if (hw->phy_type == e1000_phy_gg82563)
-                        e1000_write_phy_reg(hw,
-                                            GG82563_PHY_KMRN_MODE_CTRL,
-                                            0x180);
                 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
                 if (phy_reg & MII_CR_LOOPBACK) {
                         phy_reg &= ~MII_CR_LOOPBACK;
@@ -1560,17 +1460,6 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
 
 static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
 {
-        struct e1000_hw *hw = &adapter->hw;
-
-        /* PHY loopback cannot be performed if SoL/IDER
-         * sessions are active */
-        if (e1000_check_phy_reset_block(hw)) {
-                DPRINTK(DRV, ERR, "Cannot do PHY loopback test "
-                        "when SoL/IDER is active.\n");
-                *data = 0;
-                goto out;
-        }
-
         *data = e1000_setup_desc_rings(adapter);
         if (*data)
                 goto out;
@@ -1592,13 +1481,13 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
         *data = 0;
         if (hw->media_type == e1000_media_type_internal_serdes) {
                 int i = 0;
-                hw->serdes_link_down = true;
+                hw->serdes_has_link = false;
 
                 /* On some blade server designs, link establishment
                  * could take as long as 2-3 minutes */
                 do {
                         e1000_check_for_link(hw);
-                        if (!hw->serdes_link_down)
+                        if (hw->serdes_has_link)
                                 return *data;
                         msleep(20);
                 } while (i++ < 3750);
@@ -1716,15 +1605,11 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter,
         case E1000_DEV_ID_82545EM_COPPER:
         case E1000_DEV_ID_82546GB_QUAD_COPPER:
         case E1000_DEV_ID_82546GB_PCIE:
-        case E1000_DEV_ID_82571EB_SERDES_QUAD:
                 /* these don't support WoL at all */
                 wol->supported = 0;
                 break;
         case E1000_DEV_ID_82546EB_FIBER:
         case E1000_DEV_ID_82546GB_FIBER:
-        case E1000_DEV_ID_82571EB_FIBER:
-        case E1000_DEV_ID_82571EB_SERDES:
-        case E1000_DEV_ID_82571EB_COPPER:
                 /* Wake events not supported on port B */
                 if (er32(STATUS) & E1000_STATUS_FUNC_1) {
                         wol->supported = 0;
@@ -1733,10 +1618,6 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter,
                 /* return success for non excluded adapter ports */
                 retval = 0;
                 break;
-        case E1000_DEV_ID_82571EB_QUAD_COPPER:
-        case E1000_DEV_ID_82571EB_QUAD_FIBER:
-        case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
-        case E1000_DEV_ID_82571PT_QUAD_COPPER:
         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
                 /* quad port adapters only support WoL on port A */
                 if (!adapter->quad_port_a) {
@@ -1872,30 +1753,15 @@ static int e1000_phys_id(struct net_device *netdev, u32 data)
         if (!data)
                 data = INT_MAX;
 
-        if (hw->mac_type < e1000_82571) {
-                if (!adapter->blink_timer.function) {
-                        init_timer(&adapter->blink_timer);
-                        adapter->blink_timer.function = e1000_led_blink_callback;
-                        adapter->blink_timer.data = (unsigned long)adapter;
-                }
-                e1000_setup_led(hw);
-                mod_timer(&adapter->blink_timer, jiffies);
-                msleep_interruptible(data * 1000);
-                del_timer_sync(&adapter->blink_timer);
-        } else if (hw->phy_type == e1000_phy_ife) {
-                if (!adapter->blink_timer.function) {
-                        init_timer(&adapter->blink_timer);
-                        adapter->blink_timer.function = e1000_led_blink_callback;
-                        adapter->blink_timer.data = (unsigned long)adapter;
-                }
-                mod_timer(&adapter->blink_timer, jiffies);
-                msleep_interruptible(data * 1000);
-                del_timer_sync(&adapter->blink_timer);
-                e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
-        } else {
-                e1000_blink_led_start(hw);
-                msleep_interruptible(data * 1000);
+        if (!adapter->blink_timer.function) {
+                init_timer(&adapter->blink_timer);
+                adapter->blink_timer.function = e1000_led_blink_callback;
+                adapter->blink_timer.data = (unsigned long)adapter;
         }
+        e1000_setup_led(hw);
+        mod_timer(&adapter->blink_timer, jiffies);
+        msleep_interruptible(data * 1000);
+        del_timer_sync(&adapter->blink_timer);
 
         e1000_led_off(hw);
         clear_bit(E1000_LED_ON, &adapter->led_status);
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 45ac225a7aaa..8d7d87f12827 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -24,88 +24,34 @@
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
-*******************************************************************************/
+ */
 
 /* e1000_hw.c
  * Shared functions for accessing and configuring the MAC
  */
 
-
 #include "e1000_hw.h"
 
-static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
-static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
-static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
-static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
-static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
-static void e1000_release_software_semaphore(struct e1000_hw *hw);
-
-static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
 static s32 e1000_check_downshift(struct e1000_hw *hw);
 static s32 e1000_check_polarity(struct e1000_hw *hw,
                                 e1000_rev_polarity *polarity);
 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
 static void e1000_clear_vfta(struct e1000_hw *hw);
-static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
                                               bool link_up);
 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
-static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
                                   u16 *max_length);
-static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
-static s32 e1000_get_software_flag(struct e1000_hw *hw);
-static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
-static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
 static s32 e1000_id_led_init(struct e1000_hw *hw);
-static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
-                                                 u32 cnf_base_addr,
-                                                 u32 cnf_size);
-static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
 static void e1000_init_rx_addrs(struct e1000_hw *hw);
-static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
-static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
-static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
-static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
-static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
-                                   u16 offset, u8 *sum);
-static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
-                                      struct e1000_host_mng_command_header
-                                      *hdr);
-static s32 e1000_mng_write_commit(struct e1000_hw *hw);
-static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
-                                  struct e1000_phy_info *phy_info);
 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
                                   struct e1000_phy_info *phy_info);
-static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data);
-static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data);
-static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
                                   struct e1000_phy_info *phy_info);
-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
-static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
-static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
-                                        u8 byte);
-static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
-static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
-static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
-                                u16 *data);
-static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
-                                 u16 data);
-static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data);
-static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data);
-static void e1000_release_software_flag(struct e1000_hw *hw);
 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
-static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
-static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
-static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
 static s32 e1000_set_phy_type(struct e1000_hw *hw);
@@ -117,12 +63,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
-static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
-                                     u16 count);
+static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
-                                      u16 words, u16 *data);
+                                  u16 words, u16 *data);
 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
                                         u16 words, u16 *data);
 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
@@ -131,7 +76,7 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                   u16 phy_data);
-static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
+static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                  u16 *phy_data);
 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
@@ -140,188 +85,164 @@ static void e1000_standby_eeprom(struct e1000_hw *hw);
 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
-static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
-static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
-static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
-static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
-static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
-static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                u16 *data);
+static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                 u16 *data);
 
 /* IGP cable length table */
 static const
-u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
-    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
-      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
-      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
-      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
-      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
-      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
-      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
-
-static const
-u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
-    { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
-      0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
-      6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
-      21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
-      40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
-      60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
-      83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
-      104, 109, 114, 118, 121, 124};
+u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
+        5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+        5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
+        25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
+        40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
+        60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
+        90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
+            100,
+        100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
+            110, 110,
+        110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
+            120, 120
+};
 
 static DEFINE_SPINLOCK(e1000_eeprom_lock);
 
-/******************************************************************************
- * Set the phy type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_set_phy_type - Set the phy type member in the hw struct.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_set_phy_type(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_set_phy_type");
-
-    if (hw->mac_type == e1000_undefined)
-        return -E1000_ERR_PHY_TYPE;
-
-    switch (hw->phy_id) {
-    case M88E1000_E_PHY_ID:
-    case M88E1000_I_PHY_ID:
-    case M88E1011_I_PHY_ID:
-    case M88E1111_I_PHY_ID:
-        hw->phy_type = e1000_phy_m88;
-        break;
-    case IGP01E1000_I_PHY_ID:
-        if (hw->mac_type == e1000_82541 ||
-            hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            hw->phy_type = e1000_phy_igp;
-            break;
-        }
-    case IGP03E1000_E_PHY_ID:
-        hw->phy_type = e1000_phy_igp_3;
-        break;
-    case IFE_E_PHY_ID:
-    case IFE_PLUS_E_PHY_ID:
-    case IFE_C_E_PHY_ID:
-        hw->phy_type = e1000_phy_ife;
-        break;
-    case GG82563_E_PHY_ID:
-        if (hw->mac_type == e1000_80003es2lan) {
-            hw->phy_type = e1000_phy_gg82563;
-            break;
-        }
-        /* Fall Through */
-    default:
-        /* Should never have loaded on this device */
-        hw->phy_type = e1000_phy_undefined;
-        return -E1000_ERR_PHY_TYPE;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * IGP phy init script - initializes the GbE PHY
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void e1000_phy_init_script(struct e1000_hw *hw)
-{
-    u32 ret_val;
-    u16 phy_saved_data;
-
-    DEBUGFUNC("e1000_phy_init_script");
-
-    if (hw->phy_init_script) {
-        msleep(20);
-
-        /* Save off the current value of register 0x2F5B to be restored at
-         * the end of this routine. */
-        ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-        /* Disabled the PHY transmitter */
-        e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+        DEBUGFUNC("e1000_set_phy_type");
 
-        msleep(20);
+        if (hw->mac_type == e1000_undefined)
+                return -E1000_ERR_PHY_TYPE;
 
-        e1000_write_phy_reg(hw,0x0000,0x0140);
-
-        msleep(5);
-
-        switch (hw->mac_type) {
-        case e1000_82541:
-        case e1000_82547:
-            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
-
-            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
-
-            e1000_write_phy_reg(hw, 0x1F79, 0x0018);
-
-            e1000_write_phy_reg(hw, 0x1F30, 0x1600);
-
-            e1000_write_phy_reg(hw, 0x1F31, 0x0014);
-
-            e1000_write_phy_reg(hw, 0x1F32, 0x161C);
-
-            e1000_write_phy_reg(hw, 0x1F94, 0x0003);
-
-            e1000_write_phy_reg(hw, 0x1F96, 0x003F);
-
-            e1000_write_phy_reg(hw, 0x2010, 0x0008);
-            break;
-
-        case e1000_82541_rev_2:
-        case e1000_82547_rev_2:
-            e1000_write_phy_reg(hw, 0x1F73, 0x0099);
-            break;
-        default:
-            break;
-        }
-
-        e1000_write_phy_reg(hw, 0x0000, 0x3300);
-
-        msleep(20);
-
-        /* Now enable the transmitter */
-        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-        if (hw->mac_type == e1000_82547) {
-            u16 fused, fine, coarse;
-
-            /* Move to analog registers page */
-            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
-
-            if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
-                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+        switch (hw->phy_id) {
+        case M88E1000_E_PHY_ID:
+        case M88E1000_I_PHY_ID:
+        case M88E1011_I_PHY_ID:
+        case M88E1111_I_PHY_ID:
+                hw->phy_type = e1000_phy_m88;
+                break;
+        case IGP01E1000_I_PHY_ID:
+                if (hw->mac_type == e1000_82541 ||
+                    hw->mac_type == e1000_82541_rev_2 ||
+                    hw->mac_type == e1000_82547 ||
+                    hw->mac_type == e1000_82547_rev_2) {
+                        hw->phy_type = e1000_phy_igp;
+                        break;
+                }
+        default:
+                /* Should never have loaded on this device */
+                hw->phy_type = e1000_phy_undefined;
+                return -E1000_ERR_PHY_TYPE;
+        }
 
-                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
-                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+        return E1000_SUCCESS;
+}
 
-                if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
-                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
-                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
-                } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
-                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+/**
+ * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
+ * @hw: Struct containing variables accessed by shared code
+ */
+static void e1000_phy_init_script(struct e1000_hw *hw)
+{
+        u32 ret_val;
+        u16 phy_saved_data;
+
+        DEBUGFUNC("e1000_phy_init_script");
+
+        if (hw->phy_init_script) {
+                msleep(20);
+
+                /* Save off the current value of register 0x2F5B to be restored at
+                 * the end of this routine. */
+                ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+                /* Disabled the PHY transmitter */
+                e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+                msleep(20);
+
+                e1000_write_phy_reg(hw, 0x0000, 0x0140);
+                msleep(5);
+
+                switch (hw->mac_type) {
+                case e1000_82541:
+                case e1000_82547:
+                        e1000_write_phy_reg(hw, 0x1F95, 0x0001);
+                        e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
+                        e1000_write_phy_reg(hw, 0x1F79, 0x0018);
+                        e1000_write_phy_reg(hw, 0x1F30, 0x1600);
+                        e1000_write_phy_reg(hw, 0x1F31, 0x0014);
+                        e1000_write_phy_reg(hw, 0x1F32, 0x161C);
+                        e1000_write_phy_reg(hw, 0x1F94, 0x0003);
+                        e1000_write_phy_reg(hw, 0x1F96, 0x003F);
+                        e1000_write_phy_reg(hw, 0x2010, 0x0008);
+                        break;
 
-                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
-                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
-                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+                case e1000_82541_rev_2:
+                case e1000_82547_rev_2:
+                        e1000_write_phy_reg(hw, 0x1F73, 0x0099);
+                        break;
+                default:
+                        break;
+                }
 
-                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
-                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
-                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
-            }
-        }
-    }
+                e1000_write_phy_reg(hw, 0x0000, 0x3300);
+                msleep(20);
+
+                /* Now enable the transmitter */
+                e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+                if (hw->mac_type == e1000_82547) {
+                        u16 fused, fine, coarse;
+
+                        /* Move to analog registers page */
+                        e1000_read_phy_reg(hw,
+                                           IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
+                                           &fused);
+
+                        if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+                                e1000_read_phy_reg(hw,
+                                                   IGP01E1000_ANALOG_FUSE_STATUS,
+                                                   &fused);
+
+                                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+                                coarse =
+                                    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+
+                                if (coarse >
+                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+                                        coarse -=
+                                            IGP01E1000_ANALOG_FUSE_COARSE_10;
+                                        fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+                                } else if (coarse ==
+                                           IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+                                        fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+
+                                fused =
+                                    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+                                    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+                                    (coarse &
+                                     IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+
+                                e1000_write_phy_reg(hw,
+                                                    IGP01E1000_ANALOG_FUSE_CONTROL,
+                                                    fused);
+                                e1000_write_phy_reg(hw,
+                                                    IGP01E1000_ANALOG_FUSE_BYPASS,
+                                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+                        }
+                }
+        }
 }
 
-/******************************************************************************
- * Set the mac type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_set_mac_type - Set the mac type member in the hw struct.
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_set_mac_type(struct e1000_hw *hw)
 {
         DEBUGFUNC("e1000_set_mac_type");
@@ -397,61 +318,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
         case E1000_DEV_ID_82547GI:
                 hw->mac_type = e1000_82547_rev_2;
                 break;
-        case E1000_DEV_ID_82571EB_COPPER:
-        case E1000_DEV_ID_82571EB_FIBER:
-        case E1000_DEV_ID_82571EB_SERDES:
-        case E1000_DEV_ID_82571EB_SERDES_DUAL:
-        case E1000_DEV_ID_82571EB_SERDES_QUAD:
-        case E1000_DEV_ID_82571EB_QUAD_COPPER:
-        case E1000_DEV_ID_82571PT_QUAD_COPPER:
-        case E1000_DEV_ID_82571EB_QUAD_FIBER:
-        case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
-                hw->mac_type = e1000_82571;
-                break;
-        case E1000_DEV_ID_82572EI_COPPER:
-        case E1000_DEV_ID_82572EI_FIBER:
-        case E1000_DEV_ID_82572EI_SERDES:
-        case E1000_DEV_ID_82572EI:
-                hw->mac_type = e1000_82572;
-                break;
-        case E1000_DEV_ID_82573E:
-        case E1000_DEV_ID_82573E_IAMT:
-        case E1000_DEV_ID_82573L:
-                hw->mac_type = e1000_82573;
-                break;
-        case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
-        case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
-        case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
-        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
-                hw->mac_type = e1000_80003es2lan;
-                break;
-        case E1000_DEV_ID_ICH8_IGP_M_AMT:
-        case E1000_DEV_ID_ICH8_IGP_AMT:
-        case E1000_DEV_ID_ICH8_IGP_C:
-        case E1000_DEV_ID_ICH8_IFE:
-        case E1000_DEV_ID_ICH8_IFE_GT:
-        case E1000_DEV_ID_ICH8_IFE_G:
-        case E1000_DEV_ID_ICH8_IGP_M:
-                hw->mac_type = e1000_ich8lan;
-                break;
         default:
                 /* Should never have loaded on this device */
                 return -E1000_ERR_MAC_TYPE;
         }
 
         switch (hw->mac_type) {
-        case e1000_ich8lan:
-                hw->swfwhw_semaphore_present = true;
-                hw->asf_firmware_present = true;
-                break;
-        case e1000_80003es2lan:
-                hw->swfw_sync_present = true;
-                /* fall through */
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_82573:
-                hw->eeprom_semaphore_present = true;
-                /* fall through */
         case e1000_82541:
         case e1000_82547:
         case e1000_82541_rev_2:
@@ -468,6058 +340,4500 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
         if (hw->mac_type == e1000_82543)
                 hw->bad_tx_carr_stats_fd = true;
 
-        /* capable of receiving management packets to the host */
-        if (hw->mac_type >= e1000_82571)
-                hw->has_manc2h = true;
-
-        /* In rare occasions, ESB2 systems would end up started without
-         * the RX unit being turned on.
-         */
-        if (hw->mac_type == e1000_80003es2lan)
-                hw->rx_needs_kicking = true;
-
         if (hw->mac_type > e1000_82544)
                 hw->has_smbus = true;
 
         return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- * Set media type and TBI compatibility.
- *
- * hw - Struct containing variables accessed by shared code
- * **************************************************************************/
+/**
+ * e1000_set_media_type - Set media type and TBI compatibility.
+ * @hw: Struct containing variables accessed by shared code
+ */
 void e1000_set_media_type(struct e1000_hw *hw)
 {
-    u32 status;
-
-    DEBUGFUNC("e1000_set_media_type");
-
-    if (hw->mac_type != e1000_82543) {
-        /* tbi_compatibility is only valid on 82543 */
-        hw->tbi_compatibility_en = false;
-    }
-
-    switch (hw->device_id) {
-    case E1000_DEV_ID_82545GM_SERDES:
-    case E1000_DEV_ID_82546GB_SERDES:
-    case E1000_DEV_ID_82571EB_SERDES:
-    case E1000_DEV_ID_82571EB_SERDES_DUAL:
-    case E1000_DEV_ID_82571EB_SERDES_QUAD:
-    case E1000_DEV_ID_82572EI_SERDES:
-    case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
-        hw->media_type = e1000_media_type_internal_serdes;
-        break;
-    default:
-        switch (hw->mac_type) {
-        case e1000_82542_rev2_0:
-        case e1000_82542_rev2_1:
-            hw->media_type = e1000_media_type_fiber;
-            break;
-        case e1000_ich8lan:
-        case e1000_82573:
-            /* The STATUS_TBIMODE bit is reserved or reused for the this
-             * device.
-             */
-            hw->media_type = e1000_media_type_copper;
-            break;
-        default:
-            status = er32(STATUS);
-            if (status & E1000_STATUS_TBIMODE) {
-                hw->media_type = e1000_media_type_fiber;
-                /* tbi_compatibility not valid on fiber */
-                hw->tbi_compatibility_en = false;
-            } else {
-                hw->media_type = e1000_media_type_copper;
-            }
-            break;
-        }
-    }
+        u32 status;
+
+        DEBUGFUNC("e1000_set_media_type");
+
+        if (hw->mac_type != e1000_82543) {
+                /* tbi_compatibility is only valid on 82543 */
+                hw->tbi_compatibility_en = false;
+        }
+
+        switch (hw->device_id) {
+        case E1000_DEV_ID_82545GM_SERDES:
+        case E1000_DEV_ID_82546GB_SERDES:
+                hw->media_type = e1000_media_type_internal_serdes;
+                break;
+        default:
+                switch (hw->mac_type) {
+                case e1000_82542_rev2_0:
+                case e1000_82542_rev2_1:
+                        hw->media_type = e1000_media_type_fiber;
+                        break;
+                default:
+                        status = er32(STATUS);
+                        if (status & E1000_STATUS_TBIMODE) {
+                                hw->media_type = e1000_media_type_fiber;
+                                /* tbi_compatibility not valid on fiber */
+                                hw->tbi_compatibility_en = false;
+                        } else {
+                                hw->media_type = e1000_media_type_copper;
+                        }
+                        break;
+                }
+        }
 }
 
-/******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
+/**
+ * e1000_reset_hw: reset the hardware completely
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ */
 s32 e1000_reset_hw(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u32 ctrl_ext;
-    u32 icr;
-    u32 manc;
-    u32 led_ctrl;
-    u32 timeout;
-    u32 extcnf_ctrl;
-    s32 ret_val;
-
-    DEBUGFUNC("e1000_reset_hw");
-
-    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-        e1000_pci_clear_mwi(hw);
-    }
-
-    if (hw->bus_type == e1000_bus_type_pci_express) {
-        /* Prevent the PCI-E bus from sticking if there is no TLP connection
-         * on the last TLP read/write transaction when MAC is reset.
-         */
-        if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
-            DEBUGOUT("PCI-E Master disable polling has failed.\n");
-        }
-    }
-
-    /* Clear interrupt mask to stop board from generating interrupts */
-    DEBUGOUT("Masking off all interrupts\n");
-    ew32(IMC, 0xffffffff);
-
-    /* Disable the Transmit and Receive units.  Then delay to allow
-     * any pending transactions to complete before we hit the MAC with
-     * the global reset.
-     */
-    ew32(RCTL, 0);
-    ew32(TCTL, E1000_TCTL_PSP);
-    E1000_WRITE_FLUSH();
-
-    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-    hw->tbi_compatibility_on = false;
-
-    /* Delay to allow any outstanding PCI transactions to complete before
-     * resetting the device
-     */
-    msleep(10);
-
-    ctrl = er32(CTRL);
-
-    /* Must reset the PHY before resetting the MAC */
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
-        msleep(5);
-    }
-
-    /* Must acquire the MDIO ownership before MAC reset.
-     * Ownership defaults to firmware after a reset. */
-    if (hw->mac_type == e1000_82573) {
-        timeout = 10;
-
-        extcnf_ctrl = er32(EXTCNF_CTRL);
-        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-        do {
-            ew32(EXTCNF_CTRL, extcnf_ctrl);
-            extcnf_ctrl = er32(EXTCNF_CTRL);
-
-            if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
-                break;
-            else
-                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-            msleep(2);
-            timeout--;
-        } while (timeout);
-    }
-
-    /* Workaround for ICH8 bit corruption issue in FIFO memory */
-    if (hw->mac_type == e1000_ich8lan) {
-        /* Set Tx and Rx buffer allocation to 8k apiece. */
-        ew32(PBA, E1000_PBA_8K);
-        /* Set Packet Buffer Size to 16k. */
-        ew32(PBS, E1000_PBS_16K);
-    }
-
-    /* Issue a global reset to the MAC.  This will reset the chip's
-     * transmit, receive, DMA, and link units.  It will not effect
-     * the current PCI configuration.  The global reset bit is self-
-     * clearing, and should clear within a microsecond.
-     */
-    DEBUGOUT("Issuing a global reset to MAC\n");
-
-    switch (hw->mac_type) {
-        case e1000_82544:
-        case e1000_82540:
-        case e1000_82545:
-        case e1000_82546:
-        case e1000_82541:
-        case e1000_82541_rev_2:
-            /* These controllers can't ack the 64-bit write when issuing the
-             * reset, so use IO-mapping as a workaround to issue the reset */
-            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
-            break;
-        case e1000_82545_rev_3:
-        case e1000_82546_rev_3:
-            /* Reset is performed on a shadow of the control register */
-            ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
-            break;
-        case e1000_ich8lan:
-            if (!hw->phy_reset_disable &&
-                e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
-                /* e1000_ich8lan PHY HW reset requires MAC CORE reset
-                 * at the same time to make sure the interface between
-                 * MAC and the external PHY is reset.
-                 */
-                ctrl |= E1000_CTRL_PHY_RST;
-            }
-
-            e1000_get_software_flag(hw);
-            ew32(CTRL, (ctrl | E1000_CTRL_RST));
-            msleep(5);
-            break;
-        default:
-            ew32(CTRL, (ctrl | E1000_CTRL_RST));
-            break;
-    }
-
-    /* After MAC reset, force reload of EEPROM to restore power-on settings to
-     * device.  Later controllers reload the EEPROM automatically, so just wait
-     * for reload to complete.
-     */
-    switch (hw->mac_type) {
-        case e1000_82542_rev2_0:
-        case e1000_82542_rev2_1:
-        case e1000_82543:
-        case e1000_82544:
-            /* Wait for reset to complete */
-            udelay(10);
-            ctrl_ext = er32(CTRL_EXT);
-            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-            ew32(CTRL_EXT, ctrl_ext);
-            E1000_WRITE_FLUSH();
-            /* Wait for EEPROM reload */
-            msleep(2);
-            break;
-        case e1000_82541:
-        case e1000_82541_rev_2:
-        case e1000_82547:
-        case e1000_82547_rev_2:
-            /* Wait for EEPROM reload */
-            msleep(20);
-            break;
-        case e1000_82573:
-            if (!e1000_is_onboard_nvm_eeprom(hw)) {
-                udelay(10);
-                ctrl_ext = er32(CTRL_EXT);
-                ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-                ew32(CTRL_EXT, ctrl_ext);
-                E1000_WRITE_FLUSH();
-            }
-            /* fall through */
-        default:
-            /* Auto read done will delay 5ms or poll based on mac type */
-            ret_val = e1000_get_auto_rd_done(hw);
-            if (ret_val)
-                return ret_val;
-            break;
-    }
-
-    /* Disable HW ARPs on ASF enabled adapters */
-    if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
-        manc = er32(MANC);
-        manc &= ~(E1000_MANC_ARP_EN);
-        ew32(MANC, manc);
-    }
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        e1000_phy_init_script(hw);
-
-        /* Configure activity LED after PHY reset */
-        led_ctrl = er32(LEDCTL);
-        led_ctrl &= IGP_ACTIVITY_LED_MASK;
-        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-        ew32(LEDCTL, led_ctrl);
-    }
-
-    /* Clear interrupt mask to stop board from generating interrupts */
-    DEBUGOUT("Masking off all interrupts\n");
-    ew32(IMC, 0xffffffff);
-
-    /* Clear any pending interrupt events. */
-    icr = er32(ICR);
-
-    /* If MWI was previously enabled, reenable it. */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
-            e1000_pci_set_mwi(hw);
-    }
-
-    if (hw->mac_type == e1000_ich8lan) {
-        u32 kab = er32(KABGTXD);
-        kab |= E1000_KABGTXD_BGSQLBIAS;
-        ew32(KABGTXD, kab);
-    }
-
-    return E1000_SUCCESS;
-}
+        u32 ctrl;
+        u32 ctrl_ext;
+        u32 icr;
+        u32 manc;
+        u32 led_ctrl;
+        s32 ret_val;
 
-/******************************************************************************
- *
- * Initialize a number of hardware-dependent bits
- *
- * hw: Struct containing variables accessed by shared code
- *
- * This function contains hardware limitation workarounds for PCI-E adapters
- *
- *****************************************************************************/
-static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
-{
-    if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
-        /* Settings common to all PCI-express silicon */
-        u32 reg_ctrl, reg_ctrl_ext;
-        u32 reg_tarc0, reg_tarc1;
-        u32 reg_tctl;
-        u32 reg_txdctl, reg_txdctl1;
-
-        /* link autonegotiation/sync workarounds */
-        reg_tarc0 = er32(TARC0);
-        reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
-
-        /* Enable not-done TX descriptor counting */
-        reg_txdctl = er32(TXDCTL);
-        reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
-        ew32(TXDCTL, reg_txdctl);
-        reg_txdctl1 = er32(TXDCTL1);
-        reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
-        ew32(TXDCTL1, reg_txdctl1);
-
-        switch (hw->mac_type) {
-            case e1000_82571:
-            case e1000_82572:
-                /* Clear PHY TX compatible mode bits */
-                reg_tarc1 = er32(TARC1);
-                reg_tarc1 &= ~((1 << 30)|(1 << 29));
-
-                /* link autonegotiation/sync workarounds */
-                reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
-
-                /* TX ring control fixes */
-                reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
-
-                /* Multiple read bit is reversed polarity */
-                reg_tctl = er32(TCTL);
-                if (reg_tctl & E1000_TCTL_MULR)
-                    reg_tarc1 &= ~(1 << 28);
-                else
-                    reg_tarc1 |= (1 << 28);
-
-                ew32(TARC1, reg_tarc1);
-                break;
-            case e1000_82573:
-                reg_ctrl_ext = er32(CTRL_EXT);
-                reg_ctrl_ext &= ~(1 << 23);
-                reg_ctrl_ext |= (1 << 22);
-
-                /* TX byte count fix */
-                reg_ctrl = er32(CTRL);
-                reg_ctrl &= ~(1 << 29);
-
-                ew32(CTRL_EXT, reg_ctrl_ext);
-                ew32(CTRL, reg_ctrl);
-                break;
-            case e1000_80003es2lan:
-                /* improve small packet performace for fiber/serdes */
-                if ((hw->media_type == e1000_media_type_fiber) ||
-                    (hw->media_type == e1000_media_type_internal_serdes)) {
-                    reg_tarc0 &= ~(1 << 20);
-                }
-
-                /* Multiple read bit is reversed polarity */
-                reg_tctl = er32(TCTL);
-                reg_tarc1 = er32(TARC1);
-                if (reg_tctl & E1000_TCTL_MULR)
-                    reg_tarc1 &= ~(1 << 28);
-                else
-                    reg_tarc1 |= (1 << 28);
-
-                ew32(TARC1, reg_tarc1);
-                break;
-            case e1000_ich8lan:
-                /* Reduce concurrent DMA requests to 3 from 4 */
-                if ((hw->revision_id < 3) ||
-                    ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
-                     (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
-                    reg_tarc0 |= ((1 << 29)|(1 << 28));
-
-                reg_ctrl_ext = er32(CTRL_EXT);
-                reg_ctrl_ext |= (1 << 22);
-                ew32(CTRL_EXT, reg_ctrl_ext);
-
-                /* workaround TX hang with TSO=on */
-                reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
-
-                /* Multiple read bit is reversed polarity */
-                reg_tctl = er32(TCTL);
-                reg_tarc1 = er32(TARC1);
-                if (reg_tctl & E1000_TCTL_MULR)
-                    reg_tarc1 &= ~(1 << 28);
-                else
-                    reg_tarc1 |= (1 << 28);
-
-                /* workaround TX hang with TSO=on */
-                reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
-
-                ew32(TARC1, reg_tarc1);
-                break;
-            default:
-                break;
-        }
-
-        ew32(TARC0, reg_tarc0);
-    }
+        DEBUGFUNC("e1000_reset_hw");
+
+        /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
+        if (hw->mac_type == e1000_82542_rev2_0) {
+                DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+                e1000_pci_clear_mwi(hw);
+        }
+
+        /* Clear interrupt mask to stop board from generating interrupts */
+        DEBUGOUT("Masking off all interrupts\n");
+        ew32(IMC, 0xffffffff);
+
+        /* Disable the Transmit and Receive units.  Then delay to allow
+         * any pending transactions to complete before we hit the MAC with
+         * the global reset.
+         */
+        ew32(RCTL, 0);
+        ew32(TCTL, E1000_TCTL_PSP);
+        E1000_WRITE_FLUSH();
+
+        /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
+        hw->tbi_compatibility_on = false;
+
+        /* Delay to allow any outstanding PCI transactions to complete before
+         * resetting the device
+         */
+        msleep(10);
+
+        ctrl = er32(CTRL);
+
+        /* Must reset the PHY before resetting the MAC */
+        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+                ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
+                msleep(5);
+        }
+
+        /* Issue a global reset to the MAC.  This will reset the chip's
+         * transmit, receive, DMA, and link units.  It will not effect
+         * the current PCI configuration.  The global reset bit is self-
+         * clearing, and should clear within a microsecond.
+         */
+        DEBUGOUT("Issuing a global reset to MAC\n");
+
+        switch (hw->mac_type) {
+        case e1000_82544:
+        case e1000_82540:
+        case e1000_82545:
+        case e1000_82546:
+        case e1000_82541:
+        case e1000_82541_rev_2:
+                /* These controllers can't ack the 64-bit write when issuing the
+                 * reset, so use IO-mapping as a workaround to issue the reset */
+                E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
+                break;
+        case e1000_82545_rev_3:
+        case e1000_82546_rev_3:
+                /* Reset is performed on a shadow of the control register */
+                ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
+                break;
+        default:
+                ew32(CTRL, (ctrl | E1000_CTRL_RST));
+                break;
+        }
+
+        /* After MAC reset, force reload of EEPROM to restore power-on settings to
+         * device.  Later controllers reload the EEPROM automatically, so just wait
+         * for reload to complete.
+         */
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+        case e1000_82544:
+                /* Wait for reset to complete */
+                udelay(10);
+                ctrl_ext = er32(CTRL_EXT);
+                ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+                ew32(CTRL_EXT, ctrl_ext);
+                E1000_WRITE_FLUSH();
+                /* Wait for EEPROM reload */
+                msleep(2);
+                break;
+        case e1000_82541:
+        case e1000_82541_rev_2:
+        case e1000_82547:
+        case e1000_82547_rev_2:
+                /* Wait for EEPROM reload */
+                msleep(20);
+                break;
+        default:
+                /* Auto read done will delay 5ms or poll based on mac type */
+                ret_val = e1000_get_auto_rd_done(hw);
+                if (ret_val)
+                        return ret_val;
+                break;
+        }
+
+        /* Disable HW ARPs on ASF enabled adapters */
+        if (hw->mac_type >= e1000_82540) {
+                manc = er32(MANC);
+                manc &= ~(E1000_MANC_ARP_EN);
+                ew32(MANC, manc);
+        }
+
+        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+                e1000_phy_init_script(hw);
+
+                /* Configure activity LED after PHY reset */
+                led_ctrl = er32(LEDCTL);
+                led_ctrl &= IGP_ACTIVITY_LED_MASK;
+                led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+                ew32(LEDCTL, led_ctrl);
+        }
+
+        /* Clear interrupt mask to stop board from generating interrupts */
+        DEBUGOUT("Masking off all interrupts\n");
+        ew32(IMC, 0xffffffff);
+
+        /* Clear any pending interrupt events. */
+        icr = er32(ICR);
+
+        /* If MWI was previously enabled, reenable it. */
+        if (hw->mac_type == e1000_82542_rev2_0) {
+                if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+                        e1000_pci_set_mwi(hw);
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_init_hw: Performs basic configuration of the adapter.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Assumes that the controller has previously been reset and is in a
  * post-reset uninitialized state. Initializes the receive address registers,
  * multicast table, and VLAN filter table. Calls routines to setup link
  * configuration and flow control settings. Clears all on-chip counters. Leaves
  * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
+ */
 s32 e1000_init_hw(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u32 i;
-    s32 ret_val;
-    u32 mta_size;
-    u32 reg_data;
-    u32 ctrl_ext;
-
-    DEBUGFUNC("e1000_init_hw");
-
-    /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
-    if ((hw->mac_type == e1000_ich8lan) &&
-        ((hw->revision_id < 3) ||
-         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
-          (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
-            reg_data = er32(STATUS);
-            reg_data &= ~0x80000000;
-            ew32(STATUS, reg_data);
-    }
-
-    /* Initialize Identification LED */
-    ret_val = e1000_id_led_init(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Initializing Identification LED\n");
-        return ret_val;
-    }
-
-    /* Set the media type and TBI compatibility */
-    e1000_set_media_type(hw);
-
-    /* Must be called after e1000_set_media_type because media_type is used */
-    e1000_initialize_hardware_bits(hw);
-
-    /* Disabling VLAN filtering. */
-    DEBUGOUT("Initializing the IEEE VLAN\n");
-    /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
-    if (hw->mac_type != e1000_ich8lan) {
-        if (hw->mac_type < e1000_82545_rev_3)
-            ew32(VET, 0);
-        e1000_clear_vfta(hw);
-    }
-
-    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-        e1000_pci_clear_mwi(hw);
-        ew32(RCTL, E1000_RCTL_RST);
-        E1000_WRITE_FLUSH();
-        msleep(5);
-    }
-
-    /* Setup the receive address. This involves initializing all of the Receive
-     * Address Registers (RARs 0 - 15).
-     */
-    e1000_init_rx_addrs(hw);
-
-    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        ew32(RCTL, 0);
-        E1000_WRITE_FLUSH();
-        msleep(1);
-        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
-            e1000_pci_set_mwi(hw);
-    }
-
-    /* Zero out the Multicast HASH table */
-    DEBUGOUT("Zeroing the MTA\n");
-    mta_size = E1000_MC_TBL_SIZE;
-    if (hw->mac_type == e1000_ich8lan)
-        mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
-    for (i = 0; i < mta_size; i++) {
-        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-        /* use write flush to prevent Memory Write Block (MWB) from
-         * occuring when accessing our register space */
-        E1000_WRITE_FLUSH();
-    }
-
-    /* Set the PCI priority bit correctly in the CTRL register.  This
-     * determines if the adapter gives priority to receives, or if it
-     * gives equal priority to transmits and receives.  Valid only on
-     * 82542 and 82543 silicon.
-     */
-    if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
-        ctrl = er32(CTRL);
-        ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
-    }
-
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-        break;
-    default:
-        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-        if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
-                e1000_pcix_set_mmrbc(hw, 2048);
-        break;
-    }
-
-    /* More time needed for PHY to initialize */
-    if (hw->mac_type == e1000_ich8lan)
-        msleep(15);
-
-    /* Call a subroutine to configure the link and setup flow control. */
-    ret_val = e1000_setup_link(hw);
-
-    /* Set the transmit descriptor write-back policy */
-    if (hw->mac_type > e1000_82544) {
-        ctrl = er32(TXDCTL);
-        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-        ew32(TXDCTL, ctrl);
-    }
-
-    if (hw->mac_type == e1000_82573) {
-        e1000_enable_tx_pkt_filtering(hw);
-    }
-
-    switch (hw->mac_type) {
-    default:
-        break;
-    case e1000_80003es2lan:
-        /* Enable retransmit on late collisions */
-        reg_data = er32(TCTL);
-        reg_data |= E1000_TCTL_RTLC;
-        ew32(TCTL, reg_data);
-
-        /* Configure Gigabit Carry Extend Padding */
-        reg_data = er32(TCTL_EXT);
-        reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
-        reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
-        ew32(TCTL_EXT, reg_data);
-
-        /* Configure Transmit Inter-Packet Gap */
-        reg_data = er32(TIPG);
-        reg_data &= ~E1000_TIPG_IPGT_MASK;
-        reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
-        ew32(TIPG, reg_data);
-
-        reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
-        reg_data &= ~0x00100000;
-        E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
-        /* Fall through */
-    case e1000_82571:
-    case e1000_82572:
-    case e1000_ich8lan:
-        ctrl = er32(TXDCTL1);
-        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-        ew32(TXDCTL1, ctrl);
-        break;
-    }
-
-
-    if (hw->mac_type == e1000_82573) {
-        u32 gcr = er32(GCR);
-        gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
-        ew32(GCR, gcr);
-    }
-
-    /* Clear all of the statistics registers (clear on read).  It is
-     * important that we do this after we have tried to establish link
-     * because the symbol error count will increment wildly if there
-     * is no link.
-     */
-    e1000_clear_hw_cntrs(hw);
-
-    /* ICH8 No-snoop bits are opposite polarity.
-     * Set to snoop by default after reset. */
-    if (hw->mac_type == e1000_ich8lan)
-        e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-
-    if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
-        hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
-        ctrl_ext = er32(CTRL_EXT);
-        /* Relaxed ordering must be disabled to avoid a parity
-         * error crash in a PCI slot. */
-        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
-        ew32(CTRL_EXT, ctrl_ext);
-    }
-
-    return ret_val;
+        u32 ctrl;
+        u32 i;
+        s32 ret_val;
+        u32 mta_size;
+        u32 ctrl_ext;
+
+        DEBUGFUNC("e1000_init_hw");
+
+        /* Initialize Identification LED */
+        ret_val = e1000_id_led_init(hw);
+        if (ret_val) {
+                DEBUGOUT("Error Initializing Identification LED\n");
+                return ret_val;
+        }
+
+        /* Set the media type and TBI compatibility */
+        e1000_set_media_type(hw);
+
+        /* Disabling VLAN filtering. */
+        DEBUGOUT("Initializing the IEEE VLAN\n");
+        if (hw->mac_type < e1000_82545_rev_3)
+                ew32(VET, 0);
+        e1000_clear_vfta(hw);
+
+        /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
+        if (hw->mac_type == e1000_82542_rev2_0) {
+                DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+                e1000_pci_clear_mwi(hw);
+                ew32(RCTL, E1000_RCTL_RST);
+                E1000_WRITE_FLUSH();
+                msleep(5);
+        }
+
+        /* Setup the receive address. This involves initializing all of the Receive
+         * Address Registers (RARs 0 - 15).
+         */
+        e1000_init_rx_addrs(hw);
+
+        /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
+        if (hw->mac_type == e1000_82542_rev2_0) {
+                ew32(RCTL, 0);
+                E1000_WRITE_FLUSH();
+                msleep(1);
+                if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+                        e1000_pci_set_mwi(hw);
+        }
+
+        /* Zero out the Multicast HASH table */
+        DEBUGOUT("Zeroing the MTA\n");
+        mta_size = E1000_MC_TBL_SIZE;
+        for (i = 0; i < mta_size; i++) {
+                E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+                /* use write flush to prevent Memory Write Block (MWB) from
+                 * occurring when accessing our register space */
+                E1000_WRITE_FLUSH();
+        }
+
+        /* Set the PCI priority bit correctly in the CTRL register.  This
+         * determines if the adapter gives priority to receives, or if it
+         * gives equal priority to transmits and receives.  Valid only on
+         * 82542 and 82543 silicon.
+         */
+        if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
+                ctrl = er32(CTRL);
+                ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
+        }
+
+        switch (hw->mac_type) {
+        case e1000_82545_rev_3:
+        case e1000_82546_rev_3:
+                break;
+        default:
+                /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
+                if (hw->bus_type == e1000_bus_type_pcix
+                    && e1000_pcix_get_mmrbc(hw) > 2048)
+                        e1000_pcix_set_mmrbc(hw, 2048);
+                break;
+        }
+
+        /* Call a subroutine to configure the link and setup flow control. */
+        ret_val = e1000_setup_link(hw);
+
+        /* Set the transmit descriptor write-back policy */
+        if (hw->mac_type > e1000_82544) {
+                ctrl = er32(TXDCTL);
+                ctrl =
+                    (ctrl & ~E1000_TXDCTL_WTHRESH) |
+                    E1000_TXDCTL_FULL_TX_DESC_WB;
+                ew32(TXDCTL, ctrl);
+        }
+
+        /* Clear all of the statistics registers (clear on read).  It is
+         * important that we do this after we have tried to establish link
+         * because the symbol error count will increment wildly if there
+         * is no link.
+         */
+        e1000_clear_hw_cntrs(hw);
+
+        if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
+            hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
+                ctrl_ext = er32(CTRL_EXT);
+                /* Relaxed ordering must be disabled to avoid a parity
+                 * error crash in a PCI slot. */
+                ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
+                ew32(CTRL_EXT, ctrl_ext);
+        }
+
+        return ret_val;
 }
 
-/******************************************************************************
- * Adjust SERDES output amplitude based on EEPROM setting.
- *
- * hw - Struct containing variables accessed by shared code.
- *****************************************************************************/
+/**
+ * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
+ * @hw: Struct containing variables accessed by shared code.
+ */
 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
 {
-    u16 eeprom_data;
-    s32  ret_val;
-
-    DEBUGFUNC("e1000_adjust_serdes_amplitude");
-
-    if (hw->media_type != e1000_media_type_internal_serdes)
-        return E1000_SUCCESS;
-
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-        break;
-    default:
-        return E1000_SUCCESS;
-    }
-
-    ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
-    if (ret_val) {
-        return ret_val;
-    }
-
-    if (eeprom_data != EEPROM_RESERVED_WORD) {
-        /* Adjust SERDES output amplitude only. */
-        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+        u16 eeprom_data;
+        s32 ret_val;
+
+        DEBUGFUNC("e1000_adjust_serdes_amplitude");
+
+        if (hw->media_type != e1000_media_type_internal_serdes)
+                return E1000_SUCCESS;
+
+        switch (hw->mac_type) {
+        case e1000_82545_rev_3:
+        case e1000_82546_rev_3:
+                break;
+        default:
+                return E1000_SUCCESS;
+        }
+
+        ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
+                                    &eeprom_data);
+        if (ret_val) {
+                return ret_val;
+        }
+
+        if (eeprom_data != EEPROM_RESERVED_WORD) {
+                /* Adjust SERDES output amplitude only. */
+                eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
+                ret_val =
+                    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Configures flow control and link settings.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_setup_link - Configures flow control and link settings.
+ * @hw: Struct containing variables accessed by shared code
  *
- * Determines which flow control settings to use. Calls the apropriate media-
+ * Determines which flow control settings to use. Calls the appropriate media-
  * specific link configuration function. Configures the flow control settings.
  * Assuming the adapter has a valid link partner, a valid link should be
  * established. Assumes the hardware has previously been reset and the
  * transmitter and receiver are not enabled.
- *****************************************************************************/
+ */
 s32 e1000_setup_link(struct e1000_hw *hw)
 {
-    u32 ctrl_ext;
-    s32 ret_val;
-    u16 eeprom_data;
-
-    DEBUGFUNC("e1000_setup_link");
-
-    /* In the case of the phy reset being blocked, we already have a link.
-     * We do not have to set it up again. */
-    if (e1000_check_phy_reset_block(hw))
-        return E1000_SUCCESS;
-
-    /* Read and store word 0x0F of the EEPROM. This word contains bits
-     * that determine the hardware's default PAUSE (flow control) mode,
-     * a bit that determines whether the HW defaults to enabling or
-     * disabling auto-negotiation, and the direction of the
-     * SW defined pins. If there is no SW over-ride of the flow
-     * control setting, then the variable hw->fc will
-     * be initialized based on a value in the EEPROM.
-     */
-    if (hw->fc == E1000_FC_DEFAULT) {
-        switch (hw->mac_type) {
-        case e1000_ich8lan:
-        case e1000_82573:
-            hw->fc = E1000_FC_FULL;
-            break;
-        default:
-            ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
-                                        1, &eeprom_data);
-            if (ret_val) {
-                DEBUGOUT("EEPROM Read Error\n");
-                return -E1000_ERR_EEPROM;
-            }
-            if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
-                hw->fc = E1000_FC_NONE;
-            else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
-                    EEPROM_WORD0F_ASM_DIR)
-                hw->fc = E1000_FC_TX_PAUSE;
-            else
-                hw->fc = E1000_FC_FULL;
-            break;
-        }
-    }
-
-    /* We want to save off the original Flow Control configuration just
-     * in case we get disconnected and then reconnected into a different
-     * hub or switch with different Flow Control capabilities.
-     */
-    if (hw->mac_type == e1000_82542_rev2_0)
-        hw->fc &= (~E1000_FC_TX_PAUSE);
-
-    if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
-        hw->fc &= (~E1000_FC_RX_PAUSE);
-
-    hw->original_fc = hw->fc;
-
-    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
-
-    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
-     * polarity value for the SW controlled pins, and setup the
-     * Extended Device Control reg with that info.
-     * This is needed because one of the SW controlled pins is used for
-     * signal detection.  So this should be done before e1000_setup_pcs_link()
-     * or e1000_phy_setup() is called.
-     */
-    if (hw->mac_type == e1000_82543) {
-        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
-                                    1, &eeprom_data);
-        if (ret_val) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
-                    SWDPIO__EXT_SHIFT);
-        ew32(CTRL_EXT, ctrl_ext);
-    }
-
-    /* Call the necessary subroutine to configure the link. */
-    ret_val = (hw->media_type == e1000_media_type_copper) ?
-              e1000_setup_copper_link(hw) :
-              e1000_setup_fiber_serdes_link(hw);
-
-    /* Initialize the flow control address, type, and PAUSE timer
-     * registers to their default values.  This is done even if flow
-     * control is disabled, because it does not hurt anything to
-     * initialize these registers.
-     */
-    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
-
-    /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
-    if (hw->mac_type != e1000_ich8lan) {
-        ew32(FCT, FLOW_CONTROL_TYPE);
-        ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
-        ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
-    }
-
-    ew32(FCTTV, hw->fc_pause_time);
-
-    /* Set the flow control receive threshold registers.  Normally,
-     * these registers will be set to a default threshold that may be
-     * adjusted later by the driver's runtime code.  However, if the
-     * ability to transmit pause frames in not enabled, then these
-     * registers will be set to 0.
-     */
-    if (!(hw->fc & E1000_FC_TX_PAUSE)) {
-        ew32(FCRTL, 0);
-        ew32(FCRTH, 0);
-    } else {
-        /* We need to set up the Receive Threshold high and low water marks
-         * as well as (optionally) enabling the transmission of XON frames.
-         */
-        if (hw->fc_send_xon) {
-            ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
-            ew32(FCRTH, hw->fc_high_water);
-        } else {
-            ew32(FCRTL, hw->fc_low_water);
-            ew32(FCRTH, hw->fc_high_water);
-        }
-    }
-    return ret_val;
+        u32 ctrl_ext;
+        s32 ret_val;
+        u16 eeprom_data;
+
+        DEBUGFUNC("e1000_setup_link");
+
+        /* Read and store word 0x0F of the EEPROM. This word contains bits
+         * that determine the hardware's default PAUSE (flow control) mode,
+         * a bit that determines whether the HW defaults to enabling or
+         * disabling auto-negotiation, and the direction of the
+         * SW defined pins. If there is no SW over-ride of the flow
+         * control setting, then the variable hw->fc will
+         * be initialized based on a value in the EEPROM.
+         */
+        if (hw->fc == E1000_FC_DEFAULT) {
+                ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                            1, &eeprom_data);
+                if (ret_val) {
+                        DEBUGOUT("EEPROM Read Error\n");
+                        return -E1000_ERR_EEPROM;
+                }
+                if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+                        hw->fc = E1000_FC_NONE;
+                else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
+                         EEPROM_WORD0F_ASM_DIR)
+                        hw->fc = E1000_FC_TX_PAUSE;
+                else
+                        hw->fc = E1000_FC_FULL;
+        }
+
+        /* We want to save off the original Flow Control configuration just
+         * in case we get disconnected and then reconnected into a different
+         * hub or switch with different Flow Control capabilities.
+         */
+        if (hw->mac_type == e1000_82542_rev2_0)
+                hw->fc &= (~E1000_FC_TX_PAUSE);
+
+        if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
+                hw->fc &= (~E1000_FC_RX_PAUSE);
+
+        hw->original_fc = hw->fc;
+
+        DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
+
+        /* Take the 4 bits from EEPROM word 0x0F that determine the initial
+         * polarity value for the SW controlled pins, and setup the
+         * Extended Device Control reg with that info.
+         * This is needed because one of the SW controlled pins is used for
+         * signal detection.  So this should be done before e1000_setup_pcs_link()
+         * or e1000_phy_setup() is called.
+         */
+        if (hw->mac_type == e1000_82543) {
+                ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                            1, &eeprom_data);
+                if (ret_val) {
+                        DEBUGOUT("EEPROM Read Error\n");
+                        return -E1000_ERR_EEPROM;
+                }
+                ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
+                            SWDPIO__EXT_SHIFT);
+                ew32(CTRL_EXT, ctrl_ext);
+        }
+
+        /* Call the necessary subroutine to configure the link. */
+        ret_val = (hw->media_type == e1000_media_type_copper) ?
+            e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
+
+        /* Initialize the flow control address, type, and PAUSE timer
+         * registers to their default values.  This is done even if flow
+         * control is disabled, because it does not hurt anything to
+         * initialize these registers.
+         */
+        DEBUGOUT
+            ("Initializing the Flow Control address, type and timer regs\n");
+
+        ew32(FCT, FLOW_CONTROL_TYPE);
+        ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+        ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
+
+        ew32(FCTTV, hw->fc_pause_time);
+
+        /* Set the flow control receive threshold registers.  Normally,
+         * these registers will be set to a default threshold that may be
+         * adjusted later by the driver's runtime code.  However, if the
+         * ability to transmit pause frames in not enabled, then these
+         * registers will be set to 0.
+         */
+        if (!(hw->fc & E1000_FC_TX_PAUSE)) {
+                ew32(FCRTL, 0);
+                ew32(FCRTH, 0);
+        } else {
+                /* We need to set up the Receive Threshold high and low water marks
+                 * as well as (optionally) enabling the transmission of XON frames.
+                 */
+                if (hw->fc_send_xon) {
+                        ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
+                        ew32(FCRTH, hw->fc_high_water);
+                } else {
+                        ew32(FCRTL, hw->fc_low_water);
+                        ew32(FCRTH, hw->fc_high_water);
+                }
+        }
+        return ret_val;
 }
 
-/******************************************************************************
- * Sets up link for a fiber based or serdes based adapter
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
+ * @hw: Struct containing variables accessed by shared code
  *
  * Manipulates Physical Coding Sublayer functions in order to configure
  * link. Assumes the hardware has been previously reset and the transmitter
  * and receiver are not enabled.
- *****************************************************************************/
+ */
 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u32 status;
-    u32 txcw = 0;
-    u32 i;
-    u32 signal = 0;
-    s32 ret_val;
-
-    DEBUGFUNC("e1000_setup_fiber_serdes_link");
-
-    /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
-     * until explicitly turned off or a power cycle is performed.  A read to
-     * the register does not indicate its status.  Therefore, we ensure
-     * loopback mode is disabled during initialization.
-     */
-    if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
-        ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
-
-    /* On adapters with a MAC newer than 82544, SWDP 1 will be
-     * set when the optics detect a signal. On older adapters, it will be
-     * cleared when there is a signal.  This applies to fiber media only.
-     * If we're on serdes media, adjust the output amplitude to value
-     * set in the EEPROM.
-     */
-    ctrl = er32(CTRL);
-    if (hw->media_type == e1000_media_type_fiber)
-        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-
-    ret_val = e1000_adjust_serdes_amplitude(hw);
-    if (ret_val)
-        return ret_val;
-
-    /* Take the link out of reset */
-    ctrl &= ~(E1000_CTRL_LRST);
-
-    /* Adjust VCO speed to improve BER performance */
-    ret_val = e1000_set_vco_speed(hw);
-    if (ret_val)
-        return ret_val;
-
-    e1000_config_collision_dist(hw);
-
-    /* Check for a software override of the flow control settings, and setup
-     * the device accordingly.  If auto-negotiation is enabled, then software
-     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
-     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
-     * auto-negotiation is disabled, then software will have to manually
-     * configure the two flow control enable bits in the CTRL register.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause frames, but
-     *          not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames but we do
-     *          not support receiving pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) are enabled.
-     */
-    switch (hw->fc) {
-    case E1000_FC_NONE:
-        /* Flow control is completely disabled by a software over-ride. */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
-        break;
-    case E1000_FC_RX_PAUSE:
-        /* RX Flow control is enabled and TX Flow control is disabled by a
-         * software over-ride. Since there really isn't a way to advertise
-         * that we are capable of RX Pause ONLY, we will advertise that we
-         * support both symmetric and asymmetric RX PAUSE. Later, we will
-         *  disable the adapter's ability to send PAUSE frames.
-         */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-        break;
-    case E1000_FC_TX_PAUSE:
-        /* TX Flow control is enabled, and RX Flow control is disabled, by a
-         * software over-ride.
-         */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
-        break;
-    case E1000_FC_FULL:
-        /* Flow control (both RX and TX) is enabled by a software over-ride. */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-        break;
-    }
-
-    /* Since auto-negotiation is enabled, take the link out of reset (the link
-     * will be in reset, because we previously reset the chip). This will
-     * restart auto-negotiation.  If auto-neogtiation is successful then the
-     * link-up status bit will be set and the flow control enable bits (RFCE
-     * and TFCE) will be set according to their negotiated value.
-     */
-    DEBUGOUT("Auto-negotiation enabled\n");
-
-    ew32(TXCW, txcw);
-    ew32(CTRL, ctrl);
-    E1000_WRITE_FLUSH();
-
-    hw->txcw = txcw;
-    msleep(1);
-
-    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
-     * indication in the Device Status Register.  Time-out if a link isn't
-     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
-     * less than 500 milliseconds even if the other end is doing it in SW).
-     * For internal serdes, we just assume a signal is present, then poll.
-     */
-    if (hw->media_type == e1000_media_type_internal_serdes ||
-       (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
-        DEBUGOUT("Looking for Link\n");
-        for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
-            msleep(10);
-            status = er32(STATUS);
-            if (status & E1000_STATUS_LU) break;
-        }
-        if (i == (LINK_UP_TIMEOUT / 10)) {
-            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
-            hw->autoneg_failed = 1;
-            /* AutoNeg failed to achieve a link, so we'll call
-             * e1000_check_for_link. This routine will force the link up if
-             * we detect a signal. This will allow us to communicate with
-             * non-autonegotiating link partners.
-             */
-            ret_val = e1000_check_for_link(hw);
-            if (ret_val) {
-                DEBUGOUT("Error while checking for link\n");
-                return ret_val;
-            }
-            hw->autoneg_failed = 0;
-        } else {
-            hw->autoneg_failed = 0;
-            DEBUGOUT("Valid Link Found\n");
-        }
-    } else {
-        DEBUGOUT("No Signal Detected\n");
-    }
-    return E1000_SUCCESS;
+        u32 ctrl;
+        u32 status;
+        u32 txcw = 0;
+        u32 i;
+        u32 signal = 0;
+        s32 ret_val;
+
+        DEBUGFUNC("e1000_setup_fiber_serdes_link");
+
+        /* On adapters with a MAC newer than 82544, SWDP 1 will be
+         * set when the optics detect a signal. On older adapters, it will be
+         * cleared when there is a signal.  This applies to fiber media only.
+         * If we're on serdes media, adjust the output amplitude to value
+         * set in the EEPROM.
+         */
+        ctrl = er32(CTRL);
+        if (hw->media_type == e1000_media_type_fiber)
+                signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+
+        ret_val = e1000_adjust_serdes_amplitude(hw);
+        if (ret_val)
+                return ret_val;
+
+        /* Take the link out of reset */
+        ctrl &= ~(E1000_CTRL_LRST);
+
+        /* Adjust VCO speed to improve BER performance */
+        ret_val = e1000_set_vco_speed(hw);
+        if (ret_val)
+                return ret_val;
+
+        e1000_config_collision_dist(hw);
+
+        /* Check for a software override of the flow control settings, and setup
+         * the device accordingly.  If auto-negotiation is enabled, then software
+         * will have to set the "PAUSE" bits to the correct value in the Tranmsit
+         * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
+         * auto-negotiation is disabled, then software will have to manually
+         * configure the two flow control enable bits in the CTRL register.
+         *
+         * The possible values of the "fc" parameter are:
+         *      0:  Flow control is completely disabled
+         *      1:  Rx flow control is enabled (we can receive pause frames, but
+         *          not send pause frames).
+         *      2:  Tx flow control is enabled (we can send pause frames but we do
+         *          not support receiving pause frames).
+         *      3:  Both Rx and TX flow control (symmetric) are enabled.
+         */
+        switch (hw->fc) {
+        case E1000_FC_NONE:
+                /* Flow control is completely disabled by a software over-ride. */
+                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
+                break;
+        case E1000_FC_RX_PAUSE:
+                /* RX Flow control is enabled and TX Flow control is disabled by a
+                 * software over-ride. Since there really isn't a way to advertise
+                 * that we are capable of RX Pause ONLY, we will advertise that we
+                 * support both symmetric and asymmetric RX PAUSE. Later, we will
+                 *  disable the adapter's ability to send PAUSE frames.
+                 */
+                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+                break;
+        case E1000_FC_TX_PAUSE:
+                /* TX Flow control is enabled, and RX Flow control is disabled, by a
+                 * software over-ride.
+                 */
+                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+                break;
+        case E1000_FC_FULL:
+                /* Flow control (both RX and TX) is enabled by a software over-ride. */
+                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+                break;
+        default:
+                DEBUGOUT("Flow control param set incorrectly\n");
+                return -E1000_ERR_CONFIG;
+                break;
+        }
+
+        /* Since auto-negotiation is enabled, take the link out of reset (the link
+         * will be in reset, because we previously reset the chip). This will
+         * restart auto-negotiation.  If auto-negotiation is successful then the
+         * link-up status bit will be set and the flow control enable bits (RFCE
+         * and TFCE) will be set according to their negotiated value.
+         */
+        DEBUGOUT("Auto-negotiation enabled\n");
+
+        ew32(TXCW, txcw);
+        ew32(CTRL, ctrl);
+        E1000_WRITE_FLUSH();
+
+        hw->txcw = txcw;
+        msleep(1);
+
+        /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
+         * indication in the Device Status Register.  Time-out if a link isn't
+         * seen in 500 milliseconds seconds (Auto-negotiation should complete in
+         * less than 500 milliseconds even if the other end is doing it in SW).
+         * For internal serdes, we just assume a signal is present, then poll.
+         */
+        if (hw->media_type == e1000_media_type_internal_serdes ||
+            (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+                DEBUGOUT("Looking for Link\n");
+                for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+                        msleep(10);
+                        status = er32(STATUS);
+                        if (status & E1000_STATUS_LU)
+                                break;
+                }
+                if (i == (LINK_UP_TIMEOUT / 10)) {
+                        DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+                        hw->autoneg_failed = 1;
+                        /* AutoNeg failed to achieve a link, so we'll call
+                         * e1000_check_for_link. This routine will force the link up if
+                         * we detect a signal. This will allow us to communicate with
+                         * non-autonegotiating link partners.
+                         */
+                        ret_val = e1000_check_for_link(hw);
+                        if (ret_val) {
+                                DEBUGOUT("Error while checking for link\n");
+                                return ret_val;
+                        }
+                        hw->autoneg_failed = 0;
+                } else {
+                        hw->autoneg_failed = 0;
+                        DEBUGOUT("Valid Link Found\n");
+                }
+        } else {
+                DEBUGOUT("No Signal Detected\n");
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Make sure we have a valid PHY and change PHY mode before link setup.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_copper_link_preconfig - early configuration for copper
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Make sure we have a valid PHY and change PHY mode before link setup.
+ */
 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_preconfig");
-
-    ctrl = er32(CTRL);
-    /* With 82543, we need to force speed and duplex on the MAC equal to what
-     * the PHY speed and duplex configuration is. In addition, we need to
-     * perform a hardware reset on the PHY to take it out of reset.
-     */
-    if (hw->mac_type > e1000_82543) {
-        ctrl |= E1000_CTRL_SLU;
-        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-        ew32(CTRL, ctrl);
-    } else {
-        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
-        ew32(CTRL, ctrl);
-        ret_val = e1000_phy_hw_reset(hw);
-        if (ret_val)
-            return ret_val;
-    }
-
-    /* Make sure we have a valid PHY */
-    ret_val = e1000_detect_gig_phy(hw);
-    if (ret_val) {
-        DEBUGOUT("Error, did not detect valid phy.\n");
-        return ret_val;
-    }
-    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
-
-    /* Set PHY to class A mode (if necessary) */
-    ret_val = e1000_set_phy_mode(hw);
-    if (ret_val)
-        return ret_val;
-
-    if ((hw->mac_type == e1000_82545_rev_3) ||
-       (hw->mac_type == e1000_82546_rev_3)) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        phy_data |= 0x00000008;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-    }
-
-    if (hw->mac_type <= e1000_82543 ||
-        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
-        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
-        hw->phy_reset_disable = false;
-
-   return E1000_SUCCESS;
-}
+        u32 ctrl;
+        s32 ret_val;
+        u16 phy_data;
 
+        DEBUGFUNC("e1000_copper_link_preconfig");
 
-/********************************************************************
-* Copper link setup for e1000_phy_igp series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
-{
-    u32 led_ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_igp_setup");
-
-    if (hw->phy_reset_disable)
-        return E1000_SUCCESS;
-
-    ret_val = e1000_phy_reset(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Resetting the PHY\n");
-        return ret_val;
-    }
-
-    /* Wait 15ms for MAC to configure PHY from eeprom settings */
-    msleep(15);
-    if (hw->mac_type != e1000_ich8lan) {
-    /* Configure activity LED after PHY reset */
-    led_ctrl = er32(LEDCTL);
-    led_ctrl &= IGP_ACTIVITY_LED_MASK;
-    led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-    ew32(LEDCTL, led_ctrl);
-    }
-
-    /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
-    if (hw->phy_type == e1000_phy_igp) {
-        /* disable lplu d3 during driver init */
-        ret_val = e1000_set_d3_lplu_state(hw, false);
-        if (ret_val) {
-            DEBUGOUT("Error Disabling LPLU D3\n");
-            return ret_val;
-        }
-    }
-
-    /* disable lplu d0 during driver init */
-    ret_val = e1000_set_d0_lplu_state(hw, false);
-    if (ret_val) {
-        DEBUGOUT("Error Disabling LPLU D0\n");
-        return ret_val;
-    }
-    /* Configure mdi-mdix settings */
-    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        hw->dsp_config_state = e1000_dsp_config_disabled;
-        /* Force MDI for earlier revs of the IGP PHY */
-        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
-        hw->mdix = 1;
-
-    } else {
-        hw->dsp_config_state = e1000_dsp_config_enabled;
-        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-
-        switch (hw->mdix) {
-        case 1:
-            phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
-            break;
-        case 2:
-            phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
-            break;
-        case 0:
-        default:
-            phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
-            break;
-        }
-    }
-    ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    /* set auto-master slave resolution settings */
-    if (hw->autoneg) {
-        e1000_ms_type phy_ms_setting = hw->master_slave;
-
-        if (hw->ffe_config_state == e1000_ffe_config_active)
-            hw->ffe_config_state = e1000_ffe_config_enabled;
-
-        if (hw->dsp_config_state == e1000_dsp_config_activated)
-            hw->dsp_config_state = e1000_dsp_config_enabled;
-
-        /* when autonegotiation advertisment is only 1000Mbps then we
-          * should disable SmartSpeed and enable Auto MasterSlave
-          * resolution as hardware default. */
-        if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
-            /* Disable SmartSpeed */
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-            /* Set auto Master/Slave resolution process */
-            ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-            if (ret_val)
-                return ret_val;
-            phy_data &= ~CR_1000T_MS_ENABLE;
-            ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* load defaults for future use */
-        hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
-                                        ((phy_data & CR_1000T_MS_VALUE) ?
-                                         e1000_ms_force_master :
-                                         e1000_ms_force_slave) :
-                                         e1000_ms_auto;
-
-        switch (phy_ms_setting) {
-        case e1000_ms_force_master:
-            phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
-            break;
-        case e1000_ms_force_slave:
-            phy_data |= CR_1000T_MS_ENABLE;
-            phy_data &= ~(CR_1000T_MS_VALUE);
-            break;
-        case e1000_ms_auto:
-            phy_data &= ~CR_1000T_MS_ENABLE;
-            default:
-            break;
-        }
-        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+        ctrl = er32(CTRL);
+        /* With 82543, we need to force speed and duplex on the MAC equal to what
+         * the PHY speed and duplex configuration is. In addition, we need to
+         * perform a hardware reset on the PHY to take it out of reset.
+         */
+        if (hw->mac_type > e1000_82543) {
+                ctrl |= E1000_CTRL_SLU;
+                ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+                ew32(CTRL, ctrl);
+        } else {
+                ctrl |=
+                    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+                ew32(CTRL, ctrl);
+                ret_val = e1000_phy_hw_reset(hw);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        /* Make sure we have a valid PHY */
+        ret_val = e1000_detect_gig_phy(hw);
+        if (ret_val) {
+                DEBUGOUT("Error, did not detect valid phy.\n");
+                return ret_val;
+        }
+        DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+
+        /* Set PHY to class A mode (if necessary) */
+        ret_val = e1000_set_phy_mode(hw);
+        if (ret_val)
+                return ret_val;
+
+        if ((hw->mac_type == e1000_82545_rev_3) ||
+            (hw->mac_type == e1000_82546_rev_3)) {
+                ret_val =
+                    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+                phy_data |= 0x00000008;
+                ret_val =
+                    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+        }
+
+        if (hw->mac_type <= e1000_82543 ||
+            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
+            hw->mac_type == e1000_82541_rev_2
+            || hw->mac_type == e1000_82547_rev_2)
+                hw->phy_reset_disable = false;
+
+        return E1000_SUCCESS;
 }
 
-/********************************************************************
-* Copper link setup for e1000_phy_gg82563 series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
+/**
+ * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
+ * @hw: Struct containing variables accessed by shared code
+ */
+static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-    u32 reg_data;
-
-    DEBUGFUNC("e1000_copper_link_ggp_setup");
-
-    if (!hw->phy_reset_disable) {
-
-        /* Enable CRS on TX for half-duplex operation. */
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
-        /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
-        phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
-
-        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-                                      phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* Options:
-         *   MDI/MDI-X = 0 (default)
-         *   0 - Auto for all speeds
-         *   1 - MDI mode
-         *   2 - MDI-X mode
-         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
-         */
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
-
-        switch (hw->mdix) {
-        case 1:
-            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
-            break;
-        case 2:
-            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
-            break;
-        case 0:
-        default:
-            phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
-            break;
-        }
-
-        /* Options:
-         *   disable_polarity_correction = 0 (default)
-         *       Automatic Correction for Reversed Cable Polarity
-         *   0 - Disabled
-         *   1 - Enabled
-         */
-        phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
-        if (hw->disable_polarity_correction == 1)
-            phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
-        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
-
-        if (ret_val)
-            return ret_val;
-
-        /* SW Reset the PHY so all changes take effect */
-        ret_val = e1000_phy_reset(hw);
-        if (ret_val) {
-            DEBUGOUT("Error Resetting the PHY\n");
-            return ret_val;
-        }
-    } /* phy_reset_disable */
-
-    if (hw->mac_type == e1000_80003es2lan) {
-        /* Bypass RX and TX FIFO's */
-        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
-                                       E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
-                                       E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
-        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
-
-        if (ret_val)
-            return ret_val;
-
-        reg_data = er32(CTRL_EXT);
-        reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
-        ew32(CTRL_EXT, reg_data);
-
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
-                                          &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* Do not init these registers when the HW is in IAMT mode, since the
-         * firmware will have already initialized them.  We only initialize
-         * them if the HW is not in IAMT mode.
-         */
-        if (!e1000_check_mng_mode(hw)) {
-            /* Enable Electrical Idle on the PHY */
-            phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
-            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-                                          phy_data);
-
-            if (ret_val)
-                return ret_val;
-        }
-
-        /* Workaround: Disable padding in Kumeran interface in the MAC
-         * and in the PHY to avoid CRC errors.
-         */
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        phy_data |= GG82563_ICR_DIS_PADDING;
-        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
-                                      phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+        u32 led_ctrl;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_copper_link_igp_setup");
+
+        if (hw->phy_reset_disable)
+                return E1000_SUCCESS;
+
+        ret_val = e1000_phy_reset(hw);
+        if (ret_val) {
+                DEBUGOUT("Error Resetting the PHY\n");
+                return ret_val;
+        }
+
+        /* Wait 15ms for MAC to configure PHY from eeprom settings */
+        msleep(15);
+        /* Configure activity LED after PHY reset */
+        led_ctrl = er32(LEDCTL);
+        led_ctrl &= IGP_ACTIVITY_LED_MASK;
+        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+        ew32(LEDCTL, led_ctrl);
+
+        /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
+        if (hw->phy_type == e1000_phy_igp) {
+                /* disable lplu d3 during driver init */
+                ret_val = e1000_set_d3_lplu_state(hw, false);
+                if (ret_val) {
+                        DEBUGOUT("Error Disabling LPLU D3\n");
+                        return ret_val;
+                }
+        }
+
+        /* Configure mdi-mdix settings */
+        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+                hw->dsp_config_state = e1000_dsp_config_disabled;
+                /* Force MDI for earlier revs of the IGP PHY */
+                phy_data &=
+                    ~(IGP01E1000_PSCR_AUTO_MDIX |
+                      IGP01E1000_PSCR_FORCE_MDI_MDIX);
+                hw->mdix = 1;
+
+        } else {
+                hw->dsp_config_state = e1000_dsp_config_enabled;
+                phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+
+                switch (hw->mdix) {
+                case 1:
+                        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+                        break;
+                case 2:
+                        phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
+                        break;
+                case 0:
+                default:
+                        phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
+                        break;
+                }
+        }
+        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+        if (ret_val)
+                return ret_val;
+
+        /* set auto-master slave resolution settings */
+        if (hw->autoneg) {
+                e1000_ms_type phy_ms_setting = hw->master_slave;
+
+                if (hw->ffe_config_state == e1000_ffe_config_active)
+                        hw->ffe_config_state = e1000_ffe_config_enabled;
+
+                if (hw->dsp_config_state == e1000_dsp_config_activated)
+                        hw->dsp_config_state = e1000_dsp_config_enabled;
+
+                /* when autonegotiation advertisement is only 1000Mbps then we
+                 * should disable SmartSpeed and enable Auto MasterSlave
+                 * resolution as hardware default. */
+                if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+                        /* Disable SmartSpeed */
+                        ret_val =
+                            e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               &phy_data);
+                        if (ret_val)
+                                return ret_val;
+                        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                                phy_data);
+                        if (ret_val)
+                                return ret_val;
+                        /* Set auto Master/Slave resolution process */
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+                        if (ret_val)
+                                return ret_val;
+                        phy_data &= ~CR_1000T_MS_ENABLE;
+                        ret_val =
+                            e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+                        if (ret_val)
+                                return ret_val;
+                }
+
+                ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                /* load defaults for future use */
+                hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
+                    ((phy_data & CR_1000T_MS_VALUE) ?
+                     e1000_ms_force_master :
+                     e1000_ms_force_slave) : e1000_ms_auto;
+
+                switch (phy_ms_setting) {
+                case e1000_ms_force_master:
+                        phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+                        break;
+                case e1000_ms_force_slave:
+                        phy_data |= CR_1000T_MS_ENABLE;
+                        phy_data &= ~(CR_1000T_MS_VALUE);
+                        break;
+                case e1000_ms_auto:
+                        phy_data &= ~CR_1000T_MS_ENABLE;
+                default:
+                        break;
+                }
+                ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/********************************************************************
-* Copper link setup for e1000_phy_m88 series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
+/**
+ * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_mgp_setup");
-
-    if (hw->phy_reset_disable)
-        return E1000_SUCCESS;
-
-    /* Enable CRS on TX. This must be set for half-duplex operation. */
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-
-    /* Options:
-     *   MDI/MDI-X = 0 (default)
-     *   0 - Auto for all speeds
-     *   1 - MDI mode
-     *   2 - MDI-X mode
-     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
-     */
-    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-
-    switch (hw->mdix) {
-    case 1:
-        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
-        break;
-    case 2:
-        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
-        break;
-    case 3:
-        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
-        break;
-    case 0:
-    default:
-        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
-        break;
-    }
-
-    /* Options:
-     *   disable_polarity_correction = 0 (default)
-     *       Automatic Correction for Reversed Cable Polarity
-     *   0 - Disabled
-     *   1 - Enabled
-     */
-    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-    if (hw->disable_polarity_correction == 1)
-        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if (hw->phy_revision < M88E1011_I_REV_4) {
-        /* Force TX_CLK in the Extended PHY Specific Control Register
-         * to 25MHz clock.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_EPSCR_TX_CLK_25;
-
-        if ((hw->phy_revision == E1000_REVISION_2) &&
-            (hw->phy_id == M88E1111_I_PHY_ID)) {
-            /* Vidalia Phy, set the downshift counter to 5x */
-            phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
-            phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
-            ret_val = e1000_write_phy_reg(hw,
-                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            /* Configure Master and Slave downshift values */
-            phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
-            phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
-            ret_val = e1000_write_phy_reg(hw,
-                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-            if (ret_val)
-               return ret_val;
-        }
-    }
-
-    /* SW Reset the PHY so all changes take effect */
-    ret_val = e1000_phy_reset(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Resetting the PHY\n");
-        return ret_val;
-    }
-
-   return E1000_SUCCESS;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_copper_link_mgp_setup");
+
+        if (hw->phy_reset_disable)
+                return E1000_SUCCESS;
+
+        /* Enable CRS on TX. This must be set for half-duplex operation. */
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+
+        /* Options:
+         *   MDI/MDI-X = 0 (default)
+         *   0 - Auto for all speeds
+         *   1 - MDI mode
+         *   2 - MDI-X mode
+         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+         */
+        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+
+        switch (hw->mdix) {
+        case 1:
+                phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
+                break;
+        case 2:
+                phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
+                break;
+        case 3:
+                phy_data |= M88E1000_PSCR_AUTO_X_1000T;
+                break;
+        case 0:
+        default:
+                phy_data |= M88E1000_PSCR_AUTO_X_MODE;
+                break;
+        }
+
+        /* Options:
+         *   disable_polarity_correction = 0 (default)
+         *       Automatic Correction for Reversed Cable Polarity
+         *   0 - Disabled
+         *   1 - Enabled
+         */
+        phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
+        if (hw->disable_polarity_correction == 1)
+                phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+        if (ret_val)
+                return ret_val;
+
+        if (hw->phy_revision < M88E1011_I_REV_4) {
+                /* Force TX_CLK in the Extended PHY Specific Control Register
+                 * to 25MHz clock.
+                 */
+                ret_val =
+                    e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                       &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_data |= M88E1000_EPSCR_TX_CLK_25;
+
+                if ((hw->phy_revision == E1000_REVISION_2) &&
+                    (hw->phy_id == M88E1111_I_PHY_ID)) {
+                        /* Vidalia Phy, set the downshift counter to 5x */
+                        phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
+                        phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
+                        ret_val = e1000_write_phy_reg(hw,
+                                                      M88E1000_EXT_PHY_SPEC_CTRL,
+                                                      phy_data);
+                        if (ret_val)
+                                return ret_val;
+                } else {
+                        /* Configure Master and Slave downshift values */
+                        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
+                                      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+                        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
+                                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+                        ret_val = e1000_write_phy_reg(hw,
+                                                      M88E1000_EXT_PHY_SPEC_CTRL,
+                                                      phy_data);
+                        if (ret_val)
+                                return ret_val;
+                }
+        }
+
+        /* SW Reset the PHY so all changes take effect */
+        ret_val = e1000_phy_reset(hw);
+        if (ret_val) {
+                DEBUGOUT("Error Resetting the PHY\n");
+                return ret_val;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/********************************************************************
-* Setup auto-negotiation and flow control advertisements,
-* and then perform auto-negotiation.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
+/**
+ * e1000_copper_link_autoneg - setup auto-neg
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Setup auto-negotiation and flow control advertisements,
+ * and then perform auto-negotiation.
+ */
 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_autoneg");
-
-    /* Perform some bounds checking on the hw->autoneg_advertised
-     * parameter.  If this variable is zero, then set it to the default.
-     */
-    hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-    /* If autoneg_advertised is zero, we assume it was not defaulted
-     * by the calling code so we set to advertise full capability.
-     */
-    if (hw->autoneg_advertised == 0)
-        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-    /* IFE phy only supports 10/100 */
-    if (hw->phy_type == e1000_phy_ife)
-        hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
-
-    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
-    ret_val = e1000_phy_setup_autoneg(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Setting up Auto-Negotiation\n");
-        return ret_val;
-    }
-    DEBUGOUT("Restarting Auto-Neg\n");
-
-    /* Restart auto-negotiation by setting the Auto Neg Enable bit and
-     * the Auto Neg Restart bit in the PHY control register.
-     */
-    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
-    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    /* Does the user want to wait for Auto-Neg to complete here, or
-     * check at a later time (for example, callback routine).
-     */
-    if (hw->wait_autoneg_complete) {
-        ret_val = e1000_wait_autoneg(hw);
-        if (ret_val) {
-            DEBUGOUT("Error while waiting for autoneg to complete\n");
-            return ret_val;
-        }
-    }
-
-    hw->get_link_status = true;
-
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_copper_link_autoneg");
+
+        /* Perform some bounds checking on the hw->autoneg_advertised
+         * parameter.  If this variable is zero, then set it to the default.
+         */
+        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+        /* If autoneg_advertised is zero, we assume it was not defaulted
+         * by the calling code so we set to advertise full capability.
+         */
+        if (hw->autoneg_advertised == 0)
+                hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
+        ret_val = e1000_phy_setup_autoneg(hw);
+        if (ret_val) {
+                DEBUGOUT("Error Setting up Auto-Negotiation\n");
+                return ret_val;
+        }
+        DEBUGOUT("Restarting Auto-Neg\n");
+
+        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+         * the Auto Neg Restart bit in the PHY control register.
+         */
+        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+        if (ret_val)
+                return ret_val;
+
+        /* Does the user want to wait for Auto-Neg to complete here, or
+         * check at a later time (for example, callback routine).
+         */
+        if (hw->wait_autoneg_complete) {
+                ret_val = e1000_wait_autoneg(hw);
+                if (ret_val) {
+                        DEBUGOUT
+                            ("Error while waiting for autoneg to complete\n");
+                        return ret_val;
+                }
+        }
+
+        hw->get_link_status = true;
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Config the MAC and the PHY after link is up.
-*   1) Set up the MAC to the current PHY speed/duplex
-*      if we are on 82543.  If we
-*      are on newer silicon, we only need to configure
-*      collision distance in the Transmit Control Register.
-*   2) Set up flow control on the MAC to that established with
-*      the link partner.
-*   3) Config DSP to improve Gigabit link quality for some PHY revisions.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_copper_link_postconfig - post link setup
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Config the MAC and the PHY after link is up.
+ *   1) Set up the MAC to the current PHY speed/duplex
+ *      if we are on 82543.  If we
+ *      are on newer silicon, we only need to configure
+ *      collision distance in the Transmit Control Register.
+ *   2) Set up flow control on the MAC to that established with
+ *      the link partner.
+ *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
+ */
 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    DEBUGFUNC("e1000_copper_link_postconfig");
-
-    if (hw->mac_type >= e1000_82544) {
-        e1000_config_collision_dist(hw);
-    } else {
-        ret_val = e1000_config_mac_to_phy(hw);
-        if (ret_val) {
-            DEBUGOUT("Error configuring MAC to PHY settings\n");
-            return ret_val;
-        }
-    }
-    ret_val = e1000_config_fc_after_link_up(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Configuring Flow Control\n");
-        return ret_val;
-    }
-
-    /* Config DSP to improve Giga link quality */
-    if (hw->phy_type == e1000_phy_igp) {
-        ret_val = e1000_config_dsp_after_link_change(hw, true);
-        if (ret_val) {
-            DEBUGOUT("Error Configuring DSP after link up\n");
-            return ret_val;
-        }
-    }
-
-    return E1000_SUCCESS;
+        s32 ret_val;
+        DEBUGFUNC("e1000_copper_link_postconfig");
+
+        if (hw->mac_type >= e1000_82544) {
+                e1000_config_collision_dist(hw);
+        } else {
+                ret_val = e1000_config_mac_to_phy(hw);
+                if (ret_val) {
+                        DEBUGOUT("Error configuring MAC to PHY settings\n");
+                        return ret_val;
+                }
+        }
+        ret_val = e1000_config_fc_after_link_up(hw);
+        if (ret_val) {
+                DEBUGOUT("Error Configuring Flow Control\n");
+                return ret_val;
+        }
+
+        /* Config DSP to improve Giga link quality */
+        if (hw->phy_type == e1000_phy_igp) {
+                ret_val = e1000_config_dsp_after_link_change(hw, true);
+                if (ret_val) {
+                        DEBUGOUT("Error Configuring DSP after link up\n");
+                        return ret_val;
+                }
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Detects which PHY is present and setup the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_setup_copper_link - phy/speed/duplex setting
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Detects which PHY is present and sets up the speed and duplex
+ */
 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 i;
-    u16 phy_data;
-    u16 reg_data = 0;
-
-    DEBUGFUNC("e1000_setup_copper_link");
-
-    switch (hw->mac_type) {
-    case e1000_80003es2lan:
-    case e1000_ich8lan:
-        /* Set the mac to wait the maximum time between each
-         * iteration and increase the max iterations when
-         * polling the phy; this fixes erroneous timeouts at 10Mbps. */
-        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
-        if (ret_val)
-            return ret_val;
-        reg_data |= 0x3F;
-        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
-        if (ret_val)
-            return ret_val;
-    default:
-        break;
-    }
-
-    /* Check if it is a valid PHY and set PHY mode if necessary. */
-    ret_val = e1000_copper_link_preconfig(hw);
-    if (ret_val)
-        return ret_val;
-
-    switch (hw->mac_type) {
-    case e1000_80003es2lan:
-        /* Kumeran registers are written-only */
-        reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
-        reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
-        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
-                                       reg_data);
-        if (ret_val)
-            return ret_val;
-        break;
-    default:
-        break;
-    }
-
-    if (hw->phy_type == e1000_phy_igp ||
-        hw->phy_type == e1000_phy_igp_3 ||
-        hw->phy_type == e1000_phy_igp_2) {
-        ret_val = e1000_copper_link_igp_setup(hw);
-        if (ret_val)
-            return ret_val;
-    } else if (hw->phy_type == e1000_phy_m88) {
-        ret_val = e1000_copper_link_mgp_setup(hw);
-        if (ret_val)
-            return ret_val;
-    } else if (hw->phy_type == e1000_phy_gg82563) {
-        ret_val = e1000_copper_link_ggp_setup(hw);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if (hw->autoneg) {
-        /* Setup autoneg and flow control advertisement
-          * and perform autonegotiation */
-        ret_val = e1000_copper_link_autoneg(hw);
-        if (ret_val)
-            return ret_val;
-    } else {
-        /* PHY will be set to 10H, 10F, 100H,or 100F
-          * depending on value from forced_speed_duplex. */
-        DEBUGOUT("Forcing speed and duplex\n");
-        ret_val = e1000_phy_force_speed_duplex(hw);
-        if (ret_val) {
-            DEBUGOUT("Error Forcing Speed and Duplex\n");
-            return ret_val;
-        }
-    }
-
-    /* Check link status. Wait up to 100 microseconds for link to become
-     * valid.
-     */
-    for (i = 0; i < 10; i++) {
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (phy_data & MII_SR_LINK_STATUS) {
-            /* Config the MAC and PHY after link is up */
-            ret_val = e1000_copper_link_postconfig(hw);
-            if (ret_val)
-                return ret_val;
-
-            DEBUGOUT("Valid link established!!!\n");
-            return E1000_SUCCESS;
-        }
-        udelay(10);
-    }
-
-    DEBUGOUT("Unable to establish link!!!\n");
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 i;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_setup_copper_link");
+
+        /* Check if it is a valid PHY and set PHY mode if necessary. */
+        ret_val = e1000_copper_link_preconfig(hw);
+        if (ret_val)
+                return ret_val;
+
+        if (hw->phy_type == e1000_phy_igp) {
+                ret_val = e1000_copper_link_igp_setup(hw);
+                if (ret_val)
+                        return ret_val;
+        } else if (hw->phy_type == e1000_phy_m88) {
+                ret_val = e1000_copper_link_mgp_setup(hw);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        if (hw->autoneg) {
+                /* Setup autoneg and flow control advertisement
+                 * and perform autonegotiation */
+                ret_val = e1000_copper_link_autoneg(hw);
+                if (ret_val)
+                        return ret_val;
+        } else {
+                /* PHY will be set to 10H, 10F, 100H,or 100F
+                 * depending on value from forced_speed_duplex. */
+                DEBUGOUT("Forcing speed and duplex\n");
+                ret_val = e1000_phy_force_speed_duplex(hw);
+                if (ret_val) {
+                        DEBUGOUT("Error Forcing Speed and Duplex\n");
+                        return ret_val;
+                }
+        }
+
+        /* Check link status. Wait up to 100 microseconds for link to become
+         * valid.
+         */
+        for (i = 0; i < 10; i++) {
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if (phy_data & MII_SR_LINK_STATUS) {
+                        /* Config the MAC and PHY after link is up */
+                        ret_val = e1000_copper_link_postconfig(hw);
+                        if (ret_val)
+                                return ret_val;
+
+                        DEBUGOUT("Valid link established!!!\n");
+                        return E1000_SUCCESS;
+                }
+                udelay(10);
+        }
+
+        DEBUGOUT("Unable to establish link!!!\n");
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Configure the MAC-to-PHY interface for 10/100Mbps
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
+/**
+ * e1000_phy_setup_autoneg - phy settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Configures PHY autoneg and flow control advertisement settings
+ */
+s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 {
-    s32 ret_val = E1000_SUCCESS;
-    u32 tipg;
-    u16 reg_data;
+        s32 ret_val;
+        u16 mii_autoneg_adv_reg;
+        u16 mii_1000t_ctrl_reg;
 
-    DEBUGFUNC("e1000_configure_kmrn_for_10_100");
+        DEBUGFUNC("e1000_phy_setup_autoneg");
 
-    reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
-    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
-                                   reg_data);
-    if (ret_val)
-        return ret_val;
+        /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+        if (ret_val)
+                return ret_val;
 
-    /* Configure Transmit Inter-Packet Gap */
-    tipg = er32(TIPG);
-    tipg &= ~E1000_TIPG_IPGT_MASK;
-    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
-    ew32(TIPG, tipg);
+        /* Read the MII 1000Base-T Control Register (Address 9). */
+        ret_val =
+            e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+        if (ret_val)
+                return ret_val;
 
-    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+        /* Need to parse both autoneg_advertised and fc and set up
+         * the appropriate PHY registers.  First we will parse for
+         * autoneg_advertised software override.  Since we can advertise
+         * a plethora of combinations, we need to check each bit
+         * individually.
+         */
 
-    if (ret_val)
-        return ret_val;
+        /* First we clear all the 10/100 mb speed bits in the Auto-Neg
+         * Advertisement Register (Address 4) and the 1000 mb speed bits in
+         * the  1000Base-T Control Register (Address 9).
+         */
+        mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
+        mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
 
-    if (duplex == HALF_DUPLEX)
-        reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
-    else
-        reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
+        DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
 
-    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+        /* Do we want to advertise 10 Mb Half Duplex? */
+        if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
+                DEBUGOUT("Advertise 10mb Half duplex\n");
+                mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
+        }
 
-    return ret_val;
-}
+        /* Do we want to advertise 10 Mb Full Duplex? */
+        if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
+                DEBUGOUT("Advertise 10mb Full duplex\n");
+                mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
+        }
 
-static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
-{
-    s32 ret_val = E1000_SUCCESS;
-    u16 reg_data;
-    u32 tipg;
+        /* Do we want to advertise 100 Mb Half Duplex? */
+        if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
+                DEBUGOUT("Advertise 100mb Half duplex\n");
+                mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
+        }
 
-    DEBUGFUNC("e1000_configure_kmrn_for_1000");
+        /* Do we want to advertise 100 Mb Full Duplex? */
+        if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
+                DEBUGOUT("Advertise 100mb Full duplex\n");
+                mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
+        }
 
-    reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
-    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
-                                   reg_data);
-    if (ret_val)
-        return ret_val;
+        /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
+        if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
+                DEBUGOUT
+                    ("Advertise 1000mb Half duplex requested, request denied!\n");
+        }
 
-    /* Configure Transmit Inter-Packet Gap */
-    tipg = er32(TIPG);
-    tipg &= ~E1000_TIPG_IPGT_MASK;
-    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
-    ew32(TIPG, tipg);
+        /* Do we want to advertise 1000 Mb Full Duplex? */
+        if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
+                DEBUGOUT("Advertise 1000mb Full duplex\n");
+                mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
+        }
 
-    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
+        /* Check for a software override of the flow control settings, and
+         * setup the PHY advertisement registers accordingly.  If
+         * auto-negotiation is enabled, then software will have to set the
+         * "PAUSE" bits to the correct value in the Auto-Negotiation
+         * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
+         *
+         * The possible values of the "fc" parameter are:
+         *      0:  Flow control is completely disabled
+         *      1:  Rx flow control is enabled (we can receive pause frames
+         *          but not send pause frames).
+         *      2:  Tx flow control is enabled (we can send pause frames
+         *          but we do not support receiving pause frames).
+         *      3:  Both Rx and TX flow control (symmetric) are enabled.
+         *  other:  No software override.  The flow control configuration
+         *          in the EEPROM is used.
+         */
+        switch (hw->fc) {
+        case E1000_FC_NONE:     /* 0 */
+                /* Flow control (RX & TX) is completely disabled by a
+                 * software over-ride.
+                 */
+                mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+                break;
+        case E1000_FC_RX_PAUSE: /* 1 */
+                /* RX Flow control is enabled, and TX Flow control is
+                 * disabled, by a software over-ride.
+                 */
+                /* Since there really isn't a way to advertise that we are
+                 * capable of RX Pause ONLY, we will advertise that we
+                 * support both symmetric and asymmetric RX PAUSE.  Later
+                 * (in e1000_config_fc_after_link_up) we will disable the
+                 *hw's ability to send PAUSE frames.
+                 */
+                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+                break;
+        case E1000_FC_TX_PAUSE: /* 2 */
+                /* TX Flow control is enabled, and RX Flow control is
+                 * disabled, by a software over-ride.
+                 */
+                mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
+                mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
+                break;
+        case E1000_FC_FULL:     /* 3 */
+                /* Flow control (both RX and TX) is enabled by a software
+                 * over-ride.
+                 */
+                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+                break;
+        default:
+                DEBUGOUT("Flow control param set incorrectly\n");
+                return -E1000_ERR_CONFIG;
+        }
 
-    if (ret_val)
-        return ret_val;
+        ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+        if (ret_val)
+                return ret_val;
 
-    reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+        DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
-    return ret_val;
-}
+        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
+        if (ret_val)
+                return ret_val;
 
-/******************************************************************************
-* Configures PHY autoneg and flow control advertisement settings
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 mii_autoneg_adv_reg;
-    u16 mii_1000t_ctrl_reg;
-
-    DEBUGFUNC("e1000_phy_setup_autoneg");
-
-    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
-    ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
-    if (ret_val)
-        return ret_val;
-
-    if (hw->phy_type != e1000_phy_ife) {
-        /* Read the MII 1000Base-T Control Register (Address 9). */
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
-        if (ret_val)
-            return ret_val;
-    } else
-        mii_1000t_ctrl_reg=0;
-
-    /* Need to parse both autoneg_advertised and fc and set up
-     * the appropriate PHY registers.  First we will parse for
-     * autoneg_advertised software override.  Since we can advertise
-     * a plethora of combinations, we need to check each bit
-     * individually.
-     */
-
-    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
-     * Advertisement Register (Address 4) and the 1000 mb speed bits in
-     * the  1000Base-T Control Register (Address 9).
-     */
-    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
-    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
-
-    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
-
-    /* Do we want to advertise 10 Mb Half Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
-        DEBUGOUT("Advertise 10mb Half duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
-    }
-
-    /* Do we want to advertise 10 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
-        DEBUGOUT("Advertise 10mb Full duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
-    }
-
-    /* Do we want to advertise 100 Mb Half Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
-        DEBUGOUT("Advertise 100mb Half duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
-    }
-
-    /* Do we want to advertise 100 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
-        DEBUGOUT("Advertise 100mb Full duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
-    }
-
-    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
-    if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
-        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
-    }
-
-    /* Do we want to advertise 1000 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
-        DEBUGOUT("Advertise 1000mb Full duplex\n");
-        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
-        if (hw->phy_type == e1000_phy_ife) {
-            DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
-        }
-    }
-
-    /* Check for a software override of the flow control settings, and
-     * setup the PHY advertisement registers accordingly.  If
-     * auto-negotiation is enabled, then software will have to set the
-     * "PAUSE" bits to the correct value in the Auto-Negotiation
-     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause frames
-     *          but not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames
-     *          but we do not support receiving pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) are enabled.
-     *  other:  No software override.  The flow control configuration
-     *          in the EEPROM is used.
-     */
-    switch (hw->fc) {
-    case E1000_FC_NONE: /* 0 */
-        /* Flow control (RX & TX) is completely disabled by a
-         * software over-ride.
-         */
-        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    case E1000_FC_RX_PAUSE: /* 1 */
-        /* RX Flow control is enabled, and TX Flow control is
-         * disabled, by a software over-ride.
-         */
-        /* Since there really isn't a way to advertise that we are
-         * capable of RX Pause ONLY, we will advertise that we
-         * support both symmetric and asymmetric RX PAUSE.  Later
-         * (in e1000_config_fc_after_link_up) we will disable the
-         *hw's ability to send PAUSE frames.
-         */
-        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    case E1000_FC_TX_PAUSE: /* 2 */
-        /* TX Flow control is enabled, and RX Flow control is
-         * disabled, by a software over-ride.
-         */
-        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
-        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
-        break;
-    case E1000_FC_FULL: /* 3 */
-        /* Flow control (both RX and TX) is enabled by a software
-         * over-ride.
-         */
-        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
-    if (ret_val)
-        return ret_val;
-
-    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
-
-    if (hw->phy_type != e1000_phy_ife) {
-        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Force PHY speed and duplex settings to hw->forced_speed_duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_phy_force_speed_duplex - force link settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Force PHY speed and duplex settings to hw->forced_speed_duplex
+ */
 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    s32 ret_val;
-    u16 mii_ctrl_reg;
-    u16 mii_status_reg;
-    u16 phy_data;
-    u16 i;
-
-    DEBUGFUNC("e1000_phy_force_speed_duplex");
-
-    /* Turn off Flow control if we are forcing speed and duplex. */
-    hw->fc = E1000_FC_NONE;
-
-    DEBUGOUT1("hw->fc = %d\n", hw->fc);
-
-    /* Read the Device Control Register. */
-    ctrl = er32(CTRL);
-
-    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
-    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-    ctrl &= ~(DEVICE_SPEED_MASK);
-
-    /* Clear the Auto Speed Detect Enable bit. */
-    ctrl &= ~E1000_CTRL_ASDE;
-
-    /* Read the MII Control Register. */
-    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    /* We need to disable autoneg in order to force link and duplex. */
-
-    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
-
-    /* Are we forcing Full or Half Duplex? */
-    if (hw->forced_speed_duplex == e1000_100_full ||
-        hw->forced_speed_duplex == e1000_10_full) {
-        /* We want to force full duplex so we SET the full duplex bits in the
-         * Device and MII Control Registers.
-         */
-        ctrl |= E1000_CTRL_FD;
-        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
-        DEBUGOUT("Full Duplex\n");
-    } else {
-        /* We want to force half duplex so we CLEAR the full duplex bits in
-         * the Device and MII Control Registers.
-         */
-        ctrl &= ~E1000_CTRL_FD;
-        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
-        DEBUGOUT("Half Duplex\n");
-    }
-
-    /* Are we forcing 100Mbps??? */
-    if (hw->forced_speed_duplex == e1000_100_full ||
-       hw->forced_speed_duplex == e1000_100_half) {
-        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
-        ctrl |= E1000_CTRL_SPD_100;
-        mii_ctrl_reg |= MII_CR_SPEED_100;
-        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
-        DEBUGOUT("Forcing 100mb ");
-    } else {
-        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
-        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
-        mii_ctrl_reg |= MII_CR_SPEED_10;
-        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
-        DEBUGOUT("Forcing 10mb ");
-    }
-
-    e1000_config_collision_dist(hw);
-
-    /* Write the configured values back to the Device Control Reg. */
-    ew32(CTRL, ctrl);
-
-    if ((hw->phy_type == e1000_phy_m88) ||
-        (hw->phy_type == e1000_phy_gg82563)) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
-         * forced whenever speed are duplex are forced.
-         */
-        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
-
-        /* Need to reset the PHY or these changes will be ignored */
-        mii_ctrl_reg |= MII_CR_RESET;
-
-    /* Disable MDI-X support for 10/100 */
-    } else if (hw->phy_type == e1000_phy_ife) {
-        ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IFE_PMC_AUTO_MDIX;
-        phy_data &= ~IFE_PMC_FORCE_MDIX;
-
-        ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-    } else {
-        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
-         * forced whenever speed or duplex are forced.
-         */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
-
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    /* Write back the modified PHY MII control register. */
-    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    udelay(1);
-
-    /* The wait_autoneg_complete flag may be a little misleading here.
-     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
-     * But we do want to delay for a period while forcing only so we
-     * don't generate false No Link messages.  So we will wait here
-     * only if the user has set wait_autoneg_complete to 1, which is
-     * the default.
-     */
-    if (hw->wait_autoneg_complete) {
-        /* We will wait for autoneg to complete. */
-        DEBUGOUT("Waiting for forced speed/duplex link.\n");
-        mii_status_reg = 0;
-
-        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-        for (i = PHY_FORCE_TIME; i > 0; i--) {
-            /* Read the MII Status Register and wait for Auto-Neg Complete bit
-             * to be set.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            if (mii_status_reg & MII_SR_LINK_STATUS) break;
-            msleep(100);
-        }
-        if ((i == 0) &&
-           ((hw->phy_type == e1000_phy_m88) ||
-            (hw->phy_type == e1000_phy_gg82563))) {
-            /* We didn't get link.  Reset the DSP and wait again for link. */
-            ret_val = e1000_phy_reset_dsp(hw);
-            if (ret_val) {
-                DEBUGOUT("Error Resetting PHY DSP\n");
-                return ret_val;
-            }
-        }
-        /* This loop will early-out if the link condition has been met.  */
-        for (i = PHY_FORCE_TIME; i > 0; i--) {
-            if (mii_status_reg & MII_SR_LINK_STATUS) break;
-            msleep(100);
-            /* Read the MII Status Register and wait for Auto-Neg Complete bit
-             * to be set.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-        }
-    }
-
-    if (hw->phy_type == e1000_phy_m88) {
-        /* Because we reset the PHY above, we need to re-force TX_CLK in the
-         * Extended PHY Specific Control Register to 25MHz clock.  This value
-         * defaults back to a 2.5MHz clock when the PHY is reset.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_EPSCR_TX_CLK_25;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* In addition, because of the s/w reset above, we need to enable CRS on
-         * TX.  This must be set for both full and half duplex operation.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-            (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
-             hw->forced_speed_duplex == e1000_10_half)) {
-            ret_val = e1000_polarity_reversal_workaround(hw);
-            if (ret_val)
-                return ret_val;
-        }
-    } else if (hw->phy_type == e1000_phy_gg82563) {
-        /* The TX_CLK of the Extended PHY Specific Control Register defaults
-         * to 2.5MHz on a reset.  We need to re-force it back to 25MHz, if
-         * we're not in a forced 10/duplex configuration. */
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
-        if ((hw->forced_speed_duplex == e1000_10_full) ||
-            (hw->forced_speed_duplex == e1000_10_half))
-            phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
-        else
-            phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
-
-        /* Also due to the reset, we need to enable CRS on Tx. */
-        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
-
-        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-    return E1000_SUCCESS;
+        u32 ctrl;
+        s32 ret_val;
+        u16 mii_ctrl_reg;
+        u16 mii_status_reg;
+        u16 phy_data;
+        u16 i;
+
+        DEBUGFUNC("e1000_phy_force_speed_duplex");
+
+        /* Turn off Flow control if we are forcing speed and duplex. */
+        hw->fc = E1000_FC_NONE;
+
+        DEBUGOUT1("hw->fc = %d\n", hw->fc);
+
+        /* Read the Device Control Register. */
+        ctrl = er32(CTRL);
+
+        /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
+        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+        ctrl &= ~(DEVICE_SPEED_MASK);
+
+        /* Clear the Auto Speed Detect Enable bit. */
+        ctrl &= ~E1000_CTRL_ASDE;
+
+        /* Read the MII Control Register. */
+        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
+        if (ret_val)
+                return ret_val;
+
+        /* We need to disable autoneg in order to force link and duplex. */
+
+        mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
+
+        /* Are we forcing Full or Half Duplex? */
+        if (hw->forced_speed_duplex == e1000_100_full ||
+            hw->forced_speed_duplex == e1000_10_full) {
+                /* We want to force full duplex so we SET the full duplex bits in the
+                 * Device and MII Control Registers.
+                 */
+                ctrl |= E1000_CTRL_FD;
+                mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
+                DEBUGOUT("Full Duplex\n");
+        } else {
+                /* We want to force half duplex so we CLEAR the full duplex bits in
+                 * the Device and MII Control Registers.
+                 */
+                ctrl &= ~E1000_CTRL_FD;
+                mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
+                DEBUGOUT("Half Duplex\n");
+        }
+
+        /* Are we forcing 100Mbps??? */
+        if (hw->forced_speed_duplex == e1000_100_full ||
+            hw->forced_speed_duplex == e1000_100_half) {
+                /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
+                ctrl |= E1000_CTRL_SPD_100;
+                mii_ctrl_reg |= MII_CR_SPEED_100;
+                mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+                DEBUGOUT("Forcing 100mb ");
+        } else {
+                /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
+                ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+                mii_ctrl_reg |= MII_CR_SPEED_10;
+                mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
+                DEBUGOUT("Forcing 10mb ");
+        }
+
+        e1000_config_collision_dist(hw);
+
+        /* Write the configured values back to the Device Control Reg. */
+        ew32(CTRL, ctrl);
+
+        if (hw->phy_type == e1000_phy_m88) {
+                ret_val =
+                    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
+                 * forced whenever speed are duplex are forced.
+                 */
+                phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+                ret_val =
+                    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
+
+                /* Need to reset the PHY or these changes will be ignored */
+                mii_ctrl_reg |= MII_CR_RESET;
+
+                /* Disable MDI-X support for 10/100 */
+        } else {
+                /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
+                 * forced whenever speed or duplex are forced.
+                 */
+                ret_val =
+                    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+                phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+
+                ret_val =
+                    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        /* Write back the modified PHY MII control register. */
+        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
+        if (ret_val)
+                return ret_val;
+
+        udelay(1);
+
+        /* The wait_autoneg_complete flag may be a little misleading here.
+         * Since we are forcing speed and duplex, Auto-Neg is not enabled.
+         * But we do want to delay for a period while forcing only so we
+         * don't generate false No Link messages.  So we will wait here
+         * only if the user has set wait_autoneg_complete to 1, which is
+         * the default.
+         */
+        if (hw->wait_autoneg_complete) {
+                /* We will wait for autoneg to complete. */
+                DEBUGOUT("Waiting for forced speed/duplex link.\n");
+                mii_status_reg = 0;
+
+                /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+                for (i = PHY_FORCE_TIME; i > 0; i--) {
+                        /* Read the MII Status Register and wait for Auto-Neg Complete bit
+                         * to be set.
+                         */
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                        if (ret_val)
+                                return ret_val;
+
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                        if (ret_val)
+                                return ret_val;
+
+                        if (mii_status_reg & MII_SR_LINK_STATUS)
+                                break;
+                        msleep(100);
+                }
+                if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
+                        /* We didn't get link.  Reset the DSP and wait again for link. */
+                        ret_val = e1000_phy_reset_dsp(hw);
+                        if (ret_val) {
+                                DEBUGOUT("Error Resetting PHY DSP\n");
+                                return ret_val;
+                        }
+                }
+                /* This loop will early-out if the link condition has been met.  */
+                for (i = PHY_FORCE_TIME; i > 0; i--) {
+                        if (mii_status_reg & MII_SR_LINK_STATUS)
+                                break;
+                        msleep(100);
+                        /* Read the MII Status Register and wait for Auto-Neg Complete bit
+                         * to be set.
+                         */
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                        if (ret_val)
+                                return ret_val;
+
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                        if (ret_val)
+                                return ret_val;
+                }
+        }
+
+        if (hw->phy_type == e1000_phy_m88) {
+                /* Because we reset the PHY above, we need to re-force TX_CLK in the
+                 * Extended PHY Specific Control Register to 25MHz clock.  This value
+                 * defaults back to a 2.5MHz clock when the PHY is reset.
+                 */
+                ret_val =
+                    e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                       &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_data |= M88E1000_EPSCR_TX_CLK_25;
+                ret_val =
+                    e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                        phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                /* In addition, because of the s/w reset above, we need to enable CRS on
+                 * TX.  This must be set for both full and half duplex operation.
+                 */
+                ret_val =
+                    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+                ret_val =
+                    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
+                    && (!hw->autoneg)
+                    && (hw->forced_speed_duplex == e1000_10_full
+                        || hw->forced_speed_duplex == e1000_10_half)) {
+                        ret_val = e1000_polarity_reversal_workaround(hw);
+                        if (ret_val)
+                                return ret_val;
+                }
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Sets the collision distance in the Transmit Control register
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Link should have been established previously. Reads the speed and duplex
-* information from the Device Status register.
-******************************************************************************/
+/**
+ * e1000_config_collision_dist - set collision distance register
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Sets the collision distance in the Transmit Control register.
+ * Link should have been established previously. Reads the speed and duplex
+ * information from the Device Status register.
+ */
 void e1000_config_collision_dist(struct e1000_hw *hw)
 {
-    u32 tctl, coll_dist;
+        u32 tctl, coll_dist;
 
-    DEBUGFUNC("e1000_config_collision_dist");
+        DEBUGFUNC("e1000_config_collision_dist");
 
-    if (hw->mac_type < e1000_82543)
-        coll_dist = E1000_COLLISION_DISTANCE_82542;
-    else
-        coll_dist = E1000_COLLISION_DISTANCE;
+        if (hw->mac_type < e1000_82543)
+                coll_dist = E1000_COLLISION_DISTANCE_82542;
+        else
+                coll_dist = E1000_COLLISION_DISTANCE;
 
-    tctl = er32(TCTL);
+        tctl = er32(TCTL);
 
-    tctl &= ~E1000_TCTL_COLD;
-    tctl |= coll_dist << E1000_COLD_SHIFT;
+        tctl &= ~E1000_TCTL_COLD;
+        tctl |= coll_dist << E1000_COLD_SHIFT;
 
-    ew32(TCTL, tctl);
-    E1000_WRITE_FLUSH();
+        ew32(TCTL, tctl);
+        E1000_WRITE_FLUSH();
 }
 
-/******************************************************************************
-* Sets MAC speed and duplex settings to reflect the those in the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* mii_reg - data to write to the MII control register
-*
-* The contents of the PHY register containing the needed information need to
-* be passed in.
-******************************************************************************/
+/**
+ * e1000_config_mac_to_phy - sync phy and mac settings
+ * @hw: Struct containing variables accessed by shared code
+ * @mii_reg: data to write to the MII control register
+ *
+ * Sets MAC speed and duplex settings to reflect the those in the PHY
+ * The contents of the PHY register containing the needed information need to
+ * be passed in.
+ */
 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_config_mac_to_phy");
-
-    /* 82544 or newer MAC, Auto Speed Detection takes care of
-    * MAC speed/duplex configuration.*/
-    if (hw->mac_type >= e1000_82544)
-        return E1000_SUCCESS;
-
-    /* Read the Device Control Register and set the bits to Force Speed
-     * and Duplex.
-     */
-    ctrl = er32(CTRL);
-    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
-
-    /* Set up duplex in the Device Control and Transmit Control
-     * registers depending on negotiated values.
-     */
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if (phy_data & M88E1000_PSSR_DPLX)
-        ctrl |= E1000_CTRL_FD;
-    else
-        ctrl &= ~E1000_CTRL_FD;
-
-    e1000_config_collision_dist(hw);
-
-    /* Set up speed in the Device Control register depending on
-     * negotiated values.
-     */
-    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-        ctrl |= E1000_CTRL_SPD_1000;
-    else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-        ctrl |= E1000_CTRL_SPD_100;
-
-    /* Write the configured values back to the Device Control Reg. */
-    ew32(CTRL, ctrl);
-    return E1000_SUCCESS;
+        u32 ctrl;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_config_mac_to_phy");
+
+        /* 82544 or newer MAC, Auto Speed Detection takes care of
+         * MAC speed/duplex configuration.*/
+        if (hw->mac_type >= e1000_82544)
+                return E1000_SUCCESS;
+
+        /* Read the Device Control Register and set the bits to Force Speed
+         * and Duplex.
+         */
+        ctrl = er32(CTRL);
+        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+        ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
+
+        /* Set up duplex in the Device Control and Transmit Control
+         * registers depending on negotiated values.
+         */
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        if (phy_data & M88E1000_PSSR_DPLX)
+                ctrl |= E1000_CTRL_FD;
+        else
+                ctrl &= ~E1000_CTRL_FD;
+
+        e1000_config_collision_dist(hw);
+
+        /* Set up speed in the Device Control register depending on
+         * negotiated values.
+         */
+        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+                ctrl |= E1000_CTRL_SPD_1000;
+        else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
+                ctrl |= E1000_CTRL_SPD_100;
+
+        /* Write the configured values back to the Device Control Reg. */
+        ew32(CTRL, ctrl);
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Forces the MAC's flow control settings.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_force_mac_fc - force flow control settings
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Forces the MAC's flow control settings.
  * Sets the TFCE and RFCE bits in the device control register to reflect
  * the adapter settings. TFCE and RFCE need to be explicitly set by
  * software when a Copper PHY is used because autonegotiation is managed
  * by the PHY rather than the MAC. Software must also configure these
  * bits when link is forced on a fiber connection.
- *****************************************************************************/
+ */
 s32 e1000_force_mac_fc(struct e1000_hw *hw)
 {
-    u32 ctrl;
-
-    DEBUGFUNC("e1000_force_mac_fc");
-
-    /* Get the current configuration of the Device Control Register */
-    ctrl = er32(CTRL);
-
-    /* Because we didn't get link via the internal auto-negotiation
-     * mechanism (we either forced link or we got link via PHY
-     * auto-neg), we have to manually enable/disable transmit an
-     * receive flow control.
-     *
-     * The "Case" statement below enables/disable flow control
-     * according to the "hw->fc" parameter.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause
-     *          frames but not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames
-     *          frames but we do not receive pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) is enabled.
-     *  other:  No other values should be possible at this point.
-     */
-
-    switch (hw->fc) {
-    case E1000_FC_NONE:
-        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
-        break;
-    case E1000_FC_RX_PAUSE:
-        ctrl &= (~E1000_CTRL_TFCE);
-        ctrl |= E1000_CTRL_RFCE;
-        break;
-    case E1000_FC_TX_PAUSE:
-        ctrl &= (~E1000_CTRL_RFCE);
-        ctrl |= E1000_CTRL_TFCE;
-        break;
-    case E1000_FC_FULL:
-        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    /* Disable TX Flow Control for 82542 (rev 2.0) */
-    if (hw->mac_type == e1000_82542_rev2_0)
-        ctrl &= (~E1000_CTRL_TFCE);
-
-    ew32(CTRL, ctrl);
-    return E1000_SUCCESS;
+        u32 ctrl;
+
+        DEBUGFUNC("e1000_force_mac_fc");
+
+        /* Get the current configuration of the Device Control Register */
+        ctrl = er32(CTRL);
+
+        /* Because we didn't get link via the internal auto-negotiation
+         * mechanism (we either forced link or we got link via PHY
+         * auto-neg), we have to manually enable/disable transmit an
+         * receive flow control.
+         *
+         * The "Case" statement below enables/disable flow control
+         * according to the "hw->fc" parameter.
+         *
+         * The possible values of the "fc" parameter are:
+         *      0:  Flow control is completely disabled
+         *      1:  Rx flow control is enabled (we can receive pause
+         *          frames but not send pause frames).
+         *      2:  Tx flow control is enabled (we can send pause frames
+         *          frames but we do not receive pause frames).
+         *      3:  Both Rx and TX flow control (symmetric) is enabled.
+         *  other:  No other values should be possible at this point.
+         */
+
+        switch (hw->fc) {
+        case E1000_FC_NONE:
+                ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
+                break;
+        case E1000_FC_RX_PAUSE:
+                ctrl &= (~E1000_CTRL_TFCE);
+                ctrl |= E1000_CTRL_RFCE;
+                break;
+        case E1000_FC_TX_PAUSE:
+                ctrl &= (~E1000_CTRL_RFCE);
+                ctrl |= E1000_CTRL_TFCE;
+                break;
+        case E1000_FC_FULL:
+                ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
+                break;
+        default:
+                DEBUGOUT("Flow control param set incorrectly\n");
+                return -E1000_ERR_CONFIG;
+        }
+
+        /* Disable TX Flow Control for 82542 (rev 2.0) */
+        if (hw->mac_type == e1000_82542_rev2_0)
+                ctrl &= (~E1000_CTRL_TFCE);
+
+        ew32(CTRL, ctrl);
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Configures flow control settings after link is established
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_config_fc_after_link_up - configure flow control after autoneg
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Configures flow control settings after link is established
  * Should be called immediately after a valid link has been established.
  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  * and autonegotiation is enabled, the MAC flow control settings will be set
  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
- * and RFCE bits will be automaticaly set to the negotiated flow control mode.
- *****************************************************************************/
+ * and RFCE bits will be automatically set to the negotiated flow control mode.
+ */
 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 mii_status_reg;
-    u16 mii_nway_adv_reg;
-    u16 mii_nway_lp_ability_reg;
-    u16 speed;
-    u16 duplex;
-
-    DEBUGFUNC("e1000_config_fc_after_link_up");
-
-    /* Check for the case where we have fiber media and auto-neg failed
-     * so we had to force link.  In this case, we need to force the
-     * configuration of the MAC to match the "fc" parameter.
-     */
-    if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
-        ((hw->media_type == e1000_media_type_internal_serdes) &&
-         (hw->autoneg_failed)) ||
-        ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
-        ret_val = e1000_force_mac_fc(hw);
-        if (ret_val) {
-            DEBUGOUT("Error forcing flow control settings\n");
-            return ret_val;
-        }
-    }
-
-    /* Check for the case where we have copper media and auto-neg is
-     * enabled.  In this case, we need to check and see if Auto-Neg
-     * has completed, and if so, how the PHY and link partner has
-     * flow control configured.
-     */
-    if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
-        /* Read the MII Status Register and check to see if AutoNeg
-         * has completed.  We read this twice because this reg has
-         * some "sticky" (latched) bits.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
-            /* The AutoNeg process has completed, so we now need to
-             * read both the Auto Negotiation Advertisement Register
-             * (Address 4) and the Auto_Negotiation Base Page Ability
-             * Register (Address 5) to determine how flow control was
-             * negotiated.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
-                                         &mii_nway_adv_reg);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
-                                         &mii_nway_lp_ability_reg);
-            if (ret_val)
-                return ret_val;
-
-            /* Two bits in the Auto Negotiation Advertisement Register
-             * (Address 4) and two bits in the Auto Negotiation Base
-             * Page Ability Register (Address 5) determine flow control
-             * for both the PHY and the link partner.  The following
-             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
-             * 1999, describes these PAUSE resolution bits and how flow
-             * control is determined based upon these settings.
-             * NOTE:  DC = Don't Care
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
-             *-------|---------|-------|---------|--------------------
-             *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
-             *   0   |    1    |   0   |   DC    | E1000_FC_NONE
-             *   0   |    1    |   1   |    0    | E1000_FC_NONE
-             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
-             *   1   |    0    |   0   |   DC    | E1000_FC_NONE
-             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
-             *   1   |    1    |   0   |    0    | E1000_FC_NONE
-             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
-             *
-             */
-            /* Are both PAUSE bits set to 1?  If so, this implies
-             * Symmetric Flow Control is enabled at both ends.  The
-             * ASM_DIR bits are irrelevant per the spec.
-             *
-             * For Symmetric Flow Control:
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
-             *
-             */
-            if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
-                /* Now we need to check if the user selected RX ONLY
-                 * of pause frames.  In this case, we had to advertise
-                 * FULL flow control because we could not advertise RX
-                 * ONLY. Hence, we must now check to see if we need to
-                 * turn OFF  the TRANSMISSION of PAUSE frames.
-                 */
-                if (hw->original_fc == E1000_FC_FULL) {
-                    hw->fc = E1000_FC_FULL;
-                    DEBUGOUT("Flow Control = FULL.\n");
-                } else {
-                    hw->fc = E1000_FC_RX_PAUSE;
-                    DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-                }
-            }
-            /* For receiving PAUSE frames ONLY.
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
-             *
-             */
-            else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                hw->fc = E1000_FC_TX_PAUSE;
-                DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
-            }
-            /* For transmitting PAUSE frames ONLY.
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
-             *
-             */
-            else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                     !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                hw->fc = E1000_FC_RX_PAUSE;
-                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-            }
-            /* Per the IEEE spec, at this point flow control should be
-             * disabled.  However, we want to consider that we could
-             * be connected to a legacy switch that doesn't advertise
-             * desired flow control, but can be forced on the link
-             * partner.  So if we advertised no flow control, that is
-             * what we will resolve to.  If we advertised some kind of
-             * receive capability (Rx Pause Only or Full Flow Control)
-             * and the link partner advertised none, we will configure
-             * ourselves to enable Rx Flow Control only.  We can do
-             * this safely for two reasons:  If the link partner really
-             * didn't want flow control enabled, and we enable Rx, no
-             * harm done since we won't be receiving any PAUSE frames
-             * anyway.  If the intent on the link partner was to have
-             * flow control enabled, then by us enabling RX only, we
-             * can at least receive pause frames and process them.
-             * This is a good idea because in most cases, since we are
-             * predominantly a server NIC, more times than not we will
-             * be asked to delay transmission of packets than asking
-             * our link partner to pause transmission of frames.
-             */
-            else if ((hw->original_fc == E1000_FC_NONE ||
-                      hw->original_fc == E1000_FC_TX_PAUSE) ||
-                      hw->fc_strict_ieee) {
-                hw->fc = E1000_FC_NONE;
-                DEBUGOUT("Flow Control = NONE.\n");
-            } else {
-                hw->fc = E1000_FC_RX_PAUSE;
-                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-            }
-
-            /* Now we need to do one last check...  If we auto-
-             * negotiated to HALF DUPLEX, flow control should not be
-             * enabled per IEEE 802.3 spec.
-             */
-            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-            if (ret_val) {
-                DEBUGOUT("Error getting link speed and duplex\n");
-                return ret_val;
-            }
-
-            if (duplex == HALF_DUPLEX)
-                hw->fc = E1000_FC_NONE;
-
-            /* Now we call a subroutine to actually force the MAC
-             * controller to use the correct flow control settings.
-             */
-            ret_val = e1000_force_mac_fc(hw);
-            if (ret_val) {
-                DEBUGOUT("Error forcing flow control settings\n");
-                return ret_val;
-            }
-        } else {
-            DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
-        }
-    }
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 mii_status_reg;
+        u16 mii_nway_adv_reg;
+        u16 mii_nway_lp_ability_reg;
+        u16 speed;
+        u16 duplex;
+
+        DEBUGFUNC("e1000_config_fc_after_link_up");
+
+        /* Check for the case where we have fiber media and auto-neg failed
+         * so we had to force link.  In this case, we need to force the
+         * configuration of the MAC to match the "fc" parameter.
+         */
+        if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
+            || ((hw->media_type == e1000_media_type_internal_serdes)
+                && (hw->autoneg_failed))
+            || ((hw->media_type == e1000_media_type_copper)
+                && (!hw->autoneg))) {
+                ret_val = e1000_force_mac_fc(hw);
+                if (ret_val) {
+                        DEBUGOUT("Error forcing flow control settings\n");
+                        return ret_val;
+                }
+        }
+
+        /* Check for the case where we have copper media and auto-neg is
+         * enabled.  In this case, we need to check and see if Auto-Neg
+         * has completed, and if so, how the PHY and link partner has
+         * flow control configured.
+         */
+        if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
+                /* Read the MII Status Register and check to see if AutoNeg
+                 * has completed.  We read this twice because this reg has
+                 * some "sticky" (latched) bits.
+                 */
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
+
+                if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
+                        /* The AutoNeg process has completed, so we now need to
+                         * read both the Auto Negotiation Advertisement Register
+                         * (Address 4) and the Auto_Negotiation Base Page Ability
+                         * Register (Address 5) to determine how flow control was
+                         * negotiated.
+                         */
+                        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
+                                                     &mii_nway_adv_reg);
+                        if (ret_val)
+                                return ret_val;
+                        ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
+                                                     &mii_nway_lp_ability_reg);
+                        if (ret_val)
+                                return ret_val;
+
+                        /* Two bits in the Auto Negotiation Advertisement Register
+                         * (Address 4) and two bits in the Auto Negotiation Base
+                         * Page Ability Register (Address 5) determine flow control
+                         * for both the PHY and the link partner.  The following
+                         * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+                         * 1999, describes these PAUSE resolution bits and how flow
+                         * control is determined based upon these settings.
+                         * NOTE:  DC = Don't Care
+                         *
+                         *   LOCAL DEVICE  |   LINK PARTNER
+                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+                         *-------|---------|-------|---------|--------------------
+                         *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
+                         *   0   |    1    |   0   |   DC    | E1000_FC_NONE
+                         *   0   |    1    |   1   |    0    | E1000_FC_NONE
+                         *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+                         *   1   |    0    |   0   |   DC    | E1000_FC_NONE
+                         *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+                         *   1   |    1    |   0   |    0    | E1000_FC_NONE
+                         *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+                         *
+                         */
+                        /* Are both PAUSE bits set to 1?  If so, this implies
+                         * Symmetric Flow Control is enabled at both ends.  The
+                         * ASM_DIR bits are irrelevant per the spec.
+                         *
+                         * For Symmetric Flow Control:
+                         *
+                         *   LOCAL DEVICE  |   LINK PARTNER
+                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                         *-------|---------|-------|---------|--------------------
+                         *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+                         *
+                         */
+                        if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                            (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
+                                /* Now we need to check if the user selected RX ONLY
+                                 * of pause frames.  In this case, we had to advertise
+                                 * FULL flow control because we could not advertise RX
+                                 * ONLY. Hence, we must now check to see if we need to
+                                 * turn OFF  the TRANSMISSION of PAUSE frames.
+                                 */
+                                if (hw->original_fc == E1000_FC_FULL) {
+                                        hw->fc = E1000_FC_FULL;
+                                        DEBUGOUT("Flow Control = FULL.\n");
+                                } else {
+                                        hw->fc = E1000_FC_RX_PAUSE;
+                                        DEBUGOUT
+                                            ("Flow Control = RX PAUSE frames only.\n");
+                                }
+                        }
+                        /* For receiving PAUSE frames ONLY.
+                         *
+                         *   LOCAL DEVICE  |   LINK PARTNER
+                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                         *-------|---------|-------|---------|--------------------
+                         *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+                         *
+                         */
+                        else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
+                        {
+                                hw->fc = E1000_FC_TX_PAUSE;
+                                DEBUGOUT
+                                    ("Flow Control = TX PAUSE frames only.\n");
+                        }
+                        /* For transmitting PAUSE frames ONLY.
+                         *
+                         *   LOCAL DEVICE  |   LINK PARTNER
+                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                         *-------|---------|-------|---------|--------------------
+                         *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+                         *
+                         */
+                        else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
+                        {
+                                hw->fc = E1000_FC_RX_PAUSE;
+                                DEBUGOUT
+                                    ("Flow Control = RX PAUSE frames only.\n");
+                        }
+                        /* Per the IEEE spec, at this point flow control should be
+                         * disabled.  However, we want to consider that we could
+                         * be connected to a legacy switch that doesn't advertise
+                         * desired flow control, but can be forced on the link
+                         * partner.  So if we advertised no flow control, that is
+                         * what we will resolve to.  If we advertised some kind of
+                         * receive capability (Rx Pause Only or Full Flow Control)
+                         * and the link partner advertised none, we will configure
+                         * ourselves to enable Rx Flow Control only.  We can do
+                         * this safely for two reasons:  If the link partner really
+                         * didn't want flow control enabled, and we enable Rx, no
+                         * harm done since we won't be receiving any PAUSE frames
+                         * anyway.  If the intent on the link partner was to have
+                         * flow control enabled, then by us enabling RX only, we
+                         * can at least receive pause frames and process them.
+                         * This is a good idea because in most cases, since we are
+                         * predominantly a server NIC, more times than not we will
+                         * be asked to delay transmission of packets than asking
+                         * our link partner to pause transmission of frames.
+                         */
+                        else if ((hw->original_fc == E1000_FC_NONE ||
+                                  hw->original_fc == E1000_FC_TX_PAUSE) ||
+                                 hw->fc_strict_ieee) {
+                                hw->fc = E1000_FC_NONE;
+                                DEBUGOUT("Flow Control = NONE.\n");
+                        } else {
+                                hw->fc = E1000_FC_RX_PAUSE;
+                                DEBUGOUT
+                                    ("Flow Control = RX PAUSE frames only.\n");
+                        }
+
+                        /* Now we need to do one last check...  If we auto-
+                         * negotiated to HALF DUPLEX, flow control should not be
+                         * enabled per IEEE 802.3 spec.
+                         */
+                        ret_val =
+                            e1000_get_speed_and_duplex(hw, &speed, &duplex);
+                        if (ret_val) {
+                                DEBUGOUT
+                                    ("Error getting link speed and duplex\n");
+                                return ret_val;
+                        }
+
+                        if (duplex == HALF_DUPLEX)
+                                hw->fc = E1000_FC_NONE;
+
+                        /* Now we call a subroutine to actually force the MAC
+                         * controller to use the correct flow control settings.
+                         */
+                        ret_val = e1000_force_mac_fc(hw);
+                        if (ret_val) {
+                                DEBUGOUT
+                                    ("Error forcing flow control settings\n");
+                                return ret_val;
+                        }
+                } else {
+                        DEBUGOUT
+                            ("Copper PHY and Auto Neg has not completed.\n");
+                }
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Checks to see if the link status of the hardware has changed.
+/**
+ * e1000_check_for_serdes_link_generic - Check for link (Serdes)
+ * @hw: pointer to the HW structure
  *
- * hw - Struct containing variables accessed by shared code
+ * Checks for link up on the hardware.  If link is not up and we have
+ * a signal, then we need to force link up.
+ */
+static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
+{
+        u32 rxcw;
+        u32 ctrl;
+        u32 status;
+        s32 ret_val = E1000_SUCCESS;
+
+        DEBUGFUNC("e1000_check_for_serdes_link_generic");
+
+        ctrl = er32(CTRL);
+        status = er32(STATUS);
+        rxcw = er32(RXCW);
+
+        /*
+         * If we don't have link (auto-negotiation failed or link partner
+         * cannot auto-negotiate), and our link partner is not trying to
+         * auto-negotiate with us (we are receiving idles or data),
+         * we need to force link up. We also need to give auto-negotiation
+         * time to complete.
+         */
+        /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
+        if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
+                if (hw->autoneg_failed == 0) {
+                        hw->autoneg_failed = 1;
+                        goto out;
+                }
+                DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
+
+                /* Disable auto-negotiation in the TXCW register */
+                ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
+
+                /* Force link-up and also force full-duplex. */
+                ctrl = er32(CTRL);
+                ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+                ew32(CTRL, ctrl);
+
+                /* Configure Flow Control after forcing link up. */
+                ret_val = e1000_config_fc_after_link_up(hw);
+                if (ret_val) {
+                        DEBUGOUT("Error configuring flow control\n");
+                        goto out;
+                }
+        } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
+                /*
+                 * If we are forcing link and we are receiving /C/ ordered
+                 * sets, re-enable auto-negotiation in the TXCW register
+                 * and disable forced link in the Device Control register
+                 * in an attempt to auto-negotiate with our link partner.
+                 */
+                DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
+                ew32(TXCW, hw->txcw);
+                ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
+
+                hw->serdes_has_link = true;
+        } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
+                /*
+                 * If we force link for non-auto-negotiation switch, check
+                 * link status based on MAC synchronization for internal
+                 * serdes media type.
+                 */
+                /* SYNCH bit and IV bit are sticky. */
+                udelay(10);
+                rxcw = er32(RXCW);
+                if (rxcw & E1000_RXCW_SYNCH) {
+                        if (!(rxcw & E1000_RXCW_IV)) {
+                                hw->serdes_has_link = true;
+                                DEBUGOUT("SERDES: Link up - forced.\n");
+                        }
+                } else {
+                        hw->serdes_has_link = false;
+                        DEBUGOUT("SERDES: Link down - force failed.\n");
+                }
+        }
+
+        if (E1000_TXCW_ANE & er32(TXCW)) {
+                status = er32(STATUS);
+                if (status & E1000_STATUS_LU) {
+                        /* SYNCH bit and IV bit are sticky, so reread rxcw. */
+                        udelay(10);
+                        rxcw = er32(RXCW);
+                        if (rxcw & E1000_RXCW_SYNCH) {
+                                if (!(rxcw & E1000_RXCW_IV)) {
+                                        hw->serdes_has_link = true;
+                                        DEBUGOUT("SERDES: Link up - autoneg "
+                                                 "completed successfully.\n");
+                                } else {
+                                        hw->serdes_has_link = false;
+                                        DEBUGOUT("SERDES: Link down - invalid"
+                                                 "codewords detected in autoneg.\n");
+                                }
+                        } else {
+                                hw->serdes_has_link = false;
+                                DEBUGOUT("SERDES: Link down - no sync.\n");
+                        }
+                } else {
+                        hw->serdes_has_link = false;
+                        DEBUGOUT("SERDES: Link down - autoneg failed\n");
+                }
+        }
+
+      out:
+        return ret_val;
+}
+
+/**
+ * e1000_check_for_link
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Checks to see if the link status of the hardware has changed.
  * Called by any function that needs to check the link status of the adapter.
- *****************************************************************************/
+ */
 s32 e1000_check_for_link(struct e1000_hw *hw)
 {
-    u32 rxcw = 0;
-    u32 ctrl;
-    u32 status;
-    u32 rctl;
-    u32 icr;
-    u32 signal = 0;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_for_link");
-
-    ctrl = er32(CTRL);
-    status = er32(STATUS);
-
-    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
-     * set when the optics detect a signal. On older adapters, it will be
-     * cleared when there is a signal.  This applies to fiber media only.
-     */
-    if ((hw->media_type == e1000_media_type_fiber) ||
-        (hw->media_type == e1000_media_type_internal_serdes)) {
-        rxcw = er32(RXCW);
-
-        if (hw->media_type == e1000_media_type_fiber) {
-            signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-            if (status & E1000_STATUS_LU)
-                hw->get_link_status = false;
-        }
-    }
-
-    /* If we have a copper PHY then we only want to go out to the PHY
-     * registers to see if Auto-Neg has completed and/or if our link
-     * status has changed.  The get_link_status flag will be set if we
-     * receive a Link Status Change interrupt or we have Rx Sequence
-     * Errors.
-     */
-    if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
-        /* First we want to see if the MII Status Register reports
-         * link.  If so, then we want to get the current speed/duplex
-         * of the PHY.
-         * Read the register twice since the link bit is sticky.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (phy_data & MII_SR_LINK_STATUS) {
-            hw->get_link_status = false;
-            /* Check if there was DownShift, must be checked immediately after
-             * link-up */
-            e1000_check_downshift(hw);
-
-            /* If we are on 82544 or 82543 silicon and speed/duplex
-             * are forced to 10H or 10F, then we will implement the polarity
-             * reversal workaround.  We disable interrupts first, and upon
-             * returning, place the devices interrupt state to its previous
-             * value except for the link status change interrupt which will
-             * happen due to the execution of this workaround.
-             */
-
-            if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-                (!hw->autoneg) &&
-                (hw->forced_speed_duplex == e1000_10_full ||
-                 hw->forced_speed_duplex == e1000_10_half)) {
-                ew32(IMC, 0xffffffff);
-                ret_val = e1000_polarity_reversal_workaround(hw);
-                icr = er32(ICR);
-                ew32(ICS, (icr & ~E1000_ICS_LSC));
-                ew32(IMS, IMS_ENABLE_MASK);
-            }
-
-        } else {
-            /* No link detected */
-            e1000_config_dsp_after_link_change(hw, false);
-            return 0;
-        }
-
-        /* If we are forcing speed/duplex, then we simply return since
-         * we have already determined whether we have link or not.
-         */
-        if (!hw->autoneg) return -E1000_ERR_CONFIG;
-
-        /* optimize the dsp settings for the igp phy */
-        e1000_config_dsp_after_link_change(hw, true);
-
-        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
-         * have Si on board that is 82544 or newer, Auto
-         * Speed Detection takes care of MAC speed/duplex
-         * configuration.  So we only need to configure Collision
-         * Distance in the MAC.  Otherwise, we need to force
-         * speed/duplex on the MAC to the current PHY speed/duplex
-         * settings.
-         */
-        if (hw->mac_type >= e1000_82544)
-            e1000_config_collision_dist(hw);
-        else {
-            ret_val = e1000_config_mac_to_phy(hw);
-            if (ret_val) {
-                DEBUGOUT("Error configuring MAC to PHY settings\n");
-                return ret_val;
-            }
-        }
-
-        /* Configure Flow Control now that Auto-Neg has completed. First, we
-         * need to restore the desired flow control settings because we may
-         * have had to re-autoneg with a different link partner.
-         */
-        ret_val = e1000_config_fc_after_link_up(hw);
-        if (ret_val) {
-            DEBUGOUT("Error configuring flow control\n");
-            return ret_val;
-        }
-
-        /* At this point we know that we are on copper and we have
-         * auto-negotiated link.  These are conditions for checking the link
-         * partner capability register.  We use the link speed to determine if
-         * TBI compatibility needs to be turned on or off.  If the link is not
-         * at gigabit speed, then TBI compatibility is not needed.  If we are
-         * at gigabit speed, we turn on TBI compatibility.
-         */
-        if (hw->tbi_compatibility_en) {
-            u16 speed, duplex;
-            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-            if (ret_val) {
-                DEBUGOUT("Error getting link speed and duplex\n");
-                return ret_val;
-            }
-            if (speed != SPEED_1000) {
-                /* If link speed is not set to gigabit speed, we do not need
-                 * to enable TBI compatibility.
-                 */
-                if (hw->tbi_compatibility_on) {
-                    /* If we previously were in the mode, turn it off. */
-                    rctl = er32(RCTL);
-                    rctl &= ~E1000_RCTL_SBP;
-                    ew32(RCTL, rctl);
-                    hw->tbi_compatibility_on = false;
-                }
-            } else {
-                /* If TBI compatibility is was previously off, turn it on. For
-                 * compatibility with a TBI link partner, we will store bad
-                 * packets. Some frames have an additional byte on the end and
-                 * will look like CRC errors to the hardware.
-                 */
-                if (!hw->tbi_compatibility_on) {
-                    hw->tbi_compatibility_on = true;
-                    rctl = er32(RCTL);
-                    rctl |= E1000_RCTL_SBP;
-                    ew32(RCTL, rctl);
-                }
-            }
-        }
-    }
-    /* If we don't have link (auto-negotiation failed or link partner cannot
-     * auto-negotiate), the cable is plugged in (we have signal), and our
-     * link partner is not trying to auto-negotiate with us (we are receiving
-     * idles or data), we need to force link up. We also need to give
-     * auto-negotiation time to complete, in case the cable was just plugged
-     * in. The autoneg_failed flag does this.
-     */
-    else if ((((hw->media_type == e1000_media_type_fiber) &&
-              ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
-              (hw->media_type == e1000_media_type_internal_serdes)) &&
-              (!(status & E1000_STATUS_LU)) &&
-              (!(rxcw & E1000_RXCW_C))) {
-        if (hw->autoneg_failed == 0) {
-            hw->autoneg_failed = 1;
-            return 0;
-        }
-        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
-
-        /* Disable auto-negotiation in the TXCW register */
-        ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
-
-        /* Force link-up and also force full-duplex. */
-        ctrl = er32(CTRL);
-        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
-        ew32(CTRL, ctrl);
-
-        /* Configure Flow Control after forcing link up. */
-        ret_val = e1000_config_fc_after_link_up(hw);
-        if (ret_val) {
-            DEBUGOUT("Error configuring flow control\n");
-            return ret_val;
-        }
-    }
-    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
-     * auto-negotiation in the TXCW register and disable forced link in the
-     * Device Control register in an attempt to auto-negotiate with our link
-     * partner.
-     */
-    else if (((hw->media_type == e1000_media_type_fiber) ||
-              (hw->media_type == e1000_media_type_internal_serdes)) &&
-              (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
-        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
-        ew32(TXCW, hw->txcw);
-        ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
-
-        hw->serdes_link_down = false;
-    }
-    /* If we force link for non-auto-negotiation switch, check link status
-     * based on MAC synchronization for internal serdes media type.
-     */
-    else if ((hw->media_type == e1000_media_type_internal_serdes) &&
-             !(E1000_TXCW_ANE & er32(TXCW))) {
-        /* SYNCH bit and IV bit are sticky. */
-        udelay(10);
-        if (E1000_RXCW_SYNCH & er32(RXCW)) {
-            if (!(rxcw & E1000_RXCW_IV)) {
-                hw->serdes_link_down = false;
-                DEBUGOUT("SERDES: Link is up.\n");
-            }
-        } else {
-            hw->serdes_link_down = true;
-            DEBUGOUT("SERDES: Link is down.\n");
-        }
-    }
-    if ((hw->media_type == e1000_media_type_internal_serdes) &&
-        (E1000_TXCW_ANE & er32(TXCW))) {
-        hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
-    }
-    return E1000_SUCCESS;
+        u32 rxcw = 0;
+        u32 ctrl;
+        u32 status;
+        u32 rctl;
+        u32 icr;
+        u32 signal = 0;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_check_for_link");
+
+        ctrl = er32(CTRL);
+        status = er32(STATUS);
+
+        /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
+         * set when the optics detect a signal. On older adapters, it will be
+         * cleared when there is a signal.  This applies to fiber media only.
+         */
+        if ((hw->media_type == e1000_media_type_fiber) ||
+            (hw->media_type == e1000_media_type_internal_serdes)) {
+                rxcw = er32(RXCW);
+
+                if (hw->media_type == e1000_media_type_fiber) {
+                        signal =
+                            (hw->mac_type >
+                             e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+                        if (status & E1000_STATUS_LU)
+                                hw->get_link_status = false;
+                }
+        }
+
+        /* If we have a copper PHY then we only want to go out to the PHY
+         * registers to see if Auto-Neg has completed and/or if our link
+         * status has changed.  The get_link_status flag will be set if we
+         * receive a Link Status Change interrupt or we have Rx Sequence
+         * Errors.
+         */
+        if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
+                /* First we want to see if the MII Status Register reports
+                 * link.  If so, then we want to get the current speed/duplex
+                 * of the PHY.
+                 * Read the register twice since the link bit is sticky.
+                 */
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if (phy_data & MII_SR_LINK_STATUS) {
+                        hw->get_link_status = false;
+                        /* Check if there was DownShift, must be checked immediately after
+                         * link-up */
+                        e1000_check_downshift(hw);
+
+                        /* If we are on 82544 or 82543 silicon and speed/duplex
+                         * are forced to 10H or 10F, then we will implement the polarity
+                         * reversal workaround.  We disable interrupts first, and upon
+                         * returning, place the devices interrupt state to its previous
+                         * value except for the link status change interrupt which will
+                         * happen due to the execution of this workaround.
+                         */
+
+                        if ((hw->mac_type == e1000_82544
+                             || hw->mac_type == e1000_82543) && (!hw->autoneg)
+                            && (hw->forced_speed_duplex == e1000_10_full
+                                || hw->forced_speed_duplex == e1000_10_half)) {
+                                ew32(IMC, 0xffffffff);
+                                ret_val =
+                                    e1000_polarity_reversal_workaround(hw);
+                                icr = er32(ICR);
+                                ew32(ICS, (icr & ~E1000_ICS_LSC));
+                                ew32(IMS, IMS_ENABLE_MASK);
+                        }
+
+                } else {
+                        /* No link detected */
+                        e1000_config_dsp_after_link_change(hw, false);
+                        return 0;
+                }
+
+                /* If we are forcing speed/duplex, then we simply return since
+                 * we have already determined whether we have link or not.
+                 */
+                if (!hw->autoneg)
+                        return -E1000_ERR_CONFIG;
+
+                /* optimize the dsp settings for the igp phy */
+                e1000_config_dsp_after_link_change(hw, true);
+
+                /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
+                 * have Si on board that is 82544 or newer, Auto
+                 * Speed Detection takes care of MAC speed/duplex
+                 * configuration.  So we only need to configure Collision
+                 * Distance in the MAC.  Otherwise, we need to force
+                 * speed/duplex on the MAC to the current PHY speed/duplex
+                 * settings.
+                 */
+                if (hw->mac_type >= e1000_82544)
+                        e1000_config_collision_dist(hw);
+                else {
+                        ret_val = e1000_config_mac_to_phy(hw);
+                        if (ret_val) {
+                                DEBUGOUT
+                                    ("Error configuring MAC to PHY settings\n");
+                                return ret_val;
+                        }
+                }
+
+                /* Configure Flow Control now that Auto-Neg has completed. First, we
+                 * need to restore the desired flow control settings because we may
+                 * have had to re-autoneg with a different link partner.
+                 */
+                ret_val = e1000_config_fc_after_link_up(hw);
+                if (ret_val) {
+                        DEBUGOUT("Error configuring flow control\n");
+                        return ret_val;
+                }
+
+                /* At this point we know that we are on copper and we have
+                 * auto-negotiated link.  These are conditions for checking the link
+                 * partner capability register.  We use the link speed to determine if
+                 * TBI compatibility needs to be turned on or off.  If the link is not
+                 * at gigabit speed, then TBI compatibility is not needed.  If we are
+                 * at gigabit speed, we turn on TBI compatibility.
+                 */
+                if (hw->tbi_compatibility_en) {
+                        u16 speed, duplex;
+                        ret_val =
+                            e1000_get_speed_and_duplex(hw, &speed, &duplex);
+                        if (ret_val) {
+                                DEBUGOUT
+                                    ("Error getting link speed and duplex\n");
+                                return ret_val;
+                        }
+                        if (speed != SPEED_1000) {
+                                /* If link speed is not set to gigabit speed, we do not need
+                                 * to enable TBI compatibility.
+                                 */
+                                if (hw->tbi_compatibility_on) {
+                                        /* If we previously were in the mode, turn it off. */
+                                        rctl = er32(RCTL);
+                                        rctl &= ~E1000_RCTL_SBP;
+                                        ew32(RCTL, rctl);
+                                        hw->tbi_compatibility_on = false;
+                                }
+                        } else {
+                                /* If TBI compatibility is was previously off, turn it on. For
+                                 * compatibility with a TBI link partner, we will store bad
+                                 * packets. Some frames have an additional byte on the end and
+                                 * will look like CRC errors to to the hardware.
+                                 */
+                                if (!hw->tbi_compatibility_on) {
+                                        hw->tbi_compatibility_on = true;
+                                        rctl = er32(RCTL);
+                                        rctl |= E1000_RCTL_SBP;
+                                        ew32(RCTL, rctl);
+                                }
+                        }
+                }
+        }
+
+        if ((hw->media_type == e1000_media_type_fiber) ||
+            (hw->media_type == e1000_media_type_internal_serdes))
+                e1000_check_for_serdes_link_generic(hw);
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
+/**
+ * e1000_get_speed_and_duplex
+ * @hw: Struct containing variables accessed by shared code
+ * @speed: Speed of the connection
+ * @duplex: Duplex setting of the connection
+
  * Detects the current speed and duplex settings of the hardware.
- *
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- *****************************************************************************/
+ */
 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
 {
-    u32 status;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_get_speed_and_duplex");
-
-    if (hw->mac_type >= e1000_82543) {
-        status = er32(STATUS);
-        if (status & E1000_STATUS_SPEED_1000) {
-            *speed = SPEED_1000;
-            DEBUGOUT("1000 Mbs, ");
-        } else if (status & E1000_STATUS_SPEED_100) {
-            *speed = SPEED_100;
-            DEBUGOUT("100 Mbs, ");
-        } else {
-            *speed = SPEED_10;
-            DEBUGOUT("10 Mbs, ");
-        }
-
-        if (status & E1000_STATUS_FD) {
-            *duplex = FULL_DUPLEX;
-            DEBUGOUT("Full Duplex\n");
-        } else {
-            *duplex = HALF_DUPLEX;
-            DEBUGOUT(" Half Duplex\n");
-        }
-    } else {
-        DEBUGOUT("1000 Mbs, Full Duplex\n");
-        *speed = SPEED_1000;
-        *duplex = FULL_DUPLEX;
-    }
-
-    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
-     * if it is operating at half duplex.  Here we set the duplex settings to
-     * match the duplex in the link partner's capabilities.
-     */
-    if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
-        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
-            *duplex = HALF_DUPLEX;
-        else {
-            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
-            if (ret_val)
-                return ret_val;
-            if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
-               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
-                *duplex = HALF_DUPLEX;
-        }
-    }
-
-    if ((hw->mac_type == e1000_80003es2lan) &&
-        (hw->media_type == e1000_media_type_copper)) {
-        if (*speed == SPEED_1000)
-            ret_val = e1000_configure_kmrn_for_1000(hw);
-        else
-            ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
-        ret_val = e1000_kumeran_lock_loss_workaround(hw);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+        u32 status;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_get_speed_and_duplex");
+
+        if (hw->mac_type >= e1000_82543) {
+                status = er32(STATUS);
+                if (status & E1000_STATUS_SPEED_1000) {
+                        *speed = SPEED_1000;
+                        DEBUGOUT("1000 Mbs, ");
+                } else if (status & E1000_STATUS_SPEED_100) {
+                        *speed = SPEED_100;
+                        DEBUGOUT("100 Mbs, ");
+                } else {
+                        *speed = SPEED_10;
+                        DEBUGOUT("10 Mbs, ");
+                }
+
+                if (status & E1000_STATUS_FD) {
+                        *duplex = FULL_DUPLEX;
+                        DEBUGOUT("Full Duplex\n");
+                } else {
+                        *duplex = HALF_DUPLEX;
+                        DEBUGOUT(" Half Duplex\n");
+                }
+        } else {
+                DEBUGOUT("1000 Mbs, Full Duplex\n");
+                *speed = SPEED_1000;
+                *duplex = FULL_DUPLEX;
+        }
+
+        /* IGP01 PHY may advertise full duplex operation after speed downgrade even
+         * if it is operating at half duplex.  Here we set the duplex settings to
+         * match the duplex in the link partner's capabilities.
+         */
+        if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
+                ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+                        *duplex = HALF_DUPLEX;
+                else {
+                        ret_val =
+                            e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
+                        if (ret_val)
+                                return ret_val;
+                        if ((*speed == SPEED_100
+                             && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
+                            || (*speed == SPEED_10
+                                && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
+                                *duplex = HALF_DUPLEX;
+                }
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_wait_autoneg
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Blocks until autoneg completes or times out (~4.5 seconds)
+ */
 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 i;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_wait_autoneg");
-    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-
-    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-    for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Auto-Neg
-         * Complete bit to be set.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        if (phy_data & MII_SR_AUTONEG_COMPLETE) {
-            return E1000_SUCCESS;
-        }
-        msleep(100);
-    }
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 i;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_wait_autoneg");
+        DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+
+        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+        for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+                /* Read the MII Status Register and wait for Auto-Neg
+                 * Complete bit to be set.
+                 */
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+                if (phy_data & MII_SR_AUTONEG_COMPLETE) {
+                        return E1000_SUCCESS;
+                }
+                msleep(100);
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+/**
+ * e1000_raise_mdi_clk - Raises the Management Data Clock
+ * @hw: Struct containing variables accessed by shared code
+ * @ctrl: Device control register's current value
+ */
 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
 {
-    /* Raise the clock input to the Management Data Clock (by setting the MDC
-     * bit), and then delay 10 microseconds.
-     */
-    ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
-    E1000_WRITE_FLUSH();
-    udelay(10);
+        /* Raise the clock input to the Management Data Clock (by setting the MDC
+         * bit), and then delay 10 microseconds.
+         */
+        ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
+        E1000_WRITE_FLUSH();
+        udelay(10);
 }
 
-/******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+/**
+ * e1000_lower_mdi_clk - Lowers the Management Data Clock
+ * @hw: Struct containing variables accessed by shared code
+ * @ctrl: Device control register's current value
+ */
 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
 {
-    /* Lower the clock input to the Management Data Clock (by clearing the MDC
-     * bit), and then delay 10 microseconds.
-     */
-    ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
-    E1000_WRITE_FLUSH();
-    udelay(10);
+        /* Lower the clock input to the Management Data Clock (by clearing the MDC
+         * bit), and then delay 10 microseconds.
+         */
+        ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
+        E1000_WRITE_FLUSH();
+        udelay(10);
 }
 
-/******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
+/**
+ * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
+ * @hw: Struct containing variables accessed by shared code
+ * @data: Data to send out to the PHY
+ * @count: Number of bits to shift out
+ *
+ * Bits are shifted out in MSB to LSB order.
+ */
 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
 {
-    u32 ctrl;
-    u32 mask;
-
-    /* We need to shift "count" number of bits out to the PHY. So, the value
-     * in the "data" parameter will be shifted out to the PHY one bit at a
-     * time. In order to do this, "data" must be broken down into bits.
-     */
-    mask = 0x01;
-    mask <<= (count - 1);
-
-    ctrl = er32(CTRL);
-
-    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
-    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-
-    while (mask) {
-        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
-         * then raising and lowering the Management Data Clock. A "0" is
-         * shifted out to the PHY by setting the MDIO bit to "0" and then
-         * raising and lowering the clock.
-         */
-        if (data & mask)
-            ctrl |= E1000_CTRL_MDIO;
-        else
-            ctrl &= ~E1000_CTRL_MDIO;
-
-        ew32(CTRL, ctrl);
-        E1000_WRITE_FLUSH();
-
-        udelay(10);
-
-        e1000_raise_mdi_clk(hw, &ctrl);
-        e1000_lower_mdi_clk(hw, &ctrl);
-
-        mask = mask >> 1;
-    }
-}
-
-/******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order.
-******************************************************************************/
-static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
-{
-    u32 ctrl;
-    u16 data = 0;
-    u8 i;
-
-    /* In order to read a register from the PHY, we need to shift in a total
-     * of 18 bits from the PHY. The first two bit (turnaround) times are used
-     * to avoid contention on the MDIO pin when a read operation is performed.
-     * These two bits are ignored by us and thrown away. Bits are "shifted in"
-     * by raising the input to the Management Data Clock (setting the MDC bit),
-     * and then reading the value of the MDIO bit.
-     */
-    ctrl = er32(CTRL);
-
-    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
-    ctrl &= ~E1000_CTRL_MDIO_DIR;
-    ctrl &= ~E1000_CTRL_MDIO;
-
-    ew32(CTRL, ctrl);
-    E1000_WRITE_FLUSH();
-
-    /* Raise and Lower the clock before reading in the data. This accounts for
-     * the turnaround bits. The first clock occurred when we clocked out the
-     * last bit of the Register Address.
-     */
-    e1000_raise_mdi_clk(hw, &ctrl);
-    e1000_lower_mdi_clk(hw, &ctrl);
-
-    for (data = 0, i = 0; i < 16; i++) {
-        data = data << 1;
-        e1000_raise_mdi_clk(hw, &ctrl);
-        ctrl = er32(CTRL);
-        /* Check to see if we shifted in a "1". */
-        if (ctrl & E1000_CTRL_MDIO)
-            data |= 1;
-        e1000_lower_mdi_clk(hw, &ctrl);
-    }
-
-    e1000_raise_mdi_clk(hw, &ctrl);
-    e1000_lower_mdi_clk(hw, &ctrl);
-
-    return data;
-}
-
-static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
-{
-    u32 swfw_sync = 0;
-    u32 swmask = mask;
-    u32 fwmask = mask << 16;
-    s32 timeout = 200;
+        u32 ctrl;
+        u32 mask;
 
-    DEBUGFUNC("e1000_swfw_sync_acquire");
-
-    if (hw->swfwhw_semaphore_present)
-        return e1000_get_software_flag(hw);
+        /* We need to shift "count" number of bits out to the PHY. So, the value
+         * in the "data" parameter will be shifted out to the PHY one bit at a
+         * time. In order to do this, "data" must be broken down into bits.
+         */
+        mask = 0x01;
+        mask <<= (count - 1);
 
-    if (!hw->swfw_sync_present)
-        return e1000_get_hw_eeprom_semaphore(hw);
+        ctrl = er32(CTRL);
 
-    while (timeout) {
-            if (e1000_get_hw_eeprom_semaphore(hw))
-                return -E1000_ERR_SWFW_SYNC;
+        /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
+        ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
 
-            swfw_sync = er32(SW_FW_SYNC);
-            if (!(swfw_sync & (fwmask | swmask))) {
-                break;
-            }
+        while (mask) {
+                /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
+                 * then raising and lowering the Management Data Clock. A "0" is
+                 * shifted out to the PHY by setting the MDIO bit to "0" and then
+                 * raising and lowering the clock.
+                 */
+                if (data & mask)
+                        ctrl |= E1000_CTRL_MDIO;
+                else
+                        ctrl &= ~E1000_CTRL_MDIO;
 
-            /* firmware currently using resource (fwmask) */
-            /* or other software thread currently using resource (swmask) */
-            e1000_put_hw_eeprom_semaphore(hw);
-            mdelay(5);
-            timeout--;
-    }
+                ew32(CTRL, ctrl);
+                E1000_WRITE_FLUSH();
 
-    if (!timeout) {
-        DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
-        return -E1000_ERR_SWFW_SYNC;
-    }
+                udelay(10);
 
-    swfw_sync |= swmask;
-    ew32(SW_FW_SYNC, swfw_sync);
+                e1000_raise_mdi_clk(hw, &ctrl);
+                e1000_lower_mdi_clk(hw, &ctrl);
 
-    e1000_put_hw_eeprom_semaphore(hw);
-    return E1000_SUCCESS;
+                mask = mask >> 1;
+        }
 }
 
-static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
+/**
+ * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Bits are shifted in in MSB to LSB order.
+ */
+static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
 {
-    u32 swfw_sync;
-    u32 swmask = mask;
+        u32 ctrl;
+        u16 data = 0;
+        u8 i;
 
-    DEBUGFUNC("e1000_swfw_sync_release");
+        /* In order to read a register from the PHY, we need to shift in a total
+         * of 18 bits from the PHY. The first two bit (turnaround) times are used
+         * to avoid contention on the MDIO pin when a read operation is performed.
+         * These two bits are ignored by us and thrown away. Bits are "shifted in"
+         * by raising the input to the Management Data Clock (setting the MDC bit),
+         * and then reading the value of the MDIO bit.
+         */
+        ctrl = er32(CTRL);
 
-    if (hw->swfwhw_semaphore_present) {
-        e1000_release_software_flag(hw);
-        return;
-    }
+        /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
+        ctrl &= ~E1000_CTRL_MDIO_DIR;
+        ctrl &= ~E1000_CTRL_MDIO;
 
-    if (!hw->swfw_sync_present) {
-        e1000_put_hw_eeprom_semaphore(hw);
-        return;
-    }
+        ew32(CTRL, ctrl);
+        E1000_WRITE_FLUSH();
 
-    /* if (e1000_get_hw_eeprom_semaphore(hw))
-     *    return -E1000_ERR_SWFW_SYNC; */
-    while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
-        /* empty */
+        /* Raise and Lower the clock before reading in the data. This accounts for
+         * the turnaround bits. The first clock occurred when we clocked out the
+         * last bit of the Register Address.
+         */
+        e1000_raise_mdi_clk(hw, &ctrl);
+        e1000_lower_mdi_clk(hw, &ctrl);
+
+        for (data = 0, i = 0; i < 16; i++) {
+                data = data << 1;
+                e1000_raise_mdi_clk(hw, &ctrl);
+                ctrl = er32(CTRL);
+                /* Check to see if we shifted in a "1". */
+                if (ctrl & E1000_CTRL_MDIO)
+                        data |= 1;
+                e1000_lower_mdi_clk(hw, &ctrl);
+        }
 
-    swfw_sync = er32(SW_FW_SYNC);
-    swfw_sync &= ~swmask;
-    ew32(SW_FW_SYNC, swfw_sync);
+        e1000_raise_mdi_clk(hw, &ctrl);
+        e1000_lower_mdi_clk(hw, &ctrl);
 
-    e1000_put_hw_eeprom_semaphore(hw);
+        return data;
 }
 
-/*****************************************************************************
-* Reads the value from a PHY register, if the value is on a specific non zero
-* page, sets the page first.
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
+
+/**
+ * e1000_read_phy_reg - read a phy register
+ * @hw: Struct containing variables accessed by shared code
+ * @reg_addr: address of the PHY register to read
+ *
+ * Reads the value from a PHY register, if the value is on a specific non zero
+ * page, sets the page first.
+ */
 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
 {
-    u32 ret_val;
-    u16 swfw;
-
-    DEBUGFUNC("e1000_read_phy_reg");
-
-    if ((hw->mac_type == e1000_80003es2lan) &&
-        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
-        swfw = E1000_SWFW_PHY1_SM;
-    } else {
-        swfw = E1000_SWFW_PHY0_SM;
-    }
-    if (e1000_swfw_sync_acquire(hw, swfw))
-        return -E1000_ERR_SWFW_SYNC;
-
-    if ((hw->phy_type == e1000_phy_igp ||
-        hw->phy_type == e1000_phy_igp_3 ||
-        hw->phy_type == e1000_phy_igp_2) &&
-       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                         (u16)reg_addr);
-        if (ret_val) {
-            e1000_swfw_sync_release(hw, swfw);
-            return ret_val;
-        }
-    } else if (hw->phy_type == e1000_phy_gg82563) {
-        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
-            (hw->mac_type == e1000_80003es2lan)) {
-            /* Select Configuration Page */
-            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
-                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
-                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
-            } else {
-                /* Use Alternative Page Select register to access
-                 * registers 30 and 31
-                 */
-                ret_val = e1000_write_phy_reg_ex(hw,
-                                                 GG82563_PHY_PAGE_SELECT_ALT,
-                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
-            }
-
-            if (ret_val) {
-                e1000_swfw_sync_release(hw, swfw);
-                return ret_val;
-            }
-        }
-    }
-
-    ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-                                    phy_data);
-
-    e1000_swfw_sync_release(hw, swfw);
-    return ret_val;
+        u32 ret_val;
+
+        DEBUGFUNC("e1000_read_phy_reg");
+
+        if ((hw->phy_type == e1000_phy_igp) &&
+            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+                ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                 (u16) reg_addr);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                        phy_data);
+
+        return ret_val;
 }
 
 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                  u16 *phy_data)
 {
-    u32 i;
-    u32 mdic = 0;
-    const u32 phy_addr = 1;
-
-    DEBUGFUNC("e1000_read_phy_reg_ex");
-
-    if (reg_addr > MAX_PHY_REG_ADDRESS) {
-        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-        return -E1000_ERR_PARAM;
-    }
-
-    if (hw->mac_type > e1000_82543) {
-        /* Set up Op-code, Phy Address, and register address in the MDI
-         * Control register.  The MAC will take care of interfacing with the
-         * PHY to retrieve the desired data.
-         */
-        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                (E1000_MDIC_OP_READ));
-
-        ew32(MDIC, mdic);
-
-        /* Poll the ready bit to see if the MDI read completed */
-        for (i = 0; i < 64; i++) {
-            udelay(50);
-            mdic = er32(MDIC);
-            if (mdic & E1000_MDIC_READY) break;
-        }
-        if (!(mdic & E1000_MDIC_READY)) {
-            DEBUGOUT("MDI Read did not complete\n");
-            return -E1000_ERR_PHY;
-        }
-        if (mdic & E1000_MDIC_ERROR) {
-            DEBUGOUT("MDI Error\n");
-            return -E1000_ERR_PHY;
-        }
-        *phy_data = (u16)mdic;
-    } else {
-        /* We must first send a preamble through the MDIO pin to signal the
-         * beginning of an MII instruction.  This is done by sending 32
-         * consecutive "1" bits.
-         */
-        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-        /* Now combine the next few fields that are required for a read
-         * operation.  We use this method instead of calling the
-         * e1000_shift_out_mdi_bits routine five different times. The format of
-         * a MII read instruction consists of a shift out of 14 bits and is
-         * defined as follows:
-         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
-         * followed by a shift in of 18 bits.  This first two bits shifted in
-         * are TurnAround bits used to avoid contention on the MDIO pin when a
-         * READ operation is performed.  These two bits are thrown away
-         * followed by a shift in of 16 bits which contains the desired data.
-         */
-        mdic = ((reg_addr) | (phy_addr << 5) |
-                (PHY_OP_READ << 10) | (PHY_SOF << 12));
-
-        e1000_shift_out_mdi_bits(hw, mdic, 14);
-
-        /* Now that we've shifted out the read command to the MII, we need to
-         * "shift in" the 16-bit value (18 total bits) of the requested PHY
-         * register address.
-         */
-        *phy_data = e1000_shift_in_mdi_bits(hw);
-    }
-    return E1000_SUCCESS;
+        u32 i;
+        u32 mdic = 0;
+        const u32 phy_addr = 1;
+
+        DEBUGFUNC("e1000_read_phy_reg_ex");
+
+        if (reg_addr > MAX_PHY_REG_ADDRESS) {
+                DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+                return -E1000_ERR_PARAM;
+        }
+
+        if (hw->mac_type > e1000_82543) {
+                /* Set up Op-code, Phy Address, and register address in the MDI
+                 * Control register.  The MAC will take care of interfacing with the
+                 * PHY to retrieve the desired data.
+                 */
+                mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                        (E1000_MDIC_OP_READ));
+
+                ew32(MDIC, mdic);
+
+                /* Poll the ready bit to see if the MDI read completed */
+                for (i = 0; i < 64; i++) {
+                        udelay(50);
+                        mdic = er32(MDIC);
+                        if (mdic & E1000_MDIC_READY)
+                                break;
+                }
+                if (!(mdic & E1000_MDIC_READY)) {
+                        DEBUGOUT("MDI Read did not complete\n");
+                        return -E1000_ERR_PHY;
+                }
+                if (mdic & E1000_MDIC_ERROR) {
+                        DEBUGOUT("MDI Error\n");
+                        return -E1000_ERR_PHY;
+                }
+                *phy_data = (u16) mdic;
+        } else {
+                /* We must first send a preamble through the MDIO pin to signal the
+                 * beginning of an MII instruction.  This is done by sending 32
+                 * consecutive "1" bits.
+                 */
+                e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+                /* Now combine the next few fields that are required for a read
+                 * operation.  We use this method instead of calling the
+                 * e1000_shift_out_mdi_bits routine five different times. The format of
+                 * a MII read instruction consists of a shift out of 14 bits and is
+                 * defined as follows:
+                 *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
+                 * followed by a shift in of 18 bits.  This first two bits shifted in
+                 * are TurnAround bits used to avoid contention on the MDIO pin when a
+                 * READ operation is performed.  These two bits are thrown away
+                 * followed by a shift in of 16 bits which contains the desired data.
+                 */
+                mdic = ((reg_addr) | (phy_addr << 5) |
+                        (PHY_OP_READ << 10) | (PHY_SOF << 12));
+
+                e1000_shift_out_mdi_bits(hw, mdic, 14);
+
+                /* Now that we've shifted out the read command to the MII, we need to
+                 * "shift in" the 16-bit value (18 total bits) of the requested PHY
+                 * register address.
+                 */
+                *phy_data = e1000_shift_in_mdi_bits(hw);
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
+/**
+ * e1000_write_phy_reg - write a phy register
+ *
+ * @hw: Struct containing variables accessed by shared code
+ * @reg_addr: address of the PHY register to write
+ * @data: data to write to the PHY
+
+ * Writes a value to a PHY register
+ */
 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
 {
-    u32 ret_val;
-    u16 swfw;
-
-    DEBUGFUNC("e1000_write_phy_reg");
-
-    if ((hw->mac_type == e1000_80003es2lan) &&
-        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
-        swfw = E1000_SWFW_PHY1_SM;
-    } else {
-        swfw = E1000_SWFW_PHY0_SM;
-    }
-    if (e1000_swfw_sync_acquire(hw, swfw))
-        return -E1000_ERR_SWFW_SYNC;
-
-    if ((hw->phy_type == e1000_phy_igp ||
-        hw->phy_type == e1000_phy_igp_3 ||
-        hw->phy_type == e1000_phy_igp_2) &&
-       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                         (u16)reg_addr);
-        if (ret_val) {
-            e1000_swfw_sync_release(hw, swfw);
-            return ret_val;
-        }
-    } else if (hw->phy_type == e1000_phy_gg82563) {
-        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
-            (hw->mac_type == e1000_80003es2lan)) {
-            /* Select Configuration Page */
-            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
-                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
-                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
-            } else {
-                /* Use Alternative Page Select register to access
-                 * registers 30 and 31
-                 */
-                ret_val = e1000_write_phy_reg_ex(hw,
-                                                 GG82563_PHY_PAGE_SELECT_ALT,
-                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
-            }
-
-            if (ret_val) {
-                e1000_swfw_sync_release(hw, swfw);
-                return ret_val;
-            }
-        }
-    }
-
-    ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-                                     phy_data);
-
-    e1000_swfw_sync_release(hw, swfw);
-    return ret_val;
+        u32 ret_val;
+
+        DEBUGFUNC("e1000_write_phy_reg");
+
+        if ((hw->phy_type == e1000_phy_igp) &&
+            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+                ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                 (u16) reg_addr);
+                if (ret_val)
+                        return ret_val;
+        }
+
+        ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                         phy_data);
+
+        return ret_val;
 }
 
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                   u16 phy_data)
 {
-    u32 i;
-    u32 mdic = 0;
-    const u32 phy_addr = 1;
-
-    DEBUGFUNC("e1000_write_phy_reg_ex");
-
-    if (reg_addr > MAX_PHY_REG_ADDRESS) {
-        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-        return -E1000_ERR_PARAM;
-    }
-
-    if (hw->mac_type > e1000_82543) {
-        /* Set up Op-code, Phy Address, register address, and data intended
-         * for the PHY register in the MDI Control register.  The MAC will take
-         * care of interfacing with the PHY to send the desired data.
-         */
-        mdic = (((u32)phy_data) |
-                (reg_addr << E1000_MDIC_REG_SHIFT) |
-                (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                (E1000_MDIC_OP_WRITE));
-
-        ew32(MDIC, mdic);
-
-        /* Poll the ready bit to see if the MDI read completed */
-        for (i = 0; i < 641; i++) {
-            udelay(5);
-            mdic = er32(MDIC);
-            if (mdic & E1000_MDIC_READY) break;
-        }
-        if (!(mdic & E1000_MDIC_READY)) {
-            DEBUGOUT("MDI Write did not complete\n");
-            return -E1000_ERR_PHY;
-        }
-    } else {
-        /* We'll need to use the SW defined pins to shift the write command
-         * out to the PHY. We first send a preamble to the PHY to signal the
-         * beginning of the MII instruction.  This is done by sending 32
-         * consecutive "1" bits.
-         */
-        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-        /* Now combine the remaining required fields that will indicate a
-         * write operation. We use this method instead of calling the
-         * e1000_shift_out_mdi_bits routine for each field in the command. The
-         * format of a MII write instruction is as follows:
-         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
-         */
-        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
-                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
-        mdic <<= 16;
-        mdic |= (u32)phy_data;
-
-        e1000_shift_out_mdi_bits(hw, mdic, 32);
-    }
-
-    return E1000_SUCCESS;
-}
+        u32 i;
+        u32 mdic = 0;
+        const u32 phy_addr = 1;
 
-static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
-{
-    u32 reg_val;
-    u16 swfw;
-    DEBUGFUNC("e1000_read_kmrn_reg");
-
-    if ((hw->mac_type == e1000_80003es2lan) &&
-        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
-        swfw = E1000_SWFW_PHY1_SM;
-    } else {
-        swfw = E1000_SWFW_PHY0_SM;
-    }
-    if (e1000_swfw_sync_acquire(hw, swfw))
-        return -E1000_ERR_SWFW_SYNC;
-
-    /* Write register address */
-    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
-              E1000_KUMCTRLSTA_OFFSET) |
-              E1000_KUMCTRLSTA_REN;
-    ew32(KUMCTRLSTA, reg_val);
-    udelay(2);
-
-    /* Read the data returned */
-    reg_val = er32(KUMCTRLSTA);
-    *data = (u16)reg_val;
-
-    e1000_swfw_sync_release(hw, swfw);
-    return E1000_SUCCESS;
-}
+        DEBUGFUNC("e1000_write_phy_reg_ex");
 
-static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
-{
-    u32 reg_val;
-    u16 swfw;
-    DEBUGFUNC("e1000_write_kmrn_reg");
-
-    if ((hw->mac_type == e1000_80003es2lan) &&
-        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
-        swfw = E1000_SWFW_PHY1_SM;
-    } else {
-        swfw = E1000_SWFW_PHY0_SM;
-    }
-    if (e1000_swfw_sync_acquire(hw, swfw))
-        return -E1000_ERR_SWFW_SYNC;
-
-    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
-              E1000_KUMCTRLSTA_OFFSET) | data;
-    ew32(KUMCTRLSTA, reg_val);
-    udelay(2);
-
-    e1000_swfw_sync_release(hw, swfw);
-    return E1000_SUCCESS;
+        if (reg_addr > MAX_PHY_REG_ADDRESS) {
+                DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+                return -E1000_ERR_PARAM;
+        }
+
+        if (hw->mac_type > e1000_82543) {
+                /* Set up Op-code, Phy Address, register address, and data intended
+                 * for the PHY register in the MDI Control register.  The MAC will take
+                 * care of interfacing with the PHY to send the desired data.
+                 */
+                mdic = (((u32) phy_data) |
+                        (reg_addr << E1000_MDIC_REG_SHIFT) |
+                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                        (E1000_MDIC_OP_WRITE));
+
+                ew32(MDIC, mdic);
+
+                /* Poll the ready bit to see if the MDI read completed */
+                for (i = 0; i < 641; i++) {
+                        udelay(5);
+                        mdic = er32(MDIC);
+                        if (mdic & E1000_MDIC_READY)
+                                break;
+                }
+                if (!(mdic & E1000_MDIC_READY)) {
+                        DEBUGOUT("MDI Write did not complete\n");
+                        return -E1000_ERR_PHY;
+                }
+        } else {
+                /* We'll need to use the SW defined pins to shift the write command
+                 * out to the PHY. We first send a preamble to the PHY to signal the
+                 * beginning of the MII instruction.  This is done by sending 32
+                 * consecutive "1" bits.
+                 */
+                e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+                /* Now combine the remaining required fields that will indicate a
+                 * write operation. We use this method instead of calling the
+                 * e1000_shift_out_mdi_bits routine for each field in the command. The
+                 * format of a MII write instruction is as follows:
+                 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
+                 */
+                mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+                        (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+                mdic <<= 16;
+                mdic |= (u32) phy_data;
+
+                e1000_shift_out_mdi_bits(hw, mdic, 32);
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_phy_hw_reset - reset the phy, hardware style
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Returns the PHY to the power-on reset state
+ */
 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
 {
-    u32 ctrl, ctrl_ext;
-    u32 led_ctrl;
-    s32 ret_val;
-    u16 swfw;
-
-    DEBUGFUNC("e1000_phy_hw_reset");
-
-    /* In the case of the phy reset being blocked, it's not an error, we
-     * simply return success without performing the reset. */
-    ret_val = e1000_check_phy_reset_block(hw);
-    if (ret_val)
-        return E1000_SUCCESS;
-
-    DEBUGOUT("Resetting Phy...\n");
-
-    if (hw->mac_type > e1000_82543) {
-        if ((hw->mac_type == e1000_80003es2lan) &&
-            (er32(STATUS) & E1000_STATUS_FUNC_1)) {
-            swfw = E1000_SWFW_PHY1_SM;
-        } else {
-            swfw = E1000_SWFW_PHY0_SM;
-        }
-        if (e1000_swfw_sync_acquire(hw, swfw)) {
-            DEBUGOUT("Unable to acquire swfw sync\n");
-            return -E1000_ERR_SWFW_SYNC;
-        }
-        /* Read the device control register and assert the E1000_CTRL_PHY_RST
-         * bit. Then, take it out of reset.
-         * For pre-e1000_82571 hardware, we delay for 10ms between the assert
-         * and deassert.  For e1000_82571 hardware and later, we instead delay
-         * for 50us between and 10ms after the deassertion.
-         */
-        ctrl = er32(CTRL);
-        ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
-        E1000_WRITE_FLUSH();
-
-        if (hw->mac_type < e1000_82571)
-            msleep(10);
-        else
-            udelay(100);
-
-        ew32(CTRL, ctrl);
-        E1000_WRITE_FLUSH();
-
-        if (hw->mac_type >= e1000_82571)
-            mdelay(10);
-
-        e1000_swfw_sync_release(hw, swfw);
-    } else {
-        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
-         * bit to put the PHY into reset. Then, take it out of reset.
-         */
-        ctrl_ext = er32(CTRL_EXT);
-        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
-        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
-        ew32(CTRL_EXT, ctrl_ext);
-        E1000_WRITE_FLUSH();
-        msleep(10);
-        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
-        ew32(CTRL_EXT, ctrl_ext);
-        E1000_WRITE_FLUSH();
-    }
-    udelay(150);
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        /* Configure activity LED after PHY reset */
-        led_ctrl = er32(LEDCTL);
-        led_ctrl &= IGP_ACTIVITY_LED_MASK;
-        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-        ew32(LEDCTL, led_ctrl);
-    }
-
-    /* Wait for FW to finish PHY configuration. */
-    ret_val = e1000_get_phy_cfg_done(hw);
-    if (ret_val != E1000_SUCCESS)
-        return ret_val;
-    e1000_release_software_semaphore(hw);
-
-    if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
-        ret_val = e1000_init_lcd_from_nvm(hw);
-
-    return ret_val;
+        u32 ctrl, ctrl_ext;
+        u32 led_ctrl;
+        s32 ret_val;
+
+        DEBUGFUNC("e1000_phy_hw_reset");
+
+        DEBUGOUT("Resetting Phy...\n");
+
+        if (hw->mac_type > e1000_82543) {
+                /* Read the device control register and assert the E1000_CTRL_PHY_RST
+                 * bit. Then, take it out of reset.
+                 * For e1000 hardware, we delay for 10ms between the assert
+                 * and deassert.
+                 */
+                ctrl = er32(CTRL);
+                ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
+                E1000_WRITE_FLUSH();
+
+                msleep(10);
+
+                ew32(CTRL, ctrl);
+                E1000_WRITE_FLUSH();
+
+        } else {
+                /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
+                 * bit to put the PHY into reset. Then, take it out of reset.
+                 */
+                ctrl_ext = er32(CTRL_EXT);
+                ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
+                ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
+                ew32(CTRL_EXT, ctrl_ext);
+                E1000_WRITE_FLUSH();
+                msleep(10);
+                ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
+                ew32(CTRL_EXT, ctrl_ext);
+                E1000_WRITE_FLUSH();
+        }
+        udelay(150);
+
+        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+                /* Configure activity LED after PHY reset */
+                led_ctrl = er32(LEDCTL);
+                led_ctrl &= IGP_ACTIVITY_LED_MASK;
+                led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+                ew32(LEDCTL, led_ctrl);
+        }
+
+        /* Wait for FW to finish PHY configuration. */
+        ret_val = e1000_get_phy_cfg_done(hw);
+        if (ret_val != E1000_SUCCESS)
+                return ret_val;
+
+        return ret_val;
 }
 
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control register
-******************************************************************************/
+/**
+ * e1000_phy_reset - reset the phy to commit settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Resets the PHY
+ * Sets bit 15 of the MII Control register
+ */
 s32 e1000_phy_reset(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_phy_reset");
-
-    /* In the case of the phy reset being blocked, it's not an error, we
-     * simply return success without performing the reset. */
-    ret_val = e1000_check_phy_reset_block(hw);
-    if (ret_val)
-        return E1000_SUCCESS;
-
-    switch (hw->phy_type) {
-    case e1000_phy_igp:
-    case e1000_phy_igp_2:
-    case e1000_phy_igp_3:
-    case e1000_phy_ife:
-        ret_val = e1000_phy_hw_reset(hw);
-        if (ret_val)
-            return ret_val;
-        break;
-    default:
-        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= MII_CR_RESET;
-        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        udelay(1);
-        break;
-    }
-
-    if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
-        e1000_phy_init_script(hw);
-
-    return E1000_SUCCESS;
-}
+        s32 ret_val;
+        u16 phy_data;
 
-/******************************************************************************
-* Work-around for 82566 power-down: on D3 entry-
-* 1) disable gigabit link
-* 2) write VR power-down enable
-* 3) read it back
-* if successful continue, else issue LCD reset and repeat
-*
-* hw - struct containing variables accessed by shared code
-******************************************************************************/
-void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
-{
-    s32 reg;
-    u16 phy_data;
-    s32 retry = 0;
+        DEBUGFUNC("e1000_phy_reset");
 
-    DEBUGFUNC("e1000_phy_powerdown_workaround");
+        switch (hw->phy_type) {
+        case e1000_phy_igp:
+                ret_val = e1000_phy_hw_reset(hw);
+                if (ret_val)
+                        return ret_val;
+                break;
+        default:
+                ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-    if (hw->phy_type != e1000_phy_igp_3)
-        return;
+                phy_data |= MII_CR_RESET;
+                ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+                if (ret_val)
+                        return ret_val;
 
-    do {
-        /* Disable link */
-        reg = er32(PHY_CTRL);
-        ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
-                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+                udelay(1);
+                break;
+        }
 
-        /* Write VR power-down enable - bits 9:8 should be 10b */
-        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
-        phy_data |= (1 << 9);
-        phy_data &= ~(1 << 8);
-        e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
+        if (hw->phy_type == e1000_phy_igp)
+                e1000_phy_init_script(hw);
 
-        /* Read it back and test */
-        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
-        if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
-            break;
+        return E1000_SUCCESS;
+}
 
-        /* Issue PHY reset and repeat at most one more time */
-        reg = er32(CTRL);
-        ew32(CTRL, reg | E1000_CTRL_PHY_RST);
-        retry++;
-    } while (retry);
+/**
+ * e1000_detect_gig_phy - check the phy type
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Probes the expected PHY address for known PHY IDs
+ */
+static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
+{
+        s32 phy_init_status, ret_val;
+        u16 phy_id_high, phy_id_low;
+        bool match = false;
 
-    return;
+        DEBUGFUNC("e1000_detect_gig_phy");
 
-}
+        if (hw->phy_id != 0)
+                return E1000_SUCCESS;
 
-/******************************************************************************
-* Work-around for 82566 Kumeran PCS lock loss:
-* On link status change (i.e. PCI reset, speed change) and link is up and
-* speed is gigabit-
-* 0) if workaround is optionally disabled do nothing
-* 1) wait 1ms for Kumeran link to come up
-* 2) check Kumeran Diagnostic register PCS lock loss bit
-* 3) if not set the link is locked (all is good), otherwise...
-* 4) reset the PHY
-* 5) repeat up to 10 times
-* Note: this is only called for IGP3 copper when speed is 1gb.
-*
-* hw - struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    s32 reg;
-    s32 cnt;
-    u16 phy_data;
-
-    if (hw->kmrn_lock_loss_workaround_disabled)
-        return E1000_SUCCESS;
-
-    /* Make sure link is up before proceeding.  If not just return.
-     * Attempting this while link is negotiating fouled up link
-     * stability */
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-
-    if (phy_data & MII_SR_LINK_STATUS) {
-        for (cnt = 0; cnt < 10; cnt++) {
-            /* read once to clear */
-            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
-            if (ret_val)
-                return ret_val;
-            /* and again to get new status */
-            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            /* check for PCS lock */
-            if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
-                return E1000_SUCCESS;
-
-            /* Issue PHY reset */
-            e1000_phy_hw_reset(hw);
-            mdelay(5);
-        }
-        /* Disable GigE link negotiation */
-        reg = er32(PHY_CTRL);
-        ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
-                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
-
-        /* unable to acquire PCS lock */
-        return E1000_ERR_PHY;
-    }
-
-    return E1000_SUCCESS;
-}
+        /* Read the PHY ID Registers to identify which PHY is onboard. */
+        ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+        if (ret_val)
+                return ret_val;
 
-/******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
-{
-    s32 phy_init_status, ret_val;
-    u16 phy_id_high, phy_id_low;
-    bool match = false;
-
-    DEBUGFUNC("e1000_detect_gig_phy");
-
-    if (hw->phy_id != 0)
-        return E1000_SUCCESS;
-
-    /* The 82571 firmware may still be configuring the PHY.  In this
-     * case, we cannot access the PHY until the configuration is done.  So
-     * we explicitly set the PHY values. */
-    if (hw->mac_type == e1000_82571 ||
-        hw->mac_type == e1000_82572) {
-        hw->phy_id = IGP01E1000_I_PHY_ID;
-        hw->phy_type = e1000_phy_igp_2;
-        return E1000_SUCCESS;
-    }
-
-    /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
-     * around that forces PHY page 0 to be set or the reads fail.  The rest of
-     * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
-     * So for ESB-2 we need to have this set so our reads won't fail.  If the
-     * attached PHY is not a e1000_phy_gg82563, the routines below will figure
-     * this out as well. */
-    if (hw->mac_type == e1000_80003es2lan)
-        hw->phy_type = e1000_phy_gg82563;
-
-    /* Read the PHY ID Registers to identify which PHY is onboard. */
-    ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
-    if (ret_val)
-        return ret_val;
-
-    hw->phy_id = (u32)(phy_id_high << 16);
-    udelay(20);
-    ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
-    if (ret_val)
-        return ret_val;
-
-    hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
-    hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
-
-    switch (hw->mac_type) {
-    case e1000_82543:
-        if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
-        break;
-    case e1000_82544:
-        if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
-        break;
-    case e1000_82540:
-    case e1000_82545:
-    case e1000_82545_rev_3:
-    case e1000_82546:
-    case e1000_82546_rev_3:
-        if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
-        break;
-    case e1000_82541:
-    case e1000_82541_rev_2:
-    case e1000_82547:
-    case e1000_82547_rev_2:
-        if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
-        break;
-    case e1000_82573:
-        if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
-        break;
-    case e1000_80003es2lan:
-        if (hw->phy_id == GG82563_E_PHY_ID) match = true;
-        break;
-    case e1000_ich8lan:
-        if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
-        if (hw->phy_id == IFE_E_PHY_ID) match = true;
-        if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
-        if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
-        break;
-    default:
-        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
-        return -E1000_ERR_CONFIG;
-    }
-    phy_init_status = e1000_set_phy_type(hw);
-
-    if ((match) && (phy_init_status == E1000_SUCCESS)) {
-        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
-        return E1000_SUCCESS;
-    }
-    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
-    return -E1000_ERR_PHY;
+        hw->phy_id = (u32) (phy_id_high << 16);
+        udelay(20);
+        ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+        if (ret_val)
+                return ret_val;
+
+        hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
+        hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
+
+        switch (hw->mac_type) {
+        case e1000_82543:
+                if (hw->phy_id == M88E1000_E_PHY_ID)
+                        match = true;
+                break;
+        case e1000_82544:
+                if (hw->phy_id == M88E1000_I_PHY_ID)
+                        match = true;
+                break;
+        case e1000_82540:
+        case e1000_82545:
+        case e1000_82545_rev_3:
+        case e1000_82546:
+        case e1000_82546_rev_3:
+                if (hw->phy_id == M88E1011_I_PHY_ID)
+                        match = true;
+                break;
+        case e1000_82541:
+        case e1000_82541_rev_2:
+        case e1000_82547:
+        case e1000_82547_rev_2:
+                if (hw->phy_id == IGP01E1000_I_PHY_ID)
+                        match = true;
+                break;
+        default:
+                DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+                return -E1000_ERR_CONFIG;
+        }
+        phy_init_status = e1000_set_phy_type(hw);
+
+        if ((match) && (phy_init_status == E1000_SUCCESS)) {
+                DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
+                return E1000_SUCCESS;
+        }
+        DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
+        return -E1000_ERR_PHY;
 }
 
-/******************************************************************************
-* Resets the PHY's DSP
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_phy_reset_dsp - reset DSP
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Resets the PHY's DSP
+ */
 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    DEBUGFUNC("e1000_phy_reset_dsp");
-
-    do {
-        if (hw->phy_type != e1000_phy_gg82563) {
-            ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
-            if (ret_val) break;
-        }
-        ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
-        if (ret_val) break;
-        ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
-        if (ret_val) break;
-        ret_val = E1000_SUCCESS;
-    } while (0);
-
-    return ret_val;
+        s32 ret_val;
+        DEBUGFUNC("e1000_phy_reset_dsp");
+
+        do {
+                ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
+                if (ret_val)
+                        break;
+                ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
+                if (ret_val)
+                        break;
+                ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
+                if (ret_val)
+                        break;
+                ret_val = E1000_SUCCESS;
+        } while (0);
+
+        return ret_val;
 }
 
-/******************************************************************************
-* Get PHY information from various PHY registers for igp PHY only.
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_igp_get_info - get igp specific registers
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers for igp PHY only.
+ */
 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
                                   struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data, min_length, max_length, average;
-    e1000_rev_polarity polarity;
-
-    DEBUGFUNC("e1000_phy_igp_get_info");
-
-    /* The downshift status is checked only once, after link is established,
-     * and it stored in the hw->speed_downgraded parameter. */
-    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
-
-    /* IGP01E1000 does not need to support it. */
-    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
-
-    /* IGP01E1000 always correct polarity reversal */
-    phy_info->polarity_correction = e1000_polarity_reversal_enabled;
-
-    /* Check polarity status */
-    ret_val = e1000_check_polarity(hw, &polarity);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->cable_polarity = polarity;
-
-    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
-                          IGP01E1000_PSSR_MDIX_SHIFT);
-
-    if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-       IGP01E1000_PSSR_SPEED_1000MBPS) {
-        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
-                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
-                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
-                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
-                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-
-        /* Get cable length */
-        ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
-        if (ret_val)
-            return ret_val;
-
-        /* Translate to old method */
-        average = (max_length + min_length) / 2;
-
-        if (average <= e1000_igp_cable_length_50)
-            phy_info->cable_length = e1000_cable_length_50;
-        else if (average <= e1000_igp_cable_length_80)
-            phy_info->cable_length = e1000_cable_length_50_80;
-        else if (average <= e1000_igp_cable_length_110)
-            phy_info->cable_length = e1000_cable_length_80_110;
-        else if (average <= e1000_igp_cable_length_140)
-            phy_info->cable_length = e1000_cable_length_110_140;
-        else
-            phy_info->cable_length = e1000_cable_length_140;
-    }
-
-    return E1000_SUCCESS;
-}
+        s32 ret_val;
+        u16 phy_data, min_length, max_length, average;
+        e1000_rev_polarity polarity;
+
+        DEBUGFUNC("e1000_phy_igp_get_info");
+
+        /* The downshift status is checked only once, after link is established,
+         * and it stored in the hw->speed_downgraded parameter. */
+        phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
+
+        /* IGP01E1000 does not need to support it. */
+        phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
+
+        /* IGP01E1000 always correct polarity reversal */
+        phy_info->polarity_correction = e1000_polarity_reversal_enabled;
+
+        /* Check polarity status */
+        ret_val = e1000_check_polarity(hw, &polarity);
+        if (ret_val)
+                return ret_val;
+
+        phy_info->cable_polarity = polarity;
+
+        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        phy_info->mdix_mode =
+            (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
+                                 IGP01E1000_PSSR_MDIX_SHIFT);
+
+        if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+            IGP01E1000_PSSR_SPEED_1000MBPS) {
+                /* Local/Remote Receiver Information are only valid at 1000 Mbps */
+                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                                      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
+                    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+                phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                                       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
+                    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+
+                /* Get cable length */
+                ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
+                if (ret_val)
+                        return ret_val;
+
+                /* Translate to old method */
+                average = (max_length + min_length) / 2;
+
+                if (average <= e1000_igp_cable_length_50)
+                        phy_info->cable_length = e1000_cable_length_50;
+                else if (average <= e1000_igp_cable_length_80)
+                        phy_info->cable_length = e1000_cable_length_50_80;
+                else if (average <= e1000_igp_cable_length_110)
+                        phy_info->cable_length = e1000_cable_length_80_110;
+                else if (average <= e1000_igp_cable_length_140)
+                        phy_info->cable_length = e1000_cable_length_110_140;
+                else
+                        phy_info->cable_length = e1000_cable_length_140;
+        }
 
-/******************************************************************************
-* Get PHY information from various PHY registers for ife PHY only.
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
-static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
-                                  struct e1000_phy_info *phy_info)
-{
-    s32 ret_val;
-    u16 phy_data;
-    e1000_rev_polarity polarity;
-
-    DEBUGFUNC("e1000_phy_ife_get_info");
-
-    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
-    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
-
-    ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
-    phy_info->polarity_correction =
-                        ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
-                        IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
-                        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
-
-    if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
-        ret_val = e1000_check_polarity(hw, &polarity);
-        if (ret_val)
-            return ret_val;
-    } else {
-        /* Polarity is forced. */
-        polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
-                     IFE_PSC_FORCE_POLARITY_SHIFT) ?
-                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-    }
-    phy_info->cable_polarity = polarity;
-
-    ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->mdix_mode = (e1000_auto_x_mode)
-                     ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
-                     IFE_PMC_MDIX_MODE_SHIFT);
-
-    return E1000_SUCCESS;
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Get PHY information from various PHY registers fot m88 PHY only.
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_m88_get_info - get m88 specific registers
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers for m88 PHY only.
+ */
 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
                                   struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data;
-    e1000_rev_polarity polarity;
-
-    DEBUGFUNC("e1000_phy_m88_get_info");
-
-    /* The downshift status is checked only once, after link is established,
-     * and it stored in the hw->speed_downgraded parameter. */
-    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
-
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->extended_10bt_distance =
-        ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
-        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
-        e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
-
-    phy_info->polarity_correction =
-        ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
-        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
-        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
-
-    /* Check polarity status */
-    ret_val = e1000_check_polarity(hw, &polarity);
-    if (ret_val)
-        return ret_val;
-    phy_info->cable_polarity = polarity;
-
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
-                          M88E1000_PSSR_MDIX_SHIFT);
-
-    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
-        /* Cable Length Estimation and Local/Remote Receiver Information
-         * are only valid at 1000 Mbps.
-         */
-        if (hw->phy_type != e1000_phy_gg82563) {
-            phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
-        } else {
-            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
-        }
-
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
-                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
-                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
-                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
-                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-
-    }
-
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 phy_data;
+        e1000_rev_polarity polarity;
+
+        DEBUGFUNC("e1000_phy_m88_get_info");
+
+        /* The downshift status is checked only once, after link is established,
+         * and it stored in the hw->speed_downgraded parameter. */
+        phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
+
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        phy_info->extended_10bt_distance =
+            ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
+             M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
+            e1000_10bt_ext_dist_enable_lower :
+            e1000_10bt_ext_dist_enable_normal;
+
+        phy_info->polarity_correction =
+            ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
+             M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
+            e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
+
+        /* Check polarity status */
+        ret_val = e1000_check_polarity(hw, &polarity);
+        if (ret_val)
+                return ret_val;
+        phy_info->cable_polarity = polarity;
+
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        phy_info->mdix_mode =
+            (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
+                                 M88E1000_PSSR_MDIX_SHIFT);
+
+        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
+                /* Cable Length Estimation and Local/Remote Receiver Information
+                 * are only valid at 1000 Mbps.
+                 */
+                phy_info->cable_length =
+                    (e1000_cable_length) ((phy_data &
+                                           M88E1000_PSSR_CABLE_LENGTH) >>
+                                          M88E1000_PSSR_CABLE_LENGTH_SHIFT);
+
+                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                                      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
+                    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+                phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                                       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
+                    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Get PHY information from various PHY registers
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_get_info - request phy info
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers
+ */
 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_phy_get_info");
-
-    phy_info->cable_length = e1000_cable_length_undefined;
-    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
-    phy_info->cable_polarity = e1000_rev_polarity_undefined;
-    phy_info->downshift = e1000_downshift_undefined;
-    phy_info->polarity_correction = e1000_polarity_reversal_undefined;
-    phy_info->mdix_mode = e1000_auto_x_mode_undefined;
-    phy_info->local_rx = e1000_1000t_rx_status_undefined;
-    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
-
-    if (hw->media_type != e1000_media_type_copper) {
-        DEBUGOUT("PHY info is only valid for copper media\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
-        DEBUGOUT("PHY info is only valid if link is up\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    if (hw->phy_type == e1000_phy_igp ||
-        hw->phy_type == e1000_phy_igp_3 ||
-        hw->phy_type == e1000_phy_igp_2)
-        return e1000_phy_igp_get_info(hw, phy_info);
-    else if (hw->phy_type == e1000_phy_ife)
-        return e1000_phy_ife_get_info(hw, phy_info);
-    else
-        return e1000_phy_m88_get_info(hw, phy_info);
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_phy_get_info");
+
+        phy_info->cable_length = e1000_cable_length_undefined;
+        phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
+        phy_info->cable_polarity = e1000_rev_polarity_undefined;
+        phy_info->downshift = e1000_downshift_undefined;
+        phy_info->polarity_correction = e1000_polarity_reversal_undefined;
+        phy_info->mdix_mode = e1000_auto_x_mode_undefined;
+        phy_info->local_rx = e1000_1000t_rx_status_undefined;
+        phy_info->remote_rx = e1000_1000t_rx_status_undefined;
+
+        if (hw->media_type != e1000_media_type_copper) {
+                DEBUGOUT("PHY info is only valid for copper media\n");
+                return -E1000_ERR_CONFIG;
+        }
+
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+        if (ret_val)
+                return ret_val;
+
+        if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
+                DEBUGOUT("PHY info is only valid if link is up\n");
+                return -E1000_ERR_CONFIG;
+        }
+
+        if (hw->phy_type == e1000_phy_igp)
+                return e1000_phy_igp_get_info(hw, phy_info);
+        else
+                return e1000_phy_m88_get_info(hw, phy_info);
 }
 
 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_validate_mdi_settings");
-
-    if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
-        DEBUGOUT("Invalid MDI setting detected\n");
-        hw->mdix = 1;
-        return -E1000_ERR_CONFIG;
-    }
-    return E1000_SUCCESS;
-}
+        DEBUGFUNC("e1000_validate_mdi_settings");
 
+        if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
+                DEBUGOUT("Invalid MDI setting detected\n");
+                hw->mdix = 1;
+                return -E1000_ERR_CONFIG;
+        }
+        return E1000_SUCCESS;
+}
 
-/******************************************************************************
- * Sets up eeprom variables in the hw struct.  Must be called after mac_type
- * is configured.  Additionally, if this is ICH8, the flash controller GbE
- * registers must be mapped, or this will crash.
+/**
+ * e1000_init_eeprom_params - initialize sw eeprom vars
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Sets up eeprom variables in the hw struct.  Must be called after mac_type
+ * is configured.
+ */
 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd = er32(EECD);
-    s32 ret_val = E1000_SUCCESS;
-    u16 eeprom_size;
-
-    DEBUGFUNC("e1000_init_eeprom_params");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        eeprom->type = e1000_eeprom_microwire;
-        eeprom->word_size = 64;
-        eeprom->opcode_bits = 3;
-        eeprom->address_bits = 6;
-        eeprom->delay_usec = 50;
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82540:
-    case e1000_82545:
-    case e1000_82545_rev_3:
-    case e1000_82546:
-    case e1000_82546_rev_3:
-        eeprom->type = e1000_eeprom_microwire;
-        eeprom->opcode_bits = 3;
-        eeprom->delay_usec = 50;
-        if (eecd & E1000_EECD_SIZE) {
-            eeprom->word_size = 256;
-            eeprom->address_bits = 8;
-        } else {
-            eeprom->word_size = 64;
-            eeprom->address_bits = 6;
-        }
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82541:
-    case e1000_82541_rev_2:
-    case e1000_82547:
-    case e1000_82547_rev_2:
-        if (eecd & E1000_EECD_TYPE) {
-            eeprom->type = e1000_eeprom_spi;
-            eeprom->opcode_bits = 8;
-            eeprom->delay_usec = 1;
-            if (eecd & E1000_EECD_ADDR_BITS) {
-                eeprom->page_size = 32;
-                eeprom->address_bits = 16;
-            } else {
-                eeprom->page_size = 8;
-                eeprom->address_bits = 8;
-            }
-        } else {
-            eeprom->type = e1000_eeprom_microwire;
-            eeprom->opcode_bits = 3;
-            eeprom->delay_usec = 50;
-            if (eecd & E1000_EECD_ADDR_BITS) {
-                eeprom->word_size = 256;
-                eeprom->address_bits = 8;
-            } else {
-                eeprom->word_size = 64;
-                eeprom->address_bits = 6;
-            }
-        }
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82571:
-    case e1000_82572:
-        eeprom->type = e1000_eeprom_spi;
-        eeprom->opcode_bits = 8;
-        eeprom->delay_usec = 1;
-        if (eecd & E1000_EECD_ADDR_BITS) {
-            eeprom->page_size = 32;
-            eeprom->address_bits = 16;
-        } else {
-            eeprom->page_size = 8;
-            eeprom->address_bits = 8;
-        }
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82573:
-        eeprom->type = e1000_eeprom_spi;
-        eeprom->opcode_bits = 8;
-        eeprom->delay_usec = 1;
-        if (eecd & E1000_EECD_ADDR_BITS) {
-            eeprom->page_size = 32;
-            eeprom->address_bits = 16;
-        } else {
-            eeprom->page_size = 8;
-            eeprom->address_bits = 8;
-        }
-        eeprom->use_eerd = true;
-        eeprom->use_eewr = true;
-        if (!e1000_is_onboard_nvm_eeprom(hw)) {
-            eeprom->type = e1000_eeprom_flash;
-            eeprom->word_size = 2048;
-
-            /* Ensure that the Autonomous FLASH update bit is cleared due to
-             * Flash update issue on parts which use a FLASH for NVM. */
-            eecd &= ~E1000_EECD_AUPDEN;
-            ew32(EECD, eecd);
-        }
-        break;
-    case e1000_80003es2lan:
-        eeprom->type = e1000_eeprom_spi;
-        eeprom->opcode_bits = 8;
-        eeprom->delay_usec = 1;
-        if (eecd & E1000_EECD_ADDR_BITS) {
-            eeprom->page_size = 32;
-            eeprom->address_bits = 16;
-        } else {
-            eeprom->page_size = 8;
-            eeprom->address_bits = 8;
-        }
-        eeprom->use_eerd = true;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_ich8lan:
-        {
-        s32  i = 0;
-        u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
-
-        eeprom->type = e1000_eeprom_ich8;
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        eeprom->word_size = E1000_SHADOW_RAM_WORDS;
-
-        /* Zero the shadow RAM structure. But don't load it from NVM
-         * so as to save time for driver init */
-        if (hw->eeprom_shadow_ram != NULL) {
-            for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-                hw->eeprom_shadow_ram[i].modified = false;
-                hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
-            }
-        }
-
-        hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
-                              ICH_FLASH_SECTOR_SIZE;
-
-        hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
-        hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
-        hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
-        hw->flash_bank_size /= 2 * sizeof(u16);
-
-        break;
-        }
-    default:
-        break;
-    }
-
-    if (eeprom->type == e1000_eeprom_spi) {
-        /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
-         * 32KB (incremented by powers of 2).
-         */
-        if (hw->mac_type <= e1000_82547_rev_2) {
-            /* Set to default value for initial eeprom read. */
-            eeprom->word_size = 64;
-            ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
-            if (ret_val)
-                return ret_val;
-            eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
-            /* 256B eeprom size was not supported in earlier hardware, so we
-             * bump eeprom_size up one to ensure that "1" (which maps to 256B)
-             * is never the result used in the shifting logic below. */
-            if (eeprom_size)
-                eeprom_size++;
-        } else {
-            eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-                          E1000_EECD_SIZE_EX_SHIFT);
-        }
-
-        eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
-    }
-    return ret_val;
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 eecd = er32(EECD);
+        s32 ret_val = E1000_SUCCESS;
+        u16 eeprom_size;
+
+        DEBUGFUNC("e1000_init_eeprom_params");
+
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+        case e1000_82544:
+                eeprom->type = e1000_eeprom_microwire;
+                eeprom->word_size = 64;
+                eeprom->opcode_bits = 3;
+                eeprom->address_bits = 6;
+                eeprom->delay_usec = 50;
+                break;
+        case e1000_82540:
+        case e1000_82545:
+        case e1000_82545_rev_3:
+        case e1000_82546:
+        case e1000_82546_rev_3:
+                eeprom->type = e1000_eeprom_microwire;
+                eeprom->opcode_bits = 3;
+                eeprom->delay_usec = 50;
+                if (eecd & E1000_EECD_SIZE) {
+                        eeprom->word_size = 256;
+                        eeprom->address_bits = 8;
+                } else {
+                        eeprom->word_size = 64;
+                        eeprom->address_bits = 6;
+                }
+                break;
+        case e1000_82541:
+        case e1000_82541_rev_2:
+        case e1000_82547:
+        case e1000_82547_rev_2:
+                if (eecd & E1000_EECD_TYPE) {
+                        eeprom->type = e1000_eeprom_spi;
+                        eeprom->opcode_bits = 8;
+                        eeprom->delay_usec = 1;
+                        if (eecd & E1000_EECD_ADDR_BITS) {
+                                eeprom->page_size = 32;
+                                eeprom->address_bits = 16;
+                        } else {
+                                eeprom->page_size = 8;
+                                eeprom->address_bits = 8;
+                        }
+                } else {
+                        eeprom->type = e1000_eeprom_microwire;
+                        eeprom->opcode_bits = 3;
+                        eeprom->delay_usec = 50;
+                        if (eecd & E1000_EECD_ADDR_BITS) {
+                                eeprom->word_size = 256;
+                                eeprom->address_bits = 8;
+                        } else {
+                                eeprom->word_size = 64;
+                                eeprom->address_bits = 6;
+                        }
+                }
+                break;
+        default:
+                break;
+        }
+
+        if (eeprom->type == e1000_eeprom_spi) {
+                /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
+                 * 32KB (incremented by powers of 2).
+                 */
+                /* Set to default value for initial eeprom read. */
+                eeprom->word_size = 64;
+                ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
+                if (ret_val)
+                        return ret_val;
+                eeprom_size =
+                    (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
+                /* 256B eeprom size was not supported in earlier hardware, so we
+                 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
+                 * is never the result used in the shifting logic below. */
+                if (eeprom_size)
+                        eeprom_size++;
+
+                eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
+        }
+        return ret_val;
 }
 
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
+/**
+ * e1000_raise_ee_clk - Raises the EEPROM's clock input.
+ * @hw: Struct containing variables accessed by shared code
+ * @eecd: EECD's current value
+ */
 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
 {
-    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
-     * wait <delay> microseconds.
-     */
-    *eecd = *eecd | E1000_EECD_SK;
-    ew32(EECD, *eecd);
-    E1000_WRITE_FLUSH();
-    udelay(hw->eeprom.delay_usec);
+        /* Raise the clock input to the EEPROM (by setting the SK bit), and then
+         * wait <delay> microseconds.
+         */
+        *eecd = *eecd | E1000_EECD_SK;
+        ew32(EECD, *eecd);
+        E1000_WRITE_FLUSH();
+        udelay(hw->eeprom.delay_usec);
 }
 
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
+/**
+ * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
+ * @hw: Struct containing variables accessed by shared code
+ * @eecd: EECD's current value
+ */
 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
 {
-    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
-     * wait 50 microseconds.
-     */
-    *eecd = *eecd & ~E1000_EECD_SK;
-    ew32(EECD, *eecd);
-    E1000_WRITE_FLUSH();
-    udelay(hw->eeprom.delay_usec);
+        /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
+         * wait 50 microseconds.
+         */
+        *eecd = *eecd & ~E1000_EECD_SK;
+        ew32(EECD, *eecd);
+        E1000_WRITE_FLUSH();
+        udelay(hw->eeprom.delay_usec);
 }
 
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
+/**
+ * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @data: data to send to the EEPROM
+ * @count: number of bits to shift out
+ */
 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-    u32 mask;
-
-    /* We need to shift "count" bits out to the EEPROM. So, value in the
-     * "data" parameter will be shifted out to the EEPROM one bit at a time.
-     * In order to do this, "data" must be broken down into bits.
-     */
-    mask = 0x01 << (count - 1);
-    eecd = er32(EECD);
-    if (eeprom->type == e1000_eeprom_microwire) {
-        eecd &= ~E1000_EECD_DO;
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        eecd |= E1000_EECD_DO;
-    }
-    do {
-        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-         * and then raising and then lowering the clock (the SK bit controls
-         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-         * by setting "DI" to "0" and then raising and then lowering the clock.
-         */
-        eecd &= ~E1000_EECD_DI;
-
-        if (data & mask)
-            eecd |= E1000_EECD_DI;
-
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-
-        udelay(eeprom->delay_usec);
-
-        e1000_raise_ee_clk(hw, &eecd);
-        e1000_lower_ee_clk(hw, &eecd);
-
-        mask = mask >> 1;
-
-    } while (mask);
-
-    /* We leave the "DI" bit set to "0" when we leave this routine. */
-    eecd &= ~E1000_EECD_DI;
-    ew32(EECD, eecd);
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 eecd;
+        u32 mask;
+
+        /* We need to shift "count" bits out to the EEPROM. So, value in the
+         * "data" parameter will be shifted out to the EEPROM one bit at a time.
+         * In order to do this, "data" must be broken down into bits.
+         */
+        mask = 0x01 << (count - 1);
+        eecd = er32(EECD);
+        if (eeprom->type == e1000_eeprom_microwire) {
+                eecd &= ~E1000_EECD_DO;
+        } else if (eeprom->type == e1000_eeprom_spi) {
+                eecd |= E1000_EECD_DO;
+        }
+        do {
+                /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+                 * and then raising and then lowering the clock (the SK bit controls
+                 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+                 * by setting "DI" to "0" and then raising and then lowering the clock.
+                 */
+                eecd &= ~E1000_EECD_DI;
+
+                if (data & mask)
+                        eecd |= E1000_EECD_DI;
+
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+
+                udelay(eeprom->delay_usec);
+
+                e1000_raise_ee_clk(hw, &eecd);
+                e1000_lower_ee_clk(hw, &eecd);
+
+                mask = mask >> 1;
+
+        } while (mask);
+
+        /* We leave the "DI" bit set to "0" when we leave this routine. */
+        eecd &= ~E1000_EECD_DI;
+        ew32(EECD, eecd);
 }
 
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
+ * @hw: Struct containing variables accessed by shared code
+ * @count: number of bits to shift in
+ */
 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
 {
-    u32 eecd;
-    u32 i;
-    u16 data;
+        u32 eecd;
+        u32 i;
+        u16 data;
 
-    /* In order to read a register from the EEPROM, we need to shift 'count'
-     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
-     * input to the EEPROM (setting the SK bit), and then reading the value of
-     * the "DO" bit.  During this "shifting in" process the "DI" bit should
-     * always be clear.
-     */
+        /* In order to read a register from the EEPROM, we need to shift 'count'
+         * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+         * input to the EEPROM (setting the SK bit), and then reading the value of
+         * the "DO" bit.  During this "shifting in" process the "DI" bit should
+         * always be clear.
+         */
 
-    eecd = er32(EECD);
+        eecd = er32(EECD);
 
-    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-    data = 0;
+        eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+        data = 0;
 
-    for (i = 0; i < count; i++) {
-        data = data << 1;
-        e1000_raise_ee_clk(hw, &eecd);
+        for (i = 0; i < count; i++) {
+                data = data << 1;
+                e1000_raise_ee_clk(hw, &eecd);
 
-        eecd = er32(EECD);
+                eecd = er32(EECD);
 
-        eecd &= ~(E1000_EECD_DI);
-        if (eecd & E1000_EECD_DO)
-            data |= 1;
+                eecd &= ~(E1000_EECD_DI);
+                if (eecd & E1000_EECD_DO)
+                        data |= 1;
 
-        e1000_lower_ee_clk(hw, &eecd);
-    }
+                e1000_lower_ee_clk(hw, &eecd);
+        }
 
-    return data;
+        return data;
 }
 
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_acquire_eeprom - Prepares EEPROM for access
+ * @hw: Struct containing variables accessed by shared code
  *
  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
+ */
 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd, i=0;
-
-    DEBUGFUNC("e1000_acquire_eeprom");
-
-    if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
-        return -E1000_ERR_SWFW_SYNC;
-    eecd = er32(EECD);
-
-    if (hw->mac_type != e1000_82573) {
-        /* Request EEPROM Access */
-        if (hw->mac_type > e1000_82544) {
-            eecd |= E1000_EECD_REQ;
-            ew32(EECD, eecd);
-            eecd = er32(EECD);
-            while ((!(eecd & E1000_EECD_GNT)) &&
-                  (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
-                i++;
-                udelay(5);
-                eecd = er32(EECD);
-            }
-            if (!(eecd & E1000_EECD_GNT)) {
-                eecd &= ~E1000_EECD_REQ;
-                ew32(EECD, eecd);
-                DEBUGOUT("Could not acquire EEPROM grant\n");
-                e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
-                return -E1000_ERR_EEPROM;
-            }
-        }
-    }
-
-    /* Setup EEPROM for Read/Write */
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        /* Clear SK and DI */
-        eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
-        ew32(EECD, eecd);
-
-        /* Set CS */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        /* Clear SK and CS */
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-        ew32(EECD, eecd);
-        udelay(1);
-    }
-
-    return E1000_SUCCESS;
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 eecd, i = 0;
+
+        DEBUGFUNC("e1000_acquire_eeprom");
+
+        eecd = er32(EECD);
+
+        /* Request EEPROM Access */
+        if (hw->mac_type > e1000_82544) {
+                eecd |= E1000_EECD_REQ;
+                ew32(EECD, eecd);
+                eecd = er32(EECD);
+                while ((!(eecd & E1000_EECD_GNT)) &&
+                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
+                        i++;
+                        udelay(5);
+                        eecd = er32(EECD);
+                }
+                if (!(eecd & E1000_EECD_GNT)) {
+                        eecd &= ~E1000_EECD_REQ;
+                        ew32(EECD, eecd);
+                        DEBUGOUT("Could not acquire EEPROM grant\n");
+                        return -E1000_ERR_EEPROM;
+                }
+        }
+
+        /* Setup EEPROM for Read/Write */
+
+        if (eeprom->type == e1000_eeprom_microwire) {
+                /* Clear SK and DI */
+                eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
+                ew32(EECD, eecd);
+
+                /* Set CS */
+                eecd |= E1000_EECD_CS;
+                ew32(EECD, eecd);
+        } else if (eeprom->type == e1000_eeprom_spi) {
+                /* Clear SK and CS */
+                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+                ew32(EECD, eecd);
+                udelay(1);
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_standby_eeprom - Returns EEPROM to a "standby" state
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_standby_eeprom(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-
-    eecd = er32(EECD);
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Clock high */
-        eecd |= E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Select EEPROM */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Clock low */
-        eecd &= ~E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        /* Toggle CS to flush commands */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-        eecd &= ~E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-    }
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 eecd;
+
+        eecd = er32(EECD);
+
+        if (eeprom->type == e1000_eeprom_microwire) {
+                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+
+                /* Clock high */
+                eecd |= E1000_EECD_SK;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+
+                /* Select EEPROM */
+                eecd |= E1000_EECD_CS;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+
+                /* Clock low */
+                eecd &= ~E1000_EECD_SK;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+        } else if (eeprom->type == e1000_eeprom_spi) {
+                /* Toggle CS to flush commands */
+                eecd |= E1000_EECD_CS;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+                eecd &= ~E1000_EECD_CS;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(eeprom->delay_usec);
+        }
 }
 
-/******************************************************************************
- * Terminates a command by inverting the EEPROM's chip select pin
+/**
+ * e1000_release_eeprom - drop chip select
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Terminates a command by inverting the EEPROM's chip select pin
+ */
 static void e1000_release_eeprom(struct e1000_hw *hw)
 {
-    u32 eecd;
-
-    DEBUGFUNC("e1000_release_eeprom");
+        u32 eecd;
 
-    eecd = er32(EECD);
+        DEBUGFUNC("e1000_release_eeprom");
 
-    if (hw->eeprom.type == e1000_eeprom_spi) {
-        eecd |= E1000_EECD_CS;  /* Pull CS high */
-        eecd &= ~E1000_EECD_SK; /* Lower SCK */
+        eecd = er32(EECD);
 
-        ew32(EECD, eecd);
+        if (hw->eeprom.type == e1000_eeprom_spi) {
+                eecd |= E1000_EECD_CS;  /* Pull CS high */
+                eecd &= ~E1000_EECD_SK; /* Lower SCK */
 
-        udelay(hw->eeprom.delay_usec);
-    } else if (hw->eeprom.type == e1000_eeprom_microwire) {
-        /* cleanup eeprom */
+                ew32(EECD, eecd);
 
-        /* CS on Microwire is active-high */
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+                udelay(hw->eeprom.delay_usec);
+        } else if (hw->eeprom.type == e1000_eeprom_microwire) {
+                /* cleanup eeprom */
 
-        ew32(EECD, eecd);
+                /* CS on Microwire is active-high */
+                eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 
-        /* Rising edge of clock */
-        eecd |= E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(hw->eeprom.delay_usec);
+                ew32(EECD, eecd);
 
-        /* Falling edge of clock */
-        eecd &= ~E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(hw->eeprom.delay_usec);
-    }
+                /* Rising edge of clock */
+                eecd |= E1000_EECD_SK;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(hw->eeprom.delay_usec);
 
-    /* Stop requesting EEPROM access */
-    if (hw->mac_type > e1000_82544) {
-        eecd &= ~E1000_EECD_REQ;
-        ew32(EECD, eecd);
-    }
+                /* Falling edge of clock */
+                eecd &= ~E1000_EECD_SK;
+                ew32(EECD, eecd);
+                E1000_WRITE_FLUSH();
+                udelay(hw->eeprom.delay_usec);
+        }
 
-    e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
+        /* Stop requesting EEPROM access */
+        if (hw->mac_type > e1000_82544) {
+                eecd &= ~E1000_EECD_REQ;
+                ew32(EECD, eecd);
+        }
 }
 
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 {
-    u16 retry_count = 0;
-    u8 spi_stat_reg;
-
-    DEBUGFUNC("e1000_spi_eeprom_ready");
-
-    /* Read "Status Register" repeatedly until the LSB is cleared.  The
-     * EEPROM will signal that the command has been completed by clearing
-     * bit 0 of the internal status register.  If it's not cleared within
-     * 5 milliseconds, then error out.
-     */
-    retry_count = 0;
-    do {
-        e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
-                                hw->eeprom.opcode_bits);
-        spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
-        if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
-            break;
-
-        udelay(5);
-        retry_count += 5;
-
-        e1000_standby_eeprom(hw);
-    } while (retry_count < EEPROM_MAX_RETRY_SPI);
-
-    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
-     * only 0-5mSec on 5V devices)
-     */
-    if (retry_count >= EEPROM_MAX_RETRY_SPI) {
-        DEBUGOUT("SPI EEPROM Status error\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
-{
-    s32 ret;
-    spin_lock(&e1000_eeprom_lock);
-    ret = e1000_do_read_eeprom(hw, offset, words, data);
-    spin_unlock(&e1000_eeprom_lock);
-    return ret;
-}
-
-static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
-{
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 i = 0;
-
-    DEBUGFUNC("e1000_read_eeprom");
-
-    /* If eeprom is not yet detected, do so now */
-    if (eeprom->word_size == 0)
-        e1000_init_eeprom_params(hw);
-
-    /* A check for invalid values:  offset too large, too many words, and not
-     * enough words.
-     */
-    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
-       (words == 0)) {
-        DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
-        return -E1000_ERR_EEPROM;
-    }
-
-    /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
-     * directly. In this case, we need to acquire the EEPROM so that
-     * FW or other port software does not interrupt.
-     */
-    if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
-        /* Prepare the EEPROM for bit-bang reading */
-        if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-            return -E1000_ERR_EEPROM;
-    }
-
-    /* Eerd register EEPROM access requires no eeprom aquire/release */
-    if (eeprom->use_eerd)
-        return e1000_read_eeprom_eerd(hw, offset, words, data);
-
-    /* ICH EEPROM access is done via the ICH flash controller */
-    if (eeprom->type == e1000_eeprom_ich8)
-        return e1000_read_eeprom_ich8(hw, offset, words, data);
-
-    /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
-     * acquired the EEPROM at this point, so any returns should relase it */
-    if (eeprom->type == e1000_eeprom_spi) {
-        u16 word_in;
-        u8 read_opcode = EEPROM_READ_OPCODE_SPI;
-
-        if (e1000_spi_eeprom_ready(hw)) {
-            e1000_release_eeprom(hw);
-            return -E1000_ERR_EEPROM;
-        }
-
-        e1000_standby_eeprom(hw);
-
-        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if ((eeprom->address_bits == 8) && (offset >= 128))
-            read_opcode |= EEPROM_A8_OPCODE_SPI;
-
-        /* Send the READ command (opcode + addr)  */
-        e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
-        e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
-
-        /* Read the data.  The address of the eeprom internally increments with
-         * each byte (spi) being read, saving on the overhead of eeprom setup
-         * and tear-down.  The address counter will roll over if reading beyond
-         * the size of the eeprom, thus allowing the entire memory to be read
-         * starting from any offset. */
-        for (i = 0; i < words; i++) {
-            word_in = e1000_shift_in_ee_bits(hw, 16);
-            data[i] = (word_in >> 8) | (word_in << 8);
-        }
-    } else if (eeprom->type == e1000_eeprom_microwire) {
-        for (i = 0; i < words; i++) {
-            /* Send the READ command (opcode + addr)  */
-            e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
-                                    eeprom->opcode_bits);
-            e1000_shift_out_ee_bits(hw, (u16)(offset + i),
-                                    eeprom->address_bits);
-
-            /* Read the data.  For microwire, each word requires the overhead
-             * of eeprom setup and tear-down. */
-            data[i] = e1000_shift_in_ee_bits(hw, 16);
-            e1000_standby_eeprom(hw);
-        }
-    }
-
-    /* End this read operation */
-    e1000_release_eeprom(hw);
-
-    return E1000_SUCCESS;
-}
+        u16 retry_count = 0;
+        u8 spi_stat_reg;
 
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM using the EERD register.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data)
-{
-    u32 i, eerd = 0;
-    s32 error = 0;
+        DEBUGFUNC("e1000_spi_eeprom_ready");
 
-    for (i = 0; i < words; i++) {
-        eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
-                         E1000_EEPROM_RW_REG_START;
+        /* Read "Status Register" repeatedly until the LSB is cleared.  The
+         * EEPROM will signal that the command has been completed by clearing
+         * bit 0 of the internal status register.  If it's not cleared within
+         * 5 milliseconds, then error out.
+         */
+        retry_count = 0;
+        do {
+                e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
+                                        hw->eeprom.opcode_bits);
+                spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
+                if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+                        break;
 
-        ew32(EERD, eerd);
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
+                udelay(5);
+                retry_count += 5;
 
-        if (error) {
-            break;
-        }
-        data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
+                e1000_standby_eeprom(hw);
+        } while (retry_count < EEPROM_MAX_RETRY_SPI);
 
-    }
+        /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
+         * only 0-5mSec on 5V devices)
+         */
+        if (retry_count >= EEPROM_MAX_RETRY_SPI) {
+                DEBUGOUT("SPI EEPROM Status error\n");
+                return -E1000_ERR_EEPROM;
+        }
 
-    return error;
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Writes a 16 bit word from the EEPROM using the EEWR register.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data)
+/**
+ * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset of  word in the EEPROM to read
+ * @data: word read from the EEPROM
+ * @words: number of words to read
+ */
+s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 {
-    u32    register_value = 0;
-    u32    i              = 0;
-    s32     error          = 0;
-
-    if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
-        return -E1000_ERR_SWFW_SYNC;
-
-    for (i = 0; i < words; i++) {
-        register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
-                         ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
-                         E1000_EEPROM_RW_REG_START;
-
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
-        if (error) {
-            break;
-        }
-
-        ew32(EEWR, register_value);
-
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
-
-        if (error) {
-            break;
-        }
-    }
-
-    e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
-    return error;
+        s32 ret;
+        spin_lock(&e1000_eeprom_lock);
+        ret = e1000_do_read_eeprom(hw, offset, words, data);
+        spin_unlock(&e1000_eeprom_lock);
+        return ret;
 }
 
-/******************************************************************************
- * Polls the status bit (bit 1) of the EERD to determine when the read is done.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
+static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                u16 *data)
 {
-    u32 attempts = 100000;
-    u32 i, reg = 0;
-    s32 done = E1000_ERR_EEPROM;
-
-    for (i = 0; i < attempts; i++) {
-        if (eerd == E1000_EEPROM_POLL_READ)
-            reg = er32(EERD);
-        else
-            reg = er32(EEWR);
-
-        if (reg & E1000_EEPROM_RW_REG_DONE) {
-            done = E1000_SUCCESS;
-            break;
-        }
-        udelay(5);
-    }
-
-    return done;
-}
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 i = 0;
 
-/***************************************************************************
-* Description:     Determines if the onboard NVM is FLASH or EEPROM.
-*
-* hw - Struct containing variables accessed by shared code
-****************************************************************************/
-static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
-{
-    u32 eecd = 0;
+        DEBUGFUNC("e1000_read_eeprom");
 
-    DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
+        /* If eeprom is not yet detected, do so now */
+        if (eeprom->word_size == 0)
+                e1000_init_eeprom_params(hw);
+
+        /* A check for invalid values:  offset too large, too many words, and not
+         * enough words.
+         */
+        if ((offset >= eeprom->word_size)
+            || (words > eeprom->word_size - offset) || (words == 0)) {
+                DEBUGOUT2
+                    ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
+                     offset, eeprom->word_size);
+                return -E1000_ERR_EEPROM;
+        }
 
-    if (hw->mac_type == e1000_ich8lan)
-        return false;
+        /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
+         * directly. In this case, we need to acquire the EEPROM so that
+         * FW or other port software does not interrupt.
+         */
+        /* Prepare the EEPROM for bit-bang reading */
+        if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+                return -E1000_ERR_EEPROM;
+
+        /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
+         * acquired the EEPROM at this point, so any returns should release it */
+        if (eeprom->type == e1000_eeprom_spi) {
+                u16 word_in;
+                u8 read_opcode = EEPROM_READ_OPCODE_SPI;
+
+                if (e1000_spi_eeprom_ready(hw)) {
+                        e1000_release_eeprom(hw);
+                        return -E1000_ERR_EEPROM;
+                }
 
-    if (hw->mac_type == e1000_82573) {
-        eecd = er32(EECD);
+                e1000_standby_eeprom(hw);
+
+                /* Some SPI eeproms use the 8th address bit embedded in the opcode */
+                if ((eeprom->address_bits == 8) && (offset >= 128))
+                        read_opcode |= EEPROM_A8_OPCODE_SPI;
+
+                /* Send the READ command (opcode + addr)  */
+                e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
+                e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
+                                        eeprom->address_bits);
+
+                /* Read the data.  The address of the eeprom internally increments with
+                 * each byte (spi) being read, saving on the overhead of eeprom setup
+                 * and tear-down.  The address counter will roll over if reading beyond
+                 * the size of the eeprom, thus allowing the entire memory to be read
+                 * starting from any offset. */
+                for (i = 0; i < words; i++) {
+                        word_in = e1000_shift_in_ee_bits(hw, 16);
+                        data[i] = (word_in >> 8) | (word_in << 8);
+                }
+        } else if (eeprom->type == e1000_eeprom_microwire) {
+                for (i = 0; i < words; i++) {
+                        /* Send the READ command (opcode + addr)  */
+                        e1000_shift_out_ee_bits(hw,
+                                                EEPROM_READ_OPCODE_MICROWIRE,
+                                                eeprom->opcode_bits);
+                        e1000_shift_out_ee_bits(hw, (u16) (offset + i),
+                                                eeprom->address_bits);
+
+                        /* Read the data.  For microwire, each word requires the overhead
+                         * of eeprom setup and tear-down. */
+                        data[i] = e1000_shift_in_ee_bits(hw, 16);
+                        e1000_standby_eeprom(hw);
+                }
+        }
 
-        /* Isolate bits 15 & 16 */
-        eecd = ((eecd >> 15) & 0x03);
+        /* End this read operation */
+        e1000_release_eeprom(hw);
 
-        /* If both bits are set, device is Flash type */
-        if (eecd == 0x03) {
-            return false;
-        }
-    }
-    return true;
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
+ * @hw: Struct containing variables accessed by shared code
  *
  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  * valid.
- *****************************************************************************/
+ */
 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 {
-    u16 checksum = 0;
-    u16 i, eeprom_data;
-
-    DEBUGFUNC("e1000_validate_eeprom_checksum");
-
-    if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
-        /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
-         * 10h-12h.  Checksum may need to be fixed. */
-        e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
-        if ((eeprom_data & 0x10) == 0) {
-            /* Read 0x23 and check bit 15.  This bit is a 1 when the checksum
-             * has already been fixed.  If the checksum is still wrong and this
-             * bit is a 1, we need to return bad checksum.  Otherwise, we need
-             * to set this bit to a 1 and update the checksum. */
-            e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
-            if ((eeprom_data & 0x8000) == 0) {
-                eeprom_data |= 0x8000;
-                e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
-                e1000_update_eeprom_checksum(hw);
-            }
-        }
-    }
-
-    if (hw->mac_type == e1000_ich8lan) {
-        /* Drivers must allocate the shadow ram structure for the
-         * EEPROM checksum to be updated.  Otherwise, this bit as well
-         * as the checksum must both be set correctly for this
-         * validation to pass.
-         */
-        e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
-        if ((eeprom_data & 0x40) == 0) {
-            eeprom_data |= 0x40;
-            e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
-            e1000_update_eeprom_checksum(hw);
-        }
-    }
-
-    for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        checksum += eeprom_data;
-    }
-
-    if (checksum == (u16)EEPROM_SUM)
-        return E1000_SUCCESS;
-    else {
-        DEBUGOUT("EEPROM Checksum Invalid\n");
-        return -E1000_ERR_EEPROM;
-    }
+        u16 checksum = 0;
+        u16 i, eeprom_data;
+
+        DEBUGFUNC("e1000_validate_eeprom_checksum");
+
+        for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
+                if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+                        DEBUGOUT("EEPROM Read Error\n");
+                        return -E1000_ERR_EEPROM;
+                }
+                checksum += eeprom_data;
+        }
+
+        if (checksum == (u16) EEPROM_SUM)
+                return E1000_SUCCESS;
+        else {
+                DEBUGOUT("EEPROM Checksum Invalid\n");
+                return -E1000_ERR_EEPROM;
+        }
 }
 
-/******************************************************************************
- * Calculates the EEPROM checksum and writes it to the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
+ * @hw: Struct containing variables accessed by shared code
  *
  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
  * Writes the difference to word offset 63 of the EEPROM.
- *****************************************************************************/
+ */
 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
 {
-    u32 ctrl_ext;
-    u16 checksum = 0;
-    u16 i, eeprom_data;
-
-    DEBUGFUNC("e1000_update_eeprom_checksum");
-
-    for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
-        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        checksum += eeprom_data;
-    }
-    checksum = (u16)EEPROM_SUM - checksum;
-    if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
-        DEBUGOUT("EEPROM Write Error\n");
-        return -E1000_ERR_EEPROM;
-    } else if (hw->eeprom.type == e1000_eeprom_flash) {
-        e1000_commit_shadow_ram(hw);
-    } else if (hw->eeprom.type == e1000_eeprom_ich8) {
-        e1000_commit_shadow_ram(hw);
-        /* Reload the EEPROM, or else modifications will not appear
-         * until after next adapter reset. */
-        ctrl_ext = er32(CTRL_EXT);
-        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-        ew32(CTRL_EXT, ctrl_ext);
-        msleep(10);
-    }
-    return E1000_SUCCESS;
+        u16 checksum = 0;
+        u16 i, eeprom_data;
+
+        DEBUGFUNC("e1000_update_eeprom_checksum");
+
+        for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
+                if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+                        DEBUGOUT("EEPROM Read Error\n");
+                        return -E1000_ERR_EEPROM;
+                }
+                checksum += eeprom_data;
+        }
+        checksum = (u16) EEPROM_SUM - checksum;
+        if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
+                DEBUGOUT("EEPROM Write Error\n");
+                return -E1000_ERR_EEPROM;
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Parent function for writing words to the different EEPROM types.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - 16 bit word to be written to the EEPROM
+/**
+ * e1000_write_eeprom - write words to the different EEPROM types.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: 16 bit word to be written to the EEPROM
  *
  * If e1000_update_eeprom_checksum is not called after this function, the
  * EEPROM will most likely contain an invalid checksum.
- *****************************************************************************/
+ */
 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 {
-    s32 ret;
-    spin_lock(&e1000_eeprom_lock);
-    ret = e1000_do_write_eeprom(hw, offset, words, data);
-    spin_unlock(&e1000_eeprom_lock);
-    return ret;
+        s32 ret;
+        spin_lock(&e1000_eeprom_lock);
+        ret = e1000_do_write_eeprom(hw, offset, words, data);
+        spin_unlock(&e1000_eeprom_lock);
+        return ret;
 }
 
-
-static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                 u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    s32 status = 0;
-
-    DEBUGFUNC("e1000_write_eeprom");
-
-    /* If eeprom is not yet detected, do so now */
-    if (eeprom->word_size == 0)
-        e1000_init_eeprom_params(hw);
-
-    /* A check for invalid values:  offset too large, too many words, and not
-     * enough words.
-     */
-    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
-       (words == 0)) {
-        DEBUGOUT("\"words\" parameter out of bounds\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    /* 82573 writes only through eewr */
-    if (eeprom->use_eewr)
-        return e1000_write_eeprom_eewr(hw, offset, words, data);
-
-    if (eeprom->type == e1000_eeprom_ich8)
-        return e1000_write_eeprom_ich8(hw, offset, words, data);
-
-    /* Prepare the EEPROM for writing  */
-    if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-        return -E1000_ERR_EEPROM;
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        status = e1000_write_eeprom_microwire(hw, offset, words, data);
-    } else {
-        status = e1000_write_eeprom_spi(hw, offset, words, data);
-        msleep(10);
-    }
-
-    /* Done with writing */
-    e1000_release_eeprom(hw);
-
-    return status;
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        s32 status = 0;
+
+        DEBUGFUNC("e1000_write_eeprom");
+
+        /* If eeprom is not yet detected, do so now */
+        if (eeprom->word_size == 0)
+                e1000_init_eeprom_params(hw);
+
+        /* A check for invalid values:  offset too large, too many words, and not
+         * enough words.
+         */
+        if ((offset >= eeprom->word_size)
+            || (words > eeprom->word_size - offset) || (words == 0)) {
+                DEBUGOUT("\"words\" parameter out of bounds\n");
+                return -E1000_ERR_EEPROM;
+        }
+
+        /* Prepare the EEPROM for writing  */
+        if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+                return -E1000_ERR_EEPROM;
+
+        if (eeprom->type == e1000_eeprom_microwire) {
+                status = e1000_write_eeprom_microwire(hw, offset, words, data);
+        } else {
+                status = e1000_write_eeprom_spi(hw, offset, words, data);
+                msleep(10);
+        }
+
+        /* Done with writing */
+        e1000_release_eeprom(hw);
+
+        return status;
 }
 
-/******************************************************************************
- * Writes a 16 bit word to a given offset in an SPI EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - pointer to array of 8 bit words to be written to the EEPROM
- *
- *****************************************************************************/
+/**
+ * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: pointer to array of 8 bit words to be written to the EEPROM
+ */
 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
                                   u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u16 widx = 0;
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u16 widx = 0;
 
-    DEBUGFUNC("e1000_write_eeprom_spi");
+        DEBUGFUNC("e1000_write_eeprom_spi");
 
-    while (widx < words) {
-        u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
+        while (widx < words) {
+                u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
 
-        if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
+                if (e1000_spi_eeprom_ready(hw))
+                        return -E1000_ERR_EEPROM;
 
-        e1000_standby_eeprom(hw);
+                e1000_standby_eeprom(hw);
 
-        /*  Send the WRITE ENABLE command (8 bit opcode )  */
-        e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
-                                    eeprom->opcode_bits);
+                /*  Send the WRITE ENABLE command (8 bit opcode )  */
+                e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
+                                        eeprom->opcode_bits);
 
-        e1000_standby_eeprom(hw);
+                e1000_standby_eeprom(hw);
 
-        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if ((eeprom->address_bits == 8) && (offset >= 128))
-            write_opcode |= EEPROM_A8_OPCODE_SPI;
+                /* Some SPI eeproms use the 8th address bit embedded in the opcode */
+                if ((eeprom->address_bits == 8) && (offset >= 128))
+                        write_opcode |= EEPROM_A8_OPCODE_SPI;
 
-        /* Send the Write command (8-bit opcode + addr) */
-        e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
+                /* Send the Write command (8-bit opcode + addr) */
+                e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
 
-        e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
-                                eeprom->address_bits);
+                e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
+                                        eeprom->address_bits);
 
-        /* Send the data */
+                /* Send the data */
 
-        /* Loop to allow for up to whole page write (32 bytes) of eeprom */
-        while (widx < words) {
-            u16 word_out = data[widx];
-            word_out = (word_out >> 8) | (word_out << 8);
-            e1000_shift_out_ee_bits(hw, word_out, 16);
-            widx++;
+                /* Loop to allow for up to whole page write (32 bytes) of eeprom */
+                while (widx < words) {
+                        u16 word_out = data[widx];
+                        word_out = (word_out >> 8) | (word_out << 8);
+                        e1000_shift_out_ee_bits(hw, word_out, 16);
+                        widx++;
 
-            /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
-             * operation, while the smaller eeproms are capable of an 8-byte
-             * PAGE WRITE operation.  Break the inner loop to pass new address
-             */
-            if ((((offset + widx)*2) % eeprom->page_size) == 0) {
-                e1000_standby_eeprom(hw);
-                break;
-            }
-        }
-    }
+                        /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
+                         * operation, while the smaller eeproms are capable of an 8-byte
+                         * PAGE WRITE operation.  Break the inner loop to pass new address
+                         */
+                        if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
+                                e1000_standby_eeprom(hw);
+                                break;
+                        }
+                }
+        }
 
-    return E1000_SUCCESS;
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Writes a 16 bit word to a given offset in a Microwire EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - pointer to array of 16 bit words to be written to the EEPROM
- *
- *****************************************************************************/
+/**
+ * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: pointer to array of 8 bit words to be written to the EEPROM
+ */
 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
                                         u16 words, u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-    u16 words_written = 0;
-    u16 i = 0;
-
-    DEBUGFUNC("e1000_write_eeprom_microwire");
-
-    /* Send the write enable command to the EEPROM (3-bit opcode plus
-     * 6/8-bit dummy address beginning with 11).  It's less work to include
-     * the 11 of the dummy address as part of the opcode than it is to shift
-     * it over the correct number of bits for the address.  This puts the
-     * EEPROM into write/erase mode.
-     */
-    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
-                            (u16)(eeprom->opcode_bits + 2));
-
-    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
-
-    /* Prepare the EEPROM */
-    e1000_standby_eeprom(hw);
-
-    while (words_written < words) {
-        /* Send the Write command (3-bit opcode + addr) */
-        e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
-                                eeprom->opcode_bits);
-
-        e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
-                                eeprom->address_bits);
-
-        /* Send the data */
-        e1000_shift_out_ee_bits(hw, data[words_written], 16);
-
-        /* Toggle the CS line.  This in effect tells the EEPROM to execute
-         * the previous command.
-         */
-        e1000_standby_eeprom(hw);
-
-        /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
-         * signal that the command has been completed by raising the DO signal.
-         * If DO does not go high in 10 milliseconds, then error out.
-         */
-        for (i = 0; i < 200; i++) {
-            eecd = er32(EECD);
-            if (eecd & E1000_EECD_DO) break;
-            udelay(50);
-        }
-        if (i == 200) {
-            DEBUGOUT("EEPROM Write did not complete\n");
-            return -E1000_ERR_EEPROM;
-        }
-
-        /* Recover from write */
-        e1000_standby_eeprom(hw);
-
-        words_written++;
-    }
-
-    /* Send the write disable command to the EEPROM (3-bit opcode plus
-     * 6/8-bit dummy address beginning with 10).  It's less work to include
-     * the 10 of the dummy address as part of the opcode than it is to shift
-     * it over the correct number of bits for the address.  This takes the
-     * EEPROM out of write/erase mode.
-     */
-    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
-                            (u16)(eeprom->opcode_bits + 2));
-
-    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
-
-    return E1000_SUCCESS;
-}
+        struct e1000_eeprom_info *eeprom = &hw->eeprom;
+        u32 eecd;
+        u16 words_written = 0;
+        u16 i = 0;
 
-/******************************************************************************
- * Flushes the cached eeprom to NVM. This is done by saving the modified values
- * in the eeprom cache and the non modified values in the currently active bank
- * to the new bank.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
-{
-    u32 attempts = 100000;
-    u32 eecd = 0;
-    u32 flop = 0;
-    u32 i = 0;
-    s32 error = E1000_SUCCESS;
-    u32 old_bank_offset = 0;
-    u32 new_bank_offset = 0;
-    u8 low_byte = 0;
-    u8 high_byte = 0;
-    bool sector_write_failed = false;
-
-    if (hw->mac_type == e1000_82573) {
-        /* The flop register will be used to determine if flash type is STM */
-        flop = er32(FLOP);
-        for (i=0; i < attempts; i++) {
-            eecd = er32(EECD);
-            if ((eecd & E1000_EECD_FLUPD) == 0) {
-                break;
-            }
-            udelay(5);
-        }
-
-        if (i == attempts) {
-            return -E1000_ERR_EEPROM;
-        }
-
-        /* If STM opcode located in bits 15:8 of flop, reset firmware */
-        if ((flop & 0xFF00) == E1000_STM_OPCODE) {
-            ew32(HICR, E1000_HICR_FW_RESET);
-        }
-
-        /* Perform the flash update */
-        ew32(EECD, eecd | E1000_EECD_FLUPD);
-
-        for (i=0; i < attempts; i++) {
-            eecd = er32(EECD);
-            if ((eecd & E1000_EECD_FLUPD) == 0) {
-                break;
-            }
-            udelay(5);
-        }
-
-        if (i == attempts) {
-            return -E1000_ERR_EEPROM;
-        }
-    }
-
-    if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
-        /* We're writing to the opposite bank so if we're on bank 1,
-         * write to bank 0 etc.  We also need to erase the segment that
-         * is going to be written */
-        if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
-            new_bank_offset = hw->flash_bank_size * 2;
-            old_bank_offset = 0;
-            e1000_erase_ich8_4k_segment(hw, 1);
-        } else {
-            old_bank_offset = hw->flash_bank_size * 2;
-            new_bank_offset = 0;
-            e1000_erase_ich8_4k_segment(hw, 0);
-        }
-
-        sector_write_failed = false;
-        /* Loop for every byte in the shadow RAM,
-         * which is in units of words. */
-        for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-            /* Determine whether to write the value stored
-             * in the other NVM bank or a modified value stored
-             * in the shadow RAM */
-            if (hw->eeprom_shadow_ram[i].modified) {
-                low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
-                udelay(100);
-                error = e1000_verify_write_ich8_byte(hw,
-                            (i << 1) + new_bank_offset, low_byte);
-
-                if (error != E1000_SUCCESS)
-                    sector_write_failed = true;
-                else {
-                    high_byte =
-                        (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
-                    udelay(100);
-                }
-            } else {
-                e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
-                                     &low_byte);
-                udelay(100);
-                error = e1000_verify_write_ich8_byte(hw,
-                            (i << 1) + new_bank_offset, low_byte);
-
-                if (error != E1000_SUCCESS)
-                    sector_write_failed = true;
-                else {
-                    e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
-                                         &high_byte);
-                    udelay(100);
-                }
-            }
-
-            /* If the write of the low byte was successful, go ahead and
-             * write the high byte while checking to make sure that if it
-             * is the signature byte, then it is handled properly */
-            if (!sector_write_failed) {
-                /* If the word is 0x13, then make sure the signature bits
-                 * (15:14) are 11b until the commit has completed.
-                 * This will allow us to write 10b which indicates the
-                 * signature is valid.  We want to do this after the write
-                 * has completed so that we don't mark the segment valid
-                 * while the write is still in progress */
-                if (i == E1000_ICH_NVM_SIG_WORD)
-                    high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
-
-                error = e1000_verify_write_ich8_byte(hw,
-                            (i << 1) + new_bank_offset + 1, high_byte);
-                if (error != E1000_SUCCESS)
-                    sector_write_failed = true;
-
-            } else {
-                /* If the write failed then break from the loop and
-                 * return an error */
-                break;
-            }
-        }
-
-        /* Don't bother writing the segment valid bits if sector
-         * programming failed. */
-        if (!sector_write_failed) {
-            /* Finally validate the new segment by setting bit 15:14
-             * to 10b in word 0x13 , this can be done without an
-             * erase as well since these bits are 11 to start with
-             * and we need to change bit 14 to 0b */
-            e1000_read_ich8_byte(hw,
-                                 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
-                                 &high_byte);
-            high_byte &= 0xBF;
-            error = e1000_verify_write_ich8_byte(hw,
-                        E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
-            /* And invalidate the previously valid segment by setting
-             * its signature word (0x13) high_byte to 0b. This can be
-             * done without an erase because flash erase sets all bits
-             * to 1's. We can write 1's to 0's without an erase */
-            if (error == E1000_SUCCESS) {
-                error = e1000_verify_write_ich8_byte(hw,
-                            E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
-            }
-
-            /* Clear the now not used entry in the cache */
-            for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-                hw->eeprom_shadow_ram[i].modified = false;
-                hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
-            }
-        }
-    }
-
-    return error;
+        DEBUGFUNC("e1000_write_eeprom_microwire");
+
+        /* Send the write enable command to the EEPROM (3-bit opcode plus
+         * 6/8-bit dummy address beginning with 11).  It's less work to include
+         * the 11 of the dummy address as part of the opcode than it is to shift
+         * it over the correct number of bits for the address.  This puts the
+         * EEPROM into write/erase mode.
+         */
+        e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
+                                (u16) (eeprom->opcode_bits + 2));
+
+        e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
+
+        /* Prepare the EEPROM */
+        e1000_standby_eeprom(hw);
+
+        while (words_written < words) {
+                /* Send the Write command (3-bit opcode + addr) */
+                e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
+                                        eeprom->opcode_bits);
+
+                e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
+                                        eeprom->address_bits);
+
+                /* Send the data */
+                e1000_shift_out_ee_bits(hw, data[words_written], 16);
+
+                /* Toggle the CS line.  This in effect tells the EEPROM to execute
+                 * the previous command.
+                 */
+                e1000_standby_eeprom(hw);
+
+                /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
+                 * signal that the command has been completed by raising the DO signal.
+                 * If DO does not go high in 10 milliseconds, then error out.
+                 */
+                for (i = 0; i < 200; i++) {
+                        eecd = er32(EECD);
+                        if (eecd & E1000_EECD_DO)
+                                break;
+                        udelay(50);
+                }
+                if (i == 200) {
+                        DEBUGOUT("EEPROM Write did not complete\n");
+                        return -E1000_ERR_EEPROM;
+                }
+
+                /* Recover from write */
+                e1000_standby_eeprom(hw);
+
+                words_written++;
+        }
+
+        /* Send the write disable command to the EEPROM (3-bit opcode plus
+         * 6/8-bit dummy address beginning with 10).  It's less work to include
+         * the 10 of the dummy address as part of the opcode than it is to shift
+         * it over the correct number of bits for the address.  This takes the
+         * EEPROM out of write/erase mode.
+         */
+        e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
+                                (u16) (eeprom->opcode_bits + 2));
+
+        e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
+/**
+ * e1000_read_mac_addr - read the adapters MAC from eeprom
+ * @hw: Struct containing variables accessed by shared code
+ *
  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  * second function of dual function devices
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ */
 s32 e1000_read_mac_addr(struct e1000_hw *hw)
 {
-    u16 offset;
-    u16 eeprom_data, i;
-
-    DEBUGFUNC("e1000_read_mac_addr");
-
-    for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-        offset = i >> 1;
-        if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
-        hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
-    }
-
-    switch (hw->mac_type) {
-    default:
-        break;
-    case e1000_82546:
-    case e1000_82546_rev_3:
-    case e1000_82571:
-    case e1000_80003es2lan:
-        if (er32(STATUS) & E1000_STATUS_FUNC_1)
-            hw->perm_mac_addr[5] ^= 0x01;
-        break;
-    }
-
-    for (i = 0; i < NODE_ADDRESS_SIZE; i++)
-        hw->mac_addr[i] = hw->perm_mac_addr[i];
-    return E1000_SUCCESS;
+        u16 offset;
+        u16 eeprom_data, i;
+
+        DEBUGFUNC("e1000_read_mac_addr");
+
+        for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+                offset = i >> 1;
+                if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+                        DEBUGOUT("EEPROM Read Error\n");
+                        return -E1000_ERR_EEPROM;
+                }
+                hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
+                hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
+        }
+
+        switch (hw->mac_type) {
+        default:
+                break;
+        case e1000_82546:
+        case e1000_82546_rev_3:
+                if (er32(STATUS) & E1000_STATUS_FUNC_1)
+                        hw->perm_mac_addr[5] ^= 0x01;
+                break;
+        }
+
+        for (i = 0; i < NODE_ADDRESS_SIZE; i++)
+                hw->mac_addr[i] = hw->perm_mac_addr[i];
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_init_rx_addrs - Initializes receive address filters.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
+ * of the receive address registers. Clears the multicast table. Assumes
  * the receiver is in reset when the routine is called.
- *****************************************************************************/
+ */
 static void e1000_init_rx_addrs(struct e1000_hw *hw)
 {
-    u32 i;
-    u32 rar_num;
-
-    DEBUGFUNC("e1000_init_rx_addrs");
-
-    /* Setup the receive address. */
-    DEBUGOUT("Programming MAC Address into RAR[0]\n");
-
-    e1000_rar_set(hw, hw->mac_addr, 0);
-
-    rar_num = E1000_RAR_ENTRIES;
-
-    /* Reserve a spot for the Locally Administered Address to work around
-     * an 82571 issue in which a reset on one port will reload the MAC on
-     * the other port. */
-    if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
-        rar_num -= 1;
-    if (hw->mac_type == e1000_ich8lan)
-        rar_num = E1000_RAR_ENTRIES_ICH8LAN;
-
-    /* Zero out the other 15 receive addresses. */
-    DEBUGOUT("Clearing RAR[1-15]\n");
-    for (i = 1; i < rar_num; i++) {
-        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-        E1000_WRITE_FLUSH();
-        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
-        E1000_WRITE_FLUSH();
-    }
+        u32 i;
+        u32 rar_num;
+
+        DEBUGFUNC("e1000_init_rx_addrs");
+
+        /* Setup the receive address. */
+        DEBUGOUT("Programming MAC Address into RAR[0]\n");
+
+        e1000_rar_set(hw, hw->mac_addr, 0);
+
+        rar_num = E1000_RAR_ENTRIES;
+
+        /* Zero out the other 15 receive addresses. */
+        DEBUGOUT("Clearing RAR[1-15]\n");
+        for (i = 1; i < rar_num; i++) {
+                E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+                E1000_WRITE_FLUSH();
+                E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+                E1000_WRITE_FLUSH();
+        }
 }
 
-/******************************************************************************
- * Hashes an address to determine its location in the multicast table
- *
- * hw - Struct containing variables accessed by shared code
- * mc_addr - the multicast address to hash
- *****************************************************************************/
+/**
+ * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
+ * @hw: Struct containing variables accessed by shared code
+ * @mc_addr: the multicast address to hash
+ */
 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
 {
-    u32 hash_value = 0;
-
-    /* The portion of the address that is used for the hash table is
-     * determined by the mc_filter_type setting.
-     */
-    switch (hw->mc_filter_type) {
-    /* [0] [1] [2] [3] [4] [5]
-     * 01  AA  00  12  34  56
-     * LSB                 MSB
-     */
-    case 0:
-        if (hw->mac_type == e1000_ich8lan) {
-            /* [47:38] i.e. 0x158 for above example address */
-            hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
-        } else {
-            /* [47:36] i.e. 0x563 for above example address */
-            hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
-        }
-        break;
-    case 1:
-        if (hw->mac_type == e1000_ich8lan) {
-            /* [46:37] i.e. 0x2B1 for above example address */
-            hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
-        } else {
-            /* [46:35] i.e. 0xAC6 for above example address */
-            hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
-        }
-        break;
-    case 2:
-        if (hw->mac_type == e1000_ich8lan) {
-            /*[45:36] i.e. 0x163 for above example address */
-            hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
-        } else {
-            /* [45:34] i.e. 0x5D8 for above example address */
-            hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
-        }
-        break;
-    case 3:
-        if (hw->mac_type == e1000_ich8lan) {
-            /* [43:34] i.e. 0x18D for above example address */
-            hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
-        } else {
-            /* [43:32] i.e. 0x634 for above example address */
-            hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
-        }
-        break;
-    }
-
-    hash_value &= 0xFFF;
-    if (hw->mac_type == e1000_ich8lan)
-        hash_value &= 0x3FF;
-
-    return hash_value;
+        u32 hash_value = 0;
+
+        /* The portion of the address that is used for the hash table is
+         * determined by the mc_filter_type setting.
+         */
+        switch (hw->mc_filter_type) {
+                /* [0] [1] [2] [3] [4] [5]
+                 * 01  AA  00  12  34  56
+                 * LSB                 MSB
+                 */
+        case 0:
+                /* [47:36] i.e. 0x563 for above example address */
+                hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
+                break;
+        case 1:
+                /* [46:35] i.e. 0xAC6 for above example address */
+                hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
+                break;
+        case 2:
+                /* [45:34] i.e. 0x5D8 for above example address */
+                hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
+                break;
+        case 3:
+                /* [43:32] i.e. 0x634 for above example address */
+                hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
+                break;
+        }
+
+        hash_value &= 0xFFF;
+        return hash_value;
 }
 
-/******************************************************************************
- * Puts an ethernet address into a receive address register.
- *
- * hw - Struct containing variables accessed by shared code
- * addr - Address to put into receive address register
- * index - Receive address register to write
- *****************************************************************************/
+/**
+ * e1000_rar_set - Puts an ethernet address into a receive address register.
+ * @hw: Struct containing variables accessed by shared code
+ * @addr: Address to put into receive address register
+ * @index: Receive address register to write
+ */
 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
 {
-    u32 rar_low, rar_high;
-
-    /* HW expects these in little endian so we reverse the byte order
-     * from network order (big endian) to little endian
-     */
-    rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
-               ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
-    rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
-
-    /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
-     * unit hang.
-     *
-     * Description:
-     * If there are any Rx frames queued up or otherwise present in the HW
-     * before RSS is enabled, and then we enable RSS, the HW Rx unit will
-     * hang.  To work around this issue, we have to disable receives and
-     * flush out all Rx frames before we enable RSS. To do so, we modify we
-     * redirect all Rx traffic to manageability and then reset the HW.
-     * This flushes away Rx frames, and (since the redirections to
-     * manageability persists across resets) keeps new ones from coming in
-     * while we work.  Then, we clear the Address Valid AV bit for all MAC
-     * addresses and undo the re-direction to manageability.
-     * Now, frames are coming in again, but the MAC won't accept them, so
-     * far so good.  We now proceed to initialize RSS (if necessary) and
-     * configure the Rx unit.  Last, we re-enable the AV bits and continue
-     * on our merry way.
-     */
-    switch (hw->mac_type) {
-    case e1000_82571:
-    case e1000_82572:
-    case e1000_80003es2lan:
-        if (hw->leave_av_bit_off)
-            break;
-    default:
-        /* Indicate to hardware the Address is Valid. */
-        rar_high |= E1000_RAH_AV;
-        break;
-    }
-
-    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
-    E1000_WRITE_FLUSH();
-    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
-    E1000_WRITE_FLUSH();
+        u32 rar_low, rar_high;
+
+        /* HW expects these in little endian so we reverse the byte order
+         * from network order (big endian) to little endian
+         */
+        rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
+                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
+
+        /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
+         * unit hang.
+         *
+         * Description:
+         * If there are any Rx frames queued up or otherwise present in the HW
+         * before RSS is enabled, and then we enable RSS, the HW Rx unit will
+         * hang.  To work around this issue, we have to disable receives and
+         * flush out all Rx frames before we enable RSS. To do so, we modify we
+         * redirect all Rx traffic to manageability and then reset the HW.
+         * This flushes away Rx frames, and (since the redirections to
+         * manageability persists across resets) keeps new ones from coming in
+         * while we work.  Then, we clear the Address Valid AV bit for all MAC
+         * addresses and undo the re-direction to manageability.
+         * Now, frames are coming in again, but the MAC won't accept them, so
+         * far so good.  We now proceed to initialize RSS (if necessary) and
+         * configure the Rx unit.  Last, we re-enable the AV bits and continue
+         * on our merry way.
+         */
+        switch (hw->mac_type) {
+        default:
+                /* Indicate to hardware the Address is Valid. */
+                rar_high |= E1000_RAH_AV;
+                break;
+        }
+
+        E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
+        E1000_WRITE_FLUSH();
+        E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
+        E1000_WRITE_FLUSH();
 }
 
-/******************************************************************************
- * Writes a value to the specified offset in the VLAN filter table.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - Offset in VLAN filer table to write
- * value - Value to write into VLAN filter table
- *****************************************************************************/
+/**
+ * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: Offset in VLAN filer table to write
+ * @value: Value to write into VLAN filter table
+ */
 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
 {
-    u32 temp;
-
-    if (hw->mac_type == e1000_ich8lan)
-        return;
-
-    if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
-        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
-        E1000_WRITE_FLUSH();
-        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
-        E1000_WRITE_FLUSH();
-    } else {
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
-        E1000_WRITE_FLUSH();
-    }
+        u32 temp;
+
+        if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
+                temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
+                E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+                E1000_WRITE_FLUSH();
+                E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
+                E1000_WRITE_FLUSH();
+        } else {
+                E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+                E1000_WRITE_FLUSH();
+        }
 }
 
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_clear_vfta - Clears the VLAN filer table
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_clear_vfta(struct e1000_hw *hw)
 {
-    u32 offset;
-    u32 vfta_value = 0;
-    u32 vfta_offset = 0;
-    u32 vfta_bit_in_reg = 0;
-
-    if (hw->mac_type == e1000_ich8lan)
-        return;
-
-    if (hw->mac_type == e1000_82573) {
-        if (hw->mng_cookie.vlan_id != 0) {
-            /* The VFTA is a 4096b bit-field, each identifying a single VLAN
-             * ID.  The following operations determine which 32b entry
-             * (i.e. offset) into the array we want to set the VLAN ID
-             * (i.e. bit) of the manageability unit. */
-            vfta_offset = (hw->mng_cookie.vlan_id >>
-                           E1000_VFTA_ENTRY_SHIFT) &
-                          E1000_VFTA_ENTRY_MASK;
-            vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
-                                    E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
-        }
-    }
-    for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
-        /* If the offset we want to clear is the same offset of the
-         * manageability VLAN ID, then clear all bits except that of the
-         * manageability unit */
-        vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
-        E1000_WRITE_FLUSH();
-    }
+        u32 offset;
+        u32 vfta_value = 0;
+        u32 vfta_offset = 0;
+        u32 vfta_bit_in_reg = 0;
+
+        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+                /* If the offset we want to clear is the same offset of the
+                 * manageability VLAN ID, then clear all bits except that of the
+                 * manageability unit */
+                vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
+                E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
+                E1000_WRITE_FLUSH();
+        }
 }
 
 static s32 e1000_id_led_init(struct e1000_hw *hw)
 {
-    u32 ledctl;
-    const u32 ledctl_mask = 0x000000FF;
-    const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
-    const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
-    u16 eeprom_data, i, temp;
-    const u16 led_mask = 0x0F;
-
-    DEBUGFUNC("e1000_id_led_init");
-
-    if (hw->mac_type < e1000_82540) {
-        /* Nothing to do */
-        return E1000_SUCCESS;
-    }
-
-    ledctl = er32(LEDCTL);
-    hw->ledctl_default = ledctl;
-    hw->ledctl_mode1 = hw->ledctl_default;
-    hw->ledctl_mode2 = hw->ledctl_default;
-
-    if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
-        DEBUGOUT("EEPROM Read Error\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    if ((hw->mac_type == e1000_82573) &&
-        (eeprom_data == ID_LED_RESERVED_82573))
-        eeprom_data = ID_LED_DEFAULT_82573;
-    else if ((eeprom_data == ID_LED_RESERVED_0000) ||
-            (eeprom_data == ID_LED_RESERVED_FFFF)) {
-        if (hw->mac_type == e1000_ich8lan)
-            eeprom_data = ID_LED_DEFAULT_ICH8LAN;
-        else
-            eeprom_data = ID_LED_DEFAULT;
-    }
-
-    for (i = 0; i < 4; i++) {
-        temp = (eeprom_data >> (i << 2)) & led_mask;
-        switch (temp) {
-        case ID_LED_ON1_DEF2:
-        case ID_LED_ON1_ON2:
-        case ID_LED_ON1_OFF2:
-            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode1 |= ledctl_on << (i << 3);
-            break;
-        case ID_LED_OFF1_DEF2:
-        case ID_LED_OFF1_ON2:
-        case ID_LED_OFF1_OFF2:
-            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode1 |= ledctl_off << (i << 3);
-            break;
-        default:
-            /* Do nothing */
-            break;
-        }
-        switch (temp) {
-        case ID_LED_DEF1_ON2:
-        case ID_LED_ON1_ON2:
-        case ID_LED_OFF1_ON2:
-            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode2 |= ledctl_on << (i << 3);
-            break;
-        case ID_LED_DEF1_OFF2:
-        case ID_LED_ON1_OFF2:
-        case ID_LED_OFF1_OFF2:
-            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode2 |= ledctl_off << (i << 3);
-            break;
-        default:
-            /* Do nothing */
-            break;
-        }
-    }
-    return E1000_SUCCESS;
+        u32 ledctl;
+        const u32 ledctl_mask = 0x000000FF;
+        const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
+        const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
+        u16 eeprom_data, i, temp;
+        const u16 led_mask = 0x0F;
+
+        DEBUGFUNC("e1000_id_led_init");
+
+        if (hw->mac_type < e1000_82540) {
+                /* Nothing to do */
+                return E1000_SUCCESS;
+        }
+
+        ledctl = er32(LEDCTL);
+        hw->ledctl_default = ledctl;
+        hw->ledctl_mode1 = hw->ledctl_default;
+        hw->ledctl_mode2 = hw->ledctl_default;
+
+        if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
+                DEBUGOUT("EEPROM Read Error\n");
+                return -E1000_ERR_EEPROM;
+        }
+
+        if ((eeprom_data == ID_LED_RESERVED_0000) ||
+            (eeprom_data == ID_LED_RESERVED_FFFF)) {
+                eeprom_data = ID_LED_DEFAULT;
+        }
+
+        for (i = 0; i < 4; i++) {
+                temp = (eeprom_data >> (i << 2)) & led_mask;
+                switch (temp) {
+                case ID_LED_ON1_DEF2:
+                case ID_LED_ON1_ON2:
+                case ID_LED_ON1_OFF2:
+                        hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+                        hw->ledctl_mode1 |= ledctl_on << (i << 3);
+                        break;
+                case ID_LED_OFF1_DEF2:
+                case ID_LED_OFF1_ON2:
+                case ID_LED_OFF1_OFF2:
+                        hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+                        hw->ledctl_mode1 |= ledctl_off << (i << 3);
+                        break;
+                default:
+                        /* Do nothing */
+                        break;
+                }
+                switch (temp) {
+                case ID_LED_DEF1_ON2:
+                case ID_LED_ON1_ON2:
+                case ID_LED_OFF1_ON2:
+                        hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+                        hw->ledctl_mode2 |= ledctl_on << (i << 3);
+                        break;
+                case ID_LED_DEF1_OFF2:
+                case ID_LED_ON1_OFF2:
+                case ID_LED_OFF1_OFF2:
+                        hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+                        hw->ledctl_mode2 |= ledctl_off << (i << 3);
+                        break;
+                default:
+                        /* Do nothing */
+                        break;
+                }
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Prepares SW controlable LED for use and saves the current state of the LED.
+/**
+ * e1000_setup_led
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Prepares SW controlable LED for use and saves the current state of the LED.
+ */
 s32 e1000_setup_led(struct e1000_hw *hw)
 {
-    u32 ledctl;
-    s32 ret_val = E1000_SUCCESS;
-
-    DEBUGFUNC("e1000_setup_led");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        /* No setup necessary */
-        break;
-    case e1000_82541:
-    case e1000_82547:
-    case e1000_82541_rev_2:
-    case e1000_82547_rev_2:
-        /* Turn off PHY Smart Power Down (if enabled) */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                     &hw->phy_spd_default);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                      (u16)(hw->phy_spd_default &
-                                      ~IGP01E1000_GMII_SPD));
-        if (ret_val)
-            return ret_val;
-        /* Fall Through */
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            ledctl = er32(LEDCTL);
-            /* Save current LEDCTL settings */
-            hw->ledctl_default = ledctl;
-            /* Turn off LED0 */
-            ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
-                        E1000_LEDCTL_LED0_BLINK |
-                        E1000_LEDCTL_LED0_MODE_MASK);
-            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
-                       E1000_LEDCTL_LED0_MODE_SHIFT);
-            ew32(LEDCTL, ledctl);
-        } else if (hw->media_type == e1000_media_type_copper)
-            ew32(LEDCTL, hw->ledctl_mode1);
-        break;
-    }
-
-    return E1000_SUCCESS;
-}
+        u32 ledctl;
+        s32 ret_val = E1000_SUCCESS;
 
+        DEBUGFUNC("e1000_setup_led");
 
-/******************************************************************************
- * Used on 82571 and later Si that has LED blink bits.
- * Callers must use their own timer and should have already called
- * e1000_id_led_init()
- * Call e1000_cleanup led() to stop blinking
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-s32 e1000_blink_led_start(struct e1000_hw *hw)
-{
-    s16  i;
-    u32 ledctl_blink = 0;
-
-    DEBUGFUNC("e1000_id_led_blink_on");
-
-    if (hw->mac_type < e1000_82571) {
-        /* Nothing to do */
-        return E1000_SUCCESS;
-    }
-    if (hw->media_type == e1000_media_type_fiber) {
-        /* always blink LED0 for PCI-E fiber */
-        ledctl_blink = E1000_LEDCTL_LED0_BLINK |
-                     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
-    } else {
-        /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
-        ledctl_blink = hw->ledctl_mode2;
-        for (i=0; i < 4; i++)
-            if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
-                E1000_LEDCTL_MODE_LED_ON)
-                ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
-    }
-
-    ew32(LEDCTL, ledctl_blink);
-
-    return E1000_SUCCESS;
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+        case e1000_82544:
+                /* No setup necessary */
+                break;
+        case e1000_82541:
+        case e1000_82547:
+        case e1000_82541_rev_2:
+        case e1000_82547_rev_2:
+                /* Turn off PHY Smart Power Down (if enabled) */
+                ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                             &hw->phy_spd_default);
+                if (ret_val)
+                        return ret_val;
+                ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                              (u16) (hw->phy_spd_default &
+                                                     ~IGP01E1000_GMII_SPD));
+                if (ret_val)
+                        return ret_val;
+                /* Fall Through */
+        default:
+                if (hw->media_type == e1000_media_type_fiber) {
+                        ledctl = er32(LEDCTL);
+                        /* Save current LEDCTL settings */
+                        hw->ledctl_default = ledctl;
+                        /* Turn off LED0 */
+                        ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
+                                    E1000_LEDCTL_LED0_BLINK |
+                                    E1000_LEDCTL_LED0_MODE_MASK);
+                        ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
+                                   E1000_LEDCTL_LED0_MODE_SHIFT);
+                        ew32(LEDCTL, ledctl);
+                } else if (hw->media_type == e1000_media_type_copper)
+                        ew32(LEDCTL, hw->ledctl_mode1);
+                break;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Restores the saved state of the SW controlable LED.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_cleanup_led(struct e1000_hw *hw)
 {
-    s32 ret_val = E1000_SUCCESS;
-
-    DEBUGFUNC("e1000_cleanup_led");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        /* No cleanup necessary */
-        break;
-    case e1000_82541:
-    case e1000_82547:
-    case e1000_82541_rev_2:
-    case e1000_82547_rev_2:
-        /* Turn on PHY Smart Power Down (if previously enabled) */
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                      hw->phy_spd_default);
-        if (ret_val)
-            return ret_val;
-        /* Fall Through */
-    default:
-        if (hw->phy_type == e1000_phy_ife) {
-            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
-            break;
-        }
-        /* Restore LEDCTL settings */
-        ew32(LEDCTL, hw->ledctl_default);
-        break;
-    }
-
-    return E1000_SUCCESS;
+        s32 ret_val = E1000_SUCCESS;
+
+        DEBUGFUNC("e1000_cleanup_led");
+
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+        case e1000_82544:
+                /* No cleanup necessary */
+                break;
+        case e1000_82541:
+        case e1000_82547:
+        case e1000_82541_rev_2:
+        case e1000_82547_rev_2:
+                /* Turn on PHY Smart Power Down (if previously enabled) */
+                ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                              hw->phy_spd_default);
+                if (ret_val)
+                        return ret_val;
+                /* Fall Through */
+        default:
+                /* Restore LEDCTL settings */
+                ew32(LEDCTL, hw->ledctl_default);
+                break;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Turns on the software controllable LED
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_led_on - Turns on the software controllable LED
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_led_on(struct e1000_hw *hw)
 {
-    u32 ctrl = er32(CTRL);
-
-    DEBUGFUNC("e1000_led_on");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-        /* Set SW Defineable Pin 0 to turn on the LED */
-        ctrl |= E1000_CTRL_SWDPIN0;
-        ctrl |= E1000_CTRL_SWDPIO0;
-        break;
-    case e1000_82544:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Set SW Defineable Pin 0 to turn on the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else {
-            /* Clear SW Defineable Pin 0 to turn on the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        }
-        break;
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Clear SW Defineable Pin 0 to turn on the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else if (hw->phy_type == e1000_phy_ife) {
-            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
-        } else if (hw->media_type == e1000_media_type_copper) {
-            ew32(LEDCTL, hw->ledctl_mode2);
-            return E1000_SUCCESS;
-        }
-        break;
-    }
-
-    ew32(CTRL, ctrl);
-
-    return E1000_SUCCESS;
+        u32 ctrl = er32(CTRL);
+
+        DEBUGFUNC("e1000_led_on");
+
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+                /* Set SW Defineable Pin 0 to turn on the LED */
+                ctrl |= E1000_CTRL_SWDPIN0;
+                ctrl |= E1000_CTRL_SWDPIO0;
+                break;
+        case e1000_82544:
+                if (hw->media_type == e1000_media_type_fiber) {
+                        /* Set SW Defineable Pin 0 to turn on the LED */
+                        ctrl |= E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                } else {
+                        /* Clear SW Defineable Pin 0 to turn on the LED */
+                        ctrl &= ~E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                }
+                break;
+        default:
+                if (hw->media_type == e1000_media_type_fiber) {
+                        /* Clear SW Defineable Pin 0 to turn on the LED */
+                        ctrl &= ~E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                } else if (hw->media_type == e1000_media_type_copper) {
+                        ew32(LEDCTL, hw->ledctl_mode2);
+                        return E1000_SUCCESS;
+                }
+                break;
+        }
+
+        ew32(CTRL, ctrl);
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Turns off the software controllable LED
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_led_off - Turns off the software controllable LED
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_led_off(struct e1000_hw *hw)
 {
-    u32 ctrl = er32(CTRL);
-
-    DEBUGFUNC("e1000_led_off");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-        /* Clear SW Defineable Pin 0 to turn off the LED */
-        ctrl &= ~E1000_CTRL_SWDPIN0;
-        ctrl |= E1000_CTRL_SWDPIO0;
-        break;
-    case e1000_82544:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Clear SW Defineable Pin 0 to turn off the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else {
-            /* Set SW Defineable Pin 0 to turn off the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        }
-        break;
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Set SW Defineable Pin 0 to turn off the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else if (hw->phy_type == e1000_phy_ife) {
-            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
-        } else if (hw->media_type == e1000_media_type_copper) {
-            ew32(LEDCTL, hw->ledctl_mode1);
-            return E1000_SUCCESS;
-        }
-        break;
-    }
-
-    ew32(CTRL, ctrl);
-
-    return E1000_SUCCESS;
+        u32 ctrl = er32(CTRL);
+
+        DEBUGFUNC("e1000_led_off");
+
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+        case e1000_82543:
+                /* Clear SW Defineable Pin 0 to turn off the LED */
+                ctrl &= ~E1000_CTRL_SWDPIN0;
+                ctrl |= E1000_CTRL_SWDPIO0;
+                break;
+        case e1000_82544:
+                if (hw->media_type == e1000_media_type_fiber) {
+                        /* Clear SW Defineable Pin 0 to turn off the LED */
+                        ctrl &= ~E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                } else {
+                        /* Set SW Defineable Pin 0 to turn off the LED */
+                        ctrl |= E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                }
+                break;
+        default:
+                if (hw->media_type == e1000_media_type_fiber) {
+                        /* Set SW Defineable Pin 0 to turn off the LED */
+                        ctrl |= E1000_CTRL_SWDPIN0;
+                        ctrl |= E1000_CTRL_SWDPIO0;
+                } else if (hw->media_type == e1000_media_type_copper) {
+                        ew32(LEDCTL, hw->ledctl_mode1);
+                        return E1000_SUCCESS;
+                }
+                break;
+        }
+
+        ew32(CTRL, ctrl);
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Clears all hardware statistics counters.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
 {
-    volatile u32 temp;
-
-    temp = er32(CRCERRS);
-    temp = er32(SYMERRS);
-    temp = er32(MPC);
-    temp = er32(SCC);
-    temp = er32(ECOL);
-    temp = er32(MCC);
-    temp = er32(LATECOL);
-    temp = er32(COLC);
-    temp = er32(DC);
-    temp = er32(SEC);
-    temp = er32(RLEC);
-    temp = er32(XONRXC);
-    temp = er32(XONTXC);
-    temp = er32(XOFFRXC);
-    temp = er32(XOFFTXC);
-    temp = er32(FCRUC);
-
-    if (hw->mac_type != e1000_ich8lan) {
-    temp = er32(PRC64);
-    temp = er32(PRC127);
-    temp = er32(PRC255);
-    temp = er32(PRC511);
-    temp = er32(PRC1023);
-    temp = er32(PRC1522);
-    }
-
-    temp = er32(GPRC);
-    temp = er32(BPRC);
-    temp = er32(MPRC);
-    temp = er32(GPTC);
-    temp = er32(GORCL);
-    temp = er32(GORCH);
-    temp = er32(GOTCL);
-    temp = er32(GOTCH);
-    temp = er32(RNBC);
-    temp = er32(RUC);
-    temp = er32(RFC);
-    temp = er32(ROC);
-    temp = er32(RJC);
-    temp = er32(TORL);
-    temp = er32(TORH);
-    temp = er32(TOTL);
-    temp = er32(TOTH);
-    temp = er32(TPR);
-    temp = er32(TPT);
-
-    if (hw->mac_type != e1000_ich8lan) {
-    temp = er32(PTC64);
-    temp = er32(PTC127);
-    temp = er32(PTC255);
-    temp = er32(PTC511);
-    temp = er32(PTC1023);
-    temp = er32(PTC1522);
-    }
-
-    temp = er32(MPTC);
-    temp = er32(BPTC);
-
-    if (hw->mac_type < e1000_82543) return;
-
-    temp = er32(ALGNERRC);
-    temp = er32(RXERRC);
-    temp = er32(TNCRS);
-    temp = er32(CEXTERR);
-    temp = er32(TSCTC);
-    temp = er32(TSCTFC);
-
-    if (hw->mac_type <= e1000_82544) return;
-
-    temp = er32(MGTPRC);
-    temp = er32(MGTPDC);
-    temp = er32(MGTPTC);
-
-    if (hw->mac_type <= e1000_82547_rev_2) return;
-
-    temp = er32(IAC);
-    temp = er32(ICRXOC);
-
-    if (hw->mac_type == e1000_ich8lan) return;
-
-    temp = er32(ICRXPTC);
-    temp = er32(ICRXATC);
-    temp = er32(ICTXPTC);
-    temp = er32(ICTXATC);
-    temp = er32(ICTXQEC);
-    temp = er32(ICTXQMTC);
-    temp = er32(ICRXDMTC);
-}
-
-/******************************************************************************
- * Resets Adaptive IFS to its default state.
- *
- * hw - Struct containing variables accessed by shared code
+        volatile u32 temp;
+
+        temp = er32(CRCERRS);
+        temp = er32(SYMERRS);
+        temp = er32(MPC);
+        temp = er32(SCC);
+        temp = er32(ECOL);
+        temp = er32(MCC);
+        temp = er32(LATECOL);
+        temp = er32(COLC);
+        temp = er32(DC);
+        temp = er32(SEC);
+        temp = er32(RLEC);
+        temp = er32(XONRXC);
+        temp = er32(XONTXC);
+        temp = er32(XOFFRXC);
+        temp = er32(XOFFTXC);
+        temp = er32(FCRUC);
+
+        temp = er32(PRC64);
+        temp = er32(PRC127);
+        temp = er32(PRC255);
+        temp = er32(PRC511);
+        temp = er32(PRC1023);
+        temp = er32(PRC1522);
+
+        temp = er32(GPRC);
+        temp = er32(BPRC);
+        temp = er32(MPRC);
+        temp = er32(GPTC);
+        temp = er32(GORCL);
+        temp = er32(GORCH);
+        temp = er32(GOTCL);
+        temp = er32(GOTCH);
+        temp = er32(RNBC);
+        temp = er32(RUC);
+        temp = er32(RFC);
+        temp = er32(ROC);
+        temp = er32(RJC);
+        temp = er32(TORL);
+        temp = er32(TORH);
+        temp = er32(TOTL);
+        temp = er32(TOTH);
+        temp = er32(TPR);
+        temp = er32(TPT);
+
+        temp = er32(PTC64);
+        temp = er32(PTC127);
+        temp = er32(PTC255);
+        temp = er32(PTC511);
+        temp = er32(PTC1023);
+        temp = er32(PTC1522);
+
+        temp = er32(MPTC);
+        temp = er32(BPTC);
+
+        if (hw->mac_type < e1000_82543)
+                return;
+
+        temp = er32(ALGNERRC);
+        temp = er32(RXERRC);
+        temp = er32(TNCRS);
+        temp = er32(CEXTERR);
+        temp = er32(TSCTC);
+        temp = er32(TSCTFC);
+
+        if (hw->mac_type <= e1000_82544)
+                return;
+
+        temp = er32(MGTPRC);
+        temp = er32(MGTPDC);
+        temp = er32(MGTPTC);
+}
+
+/**
+ * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Call this after e1000_init_hw. You may override the IFS defaults by setting
  * hw->ifs_params_forced to true. However, you must initialize hw->
  * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
  * before calling this function.
- *****************************************************************************/
+ */
 void e1000_reset_adaptive(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_reset_adaptive");
-
-    if (hw->adaptive_ifs) {
-        if (!hw->ifs_params_forced) {
-            hw->current_ifs_val = 0;
-            hw->ifs_min_val = IFS_MIN;
-            hw->ifs_max_val = IFS_MAX;
-            hw->ifs_step_size = IFS_STEP;
-            hw->ifs_ratio = IFS_RATIO;
-        }
-        hw->in_ifs_mode = false;
-        ew32(AIT, 0);
-    } else {
-        DEBUGOUT("Not in Adaptive IFS mode!\n");
-    }
+        DEBUGFUNC("e1000_reset_adaptive");
+
+        if (hw->adaptive_ifs) {
+                if (!hw->ifs_params_forced) {
+                        hw->current_ifs_val = 0;
+                        hw->ifs_min_val = IFS_MIN;
+                        hw->ifs_max_val = IFS_MAX;
+                        hw->ifs_step_size = IFS_STEP;
+                        hw->ifs_ratio = IFS_RATIO;
+                }
+                hw->in_ifs_mode = false;
+                ew32(AIT, 0);
+        } else {
+                DEBUGOUT("Not in Adaptive IFS mode!\n");
+        }
 }
 
-/******************************************************************************
+/**
+ * e1000_update_adaptive - update adaptive IFS
+ * @hw: Struct containing variables accessed by shared code
+ * @tx_packets: Number of transmits since last callback
+ * @total_collisions: Number of collisions since last callback
+ *
  * Called during the callback/watchdog routine to update IFS value based on
  * the ratio of transmits to collisions.
- *
- * hw - Struct containing variables accessed by shared code
- * tx_packets - Number of transmits since last callback
- * total_collisions - Number of collisions since last callback
- *****************************************************************************/
+ */
 void e1000_update_adaptive(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_update_adaptive");
-
-    if (hw->adaptive_ifs) {
-        if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
-            if (hw->tx_packet_delta > MIN_NUM_XMITS) {
-                hw->in_ifs_mode = true;
-                if (hw->current_ifs_val < hw->ifs_max_val) {
-                    if (hw->current_ifs_val == 0)
-                        hw->current_ifs_val = hw->ifs_min_val;
-                    else
-                        hw->current_ifs_val += hw->ifs_step_size;
-                    ew32(AIT, hw->current_ifs_val);
-                }
-            }
-        } else {
-            if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
-                hw->current_ifs_val = 0;
-                hw->in_ifs_mode = false;
-                ew32(AIT, 0);
-            }
-        }
-    } else {
-        DEBUGOUT("Not in Adaptive IFS mode!\n");
-    }
+        DEBUGFUNC("e1000_update_adaptive");
+
+        if (hw->adaptive_ifs) {
+                if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
+                        if (hw->tx_packet_delta > MIN_NUM_XMITS) {
+                                hw->in_ifs_mode = true;
+                                if (hw->current_ifs_val < hw->ifs_max_val) {
+                                        if (hw->current_ifs_val == 0)
+                                                hw->current_ifs_val =
+                                                    hw->ifs_min_val;
+                                        else
+                                                hw->current_ifs_val +=
+                                                    hw->ifs_step_size;
+                                        ew32(AIT, hw->current_ifs_val);
+                                }
+                        }
+                } else {
+                        if (hw->in_ifs_mode
+                            && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
+                                hw->current_ifs_val = 0;
+                                hw->in_ifs_mode = false;
+                                ew32(AIT, 0);
+                        }
+                }
+        } else {
+                DEBUGOUT("Not in Adaptive IFS mode!\n");
+        }
 }
 
-/******************************************************************************
- * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
+/**
+ * e1000_tbi_adjust_stats
+ * @hw: Struct containing variables accessed by shared code
+ * @frame_len: The length of the frame in question
+ * @mac_addr: The Ethernet destination address of the frame in question
  *
- * hw - Struct containing variables accessed by shared code
- * frame_len - The length of the frame in question
- * mac_addr - The Ethernet destination address of the frame in question
- *****************************************************************************/
+ * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
+ */
 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
                             u32 frame_len, u8 *mac_addr)
 {
-    u64 carry_bit;
-
-    /* First adjust the frame length. */
-    frame_len--;
-    /* We need to adjust the statistics counters, since the hardware
-     * counters overcount this packet as a CRC error and undercount
-     * the packet as a good packet
-     */
-    /* This packet should not be counted as a CRC error.    */
-    stats->crcerrs--;
-    /* This packet does count as a Good Packet Received.    */
-    stats->gprc++;
-
-    /* Adjust the Good Octets received counters             */
-    carry_bit = 0x80000000 & stats->gorcl;
-    stats->gorcl += frame_len;
-    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
-     * Received Count) was one before the addition,
-     * AND it is zero after, then we lost the carry out,
-     * need to add one to Gorch (Good Octets Received Count High).
-     * This could be simplified if all environments supported
-     * 64-bit integers.
-     */
-    if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
-        stats->gorch++;
-    /* Is this a broadcast or multicast?  Check broadcast first,
-     * since the test for a multicast frame will test positive on
-     * a broadcast frame.
-     */
-    if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
-        /* Broadcast packet */
-        stats->bprc++;
-    else if (*mac_addr & 0x01)
-        /* Multicast packet */
-        stats->mprc++;
-
-    if (frame_len == hw->max_frame_size) {
-        /* In this case, the hardware has overcounted the number of
-         * oversize frames.
-         */
-        if (stats->roc > 0)
-            stats->roc--;
-    }
-
-    /* Adjust the bin counters when the extra byte put the frame in the
-     * wrong bin. Remember that the frame_len was adjusted above.
-     */
-    if (frame_len == 64) {
-        stats->prc64++;
-        stats->prc127--;
-    } else if (frame_len == 127) {
-        stats->prc127++;
-        stats->prc255--;
-    } else if (frame_len == 255) {
-        stats->prc255++;
-        stats->prc511--;
-    } else if (frame_len == 511) {
-        stats->prc511++;
-        stats->prc1023--;
-    } else if (frame_len == 1023) {
-        stats->prc1023++;
-        stats->prc1522--;
-    } else if (frame_len == 1522) {
-        stats->prc1522++;
-    }
+        u64 carry_bit;
+
+        /* First adjust the frame length. */
+        frame_len--;
+        /* We need to adjust the statistics counters, since the hardware
+         * counters overcount this packet as a CRC error and undercount
+         * the packet as a good packet
+         */
+        /* This packet should not be counted as a CRC error.    */
+        stats->crcerrs--;
+        /* This packet does count as a Good Packet Received.    */
+        stats->gprc++;
+
+        /* Adjust the Good Octets received counters             */
+        carry_bit = 0x80000000 & stats->gorcl;
+        stats->gorcl += frame_len;
+        /* If the high bit of Gorcl (the low 32 bits of the Good Octets
+         * Received Count) was one before the addition,
+         * AND it is zero after, then we lost the carry out,
+         * need to add one to Gorch (Good Octets Received Count High).
+         * This could be simplified if all environments supported
+         * 64-bit integers.
+         */
+        if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
+                stats->gorch++;
+        /* Is this a broadcast or multicast?  Check broadcast first,
+         * since the test for a multicast frame will test positive on
+         * a broadcast frame.
+         */
+        if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
+                /* Broadcast packet */
+                stats->bprc++;
+        else if (*mac_addr & 0x01)
+                /* Multicast packet */
+                stats->mprc++;
+
+        if (frame_len == hw->max_frame_size) {
+                /* In this case, the hardware has overcounted the number of
+                 * oversize frames.
+                 */
+                if (stats->roc > 0)
+                        stats->roc--;
+        }
+
+        /* Adjust the bin counters when the extra byte put the frame in the
+         * wrong bin. Remember that the frame_len was adjusted above.
+         */
+        if (frame_len == 64) {
+                stats->prc64++;
+                stats->prc127--;
+        } else if (frame_len == 127) {
+                stats->prc127++;
+                stats->prc255--;
+        } else if (frame_len == 255) {
+                stats->prc255++;
+                stats->prc511--;
+        } else if (frame_len == 511) {
+                stats->prc511++;
+                stats->prc1023--;
+        } else if (frame_len == 1023) {
+                stats->prc1023++;
+                stats->prc1522--;
+        } else if (frame_len == 1522) {
+                stats->prc1522++;
+        }
 }
 
-/******************************************************************************
- * Gets the current PCI bus type, speed, and width of the hardware
+/**
+ * e1000_get_bus_info
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Gets the current PCI bus type, speed, and width of the hardware
+ */
 void e1000_get_bus_info(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 pci_ex_link_status;
-    u32 status;
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-        hw->bus_type = e1000_bus_type_pci;
-        hw->bus_speed = e1000_bus_speed_unknown;
-        hw->bus_width = e1000_bus_width_unknown;
-        break;
-    case e1000_82571:
-    case e1000_82572:
-    case e1000_82573:
-    case e1000_80003es2lan:
-        hw->bus_type = e1000_bus_type_pci_express;
-        hw->bus_speed = e1000_bus_speed_2500;
-        ret_val = e1000_read_pcie_cap_reg(hw,
-                                      PCI_EX_LINK_STATUS,
-                                      &pci_ex_link_status);
-        if (ret_val)
-            hw->bus_width = e1000_bus_width_unknown;
-        else
-            hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
-                          PCI_EX_LINK_WIDTH_SHIFT;
-        break;
-    case e1000_ich8lan:
-        hw->bus_type = e1000_bus_type_pci_express;
-        hw->bus_speed = e1000_bus_speed_2500;
-        hw->bus_width = e1000_bus_width_pciex_1;
-        break;
-    default:
-        status = er32(STATUS);
-        hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
-                       e1000_bus_type_pcix : e1000_bus_type_pci;
-
-        if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
-            hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
-                            e1000_bus_speed_66 : e1000_bus_speed_120;
-        } else if (hw->bus_type == e1000_bus_type_pci) {
-            hw->bus_speed = (status & E1000_STATUS_PCI66) ?
-                            e1000_bus_speed_66 : e1000_bus_speed_33;
-        } else {
-            switch (status & E1000_STATUS_PCIX_SPEED) {
-            case E1000_STATUS_PCIX_SPEED_66:
-                hw->bus_speed = e1000_bus_speed_66;
-                break;
-            case E1000_STATUS_PCIX_SPEED_100:
-                hw->bus_speed = e1000_bus_speed_100;
-                break;
-            case E1000_STATUS_PCIX_SPEED_133:
-                hw->bus_speed = e1000_bus_speed_133;
-                break;
-            default:
-                hw->bus_speed = e1000_bus_speed_reserved;
-                break;
-            }
-        }
-        hw->bus_width = (status & E1000_STATUS_BUS64) ?
-                        e1000_bus_width_64 : e1000_bus_width_32;
-        break;
-    }
+        u32 status;
+
+        switch (hw->mac_type) {
+        case e1000_82542_rev2_0:
+        case e1000_82542_rev2_1:
+                hw->bus_type = e1000_bus_type_pci;
+                hw->bus_speed = e1000_bus_speed_unknown;
+                hw->bus_width = e1000_bus_width_unknown;
+                break;
+        default:
+                status = er32(STATUS);
+                hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
+                    e1000_bus_type_pcix : e1000_bus_type_pci;
+
+                if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
+                        hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
+                            e1000_bus_speed_66 : e1000_bus_speed_120;
+                } else if (hw->bus_type == e1000_bus_type_pci) {
+                        hw->bus_speed = (status & E1000_STATUS_PCI66) ?
+                            e1000_bus_speed_66 : e1000_bus_speed_33;
+                } else {
+                        switch (status & E1000_STATUS_PCIX_SPEED) {
+                        case E1000_STATUS_PCIX_SPEED_66:
+                                hw->bus_speed = e1000_bus_speed_66;
+                                break;
+                        case E1000_STATUS_PCIX_SPEED_100:
+                                hw->bus_speed = e1000_bus_speed_100;
+                                break;
+                        case E1000_STATUS_PCIX_SPEED_133:
+                                hw->bus_speed = e1000_bus_speed_133;
+                                break;
+                        default:
+                                hw->bus_speed = e1000_bus_speed_reserved;
+                                break;
+                        }
+                }
+                hw->bus_width = (status & E1000_STATUS_BUS64) ?
+                    e1000_bus_width_64 : e1000_bus_width_32;
+                break;
+        }
 }
 
-/******************************************************************************
+/**
+ * e1000_write_reg_io
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset to write to
+ * @value: value to write
+ *
  * Writes a value to one of the devices registers using port I/O (as opposed to
  * memory mapped I/O). Only 82544 and newer devices support port I/O.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset to write to
- * value - value to write
- *****************************************************************************/
+ */
 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
 {
-    unsigned long io_addr = hw->io_base;
-    unsigned long io_data = hw->io_base + 4;
+        unsigned long io_addr = hw->io_base;
+        unsigned long io_data = hw->io_base + 4;
 
-    e1000_io_write(hw, io_addr, offset);
-    e1000_io_write(hw, io_data, value);
+        e1000_io_write(hw, io_addr, offset);
+        e1000_io_write(hw, io_data, value);
 }
 
-/******************************************************************************
- * Estimates the cable length.
- *
- * hw - Struct containing variables accessed by shared code
- * min_length - The estimated minimum length
- * max_length - The estimated maximum length
+/**
+ * e1000_get_cable_length - Estimates the cable length.
+ * @hw: Struct containing variables accessed by shared code
+ * @min_length: The estimated minimum length
+ * @max_length: The estimated maximum length
  *
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
@@ -6528,185 +4842,115 @@ static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
  * So for M88 phy's, this function interprets the one value returned from the
  * register to the minimum and maximum range.
  * For IGP phy's, the function calculates the range by the AGC registers.
- *****************************************************************************/
+ */
 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
                                   u16 *max_length)
 {
-    s32 ret_val;
-    u16 agc_value = 0;
-    u16 i, phy_data;
-    u16 cable_length;
-
-    DEBUGFUNC("e1000_get_cable_length");
-
-    *min_length = *max_length = 0;
-
-    /* Use old method for Phy older than IGP */
-    if (hw->phy_type == e1000_phy_m88) {
-
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-                       M88E1000_PSSR_CABLE_LENGTH_SHIFT;
-
-        /* Convert the enum value to ranged values */
-        switch (cable_length) {
-        case e1000_cable_length_50:
-            *min_length = 0;
-            *max_length = e1000_igp_cable_length_50;
-            break;
-        case e1000_cable_length_50_80:
-            *min_length = e1000_igp_cable_length_50;
-            *max_length = e1000_igp_cable_length_80;
-            break;
-        case e1000_cable_length_80_110:
-            *min_length = e1000_igp_cable_length_80;
-            *max_length = e1000_igp_cable_length_110;
-            break;
-        case e1000_cable_length_110_140:
-            *min_length = e1000_igp_cable_length_110;
-            *max_length = e1000_igp_cable_length_140;
-            break;
-        case e1000_cable_length_140:
-            *min_length = e1000_igp_cable_length_140;
-            *max_length = e1000_igp_cable_length_170;
-            break;
-        default:
-            return -E1000_ERR_PHY;
-            break;
-        }
-    } else if (hw->phy_type == e1000_phy_gg82563) {
-        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
-
-        switch (cable_length) {
-        case e1000_gg_cable_length_60:
-            *min_length = 0;
-            *max_length = e1000_igp_cable_length_60;
-            break;
-        case e1000_gg_cable_length_60_115:
-            *min_length = e1000_igp_cable_length_60;
-            *max_length = e1000_igp_cable_length_115;
-            break;
-        case e1000_gg_cable_length_115_150:
-            *min_length = e1000_igp_cable_length_115;
-            *max_length = e1000_igp_cable_length_150;
-            break;
-        case e1000_gg_cable_length_150:
-            *min_length = e1000_igp_cable_length_150;
-            *max_length = e1000_igp_cable_length_180;
-            break;
-        default:
-            return -E1000_ERR_PHY;
-            break;
-        }
-    } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
-        u16 cur_agc_value;
-        u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
-        u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-                                                         {IGP01E1000_PHY_AGC_A,
-                                                          IGP01E1000_PHY_AGC_B,
-                                                          IGP01E1000_PHY_AGC_C,
-                                                          IGP01E1000_PHY_AGC_D};
-        /* Read the AGC registers for all channels */
-        for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-
-            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
-
-            /* Value bound check. */
-            if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
-                (cur_agc_value == 0))
-                return -E1000_ERR_PHY;
-
-            agc_value += cur_agc_value;
-
-            /* Update minimal AGC value. */
-            if (min_agc_value > cur_agc_value)
-                min_agc_value = cur_agc_value;
-        }
-
-        /* Remove the minimal AGC result for length < 50m */
-        if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
-            agc_value -= min_agc_value;
-
-            /* Get the average length of the remaining 3 channels */
-            agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
-        } else {
-            /* Get the average length of all the 4 channels. */
-            agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
-        }
-
-        /* Set the range of the calculated length. */
-        *min_length = ((e1000_igp_cable_length_table[agc_value] -
-                       IGP01E1000_AGC_RANGE) > 0) ?
-                       (e1000_igp_cable_length_table[agc_value] -
-                       IGP01E1000_AGC_RANGE) : 0;
-        *max_length = e1000_igp_cable_length_table[agc_value] +
-                      IGP01E1000_AGC_RANGE;
-    } else if (hw->phy_type == e1000_phy_igp_2 ||
-               hw->phy_type == e1000_phy_igp_3) {
-        u16 cur_agc_index, max_agc_index = 0;
-        u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
-        u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
-                                                         {IGP02E1000_PHY_AGC_A,
-                                                          IGP02E1000_PHY_AGC_B,
-                                                          IGP02E1000_PHY_AGC_C,
-                                                          IGP02E1000_PHY_AGC_D};
-        /* Read the AGC registers for all channels */
-        for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
-            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            /* Getting bits 15:9, which represent the combination of course and
-             * fine gain values.  The result is a number that can be put into
-             * the lookup table to obtain the approximate cable length. */
-            cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
-                            IGP02E1000_AGC_LENGTH_MASK;
-
-            /* Array index bound check. */
-            if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
-                (cur_agc_index == 0))
-                return -E1000_ERR_PHY;
-
-            /* Remove min & max AGC values from calculation. */
-            if (e1000_igp_2_cable_length_table[min_agc_index] >
-                e1000_igp_2_cable_length_table[cur_agc_index])
-                min_agc_index = cur_agc_index;
-            if (e1000_igp_2_cable_length_table[max_agc_index] <
-                e1000_igp_2_cable_length_table[cur_agc_index])
-                max_agc_index = cur_agc_index;
-
-            agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
-        }
-
-        agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
-                      e1000_igp_2_cable_length_table[max_agc_index]);
-        agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
-
-        /* Calculate cable length with the error range of +/- 10 meters. */
-        *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
-                       (agc_value - IGP02E1000_AGC_RANGE) : 0;
-        *max_length = agc_value + IGP02E1000_AGC_RANGE;
-    }
-
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 agc_value = 0;
+        u16 i, phy_data;
+        u16 cable_length;
+
+        DEBUGFUNC("e1000_get_cable_length");
+
+        *min_length = *max_length = 0;
+
+        /* Use old method for Phy older than IGP */
+        if (hw->phy_type == e1000_phy_m88) {
+
+                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
+                cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
+                    M88E1000_PSSR_CABLE_LENGTH_SHIFT;
+
+                /* Convert the enum value to ranged values */
+                switch (cable_length) {
+                case e1000_cable_length_50:
+                        *min_length = 0;
+                        *max_length = e1000_igp_cable_length_50;
+                        break;
+                case e1000_cable_length_50_80:
+                        *min_length = e1000_igp_cable_length_50;
+                        *max_length = e1000_igp_cable_length_80;
+                        break;
+                case e1000_cable_length_80_110:
+                        *min_length = e1000_igp_cable_length_80;
+                        *max_length = e1000_igp_cable_length_110;
+                        break;
+                case e1000_cable_length_110_140:
+                        *min_length = e1000_igp_cable_length_110;
+                        *max_length = e1000_igp_cable_length_140;
+                        break;
+                case e1000_cable_length_140:
+                        *min_length = e1000_igp_cable_length_140;
+                        *max_length = e1000_igp_cable_length_170;
+                        break;
+                default:
+                        return -E1000_ERR_PHY;
+                        break;
+                }
+        } else if (hw->phy_type == e1000_phy_igp) {     /* For IGP PHY */
+                u16 cur_agc_value;
+                u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
+                u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+                    { IGP01E1000_PHY_AGC_A,
+                        IGP01E1000_PHY_AGC_B,
+                        IGP01E1000_PHY_AGC_C,
+                        IGP01E1000_PHY_AGC_D
+                };
+                /* Read the AGC registers for all channels */
+                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+
+                        ret_val =
+                            e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
+                        if (ret_val)
+                                return ret_val;
+
+                        cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
+
+                        /* Value bound check. */
+                        if ((cur_agc_value >=
+                             IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
+                            || (cur_agc_value == 0))
+                                return -E1000_ERR_PHY;
+
+                        agc_value += cur_agc_value;
+
+                        /* Update minimal AGC value. */
+                        if (min_agc_value > cur_agc_value)
+                                min_agc_value = cur_agc_value;
+                }
+
+                /* Remove the minimal AGC result for length < 50m */
+                if (agc_value <
+                    IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
+                        agc_value -= min_agc_value;
+
+                        /* Get the average length of the remaining 3 channels */
+                        agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
+                } else {
+                        /* Get the average length of all the 4 channels. */
+                        agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
+                }
+
+                /* Set the range of the calculated length. */
+                *min_length = ((e1000_igp_cable_length_table[agc_value] -
+                                IGP01E1000_AGC_RANGE) > 0) ?
+                    (e1000_igp_cable_length_table[agc_value] -
+                     IGP01E1000_AGC_RANGE) : 0;
+                *max_length = e1000_igp_cable_length_table[agc_value] +
+                    IGP01E1000_AGC_RANGE;
+        }
+
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Check the cable polarity
- *
- * hw - Struct containing variables accessed by shared code
- * polarity - output parameter : 0 - Polarity is not reversed
+/**
+ * e1000_check_polarity - Check the cable polarity
+ * @hw: Struct containing variables accessed by shared code
+ * @polarity: output parameter : 0 - Polarity is not reversed
  *                               1 - Polarity is reversed.
  *
  * returns: - E1000_ERR_XXX
@@ -6717,73 +4961,65 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
  * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
  * return 0.  If the link speed is 1000 Mbps the polarity status is in the
  * IGP01E1000_PHY_PCS_INIT_REG.
- *****************************************************************************/
+ */
 static s32 e1000_check_polarity(struct e1000_hw *hw,
                                 e1000_rev_polarity *polarity)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_polarity");
-
-    if ((hw->phy_type == e1000_phy_m88) ||
-        (hw->phy_type == e1000_phy_gg82563)) {
-        /* return the Polarity bit in the Status register. */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
-                     M88E1000_PSSR_REV_POLARITY_SHIFT) ?
-                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-
-    } else if (hw->phy_type == e1000_phy_igp ||
-              hw->phy_type == e1000_phy_igp_3 ||
-              hw->phy_type == e1000_phy_igp_2) {
-        /* Read the Status register to check the speed */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
-         * find the polarity status */
-        if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-           IGP01E1000_PSSR_SPEED_1000MBPS) {
-
-            /* Read the GIG initialization PCS register (0x00B4) */
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            /* Check the polarity bits */
-            *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
-                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-        } else {
-            /* For 10 Mbps, read the polarity bit in the status register. (for
-             * 100 Mbps this bit is always 0) */
-            *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
-                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-        }
-    } else if (hw->phy_type == e1000_phy_ife) {
-        ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
-                     IFE_PESC_POLARITY_REVERSED_SHIFT) ?
-                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-    }
-    return E1000_SUCCESS;
+        s32 ret_val;
+        u16 phy_data;
+
+        DEBUGFUNC("e1000_check_polarity");
+
+        if (hw->phy_type == e1000_phy_m88) {
+                /* return the Polarity bit in the Status register. */
+                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
+                *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
+                             M88E1000_PSSR_REV_POLARITY_SHIFT) ?
+                    e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
+
+        } else if (hw->phy_type == e1000_phy_igp) {
+                /* Read the Status register to check the speed */
+                ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
+                 * find the polarity status */
+                if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+                    IGP01E1000_PSSR_SPEED_1000MBPS) {
+
+                        /* Read the GIG initialization PCS register (0x00B4) */
+                        ret_val =
+                            e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
+                                               &phy_data);
+                        if (ret_val)
+                                return ret_val;
+
+                        /* Check the polarity bits */
+                        *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
+                            e1000_rev_polarity_reversed :
+                            e1000_rev_polarity_normal;
+                } else {
+                        /* For 10 Mbps, read the polarity bit in the status register. (for
+                         * 100 Mbps this bit is always 0) */
+                        *polarity =
+                            (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
+                            e1000_rev_polarity_reversed :
+                            e1000_rev_polarity_normal;
+                }
+        }
+        return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Check if Downshift occured
- *
- * hw - Struct containing variables accessed by shared code
- * downshift - output parameter : 0 - No Downshift ocured.
- *                                1 - Downshift ocured.
+/**
+ * e1000_check_downshift - Check if Downshift occurred
+ * @hw: Struct containing variables accessed by shared code
+ * @downshift: output parameter : 0 - No Downshift occurred.
+ *                                1 - Downshift occurred.
  *
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
@@ -6792,2041 +5028,607 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
  * Link Health register.  In IGP this bit is latched high, so the driver must
  * read it immediately after link is established.
- *****************************************************************************/
+ */
 static s32 e1000_check_downshift(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_downshift");
-
-    if (hw->phy_type == e1000_phy_igp ||
-        hw->phy_type == e1000_phy_igp_3 ||
-        hw->phy_type == e1000_phy_igp_2) {
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
-    } else if ((hw->phy_type == e1000_phy_m88) ||
-               (hw->phy_type == e1000_phy_gg82563)) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
-                               M88E1000_PSSR_DOWNSHIFT_SHIFT;
-    } else if (hw->phy_type == e1000_phy_ife) {
-        /* e1000_phy_ife supports 10/100 speed only */
-        hw->speed_downgraded = false;
-    }
-
-    return E1000_SUCCESS;
-}
+        s32 ret_val;
+        u16 phy_data;
 
-/*****************************************************************************
- *
- * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
- * gigabit link is achieved to improve link quality.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_PHY if fail to read/write the PHY
- *            E1000_SUCCESS at any other case.
- *
- ****************************************************************************/
+        DEBUGFUNC("e1000_check_downshift");
 
-static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
-{
-    s32 ret_val;
-    u16 phy_data, phy_saved_data, speed, duplex, i;
-    u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-                                        {IGP01E1000_PHY_AGC_PARAM_A,
-                                        IGP01E1000_PHY_AGC_PARAM_B,
-                                        IGP01E1000_PHY_AGC_PARAM_C,
-                                        IGP01E1000_PHY_AGC_PARAM_D};
-    u16 min_length, max_length;
-
-    DEBUGFUNC("e1000_config_dsp_after_link_change");
-
-    if (hw->phy_type != e1000_phy_igp)
-        return E1000_SUCCESS;
-
-    if (link_up) {
-        ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-        if (ret_val) {
-            DEBUGOUT("Error getting link speed and duplex\n");
-            return ret_val;
-        }
-
-        if (speed == SPEED_1000) {
-
-            ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
-            if (ret_val)
-                return ret_val;
-
-            if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
-                min_length >= e1000_igp_cable_length_50) {
-
-                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-                    ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
-                                                 &phy_data);
-                    if (ret_val)
-                        return ret_val;
-
-                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
-
-                    ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
-                                                  phy_data);
-                    if (ret_val)
-                        return ret_val;
-                }
-                hw->dsp_config_state = e1000_dsp_config_activated;
-            }
-
-            if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
-               (min_length < e1000_igp_cable_length_50)) {
-
-                u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
-                u32 idle_errs = 0;
-
-                /* clear previous idle error counts */
-                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
-                                             &phy_data);
-                if (ret_val)
-                    return ret_val;
-
-                for (i = 0; i < ffe_idle_err_timeout; i++) {
-                    udelay(1000);
-                    ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
-                                                 &phy_data);
-                    if (ret_val)
-                        return ret_val;
-
-                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
-                    if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
-                        hw->ffe_config_state = e1000_ffe_config_active;
-
-                        ret_val = e1000_write_phy_reg(hw,
-                                    IGP01E1000_PHY_DSP_FFE,
-                                    IGP01E1000_PHY_DSP_FFE_CM_CP);
-                        if (ret_val)
-                            return ret_val;
-                        break;
-                    }
-
-                    if (idle_errs)
-                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
-                }
-            }
-        }
-    } else {
-        if (hw->dsp_config_state == e1000_dsp_config_activated) {
-            /* Save off the current value of register 0x2F5B to be restored at
-             * the end of the routines. */
-            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            /* Disable the PHY transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if (ret_val)
-                return ret_val;
-            for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-                ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
-                if (ret_val)
-                    return ret_val;
-
-                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
-                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
-
-                ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
-                if (ret_val)
-                    return ret_val;
-            }
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            /* Now enable the transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            hw->dsp_config_state = e1000_dsp_config_enabled;
-        }
-
-        if (hw->ffe_config_state == e1000_ffe_config_active) {
-            /* Save off the current value of register 0x2F5B to be restored at
-             * the end of the routines. */
-            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            /* Disable the PHY transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
-                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            /* Now enable the transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            hw->ffe_config_state = e1000_ffe_config_enabled;
-        }
-    }
-    return E1000_SUCCESS;
-}
+        if (hw->phy_type == e1000_phy_igp) {
+                ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-/*****************************************************************************
- * Set PHY to class A mode
- * Assumes the following operations will follow to enable the new class mode.
- *  1. Do a PHY soft reset
- *  2. Restart auto-negotiation or force link.
- *
- * hw - Struct containing variables accessed by shared code
- ****************************************************************************/
-static s32 e1000_set_phy_mode(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 eeprom_data;
-
-    DEBUGFUNC("e1000_set_phy_mode");
-
-    if ((hw->mac_type == e1000_82545_rev_3) &&
-        (hw->media_type == e1000_media_type_copper)) {
-        ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
-        if (ret_val) {
-            return ret_val;
-        }
-
-        if ((eeprom_data != EEPROM_RESERVED_WORD) &&
-            (eeprom_data & EEPROM_PHY_CLASS_A)) {
-            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
-            if (ret_val)
-                return ret_val;
-
-            hw->phy_reset_disable = false;
-        }
-    }
-
-    return E1000_SUCCESS;
-}
+                hw->speed_downgraded =
+                    (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
+        } else if (hw->phy_type == e1000_phy_m88) {
+                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-/*****************************************************************************
- *
- * This function sets the lplu state according to the active flag.  When
- * activating lplu this function also disables smart speed and vise versa.
- * lplu will not be activated unless the device autonegotiation advertisment
- * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
- * hw: Struct containing variables accessed by shared code
- * active - true to enable lplu false to disable lplu.
- *
- * returns: - E1000_ERR_PHY if fail to read/write the PHY
- *            E1000_SUCCESS at any other case.
- *
- ****************************************************************************/
+                hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
+                    M88E1000_PSSR_DOWNSHIFT_SHIFT;
+        }
 
-static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
-{
-    u32 phy_ctrl = 0;
-    s32 ret_val;
-    u16 phy_data;
-    DEBUGFUNC("e1000_set_d3_lplu_state");
-
-    if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
-        && hw->phy_type != e1000_phy_igp_3)
-        return E1000_SUCCESS;
-
-    /* During driver activity LPLU should not be used or it will attain link
-     * from the lowest speeds starting from 10Mbps. The capability is used for
-     * Dx transitions and states */
-    if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
-        if (ret_val)
-            return ret_val;
-    } else if (hw->mac_type == e1000_ich8lan) {
-        /* MAC writes into PHY register based on the state transition
-         * and start auto-negotiation. SW driver can overwrite the settings
-         * in CSR PHY power control E1000_PHY_CTRL register. */
-        phy_ctrl = er32(PHY_CTRL);
-    } else {
-        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if (!active) {
-        if (hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            if (hw->mac_type == e1000_ich8lan) {
-                phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
-                ew32(PHY_CTRL, phy_ctrl);
-            } else {
-                phy_data &= ~IGP02E1000_PM_D3_LPLU;
-                ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                              phy_data);
-                if (ret_val)
-                    return ret_val;
-            }
-        }
-
-        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
-         * Dx states where the power conservation is most important.  During
-         * driver activity we should enable SmartSpeed, so performance is
-         * maintained. */
-        if (hw->smart_speed == e1000_smart_speed_on) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        } else if (hw->smart_speed == e1000_smart_speed_off) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-    } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
-               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
-               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
-
-        if (hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            phy_data |= IGP01E1000_GMII_FLEX_SPD;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            if (hw->mac_type == e1000_ich8lan) {
-                phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
-                ew32(PHY_CTRL, phy_ctrl);
-            } else {
-                phy_data |= IGP02E1000_PM_D3_LPLU;
-                ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                              phy_data);
-                if (ret_val)
-                    return ret_val;
-            }
-        }
-
-        /* When LPLU is enabled we should disable SmartSpeed */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
-        if (ret_val)
-            return ret_val;
-
-    }
-    return E1000_SUCCESS;
+        return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- *
- * This function sets the lplu d0 state according to the active flag.  When
- * activating lplu this function also disables smart speed and vise versa.
- * lplu will not be activated unless the device autonegotiation advertisment
- * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
- * hw: Struct containing variables accessed by shared code
- * active - true to enable lplu false to disable lplu.
+/**
+ * e1000_config_dsp_after_link_change
+ * @hw: Struct containing variables accessed by shared code
+ * @link_up: was link up at the time this was called
  *
  * returns: - E1000_ERR_PHY if fail to read/write the PHY
  *            E1000_SUCCESS at any other case.
  *
- ****************************************************************************/
-
-static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
-{
-    u32 phy_ctrl = 0;
-    s32 ret_val;
-    u16 phy_data;
-    DEBUGFUNC("e1000_set_d0_lplu_state");
-
-    if (hw->mac_type <= e1000_82547_rev_2)
-        return E1000_SUCCESS;
-
-    if (hw->mac_type == e1000_ich8lan) {
-        phy_ctrl = er32(PHY_CTRL);
-    } else {
-        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if (!active) {
-        if (hw->mac_type == e1000_ich8lan) {
-            phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
-            ew32(PHY_CTRL, phy_ctrl);
-        } else {
-            phy_data &= ~IGP02E1000_PM_D0_LPLU;
-            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
-         * Dx states where the power conservation is most important.  During
-         * driver activity we should enable SmartSpeed, so performance is
-         * maintained. */
-        if (hw->smart_speed == e1000_smart_speed_on) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        } else if (hw->smart_speed == e1000_smart_speed_off) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-
-    } else {
-
-        if (hw->mac_type == e1000_ich8lan) {
-            phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
-            ew32(PHY_CTRL, phy_ctrl);
-        } else {
-            phy_data |= IGP02E1000_PM_D0_LPLU;
-            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        /* When LPLU is enabled we should disable SmartSpeed */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
-        if (ret_val)
-            return ret_val;
-
-    }
-    return E1000_SUCCESS;
-}
+ * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
+ * gigabit link is achieved to improve link quality.
+ */
 
-/******************************************************************************
- * Change VCO speed register to improve Bit Error Rate performance of SERDES.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static s32 e1000_set_vco_speed(struct e1000_hw *hw)
+static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
 {
-    s32  ret_val;
-    u16 default_page = 0;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_set_vco_speed");
+        s32 ret_val;
+        u16 phy_data, phy_saved_data, speed, duplex, i;
+        u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+            { IGP01E1000_PHY_AGC_PARAM_A,
+                IGP01E1000_PHY_AGC_PARAM_B,
+                IGP01E1000_PHY_AGC_PARAM_C,
+                IGP01E1000_PHY_AGC_PARAM_D
+        };
+        u16 min_length, max_length;
+
+        DEBUGFUNC("e1000_config_dsp_after_link_change");
+
+        if (hw->phy_type != e1000_phy_igp)
+                return E1000_SUCCESS;
+
+        if (link_up) {
+                ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+                if (ret_val) {
+                        DEBUGOUT("Error getting link speed and duplex\n");
+                        return ret_val;
+                }
 
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-       break;
-    default:
-        return E1000_SUCCESS;
-    }
+                if (speed == SPEED_1000) {
+
+                        ret_val =
+                            e1000_get_cable_length(hw, &min_length,
+                                                   &max_length);
+                        if (ret_val)
+                                return ret_val;
+
+                        if ((hw->dsp_config_state == e1000_dsp_config_enabled)
+                            && min_length >= e1000_igp_cable_length_50) {
+
+                                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+                                        ret_val =
+                                            e1000_read_phy_reg(hw,
+                                                               dsp_reg_array[i],
+                                                               &phy_data);
+                                        if (ret_val)
+                                                return ret_val;
+
+                                        phy_data &=
+                                            ~IGP01E1000_PHY_EDAC_MU_INDEX;
+
+                                        ret_val =
+                                            e1000_write_phy_reg(hw,
+                                                                dsp_reg_array
+                                                                [i], phy_data);
+                                        if (ret_val)
+                                                return ret_val;
+                                }
+                                hw->dsp_config_state =
+                                    e1000_dsp_config_activated;
+                        }
+
+                        if ((hw->ffe_config_state == e1000_ffe_config_enabled)
+                            && (min_length < e1000_igp_cable_length_50)) {
+
+                                u16 ffe_idle_err_timeout =
+                                    FFE_IDLE_ERR_COUNT_TIMEOUT_20;
+                                u32 idle_errs = 0;
+
+                                /* clear previous idle error counts */
+                                ret_val =
+                                    e1000_read_phy_reg(hw, PHY_1000T_STATUS,
+                                                       &phy_data);
+                                if (ret_val)
+                                        return ret_val;
+
+                                for (i = 0; i < ffe_idle_err_timeout; i++) {
+                                        udelay(1000);
+                                        ret_val =
+                                            e1000_read_phy_reg(hw,
+                                                               PHY_1000T_STATUS,
+                                                               &phy_data);
+                                        if (ret_val)
+                                                return ret_val;
+
+                                        idle_errs +=
+                                            (phy_data &
+                                             SR_1000T_IDLE_ERROR_CNT);
+                                        if (idle_errs >
+                                            SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
+                                        {
+                                                hw->ffe_config_state =
+                                                    e1000_ffe_config_active;
+
+                                                ret_val =
+                                                    e1000_write_phy_reg(hw,
+                                                                        IGP01E1000_PHY_DSP_FFE,
+                                                                        IGP01E1000_PHY_DSP_FFE_CM_CP);
+                                                if (ret_val)
+                                                        return ret_val;
+                                                break;
+                                        }
+
+                                        if (idle_errs)
+                                                ffe_idle_err_timeout =
+                                                    FFE_IDLE_ERR_COUNT_TIMEOUT_100;
+                                }
+                        }
+                }
+        } else {
+                if (hw->dsp_config_state == e1000_dsp_config_activated) {
+                        /* Save off the current value of register 0x2F5B to be restored at
+                         * the end of the routines. */
+                        ret_val =
+                            e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+                        if (ret_val)
+                                return ret_val;
+
+                        /* Disable the PHY transmitter */
+                        ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+
+                        if (ret_val)
+                                return ret_val;
+
+                        mdelay(20);
+
+                        ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                      IGP01E1000_IEEE_FORCE_GIGA);
+                        if (ret_val)
+                                return ret_val;
+                        for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+                                ret_val =
+                                    e1000_read_phy_reg(hw, dsp_reg_array[i],
+                                                       &phy_data);
+                                if (ret_val)
+                                        return ret_val;
+
+                                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
+                                phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
+
+                                ret_val =
+                                    e1000_write_phy_reg(hw, dsp_reg_array[i],
+                                                        phy_data);
+                                if (ret_val)
+                                        return ret_val;
+                        }
+
+                        ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                      IGP01E1000_IEEE_RESTART_AUTONEG);
+                        if (ret_val)
+                                return ret_val;
+
+                        mdelay(20);
+
+                        /* Now enable the transmitter */
+                        ret_val =
+                            e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+                        if (ret_val)
+                                return ret_val;
+
+                        hw->dsp_config_state = e1000_dsp_config_enabled;
+                }
 
-    /* Set PHY register 30, page 5, bit 8 to 0 */
+                if (hw->ffe_config_state == e1000_ffe_config_active) {
+                        /* Save off the current value of register 0x2F5B to be restored at
+                         * the end of the routines. */
+                        ret_val =
+                            e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
-    if (ret_val)
-        return ret_val;
+                        if (ret_val)
+                                return ret_val;
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
-    if (ret_val)
-        return ret_val;
+                        /* Disable the PHY transmitter */
+                        ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
+                        if (ret_val)
+                                return ret_val;
 
-    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if (ret_val)
-        return ret_val;
+                        mdelay(20);
 
-    /* Set PHY register 30, page 4, bit 11 to 1 */
+                        ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                      IGP01E1000_IEEE_FORCE_GIGA);
+                        if (ret_val)
+                                return ret_val;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
+                                                IGP01E1000_PHY_DSP_FFE_DEFAULT);
+                        if (ret_val)
+                                return ret_val;
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
-    if (ret_val)
-        return ret_val;
+                        ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                      IGP01E1000_IEEE_RESTART_AUTONEG);
+                        if (ret_val)
+                                return ret_val;
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
+                        mdelay(20);
 
-    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if (ret_val)
-        return ret_val;
+                        /* Now enable the transmitter */
+                        ret_val =
+                            e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
-    if (ret_val)
-        return ret_val;
+                        if (ret_val)
+                                return ret_val;
 
-    return E1000_SUCCESS;
+                        hw->ffe_config_state = e1000_ffe_config_enabled;
+                }
+        }
+        return E1000_SUCCESS;
 }
 
-
-/*****************************************************************************
- * This function reads the cookie from ARC ram.
+/**
+ * e1000_set_phy_mode - Set PHY to class A mode
+ * @hw: Struct containing variables accessed by shared code
  *
- * returns: - E1000_SUCCESS .
- ****************************************************************************/
-static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
+ * Assumes the following operations will follow to enable the new class mode.
+ *  1. Do a PHY soft reset
+ *  2. Restart auto-negotiation or force link.
+ */
+static s32 e1000_set_phy_mode(struct e1000_hw *hw)
 {
-    u8 i;
-    u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
-    u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
-
-    length = (length >> 2);
-    offset = (offset >> 2);
-
-    for (i = 0; i < length; i++) {
-        *((u32 *)buffer + i) =
-            E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
-    }
-    return E1000_SUCCESS;
-}
+        s32 ret_val;
+        u16 eeprom_data;
 
+        DEBUGFUNC("e1000_set_phy_mode");
 
-/*****************************************************************************
- * This function checks whether the HOST IF is enabled for command operaton
- * and also checks whether the previous command is completed.
- * It busy waits in case of previous command is not completed.
- *
- * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
- *            timeout
- *          - E1000_SUCCESS for success.
- ****************************************************************************/
-static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
-{
-    u32 hicr;
-    u8 i;
-
-    /* Check that the host interface is enabled. */
-    hicr = er32(HICR);
-    if ((hicr & E1000_HICR_EN) == 0) {
-        DEBUGOUT("E1000_HOST_EN bit disabled.\n");
-        return -E1000_ERR_HOST_INTERFACE_COMMAND;
-    }
-    /* check the previous command is completed */
-    for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
-        hicr = er32(HICR);
-        if (!(hicr & E1000_HICR_C))
-            break;
-        mdelay(1);
-    }
-
-    if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
-        DEBUGOUT("Previous command timeout failed .\n");
-        return -E1000_ERR_HOST_INTERFACE_COMMAND;
-    }
-    return E1000_SUCCESS;
-}
+        if ((hw->mac_type == e1000_82545_rev_3) &&
+            (hw->media_type == e1000_media_type_copper)) {
+                ret_val =
+                    e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
+                                      &eeprom_data);
+                if (ret_val) {
+                        return ret_val;
+                }
 
-/*****************************************************************************
- * This function writes the buffer content at the offset given on the host if.
- * It also does alignment considerations to do the writes in most efficient way.
- * Also fills up the sum of the buffer in *buffer parameter.
- *
- * returns  - E1000_SUCCESS for success.
- ****************************************************************************/
-static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
-                                   u16 offset, u8 *sum)
-{
-    u8 *tmp;
-    u8 *bufptr = buffer;
-    u32 data = 0;
-    u16 remaining, i, j, prev_bytes;
-
-    /* sum = only sum of the data and it is not checksum */
-
-    if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
-        return -E1000_ERR_PARAM;
-    }
-
-    tmp = (u8 *)&data;
-    prev_bytes = offset & 0x3;
-    offset &= 0xFFFC;
-    offset >>= 2;
-
-    if (prev_bytes) {
-        data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
-        for (j = prev_bytes; j < sizeof(u32); j++) {
-            *(tmp + j) = *bufptr++;
-            *sum += *(tmp + j);
-        }
-        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
-        length -= j - prev_bytes;
-        offset++;
-    }
-
-    remaining = length & 0x3;
-    length -= remaining;
-
-    /* Calculate length in DWORDs */
-    length >>= 2;
-
-    /* The device driver writes the relevant command block into the
-     * ram area. */
-    for (i = 0; i < length; i++) {
-        for (j = 0; j < sizeof(u32); j++) {
-            *(tmp + j) = *bufptr++;
-            *sum += *(tmp + j);
-        }
-
-        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
-    }
-    if (remaining) {
-        for (j = 0; j < sizeof(u32); j++) {
-            if (j < remaining)
-                *(tmp + j) = *bufptr++;
-            else
-                *(tmp + j) = 0;
-
-            *sum += *(tmp + j);
-        }
-        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
-    }
-
-    return E1000_SUCCESS;
-}
+                if ((eeprom_data != EEPROM_RESERVED_WORD) &&
+                    (eeprom_data & EEPROM_PHY_CLASS_A)) {
+                        ret_val =
+                            e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
+                                                0x000B);
+                        if (ret_val)
+                                return ret_val;
+                        ret_val =
+                            e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
+                                                0x8104);
+                        if (ret_val)
+                                return ret_val;
+
+                        hw->phy_reset_disable = false;
+                }
+        }
 
+        return E1000_SUCCESS;
+}
 
-/*****************************************************************************
- * This function writes the command header after does the checksum calculation.
+/**
+ * e1000_set_d3_lplu_state - set d3 link power state
+ * @hw: Struct containing variables accessed by shared code
+ * @active: true to enable lplu false to disable lplu.
+ *
+ * This function sets the lplu state according to the active flag.  When
+ * activating lplu this function also disables smart speed and vise versa.
+ * lplu will not be activated unless the device autonegotiation advertisement
+ * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  *
- * returns  - E1000_SUCCESS for success.
- ****************************************************************************/
-static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
-                                      struct e1000_host_mng_command_header *hdr)
+ * returns: - E1000_ERR_PHY if fail to read/write the PHY
+ *            E1000_SUCCESS at any other case.
+ */
+static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
 {
-    u16 i;
-    u8 sum;
-    u8 *buffer;
-
-    /* Write the whole command header structure which includes sum of
-     * the buffer */
-
-    u16 length = sizeof(struct e1000_host_mng_command_header);
+        s32 ret_val;
+        u16 phy_data;
+        DEBUGFUNC("e1000_set_d3_lplu_state");
+
+        if (hw->phy_type != e1000_phy_igp)
+                return E1000_SUCCESS;
+
+        /* During driver activity LPLU should not be used or it will attain link
+         * from the lowest speeds starting from 10Mbps. The capability is used for
+         * Dx transitions and states */
+        if (hw->mac_type == e1000_82541_rev_2
+            || hw->mac_type == e1000_82547_rev_2) {
+                ret_val =
+                    e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
+                if (ret_val)
+                        return ret_val;
+        }
 
-    sum = hdr->checksum;
-    hdr->checksum = 0;
+        if (!active) {
+                if (hw->mac_type == e1000_82541_rev_2 ||
+                    hw->mac_type == e1000_82547_rev_2) {
+                        phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                                phy_data);
+                        if (ret_val)
+                                return ret_val;
+                }
 
-    buffer = (u8 *)hdr;
-    i = length;
-    while (i--)
-        sum += buffer[i];
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
+                 * Dx states where the power conservation is most important.  During
+                 * driver activity we should enable SmartSpeed, so performance is
+                 * maintained. */
+                if (hw->smart_speed == e1000_smart_speed_on) {
+                        ret_val =
+                            e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               &phy_data);
+                        if (ret_val)
+                                return ret_val;
+
+                        phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                                phy_data);
+                        if (ret_val)
+                                return ret_val;
+                } else if (hw->smart_speed == e1000_smart_speed_off) {
+                        ret_val =
+                            e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               &phy_data);
+                        if (ret_val)
+                                return ret_val;
+
+                        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                                phy_data);
+                        if (ret_val)
+                                return ret_val;
+                }
+        } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
+                   || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
+                   || (hw->autoneg_advertised ==
+                       AUTONEG_ADVERTISE_10_100_ALL)) {
+
+                if (hw->mac_type == e1000_82541_rev_2 ||
+                    hw->mac_type == e1000_82547_rev_2) {
+                        phy_data |= IGP01E1000_GMII_FLEX_SPD;
+                        ret_val =
+                            e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                                phy_data);
+                        if (ret_val)
+                                return ret_val;
+                }
 
-    hdr->checksum = 0 - sum;
+                /* When LPLU is enabled we should disable SmartSpeed */
+                ret_val =
+                    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                       &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-    length >>= 2;
-    /* The device driver writes the relevant command block into the ram area. */
-    for (i = 0; i < length; i++) {
-        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
-        E1000_WRITE_FLUSH();
-    }
+                phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                ret_val =
+                    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                        phy_data);
+                if (ret_val)
+                        return ret_val;
 
-    return E1000_SUCCESS;
+        }
+        return E1000_SUCCESS;
 }
 
-
-/*****************************************************************************
- * This function indicates to ARC that a new command is pending which completes
- * one write operation by the driver.
+/**
+ * e1000_set_vco_speed
+ * @hw: Struct containing variables accessed by shared code
  *
- * returns  - E1000_SUCCESS for success.
- ****************************************************************************/
-static s32 e1000_mng_write_commit(struct e1000_hw *hw)
+ * Change VCO speed register to improve Bit Error Rate performance of SERDES.
+ */
+static s32 e1000_set_vco_speed(struct e1000_hw *hw)
 {
-    u32 hicr;
+        s32 ret_val;
+        u16 default_page = 0;
+        u16 phy_data;
 
-    hicr = er32(HICR);
-    /* Setting this bit tells the ARC that a new command is pending. */
-    ew32(HICR, hicr | E1000_HICR_C);
+        DEBUGFUNC("e1000_set_vco_speed");
 
-    return E1000_SUCCESS;
-}
+        switch (hw->mac_type) {
+        case e1000_82545_rev_3:
+        case e1000_82546_rev_3:
+                break;
+        default:
+                return E1000_SUCCESS;
+        }
 
+        /* Set PHY register 30, page 5, bit 8 to 0 */
 
-/*****************************************************************************
- * This function checks the mode of the firmware.
- *
- * returns  - true when the mode is IAMT or false.
- ****************************************************************************/
-bool e1000_check_mng_mode(struct e1000_hw *hw)
-{
-    u32 fwsm;
-
-    fwsm = er32(FWSM);
+        ret_val =
+            e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
+        if (ret_val)
+                return ret_val;
 
-    if (hw->mac_type == e1000_ich8lan) {
-        if ((fwsm & E1000_FWSM_MODE_MASK) ==
-            (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
-            return true;
-    } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
-               (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
-        return true;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
+        if (ret_val)
+                return ret_val;
 
-    return false;
-}
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+        if (ret_val)
+                return ret_val;
 
+        phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+        if (ret_val)
+                return ret_val;
 
-/*****************************************************************************
- * This function writes the dhcp info .
- ****************************************************************************/
-s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
-{
-    s32 ret_val;
-    struct e1000_host_mng_command_header hdr;
-
-    hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
-    hdr.command_length = length;
-    hdr.reserved1 = 0;
-    hdr.reserved2 = 0;
-    hdr.checksum = 0;
-
-    ret_val = e1000_mng_enable_host_if(hw);
-    if (ret_val == E1000_SUCCESS) {
-        ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
-                                          &(hdr.checksum));
-        if (ret_val == E1000_SUCCESS) {
-            ret_val = e1000_mng_write_cmd_header(hw, &hdr);
-            if (ret_val == E1000_SUCCESS)
-                ret_val = e1000_mng_write_commit(hw);
-        }
-    }
-    return ret_val;
-}
+        /* Set PHY register 30, page 4, bit 11 to 1 */
 
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
+        if (ret_val)
+                return ret_val;
 
-/*****************************************************************************
- * This function calculates the checksum.
- *
- * returns  - checksum of buffer contents.
- ****************************************************************************/
-static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
-{
-    u8 sum = 0;
-    u32 i;
+        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+        if (ret_val)
+                return ret_val;
 
-    if (!buffer)
-        return 0;
+        phy_data |= M88E1000_PHY_VCO_REG_BIT11;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+        if (ret_val)
+                return ret_val;
 
-    for (i=0; i < length; i++)
-        sum += buffer[i];
+        ret_val =
+            e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
+        if (ret_val)
+                return ret_val;
 
-    return (u8)(0 - sum);
+        return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- * This function checks whether tx pkt filtering needs to be enabled or not.
- *
- * returns  - true for packet filtering or false.
- ****************************************************************************/
-bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
-{
-    /* called in init as well as watchdog timer functions */
-
-    s32 ret_val, checksum;
-    bool tx_filter = false;
-    struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
-    u8 *buffer = (u8 *) &(hw->mng_cookie);
-
-    if (e1000_check_mng_mode(hw)) {
-        ret_val = e1000_mng_enable_host_if(hw);
-        if (ret_val == E1000_SUCCESS) {
-            ret_val = e1000_host_if_read_cookie(hw, buffer);
-            if (ret_val == E1000_SUCCESS) {
-                checksum = hdr->checksum;
-                hdr->checksum = 0;
-                if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
-                    checksum == e1000_calculate_mng_checksum((char *)buffer,
-                                               E1000_MNG_DHCP_COOKIE_LENGTH)) {
-                    if (hdr->status &
-                        E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
-                        tx_filter = true;
-                } else
-                    tx_filter = true;
-            } else
-                tx_filter = true;
-        }
-    }
-
-    hw->tx_pkt_filtering = tx_filter;
-    return tx_filter;
-}
 
-/******************************************************************************
- * Verifies the hardware needs to allow ARPs to be processed by the host
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_enable_mng_pass_thru - check for bmc pass through
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Verifies the hardware needs to allow ARPs to be processed by the host
  * returns: - true/false
- *
- *****************************************************************************/
+ */
 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 {
-    u32 manc;
-    u32 fwsm, factps;
-
-    if (hw->asf_firmware_present) {
-        manc = er32(MANC);
-
-        if (!(manc & E1000_MANC_RCV_TCO_EN) ||
-            !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
-            return false;
-        if (e1000_arc_subsystem_valid(hw)) {
-            fwsm = er32(FWSM);
-            factps = er32(FACTPS);
-
-            if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
-                   e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
-                return true;
-        } else
-            if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
-                return true;
-    }
-    return false;
-}
+        u32 manc;
 
-static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 mii_status_reg;
-    u16 i;
-
-    /* Polarity reversal workaround for forced 10F/10H links. */
-
-    /* Disable the transmitter on the PHY */
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if (ret_val)
-        return ret_val;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    /* This loop will early-out if the NO link condition has been met. */
-    for (i = PHY_FORCE_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Link Status bit
-         * to be clear.
-         */
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
-        mdelay(100);
-    }
-
-    /* Recommended delay time after link has been lost */
-    mdelay(1000);
-
-    /* Now we will re-enable th transmitter on the PHY */
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    /* This loop will early-out if the link condition has been met. */
-    for (i = PHY_FORCE_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Link Status bit
-         * to be set.
-         */
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if (mii_status_reg & MII_SR_LINK_STATUS) break;
-        mdelay(100);
-    }
-    return E1000_SUCCESS;
+        if (hw->asf_firmware_present) {
+                manc = er32(MANC);
+
+                if (!(manc & E1000_MANC_RCV_TCO_EN) ||
+                    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
+                        return false;
+                if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
+                        return true;
+        }
+        return false;
 }
 
-/***************************************************************************
- *
- * Disables PCI-Express master access.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - none.
- *
- ***************************************************************************/
-static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
+static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
 {
-    u32 ctrl;
+        s32 ret_val;
+        u16 mii_status_reg;
+        u16 i;
 
-    DEBUGFUNC("e1000_set_pci_express_master_disable");
+        /* Polarity reversal workaround for forced 10F/10H links. */
 
-    if (hw->bus_type != e1000_bus_type_pci_express)
-        return;
+        /* Disable the transmitter on the PHY */
 
-    ctrl = er32(CTRL);
-    ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
-    ew32(CTRL, ctrl);
-}
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
+        if (ret_val)
+                return ret_val;
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
+        if (ret_val)
+                return ret_val;
 
-/*******************************************************************************
- *
- * Disables PCI-Express master access and verifies there are no pending requests
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
- *            caused the master requests to be disabled.
- *            E1000_SUCCESS master requests disabled.
- *
- ******************************************************************************/
-s32 e1000_disable_pciex_master(struct e1000_hw *hw)
-{
-    s32 timeout = MASTER_DISABLE_TIMEOUT;   /* 80ms */
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
+        if (ret_val)
+                return ret_val;
 
-    DEBUGFUNC("e1000_disable_pciex_master");
+        /* This loop will early-out if the NO link condition has been met. */
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
+                /* Read the MII Status Register and wait for Link Status bit
+                 * to be clear.
+                 */
 
-    if (hw->bus_type != e1000_bus_type_pci_express)
-        return E1000_SUCCESS;
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
 
-    e1000_set_pci_express_master_disable(hw);
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
 
-    while (timeout) {
-        if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
-            break;
-        else
-            udelay(100);
-        timeout--;
-    }
-
-    if (!timeout) {
-        DEBUGOUT("Master requests are pending.\n");
-        return -E1000_ERR_MASTER_REQUESTS_PENDING;
-    }
+                if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
+                        break;
+                mdelay(100);
+        }
 
-    return E1000_SUCCESS;
+        /* Recommended delay time after link has been lost */
+        mdelay(1000);
+
+        /* Now we will re-enable th transmitter on the PHY */
+
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
+        if (ret_val)
+                return ret_val;
+        mdelay(50);
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
+        if (ret_val)
+                return ret_val;
+        mdelay(50);
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
+        if (ret_val)
+                return ret_val;
+        mdelay(50);
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
+        if (ret_val)
+                return ret_val;
+
+        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
+        if (ret_val)
+                return ret_val;
+
+        /* This loop will early-out if the link condition has been met. */
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
+                /* Read the MII Status Register and wait for Link Status bit
+                 * to be set.
+                 */
+
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
+
+                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                if (ret_val)
+                        return ret_val;
+
+                if (mii_status_reg & MII_SR_LINK_STATUS)
+                        break;
+                mdelay(100);
+        }
+        return E1000_SUCCESS;
 }
 
-/*******************************************************************************
+/**
+ * e1000_get_auto_rd_done
+ * @hw: Struct containing variables accessed by shared code
  *
  * Check for EEPROM Auto Read bit done.
- *
- * hw: Struct containing variables accessed by shared code
- *
  * returns: - E1000_ERR_RESET if fail to reset MAC
  *            E1000_SUCCESS at any other case.
- *
- ******************************************************************************/
+ */
 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
 {
-    s32 timeout = AUTO_READ_DONE_TIMEOUT;
-
-    DEBUGFUNC("e1000_get_auto_rd_done");
-
-    switch (hw->mac_type) {
-    default:
-        msleep(5);
-        break;
-    case e1000_82571:
-    case e1000_82572:
-    case e1000_82573:
-    case e1000_80003es2lan:
-    case e1000_ich8lan:
-        while (timeout) {
-            if (er32(EECD) & E1000_EECD_AUTO_RD)
-                break;
-            else msleep(1);
-            timeout--;
-        }
-
-        if (!timeout) {
-            DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
-            return -E1000_ERR_RESET;
-        }
-        break;
-    }
-
-    /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
-     * Need to wait for PHY configuration completion before accessing NVM
-     * and PHY. */
-    if (hw->mac_type == e1000_82573)
-        msleep(25);
-
-    return E1000_SUCCESS;
+        DEBUGFUNC("e1000_get_auto_rd_done");
+        msleep(5);
+        return E1000_SUCCESS;
 }
 
-/***************************************************************************
- * Checks if the PHY configuration is done
- *
- * hw: Struct containing variables accessed by shared code
+/**
+ * e1000_get_phy_cfg_done
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Checks if the PHY configuration is done
  * returns: - E1000_ERR_RESET if fail to reset MAC
  *            E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
+ */
 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
 {
-    s32 timeout = PHY_CFG_TIMEOUT;
-    u32 cfg_mask = E1000_EEPROM_CFG_DONE;
-
-    DEBUGFUNC("e1000_get_phy_cfg_done");
-
-    switch (hw->mac_type) {
-    default:
-        mdelay(10);
-        break;
-    case e1000_80003es2lan:
-        /* Separate *_CFG_DONE_* bit for each port */
-        if (er32(STATUS) & E1000_STATUS_FUNC_1)
-            cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
-        /* Fall Through */
-    case e1000_82571:
-    case e1000_82572:
-        while (timeout) {
-            if (er32(EEMNGCTL) & cfg_mask)
-                break;
-            else
-                msleep(1);
-            timeout--;
-        }
-        if (!timeout) {
-            DEBUGOUT("MNG configuration cycle has not completed.\n");
-            return -E1000_ERR_RESET;
-        }
-        break;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/***************************************************************************
- *
- * Using the combination of SMBI and SWESMBI semaphore bits when resetting
- * adapter or Eeprom access.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
- *            E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
-static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
-{
-    s32 timeout;
-    u32 swsm;
-
-    DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
-
-    if (!hw->eeprom_semaphore_present)
-        return E1000_SUCCESS;
-
-    if (hw->mac_type == e1000_80003es2lan) {
-        /* Get the SW semaphore. */
-        if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
-            return -E1000_ERR_EEPROM;
-    }
-
-    /* Get the FW semaphore. */
-    timeout = hw->eeprom.word_size + 1;
-    while (timeout) {
-        swsm = er32(SWSM);
-        swsm |= E1000_SWSM_SWESMBI;
-        ew32(SWSM, swsm);
-        /* if we managed to set the bit we got the semaphore. */
-        swsm = er32(SWSM);
-        if (swsm & E1000_SWSM_SWESMBI)
-            break;
-
-        udelay(50);
-        timeout--;
-    }
-
-    if (!timeout) {
-        /* Release semaphores */
-        e1000_put_hw_eeprom_semaphore(hw);
-        DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/***************************************************************************
- * This function clears HW semaphore bits.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - None.
- *
- ***************************************************************************/
-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
-{
-    u32 swsm;
-
-    DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
-
-    if (!hw->eeprom_semaphore_present)
-        return;
-
-    swsm = er32(SWSM);
-    if (hw->mac_type == e1000_80003es2lan) {
-        /* Release both semaphores. */
-        swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
-    } else
-        swsm &= ~(E1000_SWSM_SWESMBI);
-    ew32(SWSM, swsm);
-}
-
-/***************************************************************************
- *
- * Obtaining software semaphore bit (SMBI) before resetting PHY.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_RESET if fail to obtain semaphore.
- *            E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
-static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
-{
-    s32 timeout = hw->eeprom.word_size + 1;
-    u32 swsm;
-
-    DEBUGFUNC("e1000_get_software_semaphore");
-
-    if (hw->mac_type != e1000_80003es2lan) {
-        return E1000_SUCCESS;
-    }
-
-    while (timeout) {
-        swsm = er32(SWSM);
-        /* If SMBI bit cleared, it is now set and we hold the semaphore */
-        if (!(swsm & E1000_SWSM_SMBI))
-            break;
-        mdelay(1);
-        timeout--;
-    }
-
-    if (!timeout) {
-        DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
-        return -E1000_ERR_RESET;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/***************************************************************************
- *
- * Release semaphore bit (SMBI).
- *
- * hw: Struct containing variables accessed by shared code
- *
- ***************************************************************************/
-static void e1000_release_software_semaphore(struct e1000_hw *hw)
-{
-    u32 swsm;
-
-    DEBUGFUNC("e1000_release_software_semaphore");
-
-    if (hw->mac_type != e1000_80003es2lan) {
-        return;
-    }
-
-    swsm = er32(SWSM);
-    /* Release the SW semaphores.*/
-    swsm &= ~E1000_SWSM_SMBI;
-    ew32(SWSM, swsm);
-}
-
-/******************************************************************************
- * Checks if PHY reset is blocked due to SOL/IDER session, for example.
- * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
- * the caller to figure out how to deal with it.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * returns: - E1000_BLK_PHY_RESET
- *            E1000_SUCCESS
- *
- *****************************************************************************/
-s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
-{
-    u32 manc = 0;
-    u32 fwsm = 0;
-
-    if (hw->mac_type == e1000_ich8lan) {
-        fwsm = er32(FWSM);
-        return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
-                                            : E1000_BLK_PHY_RESET;
-    }
-
-    if (hw->mac_type > e1000_82547_rev_2)
-        manc = er32(MANC);
-    return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
-        E1000_BLK_PHY_RESET : E1000_SUCCESS;
-}
-
-static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
-{
-    u32 fwsm;
-
-    /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
-     * may not be provided a DMA clock when no manageability features are
-     * enabled.  We do not want to perform any reads/writes to these registers
-     * if this is the case.  We read FWSM to determine the manageability mode.
-     */
-    switch (hw->mac_type) {
-    case e1000_82571:
-    case e1000_82572:
-    case e1000_82573:
-    case e1000_80003es2lan:
-        fwsm = er32(FWSM);
-        if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
-            return true;
-        break;
-    case e1000_ich8lan:
-        return true;
-    default:
-        break;
-    }
-    return false;
-}
-
-
-/******************************************************************************
- * Configure PCI-Ex no-snoop
- *
- * hw - Struct containing variables accessed by shared code.
- * no_snoop - Bitmap of no-snoop events.
- *
- * returns: E1000_SUCCESS
- *
- *****************************************************************************/
-static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
-{
-    u32 gcr_reg = 0;
-
-    DEBUGFUNC("e1000_set_pci_ex_no_snoop");
-
-    if (hw->bus_type == e1000_bus_type_unknown)
-        e1000_get_bus_info(hw);
-
-    if (hw->bus_type != e1000_bus_type_pci_express)
-        return E1000_SUCCESS;
-
-    if (no_snoop) {
-        gcr_reg = er32(GCR);
-        gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
-        gcr_reg |= no_snoop;
-        ew32(GCR, gcr_reg);
-    }
-    if (hw->mac_type == e1000_ich8lan) {
-        u32 ctrl_ext;
-
-        ew32(GCR, PCI_EX_82566_SNOOP_ALL);
-
-        ctrl_ext = er32(CTRL_EXT);
-        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
-        ew32(CTRL_EXT, ctrl_ext);
-    }
-
-    return E1000_SUCCESS;
-}
-
-/***************************************************************************
- *
- * Get software semaphore FLAG bit (SWFLAG).
- * SWFLAG is used to synchronize the access to all shared resource between
- * SW, FW and HW.
- *
- * hw: Struct containing variables accessed by shared code
- *
- ***************************************************************************/
-static s32 e1000_get_software_flag(struct e1000_hw *hw)
-{
-    s32 timeout = PHY_CFG_TIMEOUT;
-    u32 extcnf_ctrl;
-
-    DEBUGFUNC("e1000_get_software_flag");
-
-    if (hw->mac_type == e1000_ich8lan) {
-        while (timeout) {
-            extcnf_ctrl = er32(EXTCNF_CTRL);
-            extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
-            ew32(EXTCNF_CTRL, extcnf_ctrl);
-
-            extcnf_ctrl = er32(EXTCNF_CTRL);
-            if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
-                break;
-            mdelay(1);
-            timeout--;
-        }
-
-        if (!timeout) {
-            DEBUGOUT("FW or HW locks the resource too long.\n");
-            return -E1000_ERR_CONFIG;
-        }
-    }
-
-    return E1000_SUCCESS;
-}
-
-/***************************************************************************
- *
- * Release software semaphore FLAG bit (SWFLAG).
- * SWFLAG is used to synchronize the access to all shared resource between
- * SW, FW and HW.
- *
- * hw: Struct containing variables accessed by shared code
- *
- ***************************************************************************/
-static void e1000_release_software_flag(struct e1000_hw *hw)
-{
-    u32 extcnf_ctrl;
-
-    DEBUGFUNC("e1000_release_software_flag");
-
-    if (hw->mac_type == e1000_ich8lan) {
-        extcnf_ctrl= er32(EXTCNF_CTRL);
-        extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
-        ew32(EXTCNF_CTRL, extcnf_ctrl);
-    }
-
-    return;
-}
-
-/******************************************************************************
- * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
- * register.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data)
-{
-    s32  error = E1000_SUCCESS;
-    u32 flash_bank = 0;
-    u32 act_offset = 0;
-    u32 bank_offset = 0;
-    u16 word = 0;
-    u16 i = 0;
-
-    /* We need to know which is the valid flash bank.  In the event
-     * that we didn't allocate eeprom_shadow_ram, we may not be
-     * managing flash_bank.  So it cannot be trusted and needs
-     * to be updated with each read.
-     */
-    /* Value of bit 22 corresponds to the flash bank we're on. */
-    flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
-
-    /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
-    bank_offset = flash_bank * (hw->flash_bank_size * 2);
-
-    error = e1000_get_software_flag(hw);
-    if (error != E1000_SUCCESS)
-        return error;
-
-    for (i = 0; i < words; i++) {
-        if (hw->eeprom_shadow_ram != NULL &&
-            hw->eeprom_shadow_ram[offset+i].modified) {
-            data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
-        } else {
-            /* The NVM part needs a byte offset, hence * 2 */
-            act_offset = bank_offset + ((offset + i) * 2);
-            error = e1000_read_ich8_word(hw, act_offset, &word);
-            if (error != E1000_SUCCESS)
-                break;
-            data[i] = word;
-        }
-    }
-
-    e1000_release_software_flag(hw);
-
-    return error;
-}
-
-/******************************************************************************
- * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
- * register.  Actually, writes are written to the shadow ram cache in the hw
- * structure hw->e1000_shadow_ram.  e1000_commit_shadow_ram flushes this to
- * the NVM, which occurs when the NVM checksum is updated.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of word in the EEPROM to write
- * words - number of words to write
- * data - words to write to the EEPROM
- *****************************************************************************/
-static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data)
-{
-    u32 i = 0;
-    s32 error = E1000_SUCCESS;
-
-    error = e1000_get_software_flag(hw);
-    if (error != E1000_SUCCESS)
-        return error;
-
-    /* A driver can write to the NVM only if it has eeprom_shadow_ram
-     * allocated.  Subsequent reads to the modified words are read from
-     * this cached structure as well.  Writes will only go into this
-     * cached structure unless it's followed by a call to
-     * e1000_update_eeprom_checksum() where it will commit the changes
-     * and clear the "modified" field.
-     */
-    if (hw->eeprom_shadow_ram != NULL) {
-        for (i = 0; i < words; i++) {
-            if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
-                hw->eeprom_shadow_ram[offset+i].modified = true;
-                hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
-            } else {
-                error = -E1000_ERR_EEPROM;
-                break;
-            }
-        }
-    } else {
-        /* Drivers have the option to not allocate eeprom_shadow_ram as long
-         * as they don't perform any NVM writes.  An attempt in doing so
-         * will result in this error.
-         */
-        error = -E1000_ERR_EEPROM;
-    }
-
-    e1000_release_software_flag(hw);
-
-    return error;
-}
-
-/******************************************************************************
- * This function does initial flash setup so that a new read/write/erase cycle
- * can be started.
- *
- * hw - The pointer to the hw structure
- ****************************************************************************/
-static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
-{
-    union ich8_hws_flash_status hsfsts;
-    s32 error = E1000_ERR_EEPROM;
-    s32 i     = 0;
-
-    DEBUGFUNC("e1000_ich8_cycle_init");
-
-    hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-
-    /* May be check the Flash Des Valid bit in Hw status */
-    if (hsfsts.hsf_status.fldesvalid == 0) {
-        DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.");
-        return error;
-    }
-
-    /* Clear FCERR in Hw status by writing 1 */
-    /* Clear DAEL in Hw status by writing a 1 */
-    hsfsts.hsf_status.flcerr = 1;
-    hsfsts.hsf_status.dael = 1;
-
-    E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
-
-    /* Either we should have a hardware SPI cycle in progress bit to check
-     * against, in order to start a new cycle or FDONE bit should be changed
-     * in the hardware so that it is 1 after harware reset, which can then be
-     * used as an indication whether a cycle is in progress or has been
-     * completed .. we should also have some software semaphore mechanism to
-     * guard FDONE or the cycle in progress bit so that two threads access to
-     * those bits can be sequentiallized or a way so that 2 threads dont
-     * start the cycle at the same time */
-
-    if (hsfsts.hsf_status.flcinprog == 0) {
-        /* There is no cycle running at present, so we can start a cycle */
-        /* Begin by setting Flash Cycle Done. */
-        hsfsts.hsf_status.flcdone = 1;
-        E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
-        error = E1000_SUCCESS;
-    } else {
-        /* otherwise poll for sometime so the current cycle has a chance
-         * to end before giving up. */
-        for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
-            hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-            if (hsfsts.hsf_status.flcinprog == 0) {
-                error = E1000_SUCCESS;
-                break;
-            }
-            udelay(1);
-        }
-        if (error == E1000_SUCCESS) {
-            /* Successful in waiting for previous cycle to timeout,
-             * now set the Flash Cycle Done. */
-            hsfsts.hsf_status.flcdone = 1;
-            E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
-        } else {
-            DEBUGOUT("Flash controller busy, cannot get access");
-        }
-    }
-    return error;
-}
-
-/******************************************************************************
- * This function starts a flash cycle and waits for its completion
- *
- * hw - The pointer to the hw structure
- ****************************************************************************/
-static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
-{
-    union ich8_hws_flash_ctrl hsflctl;
-    union ich8_hws_flash_status hsfsts;
-    s32 error = E1000_ERR_EEPROM;
-    u32 i = 0;
-
-    /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
-    hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
-    hsflctl.hsf_ctrl.flcgo = 1;
-    E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
-
-    /* wait till FDONE bit is set to 1 */
-    do {
-        hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-        if (hsfsts.hsf_status.flcdone == 1)
-            break;
-        udelay(1);
-        i++;
-    } while (i < timeout);
-    if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
-        error = E1000_SUCCESS;
-    }
-    return error;
-}
-
-/******************************************************************************
- * Reads a byte or word from the NVM using the ICH8 flash access registers.
- *
- * hw - The pointer to the hw structure
- * index - The index of the byte or word to read.
- * size - Size of data to read, 1=byte 2=word
- * data - Pointer to the word to store the value read.
- *****************************************************************************/
-static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
-                                u16 *data)
-{
-    union ich8_hws_flash_status hsfsts;
-    union ich8_hws_flash_ctrl hsflctl;
-    u32 flash_linear_address;
-    u32 flash_data = 0;
-    s32 error = -E1000_ERR_EEPROM;
-    s32 count = 0;
-
-    DEBUGFUNC("e1000_read_ich8_data");
-
-    if (size < 1  || size > 2 || data == NULL ||
-        index > ICH_FLASH_LINEAR_ADDR_MASK)
-        return error;
-
-    flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
-                           hw->flash_base_addr;
-
-    do {
-        udelay(1);
-        /* Steps */
-        error = e1000_ich8_cycle_init(hw);
-        if (error != E1000_SUCCESS)
-            break;
-
-        hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
-        /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
-        hsflctl.hsf_ctrl.fldbcount = size - 1;
-        hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
-        E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
-
-        /* Write the last 24 bits of index into Flash Linear address field in
-         * Flash Address */
-        /* TODO: TBD maybe check the index against the size of flash */
-
-        E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
-
-        error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
-
-        /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
-         * sequence a few more times, else read in (shift in) the Flash Data0,
-         * the order is least significant byte first msb to lsb */
-        if (error == E1000_SUCCESS) {
-            flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
-            if (size == 1) {
-                *data = (u8)(flash_data & 0x000000FF);
-            } else if (size == 2) {
-                *data = (u16)(flash_data & 0x0000FFFF);
-            }
-            break;
-        } else {
-            /* If we've gotten here, then things are probably completely hosed,
-             * but if the error condition is detected, it won't hurt to give
-             * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
-             */
-            hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-            if (hsfsts.hsf_status.flcerr == 1) {
-                /* Repeat for some time before giving up. */
-                continue;
-            } else if (hsfsts.hsf_status.flcdone == 0) {
-                DEBUGOUT("Timeout error - flash cycle did not complete.");
-                break;
-            }
-        }
-    } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-
-    return error;
-}
-
-/******************************************************************************
- * Writes One /two bytes to the NVM using the ICH8 flash access registers.
- *
- * hw - The pointer to the hw structure
- * index - The index of the byte/word to read.
- * size - Size of data to read, 1=byte 2=word
- * data - The byte(s) to write to the NVM.
- *****************************************************************************/
-static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
-                                 u16 data)
-{
-    union ich8_hws_flash_status hsfsts;
-    union ich8_hws_flash_ctrl hsflctl;
-    u32 flash_linear_address;
-    u32 flash_data = 0;
-    s32 error = -E1000_ERR_EEPROM;
-    s32 count = 0;
-
-    DEBUGFUNC("e1000_write_ich8_data");
-
-    if (size < 1  || size > 2 || data > size * 0xff ||
-        index > ICH_FLASH_LINEAR_ADDR_MASK)
-        return error;
-
-    flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
-                           hw->flash_base_addr;
-
-    do {
-        udelay(1);
-        /* Steps */
-        error = e1000_ich8_cycle_init(hw);
-        if (error != E1000_SUCCESS)
-            break;
-
-        hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
-        /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
-        hsflctl.hsf_ctrl.fldbcount = size -1;
-        hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
-        E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
-
-        /* Write the last 24 bits of index into Flash Linear address field in
-         * Flash Address */
-        E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
-
-        if (size == 1)
-            flash_data = (u32)data & 0x00FF;
-        else
-            flash_data = (u32)data;
-
-        E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
-
-        /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
-         * sequence a few more times else done */
-        error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
-        if (error == E1000_SUCCESS) {
-            break;
-        } else {
-            /* If we're here, then things are most likely completely hosed,
-             * but if the error condition is detected, it won't hurt to give
-             * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
-             */
-            hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-            if (hsfsts.hsf_status.flcerr == 1) {
-                /* Repeat for some time before giving up. */
-                continue;
-            } else if (hsfsts.hsf_status.flcdone == 0) {
-                DEBUGOUT("Timeout error - flash cycle did not complete.");
-                break;
-            }
-        }
-    } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-
-    return error;
-}
-
-/******************************************************************************
- * Reads a single byte from the NVM using the ICH8 flash access registers.
- *
- * hw - pointer to e1000_hw structure
- * index - The index of the byte to read.
- * data - Pointer to a byte to store the value read.
- *****************************************************************************/
-static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
-{
-    s32 status = E1000_SUCCESS;
-    u16 word = 0;
-
-    status = e1000_read_ich8_data(hw, index, 1, &word);
-    if (status == E1000_SUCCESS) {
-        *data = (u8)word;
-    }
-
-    return status;
-}
-
-/******************************************************************************
- * Writes a single byte to the NVM using the ICH8 flash access registers.
- * Performs verification by reading back the value and then going through
- * a retry algorithm before giving up.
- *
- * hw - pointer to e1000_hw structure
- * index - The index of the byte to write.
- * byte - The byte to write to the NVM.
- *****************************************************************************/
-static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
-{
-    s32 error = E1000_SUCCESS;
-    s32 program_retries = 0;
-
-    DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
-
-    error = e1000_write_ich8_byte(hw, index, byte);
-
-    if (error != E1000_SUCCESS) {
-        for (program_retries = 0; program_retries < 100; program_retries++) {
-            DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
-            error = e1000_write_ich8_byte(hw, index, byte);
-            udelay(100);
-            if (error == E1000_SUCCESS)
-                break;
-        }
-    }
-
-    if (program_retries == 100)
-        error = E1000_ERR_EEPROM;
-
-    return error;
-}
-
-/******************************************************************************
- * Writes a single byte to the NVM using the ICH8 flash access registers.
- *
- * hw - pointer to e1000_hw structure
- * index - The index of the byte to read.
- * data - The byte to write to the NVM.
- *****************************************************************************/
-static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
-{
-    s32 status = E1000_SUCCESS;
-    u16 word = (u16)data;
-
-    status = e1000_write_ich8_data(hw, index, 1, word);
-
-    return status;
-}
-
-/******************************************************************************
- * Reads a word from the NVM using the ICH8 flash access registers.
- *
- * hw - pointer to e1000_hw structure
- * index - The starting byte index of the word to read.
- * data - Pointer to a word to store the value read.
- *****************************************************************************/
-static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
-{
-    s32 status = E1000_SUCCESS;
-    status = e1000_read_ich8_data(hw, index, 2, data);
-    return status;
-}
-
-/******************************************************************************
- * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
- * based.
- *
- * hw - pointer to e1000_hw structure
- * bank - 0 for first bank, 1 for second bank
- *
- * Note that this function may actually erase as much as 8 or 64 KBytes.  The
- * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
- * bank size may be 4, 8 or 64 KBytes
- *****************************************************************************/
-static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
-{
-    union ich8_hws_flash_status hsfsts;
-    union ich8_hws_flash_ctrl hsflctl;
-    u32 flash_linear_address;
-    s32  count = 0;
-    s32  error = E1000_ERR_EEPROM;
-    s32  iteration;
-    s32  sub_sector_size = 0;
-    s32  bank_size;
-    s32  j = 0;
-    s32  error_flag = 0;
-
-    hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-
-    /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
-    /* 00: The Hw sector is 256 bytes, hence we need to erase 16
-     *     consecutive sectors.  The start index for the nth Hw sector can be
-     *     calculated as bank * 4096 + n * 256
-     * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
-     *     The start index for the nth Hw sector can be calculated
-     *     as bank * 4096
-     * 10: The HW sector is 8K bytes
-     * 11: The Hw sector size is 64K bytes */
-    if (hsfsts.hsf_status.berasesz == 0x0) {
-        /* Hw sector size 256 */
-        sub_sector_size = ICH_FLASH_SEG_SIZE_256;
-        bank_size = ICH_FLASH_SECTOR_SIZE;
-        iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
-    } else if (hsfsts.hsf_status.berasesz == 0x1) {
-        bank_size = ICH_FLASH_SEG_SIZE_4K;
-        iteration = 1;
-    } else if (hsfsts.hsf_status.berasesz == 0x3) {
-        bank_size = ICH_FLASH_SEG_SIZE_64K;
-        iteration = 1;
-    } else {
-        return error;
-    }
-
-    for (j = 0; j < iteration ; j++) {
-        do {
-            count++;
-            /* Steps */
-            error = e1000_ich8_cycle_init(hw);
-            if (error != E1000_SUCCESS) {
-                error_flag = 1;
-                break;
-            }
-
-            /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
-             * Control */
-            hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
-            hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
-            E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
-
-            /* Write the last 24 bits of an index within the block into Flash
-             * Linear address field in Flash Address.  This probably needs to
-             * be calculated here based off the on-chip erase sector size and
-             * the software bank size (4, 8 or 64 KBytes) */
-            flash_linear_address = bank * bank_size + j * sub_sector_size;
-            flash_linear_address += hw->flash_base_addr;
-            flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
-
-            E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
-
-            error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
-            /* Check if FCERR is set to 1.  If 1, clear it and try the whole
-             * sequence a few more times else Done */
-            if (error == E1000_SUCCESS) {
-                break;
-            } else {
-                hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-                if (hsfsts.hsf_status.flcerr == 1) {
-                    /* repeat for some time before giving up */
-                    continue;
-                } else if (hsfsts.hsf_status.flcdone == 0) {
-                    error_flag = 1;
-                    break;
-                }
-            }
-        } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
-        if (error_flag == 1)
-            break;
-    }
-    if (error_flag != 1)
-        error = E1000_SUCCESS;
-    return error;
-}
-
-static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
-                                                 u32 cnf_base_addr,
-                                                 u32 cnf_size)
-{
-    u32 ret_val = E1000_SUCCESS;
-    u16 word_addr, reg_data, reg_addr;
-    u16 i;
-
-    /* cnf_base_addr is in DWORD */
-    word_addr = (u16)(cnf_base_addr << 1);
-
-    /* cnf_size is returned in size of dwords */
-    for (i = 0; i < cnf_size; i++) {
-        ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_get_software_flag(hw);
-        if (ret_val != E1000_SUCCESS)
-            return ret_val;
-
-        ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
-
-        e1000_release_software_flag(hw);
-    }
-
-    return ret_val;
-}
-
-
-/******************************************************************************
- * This function initializes the PHY from the NVM on ICH8 platforms. This
- * is needed due to an issue where the NVM configuration is not properly
- * autoloaded after power transitions. Therefore, after each PHY reset, we
- * will load the configuration data out of the NVM manually.
- *
- * hw: Struct containing variables accessed by shared code
- *****************************************************************************/
-static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
-{
-    u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
-
-    if (hw->phy_type != e1000_phy_igp_3)
-          return E1000_SUCCESS;
-
-    /* Check if SW needs configure the PHY */
-    reg_data = er32(FEXTNVM);
-    if (!(reg_data & FEXTNVM_SW_CONFIG))
-        return E1000_SUCCESS;
-
-    /* Wait for basic configuration completes before proceeding*/
-    loop = 0;
-    do {
-        reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
-        udelay(100);
-        loop++;
-    } while ((!reg_data) && (loop < 50));
-
-    /* Clear the Init Done bit for the next init event */
-    reg_data = er32(STATUS);
-    reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
-    ew32(STATUS, reg_data);
-
-    /* Make sure HW does not configure LCD from PHY extended configuration
-       before SW configuration */
-    reg_data = er32(EXTCNF_CTRL);
-    if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
-        reg_data = er32(EXTCNF_SIZE);
-        cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
-        cnf_size >>= 16;
-        if (cnf_size) {
-            reg_data = er32(EXTCNF_CTRL);
-            cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
-            /* cnf_base_addr is in DWORD */
-            cnf_base_addr >>= 16;
-
-            /* Configure LCD from extended configuration region. */
-            ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
-                                                            cnf_size);
-            if (ret_val)
-                return ret_val;
-        }
-    }
-
-    return E1000_SUCCESS;
+        DEBUGFUNC("e1000_get_phy_cfg_done");
+        mdelay(10);
+        return E1000_SUCCESS;
 }
-
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index a8866bdbb671..9acfddb0dafb 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -35,7 +35,6 @@
 
 #include "e1000_osdep.h"
 
-
 /* Forward declarations of structures used by the shared code */
 struct e1000_hw;
 struct e1000_hw_stats;
@@ -43,252 +42,231 @@ struct e1000_hw_stats;
 /* Enumerated types specific to the e1000 hardware */
 /* Media Access Controlers */
 typedef enum {
-    e1000_undefined = 0,
-    e1000_82542_rev2_0,
-    e1000_82542_rev2_1,
-    e1000_82543,
-    e1000_82544,
-    e1000_82540,
-    e1000_82545,
-    e1000_82545_rev_3,
-    e1000_82546,
-    e1000_82546_rev_3,
-    e1000_82541,
-    e1000_82541_rev_2,
-    e1000_82547,
-    e1000_82547_rev_2,
-    e1000_82571,
-    e1000_82572,
-    e1000_82573,
-    e1000_80003es2lan,
-    e1000_ich8lan,
-    e1000_num_macs
+        e1000_undefined = 0,
+        e1000_82542_rev2_0,
+        e1000_82542_rev2_1,
+        e1000_82543,
+        e1000_82544,
+        e1000_82540,
+        e1000_82545,
+        e1000_82545_rev_3,
+        e1000_82546,
+        e1000_82546_rev_3,
+        e1000_82541,
+        e1000_82541_rev_2,
+        e1000_82547,
+        e1000_82547_rev_2,
+        e1000_num_macs
 } e1000_mac_type;
 
 typedef enum {
-    e1000_eeprom_uninitialized = 0,
-    e1000_eeprom_spi,
-    e1000_eeprom_microwire,
-    e1000_eeprom_flash,
-    e1000_eeprom_ich8,
-    e1000_eeprom_none, /* No NVM support */
-    e1000_num_eeprom_types
+        e1000_eeprom_uninitialized = 0,
+        e1000_eeprom_spi,
+        e1000_eeprom_microwire,
+        e1000_eeprom_flash,
+        e1000_eeprom_none,      /* No NVM support */
+        e1000_num_eeprom_types
 } e1000_eeprom_type;
 
 /* Media Types */
 typedef enum {
-    e1000_media_type_copper = 0,
-    e1000_media_type_fiber = 1,
-    e1000_media_type_internal_serdes = 2,
-    e1000_num_media_types
+        e1000_media_type_copper = 0,
+        e1000_media_type_fiber = 1,
+        e1000_media_type_internal_serdes = 2,
+        e1000_num_media_types
 } e1000_media_type;
 
 typedef enum {
-    e1000_10_half = 0,
-    e1000_10_full = 1,
-    e1000_100_half = 2,
-    e1000_100_full = 3
+        e1000_10_half = 0,
+        e1000_10_full = 1,
+        e1000_100_half = 2,
+        e1000_100_full = 3
 } e1000_speed_duplex_type;
 
 /* Flow Control Settings */
 typedef enum {
-    E1000_FC_NONE = 0,
-    E1000_FC_RX_PAUSE = 1,
-    E1000_FC_TX_PAUSE = 2,
-    E1000_FC_FULL = 3,
-    E1000_FC_DEFAULT = 0xFF
+        E1000_FC_NONE = 0,
+        E1000_FC_RX_PAUSE = 1,
+        E1000_FC_TX_PAUSE = 2,
+        E1000_FC_FULL = 3,
+        E1000_FC_DEFAULT = 0xFF
 } e1000_fc_type;
 
 struct e1000_shadow_ram {
-    u16 eeprom_word;
-    bool modified;
+        u16 eeprom_word;
+        bool modified;
 };
 
 /* PCI bus types */
 typedef enum {
-    e1000_bus_type_unknown = 0,
-    e1000_bus_type_pci,
-    e1000_bus_type_pcix,
-    e1000_bus_type_pci_express,
-    e1000_bus_type_reserved
+        e1000_bus_type_unknown = 0,
+        e1000_bus_type_pci,
+        e1000_bus_type_pcix,
+        e1000_bus_type_reserved
 } e1000_bus_type;
 
 /* PCI bus speeds */
 typedef enum {
-    e1000_bus_speed_unknown = 0,
-    e1000_bus_speed_33,
-    e1000_bus_speed_66,
-    e1000_bus_speed_100,
-    e1000_bus_speed_120,
-    e1000_bus_speed_133,
-    e1000_bus_speed_2500,
-    e1000_bus_speed_reserved
+        e1000_bus_speed_unknown = 0,
+        e1000_bus_speed_33,
+        e1000_bus_speed_66,
+        e1000_bus_speed_100,
+        e1000_bus_speed_120,
+        e1000_bus_speed_133,
+        e1000_bus_speed_reserved
 } e1000_bus_speed;
 
 /* PCI bus widths */
 typedef enum {
-    e1000_bus_width_unknown = 0,
-    /* These PCIe values should literally match the possible return values
-     * from config space */
-    e1000_bus_width_pciex_1 = 1,
-    e1000_bus_width_pciex_2 = 2,
-    e1000_bus_width_pciex_4 = 4,
-    e1000_bus_width_32,
-    e1000_bus_width_64,
-    e1000_bus_width_reserved
+        e1000_bus_width_unknown = 0,
+        e1000_bus_width_32,
+        e1000_bus_width_64,
+        e1000_bus_width_reserved
 } e1000_bus_width;
 
 /* PHY status info structure and supporting enums */
 typedef enum {
-    e1000_cable_length_50 = 0,
-    e1000_cable_length_50_80,
-    e1000_cable_length_80_110,
-    e1000_cable_length_110_140,
-    e1000_cable_length_140,
-    e1000_cable_length_undefined = 0xFF
+        e1000_cable_length_50 = 0,
+        e1000_cable_length_50_80,
+        e1000_cable_length_80_110,
+        e1000_cable_length_110_140,
+        e1000_cable_length_140,
+        e1000_cable_length_undefined = 0xFF
 } e1000_cable_length;
 
 typedef enum {
-    e1000_gg_cable_length_60 = 0,
-    e1000_gg_cable_length_60_115 = 1,
-    e1000_gg_cable_length_115_150 = 2,
-    e1000_gg_cable_length_150 = 4
+        e1000_gg_cable_length_60 = 0,
+        e1000_gg_cable_length_60_115 = 1,
+        e1000_gg_cable_length_115_150 = 2,
+        e1000_gg_cable_length_150 = 4
 } e1000_gg_cable_length;
 
 typedef enum {
-    e1000_igp_cable_length_10  = 10,
-    e1000_igp_cable_length_20  = 20,
-    e1000_igp_cable_length_30  = 30,
-    e1000_igp_cable_length_40  = 40,
-    e1000_igp_cable_length_50  = 50,
-    e1000_igp_cable_length_60  = 60,
-    e1000_igp_cable_length_70  = 70,
-    e1000_igp_cable_length_80  = 80,
-    e1000_igp_cable_length_90  = 90,
-    e1000_igp_cable_length_100 = 100,
-    e1000_igp_cable_length_110 = 110,
-    e1000_igp_cable_length_115 = 115,
-    e1000_igp_cable_length_120 = 120,
-    e1000_igp_cable_length_130 = 130,
-    e1000_igp_cable_length_140 = 140,
-    e1000_igp_cable_length_150 = 150,
-    e1000_igp_cable_length_160 = 160,
-    e1000_igp_cable_length_170 = 170,
-    e1000_igp_cable_length_180 = 180
+        e1000_igp_cable_length_10 = 10,
+        e1000_igp_cable_length_20 = 20,
+        e1000_igp_cable_length_30 = 30,
+        e1000_igp_cable_length_40 = 40,
+        e1000_igp_cable_length_50 = 50,
+        e1000_igp_cable_length_60 = 60,
+        e1000_igp_cable_length_70 = 70,
+        e1000_igp_cable_length_80 = 80,
+        e1000_igp_cable_length_90 = 90,
+        e1000_igp_cable_length_100 = 100,
+        e1000_igp_cable_length_110 = 110,
+        e1000_igp_cable_length_115 = 115,
+        e1000_igp_cable_length_120 = 120,
+        e1000_igp_cable_length_130 = 130,
+        e1000_igp_cable_length_140 = 140,
+        e1000_igp_cable_length_150 = 150,
+        e1000_igp_cable_length_160 = 160,
+        e1000_igp_cable_length_170 = 170,
+        e1000_igp_cable_length_180 = 180
 } e1000_igp_cable_length;
 
 typedef enum {
-    e1000_10bt_ext_dist_enable_normal = 0,
-    e1000_10bt_ext_dist_enable_lower,
-    e1000_10bt_ext_dist_enable_undefined = 0xFF
+        e1000_10bt_ext_dist_enable_normal = 0,
+        e1000_10bt_ext_dist_enable_lower,
+        e1000_10bt_ext_dist_enable_undefined = 0xFF
 } e1000_10bt_ext_dist_enable;
 
 typedef enum {
-    e1000_rev_polarity_normal = 0,
-    e1000_rev_polarity_reversed,
-    e1000_rev_polarity_undefined = 0xFF
+        e1000_rev_polarity_normal = 0,
+        e1000_rev_polarity_reversed,
+        e1000_rev_polarity_undefined = 0xFF
 } e1000_rev_polarity;
 
 typedef enum {
-    e1000_downshift_normal = 0,
-    e1000_downshift_activated,
-    e1000_downshift_undefined = 0xFF
+        e1000_downshift_normal = 0,
+        e1000_downshift_activated,
+        e1000_downshift_undefined = 0xFF
 } e1000_downshift;
 
 typedef enum {
-    e1000_smart_speed_default = 0,
-    e1000_smart_speed_on,
-    e1000_smart_speed_off
+        e1000_smart_speed_default = 0,
+        e1000_smart_speed_on,
+        e1000_smart_speed_off
 } e1000_smart_speed;
 
 typedef enum {
-    e1000_polarity_reversal_enabled = 0,
-    e1000_polarity_reversal_disabled,
-    e1000_polarity_reversal_undefined = 0xFF
+        e1000_polarity_reversal_enabled = 0,
+        e1000_polarity_reversal_disabled,
+        e1000_polarity_reversal_undefined = 0xFF
 } e1000_polarity_reversal;
 
 typedef enum {
-    e1000_auto_x_mode_manual_mdi = 0,
-    e1000_auto_x_mode_manual_mdix,
-    e1000_auto_x_mode_auto1,
-    e1000_auto_x_mode_auto2,
-    e1000_auto_x_mode_undefined = 0xFF
+        e1000_auto_x_mode_manual_mdi = 0,
+        e1000_auto_x_mode_manual_mdix,
+        e1000_auto_x_mode_auto1,
+        e1000_auto_x_mode_auto2,
+        e1000_auto_x_mode_undefined = 0xFF
 } e1000_auto_x_mode;
 
 typedef enum {
-    e1000_1000t_rx_status_not_ok = 0,
-    e1000_1000t_rx_status_ok,
-    e1000_1000t_rx_status_undefined = 0xFF
+        e1000_1000t_rx_status_not_ok = 0,
+        e1000_1000t_rx_status_ok,
+        e1000_1000t_rx_status_undefined = 0xFF
 } e1000_1000t_rx_status;
 
 typedef enum {
     e1000_phy_m88 = 0,
     e1000_phy_igp,
-    e1000_phy_igp_2,
-    e1000_phy_gg82563,
-    e1000_phy_igp_3,
-    e1000_phy_ife,
     e1000_phy_undefined = 0xFF
 } e1000_phy_type;
 
 typedef enum {
-    e1000_ms_hw_default = 0,
-    e1000_ms_force_master,
-    e1000_ms_force_slave,
-    e1000_ms_auto
+        e1000_ms_hw_default = 0,
+        e1000_ms_force_master,
+        e1000_ms_force_slave,
+        e1000_ms_auto
 } e1000_ms_type;
 
 typedef enum {
-    e1000_ffe_config_enabled = 0,
-    e1000_ffe_config_active,
-    e1000_ffe_config_blocked
+        e1000_ffe_config_enabled = 0,
+        e1000_ffe_config_active,
+        e1000_ffe_config_blocked
 } e1000_ffe_config;
 
 typedef enum {
-    e1000_dsp_config_disabled = 0,
-    e1000_dsp_config_enabled,
-    e1000_dsp_config_activated,
-    e1000_dsp_config_undefined = 0xFF
+        e1000_dsp_config_disabled = 0,
+        e1000_dsp_config_enabled,
+        e1000_dsp_config_activated,
+        e1000_dsp_config_undefined = 0xFF
 } e1000_dsp_config;
 
 struct e1000_phy_info {
-    e1000_cable_length cable_length;
-    e1000_10bt_ext_dist_enable extended_10bt_distance;
-    e1000_rev_polarity cable_polarity;
-    e1000_downshift downshift;
-    e1000_polarity_reversal polarity_correction;
-    e1000_auto_x_mode mdix_mode;
-    e1000_1000t_rx_status local_rx;
-    e1000_1000t_rx_status remote_rx;
+        e1000_cable_length cable_length;
+        e1000_10bt_ext_dist_enable extended_10bt_distance;
+        e1000_rev_polarity cable_polarity;
+        e1000_downshift downshift;
+        e1000_polarity_reversal polarity_correction;
+        e1000_auto_x_mode mdix_mode;
+        e1000_1000t_rx_status local_rx;
+        e1000_1000t_rx_status remote_rx;
 };
 
 struct e1000_phy_stats {
-    u32 idle_errors;
-    u32 receive_errors;
+        u32 idle_errors;
+        u32 receive_errors;
 };
 
 struct e1000_eeprom_info {
-    e1000_eeprom_type type;
-    u16 word_size;
-    u16 opcode_bits;
-    u16 address_bits;
-    u16 delay_usec;
-    u16 page_size;
-    bool use_eerd;
-    bool use_eewr;
+        e1000_eeprom_type type;
+        u16 word_size;
+        u16 opcode_bits;
+        u16 address_bits;
+        u16 delay_usec;
+        u16 page_size;
 };
 
 /* Flex ASF Information */
 #define E1000_HOST_IF_MAX_SIZE  2048
 
 typedef enum {
-    e1000_byte_align = 0,
-    e1000_word_align = 1,
-    e1000_dword_align = 2
+        e1000_byte_align = 0,
+        e1000_word_align = 1,
+        e1000_dword_align = 2
 } e1000_align_type;
 
-
-
 /* Error Codes */
 #define E1000_SUCCESS      0
 #define E1000_ERR_EEPROM   1
@@ -301,7 +279,6 @@ typedef enum {
 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
 #define E1000_BLK_PHY_RESET   12
-#define E1000_ERR_SWFW_SYNC 13
 
 #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
                                      (((_value) & 0xff00) >> 8))
@@ -318,19 +295,17 @@ s32 e1000_setup_link(struct e1000_hw *hw);
 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
 void e1000_config_collision_dist(struct e1000_hw *hw);
 s32 e1000_check_for_link(struct e1000_hw *hw);
-s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
 s32 e1000_force_mac_fc(struct e1000_hw *hw);
 
 /* PHY */
-s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data);
+s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
 s32 e1000_phy_hw_reset(struct e1000_hw *hw);
 s32 e1000_phy_reset(struct e1000_hw *hw);
 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
 s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
 
-void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
-
 /* EEPROM Functions */
 s32 e1000_init_eeprom_params(struct e1000_hw *hw);
 
@@ -338,66 +313,63 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw);
 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
 
 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
-#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8   /* Host Interface data length */
+#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8   /* Host Interface data length */
 
-#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10      /* Time in ms to process MNG command */
-#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0   /* Cookie offset */
-#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10    /* Cookie length */
+#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10      /* Time in ms to process MNG command */
+#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0   /* Cookie offset */
+#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10    /* Cookie length */
 #define E1000_MNG_IAMT_MODE             0x3
 #define E1000_MNG_ICH_IAMT_MODE         0x2
-#define E1000_IAMT_SIGNATURE            0x544D4149 /* Intel(R) Active Management Technology signature */
+#define E1000_IAMT_SIGNATURE            0x544D4149      /* Intel(R) Active Management Technology signature */
 
-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2 /* DHCP parsing enabled */
+#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1        /* DHCP parsing enabled */
+#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2        /* DHCP parsing enabled */
 #define E1000_VFTA_ENTRY_SHIFT                       0x5
 #define E1000_VFTA_ENTRY_MASK                        0x7F
 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK              0x1F
 
 struct e1000_host_mng_command_header {
-    u8 command_id;
-    u8 checksum;
-    u16 reserved1;
-    u16 reserved2;
-    u16 command_length;
+        u8 command_id;
+        u8 checksum;
+        u16 reserved1;
+        u16 reserved2;
+        u16 command_length;
 };
 
 struct e1000_host_mng_command_info {
-    struct e1000_host_mng_command_header command_header;  /* Command Head/Command Result Head has 4 bytes */
-    u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];   /* Command data can length 0..0x658*/
+        struct e1000_host_mng_command_header command_header;    /* Command Head/Command Result Head has 4 bytes */
+        u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];  /* Command data can length 0..0x658 */
 };
 #ifdef __BIG_ENDIAN
-struct e1000_host_mng_dhcp_cookie{
-    u32 signature;
-    u16 vlan_id;
-    u8 reserved0;
-    u8 status;
-    u32 reserved1;
-    u8 checksum;
-    u8 reserved3;
-    u16 reserved2;
+struct e1000_host_mng_dhcp_cookie {
+        u32 signature;
+        u16 vlan_id;
+        u8 reserved0;
+        u8 status;
+        u32 reserved1;
+        u8 checksum;
+        u8 reserved3;
+        u16 reserved2;
 };
 #else
-struct e1000_host_mng_dhcp_cookie{
-    u32 signature;
-    u8 status;
-    u8 reserved0;
-    u16 vlan_id;
-    u32 reserved1;
-    u16 reserved2;
-    u8 reserved3;
-    u8 checksum;
+struct e1000_host_mng_dhcp_cookie {
+        u32 signature;
+        u8 status;
+        u8 reserved0;
+        u16 vlan_id;
+        u32 reserved1;
+        u16 reserved2;
+        u8 reserved3;
+        u8 checksum;
 };
 #endif
 
-s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
-                                  u16 length);
 bool e1000_check_mng_mode(struct e1000_hw *hw);
-bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
-s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
+s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
-s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
-s32 e1000_read_mac_addr(struct e1000_hw * hw);
+s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
+s32 e1000_read_mac_addr(struct e1000_hw *hw);
 
 /* Filters (multicast, vlan, receive) */
 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@@ -417,18 +389,15 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
 /* Everything else */
 void e1000_reset_adaptive(struct e1000_hw *hw);
 void e1000_update_adaptive(struct e1000_hw *hw);
-void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);
+void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
+                            u32 frame_len, u8 * mac_addr);
 void e1000_get_bus_info(struct e1000_hw *hw);
 void e1000_pci_set_mwi(struct e1000_hw *hw);
 void e1000_pci_clear_mwi(struct e1000_hw *hw);
-s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
 int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
 /* Port I/O is only supported on 82544 and newer */
 void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
-s32 e1000_disable_pciex_master(struct e1000_hw *hw);
-s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
-
 
 #define E1000_READ_REG_IO(a, reg) \
     e1000_read_reg_io((a), E1000_##reg)
@@ -471,36 +440,7 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
 #define E1000_DEV_ID_82547EI             0x1019
 #define E1000_DEV_ID_82547EI_MOBILE      0x101A
-#define E1000_DEV_ID_82571EB_COPPER      0x105E
-#define E1000_DEV_ID_82571EB_FIBER       0x105F
-#define E1000_DEV_ID_82571EB_SERDES      0x1060
-#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
-#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
-#define E1000_DEV_ID_82571EB_QUAD_FIBER  0x10A5
-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE  0x10BC
-#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
-#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
-#define E1000_DEV_ID_82572EI_COPPER      0x107D
-#define E1000_DEV_ID_82572EI_FIBER       0x107E
-#define E1000_DEV_ID_82572EI_SERDES      0x107F
-#define E1000_DEV_ID_82572EI             0x10B9
-#define E1000_DEV_ID_82573E              0x108B
-#define E1000_DEV_ID_82573E_IAMT         0x108C
-#define E1000_DEV_ID_82573L              0x109A
 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
-
-#define E1000_DEV_ID_ICH8_IGP_M_AMT      0x1049
-#define E1000_DEV_ID_ICH8_IGP_AMT        0x104A
-#define E1000_DEV_ID_ICH8_IGP_C          0x104B
-#define E1000_DEV_ID_ICH8_IFE            0x104C
-#define E1000_DEV_ID_ICH8_IFE_GT         0x10C4
-#define E1000_DEV_ID_ICH8_IFE_G          0x10C5
-#define E1000_DEV_ID_ICH8_IGP_M          0x104D
-
 
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
@@ -523,21 +463,20 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
 
 /* The sizes (in bytes) of a ethernet packet */
 #define ENET_HEADER_SIZE             14
-#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
+#define MINIMUM_ETHERNET_FRAME_SIZE  64 /* With FCS */
 #define ETHERNET_FCS_SIZE            4
 #define MINIMUM_ETHERNET_PACKET_SIZE \
     (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 #define CRC_LENGTH                   ETHERNET_FCS_SIZE
 #define MAX_JUMBO_FRAME_SIZE         0x3F00
 
-
 /* 802.1q VLAN Packet Sizes */
-#define VLAN_TAG_SIZE  4     /* 802.3ac tag (not DMAed) */
+#define VLAN_TAG_SIZE  4        /* 802.3ac tag (not DMAed) */
 
 /* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
-#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
-#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
+#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
+#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
+#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
 
 /* Packet Header defines */
 #define IP_PROTOCOL_TCP    6
@@ -567,15 +506,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
     E1000_IMS_RXSEQ  |    \
     E1000_IMS_LSC)
 
-/* Additional interrupts need to be handled for e1000_ich8lan:
-    DSW = The FW changed the status of the DISSW bit in FWSM
-    PHYINT = The LAN connected device generates an interrupt
-    EPRST = Manageability reset event */
-#define IMS_ICH8LAN_ENABLE_MASK (\
-    E1000_IMS_DSW   | \
-    E1000_IMS_PHYINT | \
-    E1000_IMS_EPRST)
-
 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
  * Registers) holds the directed and multicast addresses that we monitor. We
  * reserve one of these spots for our directed address, allowing us room for
@@ -583,100 +513,98 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
  */
 #define E1000_RAR_ENTRIES 15
 
-#define E1000_RAR_ENTRIES_ICH8LAN  6
-
 #define MIN_NUMBER_OF_DESCRIPTORS  8
 #define MAX_NUMBER_OF_DESCRIPTORS  0xFFF8
 
 /* Receive Descriptor */
 struct e1000_rx_desc {
-    __le64 buffer_addr; /* Address of the descriptor's data buffer */
-    __le16 length;     /* Length of data DMAed into data buffer */
-    __le16 csum;       /* Packet checksum */
-    u8 status;      /* Descriptor status */
-    u8 errors;      /* Descriptor Errors */
-    __le16 special;
+        __le64 buffer_addr;     /* Address of the descriptor's data buffer */
+        __le16 length;          /* Length of data DMAed into data buffer */
+        __le16 csum;            /* Packet checksum */
+        u8 status;              /* Descriptor status */
+        u8 errors;              /* Descriptor Errors */
+        __le16 special;
 };
 
 /* Receive Descriptor - Extended */
 union e1000_rx_desc_extended {
-    struct {
-        __le64 buffer_addr;
-        __le64 reserved;
-    } read;
-    struct {
-        struct {
-            __le32 mrq;              /* Multiple Rx Queues */
-            union {
-                __le32 rss;          /* RSS Hash */
-                struct {
-                    __le16 ip_id;    /* IP id */
-                    __le16 csum;     /* Packet Checksum */
-                } csum_ip;
-            } hi_dword;
-        } lower;
-        struct {
-            __le32 status_error;     /* ext status/error */
-            __le16 length;
-            __le16 vlan;             /* VLAN tag */
-        } upper;
-    } wb;  /* writeback */
+        struct {
+                __le64 buffer_addr;
+                __le64 reserved;
+        } read;
+        struct {
+                struct {
+                        __le32 mrq;     /* Multiple Rx Queues */
+                        union {
+                                __le32 rss;     /* RSS Hash */
+                                struct {
+                                        __le16 ip_id;   /* IP id */
+                                        __le16 csum;    /* Packet Checksum */
+                                } csum_ip;
+                        } hi_dword;
+                } lower;
+                struct {
+                        __le32 status_error;    /* ext status/error */
+                        __le16 length;
+                        __le16 vlan;    /* VLAN tag */
+                } upper;
+        } wb;                   /* writeback */
 };
 
 #define MAX_PS_BUFFERS 4
 /* Receive Descriptor - Packet Split */
 union e1000_rx_desc_packet_split {
-    struct {
-        /* one buffer for protocol header(s), three data buffers */
-        __le64 buffer_addr[MAX_PS_BUFFERS];
-    } read;
-    struct {
-        struct {
-            __le32 mrq;              /* Multiple Rx Queues */
-            union {
-                __le32 rss;          /* RSS Hash */
-                struct {
-                    __le16 ip_id;    /* IP id */
-                    __le16 csum;     /* Packet Checksum */
-                } csum_ip;
-            } hi_dword;
-        } lower;
-        struct {
-            __le32 status_error;     /* ext status/error */
-            __le16 length0;          /* length of buffer 0 */
-            __le16 vlan;             /* VLAN tag */
-        } middle;
-        struct {
-            __le16 header_status;
-            __le16 length[3];        /* length of buffers 1-3 */
-        } upper;
-        __le64 reserved;
-    } wb; /* writeback */
+        struct {
+                /* one buffer for protocol header(s), three data buffers */
+                __le64 buffer_addr[MAX_PS_BUFFERS];
+        } read;
+        struct {
+                struct {
+                        __le32 mrq;     /* Multiple Rx Queues */
+                        union {
+                                __le32 rss;     /* RSS Hash */
+                                struct {
+                                        __le16 ip_id;   /* IP id */
+                                        __le16 csum;    /* Packet Checksum */
+                                } csum_ip;
+                        } hi_dword;
+                } lower;
+                struct {
+                        __le32 status_error;    /* ext status/error */
+                        __le16 length0; /* length of buffer 0 */
+                        __le16 vlan;    /* VLAN tag */
+                } middle;
+                struct {
+                        __le16 header_status;
+                        __le16 length[3];       /* length of buffers 1-3 */
+                } upper;
+                __le64 reserved;
+        } wb;                   /* writeback */
 };
 
-/* Receive Decriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */
-#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
-#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
-#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
-#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
-#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
-#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
+/* Receive Descriptor bit definitions */
+#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
+#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
+#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
+#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
+#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 #define E1000_RXD_SPC_PRI_SHIFT 13
-#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 #define E1000_RXD_SPC_CFI_SHIFT 12
 
 #define E1000_RXDEXT_STATERR_CE    0x01000000
@@ -698,7 +626,6 @@ union e1000_rx_desc_packet_split {
     E1000_RXD_ERR_CXE |                \
     E1000_RXD_ERR_RXE)
 
-
 /* Same mask, but for extended and packet split descriptors */
 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
     E1000_RXDEXT_STATERR_CE  |            \
@@ -707,152 +634,145 @@ union e1000_rx_desc_packet_split {
     E1000_RXDEXT_STATERR_CXE |            \
     E1000_RXDEXT_STATERR_RXE)
 
-
 /* Transmit Descriptor */
 struct e1000_tx_desc {
-    __le64 buffer_addr;       /* Address of the descriptor's data buffer */
-    union {
-        __le32 data;
-        struct {
-            __le16 length;    /* Data buffer length */
-            u8 cso;        /* Checksum offset */
-            u8 cmd;        /* Descriptor control */
-        } flags;
-    } lower;
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 css;        /* Checksum start */
-            __le16 special;
-        } fields;
-    } upper;
+        __le64 buffer_addr;     /* Address of the descriptor's data buffer */
+        union {
+                __le32 data;
+                struct {
+                        __le16 length;  /* Data buffer length */
+                        u8 cso; /* Checksum offset */
+                        u8 cmd; /* Descriptor control */
+                } flags;
+        } lower;
+        union {
+                __le32 data;
+                struct {
+                        u8 status;      /* Descriptor status */
+                        u8 css; /* Checksum start */
+                        __le16 special;
+                } fields;
+        } upper;
 };
 
 /* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
+#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
+#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 
 /* Offload Context Descriptor */
 struct e1000_context_desc {
-    union {
-        __le32 ip_config;
-        struct {
-            u8 ipcss;      /* IP checksum start */
-            u8 ipcso;      /* IP checksum offset */
-            __le16 ipcse;     /* IP checksum end */
-        } ip_fields;
-    } lower_setup;
-    union {
-        __le32 tcp_config;
-        struct {
-            u8 tucss;      /* TCP checksum start */
-            u8 tucso;      /* TCP checksum offset */
-            __le16 tucse;     /* TCP checksum end */
-        } tcp_fields;
-    } upper_setup;
-    __le32 cmd_and_length;    /* */
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 hdr_len;    /* Header length */
-            __le16 mss;       /* Maximum segment size */
-        } fields;
-    } tcp_seg_setup;
+        union {
+                __le32 ip_config;
+                struct {
+                        u8 ipcss;       /* IP checksum start */
+                        u8 ipcso;       /* IP checksum offset */
+                        __le16 ipcse;   /* IP checksum end */
+                } ip_fields;
+        } lower_setup;
+        union {
+                __le32 tcp_config;
+                struct {
+                        u8 tucss;       /* TCP checksum start */
+                        u8 tucso;       /* TCP checksum offset */
+                        __le16 tucse;   /* TCP checksum end */
+                } tcp_fields;
+        } upper_setup;
+        __le32 cmd_and_length;  /* */
+        union {
+                __le32 data;
+                struct {
+                        u8 status;      /* Descriptor status */
+                        u8 hdr_len;     /* Header length */
+                        __le16 mss;     /* Maximum segment size */
+                } fields;
+        } tcp_seg_setup;
 };
 
 /* Offload data descriptor */
 struct e1000_data_desc {
-    __le64 buffer_addr;       /* Address of the descriptor's buffer address */
-    union {
-        __le32 data;
-        struct {
-            __le16 length;    /* Data buffer length */
-            u8 typ_len_ext;        /* */
-            u8 cmd;        /* */
-        } flags;
-    } lower;
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 popts;      /* Packet Options */
-            __le16 special;   /* */
-        } fields;
-    } upper;
+        __le64 buffer_addr;     /* Address of the descriptor's buffer address */
+        union {
+                __le32 data;
+                struct {
+                        __le16 length;  /* Data buffer length */
+                        u8 typ_len_ext; /* */
+                        u8 cmd; /* */
+                } flags;
+        } lower;
+        union {
+                __le32 data;
+                struct {
+                        u8 status;      /* Descriptor status */
+                        u8 popts;       /* Packet Options */
+                        __le16 special; /* */
+                } fields;
+        } upper;
 };
 
 /* Filters */
-#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
-#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
-
-#define E1000_NUM_UNICAST_ICH8LAN  7
-#define E1000_MC_TBL_SIZE_ICH8LAN  32
-
+#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
+#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
+#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 
 /* Receive Address Register */
 struct e1000_rar {
-    volatile __le32 low;      /* receive address low */
-    volatile __le32 high;     /* receive address high */
+        volatile __le32 low;    /* receive address low */
+        volatile __le32 high;   /* receive address high */
 };
 
 /* Number of entries in the Multicast Table Array (MTA). */
 #define E1000_NUM_MTA_REGISTERS 128
-#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
 
 /* IPv4 Address Table Entry */
 struct e1000_ipv4_at_entry {
-    volatile u32 ipv4_addr;        /* IP Address (RW) */
-    volatile u32 reserved;
+        volatile u32 ipv4_addr; /* IP Address (RW) */
+        volatile u32 reserved;
 };
 
 /* Four wakeup IP addresses are supported */
 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
 #define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
-#define E1000_IP4AT_SIZE_ICH8LAN          3
 #define E1000_IP6AT_SIZE                  1
 
 /* IPv6 Address Table Entry */
 struct e1000_ipv6_at_entry {
-    volatile u8 ipv6_addr[16];
+        volatile u8 ipv6_addr[16];
 };
 
 /* Flexible Filter Length Table Entry */
 struct e1000_fflt_entry {
-    volatile u32 length;   /* Flexible Filter Length (RW) */
-    volatile u32 reserved;
+        volatile u32 length;    /* Flexible Filter Length (RW) */
+        volatile u32 reserved;
 };
 
 /* Flexible Filter Mask Table Entry */
 struct e1000_ffmt_entry {
-    volatile u32 mask;     /* Flexible Filter Mask (RW) */
-    volatile u32 reserved;
+        volatile u32 mask;      /* Flexible Filter Mask (RW) */
+        volatile u32 reserved;
 };
 
 /* Flexible Filter Value Table Entry */
 struct e1000_ffvt_entry {
-    volatile u32 value;    /* Flexible Filter Value (RW) */
-    volatile u32 reserved;
+        volatile u32 value;     /* Flexible Filter Value (RW) */
+        volatile u32 reserved;
 };
 
 /* Four Flexible Filters are supported */
@@ -879,211 +799,211 @@ struct e1000_ffvt_entry {
  * R/clr - register is read only and is cleared when read
  * A - register array
  */
-#define E1000_CTRL     0x00000  /* Device Control - RW */
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
-#define E1000_STATUS   0x00008  /* Device Status - RO */
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
-#define E1000_RCTL     0x00100  /* RX Control - RW */
-#define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
-#define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
-#define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
-#define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
-#define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
-#define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
-#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
-#define E1000_TCTL     0x00400  /* TX Control - RW */
-#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
-#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
-#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
+#define E1000_CTRL     0x00000  /* Device Control - RW */
+#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
+#define E1000_STATUS   0x00008  /* Device Status - RO */
+#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
+#define E1000_EERD     0x00014  /* EEPROM Read - RW */
+#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
+#define E1000_FLA      0x0001C  /* Flash Access - RW */
+#define E1000_MDIC     0x00020  /* MDI Control - RW */
+#define E1000_SCTL     0x00024  /* SerDes Control - RW */
+#define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
+#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
+#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
+#define E1000_FCT      0x00030  /* Flow Control Type - RW */
+#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
+#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
+#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
+#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
+#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
+#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
+#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
+#define E1000_RCTL     0x00100  /* RX Control - RW */
+#define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
+#define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
+#define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
+#define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
+#define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
+#define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
+#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
+#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
+#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
+#define E1000_TCTL     0x00400  /* TX Control - RW */
+#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
+#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
+#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
+#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
+#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
+#define E1000_EXTCNF_CTRL  0x00F00      /* Extended Configuration Control */
+#define E1000_EXTCNF_SIZE  0x00F08      /* Extended Configuration Size */
+#define E1000_PHY_CTRL     0x00F10      /* PHY Control Register in CSR */
 #define FEXTNVM_SW_CONFIG  0x0001
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
+#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
+#define E1000_PBS      0x01008  /* Packet Buffer Size */
+#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
 #define E1000_FLASH_UPDATES 1000
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
-#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
-#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
-#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
-#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
-#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
-#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
-#define E1000_RDBAL0   E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
-#define E1000_RDBAH0   E1000_RDBAH /* RX Desc Base Address High (0) - RW */
-#define E1000_RDLEN0   E1000_RDLEN /* RX Desc Length (0) - RW */
-#define E1000_RDH0     E1000_RDH   /* RX Desc Head (0) - RW */
-#define E1000_RDT0     E1000_RDT   /* RX Desc Tail (0) - RW */
-#define E1000_RDTR0    E1000_RDTR  /* RX Delay Timer (0) - RW */
-#define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
-#define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
-#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
-#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
-#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
-#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
-#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
-#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
-#define E1000_TDFTS    0x03428  /* TX Data FIFO Tail Saved - RW */
-#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
-#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
-#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
-#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
-#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
-#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
-#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
-#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
-#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_TARC0    0x03840  /* TX Arbitration Count (0) */
-#define E1000_TDBAL1   0x03900  /* TX Desc Base Address Low (1) - RW */
-#define E1000_TDBAH1   0x03904  /* TX Desc Base Address High (1) - RW */
-#define E1000_TDLEN1   0x03908  /* TX Desc Length (1) - RW */
-#define E1000_TDH1     0x03910  /* TX Desc Head (1) - RW */
-#define E1000_TDT1     0x03918  /* TX Desc Tail (1) - RW */
-#define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
-#define E1000_TARC1    0x03940  /* TX Arbitration Count (1) */
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
-#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
-#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
-#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
-#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
-#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
-#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
-#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
-#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
-#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
-#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
-#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
-#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
-#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
-#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
-#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
-#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
-#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
-#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
-#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
-#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
-#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
-#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
-#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
-#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
-#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
-#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
-#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
-#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
-#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
-#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
-#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
-#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
-#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
-#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
-#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
-#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
-#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
-#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Packet Timer Expire Count */
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Absolute Timer Expire Count */
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Packet Timer Expire Count */
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Absolute Timer Expire Count */
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Minimum Threshold Count */
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
-#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
-#define E1000_MANC     0x05820  /* Management Control - RW */
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
-#define E1000_HOST_IF  0x08800  /* Host Interface */
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
-
-#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA     0x0003C  /* PHY address - RW */
-#define E1000_MANC2H     0x05860  /* Managment Control To Host - RW */
-#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
-
-#define E1000_GCR       0x05B00 /* PCI-Ex Control */
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
-#define E1000_HICR      0x08F00 /* Host Inteface Control */
+#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
+#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
+#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
+#define E1000_FLSWCTL  0x01030  /* FLASH control register */
+#define E1000_FLSWDATA 0x01034  /* FLASH data register */
+#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
+#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
+#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
+#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
+#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
+#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
+#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
+#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
+#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
+#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
+#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
+#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
+#define E1000_RDBAL0   E1000_RDBAL      /* RX Desc Base Address Low (0) - RW */
+#define E1000_RDBAH0   E1000_RDBAH      /* RX Desc Base Address High (0) - RW */
+#define E1000_RDLEN0   E1000_RDLEN      /* RX Desc Length (0) - RW */
+#define E1000_RDH0     E1000_RDH        /* RX Desc Head (0) - RW */
+#define E1000_RDT0     E1000_RDT        /* RX Desc Tail (0) - RW */
+#define E1000_RDTR0    E1000_RDTR       /* RX Delay Timer (0) - RW */
+#define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
+#define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
+#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
+#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
+#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
+#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
+#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
+#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
+#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
+#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
+#define E1000_TDFTS    0x03428  /* TX Data FIFO Tail Saved - RW */
+#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
+#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
+#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
+#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
+#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
+#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
+#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
+#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
+#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
+#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_TARC0    0x03840  /* TX Arbitration Count (0) */
+#define E1000_TDBAL1   0x03900  /* TX Desc Base Address Low (1) - RW */
+#define E1000_TDBAH1   0x03904  /* TX Desc Base Address High (1) - RW */
+#define E1000_TDLEN1   0x03908  /* TX Desc Length (1) - RW */
+#define E1000_TDH1     0x03910  /* TX Desc Head (1) - RW */
+#define E1000_TDT1     0x03918  /* TX Desc Tail (1) - RW */
+#define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
+#define E1000_TARC1    0x03940  /* TX Arbitration Count (1) */
+#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
+#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
+#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
+#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
+#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
+#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
+#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
+#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
+#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
+#define E1000_COLC     0x04028  /* Collision Count - R/clr */
+#define E1000_DC       0x04030  /* Defer Count - R/clr */
+#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
+#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
+#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
+#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
+#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
+#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
+#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
+#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
+#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
+#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
+#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
+#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
+#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
+#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
+#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
+#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
+#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
+#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
+#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
+#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
+#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
+#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
+#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
+#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
+#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
+#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
+#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
+#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
+#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
+#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
+#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
+#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
+#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
+#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
+#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
+#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
+#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
+#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
+#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
+#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
+#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
+#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
+#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
+#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
+#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
+#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
+#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
+#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
+#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Packet Timer Expire Count */
+#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Absolute Timer Expire Count */
+#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Packet Timer Expire Count */
+#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Absolute Timer Expire Count */
+#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
+#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Minimum Threshold Count */
+#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
+#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
+#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
+#define E1000_RFCTL    0x05008  /* Receive Filter Control */
+#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
+#define E1000_RA       0x05400  /* Receive Address - RW Array */
+#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
+#define E1000_WUC      0x05800  /* Wakeup Control - RW */
+#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
+#define E1000_WUS      0x05810  /* Wakeup Status - RO */
+#define E1000_MANC     0x05820  /* Management Control - RW */
+#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
+#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
+#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
+#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
+#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
+#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
+#define E1000_HOST_IF  0x08800  /* Host Interface */
+#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
+#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
+
+#define E1000_KUMCTRLSTA 0x00034        /* MAC-PHY interface - RW */
+#define E1000_MDPHYA     0x0003C        /* PHY address - RW */
+#define E1000_MANC2H     0x05860        /* Managment Control To Host - RW */
+#define E1000_SW_FW_SYNC 0x05B5C        /* Software-Firmware Synchronization - RW */
+
+#define E1000_GCR       0x05B00 /* PCI-Ex Control */
+#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
+#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
+#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
+#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
+#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
+#define E1000_SWSM      0x05B50 /* SW Semaphore */
+#define E1000_FWSM      0x05B54 /* FW Semaphore */
+#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
+#define E1000_HICR      0x08F00 /* Host Interface Control */
 
 /* RSS registers */
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
-#define E1000_RETA      0x05C00 /* Redirection Table - RW Array */
-#define E1000_RSSRK     0x05C80 /* RSS Random Key - RW Array */
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
+#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
+#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
+#define E1000_RETA      0x05C00 /* Redirection Table - RW Array */
+#define E1000_RSSRK     0x05C80 /* RSS Random Key - RW Array */
+#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
+#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
 /* Register Set (82542)
  *
  * Some of the 82542 registers are located at different offsets than they are
@@ -1123,19 +1043,19 @@ struct e1000_ffvt_entry {
 #define E1000_82542_RDLEN0   E1000_82542_RDLEN
 #define E1000_82542_RDH0     E1000_82542_RDH
 #define E1000_82542_RDT0     E1000_82542_RDT
-#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
-                                                       * RX Control - RW */
+#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8))   /* Split and Replication
+                                                         * RX Control - RW */
 #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
-#define E1000_82542_RDBAH3   0x02B04 /* RX Desc Base High Queue 3 - RW */
-#define E1000_82542_RDBAL3   0x02B00 /* RX Desc Low Queue 3 - RW */
-#define E1000_82542_RDLEN3   0x02B08 /* RX Desc Length Queue 3 - RW */
-#define E1000_82542_RDH3     0x02B10 /* RX Desc Head Queue 3 - RW */
-#define E1000_82542_RDT3     0x02B18 /* RX Desc Tail Queue 3 - RW */
-#define E1000_82542_RDBAL2   0x02A00 /* RX Desc Base Low Queue 2 - RW */
-#define E1000_82542_RDBAH2   0x02A04 /* RX Desc Base High Queue 2 - RW */
-#define E1000_82542_RDLEN2   0x02A08 /* RX Desc Length Queue 2 - RW */
-#define E1000_82542_RDH2     0x02A10 /* RX Desc Head Queue 2 - RW */
-#define E1000_82542_RDT2     0x02A18 /* RX Desc Tail Queue 2 - RW */
+#define E1000_82542_RDBAH3   0x02B04    /* RX Desc Base High Queue 3 - RW */
+#define E1000_82542_RDBAL3   0x02B00    /* RX Desc Low Queue 3 - RW */
+#define E1000_82542_RDLEN3   0x02B08    /* RX Desc Length Queue 3 - RW */
+#define E1000_82542_RDH3     0x02B10    /* RX Desc Head Queue 3 - RW */
+#define E1000_82542_RDT3     0x02B18    /* RX Desc Tail Queue 3 - RW */
+#define E1000_82542_RDBAL2   0x02A00    /* RX Desc Base Low Queue 2 - RW */
+#define E1000_82542_RDBAH2   0x02A04    /* RX Desc Base High Queue 2 - RW */
+#define E1000_82542_RDLEN2   0x02A08    /* RX Desc Length Queue 2 - RW */
+#define E1000_82542_RDH2     0x02A10    /* RX Desc Head Queue 2 - RW */
+#define E1000_82542_RDT2     0x02A18    /* RX Desc Tail Queue 2 - RW */
 #define E1000_82542_RDTR1    0x00130
 #define E1000_82542_RDBAL1   0x00138
 #define E1000_82542_RDBAH1   0x0013C
@@ -1302,288 +1222,281 @@ struct e1000_ffvt_entry {
 #define E1000_82542_RSSIR       E1000_RSSIR
 #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
 #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
-#define E1000_82542_MANC2H      E1000_MANC2H
 
 /* Statistics counters collected by the MAC */
 struct e1000_hw_stats {
-        u64             crcerrs;
-        u64             algnerrc;
-        u64             symerrs;
-        u64             rxerrc;
-        u64             txerrc;
-        u64             mpc;
-        u64             scc;
-        u64             ecol;
-        u64             mcc;
-        u64             latecol;
-        u64             colc;
-        u64             dc;
-        u64             tncrs;
-        u64             sec;
-        u64             cexterr;
-        u64             rlec;
-        u64             xonrxc;
-        u64             xontxc;
-        u64             xoffrxc;
-        u64             xofftxc;
-        u64             fcruc;
-        u64             prc64;
-        u64             prc127;
-        u64             prc255;
-        u64             prc511;
-        u64             prc1023;
-        u64             prc1522;
-        u64             gprc;
-        u64             bprc;
-        u64             mprc;
-        u64             gptc;
-        u64             gorcl;
-        u64             gorch;
-        u64             gotcl;
-        u64             gotch;
-        u64             rnbc;
-        u64             ruc;
-        u64             rfc;
-        u64             roc;
-        u64             rlerrc;
-        u64             rjc;
-        u64             mgprc;
-        u64             mgpdc;
-        u64             mgptc;
-        u64             torl;
-        u64             torh;
-        u64             totl;
-        u64             toth;
-        u64             tpr;
-        u64             tpt;
-        u64             ptc64;
-        u64             ptc127;
-        u64             ptc255;
-        u64             ptc511;
-        u64             ptc1023;
-        u64             ptc1522;
-        u64             mptc;
-        u64             bptc;
-        u64             tsctc;
-        u64             tsctfc;
-        u64             iac;
-        u64             icrxptc;
-        u64             icrxatc;
-        u64             ictxptc;
-        u64             ictxatc;
-        u64             ictxqec;
-        u64             ictxqmtc;
-        u64             icrxdmtc;
-        u64             icrxoc;
+        u64 crcerrs;
+        u64 algnerrc;
+        u64 symerrs;
+        u64 rxerrc;
+        u64 txerrc;
+        u64 mpc;
+        u64 scc;
+        u64 ecol;
+        u64 mcc;
+        u64 latecol;
+        u64 colc;
+        u64 dc;
+        u64 tncrs;
+        u64 sec;
+        u64 cexterr;
+        u64 rlec;
+        u64 xonrxc;
+        u64 xontxc;
+        u64 xoffrxc;
+        u64 xofftxc;
+        u64 fcruc;
+        u64 prc64;
+        u64 prc127;
+        u64 prc255;
+        u64 prc511;
+        u64 prc1023;
+        u64 prc1522;
+        u64 gprc;
+        u64 bprc;
+        u64 mprc;
+        u64 gptc;
+        u64 gorcl;
+        u64 gorch;
+        u64 gotcl;
+        u64 gotch;
+        u64 rnbc;
+        u64 ruc;
+        u64 rfc;
+        u64 roc;
+        u64 rlerrc;
+        u64 rjc;
+        u64 mgprc;
+        u64 mgpdc;
+        u64 mgptc;
+        u64 torl;
+        u64 torh;
+        u64 totl;
+        u64 toth;
+        u64 tpr;
+        u64 tpt;
+        u64 ptc64;
+        u64 ptc127;
+        u64 ptc255;
+        u64 ptc511;
+        u64 ptc1023;
+        u64 ptc1522;
+        u64 mptc;
+        u64 bptc;
+        u64 tsctc;
+        u64 tsctfc;
+        u64 iac;
+        u64 icrxptc;
+        u64 icrxatc;
+        u64 ictxptc;
+        u64 ictxatc;
+        u64 ictxqec;
+        u64 ictxqmtc;
+        u64 icrxdmtc;
+        u64 icrxoc;
 };
 
 /* Structure containing variables used by the shared code (e1000_hw.c) */
 struct e1000_hw {
-        u8 __iomem              *hw_addr;
-        u8 __iomem              *flash_address;
-        e1000_mac_type          mac_type;
-        e1000_phy_type          phy_type;
-        u32             phy_init_script;
-        e1000_media_type        media_type;
-        void                    *back;
-        struct e1000_shadow_ram *eeprom_shadow_ram;
-        u32             flash_bank_size;
-        u32             flash_base_addr;
-        e1000_fc_type           fc;
-        e1000_bus_speed         bus_speed;
-        e1000_bus_width         bus_width;
-        e1000_bus_type          bus_type;
+        u8 __iomem *hw_addr;
+        u8 __iomem *flash_address;
+        e1000_mac_type mac_type;
+        e1000_phy_type phy_type;
+        u32 phy_init_script;
+        e1000_media_type media_type;
+        void *back;
+        struct e1000_shadow_ram *eeprom_shadow_ram;
+        u32 flash_bank_size;
+        u32 flash_base_addr;
+        e1000_fc_type fc;
+        e1000_bus_speed bus_speed;
+        e1000_bus_width bus_width;
+        e1000_bus_type bus_type;
         struct e1000_eeprom_info eeprom;
-        e1000_ms_type           master_slave;
-        e1000_ms_type           original_master_slave;
-        e1000_ffe_config        ffe_config_state;
-        u32             asf_firmware_present;
-        u32             eeprom_semaphore_present;
-        u32             swfw_sync_present;
-        u32             swfwhw_semaphore_present;
-        unsigned long           io_base;
-        u32             phy_id;
-        u32             phy_revision;
-        u32             phy_addr;
-        u32             original_fc;
-        u32             txcw;
-        u32             autoneg_failed;
-        u32             max_frame_size;
-        u32             min_frame_size;
-        u32             mc_filter_type;
-        u32             num_mc_addrs;
-        u32             collision_delta;
-        u32             tx_packet_delta;
-        u32             ledctl_default;
-        u32             ledctl_mode1;
-        u32             ledctl_mode2;
-        bool                    tx_pkt_filtering;
+        e1000_ms_type master_slave;
+        e1000_ms_type original_master_slave;
+        e1000_ffe_config ffe_config_state;
+        u32 asf_firmware_present;
+        u32 eeprom_semaphore_present;
+        unsigned long io_base;
+        u32 phy_id;
+        u32 phy_revision;
+        u32 phy_addr;
+        u32 original_fc;
+        u32 txcw;
+        u32 autoneg_failed;
+        u32 max_frame_size;
+        u32 min_frame_size;
+        u32 mc_filter_type;
+        u32 num_mc_addrs;
+        u32 collision_delta;
+        u32 tx_packet_delta;
+        u32 ledctl_default;
+        u32 ledctl_mode1;
+        u32 ledctl_mode2;
+        bool tx_pkt_filtering;
         struct e1000_host_mng_dhcp_cookie mng_cookie;
-        u16             phy_spd_default;
-        u16             autoneg_advertised;
-        u16             pci_cmd_word;
-        u16             fc_high_water;
-        u16             fc_low_water;
-        u16             fc_pause_time;
-        u16             current_ifs_val;
-        u16             ifs_min_val;
-        u16             ifs_max_val;
-        u16             ifs_step_size;
-        u16             ifs_ratio;
-        u16             device_id;
-        u16             vendor_id;
-        u16             subsystem_id;
-        u16             subsystem_vendor_id;
-        u8                      revision_id;
-        u8                      autoneg;
-        u8                      mdix;
-        u8                      forced_speed_duplex;
-        u8                      wait_autoneg_complete;
-        u8                      dma_fairness;
-        u8                      mac_addr[NODE_ADDRESS_SIZE];
-        u8                      perm_mac_addr[NODE_ADDRESS_SIZE];
-        bool                    disable_polarity_correction;
-        bool                    speed_downgraded;
-        e1000_smart_speed       smart_speed;
-        e1000_dsp_config        dsp_config_state;
-        bool                    get_link_status;
-        bool                    serdes_link_down;
-        bool                    tbi_compatibility_en;
-        bool                    tbi_compatibility_on;
-        bool                    laa_is_present;
-        bool                    phy_reset_disable;
-        bool                    initialize_hw_bits_disable;
-        bool                    fc_send_xon;
-        bool                    fc_strict_ieee;
-        bool                    report_tx_early;
-        bool                    adaptive_ifs;
-        bool                    ifs_params_forced;
-        bool                    in_ifs_mode;
-        bool                    mng_reg_access_disabled;
-        bool                    leave_av_bit_off;
-        bool                    kmrn_lock_loss_workaround_disabled;
-        bool                    bad_tx_carr_stats_fd;
-        bool                    has_manc2h;
-        bool                    rx_needs_kicking;
-        bool                    has_smbus;
+        u16 phy_spd_default;
+        u16 autoneg_advertised;
+        u16 pci_cmd_word;
+        u16 fc_high_water;
+        u16 fc_low_water;
+        u16 fc_pause_time;
+        u16 current_ifs_val;
+        u16 ifs_min_val;
+        u16 ifs_max_val;
+        u16 ifs_step_size;
+        u16 ifs_ratio;
+        u16 device_id;
+        u16 vendor_id;
+        u16 subsystem_id;
+        u16 subsystem_vendor_id;
+        u8 revision_id;
+        u8 autoneg;
+        u8 mdix;
+        u8 forced_speed_duplex;
+        u8 wait_autoneg_complete;
+        u8 dma_fairness;
+        u8 mac_addr[NODE_ADDRESS_SIZE];
+        u8 perm_mac_addr[NODE_ADDRESS_SIZE];
+        bool disable_polarity_correction;
+        bool speed_downgraded;
+        e1000_smart_speed smart_speed;
+        e1000_dsp_config dsp_config_state;
+        bool get_link_status;
+        bool serdes_has_link;
+        bool tbi_compatibility_en;
+        bool tbi_compatibility_on;
+        bool laa_is_present;
+        bool phy_reset_disable;
+        bool initialize_hw_bits_disable;
+        bool fc_send_xon;
+        bool fc_strict_ieee;
+        bool report_tx_early;
+        bool adaptive_ifs;
+        bool ifs_params_forced;
+        bool in_ifs_mode;
+        bool mng_reg_access_disabled;
+        bool leave_av_bit_off;
+        bool bad_tx_carr_stats_fd;
+        bool has_smbus;
 };
 
-
-#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
-#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
-#define E1000_EEPROM_RW_REG_DATA   16   /* Offset to data in EEPROM read/write registers */
-#define E1000_EEPROM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
-#define E1000_EEPROM_RW_REG_START  1    /* First bit for telling part to start operation */
-#define E1000_EEPROM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
-#define E1000_EEPROM_POLL_WRITE    1    /* Flag for polling for write complete */
-#define E1000_EEPROM_POLL_READ     0    /* Flag for polling for read complete */
+#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
+#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
+#define E1000_EEPROM_RW_REG_DATA   16   /* Offset to data in EEPROM read/write registers */
+#define E1000_EEPROM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
+#define E1000_EEPROM_RW_REG_START  1    /* First bit for telling part to start operation */
+#define E1000_EEPROM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
+#define E1000_EEPROM_POLL_WRITE    1    /* Flag for polling for write complete */
+#define E1000_EEPROM_POLL_READ     0    /* Flag for polling for read complete */
 /* Register Bit Masks */
 /* Device Control */
-#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
-#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
-#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
-#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
-#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
-#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
-#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
-#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
-#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
-#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
-#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000  /* Global reset */
-#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT 0x02000000  /* Initiate an interrupt to manageability engine */
+#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004        /*Blocks new Master requests */
+#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
+#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
+#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
+#define E1000_CTRL_D_UD_POLARITY 0x00004000     /* Defined polarity of Dock/Undock indication in SDP[0] */
+#define E1000_CTRL_FORCE_PHY_RESET 0x00008000   /* Reset both PHY ports, through PHYRST_N pin */
+#define E1000_CTRL_EXT_LINK_EN 0x00010000       /* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
+#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST      0x04000000  /* Global reset */
+#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
+#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
+#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
+#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
 
 /* Device Status */
-#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
+#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 #define E1000_STATUS_FUNC_SHIFT 2
-#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
+#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
+#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
+#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
+#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
 #define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion
-                                                   by EEPROM/Flash */
-#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
-#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state. Clear on write '0'. */
-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
-#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
-#define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
-#define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution disabled */
-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
+#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion
+                                                   by EEPROM/Flash */
+#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
+#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state. Clear on write '0'. */
+#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000       /* Status of Master requests. */
+#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
+#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
+#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
+#define E1000_STATUS_BMC_SKU_0  0x00100000      /* BMC USB redirect disabled */
+#define E1000_STATUS_BMC_SKU_1  0x00200000      /* BMC SRAM disabled */
+#define E1000_STATUS_BMC_SKU_2  0x00400000      /* BMC SDRAM disabled */
+#define E1000_STATUS_BMC_CRYPTO 0x00800000      /* BMC crypto disabled */
+#define E1000_STATUS_BMC_LITE   0x01000000      /* BMC external code execution disabled */
+#define E1000_STATUS_RGMII_ENABLE 0x02000000    /* RGMII disabled */
 #define E1000_STATUS_FUSE_8       0x04000000
 #define E1000_STATUS_FUSE_9       0x08000000
-#define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
-#define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
+#define E1000_STATUS_SERDES0_DIS  0x10000000    /* SERDES disabled on port 0 */
+#define E1000_STATUS_SERDES1_DIS  0x20000000    /* SERDES disabled on port 1 */
 
-/* Constants used to intrepret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
+/* Constants used to interpret the masked PCI-X bus speed. */
+#define E1000_STATUS_PCIX_SPEED_66  0x00000000  /* PCI-X bus speed  50-66 MHz */
+#define E1000_STATUS_PCIX_SPEED_100 0x00004000  /* PCI-X bus speed  66-100 MHz */
+#define E1000_STATUS_PCIX_SPEED_133 0x00008000  /* PCI-X bus speed 100-133 MHz */
 
 /* EEPROM/Flash Control */
-#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
-#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
-#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
-#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
+#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
+#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
+#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
+#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
 #define E1000_EECD_FWE_MASK  0x00000030
-#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
 #define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
-#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
-#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
-#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
-#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
-                                         * (0-small, 1-large) */
-#define E1000_EECD_TYPE      0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
+#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
+#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
+#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
+#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
+#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
+                                         * (0-small, 1-large) */
+#define E1000_EECD_TYPE      0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
-#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
+#define E1000_EEPROM_GRANT_ATTEMPTS 1000        /* EEPROM # attempts to gain grant */
 #endif
-#define E1000_EECD_AUTO_RD          0x00000200  /* EEPROM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* EEprom Size */
+#define E1000_EECD_AUTO_RD          0x00000200  /* EEPROM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* EEprom Size */
 #define E1000_EECD_SIZE_EX_SHIFT    11
-#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
-#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
+#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
+#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
+#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
 #define E1000_EECD_SECVAL_SHIFT      22
 #define E1000_STM_OPCODE     0xDB00
 #define E1000_HICR_FW_RESET  0xC0
@@ -1593,12 +1506,12 @@ struct e1000_hw {
 #define E1000_ICH_NVM_SIG_MASK     0xC0
 
 /* EEPROM Read */
-#define E1000_EERD_START      0x00000001 /* Start Read */
-#define E1000_EERD_DONE       0x00000010 /* Read Done */
+#define E1000_EERD_START      0x00000001        /* Start Read */
+#define E1000_EERD_DONE       0x00000010        /* Read Done */
 #define E1000_EERD_ADDR_SHIFT 8
-#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
+#define E1000_EERD_ADDR_MASK  0x0000FF00        /* Read Address */
 #define E1000_EERD_DATA_SHIFT 16
-#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
+#define E1000_EERD_DATA_MASK  0xFFFF0000        /* Read Data */
 
 /* SPI EEPROM Status Register */
 #define EEPROM_STATUS_RDY_SPI  0x01
@@ -1608,25 +1521,25 @@ struct e1000_hw {
 #define EEPROM_STATUS_WPEN_SPI 0x80
 
 /* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_GPI0_EN   0x00000001     /* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN   0x00000002     /* Maps SDP5 to GPI1 */
 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
+#define E1000_CTRL_EXT_GPI2_EN   0x00000004     /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN   0x00000008     /* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_SDP4_DATA 0x00000010     /* Value of SW Defineable Pin 4 */
+#define E1000_CTRL_EXT_SDP5_DATA 0x00000020     /* Value of SW Defineable Pin 5 */
 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
-#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
-#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_SDP6_DATA 0x00000040     /* Value of SW Defineable Pin 6 */
+#define E1000_CTRL_EXT_SDP7_DATA 0x00000080     /* Value of SW Defineable Pin 7 */
+#define E1000_CTRL_EXT_SDP4_DIR  0x00000100     /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR  0x00000200     /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR  0x00000400     /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP7_DIR  0x00000800     /* Direction of SDP7 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK    0x00001000     /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST    0x00002000     /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS       0x00004000     /* Invert Power State */
+#define E1000_CTRL_EXT_SPD_BYPS  0x00008000     /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS    0x00020000     /* Relaxed Ordering disable */
 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
@@ -1638,11 +1551,11 @@ struct e1000_hw {
 #define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
 #define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
 #define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
-#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
-#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */
-#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers after IMS clear */
-#define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error detection enabled */
-#define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity error detection enable */
+#define E1000_CTRL_EXT_DRV_LOAD       0x10000000        /* Driver loaded bit for FW */
+#define E1000_CTRL_EXT_IAME           0x08000000        /* Interrupt acknowledge Auto-mask */
+#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000        /* Clear Interrupt timers after IMS clear */
+#define E1000_CRTL_EXT_PB_PAREN       0x01000000        /* packet buffer parity error detection enabled */
+#define E1000_CTRL_EXT_DF_PAREN       0x02000000        /* descriptor FIFO parity error detection enable */
 #define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
 
 /* MDI Control */
@@ -1742,167 +1655,167 @@ struct e1000_hw {
 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 
 /* Receive Address */
-#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 
 /* Interrupt Cause Read */
-#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
-#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
-#define E1000_ICR_RXO           0x00000040 /* rx overrun */
-#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG         0x00000400 /* RX /c/ ordered set */
-#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXDW          0x00000001      /* Transmit desc written back */
+#define E1000_ICR_TXQE          0x00000002      /* Transmit Queue empty */
+#define E1000_ICR_LSC           0x00000004      /* Link Status Change */
+#define E1000_ICR_RXSEQ         0x00000008      /* rx sequence error */
+#define E1000_ICR_RXDMT0        0x00000010      /* rx desc min. threshold (0) */
+#define E1000_ICR_RXO           0x00000040      /* rx overrun */
+#define E1000_ICR_RXT0          0x00000080      /* rx timer intr (ring 0) */
+#define E1000_ICR_MDAC          0x00000200      /* MDIO access complete */
+#define E1000_ICR_RXCFG         0x00000400      /* RX /c/ ordered set */
+#define E1000_ICR_GPI_EN0       0x00000800      /* GP Int 0 */
+#define E1000_ICR_GPI_EN1       0x00001000      /* GP Int 1 */
+#define E1000_ICR_GPI_EN2       0x00002000      /* GP Int 2 */
+#define E1000_ICR_GPI_EN3       0x00004000      /* GP Int 3 */
 #define E1000_ICR_TXD_LOW       0x00008000
 #define E1000_ICR_SRPD          0x00010000
-#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
-#define E1000_ICR_MNG           0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
-#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */
-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR  0x00400000 /* host arb read buffer parity error */
-#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
-#define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
-#define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW bit in the FWSM */
-#define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates an interrupt */
-#define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
+#define E1000_ICR_ACK           0x00020000      /* Receive Ack frame */
+#define E1000_ICR_MNG           0x00040000      /* Manageability event */
+#define E1000_ICR_DOCK          0x00080000      /* Dock/Undock */
+#define E1000_ICR_INT_ASSERTED  0x80000000      /* If this bit asserted, the driver should claim the interrupt */
+#define E1000_ICR_RXD_FIFO_PAR0 0x00100000      /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR0 0x00200000      /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_ICR_HOST_ARB_PAR  0x00400000      /* host arb read buffer parity error */
+#define E1000_ICR_PB_PAR        0x00800000      /* packet buffer parity error */
+#define E1000_ICR_RXD_FIFO_PAR1 0x01000000      /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR1 0x02000000      /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_ICR_ALL_PARITY    0x03F00000      /* all parity error bits */
+#define E1000_ICR_DSW           0x00000020      /* FW changed the status of DISSW bit in the FWSM */
+#define E1000_ICR_PHYINT        0x00001000      /* LAN connected device generates an interrupt */
+#define E1000_ICR_EPRST         0x00100000      /* ME hardware reset occurs */
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
+#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
+#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
+#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
 #define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_ICS_SRPD      E1000_ICR_SRPD
-#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
+#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
+#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
+#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_ICS_DSW       E1000_ICR_DSW
 #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
 #define E1000_ICS_EPRST     E1000_ICR_EPRST
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
+#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
+#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
+#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
 #define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_IMS_SRPD      E1000_ICR_SRPD
-#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
+#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
+#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
+#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_IMS_DSW       E1000_ICR_DSW
 #define E1000_IMS_PHYINT    E1000_ICR_PHYINT
 #define E1000_IMS_EPRST     E1000_ICR_EPRST
 
 /* Interrupt Mask Clear */
-#define E1000_IMC_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_IMC_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMC_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_IMC_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_IMC_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_IMC_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMC_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_IMC_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
+#define E1000_IMC_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_IMC_LSC       E1000_ICR_LSC       /* Link Status Change */
+#define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
+#define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
+#define E1000_IMC_RXO       E1000_ICR_RXO       /* rx overrun */
+#define E1000_IMC_RXT0      E1000_ICR_RXT0      /* rx timer intr */
+#define E1000_IMC_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_IMC_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
+#define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
 #define E1000_IMC_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_IMC_SRPD      E1000_ICR_SRPD
-#define E1000_IMC_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMC_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMC_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_IMC_ACK       E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_IMC_MNG       E1000_ICR_MNG       /* Manageability event */
+#define E1000_IMC_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
+#define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
+#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_IMC_DSW       E1000_ICR_DSW
 #define E1000_IMC_PHYINT    E1000_ICR_PHYINT
 #define E1000_IMC_EPRST     E1000_ICR_EPRST
 
 /* Receive Control */
-#define E1000_RCTL_RST            0x00000001    /* Software reset */
-#define E1000_RCTL_EN             0x00000002    /* enable */
-#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
-#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
-#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
-#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
-#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
-#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
-#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
-#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
-#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
-#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+#define E1000_RCTL_RST            0x00000001    /* Software reset */
+#define E1000_RCTL_EN             0x00000002    /* enable */
+#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
+#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
+#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
+#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
+#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
+#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
+#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
+#define E1000_RCTL_MO_SHIFT       12    /* multicast offset shift */
+#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
+#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
+#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
-#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
+#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
+#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
-#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
-#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
-#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
-#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
-#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
-#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
-#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
+#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
+#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
+#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
+#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
+#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
+#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
+#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
+#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
+#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
+#define E1000_RCTL_FLXBUF_SHIFT   27    /* Flexible buffer shift */
 
 /* Use byte values for the following shift parameters
  * Usage:
@@ -1925,10 +1838,10 @@ struct e1000_hw {
 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 
-#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
-#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
-#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
-#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+#define E1000_PSRCTL_BSIZE0_SHIFT  7    /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT  2    /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT  6    /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT 14    /* Shift _left_ 14 */
 
 /* SW_W_SYNC definitions */
 #define E1000_SWFW_EEP_SM     0x0001
@@ -1937,17 +1850,17 @@ struct e1000_hw {
 #define E1000_SWFW_MAC_CSR_SM 0x0008
 
 /* Receive Descriptor */
-#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
-#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
-#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
-#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
-#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
+#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
+#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
+#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
+#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
+#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
 
 /* Flow Control */
-#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
-#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
+#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 
 /* Header split receive */
 #define E1000_RFCTL_ISCSI_DIS           0x00000001
@@ -1967,66 +1880,64 @@ struct e1000_hw {
 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
 
 /* Receive Descriptor Control */
-#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
-#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
-#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
-#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
+#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
+#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
+#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
 
 /* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
-#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
-                                              still to be processed. */
+#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH 0xFE000000        /* TXDCTL Low Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_COUNT_DESC 0x00400000      /* Enable the counting of desc.
+                                                   still to be processed. */
 /* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
-#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
+#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
+#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
+#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
+#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
+#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
+#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
+#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 
 /* Receive Configuration Word */
-#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
-#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
-#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
-#define E1000_RXCW_CC    0x10000000     /* Receive config change */
-#define E1000_RXCW_C     0x20000000     /* Receive config */
-#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
-#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
+#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
+#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
+#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
+#define E1000_RXCW_CC    0x10000000     /* Receive config change */
+#define E1000_RXCW_C     0x20000000     /* Receive config */
+#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
+#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
 
 /* Transmit Control */
-#define E1000_TCTL_RST    0x00000001    /* software reset */
-#define E1000_TCTL_EN     0x00000002    /* enable tx */
-#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
-#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
-#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
-#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+#define E1000_TCTL_RST    0x00000001    /* software reset */
+#define E1000_TCTL_EN     0x00000002    /* enable tx */
+#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
+#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
+#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
+#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
+#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
+#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
+#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
 /* Extended Transmit Control */
-#define E1000_TCTL_EXT_BST_MASK  0x000003FF /* Backoff Slot Time */
-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
-
-#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX   0x00010000
+#define E1000_TCTL_EXT_BST_MASK  0x000003FF     /* Backoff Slot Time */
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00     /* Gigabit Carry Extend Padding */
 
 /* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
-#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
+#define E1000_RXCSUM_PCSS_MASK 0x000000FF       /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL     0x00000100       /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL     0x00000200       /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL   0x00000400       /* IPv6 checksum offload */
+#define E1000_RXCSUM_IPPCSE    0x00001000       /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD      0x00002000       /* packet checksum disabled */
 
 /* Multiple Receive Queue Control */
 #define E1000_MRQC_ENABLE_MASK              0x00000003
@@ -2042,141 +1953,141 @@ struct e1000_hw {
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define E1000_WUC_APME       0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
+#define E1000_WUC_APME       0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
+#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
+#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
+#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
 
 /* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_IGNORE_TCO      0x00008000 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
-#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+#define E1000_WUFC_LNKC 0x00000001      /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG  0x00000002      /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX   0x00000004      /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC   0x00000008      /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC   0x00000010      /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP  0x00000020      /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4 0x00000040      /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6 0x00000080      /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_IGNORE_TCO      0x00008000   /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0 0x00010000      /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1 0x00020000      /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2 0x00040000      /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3 0x00080000      /* Flexible Filter 3 Enable */
+#define E1000_WUFC_ALL_FILTERS 0x000F00FF       /* Mask for all wakeup filters */
+#define E1000_WUFC_FLX_OFFSET 16        /* Offset to the Flexible Filters bits */
+#define E1000_WUFC_FLX_FILTERS 0x000F0000       /* Mask for the 4 flexible filters */
 
 /* Wake Up Status */
-#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
-#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
-#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
-#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
-#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
-#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
-#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
-#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
-#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
-#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
-#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
-#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
-#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+#define E1000_WUS_LNKC 0x00000001       /* Link Status Changed */
+#define E1000_WUS_MAG  0x00000002       /* Magic Packet Received */
+#define E1000_WUS_EX   0x00000004       /* Directed Exact Received */
+#define E1000_WUS_MC   0x00000008       /* Directed Multicast Received */
+#define E1000_WUS_BC   0x00000010       /* Broadcast Received */
+#define E1000_WUS_ARP  0x00000020       /* ARP Request Packet Received */
+#define E1000_WUS_IPV4 0x00000040       /* Directed IPv4 Packet Wakeup Received */
+#define E1000_WUS_IPV6 0x00000080       /* Directed IPv6 Packet Wakeup Received */
+#define E1000_WUS_FLX0 0x00010000       /* Flexible Filter 0 Match */
+#define E1000_WUS_FLX1 0x00020000       /* Flexible Filter 1 Match */
+#define E1000_WUS_FLX2 0x00040000       /* Flexible Filter 2 Match */
+#define E1000_WUS_FLX3 0x00080000       /* Flexible Filter 3 Match */
+#define E1000_WUS_FLX_FILTERS 0x000F0000        /* Mask for the 4 flexible filters */
 
 /* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery
-                                             * Filtering */
-#define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
-#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
-#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000 /* Enable MAC address
-                                                    * filtering */
-#define E1000_MANC_EN_MNG2HOST   0x00200000 /* Enable MNG packets to host
-                                             * memory */
-#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000 /* Enable IP address
-                                                    * filtering */
-#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
-#define E1000_MANC_BR_EN         0x01000000 /* Enable broadcast filtering */
-#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
+#define E1000_MANC_SMBUS_EN      0x00000001     /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN        0x00000002     /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE    0x00000004     /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN       0x00000100     /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN       0x00000200     /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN       0x00000400     /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN       0x00000800     /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN       0x00001000     /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN        0x00002000     /* Enable ARP Request Filtering */
+#define E1000_MANC_NEIGHBOR_EN   0x00004000     /* Enable Neighbor Discovery
+                                                 * Filtering */
+#define E1000_MANC_ARP_RES_EN    0x00008000     /* Enable ARP response Filtering */
+#define E1000_MANC_TCO_RESET     0x00010000     /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN    0x00020000     /* Receive TCO Packets Enabled */
+#define E1000_MANC_REPORT_STATUS 0x00040000     /* Status Reporting Enabled */
+#define E1000_MANC_RCV_ALL       0x00080000     /* Receive All Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000      /* Block phy resets */
+#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000      /* Enable MAC address
+                                                         * filtering */
+#define E1000_MANC_EN_MNG2HOST   0x00200000     /* Enable MNG packets to host
+                                                 * memory */
+#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000      /* Enable IP address
+                                                         * filtering */
+#define E1000_MANC_EN_XSUM_FILTER   0x00800000  /* Enable checksum filtering */
+#define E1000_MANC_BR_EN         0x01000000     /* Enable broadcast filtering */
+#define E1000_MANC_SMB_REQ       0x01000000     /* SMBus Request */
+#define E1000_MANC_SMB_GNT       0x02000000     /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN    0x04000000     /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN   0x08000000     /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT  0x10000000     /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT   0x20000000     /* SMBus Clock Out */
+
+#define E1000_MANC_SMB_DATA_OUT_SHIFT  28       /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT   29       /* SMBus Clock Out Shift */
 
 /* SW Semaphore Register */
-#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+#define E1000_SWSM_SMBI         0x00000001      /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI      0x00000002      /* FW Semaphore bit */
+#define E1000_SWSM_WMNG         0x00000004      /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD     0x00000008      /* Driver Loaded Bit */
 
 /* FW Semaphore Register */
-#define E1000_FWSM_MODE_MASK    0x0000000E /* FW mode */
+#define E1000_FWSM_MODE_MASK    0x0000000E      /* FW mode */
 #define E1000_FWSM_MODE_SHIFT            1
-#define E1000_FWSM_FW_VALID     0x00008000 /* FW established a valid mode */
+#define E1000_FWSM_FW_VALID     0x00008000      /* FW established a valid mode */
 
-#define E1000_FWSM_RSPCIPHY        0x00000040 /* Reset PHY on PCI reset */
-#define E1000_FWSM_DISSW           0x10000000 /* FW disable SW Write Access */
-#define E1000_FWSM_SKUSEL_MASK     0x60000000 /* LAN SKU select */
+#define E1000_FWSM_RSPCIPHY        0x00000040   /* Reset PHY on PCI reset */
+#define E1000_FWSM_DISSW           0x10000000   /* FW disable SW Write Access */
+#define E1000_FWSM_SKUSEL_MASK     0x60000000   /* LAN SKU select */
 #define E1000_FWSM_SKUEL_SHIFT     29
-#define E1000_FWSM_SKUSEL_EMB      0x0 /* Embedded SKU */
-#define E1000_FWSM_SKUSEL_CONS     0x1 /* Consumer SKU */
-#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
-#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
+#define E1000_FWSM_SKUSEL_EMB      0x0  /* Embedded SKU */
+#define E1000_FWSM_SKUSEL_CONS     0x1  /* Consumer SKU */
+#define E1000_FWSM_SKUSEL_PERF_100 0x2  /* Perf & Corp 10/100 SKU */
+#define E1000_FWSM_SKUSEL_PERF_GBE 0x3  /* Perf & Copr GbE SKU */
 
 /* FFLT Debug Register */
-#define E1000_FFLT_DBG_INVC     0x00100000 /* Invalid /C/ code handling */
+#define E1000_FFLT_DBG_INVC     0x00100000      /* Invalid /C/ code handling */
 
 typedef enum {
-    e1000_mng_mode_none     = 0,
-    e1000_mng_mode_asf,
-    e1000_mng_mode_pt,
-    e1000_mng_mode_ipmi,
-    e1000_mng_mode_host_interface_only
+        e1000_mng_mode_none = 0,
+        e1000_mng_mode_asf,
+        e1000_mng_mode_pt,
+        e1000_mng_mode_ipmi,
+        e1000_mng_mode_host_interface_only
 } e1000_mng_mode;
 
-/* Host Inteface Control Register */
-#define E1000_HICR_EN           0x00000001  /* Enable Bit - RO */
-#define E1000_HICR_C            0x00000002  /* Driver sets this bit when done
-                                             * to put command in RAM */
-#define E1000_HICR_SV           0x00000004  /* Status Validity */
-#define E1000_HICR_FWR          0x00000080  /* FW reset. Set by the Host */
+/* Host Interface Control Register */
+#define E1000_HICR_EN           0x00000001      /* Enable Bit - RO */
+#define E1000_HICR_C            0x00000002      /* Driver sets this bit when done
+                                                 * to put command in RAM */
+#define E1000_HICR_SV           0x00000004      /* Status Validity */
+#define E1000_HICR_FWR          0x00000080      /* FW reset. Set by the Host */
 
 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
-#define E1000_HI_MAX_DATA_LENGTH         252 /* Host Interface data length */
-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Number of bytes in range */
-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH  448 /* Number of dwords in range */
-#define E1000_HI_COMMAND_TIMEOUT         500 /* Time in ms to process HI command */
+#define E1000_HI_MAX_DATA_LENGTH         252    /* Host Interface data length */
+#define E1000_HI_MAX_BLOCK_BYTE_LENGTH  1792    /* Number of bytes in range */
+#define E1000_HI_MAX_BLOCK_DWORD_LENGTH  448    /* Number of dwords in range */
+#define E1000_HI_COMMAND_TIMEOUT         500    /* Time in ms to process HI command */
 
 struct e1000_host_command_header {
-    u8 command_id;
-    u8 command_length;
-    u8 command_options;   /* I/F bits for command, status for return */
-    u8 checksum;
+        u8 command_id;
+        u8 command_length;
+        u8 command_options;     /* I/F bits for command, status for return */
+        u8 checksum;
 };
 struct e1000_host_command_info {
-    struct e1000_host_command_header command_header;  /* Command Head/Command Result Head has 4 bytes */
-    u8 command_data[E1000_HI_MAX_DATA_LENGTH];   /* Command data can length 0..252 */
+        struct e1000_host_command_header command_header;        /* Command Head/Command Result Head has 4 bytes */
+        u8 command_data[E1000_HI_MAX_DATA_LENGTH];      /* Command data can length 0..252 */
 };
 
 /* Host SMB register #0 */
-#define E1000_HSMC0R_CLKIN      0x00000001  /* SMB Clock in */
-#define E1000_HSMC0R_DATAIN     0x00000002  /* SMB Data in */
-#define E1000_HSMC0R_DATAOUT    0x00000004  /* SMB Data out */
-#define E1000_HSMC0R_CLKOUT     0x00000008  /* SMB Clock out */
+#define E1000_HSMC0R_CLKIN      0x00000001      /* SMB Clock in */
+#define E1000_HSMC0R_DATAIN     0x00000002      /* SMB Data in */
+#define E1000_HSMC0R_DATAOUT    0x00000004      /* SMB Data out */
+#define E1000_HSMC0R_CLKOUT     0x00000008      /* SMB Clock out */
 
 /* Host SMB register #1 */
 #define E1000_HSMC1R_CLKIN      E1000_HSMC0R_CLKIN
@@ -2185,10 +2096,10 @@ struct e1000_host_command_info {
 #define E1000_HSMC1R_CLKOUT     E1000_HSMC0R_CLKOUT
 
 /* FW Status Register */
-#define E1000_FWSTS_FWS_MASK    0x000000FF  /* FW Status */
+#define E1000_FWSTS_FWS_MASK    0x000000FF      /* FW Status */
 
 /* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
 
 #define E1000_MDALIGN          4096
 
@@ -2242,24 +2153,24 @@ struct e1000_host_command_info {
 #define PCI_EX_LINK_WIDTH_SHIFT      4
 
 /* EEPROM Commands - Microwire */
-#define EEPROM_READ_OPCODE_MICROWIRE  0x6  /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5  /* EEPROM write opcode */
-#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7  /* EEPROM erase opcode */
-#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13 /* EEPROM erase/write enable */
-#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10 /* EEPROM erast/write disable */
+#define EEPROM_READ_OPCODE_MICROWIRE  0x6       /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5       /* EEPROM write opcode */
+#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7       /* EEPROM erase opcode */
+#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13      /* EEPROM erase/write enable */
+#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10      /* EEPROM erase/write disable */
 
 /* EEPROM Commands - SPI */
-#define EEPROM_MAX_RETRY_SPI        5000 /* Max wait of 5ms, for RDY signal */
-#define EEPROM_READ_OPCODE_SPI      0x03  /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_SPI     0x02  /* EEPROM write opcode */
-#define EEPROM_A8_OPCODE_SPI        0x08  /* opcode bit-3 = address bit-8 */
-#define EEPROM_WREN_OPCODE_SPI      0x06  /* EEPROM set Write Enable latch */
-#define EEPROM_WRDI_OPCODE_SPI      0x04  /* EEPROM reset Write Enable latch */
-#define EEPROM_RDSR_OPCODE_SPI      0x05  /* EEPROM read Status register */
-#define EEPROM_WRSR_OPCODE_SPI      0x01  /* EEPROM write Status register */
-#define EEPROM_ERASE4K_OPCODE_SPI   0x20  /* EEPROM ERASE 4KB */
-#define EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
-#define EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
+#define EEPROM_MAX_RETRY_SPI        5000        /* Max wait of 5ms, for RDY signal */
+#define EEPROM_READ_OPCODE_SPI      0x03        /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_SPI     0x02        /* EEPROM write opcode */
+#define EEPROM_A8_OPCODE_SPI        0x08        /* opcode bit-3 = address bit-8 */
+#define EEPROM_WREN_OPCODE_SPI      0x06        /* EEPROM set Write Enable latch */
+#define EEPROM_WRDI_OPCODE_SPI      0x04        /* EEPROM reset Write Enable latch */
+#define EEPROM_RDSR_OPCODE_SPI      0x05        /* EEPROM read Status register */
+#define EEPROM_WRSR_OPCODE_SPI      0x01        /* EEPROM write Status register */
+#define EEPROM_ERASE4K_OPCODE_SPI   0x20        /* EEPROM ERASE 4KB */
+#define EEPROM_ERASE64K_OPCODE_SPI  0xD8        /* EEPROM ERASE 64KB */
+#define EEPROM_ERASE256_OPCODE_SPI  0xDB        /* EEPROM ERASE 256B */
 
 /* EEPROM Size definitions */
 #define EEPROM_WORD_SIZE_SHIFT  6
@@ -2270,7 +2181,7 @@ struct e1000_host_command_info {
 #define EEPROM_COMPAT                 0x0003
 #define EEPROM_ID_LED_SETTINGS        0x0004
 #define EEPROM_VERSION                0x0005
-#define EEPROM_SERDES_AMPLITUDE       0x0006 /* For SERDES output amplitude adjustment. */
+#define EEPROM_SERDES_AMPLITUDE       0x0006    /* For SERDES output amplitude adjustment. */
 #define EEPROM_PHY_CLASS_WORD         0x0007
 #define EEPROM_INIT_CONTROL1_REG      0x000A
 #define EEPROM_INIT_CONTROL2_REG      0x000F
@@ -2283,22 +2194,16 @@ struct e1000_host_command_info {
 #define EEPROM_FLASH_VERSION          0x0032
 #define EEPROM_CHECKSUM_REG           0x003F
 
-#define E1000_EEPROM_CFG_DONE         0x00040000   /* MNG config cycle done */
-#define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000   /* ...for second port */
+#define E1000_EEPROM_CFG_DONE         0x00040000        /* MNG config cycle done */
+#define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000        /* ...for second port */
 
 /* Word definitions for ID LED Settings */
 #define ID_LED_RESERVED_0000 0x0000
 #define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_RESERVED_82573  0xF746
-#define ID_LED_DEFAULT_82573   0x1811
 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
                               (ID_LED_OFF1_OFF2 << 8) | \
                               (ID_LED_DEF1_DEF2 << 4) | \
                               (ID_LED_DEF1_DEF2))
-#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
-                                 (ID_LED_DEF1_OFF2 <<  8) | \
-                                 (ID_LED_DEF1_ON2  <<  4) | \
-                                 (ID_LED_DEF1_DEF2))
 #define ID_LED_DEF1_DEF2     0x1
 #define ID_LED_DEF1_ON2      0x2
 #define ID_LED_DEF1_OFF2     0x3
@@ -2313,7 +2218,6 @@ struct e1000_host_command_info {
 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 #define IGP_LED3_MODE           0x07000000
 
-
 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
 #define EEPROM_SERDES_AMPLITUDE_MASK  0x000F
 
@@ -2384,11 +2288,8 @@ struct e1000_host_command_info {
 
 #define DEFAULT_82542_TIPG_IPGR2 10
 #define DEFAULT_82543_TIPG_IPGR2 6
-#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
 #define E1000_TIPG_IPGR2_SHIFT  20
 
-#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
-#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000   0x00000008
 #define E1000_TXDMAC_DPP 0x00000001
 
 /* Adaptive IFS defines */
@@ -2421,9 +2322,9 @@ struct e1000_host_command_info {
 #define E1000_EXTCNF_CTRL_SWFLAG            0x00000020
 
 /* PBA constants */
-#define E1000_PBA_8K 0x0008    /* 8KB, default Rx allocation */
-#define E1000_PBA_12K 0x000C    /* 12KB, default Rx allocation */
-#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
+#define E1000_PBA_8K 0x0008     /* 8KB, default Rx allocation */
+#define E1000_PBA_12K 0x000C    /* 12KB, default Rx allocation */
+#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
 #define E1000_PBA_20K 0x0014
 #define E1000_PBA_22K 0x0016
 #define E1000_PBA_24K 0x0018
@@ -2432,7 +2333,7 @@ struct e1000_host_command_info {
 #define E1000_PBA_34K 0x0022
 #define E1000_PBA_38K 0x0026
 #define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
+#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
 
 #define E1000_PBS_16K E1000_PBA_16K
 
@@ -2442,9 +2343,9 @@ struct e1000_host_command_info {
 #define FLOW_CONTROL_TYPE         0x8808
 
 /* The historical defaults for the flow control values are given below. */
-#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
-#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
-#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
+#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
+#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
+#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
 
 /* PCIX Config space */
 #define PCIX_COMMAND_REGISTER    0xE6
@@ -2458,7 +2359,6 @@ struct e1000_host_command_info {
 #define PCIX_STATUS_HI_MMRBC_4K      0x3
 #define PCIX_STATUS_HI_MMRBC_2K      0x2
 
-
 /* Number of bits required to shift right the "pause" bits from the
  * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
  */
@@ -2479,14 +2379,11 @@ struct e1000_host_command_info {
  */
 #define ILOS_SHIFT  3
 
-
 #define RECEIVE_BUFFER_ALIGN_SIZE  (256)
 
 /* Number of milliseconds we wait for auto-negotiation to complete */
 #define LINK_UP_TIMEOUT             500
 
-/* Number of 100 microseconds we wait for PCI Express master disable */
-#define MASTER_DISABLE_TIMEOUT      800
 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
 #define AUTO_READ_DONE_TIMEOUT      10
 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
@@ -2534,7 +2431,6 @@ struct e1000_host_command_info {
           (((length) > (adapter)->min_frame_size) && \
            ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
 
-
 /* Structures, enums, and macros for the PHY */
 
 /* Bit definitions for the Management Data IO (MDIO) and Management Data
@@ -2551,49 +2447,49 @@ struct e1000_host_command_info {
 
 /* PHY 1000 MII Register/Bit Definitions */
 /* PHY Registers defined by IEEE */
-#define PHY_CTRL         0x00 /* Control Register */
-#define PHY_STATUS       0x01 /* Status Regiser */
-#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
-
-#define MAX_PHY_REG_ADDRESS        0x1F  /* 5 bit address bus (0-0x1F) */
-#define MAX_PHY_MULTI_PAGE_REG     0xF   /* Registers equal on all pages */
+#define PHY_CTRL         0x00   /* Control Register */
+#define PHY_STATUS       0x01   /* Status Register */
+#define PHY_ID1          0x02   /* Phy Id Reg (word 1) */
+#define PHY_ID2          0x03   /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV  0x04   /* Autoneg Advertisement */
+#define PHY_LP_ABILITY   0x05   /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP  0x06   /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX 0x07   /* Next Page TX */
+#define PHY_LP_NEXT_PAGE 0x08   /* Link Partner Next Page */
+#define PHY_1000T_CTRL   0x09   /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS 0x0A   /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS   0x0F   /* Extended Status Reg */
+
+#define MAX_PHY_REG_ADDRESS        0x1F /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG     0xF  /* Registers equal on all pages */
 
 /* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
-
-#define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
-#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
-#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
-#define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
-#define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
+#define M88E1000_PHY_SPEC_CTRL     0x10 /* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */
+#define M88E1000_INT_ENABLE        0x12 /* Interrupt Enable Register */
+#define M88E1000_INT_STATUS        0x13 /* Interrupt Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
+#define M88E1000_RX_ERR_CNTR       0x15 /* Receive Error Counter */
+
+#define M88E1000_PHY_EXT_CTRL      0x1A /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8  0x100        /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11 0x800        /* improved BER performance */
 
 #define IGP01E1000_IEEE_REGS_PAGE  0x0000
 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
 #define IGP01E1000_IEEE_FORCE_GIGA      0x0140
 
 /* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
-#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
-#define IGP01E1000_PHY_PORT_CTRL   0x12 /* PHY Specific Control Register */
-#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
-#define IGP01E1000_GMII_FIFO       0x14 /* GMII FIFO Register */
-#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
+#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
+#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
+#define IGP01E1000_PHY_PORT_CTRL   0x12 /* PHY Specific Control Register */
+#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
+#define IGP01E1000_GMII_FIFO       0x14 /* GMII FIFO Register */
+#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15     /* PHY Channel Quality Register */
 #define IGP02E1000_PHY_POWER_MGMT      0x19
-#define IGP01E1000_PHY_PAGE_SELECT     0x1F /* PHY Page Select Core Register */
+#define IGP01E1000_PHY_PAGE_SELECT     0x1F     /* PHY Page Select Core Register */
 
 /* IGP01E1000 AGC Registers - stores the cable length values*/
 #define IGP01E1000_PHY_AGC_A        0x1172
@@ -2636,192 +2532,119 @@ struct e1000_host_command_info {
 
 #define IGP01E1000_ANALOG_REGS_PAGE  0x20C0
 
-/* Bits...
- * 15-5: page
- * 4-0: register offset
- */
-#define GG82563_PAGE_SHIFT        5
-#define GG82563_REG(page, reg)    \
-        (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
-#define GG82563_MIN_ALT_REG       30
-
-/* GG82563 Specific Registers */
-#define GG82563_PHY_SPEC_CTRL           \
-        GG82563_REG(0, 16) /* PHY Specific Control */
-#define GG82563_PHY_SPEC_STATUS         \
-        GG82563_REG(0, 17) /* PHY Specific Status */
-#define GG82563_PHY_INT_ENABLE          \
-        GG82563_REG(0, 18) /* Interrupt Enable */
-#define GG82563_PHY_SPEC_STATUS_2       \
-        GG82563_REG(0, 19) /* PHY Specific Status 2 */
-#define GG82563_PHY_RX_ERR_CNTR         \
-        GG82563_REG(0, 21) /* Receive Error Counter */
-#define GG82563_PHY_PAGE_SELECT         \
-        GG82563_REG(0, 22) /* Page Select */
-#define GG82563_PHY_SPEC_CTRL_2         \
-        GG82563_REG(0, 26) /* PHY Specific Control 2 */
-#define GG82563_PHY_PAGE_SELECT_ALT     \
-        GG82563_REG(0, 29) /* Alternate Page Select */
-#define GG82563_PHY_TEST_CLK_CTRL       \
-        GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
-
-#define GG82563_PHY_MAC_SPEC_CTRL       \
-        GG82563_REG(2, 21) /* MAC Specific Control Register */
-#define GG82563_PHY_MAC_SPEC_CTRL_2     \
-        GG82563_REG(2, 26) /* MAC Specific Control 2 */
-
-#define GG82563_PHY_DSP_DISTANCE    \
-        GG82563_REG(5, 26) /* DSP Distance */
-
-/* Page 193 - Port Control Registers */
-#define GG82563_PHY_KMRN_MODE_CTRL   \
-        GG82563_REG(193, 16) /* Kumeran Mode Control */
-#define GG82563_PHY_PORT_RESET          \
-        GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID         \
-        GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID           \
-        GG82563_REG(193, 19) /* Device ID */
-#define GG82563_PHY_PWR_MGMT_CTRL       \
-        GG82563_REG(193, 20) /* Power Management Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL     \
-        GG82563_REG(193, 25) /* Rate Adaptation Control */
-
-/* Page 194 - KMRN Registers */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
-        GG82563_REG(194, 16) /* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_CTRL           \
-        GG82563_REG(194, 17) /* Control */
-#define GG82563_PHY_INBAND_CTRL         \
-        GG82563_REG(194, 18) /* Inband Control */
-#define GG82563_PHY_KMRN_DIAGNOSTIC     \
-        GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS        \
-        GG82563_REG(194, 20) /* Acknowledge Timeouts */
-#define GG82563_PHY_ADV_ABILITY         \
-        GG82563_REG(194, 21) /* Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
-        GG82563_REG(194, 23) /* Link Partner Advertised Ability */
-#define GG82563_PHY_ADV_NEXT_PAGE       \
-        GG82563_REG(194, 24) /* Advertised Next Page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
-        GG82563_REG(194, 25) /* Link Partner Advertised Next page */
-#define GG82563_PHY_KMRN_MISC           \
-        GG82563_REG(194, 26) /* Misc. */
-
 /* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800  /* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
+#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
+#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN       0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 
 /* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
 
 /* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
-#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
-#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
+#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
+#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
 
 /* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
+#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
+#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
+#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
+#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
 
 /* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
+#define NWAY_ER_LP_NWAY_CAPS      0x0001        /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD          0x0002        /* LP is 10T   Half Duplex Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS    0x0004        /* LP is 10T   Full Duplex Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008        /* LP is 100TX Half Duplex Capable */
+#define NWAY_ER_PAR_DETECT_FAULT  0x0010        /* LP is 100TX Full Duplex Capable */
 
 /* Next Page TX Register */
-#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
-                                    * of different NP
-                                    */
-#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
-                                    * 0 = cannot comply with msg
-                                    */
-#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
-#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow
-                                    * 0 = sending last NP
-                                    */
+#define NPTX_MSG_CODE_FIELD 0x0001      /* NP msg code or unformatted data */
+#define NPTX_TOGGLE         0x0800      /* Toggles between exchanges
+                                         * of different NP
+                                         */
+#define NPTX_ACKNOWLDGE2    0x1000      /* 1 = will comply with msg
+                                         * 0 = cannot comply with msg
+                                         */
+#define NPTX_MSG_PAGE       0x2000      /* formatted(1)/unformatted(0) pg */
+#define NPTX_NEXT_PAGE      0x8000      /* 1 = addition NP will follow
+                                         * 0 = sending last NP
+                                         */
 
 /* Link Partner Next Page Register */
-#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
-                                       * of different NP
-                                       */
-#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
-                                       * 0 = cannot comply with msg
-                                       */
-#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
-#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
-#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
-                                        * 0 = sending last NP
-                                        */
+#define LP_RNPR_MSG_CODE_FIELD 0x0001   /* NP msg code or unformatted data */
+#define LP_RNPR_TOGGLE         0x0800   /* Toggles between exchanges
+                                         * of different NP
+                                         */
+#define LP_RNPR_ACKNOWLDGE2    0x1000   /* 1 = will comply with msg
+                                         * 0 = cannot comply with msg
+                                         */
+#define LP_RNPR_MSG_PAGE       0x2000   /* formatted(1)/unformatted(0) pg */
+#define LP_RNPR_ACKNOWLDGE     0x4000   /* 1 = ACK / 0 = NO ACK */
+#define LP_RNPR_NEXT_PAGE      0x8000   /* 1 = addition NP will follow
+                                         * 0 = sending last NP
+                                         */
 
 /* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
-                                        /* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
-                                        /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
-                                        /* 0=Automatic Master/Slave config */
-#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
+#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
+                                        /* 0=DTE device */
+#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
+                                        /* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
+                                        /* 0=Automatic Master/Slave config */
+#define CR_1000T_TEST_MODE_NORMAL 0x0000        /* Normal Operation */
+#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
 
 /* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+#define SR_1000T_IDLE_ERROR_CNT   0x00FF        /* Num idle errors since last read */
+#define SR_1000T_ASYM_PAUSE_DIR   0x0100        /* LP asymmetric pause direction bit */
+#define SR_1000T_LP_HD_CAPS       0x0400        /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS       0x0800        /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS 0x1000        /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS  0x2000        /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES    0x4000        /* 1=Local TX is Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT  0x8000        /* Master/Slave config fault */
 #define SR_1000T_REMOTE_RX_STATUS_SHIFT          12
 #define SR_1000T_LOCAL_RX_STATUS_SHIFT           13
 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT    5
@@ -2829,64 +2652,64 @@ struct e1000_host_command_info {
 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100           100
 
 /* Extended Status Register */
-#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
-#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
-#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
-#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
+#define IEEE_ESR_1000T_HD_CAPS 0x1000   /* 1000T HD capable */
+#define IEEE_ESR_1000T_FD_CAPS 0x2000   /* 1000T FD capable */
+#define IEEE_ESR_1000X_HD_CAPS 0x4000   /* 1000X HD capable */
+#define IEEE_ESR_1000X_FD_CAPS 0x8000   /* 1000X FD capable */
 
-#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
-#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
+#define PHY_TX_POLARITY_MASK   0x0100   /* register 10h bit 8 (polarity bit) */
+#define PHY_TX_NORMAL_POLARITY 0        /* register 10h bit 8 (normal polarity) */
 
-#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
-                                      /* (0=enable, 1=disable) */
+#define AUTO_POLARITY_DISABLE  0x0010   /* register 11h bit 4 */
+                                      /* (0=enable, 1=disable) */
 
 /* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low,
-                                                * 0=CLK125 toggling
-                                                */
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
-                                               /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
-                                                *  100BASE-TX/10BASE-T:
-                                                *  MDI Mode
-                                                */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled
-                                                * all speeds.
-                                                */
+#define M88E1000_PSCR_JABBER_DISABLE    0x0001  /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002  /* 1=Polarity Reversal enabled */
+#define M88E1000_PSCR_SQE_TEST          0x0004  /* 1=SQE Test enabled */
+#define M88E1000_PSCR_CLK125_DISABLE    0x0010  /* 1=CLK125 low,
+                                                 * 0=CLK125 toggling
+                                                 */
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000   /* MDI Crossover Mode bits 6:5 */
+                                               /* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020   /* Manual MDIX configuration */
+#define M88E1000_PSCR_AUTO_X_1000T     0x0040   /* 1000BASE-T: Auto crossover,
+                                                 *  100BASE-TX/10BASE-T:
+                                                 *  MDI Mode
+                                                 */
+#define M88E1000_PSCR_AUTO_X_MODE      0x0060   /* Auto crossover enabled
+                                                 * all speeds.
+                                                 */
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
-                                        /* 1=Enable Extended 10BASE-T distance
-                                         * (Lower 10BASE-T RX Threshold)
-                                         * 0=Normal 10BASE-T RX Threshold */
+                                        /* 1=Enable Extended 10BASE-T distance
+                                         * (Lower 10BASE-T RX Threshold)
+                                         * 0=Normal 10BASE-T RX Threshold */
 #define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-                                        /* 1=5-Bit interface in 100BASE-TX
-                                         * 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
+                                        /* 1=5-Bit interface in 100BASE-TX
+                                         * 0=MII interface in 100BASE-TX */
+#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200       /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400       /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800       /* 1=Assert CRS on Transmit */
 
 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
 
 /* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
-#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
-                                            * 3=110-140M;4=>140M */
-#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
+                                                 * 3=110-140M;4=>140M */
+#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
+#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 
 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
 #define M88E1000_PSSR_DOWNSHIFT_SHIFT    5
@@ -2894,12 +2717,12 @@ struct e1000_host_command_info {
 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 
 /* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
-                                              * Will assert lost lock and bring
-                                              * link down if idle not seen
-                                              * within 1ms in 1000BASE-T
-                                              */
+#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000    /* 1=Fiber loopback */
+#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000    /* 1=Lost lock detect enabled.
+                                                 * Will assert lost lock and bring
+                                                 * link down if idle not seen
+                                                 * within 1ms in 1000BASE-T
+                                                 */
 /* Number of times we will attempt to autonegotiate before downshifting if we
  * are the master */
 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
@@ -2914,9 +2737,9 @@ struct e1000_host_command_info {
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_2_5     0x0060    /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25      0x0070    /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0       0x0000    /* NO  TX_CLK */
 
 /* M88EC018 Rev 2 specific DownShift settings */
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
@@ -2938,18 +2761,18 @@ struct e1000_host_command_info {
 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT      0x2000
 
 /* IGP01E1000 Specific Port Status Register - R/O */
-#define IGP01E1000_PSSR_AUTONEG_FAILED         0x0001 /* RO LH SC */
+#define IGP01E1000_PSSR_AUTONEG_FAILED         0x0001   /* RO LH SC */
 #define IGP01E1000_PSSR_POLARITY_REVERSED      0x0002
 #define IGP01E1000_PSSR_CABLE_LENGTH           0x007C
 #define IGP01E1000_PSSR_FULL_DUPLEX            0x0200
 #define IGP01E1000_PSSR_LINK_UP                0x0400
 #define IGP01E1000_PSSR_MDIX                   0x0800
-#define IGP01E1000_PSSR_SPEED_MASK             0xC000 /* speed bits mask */
+#define IGP01E1000_PSSR_SPEED_MASK             0xC000   /* speed bits mask */
 #define IGP01E1000_PSSR_SPEED_10MBPS           0x4000
 #define IGP01E1000_PSSR_SPEED_100MBPS          0x8000
 #define IGP01E1000_PSSR_SPEED_1000MBPS         0xC000
-#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT     0x0002 /* shift right 2 */
-#define IGP01E1000_PSSR_MDIX_SHIFT             0x000B /* shift right 11 */
+#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT     0x0002   /* shift right 2 */
+#define IGP01E1000_PSSR_MDIX_SHIFT             0x000B   /* shift right 11 */
 
 /* IGP01E1000 Specific Port Control Register - R/W */
 #define IGP01E1000_PSCR_TP_LOOPBACK            0x0010
@@ -2957,16 +2780,16 @@ struct e1000_host_command_info {
 #define IGP01E1000_PSCR_TEN_CRS_SELECT         0x0400
 #define IGP01E1000_PSCR_FLIP_CHIP              0x0800
 #define IGP01E1000_PSCR_AUTO_MDIX              0x1000
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX         0x2000 /* 0-MDI, 1-MDIX */
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX         0x2000   /* 0-MDI, 1-MDIX */
 
 /* IGP01E1000 Specific Port Link Health Register */
 #define IGP01E1000_PLHR_SS_DOWNGRADE           0x8000
 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR    0x4000
 #define IGP01E1000_PLHR_MASTER_FAULT           0x2000
 #define IGP01E1000_PLHR_MASTER_RESOLUTION      0x1000
-#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK       0x0800 /* LH */
-#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW   0x0400 /* LH */
-#define IGP01E1000_PLHR_DATA_ERR_1             0x0200 /* LH */
+#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK       0x0800   /* LH */
+#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW   0x0400   /* LH */
+#define IGP01E1000_PLHR_DATA_ERR_1             0x0200   /* LH */
 #define IGP01E1000_PLHR_DATA_ERR_0             0x0100
 #define IGP01E1000_PLHR_AUTONEG_FAULT          0x0040
 #define IGP01E1000_PLHR_AUTONEG_ACTIVE         0x0010
@@ -2981,9 +2804,9 @@ struct e1000_host_command_info {
 #define IGP01E1000_MSE_CHANNEL_B        0x0F00
 #define IGP01E1000_MSE_CHANNEL_A        0xF000
 
-#define IGP02E1000_PM_SPD                         0x0001  /* Smart Power Down */
-#define IGP02E1000_PM_D3_LPLU                     0x0004  /* Enable LPLU in non-D0a modes */
-#define IGP02E1000_PM_D0_LPLU                     0x0002  /* Enable LPLU in D0a mode */
+#define IGP02E1000_PM_SPD                         0x0001        /* Smart Power Down */
+#define IGP02E1000_PM_D3_LPLU                     0x0004        /* Enable LPLU in non-D0a modes */
+#define IGP02E1000_PM_D0_LPLU                     0x0002        /* Enable LPLU in D0a mode */
 
 /* IGP01E1000 DSP reset macros */
 #define DSP_RESET_ENABLE     0x0
@@ -2992,8 +2815,8 @@ struct e1000_host_command_info {
 
 /* IGP01E1000 & IGP02E1000 AGC Registers */
 
-#define IGP01E1000_AGC_LENGTH_SHIFT 7         /* Coarse - 13:11, Fine - 10:7 */
-#define IGP02E1000_AGC_LENGTH_SHIFT 9         /* Coarse - 15:13, Fine - 12:9 */
+#define IGP01E1000_AGC_LENGTH_SHIFT 7   /* Coarse - 13:11, Fine - 10:7 */
+#define IGP02E1000_AGC_LENGTH_SHIFT 9   /* Coarse - 15:13, Fine - 12:9 */
 
 /* IGP02E1000 AGC Register Length 9-bit mask */
 #define IGP02E1000_AGC_LENGTH_MASK  0x7F
@@ -3011,9 +2834,9 @@ struct e1000_host_command_info {
 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 
 /* IGP01E1000 GMII FIFO Register */
-#define IGP01E1000_GMII_FLEX_SPD               0x10 /* Enable flexible speed
-                                                     * on Link-Up */
-#define IGP01E1000_GMII_SPD                    0x20 /* Enable SPD */
+#define IGP01E1000_GMII_FLEX_SPD               0x10     /* Enable flexible speed
+                                                         * on Link-Up */
+#define IGP01E1000_GMII_SPD                    0x20     /* Enable SPD */
 
 /* IGP01E1000 Analog Register */
 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS       0x20D1
@@ -3032,114 +2855,6 @@ struct e1000_host_command_info {
 #define IGP01E1000_ANALOG_FUSE_FINE_1               0x0080
 #define IGP01E1000_ANALOG_FUSE_FINE_10              0x0500
 
-/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
-#define GG82563_PSCR_DISABLE_JABBER             0x0001 /* 1=Disable Jabber */
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Polarity Reversal Disabled */
-#define GG82563_PSCR_POWER_DOWN                 0x0004 /* 1=Power Down */
-#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE  0x0008 /* 1=Transmitter Disabled */
-#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
-#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI configuration */
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX configuration */
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Automatic crossover */
-#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE   0x0080 /* 1=Enable Extended Distance */
-#define GG82563_PSCR_ENERGY_DETECT_MASK         0x0300
-#define GG82563_PSCR_ENERGY_DETECT_OFF          0x0000 /* 00,01=Off */
-#define GG82563_PSCR_ENERGY_DETECT_RX           0x0200 /* 10=Sense on Rx only (Energy Detect) */
-#define GG82563_PSCR_ENERGY_DETECT_RX_TM        0x0300 /* 11=Sense and Tx NLP */
-#define GG82563_PSCR_FORCE_LINK_GOOD            0x0400 /* 1=Force Link Good */
-#define GG82563_PSCR_DOWNSHIFT_ENABLE           0x0800 /* 1=Enable Downshift */
-#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK     0x7000
-#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT    12
-
-/* PHY Specific Status Register (Page 0, Register 17) */
-#define GG82563_PSSR_JABBER                0x0001 /* 1=Jabber */
-#define GG82563_PSSR_POLARITY              0x0002 /* 1=Polarity Reversed */
-#define GG82563_PSSR_LINK                  0x0008 /* 1=Link is Up */
-#define GG82563_PSSR_ENERGY_DETECT         0x0010 /* 1=Sleep, 0=Active */
-#define GG82563_PSSR_DOWNSHIFT             0x0020 /* 1=Downshift */
-#define GG82563_PSSR_CROSSOVER_STATUS      0x0040 /* 1=MDIX, 0=MDI */
-#define GG82563_PSSR_RX_PAUSE_ENABLED      0x0100 /* 1=Receive Pause Enabled */
-#define GG82563_PSSR_TX_PAUSE_ENABLED      0x0200 /* 1=Transmit Pause Enabled */
-#define GG82563_PSSR_LINK_UP               0x0400 /* 1=Link Up */
-#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
-#define GG82563_PSSR_PAGE_RECEIVED         0x1000 /* 1=Page Received */
-#define GG82563_PSSR_DUPLEX                0x2000 /* 1-Full-Duplex */
-#define GG82563_PSSR_SPEED_MASK            0xC000
-#define GG82563_PSSR_SPEED_10MBPS          0x0000 /* 00=10Mbps */
-#define GG82563_PSSR_SPEED_100MBPS         0x4000 /* 01=100Mbps */
-#define GG82563_PSSR_SPEED_1000MBPS        0x8000 /* 10=1000Mbps */
-
-/* PHY Specific Status Register 2 (Page 0, Register 19) */
-#define GG82563_PSSR2_JABBER                0x0001 /* 1=Jabber */
-#define GG82563_PSSR2_POLARITY_CHANGED      0x0002 /* 1=Polarity Changed */
-#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
-#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT   0x0020 /* 1=Downshift Detected */
-#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE  0x0040 /* 1=Crossover Changed */
-#define GG82563_PSSR2_FALSE_CARRIER         0x0100 /* 1=False Carrier */
-#define GG82563_PSSR2_SYMBOL_ERROR          0x0200 /* 1=Symbol Error */
-#define GG82563_PSSR2_LINK_STATUS_CHANGED   0x0400 /* 1=Link Status Changed */
-#define GG82563_PSSR2_AUTO_NEG_COMPLETED    0x0800 /* 1=Auto-Neg Completed */
-#define GG82563_PSSR2_PAGE_RECEIVED         0x1000 /* 1=Page Received */
-#define GG82563_PSSR2_DUPLEX_CHANGED        0x2000 /* 1=Duplex Changed */
-#define GG82563_PSSR2_SPEED_CHANGED         0x4000 /* 1=Speed Changed */
-#define GG82563_PSSR2_AUTO_NEG_ERROR        0x8000 /* 1=Auto-Neg Error */
-
-/* PHY Specific Control Register 2 (Page 0, Register 26) */
-#define GG82563_PSCR2_10BT_POLARITY_FORCE           0x0002 /* 1=Force Negative Polarity */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK       0x000C
-#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL     0x0000 /* 00,01=Normal Operation */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS      0x0008 /* 10=Select 112ns Sequence */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS       0x000C /* 11=Select 16ns Sequence */
-#define GG82563_PSCR2_REVERSE_AUTO_NEG              0x2000 /* 1=Reverse Auto-Negotiation */
-#define GG82563_PSCR2_1000BT_DISABLE                0x4000 /* 1=Disable 1000BASE-T */
-#define GG82563_PSCR2_TRANSMITER_TYPE_MASK          0x8000
-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B      0x0000 /* 0=Class B */
-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A      0x8000 /* 1=Class A */
-
-/* MAC Specific Control Register (Page 2, Register 21) */
-/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
-#define GG82563_MSCR_TX_CLK_MASK                    0x0007
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ           0x0004
-#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ           0x0005
-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ         0x0006
-#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ          0x0007
-
-#define GG82563_MSCR_ASSERT_CRS_ON_TX               0x0010 /* 1=Assert */
-
-/* DSP Distance Register (Page 5, Register 26) */
-#define GG82563_DSPD_CABLE_LENGTH               0x0007 /* 0 = <50M;
-                                                          1 = 50-80M;
-                                                          2 = 80-110M;
-                                                          3 = 110-140M;
-                                                          4 = >140M */
-
-/* Kumeran Mode Control Register (Page 193, Register 16) */
-#define GG82563_KMCR_PHY_LEDS_EN                    0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
-#define GG82563_KMCR_FORCE_LINK_UP                  0x0040 /* 1=Force Link Up */
-#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT         0x0080
-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK     0x0400
-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT          0x0400 /* 1=6.25MHz, 0=0.8MHz */
-#define GG82563_KMCR_PASS_FALSE_CARRIER             0x0800
-
-/* Power Management Control Register (Page 193, Register 20) */
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE         0x0001 /* 1=Enalbe SERDES Electrical Idle */
-#define GG82563_PMCR_DISABLE_PORT                   0x0002 /* 1=Disable Port */
-#define GG82563_PMCR_DISABLE_SERDES                 0x0004 /* 1=Disable SERDES */
-#define GG82563_PMCR_REVERSE_AUTO_NEG               0x0008 /* 1=Enable Reverse Auto-Negotiation */
-#define GG82563_PMCR_DISABLE_1000_NON_D0            0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
-#define GG82563_PMCR_DISABLE_1000                   0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
-#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A           0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
-#define GG82563_PMCR_FORCE_POWER_STATE              0x0080 /* 1=Force Power State */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK    0x0300
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR      0x0000 /* 00=Dr */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U     0x0100 /* 01=D0u */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A     0x0200 /* 10=D0a */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3      0x0300 /* 11=D3 */
-
-/* In-Band Control Register (Page 194, Register 18) */
-#define GG82563_ICR_DIS_PADDING                     0x0010 /* Disable Padding Use */
-
-
 /* Bit definitions for valid PHY IDs. */
 /* I = Integrated
  * E = External
@@ -3154,8 +2869,6 @@ struct e1000_host_command_info {
 #define M88E1011_I_REV_4   0x04
 #define M88E1111_I_PHY_ID  0x01410CC0
 #define L1LXT971A_PHY_ID   0x001378E0
-#define GG82563_E_PHY_ID   0x01410CA0
-
 
 /* Bits...
  * 15-5: page
@@ -3166,41 +2879,41 @@ struct e1000_host_command_info {
         (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
 
 #define IGP3_PHY_PORT_CTRL           \
-        PHY_REG(769, 17) /* Port General Configuration */
+        PHY_REG(769, 17)        /* Port General Configuration */
 #define IGP3_PHY_RATE_ADAPT_CTRL \
-        PHY_REG(769, 25) /* Rate Adapter Control Register */
+        PHY_REG(769, 25)        /* Rate Adapter Control Register */
 
 #define IGP3_KMRN_FIFO_CTRL_STATS \
-        PHY_REG(770, 16) /* KMRN FIFO's control/status register */
+        PHY_REG(770, 16)        /* KMRN FIFO's control/status register */
 #define IGP3_KMRN_POWER_MNG_CTRL \
-        PHY_REG(770, 17) /* KMRN Power Management Control Register */
+        PHY_REG(770, 17)        /* KMRN Power Management Control Register */
 #define IGP3_KMRN_INBAND_CTRL \
-        PHY_REG(770, 18) /* KMRN Inband Control Register */
+        PHY_REG(770, 18)        /* KMRN Inband Control Register */
 #define IGP3_KMRN_DIAG \
-        PHY_REG(770, 19) /* KMRN Diagnostic register */
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
+        PHY_REG(770, 19)        /* KMRN Diagnostic register */
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002     /* RX PCS is not synced */
 #define IGP3_KMRN_ACK_TIMEOUT \
-        PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
+        PHY_REG(770, 20)        /* KMRN Acknowledge Timeouts register */
 
 #define IGP3_VR_CTRL \
-        PHY_REG(776, 18) /* Voltage regulator control register */
-#define IGP3_VR_CTRL_MODE_SHUT       0x0200 /* Enter powerdown, shutdown VRs */
-#define IGP3_VR_CTRL_MODE_MASK       0x0300 /* Shutdown VR Mask */
+        PHY_REG(776, 18)        /* Voltage regulator control register */
+#define IGP3_VR_CTRL_MODE_SHUT       0x0200     /* Enter powerdown, shutdown VRs */
+#define IGP3_VR_CTRL_MODE_MASK       0x0300     /* Shutdown VR Mask */
 
 #define IGP3_CAPABILITY \
-        PHY_REG(776, 19) /* IGP3 Capability Register */
+        PHY_REG(776, 19)        /* IGP3 Capability Register */
 
 /* Capabilities for SKU Control  */
-#define IGP3_CAP_INITIATE_TEAM       0x0001 /* Able to initiate a team */
-#define IGP3_CAP_WFM                 0x0002 /* Support WoL and PXE */
-#define IGP3_CAP_ASF                 0x0004 /* Support ASF */
-#define IGP3_CAP_LPLU                0x0008 /* Support Low Power Link Up */
-#define IGP3_CAP_DC_AUTO_SPEED       0x0010 /* Support AC/DC Auto Link Speed */
-#define IGP3_CAP_SPD                 0x0020 /* Support Smart Power Down */
-#define IGP3_CAP_MULT_QUEUE          0x0040 /* Support 2 tx & 2 rx queues */
-#define IGP3_CAP_RSS                 0x0080 /* Support RSS */
-#define IGP3_CAP_8021PQ              0x0100 /* Support 802.1Q & 802.1p */
-#define IGP3_CAP_AMT_CB              0x0200 /* Support active manageability and circuit breaker */
+#define IGP3_CAP_INITIATE_TEAM       0x0001     /* Able to initiate a team */
+#define IGP3_CAP_WFM                 0x0002     /* Support WoL and PXE */
+#define IGP3_CAP_ASF                 0x0004     /* Support ASF */
+#define IGP3_CAP_LPLU                0x0008     /* Support Low Power Link Up */
+#define IGP3_CAP_DC_AUTO_SPEED       0x0010     /* Support AC/DC Auto Link Speed */
+#define IGP3_CAP_SPD                 0x0020     /* Support Smart Power Down */
+#define IGP3_CAP_MULT_QUEUE          0x0040     /* Support 2 tx & 2 rx queues */
+#define IGP3_CAP_RSS                 0x0080     /* Support RSS */
+#define IGP3_CAP_8021PQ              0x0100     /* Support 802.1Q & 802.1p */
+#define IGP3_CAP_AMT_CB              0x0200     /* Support active manageability and circuit breaker */
 
 #define IGP3_PPC_JORDAN_EN           0x0001
 #define IGP3_PPC_JORDAN_GIGA_SPEED   0x0002
@@ -3210,69 +2923,69 @@ struct e1000_host_command_info {
 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA        0x0020
 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100         0x0040
 
-#define IGP3E1000_PHY_MISC_CTRL                0x1B   /* Misc. Ctrl register */
-#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET        0x1000 /* Duplex Manual Set */
+#define IGP3E1000_PHY_MISC_CTRL                0x1B     /* Misc. Ctrl register */
+#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET        0x1000   /* Duplex Manual Set */
 
 #define IGP3_KMRN_EXT_CTRL  PHY_REG(770, 18)
 #define IGP3_KMRN_EC_DIS_INBAND    0x0080
 
 #define IGP03E1000_E_PHY_ID  0x02A80390
-#define IFE_E_PHY_ID         0x02A80330 /* 10/100 PHY */
+#define IFE_E_PHY_ID         0x02A80330 /* 10/100 PHY */
 #define IFE_PLUS_E_PHY_ID    0x02A80320
 #define IFE_C_E_PHY_ID       0x02A80310
 
-#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10  /* 100BaseTx Extended Status, Control and Address */
-#define IFE_PHY_SPECIAL_CONTROL           0x11  /* 100BaseTx PHY special control register */
-#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive False Carrier Counter */
-#define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnet Counter */
-#define IFE_PHY_RCV_ERROT_FRAME           0x15  /* 100BaseTx Receive Error Frame Counter */
-#define IFE_PHY_RCV_SYMBOL_ERR            0x16  /* Receive Symbol Error Counter */
-#define IFE_PHY_PREM_EOF_ERR              0x17  /* 100BaseTx Receive Premature End Of Frame Error Counter */
-#define IFE_PHY_RCV_EOF_ERR               0x18  /* 10BaseT Receive End Of Frame Error Counter */
-#define IFE_PHY_TX_JABBER_DETECT          0x19  /* 10BaseT Transmit Jabber Detect Counter */
-#define IFE_PHY_EQUALIZER                 0x1A  /* PHY Equalizer Control and Status */
-#define IFE_PHY_SPECIAL_CONTROL_LED       0x1B  /* PHY special control and LED configuration */
-#define IFE_PHY_MDIX_CONTROL              0x1C  /* MDI/MDI-X Control register */
-#define IFE_PHY_HWI_CONTROL               0x1D  /* Hardware Integrity Control (HWI) */
-
-#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000  /* Defaut 1 = Disable auto reduced power down */
-#define IFE_PESC_100BTX_POWER_DOWN           0x0400  /* Indicates the power state of 100BASE-TX */
-#define IFE_PESC_10BTX_POWER_DOWN            0x0200  /* Indicates the power state of 10BASE-T */
-#define IFE_PESC_POLARITY_REVERSED           0x0100  /* Indicates 10BASE-T polarity */
-#define IFE_PESC_PHY_ADDR_MASK               0x007C  /* Bit 6:2 for sampled PHY address */
-#define IFE_PESC_SPEED                       0x0002  /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
-#define IFE_PESC_DUPLEX                      0x0001  /* Auto-negotiation duplex result 1=Full, 0=Half */
+#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10  /* 100BaseTx Extended Status, Control and Address */
+#define IFE_PHY_SPECIAL_CONTROL           0x11  /* 100BaseTx PHY special control register */
+#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive False Carrier Counter */
+#define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnect Counter */
+#define IFE_PHY_RCV_ERROT_FRAME           0x15  /* 100BaseTx Receive Error Frame Counter */
+#define IFE_PHY_RCV_SYMBOL_ERR            0x16  /* Receive Symbol Error Counter */
+#define IFE_PHY_PREM_EOF_ERR              0x17  /* 100BaseTx Receive Premature End Of Frame Error Counter */
+#define IFE_PHY_RCV_EOF_ERR               0x18  /* 10BaseT Receive End Of Frame Error Counter */
+#define IFE_PHY_TX_JABBER_DETECT          0x19  /* 10BaseT Transmit Jabber Detect Counter */
+#define IFE_PHY_EQUALIZER                 0x1A  /* PHY Equalizer Control and Status */
+#define IFE_PHY_SPECIAL_CONTROL_LED       0x1B  /* PHY special control and LED configuration */
+#define IFE_PHY_MDIX_CONTROL              0x1C  /* MDI/MDI-X Control register */
+#define IFE_PHY_HWI_CONTROL               0x1D  /* Hardware Integrity Control (HWI) */
+
+#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000     /* Default 1 = Disable auto reduced power down */
+#define IFE_PESC_100BTX_POWER_DOWN           0x0400     /* Indicates the power state of 100BASE-TX */
+#define IFE_PESC_10BTX_POWER_DOWN            0x0200     /* Indicates the power state of 10BASE-T */
+#define IFE_PESC_POLARITY_REVERSED           0x0100     /* Indicates 10BASE-T polarity */
+#define IFE_PESC_PHY_ADDR_MASK               0x007C     /* Bit 6:2 for sampled PHY address */
+#define IFE_PESC_SPEED                       0x0002     /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
+#define IFE_PESC_DUPLEX                      0x0001     /* Auto-negotiation duplex result 1=Full, 0=Half */
 #define IFE_PESC_POLARITY_REVERSED_SHIFT     8
 
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100  /* 1 = Dyanmic Power Down disabled */
-#define IFE_PSC_FORCE_POLARITY               0x0020  /* 1=Reversed Polarity, 0=Normal */
-#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010  /* 1=Auto Polarity Disabled, 0=Enabled */
-#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001  /* 1=Jabber Disabled, 0=Normal Jabber Operation */
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100     /* 1 = Dynamic Power Down disabled */
+#define IFE_PSC_FORCE_POLARITY               0x0020     /* 1=Reversed Polarity, 0=Normal */
+#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010     /* 1=Auto Polarity Disabled, 0=Enabled */
+#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001     /* 1=Jabber Disabled, 0=Normal Jabber Operation */
 #define IFE_PSC_FORCE_POLARITY_SHIFT         5
 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT  4
 
-#define IFE_PMC_AUTO_MDIX                    0x0080  /* 1=enable MDI/MDI-X feature, default 0=disabled */
-#define IFE_PMC_FORCE_MDIX                   0x0040  /* 1=force MDIX-X, 0=force MDI */
-#define IFE_PMC_MDIX_STATUS                  0x0020  /* 1=MDI-X, 0=MDI */
-#define IFE_PMC_AUTO_MDIX_COMPLETE           0x0010  /* Resolution algorithm is completed */
+#define IFE_PMC_AUTO_MDIX                    0x0080     /* 1=enable MDI/MDI-X feature, default 0=disabled */
+#define IFE_PMC_FORCE_MDIX                   0x0040     /* 1=force MDIX-X, 0=force MDI */
+#define IFE_PMC_MDIX_STATUS                  0x0020     /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_AUTO_MDIX_COMPLETE           0x0010     /* Resolution algorithm is completed */
 #define IFE_PMC_MDIX_MODE_SHIFT              6
-#define IFE_PHC_MDIX_RESET_ALL_MASK          0x0000  /* Disable auto MDI-X */
-
-#define IFE_PHC_HWI_ENABLE                   0x8000  /* Enable the HWI feature */
-#define IFE_PHC_ABILITY_CHECK                0x4000  /* 1= Test Passed, 0=failed */
-#define IFE_PHC_TEST_EXEC                    0x2000  /* PHY launch test pulses on the wire */
-#define IFE_PHC_HIGHZ                        0x0200  /* 1 = Open Circuit */
-#define IFE_PHC_LOWZ                         0x0400  /* 1 = Short Circuit */
-#define IFE_PHC_LOW_HIGH_Z_MASK              0x0600  /* Mask for indication type of problem on the line */
-#define IFE_PHC_DISTANCE_MASK                0x01FF  /* Mask for distance to the cable problem, in 80cm granularity */
-#define IFE_PHC_RESET_ALL_MASK               0x0000  /* Disable HWI */
-#define IFE_PSCL_PROBE_MODE                  0x0020  /* LED Probe mode */
-#define IFE_PSCL_PROBE_LEDS_OFF              0x0006  /* Force LEDs 0 and 2 off */
-#define IFE_PSCL_PROBE_LEDS_ON               0x0007  /* Force LEDs 0 and 2 on */
-
-#define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
-#define ICH_FLASH_ERASE_TIMEOUT              3000000 /* Up to 3 seconds - worst case */
-#define ICH_FLASH_CYCLE_REPEAT_COUNT         10      /* 10 cycles */
+#define IFE_PHC_MDIX_RESET_ALL_MASK          0x0000     /* Disable auto MDI-X */
+
+#define IFE_PHC_HWI_ENABLE                   0x8000     /* Enable the HWI feature */
+#define IFE_PHC_ABILITY_CHECK                0x4000     /* 1= Test Passed, 0=failed */
+#define IFE_PHC_TEST_EXEC                    0x2000     /* PHY launch test pulses on the wire */
+#define IFE_PHC_HIGHZ                        0x0200     /* 1 = Open Circuit */
+#define IFE_PHC_LOWZ                         0x0400     /* 1 = Short Circuit */
+#define IFE_PHC_LOW_HIGH_Z_MASK              0x0600     /* Mask for indication type of problem on the line */
+#define IFE_PHC_DISTANCE_MASK                0x01FF     /* Mask for distance to the cable problem, in 80cm granularity */
+#define IFE_PHC_RESET_ALL_MASK               0x0000     /* Disable HWI */
+#define IFE_PSCL_PROBE_MODE                  0x0020     /* LED Probe mode */
+#define IFE_PSCL_PROBE_LEDS_OFF              0x0006     /* Force LEDs 0 and 2 off */
+#define IFE_PSCL_PROBE_LEDS_ON               0x0007     /* Force LEDs 0 and 2 on */
+
+#define ICH_FLASH_COMMAND_TIMEOUT            5000       /* 5000 uSecs - adjusted */
+#define ICH_FLASH_ERASE_TIMEOUT              3000000    /* Up to 3 seconds - worst case */
+#define ICH_FLASH_CYCLE_REPEAT_COUNT         10 /* 10 cycles */
 #define ICH_FLASH_SEG_SIZE_256               256
 #define ICH_FLASH_SEG_SIZE_4K                4096
 #define ICH_FLASH_SEG_SIZE_64K               65536
@@ -3305,74 +3018,6 @@ struct e1000_host_command_info {
 #define ICH_GFPREG_BASE_MASK       0x1FFF
 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
 
-/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
-/* Offset 04h HSFSTS */
-union ich8_hws_flash_status {
-    struct ich8_hsfsts {
-#ifdef __BIG_ENDIAN
-        u16 reserved2      :6;
-        u16 fldesvalid     :1;
-        u16 flockdn        :1;
-        u16 flcdone        :1;
-        u16 flcerr         :1;
-        u16 dael           :1;
-        u16 berasesz       :2;
-        u16 flcinprog      :1;
-        u16 reserved1      :2;
-#else
-        u16 flcdone        :1;   /* bit 0 Flash Cycle Done */
-        u16 flcerr         :1;   /* bit 1 Flash Cycle Error */
-        u16 dael           :1;   /* bit 2 Direct Access error Log */
-        u16 berasesz       :2;   /* bit 4:3 Block/Sector Erase Size */
-        u16 flcinprog      :1;   /* bit 5 flash SPI cycle in Progress */
-        u16 reserved1      :2;   /* bit 13:6 Reserved */
-        u16 reserved2      :6;   /* bit 13:6 Reserved */
-        u16 fldesvalid     :1;   /* bit 14 Flash Descriptor Valid */
-        u16 flockdn        :1;   /* bit 15 Flash Configuration Lock-Down */
-#endif
-    } hsf_status;
-    u16 regval;
-};
-
-/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
-/* Offset 06h FLCTL */
-union ich8_hws_flash_ctrl {
-    struct ich8_hsflctl {
-#ifdef __BIG_ENDIAN
-        u16 fldbcount      :2;
-        u16 flockdn        :6;
-        u16 flcgo          :1;
-        u16 flcycle        :2;
-        u16 reserved       :5;
-#else
-        u16 flcgo          :1;   /* 0 Flash Cycle Go */
-        u16 flcycle        :2;   /* 2:1 Flash Cycle */
-        u16 reserved       :5;   /* 7:3 Reserved  */
-        u16 fldbcount      :2;   /* 9:8 Flash Data Byte Count */
-        u16 flockdn        :6;   /* 15:10 Reserved */
-#endif
-    } hsf_ctrl;
-    u16 regval;
-};
-
-/* ICH8 Flash Region Access Permissions */
-union ich8_hws_flash_regacc {
-    struct ich8_flracc {
-#ifdef __BIG_ENDIAN
-        u32 gmwag          :8;
-        u32 gmrag          :8;
-        u32 grwa           :8;
-        u32 grra           :8;
-#else
-        u32 grra           :8;   /* 0:7 GbE region Read Access */
-        u32 grwa           :8;   /* 8:15 GbE region Write Access */
-        u32 gmrag          :8;   /* 23:16 GbE Master Read Access Grant  */
-        u32 gmwag          :8;   /* 31:24 GbE Master Write Access Grant */
-#endif
-    } hsf_flregacc;
-    u16 regval;
-};
-
 /* Miscellaneous PHY bit definitions. */
 #define PHY_PREAMBLE        0xFFFFFFFF
 #define PHY_SOF             0x01
@@ -3384,10 +3029,10 @@ union ich8_hws_flash_regacc {
 #define MII_CR_SPEED_100    0x2000
 #define MII_CR_SPEED_10     0x0000
 #define E1000_PHY_ADDRESS   0x01
-#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
-#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
+#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
+#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
 #define PHY_REVISION_MASK   0xFFFFFFF0
-#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
+#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
 #define REG4_SPEED_MASK     0x01E0
 #define REG9_SPEED_MASK     0x0300
 #define ADVERTISE_10_HALF   0x0001
@@ -3396,8 +3041,8 @@ union ich8_hws_flash_regacc {
 #define ADVERTISE_100_FULL  0x0008
 #define ADVERTISE_1000_HALF 0x0010
 #define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
-#define AUTONEG_ADVERTISE_10_100_ALL    0x000F /* All 10/100 speeds*/
-#define AUTONEG_ADVERTISE_10_ALL        0x0003 /* 10Mbps Full & Half speeds*/
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
+#define AUTONEG_ADVERTISE_10_100_ALL    0x000F  /* All 10/100 speeds */
+#define AUTONEG_ADVERTISE_10_ALL        0x0003  /* 10Mbps Full & Half speeds */
 
 #endif /* _E1000_HW_H_ */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index c66dd4f9437c..bcd192ca47b0 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -31,7 +31,7 @@
 
 char e1000_driver_name[] = "e1000";
 static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
-#define DRV_VERSION "7.3.21-k3-NAPI"
+#define DRV_VERSION "7.3.21-k5-NAPI"
 const char e1000_driver_version[] = DRV_VERSION;
 static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
 
@@ -131,7 +131,6 @@ static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
 static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
 static int e1000_set_mac(struct net_device *netdev, void *p);
 static irqreturn_t e1000_intr(int irq, void *data);
-static irqreturn_t e1000_intr_msi(int irq, void *data);
 static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
                                struct e1000_tx_ring *tx_ring);
 static int e1000_clean(struct napi_struct *napi, int budget);
@@ -258,25 +257,14 @@ module_exit(e1000_exit_module);
 
 static int e1000_request_irq(struct e1000_adapter *adapter)
 {
-        struct e1000_hw *hw = &adapter->hw;
         struct net_device *netdev = adapter->netdev;
         irq_handler_t handler = e1000_intr;
         int irq_flags = IRQF_SHARED;
         int err;
 
-        if (hw->mac_type >= e1000_82571) {
-                adapter->have_msi = !pci_enable_msi(adapter->pdev);
-                if (adapter->have_msi) {
-                        handler = e1000_intr_msi;
-                        irq_flags = 0;
-                }
-        }
-
         err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
                           netdev);
         if (err) {
-                if (adapter->have_msi)
-                        pci_disable_msi(adapter->pdev);
                 DPRINTK(PROBE, ERR,
                         "Unable to allocate interrupt Error: %d\n", err);
         }
@@ -289,9 +277,6 @@ static void e1000_free_irq(struct e1000_adapter *adapter)
         struct net_device *netdev = adapter->netdev;
 
         free_irq(adapter->pdev->irq, netdev);
-
-        if (adapter->have_msi)
-                pci_disable_msi(adapter->pdev);
 }
 
 /**
@@ -345,76 +330,6 @@ static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
         }
 }
 
-/**
- * e1000_release_hw_control - release control of the h/w to f/w
- * @adapter: address of board private structure
- *
- * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
- * For ASF and Pass Through versions of f/w this means that the
- * driver is no longer loaded. For AMT version (only with 82573) i
- * of the f/w this means that the network i/f is closed.
- *
- **/
-
-static void e1000_release_hw_control(struct e1000_adapter *adapter)
-{
-        u32 ctrl_ext;
-        u32 swsm;
-        struct e1000_hw *hw = &adapter->hw;
-
-        /* Let firmware taken over control of h/w */
-        switch (hw->mac_type) {
-        case e1000_82573:
-                swsm = er32(SWSM);
-                ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
-                break;
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_80003es2lan:
-        case e1000_ich8lan:
-                ctrl_ext = er32(CTRL_EXT);
-                ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
-                break;
-        default:
-                break;
-        }
-}
-
-/**
- * e1000_get_hw_control - get control of the h/w from f/w
- * @adapter: address of board private structure
- *
- * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
- * For ASF and Pass Through versions of f/w this means that
- * the driver is loaded. For AMT version (only with 82573)
- * of the f/w this means that the network i/f is open.
- *
- **/
-
-static void e1000_get_hw_control(struct e1000_adapter *adapter)
-{
-        u32 ctrl_ext;
-        u32 swsm;
-        struct e1000_hw *hw = &adapter->hw;
-
-        /* Let firmware know the driver has taken over */
-        switch (hw->mac_type) {
-        case e1000_82573:
-                swsm = er32(SWSM);
-                ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
-                break;
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_80003es2lan:
-        case e1000_ich8lan:
-                ctrl_ext = er32(CTRL_EXT);
-                ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
-                break;
-        default:
-                break;
-        }
-}
-
 static void e1000_init_manageability(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
@@ -425,20 +340,6 @@ static void e1000_init_manageability(struct e1000_adapter *adapter)
                 /* disable hardware interception of ARP */
                 manc &= ~(E1000_MANC_ARP_EN);
 
-                /* enable receiving management packets to the host */
-                /* this will probably generate destination unreachable messages
-                 * from the host OS, but the packets will be handled on SMBUS */
-                if (hw->has_manc2h) {
-                        u32 manc2h = er32(MANC2H);
-
-                        manc |= E1000_MANC_EN_MNG2HOST;
-#define E1000_MNG2HOST_PORT_623 (1 << 5)
-#define E1000_MNG2HOST_PORT_664 (1 << 6)
-                        manc2h |= E1000_MNG2HOST_PORT_623;
-                        manc2h |= E1000_MNG2HOST_PORT_664;
-                        ew32(MANC2H, manc2h);
-                }
-
                 ew32(MANC, manc);
         }
 }
@@ -453,12 +354,6 @@ static void e1000_release_manageability(struct e1000_adapter *adapter)
                 /* re-enable hardware interception of ARP */
                 manc |= E1000_MANC_ARP_EN;
 
-                if (hw->has_manc2h)
-                        manc &= ~E1000_MANC_EN_MNG2HOST;
-
-                /* don't explicitly have to mess with MANC2H since
-                 * MANC has an enable disable that gates MANC2H */
-
                 ew32(MANC, manc);
         }
 }
@@ -563,15 +458,6 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter)
                         if (er32(MANC) & E1000_MANC_SMBUS_EN)
                                 goto out;
                         break;
-                case e1000_82571:
-                case e1000_82572:
-                case e1000_82573:
-                case e1000_80003es2lan:
-                case e1000_ich8lan:
-                        if (e1000_check_mng_mode(hw) ||
-                            e1000_check_phy_reset_block(hw))
-                                goto out;
-                        break;
                 default:
                         goto out;
                 }
@@ -599,8 +485,7 @@ void e1000_down(struct e1000_adapter *adapter)
         ew32(RCTL, rctl & ~E1000_RCTL_EN);
         /* flush and sleep below */
 
-        /* can be netif_tx_disable when NETIF_F_LLTX is removed */
-        netif_stop_queue(netdev);
+        netif_tx_disable(netdev);
 
         /* disable transmits in the hardware */
         tctl = er32(TCTL);
@@ -671,16 +556,6 @@ void e1000_reset(struct e1000_adapter *adapter)
                 legacy_pba_adjust = true;
                 pba = E1000_PBA_30K;
                 break;
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_80003es2lan:
-                pba = E1000_PBA_38K;
-                break;
-        case e1000_82573:
-                pba = E1000_PBA_20K;
-                break;
-        case e1000_ich8lan:
-                pba = E1000_PBA_8K;
         case e1000_undefined:
         case e1000_num_macs:
                 break;
@@ -744,16 +619,8 @@ void e1000_reset(struct e1000_adapter *adapter)
 
                         /* if short on rx space, rx wins and must trump tx
                          * adjustment or use Early Receive if available */
-                        if (pba < min_rx_space) {
-                                switch (hw->mac_type) {
-                                case e1000_82573:
-                                        /* ERT enabled in e1000_configure_rx */
-                                        break;
-                                default:
-                                        pba = min_rx_space;
-                                        break;
-                                }
-                        }
+                        if (pba < min_rx_space)
+                                pba = min_rx_space;
                 }
         }
 
@@ -789,7 +656,6 @@ void e1000_reset(struct e1000_adapter *adapter)
 
         /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
         if (hw->mac_type >= e1000_82544 &&
-            hw->mac_type <= e1000_82547_rev_2 &&
             hw->autoneg == 1 &&
             hw->autoneg_advertised == ADVERTISE_1000_FULL) {
                 u32 ctrl = er32(CTRL);
@@ -806,20 +672,6 @@ void e1000_reset(struct e1000_adapter *adapter)
         e1000_reset_adaptive(hw);
         e1000_phy_get_info(hw, &adapter->phy_info);
 
-        if (!adapter->smart_power_down &&
-            (hw->mac_type == e1000_82571 ||
-             hw->mac_type == e1000_82572)) {
-                u16 phy_data = 0;
-                /* speed up time to link by disabling smart power down, ignore
-                 * the return value of this function because there is nothing
-                 * different we would do if it failed */
-                e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                   &phy_data);
-                phy_data &= ~IGP02E1000_PM_SPD;
-                e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                    phy_data);
-        }
-
         e1000_release_manageability(adapter);
 }
 
@@ -1046,17 +898,6 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                 goto err_sw_init;
 
         err = -EIO;
-        /* Flash BAR mapping must happen after e1000_sw_init
-         * because it depends on mac_type */
-        if ((hw->mac_type == e1000_ich8lan) &&
-           (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
-                hw->flash_address = pci_ioremap_bar(pdev, 1);
-                if (!hw->flash_address)
-                        goto err_flashmap;
-        }
-
-        if (e1000_check_phy_reset_block(hw))
-                DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
 
         if (hw->mac_type >= e1000_82543) {
                 netdev->features = NETIF_F_SG |
@@ -1064,21 +905,16 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                                    NETIF_F_HW_VLAN_TX |
                                    NETIF_F_HW_VLAN_RX |
                                    NETIF_F_HW_VLAN_FILTER;
-                if (hw->mac_type == e1000_ich8lan)
-                        netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
         }
 
         if ((hw->mac_type >= e1000_82544) &&
            (hw->mac_type != e1000_82547))
                 netdev->features |= NETIF_F_TSO;
 
-        if (hw->mac_type > e1000_82547_rev_2)
-                netdev->features |= NETIF_F_TSO6;
         if (pci_using_dac)
                 netdev->features |= NETIF_F_HIGHDMA;
 
         netdev->vlan_features |= NETIF_F_TSO;
-        netdev->vlan_features |= NETIF_F_TSO6;
         netdev->vlan_features |= NETIF_F_HW_CSUM;
         netdev->vlan_features |= NETIF_F_SG;
 
@@ -1153,15 +989,8 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                         EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
                 eeprom_apme_mask = E1000_EEPROM_82544_APM;
                 break;
-        case e1000_ich8lan:
-                e1000_read_eeprom(hw,
-                        EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
-                eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
-                break;
         case e1000_82546:
         case e1000_82546_rev_3:
-        case e1000_82571:
-        case e1000_80003es2lan:
                 if (er32(STATUS) & E1000_STATUS_FUNC_1){
                         e1000_read_eeprom(hw,
                                 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
@@ -1185,17 +1014,12 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                 break;
         case E1000_DEV_ID_82546EB_FIBER:
         case E1000_DEV_ID_82546GB_FIBER:
-        case E1000_DEV_ID_82571EB_FIBER:
                 /* Wake events only supported on port A for dual fiber
                  * regardless of eeprom setting */
                 if (er32(STATUS) & E1000_STATUS_FUNC_1)
                         adapter->eeprom_wol = 0;
                 break;
         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
-        case E1000_DEV_ID_82571EB_QUAD_COPPER:
-        case E1000_DEV_ID_82571EB_QUAD_FIBER:
-        case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
-        case E1000_DEV_ID_82571PT_QUAD_COPPER:
                 /* if quad port adapter, disable WoL on all but port A */
                 if (global_quad_port_a != 0)
                         adapter->eeprom_wol = 0;
@@ -1213,39 +1037,18 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
 
         /* print bus type/speed/width info */
         DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
-                ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
-                 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
-                ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
-                 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
+                ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : ""),
+                ((hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
                  (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
                  (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
                  (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
-                ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
-                 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
-                 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
-                 "32-bit"));
+                ((hw->bus_width == e1000_bus_width_64) ? "64-bit" : "32-bit"));
 
         printk("%pM\n", netdev->dev_addr);
 
-        if (hw->bus_type == e1000_bus_type_pci_express) {
-                DPRINTK(PROBE, WARNING, "This device (id %04x:%04x) will no "
-                        "longer be supported by this driver in the future.\n",
-                        pdev->vendor, pdev->device);
-                DPRINTK(PROBE, WARNING, "please use the \"e1000e\" "
-                        "driver instead.\n");
-        }
-
         /* reset the hardware with the new settings */
         e1000_reset(adapter);
 
-        /* If the controller is 82573 and f/w is AMT, do not set
-         * DRV_LOAD until the interface is up.  For all other cases,
-         * let the f/w know that the h/w is now under the control
-         * of the driver. */
-        if (hw->mac_type != e1000_82573 ||
-            !e1000_check_mng_mode(hw))
-                e1000_get_hw_control(adapter);
-
         strcpy(netdev->name, "eth%d");
         err = register_netdev(netdev);
         if (err)
@@ -1260,14 +1063,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         return 0;
 
 err_register:
-        e1000_release_hw_control(adapter);
 err_eeprom:
-        if (!e1000_check_phy_reset_block(hw))
-                e1000_phy_hw_reset(hw);
+        e1000_phy_hw_reset(hw);
 
         if (hw->flash_address)
                 iounmap(hw->flash_address);
-err_flashmap:
         kfree(adapter->tx_ring);
         kfree(adapter->rx_ring);
 err_sw_init:
@@ -1298,18 +1098,18 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
         struct e1000_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
 
+        set_bit(__E1000_DOWN, &adapter->flags);
+        del_timer_sync(&adapter->tx_fifo_stall_timer);
+        del_timer_sync(&adapter->watchdog_timer);
+        del_timer_sync(&adapter->phy_info_timer);
+
         cancel_work_sync(&adapter->reset_task);
 
         e1000_release_manageability(adapter);
 
-        /* Release control of h/w to f/w.  If f/w is AMT enabled, this
-         * would have already happened in close and is redundant. */
-        e1000_release_hw_control(adapter);
-
         unregister_netdev(netdev);
 
-        if (!e1000_check_phy_reset_block(hw))
-                e1000_phy_hw_reset(hw);
+        e1000_phy_hw_reset(hw);
 
         kfree(adapter->tx_ring);
         kfree(adapter->rx_ring);
@@ -1472,12 +1272,6 @@ static int e1000_open(struct net_device *netdev)
                 e1000_update_mng_vlan(adapter);
         }
 
-        /* If AMT is enabled, let the firmware know that the network
-         * interface is now open */
-        if (hw->mac_type == e1000_82573 &&
-            e1000_check_mng_mode(hw))
-                e1000_get_hw_control(adapter);
-
         /* before we allocate an interrupt, we must be ready to handle it.
          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
          * as soon as we call pci_request_irq, so we have to setup our
@@ -1503,7 +1297,6 @@ static int e1000_open(struct net_device *netdev)
         return E1000_SUCCESS;
 
 err_req_irq:
-        e1000_release_hw_control(adapter);
         e1000_power_down_phy(adapter);
         e1000_free_all_rx_resources(adapter);
 err_setup_rx:
@@ -1548,12 +1341,6 @@ static int e1000_close(struct net_device *netdev)
                 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
         }
 
-        /* If AMT is enabled, let the firmware know that the network
-         * interface is now closed */
-        if (hw->mac_type == e1000_82573 &&
-            e1000_check_mng_mode(hw))
-                e1000_release_hw_control(adapter);
-
         return 0;
 }
 
@@ -1692,7 +1479,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
 {
         u64 tdba;
         struct e1000_hw *hw = &adapter->hw;
-        u32 tdlen, tctl, tipg, tarc;
+        u32 tdlen, tctl, tipg;
         u32 ipgr1, ipgr2;
 
         /* Setup the HW Tx Head and Tail descriptor pointers */
@@ -1714,8 +1501,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
         }
 
         /* Set the default values for the Tx Inter Packet Gap timer */
-        if (hw->mac_type <= e1000_82547_rev_2 &&
-            (hw->media_type == e1000_media_type_fiber ||
+        if ((hw->media_type == e1000_media_type_fiber ||
              hw->media_type == e1000_media_type_internal_serdes))
                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
         else
@@ -1728,10 +1514,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
                 break;
-        case e1000_80003es2lan:
-                ipgr1 = DEFAULT_82543_TIPG_IPGR1;
-                ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
-                break;
         default:
                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
@@ -1754,21 +1536,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
 
-        if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
-                tarc = er32(TARC0);
-                /* set the speed mode bit, we'll clear it if we're not at
-                 * gigabit link later */
-                tarc |= (1 << 21);
-                ew32(TARC0, tarc);
-        } else if (hw->mac_type == e1000_80003es2lan) {
-                tarc = er32(TARC0);
-                tarc |= 1;
-                ew32(TARC0, tarc);
-                tarc = er32(TARC1);
-                tarc |= 1;
-                ew32(TARC1, tarc);
-        }
-
         e1000_config_collision_dist(hw);
 
         /* Setup Transmit Descriptor Settings for eop descriptor */
@@ -1804,7 +1571,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
 static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
                                     struct e1000_rx_ring *rxdr)
 {
-        struct e1000_hw *hw = &adapter->hw;
         struct pci_dev *pdev = adapter->pdev;
         int size, desc_len;
 
@@ -1817,10 +1583,7 @@ static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
         }
         memset(rxdr->buffer_info, 0, size);
 
-        if (hw->mac_type <= e1000_82547_rev_2)
-                desc_len = sizeof(struct e1000_rx_desc);
-        else
-                desc_len = sizeof(union e1000_rx_desc_packet_split);
+        desc_len = sizeof(struct e1000_rx_desc);
 
         /* Round up to nearest 4K */
 
@@ -1977,7 +1740,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
 {
         u64 rdba;
         struct e1000_hw *hw = &adapter->hw;
-        u32 rdlen, rctl, rxcsum, ctrl_ext;
+        u32 rdlen, rctl, rxcsum;
 
         if (adapter->netdev->mtu > ETH_DATA_LEN) {
                 rdlen = adapter->rx_ring[0].count *
@@ -2004,17 +1767,6 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
                         ew32(ITR, 1000000000 / (adapter->itr * 256));
         }
 
-        if (hw->mac_type >= e1000_82571) {
-                ctrl_ext = er32(CTRL_EXT);
-                /* Reset delay timers after every interrupt */
-                ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
-                /* Auto-Mask interrupts upon ICR access */
-                ctrl_ext |= E1000_CTRL_EXT_IAME;
-                ew32(IAM, 0xffffffff);
-                ew32(CTRL_EXT, ctrl_ext);
-                E1000_WRITE_FLUSH();
-        }
-
         /* Setup the HW Rx Head and Tail Descriptor Pointers and
          * the Base and Length of the Rx Descriptor Ring */
         switch (adapter->num_rx_queues) {
@@ -2329,22 +2081,6 @@ static int e1000_set_mac(struct net_device *netdev, void *p)
 
         e1000_rar_set(hw, hw->mac_addr, 0);
 
-        /* With 82571 controllers, LAA may be overwritten (with the default)
-         * due to controller reset from the other port. */
-        if (hw->mac_type == e1000_82571) {
-                /* activate the work around */
-                hw->laa_is_present = 1;
-
-                /* Hold a copy of the LAA in RAR[14] This is done so that
-                 * between the time RAR[0] gets clobbered  and the time it
-                 * gets fixed (in e1000_watchdog), the actual LAA is in one
-                 * of the RARs and no incoming packets directed to this port
-                 * are dropped. Eventaully the LAA will be in RAR[0] and
-                 * RAR[14] */
-                e1000_rar_set(hw, hw->mac_addr,
-                                        E1000_RAR_ENTRIES - 1);
-        }
-
         if (hw->mac_type == e1000_82542_rev2_0)
                 e1000_leave_82542_rst(adapter);
 
@@ -2371,9 +2107,7 @@ static void e1000_set_rx_mode(struct net_device *netdev)
         u32 rctl;
         u32 hash_value;
         int i, rar_entries = E1000_RAR_ENTRIES;
-        int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
-                                E1000_NUM_MTA_REGISTERS_ICH8LAN :
-                                E1000_NUM_MTA_REGISTERS;
+        int mta_reg_count = E1000_NUM_MTA_REGISTERS;
         u32 *mcarray = kcalloc(mta_reg_count, sizeof(u32), GFP_ATOMIC);
 
         if (!mcarray) {
@@ -2381,13 +2115,6 @@ static void e1000_set_rx_mode(struct net_device *netdev)
                 return;
         }
 
-        if (hw->mac_type == e1000_ich8lan)
-                rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
-
-        /* reserve RAR[14] for LAA over-write work-around */
-        if (hw->mac_type == e1000_82571)
-                rar_entries--;
-
         /* Check for Promiscuous and All Multicast modes */
 
         rctl = er32(RCTL);
@@ -2396,15 +2123,13 @@ static void e1000_set_rx_mode(struct net_device *netdev)
                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
                 rctl &= ~E1000_RCTL_VFE;
         } else {
-                if (netdev->flags & IFF_ALLMULTI) {
+                if (netdev->flags & IFF_ALLMULTI)
                         rctl |= E1000_RCTL_MPE;
-                } else {
+                else
                         rctl &= ~E1000_RCTL_MPE;
-                }
-                if (adapter->hw.mac_type != e1000_ich8lan)
-                        /* Enable VLAN filter if there is a VLAN */
-                        if (adapter->vlgrp)
-                                rctl |= E1000_RCTL_VFE;
+                /* Enable VLAN filter if there is a VLAN */
+                if (adapter->vlgrp)
+                        rctl |= E1000_RCTL_VFE;
         }
 
         if (netdev->uc.count > rar_entries - 1) {
@@ -2427,7 +2152,6 @@ static void e1000_set_rx_mode(struct net_device *netdev)
          *
          * RAR 0 is used for the station MAC adddress
          * if there are not 14 addresses, go ahead and clear the filters
-         * -- with 82571 controllers only 0-13 entries are filled here
          */
         i = 1;
         if (use_uc)
@@ -2521,12 +2245,46 @@ static void e1000_82547_tx_fifo_stall(unsigned long data)
                         adapter->tx_fifo_head = 0;
                         atomic_set(&adapter->tx_fifo_stall, 0);
                         netif_wake_queue(netdev);
-                } else {
+                } else if (!test_bit(__E1000_DOWN, &adapter->flags)) {
                         mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
                 }
         }
 }
 
+static bool e1000_has_link(struct e1000_adapter *adapter)
+{
+        struct e1000_hw *hw = &adapter->hw;
+        bool link_active = false;
+
+        /* get_link_status is set on LSC (link status) interrupt or
+         * rx sequence error interrupt.  get_link_status will stay
+         * false until the e1000_check_for_link establishes link
+         * for copper adapters ONLY
+         */
+        switch (hw->media_type) {
+        case e1000_media_type_copper:
+                if (hw->get_link_status) {
+                        e1000_check_for_link(hw);
+                        link_active = !hw->get_link_status;
+                } else {
+                        link_active = true;
+                }
+                break;
+        case e1000_media_type_fiber:
+                e1000_check_for_link(hw);
+                link_active = !!(er32(STATUS) & E1000_STATUS_LU);
+                break;
+        case e1000_media_type_internal_serdes:
+                e1000_check_for_link(hw);
+                link_active = hw->serdes_has_link;
+                break;
+        default:
+                break;
+        }
+
+        return link_active;
+}
+
 /**
  * e1000_watchdog - Timer Call-back
  * @data: pointer to adapter cast into an unsigned long
@@ -2538,33 +2296,16 @@ static void e1000_watchdog(unsigned long data)
         struct net_device *netdev = adapter->netdev;
         struct e1000_tx_ring *txdr = adapter->tx_ring;
         u32 link, tctl;
-        s32 ret_val;
-
-        ret_val = e1000_check_for_link(hw);
-        if ((ret_val == E1000_ERR_PHY) &&
-            (hw->phy_type == e1000_phy_igp_3) &&
-            (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
-                /* See e1000_kumeran_lock_loss_workaround() */
-                DPRINTK(LINK, INFO,
-                        "Gigabit has been disabled, downgrading speed\n");
-        }
 
-        if (hw->mac_type == e1000_82573) {
-                e1000_enable_tx_pkt_filtering(hw);
-                if (adapter->mng_vlan_id != hw->mng_cookie.vlan_id)
-                        e1000_update_mng_vlan(adapter);
-        }
-
-        if ((hw->media_type == e1000_media_type_internal_serdes) &&
-           !(er32(TXCW) & E1000_TXCW_ANE))
-                link = !hw->serdes_link_down;
-        else
-                link = er32(STATUS) & E1000_STATUS_LU;
+        link = e1000_has_link(adapter);
+        if ((netif_carrier_ok(netdev)) && link)
+                goto link_up;
 
         if (link) {
                 if (!netif_carrier_ok(netdev)) {
                         u32 ctrl;
                         bool txb2b = true;
+                        /* update snapshot of PHY registers on LSC */
                         e1000_get_speed_and_duplex(hw,
                                                    &adapter->link_speed,
                                                    &adapter->link_duplex);
@@ -2589,7 +2330,7 @@ static void e1000_watchdog(unsigned long data)
                         case SPEED_10:
                                 txb2b = false;
                                 netdev->tx_queue_len = 10;
-                                adapter->tx_timeout_factor = 8;
+                                adapter->tx_timeout_factor = 16;
                                 break;
                         case SPEED_100:
                                 txb2b = false;
@@ -2598,52 +2339,16 @@ static void e1000_watchdog(unsigned long data)
                                 break;
                         }
 
-                        if ((hw->mac_type == e1000_82571 ||
-                             hw->mac_type == e1000_82572) &&
-                            !txb2b) {
-                                u32 tarc0;
-                                tarc0 = er32(TARC0);
-                                tarc0 &= ~(1 << 21);
-                                ew32(TARC0, tarc0);
-                        }
-
-                        /* disable TSO for pcie and 10/100 speeds, to avoid
-                         * some hardware issues */
-                        if (!adapter->tso_force &&
-                            hw->bus_type == e1000_bus_type_pci_express){
-                                switch (adapter->link_speed) {
-                                case SPEED_10:
-                                case SPEED_100:
-                                        DPRINTK(PROBE,INFO,
-                                        "10/100 speed: disabling TSO\n");
-                                        netdev->features &= ~NETIF_F_TSO;
-                                        netdev->features &= ~NETIF_F_TSO6;
-                                        break;
-                                case SPEED_1000:
-                                        netdev->features |= NETIF_F_TSO;
-                                        netdev->features |= NETIF_F_TSO6;
-                                        break;
-                                default:
-                                        /* oops */
-                                        break;
-                                }
-                        }
-
-                        /* enable transmits in the hardware, need to do this
-                         * after setting TARC0 */
+                        /* enable transmits in the hardware */
                         tctl = er32(TCTL);
                         tctl |= E1000_TCTL_EN;
                         ew32(TCTL, tctl);
 
                         netif_carrier_on(netdev);
-                        mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
+                        if (!test_bit(__E1000_DOWN, &adapter->flags))
+                                mod_timer(&adapter->phy_info_timer,
+                                          round_jiffies(jiffies + 2 * HZ));
                         adapter->smartspeed = 0;
-                } else {
-                        /* make sure the receive unit is started */
-                        if (hw->rx_needs_kicking) {
-                                u32 rctl = er32(RCTL);
-                                ew32(RCTL, rctl | E1000_RCTL_EN);
-                        }
                 }
         } else {
                 if (netif_carrier_ok(netdev)) {
@@ -2652,21 +2357,16 @@ static void e1000_watchdog(unsigned long data)
                         printk(KERN_INFO "e1000: %s NIC Link is Down\n",
                                netdev->name);
                         netif_carrier_off(netdev);
-                        mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
-
-                        /* 80003ES2LAN workaround--
-                         * For packet buffer work-around on link down event;
-                         * disable receives in the ISR and
-                         * reset device here in the watchdog
-                         */
-                        if (hw->mac_type == e1000_80003es2lan)
-                                /* reset device */
-                                schedule_work(&adapter->reset_task);
+
+                        if (!test_bit(__E1000_DOWN, &adapter->flags))
+                                mod_timer(&adapter->phy_info_timer,
+                                          round_jiffies(jiffies + 2 * HZ));
                 }
 
                 e1000_smartspeed(adapter);
         }
 
+link_up:
         e1000_update_stats(adapter);
 
         hw->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
@@ -2700,13 +2400,10 @@ static void e1000_watchdog(unsigned long data)
         /* Force detection of hung controller every watchdog period */
         adapter->detect_tx_hung = true;
 
-        /* With 82571 controllers, LAA may be overwritten due to controller
-         * reset from the other port. Set the appropriate LAA in RAR[0] */
-        if (hw->mac_type == e1000_82571 && hw->laa_is_present)
-                e1000_rar_set(hw, hw->mac_addr, 0);
-
         /* Reset the timer */
-        mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
+        if (!test_bit(__E1000_DOWN, &adapter->flags))
+                mod_timer(&adapter->watchdog_timer,
+                          round_jiffies(jiffies + 2 * HZ));
 }
 
 enum latency_range {
@@ -2718,6 +2415,11 @@ enum latency_range {
 
 /**
  * e1000_update_itr - update the dynamic ITR value based on statistics
+ * @adapter: pointer to adapter
+ * @itr_setting: current adapter->itr
+ * @packets: the number of packets during this measurement interval
+ * @bytes: the number of bytes during this measurement interval
+ *
  *      Stores a new ITR value based on packets and byte
  *      counts during the last interrupt.  The advantage of per interrupt
  *      computation is faster updates and more accurate ITR for the current
@@ -2727,10 +2429,6 @@ enum latency_range {
  *      while increasing bulk throughput.
  *      this functionality is controlled by the InterruptThrottleRate module
  *      parameter (see e1000_param.c)
- * @adapter: pointer to adapter
- * @itr_setting: current adapter->itr
- * @packets: the number of packets during this measurement interval
- * @bytes: the number of bytes during this measurement interval
  **/
 static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
                                      u16 itr_setting, int packets, int bytes)
@@ -3035,8 +2733,9 @@ static int e1000_tx_map(struct e1000_adapter *adapter,
                         size -= 4;
 
                 buffer_info->length = size;
-                buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
+                /* set time_stamp *before* dma to help avoid a possible race */
                 buffer_info->time_stamp = jiffies;
+                buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
                 buffer_info->next_to_watch = i;
 
                 len -= size;
@@ -3071,13 +2770,14 @@ static int e1000_tx_map(struct e1000_adapter *adapter,
                          * Avoid terminating buffers within evenly-aligned
                          * dwords. */
                         if (unlikely(adapter->pcix_82544 &&
-                           !((unsigned long)(frag->page+offset+size-1) & 4) &&
-                           size > 4))
+                            !((unsigned long)(page_to_phys(frag->page) + offset
+                                              + size - 1) & 4) &&
+                            size > 4))
                                 size -= 4;
 
                         buffer_info->length = size;
-                        buffer_info->dma = map[f] + offset;
                         buffer_info->time_stamp = jiffies;
+                        buffer_info->dma = map[f] + offset;
                         buffer_info->next_to_watch = i;
 
                         len -= size;
@@ -3186,41 +2886,6 @@ no_fifo_stall_required:
         return 0;
 }
 
-#define MINIMUM_DHCP_PACKET_SIZE 282
-static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
-                                    struct sk_buff *skb)
-{
-        struct e1000_hw *hw =  &adapter->hw;
-        u16 length, offset;
-        if (vlan_tx_tag_present(skb)) {
-                if (!((vlan_tx_tag_get(skb) == hw->mng_cookie.vlan_id) &&
-                        ( hw->mng_cookie.status &
-                          E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
-                        return 0;
-        }
-        if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
-                struct ethhdr *eth = (struct ethhdr *)skb->data;
-                if ((htons(ETH_P_IP) == eth->h_proto)) {
-                        const struct iphdr *ip =
-                                (struct iphdr *)((u8 *)skb->data+14);
-                        if (IPPROTO_UDP == ip->protocol) {
-                                struct udphdr *udp =
-                                        (struct udphdr *)((u8 *)ip +
-                                                (ip->ihl << 2));
-                                if (ntohs(udp->dest) == 67) {
-                                        offset = (u8 *)udp + 8 - skb->data;
-                                        length = skb->len - offset;
-
-                                        return e1000_mng_write_dhcp_info(hw,
-                                                        (u8 *)udp + 8,
-                                                        length);
-                                }
-                        }
-                }
-        }
-        return 0;
-}
-
 static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -3279,11 +2944,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
                 return NETDEV_TX_OK;
         }
 
-        /* 82571 and newer doesn't need the workaround that limited descriptor
-         * length to 4kB */
-        if (hw->mac_type >= e1000_82571)
-                max_per_txd = 8192;
-
         mss = skb_shinfo(skb)->gso_size;
         /* The controller does a simple calculation to
          * make sure there is enough room in the FIFO before
@@ -3296,9 +2956,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
                 max_per_txd = min(mss << 2, max_per_txd);
                 max_txd_pwr = fls(max_per_txd) - 1;
 
-                /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
-                * points to just header, pull a few bytes of payload from
-                * frags into skb->data */
                 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
                 if (skb->data_len && hdr_len == len) {
                         switch (hw->mac_type) {
@@ -3313,10 +2970,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
                                 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
                                         break;
                                 /* fall through */
-                        case e1000_82571:
-                        case e1000_82572:
-                        case e1000_82573:
-                        case e1000_ich8lan:
                                 pull_size = min((unsigned int)4, skb->data_len);
                                 if (!__pskb_pull_tail(skb, pull_size)) {
                                         DPRINTK(DRV, ERR,
@@ -3361,11 +3014,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
         if (adapter->pcix_82544)
                 count += nr_frags;
 
-
-        if (hw->tx_pkt_filtering &&
-            (hw->mac_type == e1000_82573))
-                e1000_transfer_dhcp_info(adapter, skb);
-
         /* need: count + 2 desc gap to keep tail from touching
          * head, otherwise try next time */
         if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2)))
@@ -3374,7 +3022,9 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
         if (unlikely(hw->mac_type == e1000_82547)) {
                 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
                         netif_stop_queue(netdev);
-                        mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
+                        if (!test_bit(__E1000_DOWN, &adapter->flags))
+                                mod_timer(&adapter->tx_fifo_stall_timer,
+                                          jiffies + 1);
                         return NETDEV_TX_BUSY;
                 }
         }
@@ -3393,14 +3043,12 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
         }
 
         if (likely(tso)) {
-                tx_ring->last_tx_tso = 1;
+                if (likely(hw->mac_type != e1000_82544))
+                        tx_ring->last_tx_tso = 1;
                 tx_flags |= E1000_TX_FLAGS_TSO;
         } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
                 tx_flags |= E1000_TX_FLAGS_CSUM;
 
-        /* Old method was to assume IPv4 packet by default if TSO was enabled.
-         * 82571 hardware supports TSO capabilities for IPv6 as well...
-         * no longer assume, we must. */
         if (likely(skb->protocol == htons(ETH_P_IP)))
                 tx_flags |= E1000_TX_FLAGS_IPV4;
 
@@ -3472,7 +3120,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
         struct e1000_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
         int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
-        u16 eeprom_data = 0;
 
         if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
@@ -3483,44 +3130,23 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
         /* Adapter-specific max frame size limits. */
         switch (hw->mac_type) {
         case e1000_undefined ... e1000_82542_rev2_1:
-        case e1000_ich8lan:
                 if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
                         DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
                         return -EINVAL;
                 }
                 break;
-        case e1000_82573:
-                /* Jumbo Frames not supported if:
-                 * - this is not an 82573L device
-                 * - ASPM is enabled in any way (0x1A bits 3:2) */
-                e1000_read_eeprom(hw, EEPROM_INIT_3GIO_3, 1,
-                                  &eeprom_data);
-                if ((hw->device_id != E1000_DEV_ID_82573L) ||
-                    (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
-                        if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
-                                DPRINTK(PROBE, ERR,
-                                        "Jumbo Frames not supported.\n");
-                                return -EINVAL;
-                        }
-                        break;
-                }
-                /* ERT will be enabled later to enable wire speed receives */
-
-                /* fall through to get support */
-        case e1000_82571:
-        case e1000_82572:
-        case e1000_80003es2lan:
-#define MAX_STD_JUMBO_FRAME_SIZE 9234
-                if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
-                        DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
-                        return -EINVAL;
-                }
-                break;
         default:
                 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
                 break;
         }
 
+        while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
+                msleep(1);
+        /* e1000_down has a dependency on max_frame_size */
+        hw->max_frame_size = max_frame;
+        if (netif_running(netdev))
+                e1000_down(adapter);
+
         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
          * means we reserve 2 more, this pushes us to allocate from the next
          * larger slab size.
@@ -3549,11 +3175,16 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
 
+        printk(KERN_INFO "e1000: %s changing MTU from %d to %d\n",
+               netdev->name, netdev->mtu, new_mtu);
         netdev->mtu = new_mtu;
-        hw->max_frame_size = max_frame;
 
         if (netif_running(netdev))
-                e1000_reinit_locked(adapter);
+                e1000_up(adapter);
+        else
+                e1000_reset(adapter);
+
+        clear_bit(__E1000_RESETTING, &adapter->flags);
 
         return 0;
 }
@@ -3596,14 +3227,12 @@ void e1000_update_stats(struct e1000_adapter *adapter)
         adapter->stats.mprc += er32(MPRC);
         adapter->stats.roc += er32(ROC);
 
-        if (hw->mac_type != e1000_ich8lan) {
-                adapter->stats.prc64 += er32(PRC64);
-                adapter->stats.prc127 += er32(PRC127);
-                adapter->stats.prc255 += er32(PRC255);
-                adapter->stats.prc511 += er32(PRC511);
-                adapter->stats.prc1023 += er32(PRC1023);
-                adapter->stats.prc1522 += er32(PRC1522);
-        }
+        adapter->stats.prc64 += er32(PRC64);
+        adapter->stats.prc127 += er32(PRC127);
+        adapter->stats.prc255 += er32(PRC255);
+        adapter->stats.prc511 += er32(PRC511);
+        adapter->stats.prc1023 += er32(PRC1023);
+        adapter->stats.prc1522 += er32(PRC1522);
 
         adapter->stats.symerrs += er32(SYMERRS);
         adapter->stats.mpc += er32(MPC);
@@ -3632,14 +3261,12 @@ void e1000_update_stats(struct e1000_adapter *adapter)
         adapter->stats.toth += er32(TOTH);
         adapter->stats.tpr += er32(TPR);
 
-        if (hw->mac_type != e1000_ich8lan) {
-                adapter->stats.ptc64 += er32(PTC64);
-                adapter->stats.ptc127 += er32(PTC127);
-                adapter->stats.ptc255 += er32(PTC255);
-                adapter->stats.ptc511 += er32(PTC511);
-                adapter->stats.ptc1023 += er32(PTC1023);
-                adapter->stats.ptc1522 += er32(PTC1522);
-        }
+        adapter->stats.ptc64 += er32(PTC64);
+        adapter->stats.ptc127 += er32(PTC127);
+        adapter->stats.ptc255 += er32(PTC255);
+        adapter->stats.ptc511 += er32(PTC511);
+        adapter->stats.ptc1023 += er32(PTC1023);
+        adapter->stats.ptc1522 += er32(PTC1522);
 
         adapter->stats.mptc += er32(MPTC);
         adapter->stats.bptc += er32(BPTC);
@@ -3659,20 +3286,6 @@ void e1000_update_stats(struct e1000_adapter *adapter)
                 adapter->stats.tsctc += er32(TSCTC);
                 adapter->stats.tsctfc += er32(TSCTFC);
         }
-        if (hw->mac_type > e1000_82547_rev_2) {
-                adapter->stats.iac += er32(IAC);
-                adapter->stats.icrxoc += er32(ICRXOC);
-
-                if (hw->mac_type != e1000_ich8lan) {
-                        adapter->stats.icrxptc += er32(ICRXPTC);
-                        adapter->stats.icrxatc += er32(ICRXATC);
-                        adapter->stats.ictxptc += er32(ICTXPTC);
-                        adapter->stats.ictxatc += er32(ICTXATC);
-                        adapter->stats.ictxqec += er32(ICTXQEC);
-                        adapter->stats.ictxqmtc += er32(ICTXQMTC);
-                        adapter->stats.icrxdmtc += er32(ICRXDMTC);
-                }
-        }
 
         /* Fill out the OS statistics structure */
         adapter->net_stats.multicast = adapter->stats.mprc;
@@ -3731,49 +3344,6 @@ void e1000_update_stats(struct e1000_adapter *adapter)
 }
 
 /**
- * e1000_intr_msi - Interrupt Handler
- * @irq: interrupt number
- * @data: pointer to a network interface device structure
- **/
-
-static irqreturn_t e1000_intr_msi(int irq, void *data)
-{
-        struct net_device *netdev = data;
-        struct e1000_adapter *adapter = netdev_priv(netdev);
-        struct e1000_hw *hw = &adapter->hw;
-        u32 icr = er32(ICR);
-
-        /* in NAPI mode read ICR disables interrupts using IAM */
-
-        if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
-                hw->get_link_status = 1;
-                /* 80003ES2LAN workaround-- For packet buffer work-around on
-                 * link down event; disable receives here in the ISR and reset
-                 * adapter in watchdog */
-                if (netif_carrier_ok(netdev) &&
-                    (hw->mac_type == e1000_80003es2lan)) {
-                        /* disable receives */
-                        u32 rctl = er32(RCTL);
-                        ew32(RCTL, rctl & ~E1000_RCTL_EN);
-                }
-                /* guard against interrupt when we're going down */
-                if (!test_bit(__E1000_DOWN, &adapter->flags))
-                        mod_timer(&adapter->watchdog_timer, jiffies + 1);
-        }
-
-        if (likely(napi_schedule_prep(&adapter->napi))) {
-                adapter->total_tx_bytes = 0;
-                adapter->total_tx_packets = 0;
-                adapter->total_rx_bytes = 0;
-                adapter->total_rx_packets = 0;
-                __napi_schedule(&adapter->napi);
-        } else
-                e1000_irq_enable(adapter);
-
-        return IRQ_HANDLED;
-}
-
-/**
  * e1000_intr - Interrupt Handler
  * @irq: interrupt number
  * @data: pointer to a network interface device structure
@@ -3784,43 +3354,22 @@ static irqreturn_t e1000_intr(int irq, void *data)
         struct net_device *netdev = data;
         struct e1000_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
-        u32 rctl, icr = er32(ICR);
+        u32 icr = er32(ICR);
 
         if (unlikely((!icr) || test_bit(__E1000_DOWN, &adapter->flags)))
                 return IRQ_NONE;  /* Not our interrupt */
 
-        /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
-         * not set, then the adapter didn't send an interrupt */
-        if (unlikely(hw->mac_type >= e1000_82571 &&
-                     !(icr & E1000_ICR_INT_ASSERTED)))
-                return IRQ_NONE;
-
-        /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
-         * need for the IMC write */
-
         if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
                 hw->get_link_status = 1;
-                /* 80003ES2LAN workaround--
-                 * For packet buffer work-around on link down event;
-                 * disable receives here in the ISR and
-                 * reset adapter in watchdog
-                 */
-                if (netif_carrier_ok(netdev) &&
-                    (hw->mac_type == e1000_80003es2lan)) {
-                        /* disable receives */
-                        rctl = er32(RCTL);
-                        ew32(RCTL, rctl & ~E1000_RCTL_EN);
-                }
                 /* guard against interrupt when we're going down */
                 if (!test_bit(__E1000_DOWN, &adapter->flags))
                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
         }
 
-        if (unlikely(hw->mac_type < e1000_82571)) {
-                /* disable interrupts, without the synchronize_irq bit */
-                ew32(IMC, ~0);
-                E1000_WRITE_FLUSH();
-        }
+        /* disable interrupts, without the synchronize_irq bit */
+        ew32(IMC, ~0);
+        E1000_WRITE_FLUSH();
+
         if (likely(napi_schedule_prep(&adapter->napi))) {
                 adapter->total_tx_bytes = 0;
                 adapter->total_tx_packets = 0;
@@ -3844,17 +3393,13 @@ static irqreturn_t e1000_intr(int irq, void *data)
 static int e1000_clean(struct napi_struct *napi, int budget)
 {
         struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
-        struct net_device *poll_dev = adapter->netdev;
-        int tx_cleaned = 0, work_done = 0;
-
-        adapter = netdev_priv(poll_dev);
+        int tx_clean_complete = 0, work_done = 0;
 
-        tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[0]);
+        tx_clean_complete = e1000_clean_tx_irq(adapter, &adapter->tx_ring[0]);
 
-        adapter->clean_rx(adapter, &adapter->rx_ring[0],
-                          &work_done, budget);
+        adapter->clean_rx(adapter, &adapter->rx_ring[0], &work_done, budget);
 
-        if (!tx_cleaned)
+        if (!tx_clean_complete)
                 work_done = budget;
 
         /* If budget not fully consumed, exit the polling mode */
@@ -3925,7 +3470,9 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
                  * sees the new next_to_clean.
                  */
                 smp_mb();
-                if (netif_queue_stopped(netdev)) {
+
+                if (netif_queue_stopped(netdev) &&
+                    !(test_bit(__E1000_DOWN, &adapter->flags))) {
                         netif_wake_queue(netdev);
                         ++adapter->restart_queue;
                 }
@@ -3935,8 +3482,8 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
                 /* Detect a transmit hang in hardware, this serializes the
                  * check with the clearing of time_stamp and movement of i */
                 adapter->detect_tx_hung = false;
-                if (tx_ring->buffer_info[i].time_stamp &&
-                    time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
+                if (tx_ring->buffer_info[eop].time_stamp &&
+                    time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
                                (adapter->tx_timeout_factor * HZ))
                     && !(er32(STATUS) & E1000_STATUS_TXOFF)) {
 
@@ -3958,7 +3505,7 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
                                 readl(hw->hw_addr + tx_ring->tdt),
                                 tx_ring->next_to_use,
                                 tx_ring->next_to_clean,
-                                tx_ring->buffer_info[i].time_stamp,
+                                tx_ring->buffer_info[eop].time_stamp,
                                 eop,
                                 jiffies,
                                 eop_desc->upper.fields.status);
@@ -3999,25 +3546,13 @@ static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
                 return;
         }
         /* TCP/UDP Checksum has not been calculated */
-        if (hw->mac_type <= e1000_82547_rev_2) {
-                if (!(status & E1000_RXD_STAT_TCPCS))
-                        return;
-        } else {
-                if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
-                        return;
-        }
+        if (!(status & E1000_RXD_STAT_TCPCS))
+                return;
+
         /* It must be a TCP or UDP packet with a valid checksum */
         if (likely(status & E1000_RXD_STAT_TCPCS)) {
                 /* TCP checksum is good */
                 skb->ip_summed = CHECKSUM_UNNECESSARY;
-        } else if (hw->mac_type > e1000_82547_rev_2) {
-                /* IP fragment with UDP payload */
-                /* Hardware complements the payload checksum, so we undo it
-                 * and then put the value in host order for further stack use.
-                 */
-                __sum16 sum = (__force __sum16)htons(csum);
-                skb->csum = csum_unfold(~sum);
-                skb->ip_summed = CHECKSUM_COMPLETE;
         }
         adapter->hw_csum_good++;
 }
@@ -4814,20 +4349,6 @@ void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
         pcix_set_mmrbc(adapter->pdev, mmrbc);
 }
 
-s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
-{
-    struct e1000_adapter *adapter = hw->back;
-    u16 cap_offset;
-
-    cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
-    if (!cap_offset)
-        return -E1000_ERR_CONFIG;
-
-    pci_read_config_word(adapter->pdev, cap_offset + reg, value);
-
-    return E1000_SUCCESS;
-}
-
 void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value)
 {
         outl(value, port);
@@ -4850,33 +4371,27 @@ static void e1000_vlan_rx_register(struct net_device *netdev,
                 ctrl |= E1000_CTRL_VME;
                 ew32(CTRL, ctrl);
 
-                if (adapter->hw.mac_type != e1000_ich8lan) {
-                        /* enable VLAN receive filtering */
-                        rctl = er32(RCTL);
-                        rctl &= ~E1000_RCTL_CFIEN;
-                        if (!(netdev->flags & IFF_PROMISC))
-                                rctl |= E1000_RCTL_VFE;
-                        ew32(RCTL, rctl);
-                        e1000_update_mng_vlan(adapter);
-                }
+                /* enable VLAN receive filtering */
+                rctl = er32(RCTL);
+                rctl &= ~E1000_RCTL_CFIEN;
+                if (!(netdev->flags & IFF_PROMISC))
+                        rctl |= E1000_RCTL_VFE;
+                ew32(RCTL, rctl);
+                e1000_update_mng_vlan(adapter);
         } else {
                 /* disable VLAN tag insert/strip */
                 ctrl = er32(CTRL);
                 ctrl &= ~E1000_CTRL_VME;
                 ew32(CTRL, ctrl);
 
-                if (adapter->hw.mac_type != e1000_ich8lan) {
-                        /* disable VLAN receive filtering */
-                        rctl = er32(RCTL);
-                        rctl &= ~E1000_RCTL_VFE;
-                        ew32(RCTL, rctl);
+                /* disable VLAN receive filtering */
+                rctl = er32(RCTL);
+                rctl &= ~E1000_RCTL_VFE;
+                ew32(RCTL, rctl);
 
-                        if (adapter->mng_vlan_id !=
-                            (u16)E1000_MNG_VLAN_NONE) {
-                                e1000_vlan_rx_kill_vid(netdev,
-                                                       adapter->mng_vlan_id);
-                                adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
-                        }
+                if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
+                        e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
+                        adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
                 }
         }
 
@@ -4913,14 +4428,6 @@ static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
         if (!test_bit(__E1000_DOWN, &adapter->flags))
                 e1000_irq_enable(adapter);
 
-        if ((hw->mng_cookie.status &
-             E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
-            (vid == adapter->mng_vlan_id)) {
-                /* release control to f/w */
-                e1000_release_hw_control(adapter);
-                return;
-        }
-
         /* remove VID from filter table */
         index = (vid >> 5) & 0x7F;
         vfta = E1000_READ_REG_ARRAY(hw, VFTA, index);
@@ -5031,16 +4538,13 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
                 }
 
                 if (hw->media_type == e1000_media_type_fiber ||
-                   hw->media_type == e1000_media_type_internal_serdes) {
+                    hw->media_type == e1000_media_type_internal_serdes) {
                         /* keep the laser running in D3 */
                         ctrl_ext = er32(CTRL_EXT);
                         ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
                         ew32(CTRL_EXT, ctrl_ext);
                 }
 
-                /* Allow time for pending master requests to run */
-                e1000_disable_pciex_master(hw);
-
                 ew32(WUC, E1000_WUC_PME_EN);
                 ew32(WUFC, wufc);
         } else {
@@ -5056,16 +4560,9 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
         if (adapter->en_mng_pt)
                 *enable_wake = true;
 
-        if (hw->phy_type == e1000_phy_igp_3)
-                e1000_phy_powerdown_workaround(hw);
-
         if (netif_running(netdev))
                 e1000_free_irq(adapter);
 
-        /* Release control of h/w to f/w.  If f/w is AMT enabled, this
-         * would have already happened in close and is redundant. */
-        e1000_release_hw_control(adapter);
-
         pci_disable_device(pdev);
 
         return 0;
@@ -5131,14 +4628,6 @@ static int e1000_resume(struct pci_dev *pdev)
 
         netif_device_attach(netdev);
 
-        /* If the controller is 82573 and f/w is AMT, do not set
-         * DRV_LOAD until the interface is up.  For all other cases,
-         * let the f/w know that the h/w is now under the control
-         * of the driver. */
-        if (hw->mac_type != e1000_82573 ||
-            !e1000_check_mng_mode(hw))
-                e1000_get_hw_control(adapter);
-
         return 0;
 }
 #endif
@@ -5174,7 +4663,7 @@ static void e1000_netpoll(struct net_device *netdev)
 /**
  * e1000_io_error_detected - called when PCI error is detected
  * @pdev: Pointer to PCI device
- * @state: The current pci conneection state
+ * @state: The current pci connection state
  *
  * This function is called after a PCI bus error affecting
  * this device has been detected.
@@ -5243,7 +4732,6 @@ static void e1000_io_resume(struct pci_dev *pdev)
 {
         struct net_device *netdev = pci_get_drvdata(pdev);
         struct e1000_adapter *adapter = netdev_priv(netdev);
-        struct e1000_hw *hw = &adapter->hw;
 
         e1000_init_manageability(adapter);
 
@@ -5255,15 +4743,6 @@ static void e1000_io_resume(struct pci_dev *pdev)
         }
 
         netif_device_attach(netdev);
-
-        /* If the controller is 82573 and f/w is AMT, do not set
-         * DRV_LOAD until the interface is up.  For all other cases,
-         * let the f/w know that the h/w is now under the control
-         * of the driver. */
-        if (hw->mac_type != e1000_82573 ||
-            !e1000_check_mng_mode(hw))
-                e1000_get_hw_control(adapter);
-
 }
 
 /* e1000_main.c */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 213437d13154..38d2741ccae9 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -518,22 +518,6 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter)
                         adapter->smart_power_down = opt.def;
                 }
         }
-        { /* Kumeran Lock Loss Workaround */
-                opt = (struct e1000_option) {
-                        .type = enable_option,
-                        .name = "Kumeran Lock Loss Workaround",
-                        .err  = "defaulting to Enabled",
-                        .def  = OPTION_ENABLED
-                };
-
-                if (num_KumeranLockLoss > bd) {
-                        unsigned int kmrn_lock_loss = KumeranLockLoss[bd];
-                        e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
-                        adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
-                } else {
-                        adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def;
-                }
-        }
 
         switch (adapter->hw.media_type) {
         case e1000_media_type_fiber:
@@ -626,12 +610,6 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter)
                                          .p = dplx_list }}
                 };
 
-                if (e1000_check_phy_reset_block(&adapter->hw)) {
-                        DPRINTK(PROBE, INFO,
-                                "Link active due to SoL/IDER Session. "
-                                "Speed/Duplex/AutoNeg parameter ignored.\n");
-                        return;
-                }
                 if (num_Duplex > bd) {
                         dplx = Duplex[bd];
                         e1000_validate_option(&dplx, &opt, adapter);
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index a95caa014143..2716b91ba9fa 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -99,6 +99,8 @@ static struct iwl_lib_ops iwl1000_lib = {
         .setup_deferred_work = iwl5000_setup_deferred_work,
         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
         .load_ucode = iwl5000_load_ucode,
+        .dump_nic_event_log = iwl_dump_nic_event_log,
+        .dump_nic_error_log = iwl_dump_nic_error_log,
         .init_alive_start = iwl5000_init_alive_start,
         .alive_notify = iwl5000_alive_notify,
         .send_tx_power = iwl5000_send_tx_power,
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index e9a685d8e3a1..e70c5b0af364 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -2839,6 +2839,8 @@ static struct iwl_lib_ops iwl3945_lib = {
         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
         .txq_init = iwl3945_hw_tx_queue_init,
         .load_ucode = iwl3945_load_bsm,
+        .dump_nic_event_log = iwl3945_dump_nic_event_log,
+        .dump_nic_error_log = iwl3945_dump_nic_error_log,
         .apm_ops = {
                 .init = iwl3945_apm_init,
                 .reset = iwl3945_apm_reset,
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index f24036909916..21679bf3a1aa 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -209,6 +209,8 @@ extern int __must_check iwl3945_send_cmd(struct iwl_priv *priv,
                                          struct iwl_host_cmd *cmd);
 extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
                                         struct ieee80211_hdr *hdr,int left);
+extern void iwl3945_dump_nic_event_log(struct iwl_priv *priv);
+extern void iwl3945_dump_nic_error_log(struct iwl_priv *priv);
 
 /*
  * Currently used by iwl-3945-rs... look at restructuring so that it doesn't
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 3259b8841544..a22a0501c190 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -2298,6 +2298,8 @@ static struct iwl_lib_ops iwl4965_lib = {
         .alive_notify = iwl4965_alive_notify,
         .init_alive_start = iwl4965_init_alive_start,
         .load_ucode = iwl4965_load_bsm,
+        .dump_nic_event_log = iwl_dump_nic_event_log,
+        .dump_nic_error_log = iwl_dump_nic_error_log,
         .apm_ops = {
                 .init = iwl4965_apm_init,
                 .reset = iwl4965_apm_reset,
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index a6391c7fea53..eb08f4411000 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -1535,6 +1535,8 @@ struct iwl_lib_ops iwl5000_lib = {
         .rx_handler_setup = iwl5000_rx_handler_setup,
         .setup_deferred_work = iwl5000_setup_deferred_work,
         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
+        .dump_nic_event_log = iwl_dump_nic_event_log,
+        .dump_nic_error_log = iwl_dump_nic_error_log,
         .load_ucode = iwl5000_load_ucode,
         .init_alive_start = iwl5000_init_alive_start,
         .alive_notify = iwl5000_alive_notify,
@@ -1585,6 +1587,8 @@ static struct iwl_lib_ops iwl5150_lib = {
         .rx_handler_setup = iwl5000_rx_handler_setup,
         .setup_deferred_work = iwl5000_setup_deferred_work,
         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
+        .dump_nic_event_log = iwl_dump_nic_event_log,
+        .dump_nic_error_log = iwl_dump_nic_error_log,
         .load_ucode = iwl5000_load_ucode,
         .init_alive_start = iwl5000_init_alive_start,
         .alive_notify = iwl5000_alive_notify,
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 82b9c93dff54..c295b8ee9228 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -100,6 +100,8 @@ static struct iwl_lib_ops iwl6000_lib = {
         .setup_deferred_work = iwl5000_setup_deferred_work,
         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
         .load_ucode = iwl5000_load_ucode,
+        .dump_nic_event_log = iwl_dump_nic_event_log,
+        .dump_nic_error_log = iwl_dump_nic_error_log,
         .init_alive_start = iwl5000_init_alive_start,
         .alive_notify = iwl5000_alive_notify,
         .send_tx_power = iwl5000_send_tx_power,
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 00457bff1ed1..cdc07c477457 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -1526,6 +1526,191 @@ static int iwl_read_ucode(struct iwl_priv *priv)
         return ret;
 }
 
+#ifdef CONFIG_IWLWIFI_DEBUG
+static const char *desc_lookup_text[] = {
+        "OK",
+        "FAIL",
+        "BAD_PARAM",
+        "BAD_CHECKSUM",
+        "NMI_INTERRUPT_WDG",
+        "SYSASSERT",
+        "FATAL_ERROR",
+        "BAD_COMMAND",
+        "HW_ERROR_TUNE_LOCK",
+        "HW_ERROR_TEMPERATURE",
+        "ILLEGAL_CHAN_FREQ",
+        "VCC_NOT_STABLE",
+        "FH_ERROR",
+        "NMI_INTERRUPT_HOST",
+        "NMI_INTERRUPT_ACTION_PT",
+        "NMI_INTERRUPT_UNKNOWN",
+        "UCODE_VERSION_MISMATCH",
+        "HW_ERROR_ABS_LOCK",
+        "HW_ERROR_CAL_LOCK_FAIL",
+        "NMI_INTERRUPT_INST_ACTION_PT",
+        "NMI_INTERRUPT_DATA_ACTION_PT",
+        "NMI_TRM_HW_ER",
+        "NMI_INTERRUPT_TRM",
+        "NMI_INTERRUPT_BREAK_POINT"
+        "DEBUG_0",
+        "DEBUG_1",
+        "DEBUG_2",
+        "DEBUG_3",
+        "UNKNOWN"
+};
+
+static const char *desc_lookup(int i)
+{
+        int max = ARRAY_SIZE(desc_lookup_text) - 1;
+
+        if (i < 0 || i > max)
+                i = max;
+
+        return desc_lookup_text[i];
+}
+
+#define ERROR_START_OFFSET  (1 * sizeof(u32))
+#define ERROR_ELEM_SIZE     (7 * sizeof(u32))
+
+void iwl_dump_nic_error_log(struct iwl_priv *priv)
+{
+        u32 data2, line;
+        u32 desc, time, count, base, data1;
+        u32 blink1, blink2, ilink1, ilink2;
+
+        if (priv->ucode_type == UCODE_INIT)
+                base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
+        else
+                base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
+
+        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
+                IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
+                return;
+        }
+
+        count = iwl_read_targ_mem(priv, base);
+
+        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
+                IWL_ERR(priv, "Start IWL Error Log Dump:\n");
+                IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
+                        priv->status, count);
+        }
+
+        desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
+        blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
+        blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
+        ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
+        ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
+        data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
+        data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
+        line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
+        time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
+
+        IWL_ERR(priv, "Desc                               Time       "
+                "data1      data2      line\n");
+        IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
+                desc_lookup(desc), desc, time, data1, data2, line);
+        IWL_ERR(priv, "blink1  blink2  ilink1  ilink2\n");
+        IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
+                ilink1, ilink2);
+
+}
+
+#define EVENT_START_OFFSET  (4 * sizeof(u32))
+
+/**
+ * iwl_print_event_log - Dump error event log to syslog
+ *
+ */
+static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
+                                u32 num_events, u32 mode)
+{
+        u32 i;
+        u32 base;       /* SRAM byte address of event log header */
+        u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
+        u32 ptr;        /* SRAM byte address of log data */
+        u32 ev, time, data; /* event log data */
+
+        if (num_events == 0)
+                return;
+        if (priv->ucode_type == UCODE_INIT)
+                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
+        else
+                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
+
+        if (mode == 0)
+                event_size = 2 * sizeof(u32);
+        else
+                event_size = 3 * sizeof(u32);
+
+        ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
+
+        /* "time" is actually "data" for mode 0 (no timestamp).
+        * place event id # at far right for easier visual parsing. */
+        for (i = 0; i < num_events; i++) {
+                ev = iwl_read_targ_mem(priv, ptr);
+                ptr += sizeof(u32);
+                time = iwl_read_targ_mem(priv, ptr);
+                ptr += sizeof(u32);
+                if (mode == 0) {
+                        /* data, ev */
+                        IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
+                } else {
+                        data = iwl_read_targ_mem(priv, ptr);
+                        ptr += sizeof(u32);
+                        IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
+                                        time, data, ev);
+                }
+        }
+}
+
+void iwl_dump_nic_event_log(struct iwl_priv *priv)
+{
+        u32 base;       /* SRAM byte address of event log header */
+        u32 capacity;   /* event log capacity in # entries */
+        u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
+        u32 num_wraps;  /* # times uCode wrapped to top of log */
+        u32 next_entry; /* index of next entry to be written by uCode */
+        u32 size;       /* # entries that we'll print */
+
+        if (priv->ucode_type == UCODE_INIT)
+                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
+        else
+                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
+
+        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
+                IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
+                return;
+        }
+
+        /* event log header */
+        capacity = iwl_read_targ_mem(priv, base);
+        mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
+        num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
+        next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
+
+        size = num_wraps ? capacity : next_entry;
+
+        /* bail out if nothing in log */
+        if (size == 0) {
+                IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
+                return;
+        }
+
+        IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
+                        size, num_wraps);
+
+        /* if uCode has wrapped back to top of log, start at the oldest entry,
+         * i.e the next one that uCode would fill. */
+        if (num_wraps)
+                iwl_print_event_log(priv, next_entry,
+                                        capacity - next_entry, mode);
+        /* (then/else) start at top of log */
+        iwl_print_event_log(priv, 0, next_entry, mode);
+
+}
+#endif
+
 /**
  * iwl_alive_start - called after REPLY_ALIVE notification received
  *                   from protocol/runtime uCode (initialization uCode's
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index fd26c0dc9c54..484d5c1a7312 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -1309,189 +1309,6 @@ static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
         IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
         IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
 }
-
-static const char *desc_lookup_text[] = {
-        "OK",
-        "FAIL",
-        "BAD_PARAM",
-        "BAD_CHECKSUM",
-        "NMI_INTERRUPT_WDG",
-        "SYSASSERT",
-        "FATAL_ERROR",
-        "BAD_COMMAND",
-        "HW_ERROR_TUNE_LOCK",
-        "HW_ERROR_TEMPERATURE",
-        "ILLEGAL_CHAN_FREQ",
-        "VCC_NOT_STABLE",
-        "FH_ERROR",
-        "NMI_INTERRUPT_HOST",
-        "NMI_INTERRUPT_ACTION_PT",
-        "NMI_INTERRUPT_UNKNOWN",
-        "UCODE_VERSION_MISMATCH",
-        "HW_ERROR_ABS_LOCK",
-        "HW_ERROR_CAL_LOCK_FAIL",
-        "NMI_INTERRUPT_INST_ACTION_PT",
-        "NMI_INTERRUPT_DATA_ACTION_PT",
-        "NMI_TRM_HW_ER",
-        "NMI_INTERRUPT_TRM",
-        "NMI_INTERRUPT_BREAK_POINT"
-        "DEBUG_0",
-        "DEBUG_1",
-        "DEBUG_2",
-        "DEBUG_3",
-        "UNKNOWN"
-};
-
-static const char *desc_lookup(int i)
-{
-        int max = ARRAY_SIZE(desc_lookup_text) - 1;
-
-        if (i < 0 || i > max)
-                i = max;
-
-        return desc_lookup_text[i];
-}
-
-#define ERROR_START_OFFSET  (1 * sizeof(u32))
-#define ERROR_ELEM_SIZE     (7 * sizeof(u32))
-
-static void iwl_dump_nic_error_log(struct iwl_priv *priv)
-{
-        u32 data2, line;
-        u32 desc, time, count, base, data1;
-        u32 blink1, blink2, ilink1, ilink2;
-
-        if (priv->ucode_type == UCODE_INIT)
-                base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
-        else
-                base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
-
-        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
-                IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
-                return;
-        }
-
-        count = iwl_read_targ_mem(priv, base);
-
-        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
-                IWL_ERR(priv, "Start IWL Error Log Dump:\n");
-                IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
-                        priv->status, count);
-        }
-
-        desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
-        blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
-        blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
-        ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
-        ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
-        data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
-        data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
-        line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
-        time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
-
-        IWL_ERR(priv, "Desc                               Time       "
-                "data1      data2      line\n");
-        IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
-                desc_lookup(desc), desc, time, data1, data2, line);
-        IWL_ERR(priv, "blink1  blink2  ilink1  ilink2\n");
-        IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
-                ilink1, ilink2);
-
-}
-
-#define EVENT_START_OFFSET  (4 * sizeof(u32))
-
-/**
- * iwl_print_event_log - Dump error event log to syslog
- *
- */
-static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
-                                u32 num_events, u32 mode)
-{
-        u32 i;
-        u32 base;       /* SRAM byte address of event log header */
-        u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
-        u32 ptr;        /* SRAM byte address of log data */
-        u32 ev, time, data; /* event log data */
-
-        if (num_events == 0)
-                return;
-        if (priv->ucode_type == UCODE_INIT)
-                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
-        else
-                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
-
-        if (mode == 0)
-                event_size = 2 * sizeof(u32);
-        else
-                event_size = 3 * sizeof(u32);
-
-        ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
-
-        /* "time" is actually "data" for mode 0 (no timestamp).
-        * place event id # at far right for easier visual parsing. */
-        for (i = 0; i < num_events; i++) {
-                ev = iwl_read_targ_mem(priv, ptr);
-                ptr += sizeof(u32);
-                time = iwl_read_targ_mem(priv, ptr);
-                ptr += sizeof(u32);
-                if (mode == 0) {
-                        /* data, ev */
-                        IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
-                } else {
-                        data = iwl_read_targ_mem(priv, ptr);
-                        ptr += sizeof(u32);
-                        IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
-                                        time, data, ev);
-                }
-        }
-}
-
-void iwl_dump_nic_event_log(struct iwl_priv *priv)
-{
-        u32 base;       /* SRAM byte address of event log header */
-        u32 capacity;   /* event log capacity in # entries */
-        u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
-        u32 num_wraps;  /* # times uCode wrapped to top of log */
-        u32 next_entry; /* index of next entry to be written by uCode */
-        u32 size;       /* # entries that we'll print */
-
-        if (priv->ucode_type == UCODE_INIT)
-                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
-        else
-                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
-
-        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
-                IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
-                return;
-        }
-
-        /* event log header */
-        capacity = iwl_read_targ_mem(priv, base);
-        mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
-        num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
-        next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
-
-        size = num_wraps ? capacity : next_entry;
-
-        /* bail out if nothing in log */
-        if (size == 0) {
-                IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
-                return;
-        }
-
-        IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
-                        size, num_wraps);
-
-        /* if uCode has wrapped back to top of log, start at the oldest entry,
-         * i.e the next one that uCode would fill. */
-        if (num_wraps)
-                iwl_print_event_log(priv, next_entry,
-                                        capacity - next_entry, mode);
-        /* (then/else) start at top of log */
-        iwl_print_event_log(priv, 0, next_entry, mode);
-
-}
 #endif
 /**
  * iwl_irq_handle_error - called for HW or SW error interrupt from card
@@ -1506,8 +1323,8 @@ void iwl_irq_handle_error(struct iwl_priv *priv)
 
 #ifdef CONFIG_IWLWIFI_DEBUG
         if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
-                iwl_dump_nic_error_log(priv);
-                iwl_dump_nic_event_log(priv);
+                priv->cfg->ops->lib->dump_nic_error_log(priv);
+                priv->cfg->ops->lib->dump_nic_event_log(priv);
                 iwl_print_rx_config_cmd(priv);
         }
 #endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index 7ff9ffb2b702..e50103a956b1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -166,6 +166,8 @@ struct iwl_lib_ops {
         int (*is_valid_rtc_data_addr)(u32 addr);
         /* 1st ucode load */
         int (*load_ucode)(struct iwl_priv *priv);
+        void (*dump_nic_event_log)(struct iwl_priv *priv);
+        void (*dump_nic_error_log)(struct iwl_priv *priv);
         /* power management */
         struct iwl_apm_ops apm_ops;
 
@@ -540,7 +542,19 @@ int iwl_pci_resume(struct pci_dev *pdev);
 /*****************************************************
 *  Error Handling Debugging
 ******************************************************/
+#ifdef CONFIG_IWLWIFI_DEBUG
 void iwl_dump_nic_event_log(struct iwl_priv *priv);
+void iwl_dump_nic_error_log(struct iwl_priv *priv);
+#else
+static inline void iwl_dump_nic_event_log(struct iwl_priv *priv)
+{
+}
+
+static inline void iwl_dump_nic_error_log(struct iwl_priv *priv)
+{
+}
+#endif
+
 void iwl_clear_isr_stats(struct iwl_priv *priv);
 
 /*****************************************************
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index fb844859a443..a198bcf61022 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -410,7 +410,7 @@ static ssize_t iwl_dbgfs_nvm_read(struct file *file,
                 pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs);
                 hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos,
                                    buf_size - pos, 0);
-                pos += strlen(buf);
+                pos += strlen(buf + pos);
                 if (buf_size - pos > 0)
                         buf[pos++] = '\n';
         }
@@ -436,7 +436,7 @@ static ssize_t iwl_dbgfs_log_event_write(struct file *file,
         if (sscanf(buf, "%d", &event_log_flag) != 1)
                 return -EFAULT;
         if (event_log_flag == 1)
-                iwl_dump_nic_event_log(priv);
+                priv->cfg->ops->lib->dump_nic_event_log(priv);
 
         return count;
 }
@@ -909,7 +909,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
                                                 "0x%.4x ", ofs);
                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
                                                    buf + pos, bufsz - pos, 0);
-                                pos += strlen(buf);
+                                pos += strlen(buf + pos);
                                 if (bufsz - pos > 0)
                                         buf[pos++] = '\n';
                         }
@@ -932,7 +932,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
                                                 "0x%.4x ", ofs);
                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
                                                    buf + pos, bufsz - pos, 0);
-                                pos += strlen(buf);
+                                pos += strlen(buf + pos);
                                 if (bufsz - pos > 0)
                                         buf[pos++] = '\n';
                         }
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index a7422e52d883..c18907544701 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -197,6 +197,12 @@ void iwl_cmd_queue_free(struct iwl_priv *priv)
                 pci_free_consistent(dev, priv->hw_params.tfd_size *
                                     txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 
+        /* deallocate arrays */
+        kfree(txq->cmd);
+        kfree(txq->meta);
+        txq->cmd = NULL;
+        txq->meta = NULL;
+
         /* 0-fill queue descriptor structure */
         memset(txq, 0, sizeof(*txq));
 }
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 4f2d43937283..c390dbd877e4 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -1481,6 +1481,7 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv)
         tasklet_kill(&priv->irq_tasklet);
 }
 
+#ifdef CONFIG_IWLWIFI_DEBUG
 static const char *desc_lookup(int i)
 {
         switch (i) {
@@ -1504,7 +1505,7 @@ static const char *desc_lookup(int i)
 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 
-static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
+void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
 {
         u32 i;
         u32 desc, time, count, base, data1;
@@ -1598,7 +1599,7 @@ static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
         }
 }
 
-static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
+void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
 {
         u32 base;       /* SRAM byte address of event log header */
         u32 capacity;   /* event log capacity in # entries */
@@ -1640,6 +1641,16 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
         iwl3945_print_event_log(priv, 0, next_entry, mode);
 
 }
+#else
+void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
+{
+}
+
+void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
+{
+}
+
+#endif
 
 static void iwl3945_irq_tasklet(struct iwl_priv *priv)
 {
@@ -3683,21 +3694,6 @@ static ssize_t dump_error_log(struct device *d,
 
 static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
 
-static ssize_t dump_event_log(struct device *d,
-                              struct device_attribute *attr,
-                              const char *buf, size_t count)
-{
-        struct iwl_priv *priv = dev_get_drvdata(d);
-        char *p = (char *)buf;
-
-        if (p[0] == '1')
-                iwl3945_dump_nic_event_log(priv);
-
-        return strnlen(buf, count);
-}
-
-static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
-
 /*****************************************************************************
  *
  * driver setup and tear down
@@ -3742,7 +3738,6 @@ static struct attribute *iwl3945_sysfs_entries[] = {
         &dev_attr_antenna.attr,
         &dev_attr_channels.attr,
         &dev_attr_dump_errors.attr,
-        &dev_attr_dump_events.attr,
         &dev_attr_flags.attr,
         &dev_attr_filter_flags.attr,
 #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c
index f9f68e0e7344..afdbdaaf80cb 100644
--- a/drivers/platform/x86/sony-laptop.c
+++ b/drivers/platform/x86/sony-laptop.c
@@ -1041,6 +1041,9 @@ static int sony_nc_resume(struct acpi_device *device)
                         sony_backlight_update_status(sony_backlight_device) < 0)
                 printk(KERN_WARNING DRV_PFX "unable to restore brightness level\n");
 
+        /* re-read rfkill state */
+        sony_nc_rfkill_update();
+
         return 0;
 }
 
@@ -1078,6 +1081,8 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
         struct rfkill *rfk;
         enum rfkill_type type;
         const char *name;
+        int result;
+        bool hwblock;
 
         switch (nc_type) {
         case SONY_WIFI:
@@ -1105,6 +1110,10 @@ static int sony_nc_setup_rfkill(struct acpi_device *device,
         if (!rfk)
                 return -ENOMEM;
 
+        sony_call_snc_handle(0x124, 0x200, &result);
+        hwblock = !(result & 0x1);
+        rfkill_set_hw_state(rfk, hwblock);
+
         err = rfkill_register(rfk);
         if (err) {
                 rfkill_destroy(rfk);
diff --git a/include/linux/if_tunnel.h b/include/linux/if_tunnel.h
index 5eb9b0f857e0..5a9aae4adb44 100644
--- a/include/linux/if_tunnel.h
+++ b/include/linux/if_tunnel.h
@@ -44,7 +44,7 @@ struct ip_tunnel_prl {
         __u16                   flags;
         __u16                   __reserved;
         __u32                   datalen;
-        __u32                   rs_delay;
+        __u32                   __reserved2;
         /* data follows */
 };
 
diff --git a/include/net/ipip.h b/include/net/ipip.h
index 76e3ea6e2fe5..87acf8f3a155 100644
--- a/include/net/ipip.h
+++ b/include/net/ipip.h
@@ -27,18 +27,11 @@ struct ip_tunnel
         unsigned int                    prl_count;      /* # of entries in PRL */
 };
 
-/* ISATAP: default interval between RS in secondy */
-#define IPTUNNEL_RS_DEFAULT_DELAY       (900)
-
 struct ip_tunnel_prl_entry
 {
         struct ip_tunnel_prl_entry      *next;
         __be32                          addr;
         u16                             flags;
-        unsigned long                   rs_delay;
-        struct timer_list               rs_timer;
-        struct ip_tunnel                *tunnel;
-        spinlock_t                      lock;
 };
 
 #define IPTUNNEL_XMIT() do {                                            \
diff --git a/include/net/wext.h b/include/net/wext.h
index 6d76a39a9c5b..3f2b94de2cfa 100644
--- a/include/net/wext.h
+++ b/include/net/wext.h
@@ -14,6 +14,7 @@ extern int wext_handle_ioctl(struct net *net, struct ifreq *ifr, unsigned int cm
                              void __user *arg);
 extern int compat_wext_handle_ioctl(struct net *net, unsigned int cmd,
                                     unsigned long arg);
+extern struct iw_statistics *get_wireless_stats(struct net_device *dev);
 #else
 static inline int wext_proc_init(struct net *net)
 {
diff --git a/net/8021q/vlan_netlink.c b/net/8021q/vlan_netlink.c
index 343146e1bceb..a91504850195 100644
--- a/net/8021q/vlan_netlink.c
+++ b/net/8021q/vlan_netlink.c
@@ -169,6 +169,7 @@ static size_t vlan_get_size(const struct net_device *dev)
         struct vlan_dev_info *vlan = vlan_dev_info(dev);
 
         return nla_total_size(2) +      /* IFLA_VLAN_ID */
+               sizeof(struct ifla_vlan_flags) + /* IFLA_VLAN_FLAGS */
                vlan_qos_map_size(vlan->nr_ingress_mappings) +
                vlan_qos_map_size(vlan->nr_egress_mappings);
 }
diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c
index fbcac76fdc0d..4102de1022ee 100644
--- a/net/ax25/af_ax25.c
+++ b/net/ax25/af_ax25.c
@@ -641,15 +641,10 @@ static int ax25_setsockopt(struct socket *sock, int level, int optname,
 
         case SO_BINDTODEVICE:
                 if (optlen > IFNAMSIZ)
-                        optlen=IFNAMSIZ;
-                if (copy_from_user(devname, optval, optlen)) {
-                res = -EFAULT;
-                        break;
-                }
+                        optlen = IFNAMSIZ;
 
-                dev = dev_get_by_name(&init_net, devname);
-                if (dev == NULL) {
-                        res = -ENODEV;
+                if (copy_from_user(devname, optval, optlen)) {
+                        res = -EFAULT;
                         break;
                 }
 
@@ -657,12 +652,18 @@ static int ax25_setsockopt(struct socket *sock, int level, int optname,
                    (sock->state != SS_UNCONNECTED ||
                     sk->sk_state == TCP_LISTEN)) {
                         res = -EADDRNOTAVAIL;
-                        dev_put(dev);
+                        break;
+                }
+
+                dev = dev_get_by_name(&init_net, devname);
+                if (!dev) {
+                        res = -ENODEV;
                         break;
                 }
 
                 ax25->ax25_dev = ax25_dev_ax25dev(dev);
                 ax25_fillin_cb(ax25, ax25->ax25_dev);
+                dev_put(dev);
                 break;
 
         default:
diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c
index 142ebac14176..b1b3b0fbf41c 100644
--- a/net/bridge/br_if.c
+++ b/net/bridge/br_if.c
@@ -432,6 +432,7 @@ err2:
         br_fdb_delete_by_port(br, p, 1);
 err1:
         kobject_put(&p->kobj);
+        p = NULL; /* kobject_put frees */
 err0:
         dev_set_promiscuity(dev, -1);
 put_back:
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c
index 7d4c57523b09..821d30918cfc 100644
--- a/net/core/net-sysfs.c
+++ b/net/core/net-sysfs.c
@@ -16,7 +16,7 @@
 #include <net/sock.h>
 #include <linux/rtnetlink.h>
 #include <linux/wireless.h>
-#include <net/iw_handler.h>
+#include <net/wext.h>
 
 #include "net-sysfs.h"
 
@@ -363,15 +363,13 @@ static ssize_t wireless_show(struct device *d, char *buf,
                                                char *))
 {
         struct net_device *dev = to_net_dev(d);
-        const struct iw_statistics *iw = NULL;
+        const struct iw_statistics *iw;
         ssize_t ret = -EINVAL;
 
         read_lock(&dev_base_lock);
         if (dev_isalive(dev)) {
-                if (dev->wireless_handlers &&
-                    dev->wireless_handlers->get_wireless_stats)
-                        iw = dev->wireless_handlers->get_wireless_stats(dev);
-                if (iw != NULL)
+                iw = get_wireless_stats(dev);
+                if (iw)
                         ret = (*format)(iw, buf);
         }
         read_unlock(&dev_base_lock);
@@ -505,7 +503,7 @@ int netdev_register_kobject(struct net_device *net)
         *groups++ = &netstat_group;
 
 #ifdef CONFIG_WIRELESS_EXT_SYSFS
-        if (net->wireless_handlers && net->wireless_handlers->get_wireless_stats)
+        if (net->wireless_handlers || net->ieee80211_ptr)
                 *groups++ = &wireless_group;
 #endif
 #endif /* CONFIG_SYSFS */
diff --git a/net/dcb/dcbnl.c b/net/dcb/dcbnl.c
index e0879bfb7dd5..ac1205df6c86 100644
--- a/net/dcb/dcbnl.c
+++ b/net/dcb/dcbnl.c
@@ -194,7 +194,7 @@ static int dcbnl_reply(u8 value, u8 event, u8 cmd, u8 attr, u32 pid,
         nlmsg_end(dcbnl_skb, nlh);
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                return -EINVAL;
 
         return 0;
 nlmsg_failure:
@@ -275,7 +275,7 @@ static int dcbnl_getpfccfg(struct net_device *netdev, struct nlattr **tb,
 
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                goto err_out;
 
         return 0;
 nlmsg_failure:
@@ -316,12 +316,11 @@ static int dcbnl_getperm_hwaddr(struct net_device *netdev, struct nlattr **tb,
 
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                goto err_out;
 
         return 0;
 
 nlmsg_failure:
-err:
         kfree_skb(dcbnl_skb);
 err_out:
         return -EINVAL;
@@ -383,7 +382,7 @@ static int dcbnl_getcap(struct net_device *netdev, struct nlattr **tb,
 
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                goto err_out;
 
         return 0;
 nlmsg_failure:
@@ -460,7 +459,7 @@ static int dcbnl_getnumtcs(struct net_device *netdev, struct nlattr **tb,
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret) {
                 ret = -EINVAL;
-                goto err;
+                goto err_out;
         }
 
         return 0;
@@ -799,7 +798,7 @@ static int __dcbnl_pg_getcfg(struct net_device *netdev, struct nlattr **tb,
 
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                goto err_out;
 
         return 0;
 
@@ -1063,7 +1062,7 @@ static int dcbnl_bcn_getcfg(struct net_device *netdev, struct nlattr **tb,
 
         ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
         if (ret)
-                goto err;
+                goto err_out;
 
         return 0;
 
diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
index 498b9b0b0fad..f74e4e2cdd06 100644
--- a/net/ipv6/ndisc.c
+++ b/net/ipv6/ndisc.c
@@ -658,7 +658,6 @@ void ndisc_send_rs(struct net_device *dev, const struct in6_addr *saddr,
                      &icmp6h, NULL,
                      send_sllao ? ND_OPT_SOURCE_LL_ADDR : 0);
 }
-EXPORT_SYMBOL(ndisc_send_rs);
 
 
 static void ndisc_error_report(struct neighbour *neigh, struct sk_buff *skb)
diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
index fcb539628847..d65e0c496cc0 100644
--- a/net/ipv6/sit.c
+++ b/net/ipv6/sit.c
@@ -15,7 +15,6 @@
  * Roger Venning <r.venning@telstra.com>:       6to4 support
  * Nate Thompson <nate@thebog.net>:             6to4 support
  * Fred Templin <fred.l.templin@boeing.com>:    isatap support
- * Sascha Hlusiak <mail@saschahlusiak.de>:      stateless autoconf for isatap
  */
 
 #include <linux/module.h>
@@ -223,44 +222,6 @@ failed:
         return NULL;
 }
 
-static void ipip6_tunnel_rs_timer(unsigned long data)
-{
-        struct ip_tunnel_prl_entry *p = (struct ip_tunnel_prl_entry *) data;
-        struct inet6_dev *ifp;
-        struct inet6_ifaddr *addr;
-
-        spin_lock(&p->lock);
-        ifp = __in6_dev_get(p->tunnel->dev);
-
-        read_lock_bh(&ifp->lock);
-        for (addr = ifp->addr_list; addr; addr = addr->if_next) {
-                struct in6_addr rtr;
-
-                if (!(ipv6_addr_type(&addr->addr) & IPV6_ADDR_LINKLOCAL))
-                        continue;
-
-                /* Send RS to guessed linklocal address of router
-                 *
-                 * Better: send to ff02::2 encapsuled in unicast directly
-                 * to router-v4 instead of guessing the v6 address.
-                 *
-                 * Cisco/Windows seem to not set the u/l bit correctly,
-                 * so we won't guess right.
-                 */
-                ipv6_addr_set(&rtr,  htonl(0xFE800000), 0, 0, 0);
-                if (!__ipv6_isatap_ifid(rtr.s6_addr + 8,
-                                        p->addr)) {
-                        ndisc_send_rs(p->tunnel->dev, &addr->addr, &rtr);
-                }
-        }
-        read_unlock_bh(&ifp->lock);
-
-        mod_timer(&p->rs_timer, jiffies + HZ * p->rs_delay);
-        spin_unlock(&p->lock);
-
-        return;
-}
-
 static struct ip_tunnel_prl_entry *
 __ipip6_tunnel_locate_prl(struct ip_tunnel *t, __be32 addr)
 {
@@ -319,7 +280,6 @@ static int ipip6_tunnel_get_prl(struct ip_tunnel *t,
                         continue;
                 kp[c].addr = prl->addr;
                 kp[c].flags = prl->flags;
-                kp[c].rs_delay = prl->rs_delay;
                 c++;
                 if (kprl.addr != htonl(INADDR_ANY))
                         break;
@@ -369,23 +329,11 @@ ipip6_tunnel_add_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a, int chg)
         }
 
         p->next = t->prl;
-        p->tunnel = t;
         t->prl = p;
         t->prl_count++;
-
-        spin_lock_init(&p->lock);
-        setup_timer(&p->rs_timer, ipip6_tunnel_rs_timer, (unsigned long) p);
 update:
         p->addr = a->addr;
         p->flags = a->flags;
-        p->rs_delay = a->rs_delay;
-        if (p->rs_delay == 0)
-                p->rs_delay = IPTUNNEL_RS_DEFAULT_DELAY;
-        spin_lock(&p->lock);
-        del_timer(&p->rs_timer);
-        if (p->flags & PRL_DEFAULT)
-                mod_timer(&p->rs_timer, jiffies + 1);
-        spin_unlock(&p->lock);
 out:
         write_unlock(&ipip6_lock);
         return err;
@@ -404,9 +352,6 @@ ipip6_tunnel_del_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a)
                         if ((*p)->addr == a->addr) {
                                 x = *p;
                                 *p = x->next;
-                                spin_lock(&x->lock);
-                                del_timer(&x->rs_timer);
-                                spin_unlock(&x->lock);
                                 kfree(x);
                                 t->prl_count--;
                                 goto out;
@@ -417,9 +362,6 @@ ipip6_tunnel_del_prl(struct ip_tunnel *t, struct ip_tunnel_prl *a)
                 while (t->prl) {
                         x = t->prl;
                         t->prl = t->prl->next;
-                        spin_lock(&x->lock);
-                        del_timer(&x->rs_timer);
-                        spin_unlock(&x->lock);
                         kfree(x);
                         t->prl_count--;
                 }
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 97a278a2f48e..8d26e9bf8964 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -1388,8 +1388,8 @@ ieee80211_rx_mgmt_disassoc(struct ieee80211_sub_if_data *sdata,
 
         reason_code = le16_to_cpu(mgmt->u.disassoc.reason_code);
 
-        printk(KERN_DEBUG "%s: disassociated (Reason: %u)\n",
-                        sdata->dev->name, reason_code);
+        printk(KERN_DEBUG "%s: disassociated from %pM (Reason: %u)\n",
+                        sdata->dev->name, mgmt->sa, reason_code);
 
         ieee80211_set_disassoc(sdata, false);
         return RX_MGMT_CFG80211_DISASSOC;
@@ -1675,7 +1675,7 @@ static void ieee80211_rx_mgmt_probe_resp(struct ieee80211_sub_if_data *sdata,
 
         /* direct probe may be part of the association flow */
         if (wk && wk->state == IEEE80211_MGD_STATE_PROBE) {
-                printk(KERN_DEBUG "%s direct probe responded\n",
+                printk(KERN_DEBUG "%s: direct probe responded\n",
                        sdata->dev->name);
                 wk->tries = 0;
                 wk->state = IEEE80211_MGD_STATE_AUTH;
@@ -2502,9 +2502,6 @@ int ieee80211_mgd_deauth(struct ieee80211_sub_if_data *sdata,
         struct ieee80211_mgd_work *wk;
         const u8 *bssid = NULL;
 
-        printk(KERN_DEBUG "%s: deauthenticating by local choice (reason=%d)\n",
-               sdata->dev->name, req->reason_code);
-
         mutex_lock(&ifmgd->mtx);
 
         if (ifmgd->associated && &ifmgd->associated->cbss == req->bss) {
@@ -2532,6 +2529,9 @@ int ieee80211_mgd_deauth(struct ieee80211_sub_if_data *sdata,
 
         mutex_unlock(&ifmgd->mtx);
 
+        printk(KERN_DEBUG "%s: deauthenticating from %pM by local choice (reason=%d)\n",
+               sdata->dev->name, bssid, req->reason_code);
+
         ieee80211_send_deauth_disassoc(sdata, bssid,
                         IEEE80211_STYPE_DEAUTH, req->reason_code,
                         cookie);
@@ -2545,9 +2545,6 @@ int ieee80211_mgd_disassoc(struct ieee80211_sub_if_data *sdata,
 {
         struct ieee80211_if_managed *ifmgd = &sdata->u.mgd;
 
-        printk(KERN_DEBUG "%s: disassociating by local choice (reason=%d)\n",
-               sdata->dev->name, req->reason_code);
-
         mutex_lock(&ifmgd->mtx);
 
         /*
@@ -2561,6 +2558,9 @@ int ieee80211_mgd_disassoc(struct ieee80211_sub_if_data *sdata,
                 return -ENOLINK;
         }
 
+        printk(KERN_DEBUG "%s: disassociating from %pM by local choice (reason=%d)\n",
+               sdata->dev->name, req->bss->bssid, req->reason_code);
+
         ieee80211_set_disassoc(sdata, false);
 
         mutex_unlock(&ifmgd->mtx);
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
index a4bafbf15097..dd85320907cb 100644
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
@@ -1788,7 +1788,7 @@ void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err)
         }
 
         rep = __nlmsg_put(skb, NETLINK_CB(in_skb).pid, nlh->nlmsg_seq,
-                          NLMSG_ERROR, sizeof(struct nlmsgerr), 0);
+                          NLMSG_ERROR, payload, 0);
         errmsg = nlmsg_data(rep);
         errmsg->error = err;
         memcpy(&errmsg->msg, nlh, err ? nlh->nlmsg_len : sizeof(*nlh));
diff --git a/net/socket.c b/net/socket.c
index 49917a1cac7d..41e8847508aa 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -2098,12 +2098,17 @@ SYSCALL_DEFINE2(socketcall, int, call, unsigned long __user *, args)
         unsigned long a[6];
         unsigned long a0, a1;
         int err;
+        unsigned int len;
 
         if (call < 1 || call > SYS_ACCEPT4)
                 return -EINVAL;
 
+        len = nargs[call];
+        if (len > sizeof(a))
+                return -EINVAL;
+
         /* copy_from_user should be SMP safe. */
-        if (copy_from_user(a, args, nargs[call]))
+        if (copy_from_user(a, args, len))
                 return -EFAULT;
 
         audit_socketcall(nargs[call] / sizeof(unsigned long), a);
diff --git a/net/wireless/sme.c b/net/wireless/sme.c
index 7fae7eee65de..93c3ed329204 100644
--- a/net/wireless/sme.c
+++ b/net/wireless/sme.c
@@ -762,9 +762,8 @@ int __cfg80211_connect(struct cfg80211_registered_device *rdev,
                 wdev->conn->params.ssid = wdev->ssid;
                 wdev->conn->params.ssid_len = connect->ssid_len;
 
-                /* don't care about result -- but fill bssid & channel */
-                if (!wdev->conn->params.bssid || !wdev->conn->params.channel)
-                        bss = cfg80211_get_conn_bss(wdev);
+                /* see if we have the bss already */
+                bss = cfg80211_get_conn_bss(wdev);
 
                 wdev->sme_state = CFG80211_SME_CONNECTING;
                 wdev->connect_keys = connkeys;
diff --git a/net/wireless/wext-sme.c b/net/wireless/wext-sme.c
index bf725275eb8d..5615a8802536 100644
--- a/net/wireless/wext-sme.c
+++ b/net/wireless/wext-sme.c
@@ -30,7 +30,8 @@ int cfg80211_mgd_wext_connect(struct cfg80211_registered_device *rdev,
         if (wdev->wext.keys) {
                 wdev->wext.keys->def = wdev->wext.default_key;
                 wdev->wext.keys->defmgmt = wdev->wext.default_mgmt_key;
-                wdev->wext.connect.privacy = true;
+                if (wdev->wext.default_key != -1)
+                        wdev->wext.connect.privacy = true;
         }
 
         if (!wdev->wext.connect.ssid_len)
@@ -229,8 +230,7 @@ int cfg80211_mgd_wext_giwessid(struct net_device *dev,
                 data->flags = 1;
                 data->length = wdev->wext.connect.ssid_len;
                 memcpy(ssid, wdev->wext.connect.ssid, data->length);
-        } else
-                data->flags = 0;
+        }
         wdev_unlock(wdev);
 
         return 0;
@@ -306,8 +306,6 @@ int cfg80211_mgd_wext_giwap(struct net_device *dev,
         wdev_lock(wdev);
         if (wdev->current_bss)
                 memcpy(ap_addr->sa_data, wdev->current_bss->pub.bssid, ETH_ALEN);
-        else if (wdev->wext.connect.bssid)
-                memcpy(ap_addr->sa_data, wdev->wext.connect.bssid, ETH_ALEN);
         else
                 memset(ap_addr->sa_data, 0, ETH_ALEN);
         wdev_unlock(wdev);
diff --git a/net/wireless/wext.c b/net/wireless/wext.c
index 5b4a0cee4418..60fe57761ca9 100644
--- a/net/wireless/wext.c
+++ b/net/wireless/wext.c
@@ -470,7 +470,7 @@ static iw_handler get_handler(struct net_device *dev, unsigned int cmd)
 /*
  * Get statistics out of the driver
  */
-static struct iw_statistics *get_wireless_stats(struct net_device *dev)
+struct iw_statistics *get_wireless_stats(struct net_device *dev)
 {
         /* New location */
         if ((dev->wireless_handlers != NULL) &&
@@ -773,10 +773,13 @@ static int ioctl_standard_iw_point(struct iw_point *iwp, unsigned int cmd,
                         essid_compat = 1;
                 else if (IW_IS_SET(cmd) && (iwp->length != 0)) {
                         char essid[IW_ESSID_MAX_SIZE + 1];
+                        unsigned int len;
+                        len = iwp->length * descr->token_size;
 
-                        err = copy_from_user(essid, iwp->pointer,
-                                             iwp->length *
-                                             descr->token_size);
+                        if (len > IW_ESSID_MAX_SIZE)
+                                return -EFAULT;
+
+                        err = copy_from_user(essid, iwp->pointer, len);
                         if (err)
                                 return -EFAULT;