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-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c140
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h2
-rw-r--r--arch/sh/boards/board-magicpanelr2.c34
-rw-r--r--arch/sh/boards/board-sh7757lcr.c39
-rw-r--r--arch/sh/boards/mach-ap325rxa/setup.c12
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c36
-rw-r--r--arch/sh/boards/mach-kfr2r09/setup.c12
-rw-r--r--arch/sh/boards/mach-migor/setup.c12
-rw-r--r--arch/sh/boards/mach-rsk/setup.c43
-rw-r--r--arch/sh/boards/mach-se/7722/setup.c3
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c30
-rw-r--r--arch/sh/include/asm/device.h10
-rw-r--r--arch/sh/include/asm/hwblk.h70
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7722.h13
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7723.h3
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h4
-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/hwblk.c159
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c77
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c209
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c201
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c106
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c38
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c64
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c7
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile1
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c3
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c319
-rw-r--r--arch/sh/kernel/entry-common.S1
-rw-r--r--arch/sh/kernel/signal_32.c4
-rw-r--r--arch/sh/kernel/signal_64.c4
-rw-r--r--arch/sh/kernel/time.c2
-rw-r--r--arch/sh/mm/cache-sh2a.c123
-rw-r--r--drivers/sh/Makefile9
-rw-r--r--drivers/sh/clk/core.c9
-rw-r--r--drivers/sh/clk/cpg.c79
-rw-r--r--drivers/sh/pfc.c137
-rw-r--r--drivers/tty/serial/sh-sci.c183
-rw-r--r--include/linux/serial_sci.h22
-rw-r--r--include/linux/sh_clk.h10
-rw-r--r--include/linux/sh_pfc.h11
51 files changed, 897 insertions, 1651 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 995a9c3aec8f..e349c22a0d71 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = {
411}; 411};
412 412
413static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 413static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
414 [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, 414 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
415 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), 415 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
416 [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0, 416 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
417 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2), 417 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
418 [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0, 418 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
419 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), 419 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
420}; 420};
421 421
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 1370a89ca358..34944d01bf1e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
92 .recalc = div2_recalc, 92 .recalc = div2_recalc,
93}; 93};
94 94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
95/* Divide extal1 by two */ 113/* Divide extal1 by two */
96static struct clk extal1_div2_clk = { 114static struct clk extal1_div2_clk = {
97 .ops = &div2_clk_ops, 115 .ops = &div2_clk_ops,
@@ -174,12 +192,29 @@ static struct clk pll3_clk = {
174 .enable_bit = 3, 192 .enable_bit = 3,
175}; 193};
176 194
177/* Divide PLL1 by two */ 195/* Divide PLL */
178static struct clk pll1_div2_clk = { 196static struct clk pll1_div2_clk = {
179 .ops = &div2_clk_ops, 197 .ops = &div2_clk_ops,
180 .parent = &pll1_clk, 198 .parent = &pll1_clk,
181}; 199};
182 200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205
206static struct clk pll1_div13_clk = {
207 .ops = &div13_clk_ops,
208 .parent = &pll1_clk,
209};
210
211/* External input clock */
212struct clk sh73a0_extcki_clk = {
213};
214
215struct clk sh73a0_extalr_clk = {
216};
217
183static struct clk *main_clks[] = { 218static struct clk *main_clks[] = {
184 &r_clk, 219 &r_clk,
185 &sh73a0_extal1_clk, 220 &sh73a0_extal1_clk,
@@ -193,6 +228,10 @@ static struct clk *main_clks[] = {
193 &pll2_clk, 228 &pll2_clk,
194 &pll3_clk, 229 &pll3_clk,
195 &pll1_div2_clk, 230 &pll1_div2_clk,
231 &pll1_div7_clk,
232 &pll1_div13_clk,
233 &sh73a0_extcki_clk,
234 &sh73a0_extalr_clk,
196}; 235};
197 236
198static void div4_kick(struct clk *clk) 237static void div4_kick(struct clk *clk)
@@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
246 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, 285 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
247 DIV6_NR }; 286 DIV6_NR };
248 287
288static struct clk *vck_parent[8] = {
289 [0] = &pll1_div2_clk,
290 [1] = &pll2_clk,
291 [2] = &sh73a0_extcki_clk,
292 [3] = &sh73a0_extal2_clk,
293 [4] = &main_div2_clk,
294 [5] = &sh73a0_extalr_clk,
295 [6] = &main_clk,
296};
297
298static struct clk *pll_parent[4] = {
299 [0] = &pll1_div2_clk,
300 [1] = &pll2_clk,
301 [2] = &pll1_div13_clk,
302};
303
304static struct clk *hsi_parent[4] = {
305 [0] = &pll1_div2_clk,
306 [1] = &pll2_clk,
307 [2] = &pll1_div7_clk,
308};
309
310static struct clk *pll_extal2_parent[] = {
311 [0] = &pll1_div2_clk,
312 [1] = &pll2_clk,
313 [2] = &sh73a0_extal2_clk,
314 [3] = &sh73a0_extal2_clk,
315};
316
317static struct clk *dsi_parent[8] = {
318 [0] = &pll1_div2_clk,
319 [1] = &pll2_clk,
320 [2] = &main_clk,
321 [3] = &sh73a0_extal2_clk,
322 [4] = &sh73a0_extcki_clk,
323};
324
249static struct clk div6_clks[DIV6_NR] = { 325static struct clk div6_clks[DIV6_NR] = {
250 [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0), 326 [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
251 [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0), 327 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
252 [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0), 328 [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
253 [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT), 329 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
254 [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0), 330 [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
255 [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0), 331 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
256 [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), 332 [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
257 [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), 333 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
258 [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0), 334 [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
259 [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0), 335 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
260 [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0), 336 [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
261 [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0), 337 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
262 [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0), 338 [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
263 [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0), 339 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
264 [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0), 340 [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
265 [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0), 341 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
266 [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0), 342 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
267 [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0), 343 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
268 [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0), 344 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
269 [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0), 345 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
346 [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
347 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
348 [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
349 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
350 [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
351 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
352 [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
353 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
354 [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
355 hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
356 [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
357 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
358 [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
359 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
360 [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
361 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
362 [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
363 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
364 [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
270}; 366};
271 367
272enum { MSTP001, 368enum { MSTP001,
@@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void)
403 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 499 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
404 500
405 if (!ret) 501 if (!ret)
406 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 502 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
407 503
408 if (!ret) 504 if (!ret)
409 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 505 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index be78a2c73db4..13a18d343ecb 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -46,6 +46,8 @@ extern void sh73a0_clock_init(void);
46extern void sh73a0_pinmux_init(void); 46extern void sh73a0_pinmux_init(void);
47extern struct clk sh73a0_extal1_clk; 47extern struct clk sh73a0_extal1_clk;
48extern struct clk sh73a0_extal2_clk; 48extern struct clk sh73a0_extal2_clk;
49extern struct clk sh73a0_extcki_clk;
50extern struct clk sh73a0_extalr_clk;
49 51
50extern unsigned int sh73a0_get_core_count(void); 52extern unsigned int sh73a0_get_core_count(void);
51extern void sh73a0_secondary_init(unsigned int cpu); 53extern void sh73a0_secondary_init(unsigned int cpu);
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 93f5039099b7..b2ca1d9948fb 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -25,9 +25,6 @@
25 25
26#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 26#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
27 27
28/* Prefer cmdline over RedBoot */
29static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
30
31/* Wait until reset finished. Timeout is 100ms. */ 28/* Wait until reset finished. Timeout is 100ms. */
32static int __init ethernet_reset_finished(void) 29static int __init ethernet_reset_finished(void)
33{ 30{
@@ -293,8 +290,6 @@ static struct platform_device heartbeat_device = {
293 .resource = heartbeat_resources, 290 .resource = heartbeat_resources,
294}; 291};
295 292
296static struct mtd_partition *parsed_partitions;
297
298static struct mtd_partition mpr2_partitions[] = { 293static struct mtd_partition mpr2_partitions[] = {
299 /* Reserved for bootloader, read-only */ 294 /* Reserved for bootloader, read-only */
300 { 295 {
@@ -318,6 +313,8 @@ static struct mtd_partition mpr2_partitions[] = {
318}; 313};
319 314
320static struct physmap_flash_data flash_data = { 315static struct physmap_flash_data flash_data = {
316 .parts = mpr2_partitions,
317 .nr_parts = ARRAY_SIZE(mpr2_partitions),
321 .width = 2, 318 .width = 2,
322}; 319};
323 320
@@ -337,32 +334,6 @@ static struct platform_device flash_device = {
337 }, 334 },
338}; 335};
339 336
340static struct mtd_info *flash_mtd;
341
342static struct map_info mpr2_flash_map = {
343 .name = "Magic Panel R2 Flash",
344 .size = 0x2000000UL,
345 .bankwidth = 2,
346};
347
348static void __init set_mtd_partitions(void)
349{
350 int nr_parts = 0;
351
352 simple_map_init(&mpr2_flash_map);
353 flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map);
354 nr_parts = parse_mtd_partitions(flash_mtd, probes,
355 &parsed_partitions, 0);
356 /* If there is no partition table, used the hard coded table */
357 if (nr_parts <= 0) {
358 flash_data.parts = mpr2_partitions;
359 flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions);
360 } else {
361 flash_data.nr_parts = nr_parts;
362 flash_data.parts = parsed_partitions;
363 }
364}
365
366/* 337/*
367 * Add all resources to the platform_device 338 * Add all resources to the platform_device
368 */ 339 */
@@ -376,7 +347,6 @@ static struct platform_device *mpr2_devices[] __initdata = {
376 347
377static int __init mpr2_devices_setup(void) 348static int __init mpr2_devices_setup(void)
378{ 349{
379 set_mtd_partitions();
380 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 350 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
381} 351}
382device_initcall(mpr2_devices_setup); 352device_initcall(mpr2_devices_setup);
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
index 895e337c79b6..0838154dd216 100644
--- a/arch/sh/boards/board-sh7757lcr.c
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -19,6 +19,7 @@
19#include <linux/mmc/sh_mmcif.h> 19#include <linux/mmc/sh_mmcif.h>
20#include <linux/mmc/sh_mobile_sdhi.h> 20#include <linux/mmc/sh_mobile_sdhi.h>
21#include <linux/sh_eth.h> 21#include <linux/sh_eth.h>
22#include <linux/usb/renesas_usbhs.h>
22#include <cpu/sh7757.h> 23#include <cpu/sh7757.h>
23#include <asm/heartbeat.h> 24#include <asm/heartbeat.h>
24 25
@@ -264,6 +265,43 @@ static struct platform_device sdhi_device = {
264 }, 265 },
265}; 266};
266 267
268static int usbhs0_get_id(struct platform_device *pdev)
269{
270 return USBHS_GADGET;
271}
272
273static struct renesas_usbhs_platform_info usb0_data = {
274 .platform_callback = {
275 .get_id = usbhs0_get_id,
276 },
277 .driver_param = {
278 .buswait_bwait = 5,
279 }
280};
281
282static struct resource usb0_resources[] = {
283 [0] = {
284 .start = 0xfe450000,
285 .end = 0xfe4501ff,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = 50,
290 .end = 50,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device usb0_device = {
296 .name = "renesas_usbhs",
297 .id = 0,
298 .dev = {
299 .platform_data = &usb0_data,
300 },
301 .num_resources = ARRAY_SIZE(usb0_resources),
302 .resource = usb0_resources,
303};
304
267static struct platform_device *sh7757lcr_devices[] __initdata = { 305static struct platform_device *sh7757lcr_devices[] __initdata = {
268 &heartbeat_device, 306 &heartbeat_device,
269 &sh7757_eth0_device, 307 &sh7757_eth0_device,
@@ -272,6 +310,7 @@ static struct platform_device *sh7757lcr_devices[] __initdata = {
272 &sh7757_eth_giga1_device, 310 &sh7757_eth_giga1_device,
273 &sh_mmcif_device, 311 &sh_mmcif_device,
274 &sdhi_device, 312 &sdhi_device,
313 &usb0_device,
275}; 314};
276 315
277static struct flash_platform_data spi_flash_data = { 316static struct flash_platform_data spi_flash_data = {
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 7030f4c8cf11..74d49c01783b 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -249,9 +249,6 @@ static struct platform_device lcdc_device = {
249 .dev = { 249 .dev = {
250 .platform_data = &lcdc_info, 250 .platform_data = &lcdc_info,
251 }, 251 },
252 .archdata = {
253 .hwblk_id = HWBLK_LCDC,
254 },
255}; 252};
256 253
257static void camera_power(int val) 254static void camera_power(int val)
@@ -424,9 +421,6 @@ static struct platform_device ceu_device = {
424 .dev = { 421 .dev = {
425 .platform_data = &sh_mobile_ceu_info, 422 .platform_data = &sh_mobile_ceu_info,
426 }, 423 },
427 .archdata = {
428 .hwblk_id = HWBLK_CEU,
429 },
430}; 424};
431 425
432static struct resource sdhi0_cn3_resources[] = { 426static struct resource sdhi0_cn3_resources[] = {
@@ -454,9 +448,6 @@ static struct platform_device sdhi0_cn3_device = {
454 .dev = { 448 .dev = {
455 .platform_data = &sdhi0_cn3_data, 449 .platform_data = &sdhi0_cn3_data,
456 }, 450 },
457 .archdata = {
458 .hwblk_id = HWBLK_SDHI0,
459 },
460}; 451};
461 452
462static struct resource sdhi1_cn7_resources[] = { 453static struct resource sdhi1_cn7_resources[] = {
@@ -484,9 +475,6 @@ static struct platform_device sdhi1_cn7_device = {
484 .dev = { 475 .dev = {
485 .platform_data = &sdhi1_cn7_data, 476 .platform_data = &sdhi1_cn7_data,
486 }, 477 },
487 .archdata = {
488 .hwblk_id = HWBLK_SDHI1,
489 },
490}; 478};
491 479
492static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 480static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 92ddce4b3456..9a19fb07276c 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -156,9 +156,6 @@ static struct platform_device sh_eth_device = {
156 }, 156 },
157 .num_resources = ARRAY_SIZE(sh_eth_resources), 157 .num_resources = ARRAY_SIZE(sh_eth_resources),
158 .resource = sh_eth_resources, 158 .resource = sh_eth_resources,
159 .archdata = {
160 .hwblk_id = HWBLK_ETHER,
161 },
162}; 159};
163 160
164/* USB0 host */ 161/* USB0 host */
@@ -278,9 +275,6 @@ static struct platform_device usbhs_device = {
278 }, 275 },
279 .num_resources = ARRAY_SIZE(usbhs_resources), 276 .num_resources = ARRAY_SIZE(usbhs_resources),
280 .resource = usbhs_resources, 277 .resource = usbhs_resources,
281 .archdata = {
282 .hwblk_id = HWBLK_USB1,
283 },
284}; 278};
285 279
286/* LCDC */ 280/* LCDC */
@@ -366,9 +360,6 @@ static struct platform_device lcdc_device = {
366 .dev = { 360 .dev = {
367 .platform_data = &lcdc_info, 361 .platform_data = &lcdc_info,
368 }, 362 },
369 .archdata = {
370 .hwblk_id = HWBLK_LCDC,
371 },
372}; 363};
373 364
374/* CEU0 */ 365/* CEU0 */
@@ -400,9 +391,6 @@ static struct platform_device ceu0_device = {
400 .dev = { 391 .dev = {
401 .platform_data = &sh_mobile_ceu0_info, 392 .platform_data = &sh_mobile_ceu0_info,
402 }, 393 },
403 .archdata = {
404 .hwblk_id = HWBLK_CEU0,
405 },
406}; 394};
407 395
408/* CEU1 */ 396/* CEU1 */
@@ -434,9 +422,6 @@ static struct platform_device ceu1_device = {
434 .dev = { 422 .dev = {
435 .platform_data = &sh_mobile_ceu1_info, 423 .platform_data = &sh_mobile_ceu1_info,
436 }, 424 },
437 .archdata = {
438 .hwblk_id = HWBLK_CEU1,
439 },
440}; 425};
441 426
442/* I2C device */ 427/* I2C device */
@@ -491,9 +476,6 @@ static struct platform_device keysc_device = {
491 .dev = { 476 .dev = {
492 .platform_data = &keysc_info, 477 .platform_data = &keysc_info,
493 }, 478 },
494 .archdata = {
495 .hwblk_id = HWBLK_KEYSC,
496 },
497}; 479};
498 480
499/* TouchScreen */ 481/* TouchScreen */
@@ -568,9 +550,6 @@ static struct platform_device sdhi0_device = {
568 .dev = { 550 .dev = {
569 .platform_data = &sdhi0_info, 551 .platform_data = &sdhi0_info,
570 }, 552 },
571 .archdata = {
572 .hwblk_id = HWBLK_SDHI0,
573 },
574}; 553};
575 554
576#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 555#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
@@ -608,9 +587,6 @@ static struct platform_device sdhi1_device = {
608 .dev = { 587 .dev = {
609 .platform_data = &sdhi1_info, 588 .platform_data = &sdhi1_info,
610 }, 589 },
611 .archdata = {
612 .hwblk_id = HWBLK_SDHI1,
613 },
614}; 590};
615#endif /* CONFIG_MMC_SH_MMCIF */ 591#endif /* CONFIG_MMC_SH_MMCIF */
616 592
@@ -676,9 +652,6 @@ static struct platform_device msiof0_device = {
676 }, 652 },
677 .num_resources = ARRAY_SIZE(msiof0_resources), 653 .num_resources = ARRAY_SIZE(msiof0_resources),
678 .resource = msiof0_resources, 654 .resource = msiof0_resources,
679 .archdata = {
680 .hwblk_id = HWBLK_MSIOF0,
681 },
682}; 655};
683 656
684#endif 657#endif
@@ -818,9 +791,6 @@ static struct platform_device fsi_device = {
818 .dev = { 791 .dev = {
819 .platform_data = &fsi_info, 792 .platform_data = &fsi_info,
820 }, 793 },
821 .archdata = {
822 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
823 },
824}; 794};
825 795
826/* IrDA */ 796/* IrDA */
@@ -882,9 +852,6 @@ static struct platform_device vou_device = {
882 .dev = { 852 .dev = {
883 .platform_data = &sh_vou_pdata, 853 .platform_data = &sh_vou_pdata,
884 }, 854 },
885 .archdata = {
886 .hwblk_id = HWBLK_VOU,
887 },
888}; 855};
889 856
890#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) 857#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
@@ -936,9 +903,6 @@ static struct platform_device sh_mmcif_device = {
936 }, 903 },
937 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 904 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
938 .resource = sh_mmcif_resources, 905 .resource = sh_mmcif_resources,
939 .archdata = {
940 .hwblk_id = HWBLK_MMC,
941 },
942}; 906};
943#endif 907#endif
944 908
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index f65271a8d075..5c3c71366848 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -122,9 +122,6 @@ static struct platform_device kfr2r09_sh_keysc_device = {
122 .dev = { 122 .dev = {
123 .platform_data = &kfr2r09_sh_keysc_info, 123 .platform_data = &kfr2r09_sh_keysc_info,
124 }, 124 },
125 .archdata = {
126 .hwblk_id = HWBLK_KEYSC,
127 },
128}; 125};
129 126
130static const struct fb_videomode kfr2r09_lcdc_modes[] = { 127static const struct fb_videomode kfr2r09_lcdc_modes[] = {
@@ -191,9 +188,6 @@ static struct platform_device kfr2r09_sh_lcdc_device = {
191 .dev = { 188 .dev = {
192 .platform_data = &kfr2r09_sh_lcdc_info, 189 .platform_data = &kfr2r09_sh_lcdc_info,
193 }, 190 },
194 .archdata = {
195 .hwblk_id = HWBLK_LCDC,
196 },
197}; 191};
198 192
199static struct r8a66597_platdata kfr2r09_usb0_gadget_data = { 193static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
@@ -254,9 +248,6 @@ static struct platform_device kfr2r09_ceu_device = {
254 .dev = { 248 .dev = {
255 .platform_data = &sh_mobile_ceu_info, 249 .platform_data = &sh_mobile_ceu_info,
256 }, 250 },
257 .archdata = {
258 .hwblk_id = HWBLK_CEU0,
259 },
260}; 251};
261 252
262static struct i2c_board_info kfr2r09_i2c_camera = { 253static struct i2c_board_info kfr2r09_i2c_camera = {
@@ -377,9 +368,6 @@ static struct platform_device kfr2r09_sh_sdhi0_device = {
377 .dev = { 368 .dev = {
378 .platform_data = &sh7724_sdhi0_data, 369 .platform_data = &sh7724_sdhi0_data,
379 }, 370 },
380 .archdata = {
381 .hwblk_id = HWBLK_SDHI0,
382 },
383}; 371};
384 372
385static struct platform_device *kfr2r09_devices[] __initdata = { 373static struct platform_device *kfr2r09_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index e4c81195929c..f8f9377d5684 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -99,9 +99,6 @@ static struct platform_device sh_keysc_device = {
99 .dev = { 99 .dev = {
100 .platform_data = &sh_keysc_info, 100 .platform_data = &sh_keysc_info,
101 }, 101 },
102 .archdata = {
103 .hwblk_id = HWBLK_KEYSC,
104 },
105}; 102};
106 103
107static struct mtd_partition migor_nor_flash_partitions[] = 104static struct mtd_partition migor_nor_flash_partitions[] =
@@ -300,9 +297,6 @@ static struct platform_device migor_lcdc_device = {
300 .dev = { 297 .dev = {
301 .platform_data = &sh_mobile_lcdc_info, 298 .platform_data = &sh_mobile_lcdc_info,
302 }, 299 },
303 .archdata = {
304 .hwblk_id = HWBLK_LCDC,
305 },
306}; 300};
307 301
308static struct clk *camera_clk; 302static struct clk *camera_clk;
@@ -390,9 +384,6 @@ static struct platform_device migor_ceu_device = {
390 .dev = { 384 .dev = {
391 .platform_data = &sh_mobile_ceu_info, 385 .platform_data = &sh_mobile_ceu_info,
392 }, 386 },
393 .archdata = {
394 .hwblk_id = HWBLK_CEU,
395 },
396}; 387};
397 388
398static struct resource sdhi_cn9_resources[] = { 389static struct resource sdhi_cn9_resources[] = {
@@ -421,9 +412,6 @@ static struct platform_device sdhi_cn9_device = {
421 .dev = { 412 .dev = {
422 .platform_data = &sh7724_sdhi_data, 413 .platform_data = &sh7724_sdhi_data,
423 }, 414 },
424 .archdata = {
425 .hwblk_id = HWBLK_SDHI,
426 },
427}; 415};
428 416
429static struct i2c_board_info migor_i2c_devices[] = { 417static struct i2c_board_info migor_i2c_devices[] = {
diff --git a/arch/sh/boards/mach-rsk/setup.c b/arch/sh/boards/mach-rsk/setup.c
index a5c0df785bfe..895f030070d3 100644
--- a/arch/sh/boards/mach-rsk/setup.c
+++ b/arch/sh/boards/mach-rsk/setup.c
@@ -15,12 +15,12 @@
15#include <linux/mtd/mtd.h> 15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
17#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
18#ifdef CONFIG_MTD
19#include <linux/mtd/map.h> 18#include <linux/mtd/map.h>
20#endif
21#include <asm/machvec.h> 19#include <asm/machvec.h>
22#include <asm/io.h> 20#include <asm/io.h>
23 21
22static const char *part_probes[] = { "cmdlinepart", NULL };
23
24static struct mtd_partition rsk_partitions[] = { 24static struct mtd_partition rsk_partitions[] = {
25 { 25 {
26 .name = "Bootloader", 26 .name = "Bootloader",
@@ -39,9 +39,10 @@ static struct mtd_partition rsk_partitions[] = {
39}; 39};
40 40
41static struct physmap_flash_data flash_data = { 41static struct physmap_flash_data flash_data = {
42 .parts = rsk_partitions, 42 .parts = rsk_partitions,
43 .nr_parts = ARRAY_SIZE(rsk_partitions), 43 .nr_parts = ARRAY_SIZE(rsk_partitions),
44 .width = 2, 44 .width = 2,
45 .part_probe_types = part_probes,
45}; 46};
46 47
47static struct resource flash_resource = { 48static struct resource flash_resource = {
@@ -60,44 +61,12 @@ static struct platform_device flash_device = {
60 }, 61 },
61}; 62};
62 63
63#ifdef CONFIG_MTD
64static const char *probes[] = { "cmdlinepart", NULL };
65
66static struct map_info rsk_flash_map = {
67 .name = "RSK+ Flash",
68 .size = 0x400000,
69 .bankwidth = 2,
70};
71
72static struct mtd_info *flash_mtd;
73
74static struct mtd_partition *parsed_partitions;
75
76static void __init set_mtd_partitions(void)
77{
78 int nr_parts = 0;
79
80 simple_map_init(&rsk_flash_map);
81 flash_mtd = do_map_probe("cfi_probe", &rsk_flash_map);
82 nr_parts = parse_mtd_partitions(flash_mtd, probes,
83 &parsed_partitions, 0);
84 /* If there is no partition table, used the hard coded table */
85 if (nr_parts > 0) {
86 flash_data.nr_parts = nr_parts;
87 flash_data.parts = parsed_partitions;
88 }
89}
90#else
91static inline void set_mtd_partitions(void) {}
92#endif
93
94static struct platform_device *rsk_devices[] __initdata = { 64static struct platform_device *rsk_devices[] __initdata = {
95 &flash_device, 65 &flash_device,
96}; 66};
97 67
98static int __init rsk_devices_setup(void) 68static int __init rsk_devices_setup(void)
99{ 69{
100 set_mtd_partitions();
101 return platform_add_devices(rsk_devices, 70 return platform_add_devices(rsk_devices,
102 ARRAY_SIZE(rsk_devices)); 71 ARRAY_SIZE(rsk_devices));
103} 72}
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index 80a4e571b310..e1963fecd761 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -127,9 +127,6 @@ static struct platform_device sh_keysc_device = {
127 .dev = { 127 .dev = {
128 .platform_data = &sh_keysc_info, 128 .platform_data = &sh_keysc_info,
129 }, 129 },
130 .archdata = {
131 .hwblk_id = HWBLK_KEYSC,
132 },
133}; 130};
134 131
135static struct platform_device *se7722_devices[] __initdata = { 132static struct platform_device *se7722_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index b747c0ab9264..affde85ff63e 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -210,9 +210,6 @@ static struct platform_device lcdc_device = {
210 .dev = { 210 .dev = {
211 .platform_data = &lcdc_info, 211 .platform_data = &lcdc_info,
212 }, 212 },
213 .archdata = {
214 .hwblk_id = HWBLK_LCDC,
215 },
216}; 213};
217 214
218/* CEU0 */ 215/* CEU0 */
@@ -244,9 +241,6 @@ static struct platform_device ceu0_device = {
244 .dev = { 241 .dev = {
245 .platform_data = &sh_mobile_ceu0_info, 242 .platform_data = &sh_mobile_ceu0_info,
246 }, 243 },
247 .archdata = {
248 .hwblk_id = HWBLK_CEU0,
249 },
250}; 244};
251 245
252/* CEU1 */ 246/* CEU1 */
@@ -278,9 +272,6 @@ static struct platform_device ceu1_device = {
278 .dev = { 272 .dev = {
279 .platform_data = &sh_mobile_ceu1_info, 273 .platform_data = &sh_mobile_ceu1_info,
280 }, 274 },
281 .archdata = {
282 .hwblk_id = HWBLK_CEU1,
283 },
284}; 275};
285 276
286/* FSI */ 277/* FSI */
@@ -310,9 +301,6 @@ static struct platform_device fsi_device = {
310 .dev = { 301 .dev = {
311 .platform_data = &fsi_info, 302 .platform_data = &fsi_info,
312 }, 303 },
313 .archdata = {
314 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
315 },
316}; 304};
317 305
318static struct platform_device fsi_ak4642_device = { 306static struct platform_device fsi_ak4642_device = {
@@ -355,9 +343,6 @@ static struct platform_device keysc_device = {
355 .dev = { 343 .dev = {
356 .platform_data = &keysc_info, 344 .platform_data = &keysc_info,
357 }, 345 },
358 .archdata = {
359 .hwblk_id = HWBLK_KEYSC,
360 },
361}; 346};
362 347
363/* SH Eth */ 348/* SH Eth */
@@ -386,9 +371,6 @@ static struct platform_device sh_eth_device = {
386 }, 371 },
387 .num_resources = ARRAY_SIZE(sh_eth_resources), 372 .num_resources = ARRAY_SIZE(sh_eth_resources),
388 .resource = sh_eth_resources, 373 .resource = sh_eth_resources,
389 .archdata = {
390 .hwblk_id = HWBLK_ETHER,
391 },
392}; 374};
393 375
394static struct r8a66597_platdata sh7724_usb0_host_data = { 376static struct r8a66597_platdata sh7724_usb0_host_data = {
@@ -418,9 +400,6 @@ static struct platform_device sh7724_usb0_host_device = {
418 }, 400 },
419 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), 401 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
420 .resource = sh7724_usb0_host_resources, 402 .resource = sh7724_usb0_host_resources,
421 .archdata = {
422 .hwblk_id = HWBLK_USB0,
423 },
424}; 403};
425 404
426static struct r8a66597_platdata sh7724_usb1_gadget_data = { 405static struct r8a66597_platdata sh7724_usb1_gadget_data = {
@@ -479,9 +458,6 @@ static struct platform_device sdhi0_cn7_device = {
479 .dev = { 458 .dev = {
480 .platform_data = &sh7724_sdhi0_data, 459 .platform_data = &sh7724_sdhi0_data,
481 }, 460 },
482 .archdata = {
483 .hwblk_id = HWBLK_SDHI0,
484 },
485}; 461};
486 462
487static struct resource sdhi1_cn8_resources[] = { 463static struct resource sdhi1_cn8_resources[] = {
@@ -511,9 +487,6 @@ static struct platform_device sdhi1_cn8_device = {
511 .dev = { 487 .dev = {
512 .platform_data = &sh7724_sdhi1_data, 488 .platform_data = &sh7724_sdhi1_data,
513 }, 489 },
514 .archdata = {
515 .hwblk_id = HWBLK_SDHI1,
516 },
517}; 490};
518 491
519/* IrDA */ 492/* IrDA */
@@ -576,9 +549,6 @@ static struct platform_device vou_device = {
576 .dev = { 549 .dev = {
577 .platform_data = &sh_vou_pdata, 550 .platform_data = &sh_vou_pdata,
578 }, 551 },
579 .archdata = {
580 .hwblk_id = HWBLK_VOU,
581 },
582}; 552};
583 553
584static struct platform_device *ms7724se_devices[] __initdata = { 554static struct platform_device *ms7724se_devices[] __initdata = {
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index b16debfe8c1e..a1c9c0daec10 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -14,15 +14,5 @@ int platform_resource_setup_memory(struct platform_device *pdev,
14 14
15void plat_early_device_setup(void); 15void plat_early_device_setup(void);
16 16
17#define PDEV_ARCHDATA_FLAG_INIT 0
18#define PDEV_ARCHDATA_FLAG_IDLE 1
19#define PDEV_ARCHDATA_FLAG_SUSP 2
20
21struct pdev_archdata { 17struct pdev_archdata {
22 int hwblk_id;
23#ifdef CONFIG_PM_RUNTIME
24 unsigned long flags;
25 struct list_head entry;
26 struct mutex mutex;
27#endif
28}; 18};
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
deleted file mode 100644
index 855e945c6199..000000000000
--- a/arch/sh/include/asm/hwblk.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_HWBLK_H
2#define __ASM_SH_HWBLK_H
3
4#include <asm/clock.h>
5#include <asm/io.h>
6
7#define HWBLK_CNT_USAGE 0
8#define HWBLK_CNT_IDLE 1
9#define HWBLK_CNT_DEVICES 2
10#define HWBLK_CNT_NR 3
11
12#define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */
13
14#define HWBLK_AREA(_flags, _parent) \
15{ \
16 .flags = _flags, \
17 .parent = _parent, \
18}
19
20struct hwblk_area {
21 int cnt[HWBLK_CNT_NR];
22 unsigned char parent;
23 unsigned char flags;
24};
25
26#define HWBLK(_mstp, _bit, _area) \
27{ \
28 .mstp = (void __iomem *)_mstp, \
29 .bit = _bit, \
30 .area = _area, \
31}
32
33struct hwblk {
34 void __iomem *mstp;
35 unsigned char bit;
36 unsigned char area;
37 int cnt[HWBLK_CNT_NR];
38};
39
40struct hwblk_info {
41 struct hwblk_area *areas;
42 int nr_areas;
43 struct hwblk *hwblks;
44 int nr_hwblks;
45};
46
47/* Should be defined by processor-specific code */
48int arch_hwblk_init(void);
49int arch_hwblk_sleep_mode(void);
50
51int hwblk_register(struct hwblk_info *info);
52int hwblk_init(void);
53
54void hwblk_enable(struct hwblk_info *info, int hwblk);
55void hwblk_disable(struct hwblk_info *info, int hwblk);
56
57void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int cnt);
58void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int cnt);
59
60/* allow clocks to enable and disable hardware blocks */
61#define SH_HWBLK_CLK(_hwblk, _parent, _flags) \
62[_hwblk] = { \
63 .parent = _parent, \
64 .arch_flags = _hwblk, \
65 .flags = _flags, \
66}
67
68int sh_hwblk_clk_register(struct clk *clks, int nr);
69
70#endif /* __ASM_SH_HWBLK_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index bd0622788d64..3bb74e534d0f 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -222,14 +222,11 @@ enum {
222}; 222};
223 223
224enum { 224enum {
225 HWBLK_UNKNOWN = 0, 225 HWBLK_URAM, HWBLK_XYMEM,
226 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_URAM, HWBLK_XYMEM, 226 HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL,
227 HWBLK_INTC, HWBLK_DMAC, HWBLK_SHYWAY, HWBLK_HUDI, 227 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_IIC, HWBLK_RTC,
228 HWBLK_UBC, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL, 228 HWBLK_SDHI, HWBLK_KEYSC,
229 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SIO, 229 HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
230 HWBLK_SIOF0, HWBLK_SIOF1, HWBLK_IIC, HWBLK_RTC,
231 HWBLK_TPU, HWBLK_IRDA, HWBLK_SDHI, HWBLK_SIM, HWBLK_KEYSC,
232 HWBLK_TSIF, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
233 HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU, 230 HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU,
234 HWBLK_LCDC, 231 HWBLK_LCDC,
235 HWBLK_NR, 232 HWBLK_NR,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 9b36fae72324..6fae50cb1e94 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -266,10 +266,9 @@ enum {
266}; 266};
267 267
268enum { 268enum {
269 HWBLK_UNKNOWN = 0,
270 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU, 269 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU,
271 HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, 270 HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
272 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, HWBLK_SUBC, 271 HWBLK_HUDI, HWBLK_UBC,
273 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, 272 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
274 HWBLK_FLCTL, 273 HWBLK_FLCTL,
275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, 274 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index cbc47e6bcab5..38859f96d4e5 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -268,10 +268,9 @@ enum {
268}; 268};
269 269
270enum { 270enum {
271 HWBLK_UNKNOWN = 0,
272 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C, 271 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C,
273 HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, 272 HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
274 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, 273 HWBLK_HUDI, HWBLK_UBC,
275 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, 274 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
276 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3, 275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3,
277 HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1, 276 HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1,
@@ -314,5 +313,6 @@ enum {
314 313
315extern struct clk sh7724_fsimcka_clk; 314extern struct clk sh7724_fsimcka_clk;
316extern struct clk sh7724_fsimckb_clk; 315extern struct clk sh7724_fsimckb_clk;
316extern struct clk sh7724_dv_clki;
317 317
318#endif /* __ASM_SH7724_H__ */ 318#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index ae95935d93cd..fa58bfd30d82 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -18,4 +18,4 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20
21obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o 21obj-y += irq/ init.o clock.o fpu.o proc.o
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
deleted file mode 100644
index 3e985aae5d91..000000000000
--- a/arch/sh/kernel/cpu/hwblk.c
+++ /dev/null
@@ -1,159 +0,0 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/io.h>
4#include <linux/spinlock.h>
5#include <asm/suspend.h>
6#include <asm/hwblk.h>
7#include <asm/clock.h>
8
9static DEFINE_SPINLOCK(hwblk_lock);
10
11static void hwblk_area_mod_cnt(struct hwblk_info *info,
12 int area, int counter, int value, int goal)
13{
14 struct hwblk_area *hap = info->areas + area;
15
16 hap->cnt[counter] += value;
17
18 if (hap->cnt[counter] != goal)
19 return;
20
21 if (hap->flags & HWBLK_AREA_FLAG_PARENT)
22 hwblk_area_mod_cnt(info, hap->parent, counter, value, goal);
23}
24
25
26static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
27 int counter, int value, int goal)
28{
29 struct hwblk *hp = info->hwblks + hwblk;
30
31 hp->cnt[counter] += value;
32 if (hp->cnt[counter] == goal)
33 hwblk_area_mod_cnt(info, hp->area, counter, value, goal);
34
35 return hp->cnt[counter];
36}
37
38static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
39 int counter, int value, int goal)
40{
41 unsigned long flags;
42
43 spin_lock_irqsave(&hwblk_lock, flags);
44 __hwblk_mod_cnt(info, hwblk, counter, value, goal);
45 spin_unlock_irqrestore(&hwblk_lock, flags);
46}
47
48void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter)
49{
50 hwblk_mod_cnt(info, hwblk, counter, 1, 1);
51}
52
53void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter)
54{
55 hwblk_mod_cnt(info, hwblk, counter, -1, 0);
56}
57
58void hwblk_enable(struct hwblk_info *info, int hwblk)
59{
60 struct hwblk *hp = info->hwblks + hwblk;
61 unsigned long tmp;
62 unsigned long flags;
63 int ret;
64
65 spin_lock_irqsave(&hwblk_lock, flags);
66
67 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1);
68 if (ret == 1) {
69 tmp = __raw_readl(hp->mstp);
70 tmp &= ~(1 << hp->bit);
71 __raw_writel(tmp, hp->mstp);
72 }
73
74 spin_unlock_irqrestore(&hwblk_lock, flags);
75}
76
77void hwblk_disable(struct hwblk_info *info, int hwblk)
78{
79 struct hwblk *hp = info->hwblks + hwblk;
80 unsigned long tmp;
81 unsigned long flags;
82 int ret;
83
84 spin_lock_irqsave(&hwblk_lock, flags);
85
86 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0);
87 if (ret == 0) {
88 tmp = __raw_readl(hp->mstp);
89 tmp |= 1 << hp->bit;
90 __raw_writel(tmp, hp->mstp);
91 }
92
93 spin_unlock_irqrestore(&hwblk_lock, flags);
94}
95
96struct hwblk_info *hwblk_info;
97
98int __init hwblk_register(struct hwblk_info *info)
99{
100 hwblk_info = info;
101 return 0;
102}
103
104int __init __weak arch_hwblk_init(void)
105{
106 return 0;
107}
108
109int __weak arch_hwblk_sleep_mode(void)
110{
111 return SUSP_SH_SLEEP;
112}
113
114int __init hwblk_init(void)
115{
116 return arch_hwblk_init();
117}
118
119/* allow clocks to enable and disable hardware blocks */
120static int sh_hwblk_clk_enable(struct clk *clk)
121{
122 if (!hwblk_info)
123 return -ENOENT;
124
125 hwblk_enable(hwblk_info, clk->arch_flags);
126 return 0;
127}
128
129static void sh_hwblk_clk_disable(struct clk *clk)
130{
131 if (hwblk_info)
132 hwblk_disable(hwblk_info, clk->arch_flags);
133}
134
135static struct clk_ops sh_hwblk_clk_ops = {
136 .enable = sh_hwblk_clk_enable,
137 .disable = sh_hwblk_clk_disable,
138 .recalc = followparent_recalc,
139};
140
141int __init sh_hwblk_clk_register(struct clk *clks, int nr)
142{
143 struct clk *clkp;
144 int ret = 0;
145 int k;
146
147 for (k = 0; !ret && (k < nr); k++) {
148 clkp = clks + k;
149
150 /* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
151 if (!clkp->arch_flags)
152 continue;
153
154 clkp->ops = &sh_hwblk_clk_ops;
155 ret |= clk_register(clkp);
156 }
157
158 return ret;
159}
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index a8140f0bbf6c..0a47bd3e7bee 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -337,7 +337,7 @@ static struct kobj_type ktype_percpu_entry = {
337 .default_attrs = sq_sysfs_attrs, 337 .default_attrs = sq_sysfs_attrs,
338}; 338};
339 339
340static int __devinit sq_dev_add(struct device *dev) 340static int sq_dev_add(struct device *dev, struct subsys_interface *sif)
341{ 341{
342 unsigned int cpu = dev->id; 342 unsigned int cpu = dev->id;
343 struct kobject *kobj; 343 struct kobject *kobj;
@@ -355,7 +355,7 @@ static int __devinit sq_dev_add(struct device *dev)
355 return error; 355 return error;
356} 356}
357 357
358static int __devexit sq_dev_remove(struct device *dev) 358static int sq_dev_remove(struct device *dev, struct subsys_interface *sif)
359{ 359{
360 unsigned int cpu = dev->id; 360 unsigned int cpu = dev->id;
361 struct kobject *kobj = sq_kobject[cpu]; 361 struct kobject *kobj = sq_kobject[cpu];
@@ -365,10 +365,10 @@ static int __devexit sq_dev_remove(struct device *dev)
365} 365}
366 366
367static struct subsys_interface sq_interface = { 367static struct subsys_interface sq_interface = {
368 .name = "sq" 368 .name = "sq",
369 .subsys = &cpu_subsys, 369 .subsys = &cpu_subsys,
370 .add_dev = sq_dev_add, 370 .add_dev = sq_dev_add,
371 .remove_dev = __devexit_p(sq_dev_remove), 371 .remove_dev = sq_dev_remove,
372}; 372};
373 373
374static int __init sq_api_init(void) 374static int __init sq_api_init(void)
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index c57fb287011e..0b22d108f4c5 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,9 +27,9 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 35
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index c9a48088ad47..212c72ef959c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -22,8 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/sh_clk.h>
25#include <asm/clock.h> 26#include <asm/clock.h>
26#include <asm/hwblk.h>
27#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
28 28
29/* SH7722 registers */ 29/* SH7722 registers */
@@ -33,6 +33,9 @@
33#define SCLKBCR 0xa415000c 33#define SCLKBCR 0xa415000c
34#define IRDACLKCR 0xa4150018 34#define IRDACLKCR 0xa4150018
35#define PLLCR 0xa4150024 35#define PLLCR 0xa4150024
36#define MSTPCR0 0xa4150030
37#define MSTPCR1 0xa4150034
38#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 39#define DLLFRQ 0xa4150050
37 40
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 41/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -148,31 +151,31 @@ struct clk div6_clks[DIV6_NR] = {
148}; 151};
149 152
150static struct clk mstp_clks[HWBLK_NR] = { 153static struct clk mstp_clks[HWBLK_NR] = {
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT), 154 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 155 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0), 156 [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 157 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 158 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 159 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
160 163
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 164 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 165 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
163 166
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0), 167 [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 168 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0), 169 [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 170 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 171 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 172 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 173 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 174 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 175 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0), 176 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 177 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0), 178 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
176}; 179};
177 180
178static struct clk_lookup lookups[] = { 181static struct clk_lookup lookups[] = {
@@ -205,27 +208,27 @@ static struct clk_lookup lookups[] = {
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]), 208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
206 209
207 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 210 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
208 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 211 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
209 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 212 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
210 213
211 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 214 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
212 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 215 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
213 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 216 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
214 217
215 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 218 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
216 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 219 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
217 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]), 220 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
218 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 221 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
219 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), 222 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
220 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 223 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
221 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 224 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
222 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 225 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
223 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 226 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
224 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 227 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
225 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 228 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
226 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), 229 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
227 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 230 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
228 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 231 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
229}; 232};
230 233
231int __init arch_clk_init(void) 234int __init arch_clk_init(void)
@@ -258,7 +261,7 @@ int __init arch_clk_init(void)
258 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 261 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
259 262
260 if (!ret) 263 if (!ret)
261 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 264 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
262 265
263 return ret; 266 return ret;
264} 267}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 3cc3827380e3..2f8c9179da47 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
29 29
30/* SH7723 registers */ 30/* SH7723 registers */
@@ -34,6 +34,9 @@
34#define SCLKBCR 0xa415000c 34#define SCLKBCR 0xa415000c
35#define IRDACLKCR 0xa4150018 35#define IRDACLKCR 0xa4150018
36#define PLLCR 0xa4150024 36#define PLLCR 0xa4150024
37#define MSTPCR0 0xa4150030
38#define MSTPCR1 0xa4150034
39#define MSTPCR2 0xa4150038
37#define DLLFRQ 0xa4150050 40#define DLLFRQ 0xa4150050
38 41
39/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -149,55 +152,55 @@ struct clk div6_clks[DIV6_NR] = {
149 152
150static struct clk mstp_clks[] = { 153static struct clk mstp_clks[] = {
151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 154 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 156 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 160 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 161 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 162 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 164 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 165 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 166 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 167 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 168 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 169 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 170 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 171 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 172 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 173 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 174 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 175 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 176 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 177 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 178 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 179 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0), 180 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
178 181
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 184
182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0), 185 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0), 186 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 187 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 188 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 189 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 190 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 191 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 192 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 193 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0), 194 [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 195 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 196 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0), 197 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 198 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 199 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 200 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0), 201 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 202 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 203 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201}; 204};
202 205
203static struct clk_lookup lookups[] = { 206static struct clk_lookup lookups[] = {
@@ -229,80 +232,17 @@ static struct clk_lookup lookups[] = {
229 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
233 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 237 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 238 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
236 {
237 /* TMU0 */
238 .dev_id = "sh_tmu.0",
239 .con_id = "tmu_fck",
240 .clk = &mstp_clks[HWBLK_TMU0],
241 }, {
242 /* TMU1 */
243 .dev_id = "sh_tmu.1",
244 .con_id = "tmu_fck",
245 .clk = &mstp_clks[HWBLK_TMU0],
246 }, {
247 /* TMU2 */
248 .dev_id = "sh_tmu.2",
249 .con_id = "tmu_fck",
250 .clk = &mstp_clks[HWBLK_TMU0],
251 },
252 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 239 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
253 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 240 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
254 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 241 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
255 {
256 /* TMU3 */
257 .dev_id = "sh_tmu.3",
258 .con_id = "tmu_fck",
259 .clk = &mstp_clks[HWBLK_TMU1],
260 }, {
261 /* TMU4 */
262 .dev_id = "sh_tmu.4",
263 .con_id = "tmu_fck",
264 .clk = &mstp_clks[HWBLK_TMU1],
265 }, {
266 /* TMU5 */
267 .dev_id = "sh_tmu.5",
268 .con_id = "tmu_fck",
269 .clk = &mstp_clks[HWBLK_TMU1],
270 },
271 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 242 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
272 { 243 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
273 /* SCIF0 */ 244 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
274 .dev_id = "sh-sci.0", 245 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]),
275 .con_id = "sci_fck",
276 .clk = &mstp_clks[HWBLK_SCIF0],
277 }, {
278 /* SCIF1 */
279 .dev_id = "sh-sci.1",
280 .con_id = "sci_fck",
281 .clk = &mstp_clks[HWBLK_SCIF1],
282 }, {
283 /* SCIF2 */
284 .dev_id = "sh-sci.2",
285 .con_id = "sci_fck",
286 .clk = &mstp_clks[HWBLK_SCIF2],
287 }, {
288 /* SCIF3 */
289 .dev_id = "sh-sci.3",
290 .con_id = "sci_fck",
291 .clk = &mstp_clks[HWBLK_SCIF3],
292 }, {
293 /* SCIF4 */
294 .dev_id = "sh-sci.4",
295 .con_id = "sci_fck",
296 .clk = &mstp_clks[HWBLK_SCIF4],
297 }, {
298 /* SCIF5 */
299 .dev_id = "sh-sci.5",
300 .con_id = "sci_fck",
301 .clk = &mstp_clks[HWBLK_SCIF5],
302 },
303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 246 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 247 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 248 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
@@ -311,19 +251,34 @@ static struct clk_lookup lookups[] = {
311 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 251 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
312 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 252 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
313 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 253 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
314 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 254 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
315 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 255 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
316 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 256 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
317 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 257 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
318 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 258 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
319 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 259 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
320 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 260 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
321 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 261 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
322 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 262 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
323 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 263 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
324 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 264 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
325 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 265 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
326 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 266
267 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
268 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
269 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
270 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
271 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
272 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
273
274 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
275 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
276 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
277 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
278 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
279 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
280
281 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
327}; 282};
328 283
329int __init arch_clk_init(void) 284int __init arch_clk_init(void)
@@ -356,7 +311,7 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 311 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
357 312
358 if (!ret) 313 if (!ret)
359 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 314 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
360 315
361 return ret; 316 return ret;
362} 317}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 8668f557e0ac..b3c039a5064a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
29 29
30/* SH7724 registers */ 30/* SH7724 registers */
@@ -35,6 +35,9 @@
35#define FCLKBCR 0xa415000c 35#define FCLKBCR 0xa415000c
36#define IRDACLKCR 0xa4150018 36#define IRDACLKCR 0xa4150018
37#define PLLCR 0xa4150024 37#define PLLCR 0xa4150024
38#define MSTPCR0 0xa4150030
39#define MSTPCR1 0xa4150034
40#define MSTPCR2 0xa4150038
38#define SPUCLKCR 0xa415003c 41#define SPUCLKCR 0xa415003c
39#define FLLFRQ 0xa4150050 42#define FLLFRQ 0xa4150050
40#define LSTATS 0xa4150060 43#define LSTATS 0xa4150060
@@ -111,13 +114,16 @@ static struct clk div3_clk = {
111 .parent = &pll_clk, 114 .parent = &pll_clk,
112}; 115};
113 116
114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */ 117/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
115struct clk sh7724_fsimcka_clk = { 118struct clk sh7724_fsimcka_clk = {
116}; 119};
117 120
118struct clk sh7724_fsimckb_clk = { 121struct clk sh7724_fsimckb_clk = {
119}; 122};
120 123
124struct clk sh7724_dv_clki = {
125};
126
121static struct clk *main_clks[] = { 127static struct clk *main_clks[] = {
122 &r_clk, 128 &r_clk,
123 &extal_clk, 129 &extal_clk,
@@ -126,6 +132,7 @@ static struct clk *main_clks[] = {
126 &div3_clk, 132 &div3_clk,
127 &sh7724_fsimcka_clk, 133 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk, 134 &sh7724_fsimckb_clk,
135 &sh7724_dv_clki,
129}; 136};
130 137
131static void div4_kick(struct clk *clk) 138static void div4_kick(struct clk *clk)
@@ -163,17 +170,20 @@ struct clk div4_clks[DIV4_NR] = {
163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
164}; 171};
165 172
166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR }; 173enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };
167 174
168static struct clk div6_clks[DIV6_NR] = { 175/* Indices are important - they are the actual src selecting values */
169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 176static struct clk *common_parent[] = {
170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 177 [0] = &div3_clk,
171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 178 [1] = NULL,
172}; 179};
173 180
174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR }; 181static struct clk *vclkcr_parent[8] = {
182 [0] = &div3_clk,
183 [2] = &sh7724_dv_clki,
184 [4] = &extal_clk,
185};
175 186
176/* Indices are important - they are the actual src selecting values */
177static struct clk *fclkacr_parent[] = { 187static struct clk *fclkacr_parent[] = {
178 [0] = &div3_clk, 188 [0] = &div3_clk,
179 [1] = NULL, 189 [1] = NULL,
@@ -188,68 +198,74 @@ static struct clk *fclkbcr_parent[] = {
188 [3] = NULL, 198 [3] = NULL,
189}; 199};
190 200
191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 201static struct clk div6_clks[DIV6_NR] = {
192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0, 202 [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0,
203 vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3),
204 [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0,
205 common_parent, ARRAY_SIZE(common_parent), 6, 1),
206 [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
207 common_parent, ARRAY_SIZE(common_parent), 6, 1),
208 [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0,
193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), 209 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0, 210 [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0,
195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), 211 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
196}; 212};
197 213
198static struct clk mstp_clks[HWBLK_NR] = { 214static struct clk mstp_clks[HWBLK_NR] = {
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 215 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 216 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 217 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 218 [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 219 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 220 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 221 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 222 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 223 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 224 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 225 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 226 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 227 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 228 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 229 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 230 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 231 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 232 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 233 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 234 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 235 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 236 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 237 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 238 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 239 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
224 240
225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 241 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 242 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 243 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 244 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
229 245
230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 246 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 247 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 248 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 249 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 250 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 251 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 252 [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 253 [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 254 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 255 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 256 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 257 [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 258 [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 259 [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 260 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 261 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 262 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 263 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 264 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 265 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 266 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 267 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 268 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
253}; 269};
254 270
255static struct clk_lookup lookups[] = { 271static struct clk_lookup lookups[] = {
@@ -269,8 +285,8 @@ static struct clk_lookup lookups[] = {
269 285
270 /* DIV6 clocks */ 286 /* DIV6 clocks */
271 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 287 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
272 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]), 288 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
273 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]), 289 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
274 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 290 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
275 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 291 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
276 292
@@ -283,7 +299,7 @@ static struct clk_lookup lookups[] = {
283 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
284 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
285 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
286 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 302 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
287 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 303 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
288 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 304 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
289 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 305 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
@@ -294,26 +310,26 @@ static struct clk_lookup lookups[] = {
294 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]), 310 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
295 311
296 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 312 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
297 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 313 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
298 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 314 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
299 315
300 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]), 316 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
301 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]), 317 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
302 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 318 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
303 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 319 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
304 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 320 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
305 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), 321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
306 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), 322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
307 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), 323 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
308 324
309 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 325 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
310 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 326 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
311 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 327 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
312 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 328 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
313 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), 329 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
314 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), 330 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
315 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 331 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
316 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 332 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
317 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 333 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
318 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 334 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
319 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 335 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
@@ -321,20 +337,20 @@ static struct clk_lookup lookups[] = {
321 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 337 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
322 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 338 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
323 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 339 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
324 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 340 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
325 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 341 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
326 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 342 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
327 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 343 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
328 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 344 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
329 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 345 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
330 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 346 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
331 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 347 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
332 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 348 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
333 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 349 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
334 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 350 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
335 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 351 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
336 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 352 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
337 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 353 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
338}; 354};
339 355
340int __init arch_clk_init(void) 356int __init arch_clk_init(void)
@@ -356,13 +372,10 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 372 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
357 373
358 if (!ret) 374 if (!ret)
359 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 375 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
360
361 if (!ret)
362 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
363 376
364 if (!ret) 377 if (!ret)
365 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 378 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
366 379
367 return ret; 380 return ret;
368} 381}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 19222dae8233..0fbff1422f54 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -129,7 +129,7 @@ static struct clk_lookup lookups[] = {
129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]), 129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]),
130 130
131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]), 131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
132 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), 132 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), 133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
134}; 134};
135 135
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
deleted file mode 100644
index a288b5d92341..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3 *
4 * SH7722 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
27
28/* SH7722 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7722 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7722_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53 [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60 [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61 [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62 [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80 [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83};
84
85static struct hwblk_info sh7722_hwblk_info = {
86 .areas = sh7722_hwblk_area,
87 .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88 .hwblks = sh7722_hwblk,
89 .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90};
91
92int arch_hwblk_sleep_mode(void)
93{
94 if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95 return SUSP_SH_STANDBY | SUSP_SH_SF;
96
97 if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98 return SUSP_SH_SLEEP | SUSP_SH_SF;
99
100 return SUSP_SH_SLEEP;
101}
102
103int __init arch_hwblk_init(void)
104{
105 return hwblk_register(&sh7722_hwblk_info);
106}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
deleted file mode 100644
index a7f4684d2032..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
deleted file mode 100644
index 1613ad6013c3..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 278a0e572158..8420d4bc8bfc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -146,7 +146,7 @@ static struct resource sh7722_dmae_resources[] = {
146 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
147 }, 147 },
148 { 148 {
149 /* DMA error IRQ */ 149 .name = "error_irq",
150 .start = 78, 150 .start = 78,
151 .end = 78, 151 .end = 78,
152 .flags = IORESOURCE_IRQ, 152 .flags = IORESOURCE_IRQ,
@@ -173,9 +173,6 @@ struct platform_device dma_device = {
173 .dev = { 173 .dev = {
174 .platform_data = &dma_platform_data, 174 .platform_data = &dma_platform_data,
175 }, 175 },
176 .archdata = {
177 .hwblk_id = HWBLK_DMAC,
178 },
179}; 176};
180 177
181/* Serial */ 178/* Serial */
@@ -264,9 +261,6 @@ static struct platform_device rtc_device = {
264 .id = -1, 261 .id = -1,
265 .num_resources = ARRAY_SIZE(rtc_resources), 262 .num_resources = ARRAY_SIZE(rtc_resources),
266 .resource = rtc_resources, 263 .resource = rtc_resources,
267 .archdata = {
268 .hwblk_id = HWBLK_RTC,
269 },
270}; 264};
271 265
272static struct m66592_platdata usbf_platdata = { 266static struct m66592_platdata usbf_platdata = {
@@ -297,9 +291,6 @@ static struct platform_device usbf_device = {
297 }, 291 },
298 .num_resources = ARRAY_SIZE(usbf_resources), 292 .num_resources = ARRAY_SIZE(usbf_resources),
299 .resource = usbf_resources, 293 .resource = usbf_resources,
300 .archdata = {
301 .hwblk_id = HWBLK_USBF,
302 },
303}; 294};
304 295
305static struct resource iic_resources[] = { 296static struct resource iic_resources[] = {
@@ -321,9 +312,6 @@ static struct platform_device iic_device = {
321 .id = 0, /* "i2c0" clock */ 312 .id = 0, /* "i2c0" clock */
322 .num_resources = ARRAY_SIZE(iic_resources), 313 .num_resources = ARRAY_SIZE(iic_resources),
323 .resource = iic_resources, 314 .resource = iic_resources,
324 .archdata = {
325 .hwblk_id = HWBLK_IIC,
326 },
327}; 315};
328 316
329static struct uio_info vpu_platform_data = { 317static struct uio_info vpu_platform_data = {
@@ -352,9 +340,6 @@ static struct platform_device vpu_device = {
352 }, 340 },
353 .resource = vpu_resources, 341 .resource = vpu_resources,
354 .num_resources = ARRAY_SIZE(vpu_resources), 342 .num_resources = ARRAY_SIZE(vpu_resources),
355 .archdata = {
356 .hwblk_id = HWBLK_VPU,
357 },
358}; 343};
359 344
360static struct uio_info veu_platform_data = { 345static struct uio_info veu_platform_data = {
@@ -383,9 +368,6 @@ static struct platform_device veu_device = {
383 }, 368 },
384 .resource = veu_resources, 369 .resource = veu_resources,
385 .num_resources = ARRAY_SIZE(veu_resources), 370 .num_resources = ARRAY_SIZE(veu_resources),
386 .archdata = {
387 .hwblk_id = HWBLK_VEU,
388 },
389}; 371};
390 372
391static struct uio_info jpu_platform_data = { 373static struct uio_info jpu_platform_data = {
@@ -414,9 +396,6 @@ static struct platform_device jpu_device = {
414 }, 396 },
415 .resource = jpu_resources, 397 .resource = jpu_resources,
416 .num_resources = ARRAY_SIZE(jpu_resources), 398 .num_resources = ARRAY_SIZE(jpu_resources),
417 .archdata = {
418 .hwblk_id = HWBLK_JPU,
419 },
420}; 399};
421 400
422static struct sh_timer_config cmt_platform_data = { 401static struct sh_timer_config cmt_platform_data = {
@@ -446,9 +425,6 @@ static struct platform_device cmt_device = {
446 }, 425 },
447 .resource = cmt_resources, 426 .resource = cmt_resources,
448 .num_resources = ARRAY_SIZE(cmt_resources), 427 .num_resources = ARRAY_SIZE(cmt_resources),
449 .archdata = {
450 .hwblk_id = HWBLK_CMT,
451 },
452}; 428};
453 429
454static struct sh_timer_config tmu0_platform_data = { 430static struct sh_timer_config tmu0_platform_data = {
@@ -477,9 +453,6 @@ static struct platform_device tmu0_device = {
477 }, 453 },
478 .resource = tmu0_resources, 454 .resource = tmu0_resources,
479 .num_resources = ARRAY_SIZE(tmu0_resources), 455 .num_resources = ARRAY_SIZE(tmu0_resources),
480 .archdata = {
481 .hwblk_id = HWBLK_TMU,
482 },
483}; 456};
484 457
485static struct sh_timer_config tmu1_platform_data = { 458static struct sh_timer_config tmu1_platform_data = {
@@ -508,9 +481,6 @@ static struct platform_device tmu1_device = {
508 }, 481 },
509 .resource = tmu1_resources, 482 .resource = tmu1_resources,
510 .num_resources = ARRAY_SIZE(tmu1_resources), 483 .num_resources = ARRAY_SIZE(tmu1_resources),
511 .archdata = {
512 .hwblk_id = HWBLK_TMU,
513 },
514}; 484};
515 485
516static struct sh_timer_config tmu2_platform_data = { 486static struct sh_timer_config tmu2_platform_data = {
@@ -538,9 +508,6 @@ static struct platform_device tmu2_device = {
538 }, 508 },
539 .resource = tmu2_resources, 509 .resource = tmu2_resources,
540 .num_resources = ARRAY_SIZE(tmu2_resources), 510 .num_resources = ARRAY_SIZE(tmu2_resources),
541 .archdata = {
542 .hwblk_id = HWBLK_TMU,
543 },
544}; 511};
545 512
546static struct siu_platform siu_platform_data = { 513static struct siu_platform siu_platform_data = {
@@ -571,9 +538,6 @@ static struct platform_device siu_device = {
571 }, 538 },
572 .resource = siu_resources, 539 .resource = siu_resources,
573 .num_resources = ARRAY_SIZE(siu_resources), 540 .num_resources = ARRAY_SIZE(siu_resources),
574 .archdata = {
575 .hwblk_id = HWBLK_SIU,
576 },
577}; 541};
578 542
579static struct platform_device *sh7722_devices[] __initdata = { 543static struct platform_device *sh7722_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 3c2810d8f72e..a188c9ea4393 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -158,9 +158,6 @@ static struct platform_device vpu_device = {
158 }, 158 },
159 .resource = vpu_resources, 159 .resource = vpu_resources,
160 .num_resources = ARRAY_SIZE(vpu_resources), 160 .num_resources = ARRAY_SIZE(vpu_resources),
161 .archdata = {
162 .hwblk_id = HWBLK_VPU,
163 },
164}; 161};
165 162
166static struct uio_info veu0_platform_data = { 163static struct uio_info veu0_platform_data = {
@@ -189,9 +186,6 @@ static struct platform_device veu0_device = {
189 }, 186 },
190 .resource = veu0_resources, 187 .resource = veu0_resources,
191 .num_resources = ARRAY_SIZE(veu0_resources), 188 .num_resources = ARRAY_SIZE(veu0_resources),
192 .archdata = {
193 .hwblk_id = HWBLK_VEU2H0,
194 },
195}; 189};
196 190
197static struct uio_info veu1_platform_data = { 191static struct uio_info veu1_platform_data = {
@@ -220,9 +214,6 @@ static struct platform_device veu1_device = {
220 }, 214 },
221 .resource = veu1_resources, 215 .resource = veu1_resources,
222 .num_resources = ARRAY_SIZE(veu1_resources), 216 .num_resources = ARRAY_SIZE(veu1_resources),
223 .archdata = {
224 .hwblk_id = HWBLK_VEU2H1,
225 },
226}; 217};
227 218
228static struct sh_timer_config cmt_platform_data = { 219static struct sh_timer_config cmt_platform_data = {
@@ -252,9 +243,6 @@ static struct platform_device cmt_device = {
252 }, 243 },
253 .resource = cmt_resources, 244 .resource = cmt_resources,
254 .num_resources = ARRAY_SIZE(cmt_resources), 245 .num_resources = ARRAY_SIZE(cmt_resources),
255 .archdata = {
256 .hwblk_id = HWBLK_CMT,
257 },
258}; 246};
259 247
260static struct sh_timer_config tmu0_platform_data = { 248static struct sh_timer_config tmu0_platform_data = {
@@ -283,9 +271,6 @@ static struct platform_device tmu0_device = {
283 }, 271 },
284 .resource = tmu0_resources, 272 .resource = tmu0_resources,
285 .num_resources = ARRAY_SIZE(tmu0_resources), 273 .num_resources = ARRAY_SIZE(tmu0_resources),
286 .archdata = {
287 .hwblk_id = HWBLK_TMU0,
288 },
289}; 274};
290 275
291static struct sh_timer_config tmu1_platform_data = { 276static struct sh_timer_config tmu1_platform_data = {
@@ -314,9 +299,6 @@ static struct platform_device tmu1_device = {
314 }, 299 },
315 .resource = tmu1_resources, 300 .resource = tmu1_resources,
316 .num_resources = ARRAY_SIZE(tmu1_resources), 301 .num_resources = ARRAY_SIZE(tmu1_resources),
317 .archdata = {
318 .hwblk_id = HWBLK_TMU0,
319 },
320}; 302};
321 303
322static struct sh_timer_config tmu2_platform_data = { 304static struct sh_timer_config tmu2_platform_data = {
@@ -344,9 +326,6 @@ static struct platform_device tmu2_device = {
344 }, 326 },
345 .resource = tmu2_resources, 327 .resource = tmu2_resources,
346 .num_resources = ARRAY_SIZE(tmu2_resources), 328 .num_resources = ARRAY_SIZE(tmu2_resources),
347 .archdata = {
348 .hwblk_id = HWBLK_TMU0,
349 },
350}; 329};
351 330
352static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
@@ -374,9 +353,6 @@ static struct platform_device tmu3_device = {
374 }, 353 },
375 .resource = tmu3_resources, 354 .resource = tmu3_resources,
376 .num_resources = ARRAY_SIZE(tmu3_resources), 355 .num_resources = ARRAY_SIZE(tmu3_resources),
377 .archdata = {
378 .hwblk_id = HWBLK_TMU1,
379 },
380}; 356};
381 357
382static struct sh_timer_config tmu4_platform_data = { 358static struct sh_timer_config tmu4_platform_data = {
@@ -404,9 +380,6 @@ static struct platform_device tmu4_device = {
404 }, 380 },
405 .resource = tmu4_resources, 381 .resource = tmu4_resources,
406 .num_resources = ARRAY_SIZE(tmu4_resources), 382 .num_resources = ARRAY_SIZE(tmu4_resources),
407 .archdata = {
408 .hwblk_id = HWBLK_TMU1,
409 },
410}; 383};
411 384
412static struct sh_timer_config tmu5_platform_data = { 385static struct sh_timer_config tmu5_platform_data = {
@@ -434,9 +407,6 @@ static struct platform_device tmu5_device = {
434 }, 407 },
435 .resource = tmu5_resources, 408 .resource = tmu5_resources,
436 .num_resources = ARRAY_SIZE(tmu5_resources), 409 .num_resources = ARRAY_SIZE(tmu5_resources),
437 .archdata = {
438 .hwblk_id = HWBLK_TMU1,
439 },
440}; 410};
441 411
442static struct resource rtc_resources[] = { 412static struct resource rtc_resources[] = {
@@ -467,9 +437,6 @@ static struct platform_device rtc_device = {
467 .id = -1, 437 .id = -1,
468 .num_resources = ARRAY_SIZE(rtc_resources), 438 .num_resources = ARRAY_SIZE(rtc_resources),
469 .resource = rtc_resources, 439 .resource = rtc_resources,
470 .archdata = {
471 .hwblk_id = HWBLK_RTC,
472 },
473}; 440};
474 441
475static struct r8a66597_platdata r8a66597_data = { 442static struct r8a66597_platdata r8a66597_data = {
@@ -499,9 +466,6 @@ static struct platform_device sh7723_usb_host_device = {
499 }, 466 },
500 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 467 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
501 .resource = sh7723_usb_host_resources, 468 .resource = sh7723_usb_host_resources,
502 .archdata = {
503 .hwblk_id = HWBLK_USB,
504 },
505}; 469};
506 470
507static struct resource iic_resources[] = { 471static struct resource iic_resources[] = {
@@ -523,9 +487,6 @@ static struct platform_device iic_device = {
523 .id = 0, /* "i2c0" clock */ 487 .id = 0, /* "i2c0" clock */
524 .num_resources = ARRAY_SIZE(iic_resources), 488 .num_resources = ARRAY_SIZE(iic_resources),
525 .resource = iic_resources, 489 .resource = iic_resources,
526 .archdata = {
527 .hwblk_id = HWBLK_IIC,
528 },
529}; 490};
530 491
531static struct platform_device *sh7723_devices[] __initdata = { 492static struct platform_device *sh7723_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index a37dd72c3671..4c671cfe68aa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -214,7 +214,7 @@ static struct resource sh7724_dmae0_resources[] = {
214 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
215 }, 215 },
216 { 216 {
217 /* DMA error IRQ */ 217 .name = "error_irq",
218 .start = 78, 218 .start = 78,
219 .end = 78, 219 .end = 78,
220 .flags = IORESOURCE_IRQ, 220 .flags = IORESOURCE_IRQ,
@@ -248,7 +248,7 @@ static struct resource sh7724_dmae1_resources[] = {
248 .flags = IORESOURCE_MEM, 248 .flags = IORESOURCE_MEM,
249 }, 249 },
250 { 250 {
251 /* DMA error IRQ */ 251 .name = "error_irq",
252 .start = 74, 252 .start = 74,
253 .end = 74, 253 .end = 74,
254 .flags = IORESOURCE_IRQ, 254 .flags = IORESOURCE_IRQ,
@@ -275,9 +275,6 @@ static struct platform_device dma0_device = {
275 .dev = { 275 .dev = {
276 .platform_data = &dma_platform_data, 276 .platform_data = &dma_platform_data,
277 }, 277 },
278 .archdata = {
279 .hwblk_id = HWBLK_DMAC0,
280 },
281}; 278};
282 279
283static struct platform_device dma1_device = { 280static struct platform_device dma1_device = {
@@ -288,9 +285,6 @@ static struct platform_device dma1_device = {
288 .dev = { 285 .dev = {
289 .platform_data = &dma_platform_data, 286 .platform_data = &dma_platform_data,
290 }, 287 },
291 .archdata = {
292 .hwblk_id = HWBLK_DMAC1,
293 },
294}; 288};
295 289
296/* Serial */ 290/* Serial */
@@ -434,9 +428,6 @@ static struct platform_device rtc_device = {
434 .id = -1, 428 .id = -1,
435 .num_resources = ARRAY_SIZE(rtc_resources), 429 .num_resources = ARRAY_SIZE(rtc_resources),
436 .resource = rtc_resources, 430 .resource = rtc_resources,
437 .archdata = {
438 .hwblk_id = HWBLK_RTC,
439 },
440}; 431};
441 432
442/* I2C0 */ 433/* I2C0 */
@@ -459,9 +450,6 @@ static struct platform_device iic0_device = {
459 .id = 0, /* "i2c0" clock */ 450 .id = 0, /* "i2c0" clock */
460 .num_resources = ARRAY_SIZE(iic0_resources), 451 .num_resources = ARRAY_SIZE(iic0_resources),
461 .resource = iic0_resources, 452 .resource = iic0_resources,
462 .archdata = {
463 .hwblk_id = HWBLK_IIC0,
464 },
465}; 453};
466 454
467/* I2C1 */ 455/* I2C1 */
@@ -484,9 +472,6 @@ static struct platform_device iic1_device = {
484 .id = 1, /* "i2c1" clock */ 472 .id = 1, /* "i2c1" clock */
485 .num_resources = ARRAY_SIZE(iic1_resources), 473 .num_resources = ARRAY_SIZE(iic1_resources),
486 .resource = iic1_resources, 474 .resource = iic1_resources,
487 .archdata = {
488 .hwblk_id = HWBLK_IIC1,
489 },
490}; 475};
491 476
492/* VPU */ 477/* VPU */
@@ -516,9 +501,6 @@ static struct platform_device vpu_device = {
516 }, 501 },
517 .resource = vpu_resources, 502 .resource = vpu_resources,
518 .num_resources = ARRAY_SIZE(vpu_resources), 503 .num_resources = ARRAY_SIZE(vpu_resources),
519 .archdata = {
520 .hwblk_id = HWBLK_VPU,
521 },
522}; 504};
523 505
524/* VEU0 */ 506/* VEU0 */
@@ -548,9 +530,6 @@ static struct platform_device veu0_device = {
548 }, 530 },
549 .resource = veu0_resources, 531 .resource = veu0_resources,
550 .num_resources = ARRAY_SIZE(veu0_resources), 532 .num_resources = ARRAY_SIZE(veu0_resources),
551 .archdata = {
552 .hwblk_id = HWBLK_VEU0,
553 },
554}; 533};
555 534
556/* VEU1 */ 535/* VEU1 */
@@ -580,9 +559,6 @@ static struct platform_device veu1_device = {
580 }, 559 },
581 .resource = veu1_resources, 560 .resource = veu1_resources,
582 .num_resources = ARRAY_SIZE(veu1_resources), 561 .num_resources = ARRAY_SIZE(veu1_resources),
583 .archdata = {
584 .hwblk_id = HWBLK_VEU1,
585 },
586}; 562};
587 563
588/* BEU0 */ 564/* BEU0 */
@@ -612,9 +588,6 @@ static struct platform_device beu0_device = {
612 }, 588 },
613 .resource = beu0_resources, 589 .resource = beu0_resources,
614 .num_resources = ARRAY_SIZE(beu0_resources), 590 .num_resources = ARRAY_SIZE(beu0_resources),
615 .archdata = {
616 .hwblk_id = HWBLK_BEU0,
617 },
618}; 591};
619 592
620/* BEU1 */ 593/* BEU1 */
@@ -644,9 +617,6 @@ static struct platform_device beu1_device = {
644 }, 617 },
645 .resource = beu1_resources, 618 .resource = beu1_resources,
646 .num_resources = ARRAY_SIZE(beu1_resources), 619 .num_resources = ARRAY_SIZE(beu1_resources),
647 .archdata = {
648 .hwblk_id = HWBLK_BEU1,
649 },
650}; 620};
651 621
652static struct sh_timer_config cmt_platform_data = { 622static struct sh_timer_config cmt_platform_data = {
@@ -676,9 +646,6 @@ static struct platform_device cmt_device = {
676 }, 646 },
677 .resource = cmt_resources, 647 .resource = cmt_resources,
678 .num_resources = ARRAY_SIZE(cmt_resources), 648 .num_resources = ARRAY_SIZE(cmt_resources),
679 .archdata = {
680 .hwblk_id = HWBLK_CMT,
681 },
682}; 649};
683 650
684static struct sh_timer_config tmu0_platform_data = { 651static struct sh_timer_config tmu0_platform_data = {
@@ -707,9 +674,6 @@ static struct platform_device tmu0_device = {
707 }, 674 },
708 .resource = tmu0_resources, 675 .resource = tmu0_resources,
709 .num_resources = ARRAY_SIZE(tmu0_resources), 676 .num_resources = ARRAY_SIZE(tmu0_resources),
710 .archdata = {
711 .hwblk_id = HWBLK_TMU0,
712 },
713}; 677};
714 678
715static struct sh_timer_config tmu1_platform_data = { 679static struct sh_timer_config tmu1_platform_data = {
@@ -738,9 +702,6 @@ static struct platform_device tmu1_device = {
738 }, 702 },
739 .resource = tmu1_resources, 703 .resource = tmu1_resources,
740 .num_resources = ARRAY_SIZE(tmu1_resources), 704 .num_resources = ARRAY_SIZE(tmu1_resources),
741 .archdata = {
742 .hwblk_id = HWBLK_TMU0,
743 },
744}; 705};
745 706
746static struct sh_timer_config tmu2_platform_data = { 707static struct sh_timer_config tmu2_platform_data = {
@@ -768,9 +729,6 @@ static struct platform_device tmu2_device = {
768 }, 729 },
769 .resource = tmu2_resources, 730 .resource = tmu2_resources,
770 .num_resources = ARRAY_SIZE(tmu2_resources), 731 .num_resources = ARRAY_SIZE(tmu2_resources),
771 .archdata = {
772 .hwblk_id = HWBLK_TMU0,
773 },
774}; 732};
775 733
776 734
@@ -799,9 +757,6 @@ static struct platform_device tmu3_device = {
799 }, 757 },
800 .resource = tmu3_resources, 758 .resource = tmu3_resources,
801 .num_resources = ARRAY_SIZE(tmu3_resources), 759 .num_resources = ARRAY_SIZE(tmu3_resources),
802 .archdata = {
803 .hwblk_id = HWBLK_TMU1,
804 },
805}; 760};
806 761
807static struct sh_timer_config tmu4_platform_data = { 762static struct sh_timer_config tmu4_platform_data = {
@@ -829,9 +784,6 @@ static struct platform_device tmu4_device = {
829 }, 784 },
830 .resource = tmu4_resources, 785 .resource = tmu4_resources,
831 .num_resources = ARRAY_SIZE(tmu4_resources), 786 .num_resources = ARRAY_SIZE(tmu4_resources),
832 .archdata = {
833 .hwblk_id = HWBLK_TMU1,
834 },
835}; 787};
836 788
837static struct sh_timer_config tmu5_platform_data = { 789static struct sh_timer_config tmu5_platform_data = {
@@ -859,9 +811,6 @@ static struct platform_device tmu5_device = {
859 }, 811 },
860 .resource = tmu5_resources, 812 .resource = tmu5_resources,
861 .num_resources = ARRAY_SIZE(tmu5_resources), 813 .num_resources = ARRAY_SIZE(tmu5_resources),
862 .archdata = {
863 .hwblk_id = HWBLK_TMU1,
864 },
865}; 814};
866 815
867/* JPU */ 816/* JPU */
@@ -891,9 +840,6 @@ static struct platform_device jpu_device = {
891 }, 840 },
892 .resource = jpu_resources, 841 .resource = jpu_resources,
893 .num_resources = ARRAY_SIZE(jpu_resources), 842 .num_resources = ARRAY_SIZE(jpu_resources),
894 .archdata = {
895 .hwblk_id = HWBLK_JPU,
896 },
897}; 843};
898 844
899/* SPU2DSP0 */ 845/* SPU2DSP0 */
@@ -923,9 +869,6 @@ static struct platform_device spu0_device = {
923 }, 869 },
924 .resource = spu0_resources, 870 .resource = spu0_resources,
925 .num_resources = ARRAY_SIZE(spu0_resources), 871 .num_resources = ARRAY_SIZE(spu0_resources),
926 .archdata = {
927 .hwblk_id = HWBLK_SPU,
928 },
929}; 872};
930 873
931/* SPU2DSP1 */ 874/* SPU2DSP1 */
@@ -955,9 +898,6 @@ static struct platform_device spu1_device = {
955 }, 898 },
956 .resource = spu1_resources, 899 .resource = spu1_resources,
957 .num_resources = ARRAY_SIZE(spu1_resources), 900 .num_resources = ARRAY_SIZE(spu1_resources),
958 .archdata = {
959 .hwblk_id = HWBLK_SPU,
960 },
961}; 901};
962 902
963static struct platform_device *sh7724_devices[] __initdata = { 903static struct platform_device *sh7724_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 05559295d2ca..a7b2da6b3a1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -465,6 +465,7 @@ static struct resource sh7757_dmae0_resources[] = {
465 .flags = IORESOURCE_MEM, 465 .flags = IORESOURCE_MEM,
466 }, 466 },
467 { 467 {
468 .name = "error_irq",
468 .start = 34, 469 .start = 34,
469 .end = 34, 470 .end = 34,
470 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -486,7 +487,7 @@ static struct resource sh7757_dmae1_resources[] = {
486 .flags = IORESOURCE_MEM, 487 .flags = IORESOURCE_MEM,
487 }, 488 },
488 { 489 {
489 /* DMA error */ 490 .name = "error_irq",
490 .start = 34, 491 .start = 34,
491 .end = 34, 492 .end = 34,
492 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -556,7 +557,7 @@ static struct resource sh7757_dmae2_resources[] = {
556 .flags = IORESOURCE_MEM, 557 .flags = IORESOURCE_MEM,
557 }, 558 },
558 { 559 {
559 /* DMA error */ 560 .name = "error_irq",
560 .start = 323, 561 .start = 323,
561 .end = 323, 562 .end = 323,
562 .flags = IORESOURCE_IRQ, 563 .flags = IORESOURCE_IRQ,
@@ -590,7 +591,7 @@ static struct resource sh7757_dmae3_resources[] = {
590 .flags = IORESOURCE_MEM, 591 .flags = IORESOURCE_MEM,
591 }, 592 },
592 { 593 {
593 /* DMA error */ 594 .name = "error_irq",
594 .start = 324, 595 .start = 324,
595 .end = 324, 596 .end = 324,
596 .flags = IORESOURCE_IRQ, 597 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 3d4d2075c19a..d431b0052d0c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -322,6 +322,7 @@ static struct resource sh7780_dmae0_resources[] = {
322 }, 322 },
323 { 323 {
324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ 324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
325 .name = "error_irq",
325 .start = 34, 326 .start = 34,
326 .end = 34, 327 .end = 34,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 328 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -338,6 +339,7 @@ static struct resource sh7780_dmae1_resources[] = {
338 /* DMAC1 has no DMARS */ 339 /* DMAC1 has no DMARS */
339 { 340 {
340 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ 341 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
342 .name = "error_irq",
341 .start = 46, 343 .start = 46,
342 .end = 46, 344 .end = 46,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 345 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index b29e6340414a..81588ef15a6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -376,6 +376,7 @@ static struct resource sh7785_dmae0_resources[] = {
376 }, 376 },
377 { 377 {
378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ 378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
379 .name = "error_irq",
379 .start = 33, 380 .start = 33,
380 .end = 33, 381 .end = 33,
381 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 382 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -392,6 +393,7 @@ static struct resource sh7785_dmae1_resources[] = {
392 /* DMAC1 has no DMARS */ 393 /* DMAC1 has no DMARS */
393 { 394 {
394 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ 395 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
396 .name = "error_irq",
395 .start = 52, 397 .start = 52,
396 .end = 52, 398 .end = 52,
397 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 399 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index dd5e709f9821..599022d73b28 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -518,7 +518,7 @@ static struct resource dmac0_resources[] = {
518 .end = 0xfe00900b, 518 .end = 0xfe00900b,
519 .flags = IORESOURCE_MEM, 519 .flags = IORESOURCE_MEM,
520 }, { 520 }, {
521 /* DMA error IRQ */ 521 .name = "error_irq",
522 .start = evt2irq(0x5c0), 522 .start = evt2irq(0x5c0),
523 .end = evt2irq(0x5c0), 523 .end = evt2irq(0x5c0),
524 .flags = IORESOURCE_IRQ, 524 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index a39f88ea1a85..e8a5111e848a 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,4 +5,3 @@
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 1cc257c9b1e3..6d62eb40e750 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -17,7 +17,6 @@
17#include <linux/export.h> 17#include <linux/export.h>
18#include <asm/suspend.h> 18#include <asm/suspend.h>
19#include <asm/uaccess.h> 19#include <asm/uaccess.h>
20#include <asm/hwblk.h>
21 20
22static unsigned long cpuidle_mode[] = { 21static unsigned long cpuidle_mode[] = {
23 SUSP_SH_SLEEP, /* regular sleep mode */ 22 SUSP_SH_SLEEP, /* regular sleep mode */
@@ -29,7 +28,7 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
29 struct cpuidle_driver *drv, 28 struct cpuidle_driver *drv,
30 int index) 29 int index)
31{ 30{
32 unsigned long allowed_mode = arch_hwblk_sleep_mode(); 31 unsigned long allowed_mode = SUSP_SH_SLEEP;
33 ktime_t before, after; 32 ktime_t before, after;
34 int requested_state = index; 33 int requested_state = index;
35 int allowed_state; 34 int allowed_state;
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
deleted file mode 100644
index bf280c812d2f..000000000000
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/shmobile/pm_runtime.c
3 *
4 * Runtime PM support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18#include <asm/hwblk.h>
19
20static DEFINE_SPINLOCK(hwblk_lock);
21static LIST_HEAD(hwblk_idle_list);
22static struct work_struct hwblk_work;
23
24extern struct hwblk_info *hwblk_info;
25
26static void platform_pm_runtime_not_idle(struct platform_device *pdev)
27{
28 unsigned long flags;
29
30 /* remove device from idle list */
31 spin_lock_irqsave(&hwblk_lock, flags);
32 if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
33 list_del(&pdev->archdata.entry);
34 __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
35 }
36 spin_unlock_irqrestore(&hwblk_lock, flags);
37}
38
39static int __platform_pm_runtime_resume(struct platform_device *pdev)
40{
41 struct device *d = &pdev->dev;
42 struct pdev_archdata *ad = &pdev->archdata;
43 int hwblk = ad->hwblk_id;
44 int ret = -ENOSYS;
45
46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47
48 if (d->driver) {
49 hwblk_enable(hwblk_info, hwblk);
50 ret = 0;
51
52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53 if (d->driver->pm && d->driver->pm->runtime_resume)
54 ret = d->driver->pm->runtime_resume(d);
55
56 if (!ret)
57 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
58 else
59 hwblk_disable(hwblk_info, hwblk);
60 }
61 }
62
63 dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
64 hwblk, ret);
65
66 return ret;
67}
68
69static int __platform_pm_runtime_suspend(struct platform_device *pdev)
70{
71 struct device *d = &pdev->dev;
72 struct pdev_archdata *ad = &pdev->archdata;
73 int hwblk = ad->hwblk_id;
74 int ret = -ENOSYS;
75
76 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
77
78 if (d->driver) {
79 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
80 ret = 0;
81
82 if (d->driver->pm && d->driver->pm->runtime_suspend) {
83 hwblk_enable(hwblk_info, hwblk);
84 ret = d->driver->pm->runtime_suspend(d);
85 hwblk_disable(hwblk_info, hwblk);
86 }
87
88 if (!ret) {
89 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
90 platform_pm_runtime_not_idle(pdev);
91 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
92 }
93 }
94
95 dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
96 hwblk, ret);
97
98 return ret;
99}
100
101static void platform_pm_runtime_work(struct work_struct *work)
102{
103 struct platform_device *pdev;
104 unsigned long flags;
105 int ret;
106
107 /* go through the idle list and suspend one device at a time */
108 do {
109 spin_lock_irqsave(&hwblk_lock, flags);
110 if (list_empty(&hwblk_idle_list))
111 pdev = NULL;
112 else
113 pdev = list_first_entry(&hwblk_idle_list,
114 struct platform_device,
115 archdata.entry);
116 spin_unlock_irqrestore(&hwblk_lock, flags);
117
118 if (pdev) {
119 mutex_lock(&pdev->archdata.mutex);
120 ret = __platform_pm_runtime_suspend(pdev);
121
122 /* at this point the platform device may be:
123 * suspended: ret = 0, FLAG_SUSP set, clock stopped
124 * failed: ret < 0, FLAG_IDLE set, clock stopped
125 */
126 mutex_unlock(&pdev->archdata.mutex);
127 } else {
128 ret = -ENODEV;
129 }
130 } while (!ret);
131}
132
133/* this function gets called from cpuidle context when all devices in the
134 * main power domain are unused but some are counted as idle, ie the hwblk
135 * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
136 */
137void platform_pm_runtime_suspend_idle(void)
138{
139 queue_work(pm_wq, &hwblk_work);
140}
141
142static int default_platform_runtime_suspend(struct device *dev)
143{
144 struct platform_device *pdev = to_platform_device(dev);
145 struct pdev_archdata *ad = &pdev->archdata;
146 unsigned long flags;
147 int hwblk = ad->hwblk_id;
148 int ret = 0;
149
150 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
151
152 /* ignore off-chip platform devices */
153 if (!hwblk)
154 goto out;
155
156 /* interrupt context not allowed */
157 might_sleep();
158
159 /* catch misconfigured drivers not starting with resume */
160 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
161 ret = -EINVAL;
162 goto out;
163 }
164
165 /* serialize */
166 mutex_lock(&ad->mutex);
167
168 /* disable clock */
169 hwblk_disable(hwblk_info, hwblk);
170
171 /* put device on idle list */
172 spin_lock_irqsave(&hwblk_lock, flags);
173 list_add_tail(&ad->entry, &hwblk_idle_list);
174 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
175 spin_unlock_irqrestore(&hwblk_lock, flags);
176
177 /* increase idle count */
178 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
179
180 /* at this point the platform device is:
181 * idle: ret = 0, FLAG_IDLE set, clock stopped
182 */
183 mutex_unlock(&ad->mutex);
184
185out:
186 dev_dbg(dev, "%s() [%d] returns %d\n",
187 __func__, hwblk, ret);
188
189 return ret;
190}
191
192static int default_platform_runtime_resume(struct device *dev)
193{
194 struct platform_device *pdev = to_platform_device(dev);
195 struct pdev_archdata *ad = &pdev->archdata;
196 int hwblk = ad->hwblk_id;
197 int ret = 0;
198
199 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
200
201 /* ignore off-chip platform devices */
202 if (!hwblk)
203 goto out;
204
205 /* interrupt context not allowed */
206 might_sleep();
207
208 /* serialize */
209 mutex_lock(&ad->mutex);
210
211 /* make sure device is removed from idle list */
212 platform_pm_runtime_not_idle(pdev);
213
214 /* decrease idle count */
215 if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
216 !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
217 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
218
219 /* resume the device if needed */
220 ret = __platform_pm_runtime_resume(pdev);
221
222 /* the driver has been initialized now, so clear the init flag */
223 clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
224
225 /* at this point the platform device may be:
226 * resumed: ret = 0, flags = 0, clock started
227 * failed: ret < 0, FLAG_SUSP set, clock stopped
228 */
229 mutex_unlock(&ad->mutex);
230out:
231 dev_dbg(dev, "%s() [%d] returns %d\n",
232 __func__, hwblk, ret);
233
234 return ret;
235}
236
237static int default_platform_runtime_idle(struct device *dev)
238{
239 struct platform_device *pdev = to_platform_device(dev);
240 int hwblk = pdev->archdata.hwblk_id;
241 int ret = 0;
242
243 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
244
245 /* ignore off-chip platform devices */
246 if (!hwblk)
247 goto out;
248
249 /* interrupt context not allowed, use pm_runtime_put()! */
250 might_sleep();
251
252 /* suspend synchronously to disable clocks immediately */
253 ret = pm_runtime_suspend(dev);
254out:
255 dev_dbg(dev, "%s() [%d] done!\n", __func__, hwblk);
256 return ret;
257}
258
259static struct dev_pm_domain default_pm_domain = {
260 .ops = {
261 .runtime_suspend = default_platform_runtime_suspend,
262 .runtime_resume = default_platform_runtime_resume,
263 .runtime_idle = default_platform_runtime_idle,
264 USE_PLATFORM_PM_SLEEP_OPS
265 },
266};
267
268static int platform_bus_notify(struct notifier_block *nb,
269 unsigned long action, void *data)
270{
271 struct device *dev = data;
272 struct platform_device *pdev = to_platform_device(dev);
273 int hwblk = pdev->archdata.hwblk_id;
274
275 /* ignore off-chip platform devices */
276 if (!hwblk)
277 return 0;
278
279 switch (action) {
280 case BUS_NOTIFY_ADD_DEVICE:
281 INIT_LIST_HEAD(&pdev->archdata.entry);
282 mutex_init(&pdev->archdata.mutex);
283 /* platform devices without drivers should be disabled */
284 hwblk_enable(hwblk_info, hwblk);
285 hwblk_disable(hwblk_info, hwblk);
286 /* make sure driver re-inits itself once */
287 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
288 dev->pm_domain = &default_pm_domain;
289 break;
290 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
291 case BUS_NOTIFY_BOUND_DRIVER:
292 /* keep track of number of devices in use per hwblk */
293 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
294 break;
295 case BUS_NOTIFY_UNBOUND_DRIVER:
296 /* keep track of number of devices in use per hwblk */
297 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
298 /* make sure driver re-inits itself once */
299 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
300 break;
301 case BUS_NOTIFY_DEL_DEVICE:
302 dev->pm_domain = NULL;
303 break;
304 }
305 return 0;
306}
307
308static struct notifier_block platform_bus_notifier = {
309 .notifier_call = platform_bus_notify
310};
311
312static int __init sh_pm_runtime_init(void)
313{
314 INIT_WORK(&hwblk_work, platform_pm_runtime_work);
315
316 bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
317 return 0;
318}
319core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 2b15ae60c3a0..f67601cb3f1f 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -145,6 +145,7 @@ work_notifysig:
145 mov r15, r4 145 mov r15, r4
146 mov r12, r5 ! set arg1(save_r0) 146 mov r12, r5 ! set arg1(save_r0)
147 mov r0, r6 147 mov r0, r6
148 sti
148 mov.l 2f, r1 149 mov.l 2f, r1
149 mov.l 3f, r0 150 mov.l 3f, r0
150 jmp @r1 151 jmp @r1
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 579cd2ca358d..a7a55ed43a59 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -588,9 +588,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
588 if (!user_mode(regs)) 588 if (!user_mode(regs))
589 return; 589 return;
590 590
591 if (try_to_freeze())
592 goto no_signal;
593
594 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 591 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
595 oldset = &current->saved_sigmask; 592 oldset = &current->saved_sigmask;
596 else 593 else
@@ -618,7 +615,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
618 return; 615 return;
619 } 616 }
620 617
621no_signal:
622 /* Did we come from a system call? */ 618 /* Did we come from a system call? */
623 if (regs->tra >= 0) { 619 if (regs->tra >= 0) {
624 /* Restart the system call - no handlers present */ 620 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 5a9f1f10ebf4..6b5603fe274b 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -98,9 +98,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
98 if (!user_mode(regs)) 98 if (!user_mode(regs))
99 return 1; 99 return 1;
100 100
101 if (try_to_freeze())
102 goto no_signal;
103
104 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 101 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
105 oldset = &current->saved_sigmask; 102 oldset = &current->saved_sigmask;
106 else if (!oldset) 103 else if (!oldset)
@@ -125,7 +122,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
125 } 122 }
126 } 123 }
127 124
128no_signal:
129 /* Did we come from a system call? */ 125 /* Did we come from a system call? */
130 if (regs->syscall_nr >= 0) { 126 if (regs->syscall_nr >= 0) {
131 /* Restart the system call - no handlers present */ 127 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 8a0072de2bcc..552c8fcf9416 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -21,7 +21,6 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <asm/clock.h> 23#include <asm/clock.h>
24#include <asm/hwblk.h>
25#include <asm/rtc.h> 24#include <asm/rtc.h>
26 25
27/* Dummy RTC ops */ 26/* Dummy RTC ops */
@@ -110,7 +109,6 @@ void __init time_init(void)
110 if (board_time_init) 109 if (board_time_init)
111 board_time_init(); 110 board_time_init();
112 111
113 hwblk_init();
114 clk_init(); 112 clk_init();
115 113
116 late_time_init = sh_late_time_init; 114 late_time_init = sh_late_time_init;
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 1f51225426a2..ae08cbbfa569 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -15,35 +15,78 @@
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/io.h> 16#include <asm/io.h>
17 17
18/*
19 * The maximum number of pages we support up to when doing ranged dcache
20 * flushing. Anything exceeding this will simply flush the dcache in its
21 * entirety.
22 */
23#define MAX_OCACHE_PAGES 32
24#define MAX_ICACHE_PAGES 32
25
26static void sh2a_flush_oc_line(unsigned long v, int way)
27{
28 unsigned long addr = (v & 0x000007f0) | (way << 11);
29 unsigned long data;
30
31 data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
33 data &= ~SH_CACHE_UPDATED;
34 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
35 }
36}
37
38static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
39{
40 /* Set associative bit to hit all ways */
41 unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
42 __raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
43}
44
45/*
46 * Write back the dirty D-caches, but not invalidate them.
47 */
18static void sh2a__flush_wback_region(void *start, int size) 48static void sh2a__flush_wback_region(void *start, int size)
19{ 49{
50#ifdef CONFIG_CACHE_WRITEBACK
20 unsigned long v; 51 unsigned long v;
21 unsigned long begin, end; 52 unsigned long begin, end;
22 unsigned long flags; 53 unsigned long flags;
54 int nr_ways;
23 55
24 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 56 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
25 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 57 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
26 & ~(L1_CACHE_BYTES-1); 58 & ~(L1_CACHE_BYTES-1);
59 nr_ways = current_cpu_data.dcache.ways;
27 60
28 local_irq_save(flags); 61 local_irq_save(flags);
29 jump_to_uncached(); 62 jump_to_uncached();
30 63
31 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 64 /* If there are too many pages then flush the entire cache */
32 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0); 65 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
66 begin = CACHE_OC_ADDRESS_ARRAY;
67 end = begin + (nr_ways * current_cpu_data.dcache.way_size);
68
69 for (v = begin; v < end; v += L1_CACHE_BYTES) {
70 unsigned long data = __raw_readl(v);
71 if (data & SH_CACHE_UPDATED)
72 __raw_writel(data & ~SH_CACHE_UPDATED, v);
73 }
74 } else {
33 int way; 75 int way;
34 for (way = 0; way < 4; way++) { 76 for (way = 0; way < nr_ways; way++) {
35 unsigned long data = __raw_readl(addr | (way << 11)); 77 for (v = begin; v < end; v += L1_CACHE_BYTES)
36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 78 sh2a_flush_oc_line(v, way);
37 data &= ~SH_CACHE_UPDATED;
38 __raw_writel(data, addr | (way << 11));
39 }
40 } 79 }
41 } 80 }
42 81
43 back_to_cached(); 82 back_to_cached();
44 local_irq_restore(flags); 83 local_irq_restore(flags);
84#endif
45} 85}
46 86
87/*
88 * Write back the dirty D-caches and invalidate them.
89 */
47static void sh2a__flush_purge_region(void *start, int size) 90static void sh2a__flush_purge_region(void *start, int size)
48{ 91{
49 unsigned long v; 92 unsigned long v;
@@ -58,13 +101,22 @@ static void sh2a__flush_purge_region(void *start, int size)
58 jump_to_uncached(); 101 jump_to_uncached();
59 102
60 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 103 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
61 __raw_writel((v & CACHE_PHYSADDR_MASK), 104#ifdef CONFIG_CACHE_WRITEBACK
62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 105 int way;
106 int nr_ways = current_cpu_data.dcache.ways;
107 for (way = 0; way < nr_ways; way++)
108 sh2a_flush_oc_line(v, way);
109#endif
110 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
63 } 111 }
112
64 back_to_cached(); 113 back_to_cached();
65 local_irq_restore(flags); 114 local_irq_restore(flags);
66} 115}
67 116
117/*
118 * Invalidate the D-caches, but no write back please
119 */
68static void sh2a__flush_invalidate_region(void *start, int size) 120static void sh2a__flush_invalidate_region(void *start, int size)
69{ 121{
70 unsigned long v; 122 unsigned long v;
@@ -74,29 +126,25 @@ static void sh2a__flush_invalidate_region(void *start, int size)
74 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 126 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
75 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 127 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
76 & ~(L1_CACHE_BYTES-1); 128 & ~(L1_CACHE_BYTES-1);
129
77 local_irq_save(flags); 130 local_irq_save(flags);
78 jump_to_uncached(); 131 jump_to_uncached();
79 132
80#ifdef CONFIG_CACHE_WRITEBACK 133 /* If there are too many pages then just blow the cache */
81 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); 134 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
82 /* I-cache invalidate */ 135 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
83 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 136 } else {
84 __raw_writel((v & CACHE_PHYSADDR_MASK), 137 for (v = begin; v < end; v += L1_CACHE_BYTES)
85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 138 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
86 }
87#else
88 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
89 __raw_writel((v & CACHE_PHYSADDR_MASK),
90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
91 __raw_writel((v & CACHE_PHYSADDR_MASK),
92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
93 } 139 }
94#endif 140
95 back_to_cached(); 141 back_to_cached();
96 local_irq_restore(flags); 142 local_irq_restore(flags);
97} 143}
98 144
99/* WBack O-Cache and flush I-Cache */ 145/*
146 * Write back the range of D-cache, and purge the I-cache.
147 */
100static void sh2a_flush_icache_range(void *args) 148static void sh2a_flush_icache_range(void *args)
101{ 149{
102 struct flusher_data *data = args; 150 struct flusher_data *data = args;
@@ -107,23 +155,20 @@ static void sh2a_flush_icache_range(void *args)
107 start = data->addr1 & ~(L1_CACHE_BYTES-1); 155 start = data->addr1 & ~(L1_CACHE_BYTES-1);
108 end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1); 156 end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
109 157
158#ifdef CONFIG_CACHE_WRITEBACK
159 sh2a__flush_wback_region((void *)start, end-start);
160#endif
161
110 local_irq_save(flags); 162 local_irq_save(flags);
111 jump_to_uncached(); 163 jump_to_uncached();
112 164
113 for (v = start; v < end; v+=L1_CACHE_BYTES) { 165 /* I-Cache invalidate */
114 unsigned long addr = (v & 0x000007f0); 166 /* If there are too many pages then just blow the cache */
115 int way; 167 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
116 /* O-Cache writeback */ 168 __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR);
117 for (way = 0; way < 4; way++) { 169 } else {
118 unsigned long data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); 170 for (v = start; v < end; v += L1_CACHE_BYTES)
119 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 171 sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
120 data &= ~SH_CACHE_UPDATED;
121 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
122 }
123 }
124 /* I-Cache invalidate */
125 __raw_writel(addr,
126 CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
127 } 172 }
128 173
129 back_to_cached(); 174 back_to_cached();
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 67e272ab1623..7139ad2f2086 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -7,11 +7,4 @@ obj-$(CONFIG_HAVE_CLK) += clk/
7obj-$(CONFIG_MAPLE) += maple/ 7obj-$(CONFIG_MAPLE) += maple/
8obj-$(CONFIG_SUPERHYWAY) += superhyway/ 8obj-$(CONFIG_SUPERHYWAY) += superhyway/
9obj-$(CONFIG_GENERIC_GPIO) += pfc.o 9obj-$(CONFIG_GENERIC_GPIO) += pfc.o
10 10obj-y += pm_runtime.o
11#
12# For the moment we only use this framework for ARM-based SH/R-Mobile
13# platforms and generic SH. SH-based SH-Mobile platforms are still using
14# an older framework that is pending up-porting, at which point this
15# special casing can go away.
16#
17obj-$(CONFIG_SUPERH)$(CONFIG_ARCH_SHMOBILE) += pm_runtime.o
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c
index db257a35e71a..7715de2629c1 100644
--- a/drivers/sh/clk/core.c
+++ b/drivers/sh/clk/core.c
@@ -355,7 +355,7 @@ static int clk_establish_mapping(struct clk *clk)
355 */ 355 */
356 if (!clk->parent) { 356 if (!clk->parent) {
357 clk->mapping = &dummy_mapping; 357 clk->mapping = &dummy_mapping;
358 return 0; 358 goto out;
359 } 359 }
360 360
361 /* 361 /*
@@ -384,6 +384,9 @@ static int clk_establish_mapping(struct clk *clk)
384 } 384 }
385 385
386 clk->mapping = mapping; 386 clk->mapping = mapping;
387out:
388 clk->mapped_reg = clk->mapping->base;
389 clk->mapped_reg += (phys_addr_t)clk->enable_reg - clk->mapping->phys;
387 return 0; 390 return 0;
388} 391}
389 392
@@ -402,10 +405,12 @@ static void clk_teardown_mapping(struct clk *clk)
402 405
403 /* Nothing to do */ 406 /* Nothing to do */
404 if (mapping == &dummy_mapping) 407 if (mapping == &dummy_mapping)
405 return; 408 goto out;
406 409
407 kref_put(&mapping->ref, clk_destroy_mapping); 410 kref_put(&mapping->ref, clk_destroy_mapping);
408 clk->mapping = NULL; 411 clk->mapping = NULL;
412out:
413 clk->mapped_reg = NULL;
409} 414}
410 415
411int clk_register(struct clk *clk) 416int clk_register(struct clk *clk)
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 82dd6fb17838..45fee368b092 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -15,15 +15,15 @@
15 15
16static int sh_clk_mstp32_enable(struct clk *clk) 16static int sh_clk_mstp32_enable(struct clk *clk)
17{ 17{
18 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit), 18 iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
19 clk->enable_reg); 19 clk->mapped_reg);
20 return 0; 20 return 0;
21} 21}
22 22
23static void sh_clk_mstp32_disable(struct clk *clk) 23static void sh_clk_mstp32_disable(struct clk *clk)
24{ 24{
25 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit), 25 iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
26 clk->enable_reg); 26 clk->mapped_reg);
27} 27}
28 28
29static struct clk_ops sh_clk_mstp32_clk_ops = { 29static struct clk_ops sh_clk_mstp32_clk_ops = {
@@ -72,7 +72,7 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
72 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 72 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
73 table, NULL); 73 table, NULL);
74 74
75 idx = __raw_readl(clk->enable_reg) & 0x003f; 75 idx = ioread32(clk->mapped_reg) & 0x003f;
76 76
77 return clk->freq_table[idx].frequency; 77 return clk->freq_table[idx].frequency;
78} 78}
@@ -98,10 +98,10 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
98 if (ret < 0) 98 if (ret < 0)
99 return ret; 99 return ret;
100 100
101 value = __raw_readl(clk->enable_reg) & 101 value = ioread32(clk->mapped_reg) &
102 ~(((1 << clk->src_width) - 1) << clk->src_shift); 102 ~(((1 << clk->src_width) - 1) << clk->src_shift);
103 103
104 __raw_writel(value | (i << clk->src_shift), clk->enable_reg); 104 iowrite32(value | (i << clk->src_shift), clk->mapped_reg);
105 105
106 /* Rebuild the frequency table */ 106 /* Rebuild the frequency table */
107 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 107 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -119,10 +119,10 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
119 if (idx < 0) 119 if (idx < 0)
120 return idx; 120 return idx;
121 121
122 value = __raw_readl(clk->enable_reg); 122 value = ioread32(clk->mapped_reg);
123 value &= ~0x3f; 123 value &= ~0x3f;
124 value |= idx; 124 value |= idx;
125 __raw_writel(value, clk->enable_reg); 125 iowrite32(value, clk->mapped_reg);
126 return 0; 126 return 0;
127} 127}
128 128
@@ -133,9 +133,9 @@ static int sh_clk_div6_enable(struct clk *clk)
133 133
134 ret = sh_clk_div6_set_rate(clk, clk->rate); 134 ret = sh_clk_div6_set_rate(clk, clk->rate);
135 if (ret == 0) { 135 if (ret == 0) {
136 value = __raw_readl(clk->enable_reg); 136 value = ioread32(clk->mapped_reg);
137 value &= ~0x100; /* clear stop bit to enable clock */ 137 value &= ~0x100; /* clear stop bit to enable clock */
138 __raw_writel(value, clk->enable_reg); 138 iowrite32(value, clk->mapped_reg);
139 } 139 }
140 return ret; 140 return ret;
141} 141}
@@ -144,10 +144,10 @@ static void sh_clk_div6_disable(struct clk *clk)
144{ 144{
145 unsigned long value; 145 unsigned long value;
146 146
147 value = __raw_readl(clk->enable_reg); 147 value = ioread32(clk->mapped_reg);
148 value |= 0x100; /* stop clock */ 148 value |= 0x100; /* stop clock */
149 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ 149 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
150 __raw_writel(value, clk->enable_reg); 150 iowrite32(value, clk->mapped_reg);
151} 151}
152 152
153static struct clk_ops sh_clk_div6_clk_ops = { 153static struct clk_ops sh_clk_div6_clk_ops = {
@@ -167,6 +167,38 @@ static struct clk_ops sh_clk_div6_reparent_clk_ops = {
167 .set_parent = sh_clk_div6_set_parent, 167 .set_parent = sh_clk_div6_set_parent,
168}; 168};
169 169
170static int __init sh_clk_init_parent(struct clk *clk)
171{
172 u32 val;
173
174 if (clk->parent)
175 return 0;
176
177 if (!clk->parent_table || !clk->parent_num)
178 return 0;
179
180 if (!clk->src_width) {
181 pr_err("sh_clk_init_parent: cannot select parent clock\n");
182 return -EINVAL;
183 }
184
185 val = (ioread32(clk->mapped_reg) >> clk->src_shift);
186 val &= (1 << clk->src_width) - 1;
187
188 if (val >= clk->parent_num) {
189 pr_err("sh_clk_init_parent: parent table size failed\n");
190 return -EINVAL;
191 }
192
193 clk->parent = clk->parent_table[val];
194 if (!clk->parent) {
195 pr_err("sh_clk_init_parent: unable to set parent");
196 return -EINVAL;
197 }
198
199 return 0;
200}
201
170static int __init sh_clk_div6_register_ops(struct clk *clks, int nr, 202static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
171 struct clk_ops *ops) 203 struct clk_ops *ops)
172{ 204{
@@ -190,8 +222,11 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
190 clkp->ops = ops; 222 clkp->ops = ops;
191 clkp->freq_table = freq_table + (k * freq_table_size); 223 clkp->freq_table = freq_table + (k * freq_table_size);
192 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; 224 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
193
194 ret = clk_register(clkp); 225 ret = clk_register(clkp);
226 if (ret < 0)
227 break;
228
229 ret = sh_clk_init_parent(clkp);
195 } 230 }
196 231
197 return ret; 232 return ret;
@@ -217,7 +252,7 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
217 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 252 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
218 table, &clk->arch_flags); 253 table, &clk->arch_flags);
219 254
220 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f; 255 idx = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0x000f;
221 256
222 return clk->freq_table[idx].frequency; 257 return clk->freq_table[idx].frequency;
223} 258}
@@ -235,15 +270,15 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
235 */ 270 */
236 271
237 if (parent->flags & CLK_ENABLE_ON_INIT) 272 if (parent->flags & CLK_ENABLE_ON_INIT)
238 value = __raw_readl(clk->enable_reg) & ~(1 << 7); 273 value = ioread32(clk->mapped_reg) & ~(1 << 7);
239 else 274 else
240 value = __raw_readl(clk->enable_reg) | (1 << 7); 275 value = ioread32(clk->mapped_reg) | (1 << 7);
241 276
242 ret = clk_reparent(clk, parent); 277 ret = clk_reparent(clk, parent);
243 if (ret < 0) 278 if (ret < 0)
244 return ret; 279 return ret;
245 280
246 __raw_writel(value, clk->enable_reg); 281 iowrite32(value, clk->mapped_reg);
247 282
248 /* Rebiuld the frequency table */ 283 /* Rebiuld the frequency table */
249 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 284 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -260,10 +295,10 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
260 if (idx < 0) 295 if (idx < 0)
261 return idx; 296 return idx;
262 297
263 value = __raw_readl(clk->enable_reg); 298 value = ioread32(clk->mapped_reg);
264 value &= ~(0xf << clk->enable_bit); 299 value &= ~(0xf << clk->enable_bit);
265 value |= (idx << clk->enable_bit); 300 value |= (idx << clk->enable_bit);
266 __raw_writel(value, clk->enable_reg); 301 iowrite32(value, clk->mapped_reg);
267 302
268 if (d4t->kick) 303 if (d4t->kick)
269 d4t->kick(clk); 304 d4t->kick(clk);
@@ -273,13 +308,13 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
273 308
274static int sh_clk_div4_enable(struct clk *clk) 309static int sh_clk_div4_enable(struct clk *clk)
275{ 310{
276 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg); 311 iowrite32(ioread32(clk->mapped_reg) & ~(1 << 8), clk->mapped_reg);
277 return 0; 312 return 0;
278} 313}
279 314
280static void sh_clk_div4_disable(struct clk *clk) 315static void sh_clk_div4_disable(struct clk *clk)
281{ 316{
282 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg); 317 iowrite32(ioread32(clk->mapped_reg) | (1 << 8), clk->mapped_reg);
283} 318}
284 319
285static struct clk_ops sh_clk_div4_clk_ops = { 320static struct clk_ops sh_clk_div4_clk_ops = {
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
index e67fe170d8d5..e7d127a9c1c5 100644
--- a/drivers/sh/pfc.c
+++ b/drivers/sh/pfc.c
@@ -19,6 +19,75 @@
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <linux/slab.h>
23#include <linux/ioport.h>
24
25static void pfc_iounmap(struct pinmux_info *pip)
26{
27 int k;
28
29 for (k = 0; k < pip->num_resources; k++)
30 if (pip->window[k].virt)
31 iounmap(pip->window[k].virt);
32
33 kfree(pip->window);
34 pip->window = NULL;
35}
36
37static int pfc_ioremap(struct pinmux_info *pip)
38{
39 struct resource *res;
40 int k;
41
42 if (!pip->num_resources)
43 return 0;
44
45 pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
46 GFP_NOWAIT);
47 if (!pip->window)
48 goto err1;
49
50 for (k = 0; k < pip->num_resources; k++) {
51 res = pip->resource + k;
52 WARN_ON(resource_type(res) != IORESOURCE_MEM);
53 pip->window[k].phys = res->start;
54 pip->window[k].size = resource_size(res);
55 pip->window[k].virt = ioremap_nocache(res->start,
56 resource_size(res));
57 if (!pip->window[k].virt)
58 goto err2;
59 }
60
61 return 0;
62
63err2:
64 pfc_iounmap(pip);
65err1:
66 return -1;
67}
68
69static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
70 unsigned long address)
71{
72 struct pfc_window *window;
73 int k;
74
75 /* scan through physical windows and convert address */
76 for (k = 0; k < pip->num_resources; k++) {
77 window = pip->window + k;
78
79 if (address < window->phys)
80 continue;
81
82 if (address >= (window->phys + window->size))
83 continue;
84
85 return window->virt + (address - window->phys);
86 }
87
88 /* no windows defined, register must be 1:1 mapped virt:phys */
89 return (void __iomem *)address;
90}
22 91
23static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) 92static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
24{ 93{
@@ -31,35 +100,35 @@ static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
31 return 1; 100 return 1;
32} 101}
33 102
34static unsigned long gpio_read_raw_reg(unsigned long reg, 103static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
35 unsigned long reg_width) 104 unsigned long reg_width)
36{ 105{
37 switch (reg_width) { 106 switch (reg_width) {
38 case 8: 107 case 8:
39 return __raw_readb(reg); 108 return ioread8(mapped_reg);
40 case 16: 109 case 16:
41 return __raw_readw(reg); 110 return ioread16(mapped_reg);
42 case 32: 111 case 32:
43 return __raw_readl(reg); 112 return ioread32(mapped_reg);
44 } 113 }
45 114
46 BUG(); 115 BUG();
47 return 0; 116 return 0;
48} 117}
49 118
50static void gpio_write_raw_reg(unsigned long reg, 119static void gpio_write_raw_reg(void __iomem *mapped_reg,
51 unsigned long reg_width, 120 unsigned long reg_width,
52 unsigned long data) 121 unsigned long data)
53{ 122{
54 switch (reg_width) { 123 switch (reg_width) {
55 case 8: 124 case 8:
56 __raw_writeb(data, reg); 125 iowrite8(data, mapped_reg);
57 return; 126 return;
58 case 16: 127 case 16:
59 __raw_writew(data, reg); 128 iowrite16(data, mapped_reg);
60 return; 129 return;
61 case 32: 130 case 32:
62 __raw_writel(data, reg); 131 iowrite32(data, mapped_reg);
63 return; 132 return;
64 } 133 }
65 134
@@ -82,11 +151,12 @@ static void gpio_write_bit(struct pinmux_data_reg *dr,
82 else 151 else
83 clear_bit(pos, &dr->reg_shadow); 152 clear_bit(pos, &dr->reg_shadow);
84 153
85 gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow); 154 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
86} 155}
87 156
88static int gpio_read_reg(unsigned long reg, unsigned long reg_width, 157static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width,
89 unsigned long field_width, unsigned long in_pos) 158 unsigned long field_width, unsigned long in_pos,
159 unsigned long reg)
90{ 160{
91 unsigned long data, mask, pos; 161 unsigned long data, mask, pos;
92 162
@@ -98,13 +168,13 @@ static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
98 "r_width = %ld, f_width = %ld\n", 168 "r_width = %ld, f_width = %ld\n",
99 reg, pos, reg_width, field_width); 169 reg, pos, reg_width, field_width);
100 170
101 data = gpio_read_raw_reg(reg, reg_width); 171 data = gpio_read_raw_reg(mapped_reg, reg_width);
102 return (data >> pos) & mask; 172 return (data >> pos) & mask;
103} 173}
104 174
105static void gpio_write_reg(unsigned long reg, unsigned long reg_width, 175static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width,
106 unsigned long field_width, unsigned long in_pos, 176 unsigned long field_width, unsigned long in_pos,
107 unsigned long value) 177 unsigned long value, unsigned long reg)
108{ 178{
109 unsigned long mask, pos; 179 unsigned long mask, pos;
110 180
@@ -120,13 +190,13 @@ static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
120 190
121 switch (reg_width) { 191 switch (reg_width) {
122 case 8: 192 case 8:
123 __raw_writeb((__raw_readb(reg) & mask) | value, reg); 193 iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg);
124 break; 194 break;
125 case 16: 195 case 16:
126 __raw_writew((__raw_readw(reg) & mask) | value, reg); 196 iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg);
127 break; 197 break;
128 case 32: 198 case 32:
129 __raw_writel((__raw_readl(reg) & mask) | value, reg); 199 iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg);
130 break; 200 break;
131 } 201 }
132} 202}
@@ -147,6 +217,8 @@ static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
147 if (!data_reg->reg_width) 217 if (!data_reg->reg_width)
148 break; 218 break;
149 219
220 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
221
150 for (n = 0; n < data_reg->reg_width; n++) { 222 for (n = 0; n < data_reg->reg_width; n++) {
151 if (data_reg->enum_ids[n] == gpiop->enum_id) { 223 if (data_reg->enum_ids[n] == gpiop->enum_id) {
152 gpiop->flags &= ~PINMUX_FLAG_DREG; 224 gpiop->flags &= ~PINMUX_FLAG_DREG;
@@ -179,7 +251,8 @@ static void setup_data_regs(struct pinmux_info *gpioc)
179 if (!drp->reg_width) 251 if (!drp->reg_width)
180 break; 252 break;
181 253
182 drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width); 254 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
255 drp->reg_width);
183 k++; 256 k++;
184 } 257 }
185} 258}
@@ -266,12 +339,16 @@ static void write_config_reg(struct pinmux_info *gpioc,
266 int index) 339 int index)
267{ 340{
268 unsigned long ncomb, pos, value; 341 unsigned long ncomb, pos, value;
342 void __iomem *mapped_reg;
269 343
270 ncomb = 1 << crp->field_width; 344 ncomb = 1 << crp->field_width;
271 pos = index / ncomb; 345 pos = index / ncomb;
272 value = index % ncomb; 346 value = index % ncomb;
273 347
274 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value); 348 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
349
350 gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
351 pos, value, crp->reg);
275} 352}
276 353
277static int check_config_reg(struct pinmux_info *gpioc, 354static int check_config_reg(struct pinmux_info *gpioc,
@@ -279,13 +356,16 @@ static int check_config_reg(struct pinmux_info *gpioc,
279 int index) 356 int index)
280{ 357{
281 unsigned long ncomb, pos, value; 358 unsigned long ncomb, pos, value;
359 void __iomem *mapped_reg;
282 360
283 ncomb = 1 << crp->field_width; 361 ncomb = 1 << crp->field_width;
284 pos = index / ncomb; 362 pos = index / ncomb;
285 value = index % ncomb; 363 value = index % ncomb;
286 364
287 if (gpio_read_reg(crp->reg, crp->reg_width, 365 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
288 crp->field_width, pos) == value) 366
367 if (gpio_read_reg(mapped_reg, crp->reg_width,
368 crp->field_width, pos, crp->reg) == value)
289 return 0; 369 return 0;
290 370
291 return -1; 371 return -1;
@@ -564,7 +644,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
564 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) 644 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
565 return -EINVAL; 645 return -EINVAL;
566 646
567 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit); 647 return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg);
568} 648}
569 649
570static int sh_gpio_get(struct gpio_chip *chip, unsigned offset) 650static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -606,10 +686,15 @@ static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
606int register_pinmux(struct pinmux_info *pip) 686int register_pinmux(struct pinmux_info *pip)
607{ 687{
608 struct gpio_chip *chip = &pip->chip; 688 struct gpio_chip *chip = &pip->chip;
689 int ret;
609 690
610 pr_info("%s handling gpio %d -> %d\n", 691 pr_info("%s handling gpio %d -> %d\n",
611 pip->name, pip->first_gpio, pip->last_gpio); 692 pip->name, pip->first_gpio, pip->last_gpio);
612 693
694 ret = pfc_ioremap(pip);
695 if (ret < 0)
696 return ret;
697
613 setup_data_regs(pip); 698 setup_data_regs(pip);
614 699
615 chip->request = sh_gpio_request; 700 chip->request = sh_gpio_request;
@@ -627,12 +712,16 @@ int register_pinmux(struct pinmux_info *pip)
627 chip->base = pip->first_gpio; 712 chip->base = pip->first_gpio;
628 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1; 713 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
629 714
630 return gpiochip_add(chip); 715 ret = gpiochip_add(chip);
716 if (ret < 0)
717 pfc_iounmap(pip);
718
719 return ret;
631} 720}
632 721
633int unregister_pinmux(struct pinmux_info *pip) 722int unregister_pinmux(struct pinmux_info *pip)
634{ 723{
635 pr_info("%s deregistering\n", pip->name); 724 pr_info("%s deregistering\n", pip->name);
636 725 pfc_iounmap(pip);
637 return gpiochip_remove(&pip->chip); 726 return gpiochip_remove(&pip->chip);
638} 727}
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index aff9d612dff0..9e62349b3d9f 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -50,6 +50,7 @@
50#include <linux/dma-mapping.h> 50#include <linux/dma-mapping.h>
51#include <linux/scatterlist.h> 51#include <linux/scatterlist.h>
52#include <linux/slab.h> 52#include <linux/slab.h>
53#include <linux/gpio.h>
53 54
54#ifdef CONFIG_SUPERH 55#ifdef CONFIG_SUPERH
55#include <asm/sh_bios.h> 56#include <asm/sh_bios.h>
@@ -73,6 +74,7 @@ struct sci_port {
73 struct clk *fclk; 74 struct clk *fclk;
74 75
75 char *irqstr[SCIx_NR_IRQS]; 76 char *irqstr[SCIx_NR_IRQS];
77 char *gpiostr[SCIx_NR_FNS];
76 78
77 struct dma_chan *chan_tx; 79 struct dma_chan *chan_tx;
78 struct dma_chan *chan_rx; 80 struct dma_chan *chan_rx;
@@ -474,8 +476,15 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
474 if (!reg->size) 476 if (!reg->size)
475 return; 477 return;
476 478
477 if (!(cflag & CRTSCTS)) 479 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
478 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */ 480 ((!(cflag & CRTSCTS)))) {
481 unsigned short status;
482
483 status = sci_in(port, SCSPTR);
484 status &= ~SCSPTR_CTSIO;
485 status |= SCSPTR_RTSIO;
486 sci_out(port, SCSPTR, status); /* Set RTS = 1 */
487 }
479} 488}
480 489
481static int sci_txfill(struct uart_port *port) 490static int sci_txfill(struct uart_port *port)
@@ -621,6 +630,7 @@ static void sci_receive_chars(struct uart_port *port)
621 } else { 630 } else {
622 for (i = 0; i < count; i++) { 631 for (i = 0; i < count; i++) {
623 char c = sci_in(port, SCxRDR); 632 char c = sci_in(port, SCxRDR);
633
624 status = sci_in(port, SCxSR); 634 status = sci_in(port, SCxSR);
625#if defined(CONFIG_CPU_SH3) 635#if defined(CONFIG_CPU_SH3)
626 /* Skip "chars" during break */ 636 /* Skip "chars" during break */
@@ -649,9 +659,11 @@ static void sci_receive_chars(struct uart_port *port)
649 /* Store data and status */ 659 /* Store data and status */
650 if (status & SCxSR_FER(port)) { 660 if (status & SCxSR_FER(port)) {
651 flag = TTY_FRAME; 661 flag = TTY_FRAME;
662 port->icount.frame++;
652 dev_notice(port->dev, "frame error\n"); 663 dev_notice(port->dev, "frame error\n");
653 } else if (status & SCxSR_PER(port)) { 664 } else if (status & SCxSR_PER(port)) {
654 flag = TTY_PARITY; 665 flag = TTY_PARITY;
666 port->icount.parity++;
655 dev_notice(port->dev, "parity error\n"); 667 dev_notice(port->dev, "parity error\n");
656 } else 668 } else
657 flag = TTY_NORMAL; 669 flag = TTY_NORMAL;
@@ -723,6 +735,8 @@ static int sci_handle_errors(struct uart_port *port)
723 */ 735 */
724 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { 736 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
725 if (status & (1 << s->cfg->overrun_bit)) { 737 if (status & (1 << s->cfg->overrun_bit)) {
738 port->icount.overrun++;
739
726 /* overrun error */ 740 /* overrun error */
727 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 741 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
728 copied++; 742 copied++;
@@ -737,6 +751,8 @@ static int sci_handle_errors(struct uart_port *port)
737 struct sci_port *sci_port = to_sci_port(port); 751 struct sci_port *sci_port = to_sci_port(port);
738 752
739 if (!sci_port->break_flag) { 753 if (!sci_port->break_flag) {
754 port->icount.brk++;
755
740 sci_port->break_flag = 1; 756 sci_port->break_flag = 1;
741 sci_schedule_break_timer(sci_port); 757 sci_schedule_break_timer(sci_port);
742 758
@@ -752,6 +768,8 @@ static int sci_handle_errors(struct uart_port *port)
752 768
753 } else { 769 } else {
754 /* frame error */ 770 /* frame error */
771 port->icount.frame++;
772
755 if (tty_insert_flip_char(tty, 0, TTY_FRAME)) 773 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
756 copied++; 774 copied++;
757 775
@@ -761,6 +779,8 @@ static int sci_handle_errors(struct uart_port *port)
761 779
762 if (status & SCxSR_PER(port)) { 780 if (status & SCxSR_PER(port)) {
763 /* parity error */ 781 /* parity error */
782 port->icount.parity++;
783
764 if (tty_insert_flip_char(tty, 0, TTY_PARITY)) 784 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
765 copied++; 785 copied++;
766 786
@@ -787,6 +807,8 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
787 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { 807 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
788 sci_out(port, SCLSR, 0); 808 sci_out(port, SCLSR, 0);
789 809
810 port->icount.overrun++;
811
790 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 812 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
791 tty_flip_buffer_push(tty); 813 tty_flip_buffer_push(tty);
792 814
@@ -812,6 +834,9 @@ static int sci_handle_breaks(struct uart_port *port)
812 /* Debounce break */ 834 /* Debounce break */
813 s->break_flag = 1; 835 s->break_flag = 1;
814#endif 836#endif
837
838 port->icount.brk++;
839
815 /* Notify of BREAK */ 840 /* Notify of BREAK */
816 if (tty_insert_flip_char(tty, 0, TTY_BREAK)) 841 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
817 copied++; 842 copied++;
@@ -1082,6 +1107,67 @@ static void sci_free_irq(struct sci_port *port)
1082 } 1107 }
1083} 1108}
1084 1109
1110static const char *sci_gpio_names[SCIx_NR_FNS] = {
1111 "sck", "rxd", "txd", "cts", "rts",
1112};
1113
1114static const char *sci_gpio_str(unsigned int index)
1115{
1116 return sci_gpio_names[index];
1117}
1118
1119static void __devinit sci_init_gpios(struct sci_port *port)
1120{
1121 struct uart_port *up = &port->port;
1122 int i;
1123
1124 if (!port->cfg)
1125 return;
1126
1127 for (i = 0; i < SCIx_NR_FNS; i++) {
1128 const char *desc;
1129 int ret;
1130
1131 if (!port->cfg->gpios[i])
1132 continue;
1133
1134 desc = sci_gpio_str(i);
1135
1136 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1137 dev_name(up->dev), desc);
1138
1139 /*
1140 * If we've failed the allocation, we can still continue
1141 * on with a NULL string.
1142 */
1143 if (!port->gpiostr[i])
1144 dev_notice(up->dev, "%s string allocation failure\n",
1145 desc);
1146
1147 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1148 if (unlikely(ret != 0)) {
1149 dev_notice(up->dev, "failed %s gpio request\n", desc);
1150
1151 /*
1152 * If we can't get the GPIO for whatever reason,
1153 * no point in keeping the verbose string around.
1154 */
1155 kfree(port->gpiostr[i]);
1156 }
1157 }
1158}
1159
1160static void sci_free_gpios(struct sci_port *port)
1161{
1162 int i;
1163
1164 for (i = 0; i < SCIx_NR_FNS; i++)
1165 if (port->cfg->gpios[i]) {
1166 gpio_free(port->cfg->gpios[i]);
1167 kfree(port->gpiostr[i]);
1168 }
1169}
1170
1085static unsigned int sci_tx_empty(struct uart_port *port) 1171static unsigned int sci_tx_empty(struct uart_port *port)
1086{ 1172{
1087 unsigned short status = sci_in(port, SCxSR); 1173 unsigned short status = sci_in(port, SCxSR);
@@ -1090,19 +1176,39 @@ static unsigned int sci_tx_empty(struct uart_port *port)
1090 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1176 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1091} 1177}
1092 1178
1179/*
1180 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1181 * CTS/RTS is supported in hardware by at least one port and controlled
1182 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1183 * handled via the ->init_pins() op, which is a bit of a one-way street,
1184 * lacking any ability to defer pin control -- this will later be
1185 * converted over to the GPIO framework).
1186 *
1187 * Other modes (such as loopback) are supported generically on certain
1188 * port types, but not others. For these it's sufficient to test for the
1189 * existence of the support register and simply ignore the port type.
1190 */
1093static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 1191static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1094{ 1192{
1095 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ 1193 if (mctrl & TIOCM_LOOP) {
1096 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ 1194 struct plat_sci_reg *reg;
1097 /* If you have signals for DTR and DCD, please implement here. */ 1195
1196 /*
1197 * Standard loopback mode for SCFCR ports.
1198 */
1199 reg = sci_getreg(port, SCFCR);
1200 if (reg->size)
1201 sci_out(port, SCFCR, sci_in(port, SCFCR) | 1);
1202 }
1098} 1203}
1099 1204
1100static unsigned int sci_get_mctrl(struct uart_port *port) 1205static unsigned int sci_get_mctrl(struct uart_port *port)
1101{ 1206{
1102 /* This routine is used for getting signals of: DTR, DCD, DSR, RI, 1207 /*
1103 and CTS/RTS */ 1208 * CTS/RTS is handled in hardware when supported, while nothing
1104 1209 * else is wired up. Keep it simple and simply assert DSR/CAR.
1105 return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR; 1210 */
1211 return TIOCM_DSR | TIOCM_CAR;
1106} 1212}
1107 1213
1108#ifdef CONFIG_SERIAL_SH_SCI_DMA 1214#ifdef CONFIG_SERIAL_SH_SCI_DMA
@@ -1449,12 +1555,17 @@ static void sci_stop_rx(struct uart_port *port)
1449 1555
1450static void sci_enable_ms(struct uart_port *port) 1556static void sci_enable_ms(struct uart_port *port)
1451{ 1557{
1452 /* Nothing here yet .. */ 1558 /*
1559 * Not supported by hardware, always a nop.
1560 */
1453} 1561}
1454 1562
1455static void sci_break_ctl(struct uart_port *port, int break_state) 1563static void sci_break_ctl(struct uart_port *port, int break_state)
1456{ 1564{
1457 /* Nothing here yet .. */ 1565 /*
1566 * Not supported by hardware. Most parts couple break and rx
1567 * interrupts together, with break detection always enabled.
1568 */
1458} 1569}
1459 1570
1460#ifdef CONFIG_SERIAL_SH_SCI_DMA 1571#ifdef CONFIG_SERIAL_SH_SCI_DMA
@@ -1652,6 +1763,7 @@ static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1652 1763
1653static void sci_reset(struct uart_port *port) 1764static void sci_reset(struct uart_port *port)
1654{ 1765{
1766 struct plat_sci_reg *reg;
1655 unsigned int status; 1767 unsigned int status;
1656 1768
1657 do { 1769 do {
@@ -1660,7 +1772,8 @@ static void sci_reset(struct uart_port *port)
1660 1772
1661 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ 1773 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1662 1774
1663 if (port->type != PORT_SCI) 1775 reg = sci_getreg(port, SCFCR);
1776 if (reg->size)
1664 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 1777 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1665} 1778}
1666 1779
@@ -1668,9 +1781,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1668 struct ktermios *old) 1781 struct ktermios *old)
1669{ 1782{
1670 struct sci_port *s = to_sci_port(port); 1783 struct sci_port *s = to_sci_port(port);
1784 struct plat_sci_reg *reg;
1671 unsigned int baud, smr_val, max_baud; 1785 unsigned int baud, smr_val, max_baud;
1672 int t = -1; 1786 int t = -1;
1673 u16 scfcr = 0;
1674 1787
1675 /* 1788 /*
1676 * earlyprintk comes here early on with port->uartclk set to zero. 1789 * earlyprintk comes here early on with port->uartclk set to zero.
@@ -1720,7 +1833,27 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1720 } 1833 }
1721 1834
1722 sci_init_pins(port, termios->c_cflag); 1835 sci_init_pins(port, termios->c_cflag);
1723 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); 1836
1837 reg = sci_getreg(port, SCFCR);
1838 if (reg->size) {
1839 unsigned short ctrl = sci_in(port, SCFCR);
1840
1841 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1842 if (termios->c_cflag & CRTSCTS)
1843 ctrl |= SCFCR_MCE;
1844 else
1845 ctrl &= ~SCFCR_MCE;
1846 }
1847
1848 /*
1849 * As we've done a sci_reset() above, ensure we don't
1850 * interfere with the FIFOs while toggling MCE. As the
1851 * reset values could still be set, simply mask them out.
1852 */
1853 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1854
1855 sci_out(port, SCFCR, ctrl);
1856 }
1724 1857
1725 sci_out(port, SCSCR, s->cfg->scscr); 1858 sci_out(port, SCSCR, s->cfg->scscr);
1726 1859
@@ -1892,6 +2025,8 @@ static int __devinit sci_init_single(struct platform_device *dev,
1892 struct uart_port *port = &sci_port->port; 2025 struct uart_port *port = &sci_port->port;
1893 int ret; 2026 int ret;
1894 2027
2028 sci_port->cfg = p;
2029
1895 port->ops = &sci_uart_ops; 2030 port->ops = &sci_uart_ops;
1896 port->iotype = UPIO_MEM; 2031 port->iotype = UPIO_MEM;
1897 port->line = index; 2032 port->line = index;
@@ -1937,6 +2072,8 @@ static int __devinit sci_init_single(struct platform_device *dev,
1937 2072
1938 port->dev = &dev->dev; 2073 port->dev = &dev->dev;
1939 2074
2075 sci_init_gpios(sci_port);
2076
1940 pm_runtime_irq_safe(&dev->dev); 2077 pm_runtime_irq_safe(&dev->dev);
1941 pm_runtime_enable(&dev->dev); 2078 pm_runtime_enable(&dev->dev);
1942 } 2079 }
@@ -1971,8 +2108,6 @@ static int __devinit sci_init_single(struct platform_device *dev,
1971 p->error_mask |= (1 << p->overrun_bit); 2108 p->error_mask |= (1 << p->overrun_bit);
1972 } 2109 }
1973 2110
1974 sci_port->cfg = p;
1975
1976 port->mapbase = p->mapbase; 2111 port->mapbase = p->mapbase;
1977 port->type = p->type; 2112 port->type = p->type;
1978 port->flags = p->flags; 2113 port->flags = p->flags;
@@ -2113,9 +2248,16 @@ static int sci_runtime_suspend(struct device *dev)
2113 struct uart_port *port = &sci_port->port; 2248 struct uart_port *port = &sci_port->port;
2114 2249
2115 if (uart_console(port)) { 2250 if (uart_console(port)) {
2251 struct plat_sci_reg *reg;
2252
2116 sci_port->saved_smr = sci_in(port, SCSMR); 2253 sci_port->saved_smr = sci_in(port, SCSMR);
2117 sci_port->saved_brr = sci_in(port, SCBRR); 2254 sci_port->saved_brr = sci_in(port, SCBRR);
2118 sci_port->saved_fcr = sci_in(port, SCFCR); 2255
2256 reg = sci_getreg(port, SCFCR);
2257 if (reg->size)
2258 sci_port->saved_fcr = sci_in(port, SCFCR);
2259 else
2260 sci_port->saved_fcr = 0;
2119 } 2261 }
2120 return 0; 2262 return 0;
2121} 2263}
@@ -2129,7 +2271,10 @@ static int sci_runtime_resume(struct device *dev)
2129 sci_reset(port); 2271 sci_reset(port);
2130 sci_out(port, SCSMR, sci_port->saved_smr); 2272 sci_out(port, SCSMR, sci_port->saved_smr);
2131 sci_out(port, SCBRR, sci_port->saved_brr); 2273 sci_out(port, SCBRR, sci_port->saved_brr);
2132 sci_out(port, SCFCR, sci_port->saved_fcr); 2274
2275 if (sci_port->saved_fcr)
2276 sci_out(port, SCFCR, sci_port->saved_fcr);
2277
2133 sci_out(port, SCSCR, sci_port->cfg->scscr); 2278 sci_out(port, SCSCR, sci_port->cfg->scscr);
2134 } 2279 }
2135 return 0; 2280 return 0;
@@ -2169,6 +2314,8 @@ static int sci_remove(struct platform_device *dev)
2169 cpufreq_unregister_notifier(&port->freq_transition, 2314 cpufreq_unregister_notifier(&port->freq_transition,
2170 CPUFREQ_TRANSITION_NOTIFIER); 2315 CPUFREQ_TRANSITION_NOTIFIER);
2171 2316
2317 sci_free_gpios(port);
2318
2172 uart_remove_one_port(&sci_uart_driver, &port->port); 2319 uart_remove_one_port(&sci_uart_driver, &port->port);
2173 2320
2174 clk_put(port->iclk); 2321 clk_put(port->iclk);
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 369273a52679..78779074f6e8 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -49,6 +49,10 @@ enum {
49 49
50#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 50#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
51 51
52/* SCSPTR, optional */
53#define SCSPTR_RTSIO (1 << 7)
54#define SCSPTR_CTSIO (1 << 5)
55
52/* Offsets into the sci_port->irqs array */ 56/* Offsets into the sci_port->irqs array */
53enum { 57enum {
54 SCIx_ERI_IRQ, 58 SCIx_ERI_IRQ,
@@ -60,6 +64,17 @@ enum {
60 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 64 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
61}; 65};
62 66
67/* Offsets into the sci_port->gpios array */
68enum {
69 SCIx_SCK,
70 SCIx_RXD,
71 SCIx_TXD,
72 SCIx_CTS,
73 SCIx_RTS,
74
75 SCIx_NR_FNS,
76};
77
63enum { 78enum {
64 SCIx_PROBE_REGTYPE, 79 SCIx_PROBE_REGTYPE,
65 80
@@ -109,13 +124,20 @@ struct plat_sci_port_ops {
109}; 124};
110 125
111/* 126/*
127 * Port-specific capabilities
128 */
129#define SCIx_HAVE_RTSCTS (1 << 0)
130
131/*
112 * Platform device specific platform_data struct 132 * Platform device specific platform_data struct
113 */ 133 */
114struct plat_sci_port { 134struct plat_sci_port {
115 unsigned long mapbase; /* resource base */ 135 unsigned long mapbase; /* resource base */
116 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ 136 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
137 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
117 unsigned int type; /* SCI / SCIF / IRDA */ 138 unsigned int type; /* SCI / SCIF / IRDA */
118 upf_t flags; /* UPF_* flags */ 139 upf_t flags; /* UPF_* flags */
140 unsigned long capabilities; /* Port features/capabilities */
119 141
120 unsigned int scbrr_algo_id; /* SCBRR calculation algo */ 142 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
121 unsigned int scscr; /* SCSCR initialization */ 143 unsigned int scscr; /* SCSCR initialization */
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index a20831cf336a..54341d811685 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -49,6 +49,7 @@ struct clk {
49 49
50 void __iomem *enable_reg; 50 void __iomem *enable_reg;
51 unsigned int enable_bit; 51 unsigned int enable_bit;
52 void __iomem *mapped_reg;
52 53
53 unsigned long arch_flags; 54 unsigned long arch_flags;
54 void *priv; 55 void *priv;
@@ -131,10 +132,9 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr,
131int sh_clk_div4_reparent_register(struct clk *clks, int nr, 132int sh_clk_div4_reparent_register(struct clk *clks, int nr,
132 struct clk_div4_table *table); 133 struct clk_div4_table *table);
133 134
134#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \ 135#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
135 _num_parents, _src_shift, _src_width) \ 136 _num_parents, _src_shift, _src_width) \
136{ \ 137{ \
137 .parent = _parent, \
138 .enable_reg = (void __iomem *)_reg, \ 138 .enable_reg = (void __iomem *)_reg, \
139 .flags = _flags, \ 139 .flags = _flags, \
140 .parent_table = _parents, \ 140 .parent_table = _parents, \
@@ -144,7 +144,11 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
144} 144}
145 145
146#define SH_CLK_DIV6(_parent, _reg, _flags) \ 146#define SH_CLK_DIV6(_parent, _reg, _flags) \
147 SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0) 147{ \
148 .parent = _parent, \
149 .enable_reg = (void __iomem *)_reg, \
150 .flags = _flags, \
151}
148 152
149int sh_clk_div6_register(struct clk *clks, int nr); 153int sh_clk_div6_register(struct clk *clks, int nr);
150int sh_clk_div6_reparent_register(struct clk *clks, int nr); 154int sh_clk_div6_reparent_register(struct clk *clks, int nr);
diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h
index 8446789216e5..91666a58529d 100644
--- a/include/linux/sh_pfc.h
+++ b/include/linux/sh_pfc.h
@@ -55,6 +55,7 @@ struct pinmux_cfg_reg {
55struct pinmux_data_reg { 55struct pinmux_data_reg {
56 unsigned long reg, reg_width, reg_shadow; 56 unsigned long reg, reg_width, reg_shadow;
57 pinmux_enum_t *enum_ids; 57 pinmux_enum_t *enum_ids;
58 void __iomem *mapped_reg;
58}; 59};
59 60
60#define PINMUX_DATA_REG(name, r, r_width) \ 61#define PINMUX_DATA_REG(name, r, r_width) \
@@ -75,6 +76,12 @@ struct pinmux_range {
75 pinmux_enum_t force; 76 pinmux_enum_t force;
76}; 77};
77 78
79struct pfc_window {
80 phys_addr_t phys;
81 void __iomem *virt;
82 unsigned long size;
83};
84
78struct pinmux_info { 85struct pinmux_info {
79 char *name; 86 char *name;
80 pinmux_enum_t reserved_id; 87 pinmux_enum_t reserved_id;
@@ -98,6 +105,10 @@ struct pinmux_info {
98 struct pinmux_irq *gpio_irq; 105 struct pinmux_irq *gpio_irq;
99 unsigned int gpio_irq_size; 106 unsigned int gpio_irq_size;
100 107
108 struct resource *resource;
109 unsigned int num_resources;
110 struct pfc_window *window;
111
101 struct gpio_chip chip; 112 struct gpio_chip chip;
102}; 113};
103 114
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 04:03:06 -0500