diff options
-rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 6426c7ed9ccc..e804585cc59c 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c | |||
@@ -242,28 +242,35 @@ static void | |||
242 | qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) | 242 | qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) |
243 | { | 243 | { |
244 | uint16_t cnt; | 244 | uint16_t cnt; |
245 | uint32_t mboxes; | ||
245 | uint16_t __iomem *wptr; | 246 | uint16_t __iomem *wptr; |
246 | struct qla_hw_data *ha = vha->hw; | 247 | struct qla_hw_data *ha = vha->hw; |
247 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | 248 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
248 | 249 | ||
250 | /* Read all mbox registers? */ | ||
251 | mboxes = (1 << ha->mbx_count) - 1; | ||
252 | if (!ha->mcp) | ||
253 | ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERRROR.\n"); | ||
254 | else | ||
255 | mboxes = ha->mcp->in_mb; | ||
256 | |||
249 | /* Load return mailbox registers. */ | 257 | /* Load return mailbox registers. */ |
250 | ha->flags.mbox_int = 1; | 258 | ha->flags.mbox_int = 1; |
251 | ha->mailbox_out[0] = mb0; | 259 | ha->mailbox_out[0] = mb0; |
260 | mboxes >>= 1; | ||
252 | wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); | 261 | wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); |
253 | 262 | ||
254 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | 263 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { |
255 | if (IS_QLA2200(ha) && cnt == 8) | 264 | if (IS_QLA2200(ha) && cnt == 8) |
256 | wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); | 265 | wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); |
257 | if (cnt == 4 || cnt == 5) | 266 | if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) |
258 | ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); | 267 | ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); |
259 | else | 268 | else if (mboxes & BIT_0) |
260 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | 269 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); |
261 | 270 | ||
262 | wptr++; | 271 | wptr++; |
272 | mboxes >>= 1; | ||
263 | } | 273 | } |
264 | |||
265 | if (!ha->mcp) | ||
266 | ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n"); | ||
267 | } | 274 | } |
268 | 275 | ||
269 | static void | 276 | static void |
@@ -2004,22 +2011,31 @@ static void | |||
2004 | qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) | 2011 | qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) |
2005 | { | 2012 | { |
2006 | uint16_t cnt; | 2013 | uint16_t cnt; |
2014 | uint32_t mboxes; | ||
2007 | uint16_t __iomem *wptr; | 2015 | uint16_t __iomem *wptr; |
2008 | struct qla_hw_data *ha = vha->hw; | 2016 | struct qla_hw_data *ha = vha->hw; |
2009 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 2017 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
2010 | 2018 | ||
2019 | /* Read all mbox registers? */ | ||
2020 | mboxes = (1 << ha->mbx_count) - 1; | ||
2021 | if (!ha->mcp) | ||
2022 | ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERRROR.\n"); | ||
2023 | else | ||
2024 | mboxes = ha->mcp->in_mb; | ||
2025 | |||
2011 | /* Load return mailbox registers. */ | 2026 | /* Load return mailbox registers. */ |
2012 | ha->flags.mbox_int = 1; | 2027 | ha->flags.mbox_int = 1; |
2013 | ha->mailbox_out[0] = mb0; | 2028 | ha->mailbox_out[0] = mb0; |
2029 | mboxes >>= 1; | ||
2014 | wptr = (uint16_t __iomem *)®->mailbox1; | 2030 | wptr = (uint16_t __iomem *)®->mailbox1; |
2015 | 2031 | ||
2016 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | 2032 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { |
2017 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | 2033 | if (mboxes & BIT_0) |
2034 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | ||
2035 | |||
2036 | mboxes >>= 1; | ||
2018 | wptr++; | 2037 | wptr++; |
2019 | } | 2038 | } |
2020 | |||
2021 | if (!ha->mcp) | ||
2022 | ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERRROR.\n"); | ||
2023 | } | 2039 | } |
2024 | 2040 | ||
2025 | /** | 2041 | /** |