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-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c58
1 files changed, 26 insertions, 32 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index cc94b64c2ef5..605298b2ffe5 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,35 @@ void __init r8a73a4_pinmux_init(void)
40 ARRAY_SIZE(pfc_resources)); 40 ARRAY_SIZE(pfc_resources));
41} 41}
42 42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \ 43#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
44static struct plat_sci_port scif##index##_platform_data = { \
44 .type = scif_type, \ 45 .type = scif_type, \
45 .mapbase = baseaddr, \ 46 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 47 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .scbrr_algo_id = SCBRR_ALGO_4, \ 48 .scbrr_algo_id = SCBRR_ALGO_4, \
48 .irqs = SCIx_IRQ_MUXED(irq) 49 .scscr = _scscr, \
49 50 .irqs = SCIx_IRQ_MUXED(irq), \
50#define SCIFA_DATA(index, baseaddr, irq) \
51[index] = { \
52 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54} 51}
55 52
56#define SCIFB_DATA(index, baseaddr, irq) \ 53#define R8A73A4_SCIFA(index, baseaddr, irq) \
57[index] = { \ 54 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ 55 index, baseaddr, irq)
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61 56
62enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; 57#define R8A73A4_SCIFB(index, baseaddr, irq) \
58 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
59 index, baseaddr, irq)
63 60
64static const struct plat_sci_port scif[] = { 61R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
65 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 62R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
66 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 63R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
67 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 64R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
68 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 65R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
69 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 66R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
70 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
71};
72 67
73static inline void r8a73a4_register_scif(int idx) 68#define r8a73a4_register_scif(index) \
74{ 69 platform_device_register_data(&platform_bus, "sh-sci", index, \
75 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 70 &scif##index##_platform_data, \
76 sizeof(struct plat_sci_port)); 71 sizeof(scif##index##_platform_data))
77}
78 72
79static const struct renesas_irqc_config irqc0_data = { 73static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 74 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +186,12 @@ static struct resource cmt10_resources[] = {
192 186
193void __init r8a73a4_add_dt_devices(void) 187void __init r8a73a4_add_dt_devices(void)
194{ 188{
195 r8a73a4_register_scif(SCIFA0); 189 r8a73a4_register_scif(0);
196 r8a73a4_register_scif(SCIFA1); 190 r8a73a4_register_scif(1);
197 r8a73a4_register_scif(SCIFB0); 191 r8a73a4_register_scif(2);
198 r8a73a4_register_scif(SCIFB1); 192 r8a73a4_register_scif(3);
199 r8a73a4_register_scif(SCIFB2); 193 r8a73a4_register_scif(4);
200 r8a73a4_register_scif(SCIFB3); 194 r8a73a4_register_scif(5);
201 r8a7790_register_cmt(10); 195 r8a7790_register_cmt(10);
202} 196}
203 197