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-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c4
-rw-r--r--drivers/gpu/drm/radeon/rs600.c1
-rw-r--r--drivers/gpu/drm/radeon/rs690.c2
4 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 6df7bd569495..3bc2bcdf5308 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1032,21 +1032,18 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1032 u8 frev, crev; 1032 u8 frev, crev;
1033 u16 data_offset; 1033 u16 data_offset;
1034 1034
1035 /* sideport is AMD only */
1036 if (rdev->family == CHIP_RS600)
1037 return false;
1038
1035 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1039 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1036 &frev, &crev, &data_offset)) { 1040 &frev, &crev, &data_offset)) {
1037 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1041 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1038 data_offset); 1042 data_offset);
1039 switch (crev) { 1043 switch (crev) {
1040 case 1: 1044 case 1:
1041 /* AMD IGPS */ 1045 if (igp_info->info.ulBootUpMemoryClock)
1042 if ((rdev->family == CHIP_RS690) || 1046 return true;
1043 (rdev->family == CHIP_RS740)) {
1044 if (igp_info->info.ulBootUpMemoryClock)
1045 return true;
1046 } else {
1047 if (igp_info->info.ucMemoryType & 0xf0)
1048 return true;
1049 }
1050 break; 1047 break;
1051 case 2: 1048 case 2:
1052 if (igp_info->info_2.ucMemoryType & 0x0f) 1049 if (igp_info->info_2.ucMemoryType & 0x0f)
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index cd2a6c254e3e..5e1474cde4b4 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -693,6 +693,10 @@ bool radeon_combios_sideport_present(struct radeon_device *rdev)
693 struct drm_device *dev = rdev->ddev; 693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info; 694 u16 igp_info;
695 695
696 /* sideport is AMD only */
697 if (rdev->family == CHIP_RS400)
698 return false;
699
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 700 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697 701
698 if (igp_info) { 702 if (igp_info) {
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 85cd911952c1..cc05b230d7ef 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -696,7 +696,6 @@ void rs600_mc_init(struct radeon_device *rdev)
696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 696 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
697 base = RREG32_MC(R_000004_MC_FB_LOCATION); 697 base = RREG32_MC(R_000004_MC_FB_LOCATION);
698 base = G_000004_MC_FB_START(base) << 16; 698 base = G_000004_MC_FB_START(base) << 16;
699 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
700 radeon_vram_location(rdev, &rdev->mc, base); 699 radeon_vram_location(rdev, &rdev->mc, base);
701 rdev->mc.gtt_base_align = 0; 700 rdev->mc.gtt_base_align = 0;
702 radeon_gtt_location(rdev, &rdev->mc); 701 radeon_gtt_location(rdev, &rdev->mc);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 6fbb874583f4..3e3f75718be3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -159,8 +159,8 @@ void rs690_mc_init(struct radeon_device *rdev)
159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 161 base = G_000100_MC_FB_START(base) << 16;
162 rs690_pm_info(rdev);
163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
163 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 164 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
166 radeon_gtt_location(rdev, &rdev->mc); 166 radeon_gtt_location(rdev, &rdev->mc);