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-rw-r--r--arch/mips/mm/c-r4k.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9b223e07f784..8fc713f1d139 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -640,6 +640,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
640 break; 640 break;
641 } 641 }
642 } 642 }
643#ifdef CONFIG_EVA
644 /*
645 * Due to all possible segment mappings, there might cache aliases
646 * caused by the bootloader being in non-EVA mode, and the CPU switching
647 * to EVA during early kernel init. It's best to flush the scache
648 * to avoid having secondary cores fetching stale data and lead to
649 * kernel crashes.
650 */
651 bc_wback_inv(start, (end - start));
652 __sync();
653#endif
643} 654}
644 655
645static inline void local_r4k_flush_icache_range_ipi(void *args) 656static inline void local_r4k_flush_icache_range_ipi(void *args)