14 files changed, 172 insertions, 38 deletions

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 57226424690c..6f007b6c240d 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -239,16 +239,45 @@
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG          0x016A
 #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB               0x0F00 /* VLV1 */
 #define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG               0x0F30
-#define PCI_DEVICE_ID_INTEL_HASWELL_HB                          0x0400 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_HASWELL_HB                  0x0400 /* Desktop */
 #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG            0x0402
 #define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG            0x0412
-#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB                        0x0404 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG       0x0422
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB                0x0404 /* Mobile */
 #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG            0x0406
 #define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG            0x0416
-#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB                        0x0408 /* Server */
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG       0x0426
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB                0x0408 /* Server */
 #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG            0x040a
 #define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG            0x041a
-#define PCI_DEVICE_ID_INTEL_HASWELL_SDV         0x0c16 /* SDV */
-#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB                        0x0c04
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG       0x042a
+#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB                0x0c04
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG        0x0C02
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG        0x0C12
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG   0x0C22
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG        0x0C06
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG        0x0C16
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG   0x0C26
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG        0x0C0A
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG        0x0C1A
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG   0x0C2A
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG        0x0A02
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG        0x0A12
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG   0x0A22
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG        0x0A06
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG        0x0A16
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG   0x0A26
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG        0x0A0A
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG        0x0A1A
+#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG   0x0A2A
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG        0x0D12
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG        0x0D22
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG   0x0D32
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG        0x0D16
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG        0x0D26
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG   0x0D36
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG        0x0D1A
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG        0x0D2A
+#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG   0x0D3A
 
 #endif
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 9ed92ef5829b..08fc5cbb13cd 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description {
             "Haswell", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
             "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
             "Haswell", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
             "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
             "Haswell", &sandybridge_gtt_driver },
         { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
             "Haswell", &sandybridge_gtt_driver },
-        { PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+        { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
+            "Haswell", &sandybridge_gtt_driver },
+        { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
             "Haswell", &sandybridge_gtt_driver },
         { 0, NULL, NULL }
 };
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ed22612bc847..a24ffbe97c01 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
-        INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
+        INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
+        INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
+        INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
+        INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
+        INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
+        INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
+        INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
+        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
+        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
+        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index da8b01fb1bf8..a9d58d72bb4d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
         struct drm_i915_file_private *file_priv = NULL;
         struct i915_hw_context *to;
         struct drm_i915_gem_object *from_obj = ring->last_context_obj;
-        int ret;
 
         if (dev_priv->hw_contexts_disabled)
                 return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 5af631e788c8..ff2819ea0813 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -291,6 +291,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
         target_i915_obj = to_intel_bo(target_obj);
         target_offset = target_i915_obj->gtt_offset;
 
+        /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
+         * pipe_control writes because the gpu doesn't properly redirect them
+         * through the ppgtt for non_secure batchbuffers. */
+        if (unlikely(IS_GEN6(dev) &&
+            reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
+            !target_i915_obj->has_global_gtt_mapping)) {
+                i915_gem_gtt_bind_object(target_i915_obj,
+                                         target_i915_obj->cache_level);
+        }
+
         /* The target buffer should have appeared before us in the
          * exec_object list, so it should have a GTT space bound by now.
          */
@@ -399,16 +409,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
                 io_mapping_unmap_atomic(reloc_page);
         }
 
-        /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
-         * pipe_control writes because the gpu doesn't properly redirect them
-         * through the ppgtt for non_secure batchbuffers. */
-        if (unlikely(IS_GEN6(dev) &&
-            reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
-            !target_i915_obj->has_global_gtt_mapping)) {
-                i915_gem_gtt_bind_object(target_i915_obj,
-                                         target_i915_obj->cache_level);
-        }
-
         /* and update the user's relocation entry */
         reloc->presumed_offset = target_offset;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9fd25a435536..ee9b68f6bc36 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -361,7 +361,8 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
         struct drm_device *dev = obj->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (dev_priv->mm.gtt->needs_dmar)
+        /* don't map imported dma buf objects */
+        if (dev_priv->mm.gtt->needs_dmar && !obj->sg_table)
                 return intel_gtt_map_memory(obj->pages,
                                             obj->base.size >> PAGE_SHIFT,
                                             &obj->sg_list,
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2f5388af8df9..7631807a2788 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -32,6 +32,7 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+#ifdef CONFIG_PM
 static u32 calc_residency(struct drm_device *dev, const u32 reg)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -224,3 +225,14 @@ void i915_teardown_sysfs(struct drm_device *dev)
         device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
         sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
 }
+#else
+void i915_setup_sysfs(struct drm_device *dev)
+{
+        return;
+}
+
+void i915_teardown_sysfs(struct drm_device *dev)
+{
+        return;
+}
+#endif /* CONFIG_PM */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6159765f1eb..88913a47cd34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -869,6 +869,7 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
         unsigned long bestppm, ppm, absppm;
         int dotclk, flag;
 
+        flag = 0;
         dotclk = target * 1000;
         bestppm = 1000000;
         ppm = absppm = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 84353559441c..132ab511b90c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -46,15 +46,16 @@
 })
 
 #define wait_for_atomic_us(COND, US) ({ \
-        int i, ret__ = -ETIMEDOUT;      \
-        for (i = 0; i < (US); i++) {    \
-                if ((COND)) {           \
-                        ret__ = 0;      \
-                        break;          \
-                }                       \
-                udelay(1);              \
-        }                               \
-        ret__;                          \
+        unsigned long timeout__ = jiffies + usecs_to_jiffies(US);       \
+        int ret__ = 0;                                                  \
+        while (!(COND)) {                                               \
+                if (time_after(jiffies, timeout__)) {                   \
+                        ret__ = -ETIMEDOUT;                             \
+                        break;                                          \
+                }                                                       \
+                cpu_relax();                                            \
+        }                                                               \
+        ret__;                                                          \
 })
 
 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
@@ -380,7 +381,6 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
                                     const struct drm_display_mode *mode,
                                     struct drm_display_mode *adjusted_mode);
 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
-extern u32 intel_panel_get_backlight(struct drm_device *dev);
 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
 extern int intel_panel_setup_backlight(struct drm_device *dev);
 extern void intel_panel_enable_backlight(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1991a4408cf9..d79500bc1ce5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -540,9 +540,6 @@ void intel_teardown_gmbus(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        if (dev_priv->gmbus == NULL)
-                return;
-
         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
                 i2c_del_adapter(&bus->adapter);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 10c7d39034e1..9474488db948 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -213,7 +213,7 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
         return val;
 }
 
-u32 intel_panel_get_backlight(struct drm_device *dev)
+static u32 intel_panel_get_backlight(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94aabcaa3a67..58c07cdafb7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3963,6 +3963,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
                 DRM_ERROR("Force wake wait timed out\n");
 
         I915_WRITE_NOTRACE(FORCEWAKE, 1);
+        POSTING_READ(FORCEWAKE);
 
         if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
                 DRM_ERROR("Force wake wait timed out\n");
@@ -3983,6 +3984,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
                 DRM_ERROR("Force wake wait timed out\n");
 
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
+        POSTING_READ(FORCEWAKE_MT);
 
         if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
                 DRM_ERROR("Force wake wait timed out\n");
@@ -4018,14 +4020,14 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE, 0);
-        /* The below doubles as a POSTING_READ */
+        POSTING_READ(FORCEWAKE);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
-        /* The below doubles as a POSTING_READ */
+        POSTING_READ(FORCEWAKE_MT);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bf0195a96d53..414af1e2973b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -289,8 +289,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
         I915_WRITE_HEAD(ring, 0);
         ring->write_tail(ring, 0);
 
-        /* Initialize the ring. */
-        I915_WRITE_START(ring, obj->gtt_offset);
         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 
         /* G45 ring initialization fails to reset head to zero */
@@ -316,6 +314,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                 }
         }
 
+        /* Initialize the ring. This must happen _after_ we've cleared the ring
+         * registers with the above sequence (the readback of the HEAD registers
+         * also enforces ordering), otherwise the hw might lose the new ring
+         * register values. */
+        I915_WRITE_START(ring, obj->gtt_offset);
         I915_WRITE_CTL(ring,
                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
                         | RING_VALID);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 26a6a4d0d078..d172e9873131 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -444,13 +444,16 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
         struct i2c_msg *msgs;
         int i, ret = true;
 
+        /* Would be simpler to allocate both in one go ? */        
         buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
         if (!buf)
                 return false;
 
         msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
-        if (!msgs)
+        if (!msgs) {
+                kfree(buf);
                 return false;
+        }
 
         intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);