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-rw-r--r--arch/arm/mach-ep93xx/clock.c52
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h19
2 files changed, 42 insertions, 29 deletions
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 29f36b458a0f..209a465bd679 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -37,58 +37,58 @@ static struct clk clk_h;
37static struct clk clk_p; 37static struct clk clk_p;
38static struct clk clk_pll2; 38static struct clk clk_pll2;
39static struct clk clk_usb_host = { 39static struct clk clk_usb_host = {
40 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 40 .enable_reg = EP93XX_SYSCON_PWRCNT,
41 .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, 41 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
42}; 42};
43 43
44/* DMA Clocks */ 44/* DMA Clocks */
45static struct clk clk_m2p0 = { 45static struct clk clk_m2p0 = {
46 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 46 .enable_reg = EP93XX_SYSCON_PWRCNT,
47 .enable_mask = 0x00020000, 47 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
48}; 48};
49static struct clk clk_m2p1 = { 49static struct clk clk_m2p1 = {
50 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 50 .enable_reg = EP93XX_SYSCON_PWRCNT,
51 .enable_mask = 0x00010000, 51 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
52}; 52};
53static struct clk clk_m2p2 = { 53static struct clk clk_m2p2 = {
54 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 54 .enable_reg = EP93XX_SYSCON_PWRCNT,
55 .enable_mask = 0x00080000, 55 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
56}; 56};
57static struct clk clk_m2p3 = { 57static struct clk clk_m2p3 = {
58 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 58 .enable_reg = EP93XX_SYSCON_PWRCNT,
59 .enable_mask = 0x00040000, 59 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
60}; 60};
61static struct clk clk_m2p4 = { 61static struct clk clk_m2p4 = {
62 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 62 .enable_reg = EP93XX_SYSCON_PWRCNT,
63 .enable_mask = 0x00200000, 63 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
64}; 64};
65static struct clk clk_m2p5 = { 65static struct clk clk_m2p5 = {
66 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 66 .enable_reg = EP93XX_SYSCON_PWRCNT,
67 .enable_mask = 0x00100000, 67 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
68}; 68};
69static struct clk clk_m2p6 = { 69static struct clk clk_m2p6 = {
70 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 70 .enable_reg = EP93XX_SYSCON_PWRCNT,
71 .enable_mask = 0x00800000, 71 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
72}; 72};
73static struct clk clk_m2p7 = { 73static struct clk clk_m2p7 = {
74 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 74 .enable_reg = EP93XX_SYSCON_PWRCNT,
75 .enable_mask = 0x00400000, 75 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
76}; 76};
77static struct clk clk_m2p8 = { 77static struct clk clk_m2p8 = {
78 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 78 .enable_reg = EP93XX_SYSCON_PWRCNT,
79 .enable_mask = 0x02000000, 79 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
80}; 80};
81static struct clk clk_m2p9 = { 81static struct clk clk_m2p9 = {
82 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 82 .enable_reg = EP93XX_SYSCON_PWRCNT,
83 .enable_mask = 0x01000000, 83 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
84}; 84};
85static struct clk clk_m2m0 = { 85static struct clk clk_m2m0 = {
86 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 86 .enable_reg = EP93XX_SYSCON_PWRCNT,
87 .enable_mask = 0x04000000, 87 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
88}; 88};
89static struct clk clk_m2m1 = { 89static struct clk clk_m2m1 = {
90 .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, 90 .enable_reg = EP93XX_SYSCON_PWRCNT,
91 .enable_mask = 0x08000000, 91 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
92}; 92};
93 93
94#define INIT_CK(dev,con,ck) \ 94#define INIT_CK(dev,con,ck) \
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 78ac1bddc8bc..ab73889e5e88 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -152,9 +152,22 @@
152#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) 152#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000)
153#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) 153#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
154#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) 154#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
155#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) 155#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
156#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 156#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
157#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 157#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
158#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
159#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
160#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
161#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
162#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
163#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
164#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
165#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
166#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
167#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
168#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
169#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
170#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
158#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) 171#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
159#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) 172#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
160#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) 173#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 23:08:52 -0500