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-rw-r--r--drivers/scsi/qla4xxx/ql4_attr.c10
-rw-r--r--drivers/scsi/qla4xxx/ql4_def.h27
-rw-r--r--drivers/scsi/qla4xxx/ql4_glbl.h13
-rw-r--r--drivers/scsi/qla4xxx/ql4_mbx.c96
-rw-r--r--drivers/scsi/qla4xxx/ql4_nx.c273
-rw-r--r--drivers/scsi/qla4xxx/ql4_nx.h34
-rw-r--r--drivers/scsi/qla4xxx/ql4_os.c108
7 files changed, 341 insertions, 220 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_attr.c b/drivers/scsi/qla4xxx/ql4_attr.c
index 71b44f087148..befe4f9fa629 100644
--- a/drivers/scsi/qla4xxx/ql4_attr.c
+++ b/drivers/scsi/qla4xxx/ql4_attr.c
@@ -75,21 +75,21 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj,
75 break; 75 break;
76 case 2: 76 case 2:
77 /* Reset HBA */ 77 /* Reset HBA */
78 qla4_82xx_idc_lock(ha); 78 ha->isp_ops->idc_lock(ha);
79 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 79 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
80 if (dev_state == QLA8XXX_DEV_READY) { 80 if (dev_state == QLA8XXX_DEV_READY) {
81 ql4_printk(KERN_INFO, ha, 81 ql4_printk(KERN_INFO, ha,
82 "%s: Setting Need reset, reset_owner is 0x%x.\n", 82 "%s: Setting Need reset, reset_owner is 0x%x.\n",
83 __func__, ha->func_num); 83 __func__, ha->func_num);
84 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 84 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
85 QLA8XXX_DEV_NEED_RESET); 85 QLA8XXX_DEV_NEED_RESET);
86 set_bit(AF_8XXX_RST_OWNER, &ha->flags); 86 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
87 } else 87 } else
88 ql4_printk(KERN_INFO, ha, 88 ql4_printk(KERN_INFO, ha,
89 "%s: Reset not performed as device state is 0x%x\n", 89 "%s: Reset not performed as device state is 0x%x\n",
90 __func__, dev_state); 90 __func__, dev_state);
91 91
92 qla4_82xx_idc_unlock(ha); 92 ha->isp_ops->idc_unlock(ha);
93 break; 93 break;
94 default: 94 default:
95 /* do nothing */ 95 /* do nothing */
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h
index 82f70db08078..11271a2f551c 100644
--- a/drivers/scsi/qla4xxx/ql4_def.h
+++ b/drivers/scsi/qla4xxx/ql4_def.h
@@ -388,8 +388,10 @@ struct isp_operations {
388 void (*disable_intrs) (struct scsi_qla_host *); 388 void (*disable_intrs) (struct scsi_qla_host *);
389 void (*enable_intrs) (struct scsi_qla_host *); 389 void (*enable_intrs) (struct scsi_qla_host *);
390 int (*start_firmware) (struct scsi_qla_host *); 390 int (*start_firmware) (struct scsi_qla_host *);
391 int (*restart_firmware) (struct scsi_qla_host *);
391 irqreturn_t (*intr_handler) (int , void *); 392 irqreturn_t (*intr_handler) (int , void *);
392 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 393 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
394 int (*need_reset) (struct scsi_qla_host *);
393 int (*reset_chip) (struct scsi_qla_host *); 395 int (*reset_chip) (struct scsi_qla_host *);
394 int (*reset_firmware) (struct scsi_qla_host *); 396 int (*reset_firmware) (struct scsi_qla_host *);
395 void (*queue_iocb) (struct scsi_qla_host *); 397 void (*queue_iocb) (struct scsi_qla_host *);
@@ -397,6 +399,15 @@ struct isp_operations {
397 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 399 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
398 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 400 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
399 int (*get_sys_info) (struct scsi_qla_host *); 401 int (*get_sys_info) (struct scsi_qla_host *);
402 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
403 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
404 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
405 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
406 int (*idc_lock) (struct scsi_qla_host *);
407 void (*idc_unlock) (struct scsi_qla_host *);
408 void (*rom_lock_recovery) (struct scsi_qla_host *);
409 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
410 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
400}; 411};
401 412
402struct ql4_mdump_size_table { 413struct ql4_mdump_size_table {
@@ -733,6 +744,8 @@ struct scsi_qla_host {
733#define MAX_MRB 128 744#define MAX_MRB 128
734 struct mrb *active_mrb_array[MAX_MRB]; 745 struct mrb *active_mrb_array[MAX_MRB];
735 uint32_t mrb_index; 746 uint32_t mrb_index;
747
748 uint32_t *reg_tbl;
736}; 749};
737 750
738struct ql4_task_data { 751struct ql4_task_data {
@@ -942,6 +955,20 @@ static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
942 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 955 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
943 956
944} 957}
958
959static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
960 const uint32_t crb_reg)
961{
962 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
963}
964
965static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
966 const uint32_t crb_reg,
967 const uint32_t value)
968{
969 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
970}
971
945/*---------------------------------------------------------------------------*/ 972/*---------------------------------------------------------------------------*/
946 973
947/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 974/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
diff --git a/drivers/scsi/qla4xxx/ql4_glbl.h b/drivers/scsi/qla4xxx/ql4_glbl.h
index a9f651618c79..1010d717b7db 100644
--- a/drivers/scsi/qla4xxx/ql4_glbl.h
+++ b/drivers/scsi/qla4xxx/ql4_glbl.h
@@ -117,7 +117,7 @@ int qla4_82xx_crb_win_lock(struct scsi_qla_host *);
117void qla4_82xx_crb_win_unlock(struct scsi_qla_host *); 117void qla4_82xx_crb_win_unlock(struct scsi_qla_host *);
118int qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *, ulong *); 118int qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *, ulong *);
119void qla4_82xx_wr_32(struct scsi_qla_host *, ulong, u32); 119void qla4_82xx_wr_32(struct scsi_qla_host *, ulong, u32);
120int qla4_82xx_rd_32(struct scsi_qla_host *, ulong); 120uint32_t qla4_82xx_rd_32(struct scsi_qla_host *, ulong);
121int qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *, u64, void *, int); 121int qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *, u64, void *, int);
122int qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, u64, void *, int); 122int qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, u64, void *, int);
123int qla4_82xx_isp_reset(struct scsi_qla_host *ha); 123int qla4_82xx_isp_reset(struct scsi_qla_host *ha);
@@ -203,6 +203,17 @@ int qla4xxx_req_template_size(struct scsi_qla_host *ha);
203void qla4_8xxx_alloc_sysfs_attr(struct scsi_qla_host *ha); 203void qla4_8xxx_alloc_sysfs_attr(struct scsi_qla_host *ha);
204void qla4_8xxx_free_sysfs_attr(struct scsi_qla_host *ha); 204void qla4_8xxx_free_sysfs_attr(struct scsi_qla_host *ha);
205void qla4xxx_alloc_fw_dump(struct scsi_qla_host *ha); 205void qla4xxx_alloc_fw_dump(struct scsi_qla_host *ha);
206int qla4_82xx_try_start_fw(struct scsi_qla_host *ha);
207int qla4_8xxx_need_reset(struct scsi_qla_host *ha);
208int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data);
209int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data);
210void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha);
211void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
212 int incount);
213void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int outcount);
214void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
215 int incount);
216void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int outcount);
206 217
207extern int ql4xextended_error_logging; 218extern int ql4xextended_error_logging;
208extern int ql4xdontresethba; 219extern int ql4xdontresethba;
diff --git a/drivers/scsi/qla4xxx/ql4_mbx.c b/drivers/scsi/qla4xxx/ql4_mbx.c
index ea08e527faf7..73324fba64bc 100644
--- a/drivers/scsi/qla4xxx/ql4_mbx.c
+++ b/drivers/scsi/qla4xxx/ql4_mbx.c
@@ -10,6 +10,37 @@
10#include "ql4_dbg.h" 10#include "ql4_dbg.h"
11#include "ql4_inline.h" 11#include "ql4_inline.h"
12 12
13void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
14 int in_count)
15{
16 int i;
17
18 /* Load all mailbox registers, except mailbox 0. */
19 for (i = 1; i < in_count; i++)
20 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
21
22 /* Wakeup firmware */
23 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
24 readl(&ha->reg->mailbox[0]);
25 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
26 readl(&ha->reg->ctrl_status);
27}
28
29void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
30{
31 int intr_status;
32
33 intr_status = readl(&ha->reg->ctrl_status);
34 if (intr_status & INTR_PENDING) {
35 /*
36 * Service the interrupt.
37 * The ISR will save the mailbox status registers
38 * to a temporary storage location in the adapter structure.
39 */
40 ha->mbox_status_count = out_count;
41 ha->isp_ops->interrupt_service_routine(ha, intr_status);
42 }
43}
13 44
14/** 45/**
15 * qla4xxx_mailbox_command - issues mailbox commands 46 * qla4xxx_mailbox_command - issues mailbox commands
@@ -30,7 +61,6 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
30 int status = QLA_ERROR; 61 int status = QLA_ERROR;
31 uint8_t i; 62 uint8_t i;
32 u_long wait_count; 63 u_long wait_count;
33 uint32_t intr_status;
34 unsigned long flags = 0; 64 unsigned long flags = 0;
35 uint32_t dev_state; 65 uint32_t dev_state;
36 66
@@ -85,9 +115,9 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
85 goto mbox_exit; 115 goto mbox_exit;
86 } 116 }
87 /* Do not send any mbx cmd if h/w is in failed state*/ 117 /* Do not send any mbx cmd if h/w is in failed state*/
88 qla4_82xx_idc_lock(ha); 118 ha->isp_ops->idc_lock(ha);
89 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 119 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
90 qla4_82xx_idc_unlock(ha); 120 ha->isp_ops->idc_unlock(ha);
91 if (dev_state == QLA8XXX_DEV_FAILED) { 121 if (dev_state == QLA8XXX_DEV_FAILED) {
92 ql4_printk(KERN_WARNING, ha, 122 ql4_printk(KERN_WARNING, ha,
93 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n", 123 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
@@ -102,30 +132,8 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
102 for (i = 0; i < outCount; i++) 132 for (i = 0; i < outCount; i++)
103 ha->mbox_status[i] = 0; 133 ha->mbox_status[i] = 0;
104 134
105 if (is_qla8022(ha)) { 135 /* Queue the mailbox command to the firmware */
106 /* Load all mailbox registers, except mailbox 0. */ 136 ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
107 DEBUG5(
108 printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
109 for (i = 0; i < inCount; i++)
110 printk("mb%d=%04x ", i, mbx_cmd[i]);
111 printk("\n"));
112
113 for (i = 1; i < inCount; i++)
114 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
115 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
116 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
117 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
118 } else {
119 /* Load all mailbox registers, except mailbox 0. */
120 for (i = 1; i < inCount; i++)
121 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
122
123 /* Wakeup firmware */
124 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
125 readl(&ha->reg->mailbox[0]);
126 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
127 readl(&ha->reg->ctrl_status);
128 }
129 137
130 spin_unlock_irqrestore(&ha->hardware_lock, flags); 138 spin_unlock_irqrestore(&ha->hardware_lock, flags);
131 139
@@ -167,37 +175,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
167 */ 175 */
168 176
169 spin_lock_irqsave(&ha->hardware_lock, flags); 177 spin_lock_irqsave(&ha->hardware_lock, flags);
170 if (is_qla8022(ha)) { 178 ha->isp_ops->process_mailbox_interrupt(ha, outCount);
171 intr_status =
172 readl(&ha->qla4_82xx_reg->host_int);
173 if (intr_status & ISRX_82XX_RISC_INT) {
174 ha->mbox_status_count = outCount;
175 intr_status =
176 readl(&ha->qla4_82xx_reg->host_status);
177 ha->isp_ops->interrupt_service_routine(
178 ha, intr_status);
179 if (test_bit(AF_INTERRUPTS_ON,
180 &ha->flags) &&
181 test_bit(AF_INTx_ENABLED,
182 &ha->flags))
183 qla4_82xx_wr_32(ha,
184 ha->nx_legacy_intr.tgt_mask_reg,
185 0xfbff);
186 }
187 } else {
188 intr_status = readl(&ha->reg->ctrl_status);
189 if (intr_status & INTR_PENDING) {
190 /*
191 * Service the interrupt.
192 * The ISR will save the mailbox status
193 * registers to a temporary storage
194 * location in the adapter structure.
195 */
196 ha->mbox_status_count = outCount;
197 ha->isp_ops->interrupt_service_routine(
198 ha, intr_status);
199 }
200 }
201 spin_unlock_irqrestore(&ha->hardware_lock, flags); 179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
202 msleep(10); 180 msleep(10);
203 } 181 }
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index 84b039f9e9b5..13d8e4895f58 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -396,8 +396,7 @@ qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
396 } 396 }
397} 397}
398 398
399int 399uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
400qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
401{ 400{
402 unsigned long flags = 0; 401 unsigned long flags = 0;
403 int rv; 402 int rv;
@@ -422,34 +421,54 @@ qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
422} 421}
423 422
424/* Minidump related functions */ 423/* Minidump related functions */
425static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off, 424int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
426 u32 data, uint8_t flag)
427{ 425{
428 uint32_t win_read, off_value, rval = QLA_SUCCESS; 426 uint32_t win_read, off_value;
427 int rval = QLA_SUCCESS;
429 428
430 off_value = off & 0xFFFF0000; 429 off_value = off & 0xFFFF0000;
431 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 430 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
432 431
433 /* Read back value to make sure write has gone through before trying 432 /*
433 * Read back value to make sure write has gone through before trying
434 * to use it. 434 * to use it.
435 */ 435 */
436 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 436 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
437 if (win_read != off_value) { 437 if (win_read != off_value) {
438 DEBUG2(ql4_printk(KERN_INFO, ha, 438 DEBUG2(ql4_printk(KERN_INFO, ha,
439 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 439 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
440 __func__, off_value, win_read, off)); 440 __func__, off_value, win_read, off));
441 return QLA_ERROR; 441 rval = QLA_ERROR;
442 } else {
443 off_value = off & 0x0000FFFF;
444 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
445 ha->nx_pcibase));
442 } 446 }
447 return rval;
448}
443 449
444 off_value = off & 0x0000FFFF; 450int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
451{
452 uint32_t win_read, off_value;
453 int rval = QLA_SUCCESS;
445 454
446 if (flag) 455 off_value = off & 0xFFFF0000;
456 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
457
458 /* Read back value to make sure write has gone through before trying
459 * to use it.
460 */
461 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
462 if (win_read != off_value) {
463 DEBUG2(ql4_printk(KERN_INFO, ha,
464 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
465 __func__, off_value, win_read, off));
466 rval = QLA_ERROR;
467 } else {
468 off_value = off & 0x0000FFFF;
447 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 469 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
448 ha->nx_pcibase)); 470 ha->nx_pcibase));
449 else 471 }
450 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
451 ha->nx_pcibase));
452
453 return rval; 472 return rval;
454} 473}
455 474
@@ -1491,11 +1510,11 @@ qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1491{ 1510{
1492 uint32_t drv_active; 1511 uint32_t drv_active;
1493 1512
1494 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1513 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1495 drv_active |= (1 << (ha->func_num * 4)); 1514 drv_active |= (1 << (ha->func_num * 4));
1496 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1515 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1497 __func__, ha->host_no, drv_active); 1516 __func__, ha->host_no, drv_active);
1498 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1517 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1499} 1518}
1500 1519
1501void 1520void
@@ -1503,21 +1522,20 @@ qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1503{ 1522{
1504 uint32_t drv_active; 1523 uint32_t drv_active;
1505 1524
1506 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1525 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1507 drv_active &= ~(1 << (ha->func_num * 4)); 1526 drv_active &= ~(1 << (ha->func_num * 4));
1508 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1527 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1509 __func__, ha->host_no, drv_active); 1528 __func__, ha->host_no, drv_active);
1510 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1529 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1511} 1530}
1512 1531
1513static inline int 1532inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1514qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1515{ 1533{
1516 uint32_t drv_state, drv_active; 1534 uint32_t drv_state, drv_active;
1517 int rval; 1535 int rval;
1518 1536
1519 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1537 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1520 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1538 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1521 rval = drv_state & (1 << (ha->func_num * 4)); 1539 rval = drv_state & (1 << (ha->func_num * 4));
1522 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1540 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1523 rval = 1; 1541 rval = 1;
@@ -1530,11 +1548,11 @@ qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1530{ 1548{
1531 uint32_t drv_state; 1549 uint32_t drv_state;
1532 1550
1533 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1551 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1534 drv_state |= (1 << (ha->func_num * 4)); 1552 drv_state |= (1 << (ha->func_num * 4));
1535 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1553 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1536 __func__, ha->host_no, drv_state); 1554 __func__, ha->host_no, drv_state);
1537 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1555 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1538} 1556}
1539 1557
1540static inline void 1558static inline void
@@ -1542,11 +1560,11 @@ qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1542{ 1560{
1543 uint32_t drv_state; 1561 uint32_t drv_state;
1544 1562
1545 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1563 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1546 drv_state &= ~(1 << (ha->func_num * 4)); 1564 drv_state &= ~(1 << (ha->func_num * 4));
1547 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1565 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1548 __func__, ha->host_no, drv_state); 1566 __func__, ha->host_no, drv_state);
1549 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1567 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1550} 1568}
1551 1569
1552static inline void 1570static inline void
@@ -1554,9 +1572,9 @@ qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1554{ 1572{
1555 uint32_t qsnt_state; 1573 uint32_t qsnt_state;
1556 1574
1557 qsnt_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1575 qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1558 qsnt_state |= (2 << (ha->func_num * 4)); 1576 qsnt_state |= (2 << (ha->func_num * 4));
1559 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1577 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1560} 1578}
1561 1579
1562 1580
@@ -1595,8 +1613,7 @@ qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1595 return qla4_82xx_rcvpeg_ready(ha); 1613 return qla4_82xx_rcvpeg_ready(ha);
1596} 1614}
1597 1615
1598static int 1616int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1599qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1600{ 1617{
1601 int rval = QLA_ERROR; 1618 int rval = QLA_ERROR;
1602 1619
@@ -1625,7 +1642,7 @@ qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1625 return rval; 1642 return rval;
1626} 1643}
1627 1644
1628static void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1645void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1629{ 1646{
1630 if (qla4_82xx_rom_lock(ha)) { 1647 if (qla4_82xx_rom_lock(ha)) {
1631 /* Someone else is holding the lock. */ 1648 /* Someone else is holding the lock. */
@@ -1655,7 +1672,7 @@ static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1655 loop_cnt = crb_hdr->op_count; 1672 loop_cnt = crb_hdr->op_count;
1656 1673
1657 for (i = 0; i < loop_cnt; i++) { 1674 for (i = 0; i < loop_cnt; i++) {
1658 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1675 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1659 *data_ptr++ = cpu_to_le32(r_addr); 1676 *data_ptr++ = cpu_to_le32(r_addr);
1660 *data_ptr++ = cpu_to_le32(r_value); 1677 *data_ptr++ = cpu_to_le32(r_value);
1661 r_addr += r_stride; 1678 r_addr += r_stride;
@@ -1690,16 +1707,16 @@ static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1690 p_mask = cache_hdr->cache_ctrl.poll_mask; 1707 p_mask = cache_hdr->cache_ctrl.poll_mask;
1691 1708
1692 for (i = 0; i < loop_count; i++) { 1709 for (i = 0; i < loop_count; i++) {
1693 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1710 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1694 1711
1695 if (c_value_w) 1712 if (c_value_w)
1696 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1713 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1697 1714
1698 if (p_mask) { 1715 if (p_mask) {
1699 w_time = jiffies + p_wait; 1716 w_time = jiffies + p_wait;
1700 do { 1717 do {
1701 c_value_r = qla4_8xxx_md_rw_32(ha, c_addr, 1718 ha->isp_ops->rd_reg_indirect(ha, c_addr,
1702 0, 0); 1719 &c_value_r);
1703 if ((c_value_r & p_mask) == 0) { 1720 if ((c_value_r & p_mask) == 0) {
1704 break; 1721 break;
1705 } else if (time_after_eq(jiffies, w_time)) { 1722 } else if (time_after_eq(jiffies, w_time)) {
@@ -1711,7 +1728,7 @@ static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1711 1728
1712 addr = r_addr; 1729 addr = r_addr;
1713 for (k = 0; k < r_cnt; k++) { 1730 for (k = 0; k < r_cnt; k++) {
1714 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1731 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1715 *data_ptr++ = cpu_to_le32(r_value); 1732 *data_ptr++ = cpu_to_le32(r_value);
1716 addr += cache_hdr->read_ctrl.read_addr_stride; 1733 addr += cache_hdr->read_ctrl.read_addr_stride;
1717 } 1734 }
@@ -1741,47 +1758,48 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1741 for (i = 0; i < crb_entry->op_count; i++) { 1758 for (i = 0; i < crb_entry->op_count; i++) {
1742 opcode = crb_entry->crb_ctrl.opcode; 1759 opcode = crb_entry->crb_ctrl.opcode;
1743 if (opcode & QLA8XXX_DBG_OPCODE_WR) { 1760 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
1744 qla4_8xxx_md_rw_32(ha, crb_addr, 1761 ha->isp_ops->wr_reg_indirect(ha, crb_addr,
1745 crb_entry->value_1, 1); 1762 crb_entry->value_1);
1746 opcode &= ~QLA8XXX_DBG_OPCODE_WR; 1763 opcode &= ~QLA8XXX_DBG_OPCODE_WR;
1747 } 1764 }
1748 if (opcode & QLA8XXX_DBG_OPCODE_RW) { 1765 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
1749 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1766 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1750 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1767 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1751 opcode &= ~QLA8XXX_DBG_OPCODE_RW; 1768 opcode &= ~QLA8XXX_DBG_OPCODE_RW;
1752 } 1769 }
1753 if (opcode & QLA8XXX_DBG_OPCODE_AND) { 1770 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
1754 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1771 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1755 read_value &= crb_entry->value_2; 1772 read_value &= crb_entry->value_2;
1756 opcode &= ~QLA8XXX_DBG_OPCODE_AND; 1773 opcode &= ~QLA8XXX_DBG_OPCODE_AND;
1757 if (opcode & QLA8XXX_DBG_OPCODE_OR) { 1774 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1758 read_value |= crb_entry->value_3; 1775 read_value |= crb_entry->value_3;
1759 opcode &= ~QLA8XXX_DBG_OPCODE_OR; 1776 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1760 } 1777 }
1761 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1778 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1762 } 1779 }
1763 if (opcode & QLA8XXX_DBG_OPCODE_OR) { 1780 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
1764 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1781 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1765 read_value |= crb_entry->value_3; 1782 read_value |= crb_entry->value_3;
1766 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1783 ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
1767 opcode &= ~QLA8XXX_DBG_OPCODE_OR; 1784 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
1768 } 1785 }
1769 if (opcode & QLA8XXX_DBG_OPCODE_POLL) { 1786 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
1770 poll_time = crb_entry->crb_strd.poll_timeout; 1787 poll_time = crb_entry->crb_strd.poll_timeout;
1771 wtime = jiffies + poll_time; 1788 wtime = jiffies + poll_time;
1772 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1789 ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
1773 1790
1774 do { 1791 do {
1775 if ((read_value & crb_entry->value_2) == 1792 if ((read_value & crb_entry->value_2) ==
1776 crb_entry->value_1) 1793 crb_entry->value_1) {
1777 break; 1794 break;
1778 else if (time_after_eq(jiffies, wtime)) { 1795 } else if (time_after_eq(jiffies, wtime)) {
1779 /* capturing dump failed */ 1796 /* capturing dump failed */
1780 rval = QLA_ERROR; 1797 rval = QLA_ERROR;
1781 break; 1798 break;
1782 } else 1799 } else {
1783 read_value = qla4_8xxx_md_rw_32(ha, 1800 ha->isp_ops->rd_reg_indirect(ha,
1784 crb_addr, 0, 0); 1801 crb_addr, &read_value);
1802 }
1785 } while (1); 1803 } while (1);
1786 opcode &= ~QLA8XXX_DBG_OPCODE_POLL; 1804 opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
1787 } 1805 }
@@ -1794,7 +1812,7 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1794 addr = crb_addr; 1812 addr = crb_addr;
1795 } 1813 }
1796 1814
1797 read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1815 ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
1798 index = crb_entry->crb_ctrl.state_index_v; 1816 index = crb_entry->crb_ctrl.state_index_v;
1799 tmplt_hdr->saved_state_array[index] = read_value; 1817 tmplt_hdr->saved_state_array[index] = read_value;
1800 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; 1818 opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
@@ -1816,7 +1834,7 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1816 read_value = crb_entry->value_1; 1834 read_value = crb_entry->value_1;
1817 } 1835 }
1818 1836
1819 qla4_8xxx_md_rw_32(ha, addr, read_value, 1); 1837 ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
1820 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; 1838 opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
1821 } 1839 }
1822 1840
@@ -1883,8 +1901,8 @@ static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1883 loop_cnt = mux_hdr->op_count; 1901 loop_cnt = mux_hdr->op_count;
1884 1902
1885 for (i = 0; i < loop_cnt; i++) { 1903 for (i = 0; i < loop_cnt; i++) {
1886 qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1); 1904 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
1887 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1905 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1888 *data_ptr++ = cpu_to_le32(s_value); 1906 *data_ptr++ = cpu_to_le32(s_value);
1889 *data_ptr++ = cpu_to_le32(r_value); 1907 *data_ptr++ = cpu_to_le32(r_value);
1890 s_value += s_stride; 1908 s_value += s_stride;
@@ -1913,11 +1931,11 @@ static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1913 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1931 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1914 1932
1915 for (i = 0; i < loop_count; i++) { 1933 for (i = 0; i < loop_count; i++) {
1916 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1934 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
1917 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1935 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
1918 addr = r_addr; 1936 addr = r_addr;
1919 for (k = 0; k < r_cnt; k++) { 1937 for (k = 0; k < r_cnt; k++) {
1920 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1938 ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
1921 *data_ptr++ = cpu_to_le32(r_value); 1939 *data_ptr++ = cpu_to_le32(r_value);
1922 addr += cache_hdr->read_ctrl.read_addr_stride; 1940 addr += cache_hdr->read_ctrl.read_addr_stride;
1923 } 1941 }
@@ -1944,10 +1962,10 @@ static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
1944 loop_cnt = q_hdr->op_count; 1962 loop_cnt = q_hdr->op_count;
1945 1963
1946 for (i = 0; i < loop_cnt; i++) { 1964 for (i = 0; i < loop_cnt; i++) {
1947 qla4_8xxx_md_rw_32(ha, s_addr, qid, 1); 1965 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
1948 r_addr = q_hdr->read_addr; 1966 r_addr = q_hdr->read_addr;
1949 for (k = 0; k < r_cnt; k++) { 1967 for (k = 0; k < r_cnt; k++) {
1950 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1968 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1951 *data_ptr++ = cpu_to_le32(r_value); 1969 *data_ptr++ = cpu_to_le32(r_value);
1952 r_addr += r_stride; 1970 r_addr += r_stride;
1953 } 1971 }
@@ -1978,11 +1996,11 @@ static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
1978 __func__, r_addr, loop_cnt)); 1996 __func__, r_addr, loop_cnt));
1979 1997
1980 for (i = 0; i < loop_cnt; i++) { 1998 for (i = 0; i < loop_cnt; i++) {
1981 qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 1999 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
1982 (r_addr & 0xFFFF0000), 1); 2000 (r_addr & 0xFFFF0000));
1983 r_value = qla4_8xxx_md_rw_32(ha, 2001 ha->isp_ops->rd_reg_indirect(ha,
1984 MD_DIRECT_ROM_READ_BASE + 2002 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
1985 (r_addr & 0x0000FFFF), 0, 0); 2003 &r_value);
1986 *data_ptr++ = cpu_to_le32(r_value); 2004 *data_ptr++ = cpu_to_le32(r_value);
1987 r_addr += sizeof(uint32_t); 2005 r_addr += sizeof(uint32_t);
1988 } 2006 }
@@ -2032,17 +2050,19 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2032 2050
2033 write_lock_irqsave(&ha->hw_lock, flags); 2051 write_lock_irqsave(&ha->hw_lock, flags);
2034 for (i = 0; i < loop_cnt; i++) { 2052 for (i = 0; i < loop_cnt; i++) {
2035 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 2053 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2054 r_addr);
2036 r_value = 0; 2055 r_value = 0;
2037 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 2056 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2057 r_value);
2038 r_value = MIU_TA_CTL_ENABLE; 2058 r_value = MIU_TA_CTL_ENABLE;
2039 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2059 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2040 r_value = MIU_TA_CTL_START_ENABLE; 2060 r_value = MIU_TA_CTL_START_ENABLE;
2041 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2061 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2042 2062
2043 for (j = 0; j < MAX_CTL_CHECK; j++) { 2063 for (j = 0; j < MAX_CTL_CHECK; j++) {
2044 r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, 2064 ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2045 0, 0); 2065 &r_value);
2046 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2066 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2047 break; 2067 break;
2048 } 2068 }
@@ -2056,9 +2076,9 @@ static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2056 } 2076 }
2057 2077
2058 for (j = 0; j < 4; j++) { 2078 for (j = 0; j < 4; j++) {
2059 r_data = qla4_8xxx_md_rw_32(ha, 2079 ha->isp_ops->rd_reg_indirect(ha,
2060 MD_MIU_TEST_AGT_RDDATA[j], 2080 MD_MIU_TEST_AGT_RDDATA[j],
2061 0, 0); 2081 &r_data);
2062 *data_ptr++ = cpu_to_le32(r_data); 2082 *data_ptr++ = cpu_to_le32(r_data);
2063 } 2083 }
2064 2084
@@ -2277,19 +2297,18 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2277 uint32_t old_count, count; 2297 uint32_t old_count, count;
2278 int need_reset = 0, peg_stuck = 1; 2298 int need_reset = 0, peg_stuck = 1;
2279 2299
2280 need_reset = qla4_8xxx_need_reset(ha); 2300 need_reset = ha->isp_ops->need_reset(ha);
2281 2301 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2282 old_count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2283 2302
2284 for (i = 0; i < 10; i++) { 2303 for (i = 0; i < 10; i++) {
2285 timeout = msleep_interruptible(200); 2304 timeout = msleep_interruptible(200);
2286 if (timeout) { 2305 if (timeout) {
2287 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2306 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2288 QLA8XXX_DEV_FAILED); 2307 QLA8XXX_DEV_FAILED);
2289 return rval; 2308 return rval;
2290 } 2309 }
2291 2310
2292 count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2311 count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
2293 if (count != old_count) 2312 if (count != old_count)
2294 peg_stuck = 0; 2313 peg_stuck = 0;
2295 } 2314 }
@@ -2297,13 +2316,13 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2297 if (need_reset) { 2316 if (need_reset) {
2298 /* We are trying to perform a recovery here. */ 2317 /* We are trying to perform a recovery here. */
2299 if (peg_stuck) 2318 if (peg_stuck)
2300 qla4_82xx_rom_lock_recovery(ha); 2319 ha->isp_ops->rom_lock_recovery(ha);
2301 goto dev_initialize; 2320 goto dev_initialize;
2302 } else { 2321 } else {
2303 /* Start of day for this ha context. */ 2322 /* Start of day for this ha context. */
2304 if (peg_stuck) { 2323 if (peg_stuck) {
2305 /* Either we are the first or recovery in progress. */ 2324 /* Either we are the first or recovery in progress. */
2306 qla4_82xx_rom_lock_recovery(ha); 2325 ha->isp_ops->rom_lock_recovery(ha);
2307 goto dev_initialize; 2326 goto dev_initialize;
2308 } else { 2327 } else {
2309 /* Firmware already running. */ 2328 /* Firmware already running. */
@@ -2315,12 +2334,14 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2315dev_initialize: 2334dev_initialize:
2316 /* set to DEV_INITIALIZING */ 2335 /* set to DEV_INITIALIZING */
2317 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 2336 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2318 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 2337 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2338 QLA8XXX_DEV_INITIALIZING);
2319 2339
2320 /* Driver that sets device state to initializating sets IDC version */ 2340 /* Driver that sets device state to initializating sets IDC version */
2321 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2341 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
2342 QLA82XX_IDC_VERSION);
2322 2343
2323 qla4_82xx_idc_unlock(ha); 2344 ha->isp_ops->idc_unlock(ha);
2324 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 2345 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2325 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 2346 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2326 if (!qla4_8xxx_collect_md_data(ha)) { 2347 if (!qla4_8xxx_collect_md_data(ha)) {
@@ -2330,19 +2351,20 @@ dev_initialize:
2330 clear_bit(AF_82XX_FW_DUMPED, &ha->flags); 2351 clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2331 } 2352 }
2332 } 2353 }
2333 rval = qla4_82xx_try_start_fw(ha); 2354 rval = ha->isp_ops->restart_firmware(ha);
2334 qla4_82xx_idc_lock(ha); 2355 ha->isp_ops->idc_lock(ha);
2335 2356
2336 if (rval != QLA_SUCCESS) { 2357 if (rval != QLA_SUCCESS) {
2337 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 2358 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2338 qla4_8xxx_clear_drv_active(ha); 2359 qla4_8xxx_clear_drv_active(ha);
2339 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); 2360 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2361 QLA8XXX_DEV_FAILED);
2340 return rval; 2362 return rval;
2341 } 2363 }
2342 2364
2343dev_ready: 2365dev_ready:
2344 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 2366 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2345 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2367 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2346 2368
2347 return rval; 2369 return rval;
2348} 2370}
@@ -2436,9 +2458,9 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2436void 2458void
2437qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 2459qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2438{ 2460{
2439 qla4_82xx_idc_lock(ha); 2461 ha->isp_ops->idc_lock(ha);
2440 qla4_8xxx_set_qsnt_ready(ha); 2462 qla4_8xxx_set_qsnt_ready(ha);
2441 qla4_82xx_idc_unlock(ha); 2463 ha->isp_ops->idc_unlock(ha);
2442} 2464}
2443 2465
2444/** 2466/**
@@ -2454,12 +2476,12 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2454 unsigned long dev_init_timeout; 2476 unsigned long dev_init_timeout;
2455 2477
2456 if (!test_bit(AF_INIT_DONE, &ha->flags)) { 2478 if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2457 qla4_82xx_idc_lock(ha); 2479 ha->isp_ops->idc_lock(ha);
2458 qla4_8xxx_set_drv_active(ha); 2480 qla4_8xxx_set_drv_active(ha);
2459 qla4_82xx_idc_unlock(ha); 2481 ha->isp_ops->idc_unlock(ha);
2460 } 2482 }
2461 2483
2462 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2484 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2463 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2485 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2464 dev_state, dev_state < MAX_STATES ? 2486 dev_state, dev_state < MAX_STATES ?
2465 qdev_state[dev_state] : "Unknown")); 2487 qdev_state[dev_state] : "Unknown"));
@@ -2467,7 +2489,7 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2467 /* wait for 30 seconds for device to go ready */ 2489 /* wait for 30 seconds for device to go ready */
2468 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 2490 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2469 2491
2470 qla4_82xx_idc_lock(ha); 2492 ha->isp_ops->idc_lock(ha);
2471 while (1) { 2493 while (1) {
2472 2494
2473 if (time_after_eq(jiffies, dev_init_timeout)) { 2495 if (time_after_eq(jiffies, dev_init_timeout)) {
@@ -2476,11 +2498,11 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2476 DRIVER_NAME, 2498 DRIVER_NAME,
2477 dev_state, dev_state < MAX_STATES ? 2499 dev_state, dev_state < MAX_STATES ?
2478 qdev_state[dev_state] : "Unknown"); 2500 qdev_state[dev_state] : "Unknown");
2479 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2501 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
2480 QLA8XXX_DEV_FAILED); 2502 QLA8XXX_DEV_FAILED);
2481 } 2503 }
2482 2504
2483 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2505 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2484 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2506 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2485 dev_state, dev_state < MAX_STATES ? 2507 dev_state, dev_state < MAX_STATES ?
2486 qdev_state[dev_state] : "Unknown"); 2508 qdev_state[dev_state] : "Unknown");
@@ -2493,9 +2515,9 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2493 rval = qla4_8xxx_device_bootstrap(ha); 2515 rval = qla4_8xxx_device_bootstrap(ha);
2494 goto exit; 2516 goto exit;
2495 case QLA8XXX_DEV_INITIALIZING: 2517 case QLA8XXX_DEV_INITIALIZING:
2496 qla4_82xx_idc_unlock(ha); 2518 ha->isp_ops->idc_unlock(ha);
2497 msleep(1000); 2519 msleep(1000);
2498 qla4_82xx_idc_lock(ha); 2520 ha->isp_ops->idc_lock(ha);
2499 break; 2521 break;
2500 case QLA8XXX_DEV_NEED_RESET: 2522 case QLA8XXX_DEV_NEED_RESET:
2501 if (!ql4xdontresethba) { 2523 if (!ql4xdontresethba) {
@@ -2505,9 +2527,9 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2505 dev_init_timeout = jiffies + 2527 dev_init_timeout = jiffies +
2506 (ha->nx_dev_init_timeout * HZ); 2528 (ha->nx_dev_init_timeout * HZ);
2507 } else { 2529 } else {
2508 qla4_82xx_idc_unlock(ha); 2530 ha->isp_ops->idc_unlock(ha);
2509 msleep(1000); 2531 msleep(1000);
2510 qla4_82xx_idc_lock(ha); 2532 ha->isp_ops->idc_lock(ha);
2511 } 2533 }
2512 break; 2534 break;
2513 case QLA8XXX_DEV_NEED_QUIESCENT: 2535 case QLA8XXX_DEV_NEED_QUIESCENT:
@@ -2515,26 +2537,26 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2515 qla4_8xxx_need_qsnt_handler(ha); 2537 qla4_8xxx_need_qsnt_handler(ha);
2516 break; 2538 break;
2517 case QLA8XXX_DEV_QUIESCENT: 2539 case QLA8XXX_DEV_QUIESCENT:
2518 qla4_82xx_idc_unlock(ha); 2540 ha->isp_ops->idc_unlock(ha);
2519 msleep(1000); 2541 msleep(1000);
2520 qla4_82xx_idc_lock(ha); 2542 ha->isp_ops->idc_lock(ha);
2521 break; 2543 break;
2522 case QLA8XXX_DEV_FAILED: 2544 case QLA8XXX_DEV_FAILED:
2523 qla4_82xx_idc_unlock(ha); 2545 ha->isp_ops->idc_unlock(ha);
2524 qla4xxx_dead_adapter_cleanup(ha); 2546 qla4xxx_dead_adapter_cleanup(ha);
2525 rval = QLA_ERROR; 2547 rval = QLA_ERROR;
2526 qla4_82xx_idc_lock(ha); 2548 ha->isp_ops->idc_lock(ha);
2527 goto exit; 2549 goto exit;
2528 default: 2550 default:
2529 qla4_82xx_idc_unlock(ha); 2551 ha->isp_ops->idc_unlock(ha);
2530 qla4xxx_dead_adapter_cleanup(ha); 2552 qla4xxx_dead_adapter_cleanup(ha);
2531 rval = QLA_ERROR; 2553 rval = QLA_ERROR;
2532 qla4_82xx_idc_lock(ha); 2554 ha->isp_ops->idc_lock(ha);
2533 goto exit; 2555 goto exit;
2534 } 2556 }
2535 } 2557 }
2536exit: 2558exit:
2537 qla4_82xx_idc_unlock(ha); 2559 ha->isp_ops->idc_unlock(ha);
2538 return rval; 2560 return rval;
2539} 2561}
2540 2562
@@ -2822,6 +2844,39 @@ qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
2822 return; 2844 return;
2823} 2845}
2824 2846
2847void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
2848 int in_count)
2849{
2850 int i;
2851
2852 /* Load all mailbox registers, except mailbox 0. */
2853 for (i = 1; i < in_count; i++)
2854 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
2855
2856 /* Wakeup firmware */
2857 writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
2858 readl(&ha->qla4_82xx_reg->mailbox_in[0]);
2859 writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
2860 readl(&ha->qla4_82xx_reg->hint);
2861}
2862
2863void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
2864{
2865 int intr_status;
2866
2867 intr_status = readl(&ha->qla4_82xx_reg->host_int);
2868 if (intr_status & ISRX_82XX_RISC_INT) {
2869 ha->mbox_status_count = out_count;
2870 intr_status = readl(&ha->qla4_82xx_reg->host_status);
2871 ha->isp_ops->interrupt_service_routine(ha, intr_status);
2872
2873 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
2874 test_bit(AF_INTx_ENABLED, &ha->flags))
2875 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
2876 0xfbff);
2877 }
2878}
2879
2825int 2880int
2826qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2881qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2827{ 2882{
diff --git a/drivers/scsi/qla4xxx/ql4_nx.h b/drivers/scsi/qla4xxx/ql4_nx.h
index 16c5ae6d271a..1894de093f06 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.h
+++ b/drivers/scsi/qla4xxx/ql4_nx.h
@@ -579,6 +579,40 @@ enum {
579#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 579#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
580#define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) 580#define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
581 581
582enum qla_regs {
583 QLA8XXX_PEG_HALT_STATUS1 = 0,
584 QLA8XXX_PEG_HALT_STATUS2,
585 QLA8XXX_PEG_ALIVE_COUNTER,
586 QLA8XXX_CRB_DRV_ACTIVE,
587 QLA8XXX_CRB_DEV_STATE,
588 QLA8XXX_CRB_DRV_STATE,
589 QLA8XXX_CRB_DRV_SCRATCH,
590 QLA8XXX_CRB_DEV_PART_INFO,
591 QLA8XXX_CRB_DRV_IDC_VERSION,
592 QLA8XXX_FW_VERSION_MAJOR,
593 QLA8XXX_FW_VERSION_MINOR,
594 QLA8XXX_FW_VERSION_SUB,
595 QLA8XXX_CRB_CMDPEG_STATE,
596 QLA8XXX_CRB_TEMP_STATE,
597};
598
599static const uint32_t qla4_82xx_reg_tbl[] = {
600 QLA82XX_PEG_HALT_STATUS1,
601 QLA82XX_PEG_HALT_STATUS2,
602 QLA82XX_PEG_ALIVE_COUNTER,
603 QLA82XX_CRB_DRV_ACTIVE,
604 QLA82XX_CRB_DEV_STATE,
605 QLA82XX_CRB_DRV_STATE,
606 QLA82XX_CRB_DRV_SCRATCH,
607 QLA82XX_CRB_DEV_PART_INFO,
608 QLA82XX_CRB_DRV_IDC_VERSION,
609 QLA82XX_FW_VERSION_MAJOR,
610 QLA82XX_FW_VERSION_MINOR,
611 QLA82XX_FW_VERSION_SUB,
612 CRB_CMDPEG_STATE,
613 CRB_TEMP_STATE,
614};
615
582/* Every driver should use these Device State */ 616/* Every driver should use these Device State */
583#define QLA8XXX_DEV_COLD 1 617#define QLA8XXX_DEV_COLD 1
584#define QLA8XXX_DEV_INITIALIZING 2 618#define QLA8XXX_DEV_INITIALIZING 2
diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c
index 6aa508c5e4c6..ea8845ba0aaa 100644
--- a/drivers/scsi/qla4xxx/ql4_os.c
+++ b/drivers/scsi/qla4xxx/ql4_os.c
@@ -2420,7 +2420,7 @@ static int qla4_8xxx_check_temp(struct scsi_qla_host *ha)
2420 uint32_t temp, temp_state, temp_val; 2420 uint32_t temp, temp_state, temp_val;
2421 int status = QLA_SUCCESS; 2421 int status = QLA_SUCCESS;
2422 2422
2423 temp = qla4_82xx_rd_32(ha, CRB_TEMP_STATE); 2423 temp = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_TEMP_STATE);
2424 2424
2425 temp_state = qla82xx_get_temp_state(temp); 2425 temp_state = qla82xx_get_temp_state(temp);
2426 temp_val = qla82xx_get_temp_val(temp); 2426 temp_val = qla82xx_get_temp_val(temp);
@@ -2454,9 +2454,11 @@ static int qla4_8xxx_check_temp(struct scsi_qla_host *ha)
2454static int qla4_8xxx_check_fw_alive(struct scsi_qla_host *ha) 2454static int qla4_8xxx_check_fw_alive(struct scsi_qla_host *ha)
2455{ 2455{
2456 uint32_t fw_heartbeat_counter; 2456 uint32_t fw_heartbeat_counter;
2457 uint32_t halt_status1, halt_status2;
2457 int status = QLA_SUCCESS; 2458 int status = QLA_SUCCESS;
2458 2459
2459 fw_heartbeat_counter = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2460 fw_heartbeat_counter = qla4_8xxx_rd_direct(ha,
2461 QLA8XXX_PEG_ALIVE_COUNTER);
2460 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */ 2462 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
2461 if (fw_heartbeat_counter == 0xffffffff) { 2463 if (fw_heartbeat_counter == 0xffffffff) {
2462 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Device in frozen " 2464 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Device in frozen "
@@ -2470,18 +2472,18 @@ static int qla4_8xxx_check_fw_alive(struct scsi_qla_host *ha)
2470 /* FW not alive after 2 seconds */ 2472 /* FW not alive after 2 seconds */
2471 if (ha->seconds_since_last_heartbeat == 2) { 2473 if (ha->seconds_since_last_heartbeat == 2) {
2472 ha->seconds_since_last_heartbeat = 0; 2474 ha->seconds_since_last_heartbeat = 0;
2475 halt_status1 = qla4_8xxx_rd_direct(ha,
2476 QLA8XXX_PEG_HALT_STATUS1);
2477 halt_status2 = qla4_8xxx_rd_direct(ha,
2478 QLA8XXX_PEG_HALT_STATUS2);
2473 2479
2474 ql4_printk(KERN_INFO, ha, 2480 ql4_printk(KERN_INFO, ha,
2475 "scsi(%ld): %s, Dumping hw/fw registers:\n " 2481 "scsi(%ld): %s, Dumping hw/fw registers:\n "
2476 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2:" 2482 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2:"
2477 " 0x%x,\n PEG_NET_0_PC: 0x%x, PEG_NET_1_PC:" 2483 " 0x%x,\n PEG_NET_0_PC: 0x%x, PEG_NET_1_PC:"
2478 " 0x%x,\n PEG_NET_2_PC: 0x%x, PEG_NET_3_PC:" 2484 " 0x%x,\n PEG_NET_2_PC: 0x%x, PEG_NET_3_PC:"
2479 " 0x%x,\n PEG_NET_4_PC: 0x%x\n", 2485 " 0x%x,\n PEG_NET_4_PC: 0x%x\n", ha->host_no,
2480 ha->host_no, __func__, 2486 __func__, halt_status1, halt_status2,
2481 qla4_82xx_rd_32(ha,
2482 QLA82XX_PEG_HALT_STATUS1),
2483 qla4_82xx_rd_32(ha,
2484 QLA82XX_PEG_HALT_STATUS2),
2485 qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 2487 qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 +
2486 0x3c), 2488 0x3c),
2487 qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 2489 qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 +
@@ -2515,7 +2517,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
2515 if (!(test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 2517 if (!(test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
2516 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 2518 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
2517 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags))) { 2519 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags))) {
2518 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2520 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
2519 2521
2520 if (qla4_8xxx_check_temp(ha)) { 2522 if (qla4_8xxx_check_temp(ha)) {
2521 ql4_printk(KERN_INFO, ha, "disabling pause" 2523 ql4_printk(KERN_INFO, ha, "disabling pause"
@@ -2547,8 +2549,8 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
2547 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, 2549 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
2548 CRB_NIU_XG_PAUSE_CTL_P0 | 2550 CRB_NIU_XG_PAUSE_CTL_P0 |
2549 CRB_NIU_XG_PAUSE_CTL_P1); 2551 CRB_NIU_XG_PAUSE_CTL_P1);
2550 halt_status = qla4_82xx_rd_32(ha, 2552 halt_status = qla4_8xxx_rd_direct(ha,
2551 QLA82XX_PEG_HALT_STATUS1); 2553 QLA8XXX_PEG_HALT_STATUS1);
2552 2554
2553 if (QLA82XX_FWERROR_CODE(halt_status) == 0x67) 2555 if (QLA82XX_FWERROR_CODE(halt_status) == 0x67)
2554 ql4_printk(KERN_ERR, ha, "%s:" 2556 ql4_printk(KERN_ERR, ha, "%s:"
@@ -3040,9 +3042,10 @@ recover_ha_init_adapter:
3040 * with multiple resets in the same thread, 3042 * with multiple resets in the same thread,
3041 * utilize DPC to retry */ 3043 * utilize DPC to retry */
3042 if (is_qla8022(ha)) { 3044 if (is_qla8022(ha)) {
3043 qla4_82xx_idc_lock(ha); 3045 ha->isp_ops->idc_lock(ha);
3044 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3046 dev_state = qla4_8xxx_rd_direct(ha,
3045 qla4_82xx_idc_unlock(ha); 3047 QLA8XXX_CRB_DEV_STATE);
3048 ha->isp_ops->idc_unlock(ha);
3046 if (dev_state == QLA8XXX_DEV_FAILED) { 3049 if (dev_state == QLA8XXX_DEV_FAILED) {
3047 ql4_printk(KERN_INFO, ha, "%s: don't retry " 3050 ql4_printk(KERN_INFO, ha, "%s: don't retry "
3048 "recover adapter. H/W is in Failed " 3051 "recover adapter. H/W is in Failed "
@@ -3385,10 +3388,10 @@ static void qla4xxx_do_dpc(struct work_struct *work)
3385 3388
3386 if (is_qla8022(ha)) { 3389 if (is_qla8022(ha)) {
3387 if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) { 3390 if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) {
3388 qla4_82xx_idc_lock(ha); 3391 ha->isp_ops->idc_lock(ha);
3389 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3392 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3390 QLA8XXX_DEV_FAILED); 3393 QLA8XXX_DEV_FAILED);
3391 qla4_82xx_idc_unlock(ha); 3394 ha->isp_ops->idc_unlock(ha);
3392 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3395 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3393 qla4_8xxx_device_state_handler(ha); 3396 qla4_8xxx_device_state_handler(ha);
3394 } 3397 }
@@ -3512,9 +3515,9 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha)
3512 ha->isp_ops->reset_firmware(ha); 3515 ha->isp_ops->reset_firmware(ha);
3513 3516
3514 if (is_qla8022(ha)) { 3517 if (is_qla8022(ha)) {
3515 qla4_82xx_idc_lock(ha); 3518 ha->isp_ops->idc_lock(ha);
3516 qla4_8xxx_clear_drv_active(ha); 3519 qla4_8xxx_clear_drv_active(ha);
3517 qla4_82xx_idc_unlock(ha); 3520 ha->isp_ops->idc_unlock(ha);
3518 } 3521 }
3519 3522
3520 /* Detach interrupts */ 3523 /* Detach interrupts */
@@ -3658,6 +3661,8 @@ static struct isp_operations qla4xxx_isp_ops = {
3658 .rd_shdw_req_q_out = qla4xxx_rd_shdw_req_q_out, 3661 .rd_shdw_req_q_out = qla4xxx_rd_shdw_req_q_out,
3659 .rd_shdw_rsp_q_in = qla4xxx_rd_shdw_rsp_q_in, 3662 .rd_shdw_rsp_q_in = qla4xxx_rd_shdw_rsp_q_in,
3660 .get_sys_info = qla4xxx_get_sys_info, 3663 .get_sys_info = qla4xxx_get_sys_info,
3664 .queue_mailbox_command = qla4xxx_queue_mbox_cmd,
3665 .process_mailbox_interrupt = qla4xxx_process_mbox_intr,
3661}; 3666};
3662 3667
3663static struct isp_operations qla4_82xx_isp_ops = { 3668static struct isp_operations qla4_82xx_isp_ops = {
@@ -3666,8 +3671,10 @@ static struct isp_operations qla4_82xx_isp_ops = {
3666 .disable_intrs = qla4_82xx_disable_intrs, 3671 .disable_intrs = qla4_82xx_disable_intrs,
3667 .enable_intrs = qla4_82xx_enable_intrs, 3672 .enable_intrs = qla4_82xx_enable_intrs,
3668 .start_firmware = qla4_8xxx_load_risc, 3673 .start_firmware = qla4_8xxx_load_risc,
3674 .restart_firmware = qla4_82xx_try_start_fw,
3669 .intr_handler = qla4_82xx_intr_handler, 3675 .intr_handler = qla4_82xx_intr_handler,
3670 .interrupt_service_routine = qla4_82xx_interrupt_service_routine, 3676 .interrupt_service_routine = qla4_82xx_interrupt_service_routine,
3677 .need_reset = qla4_8xxx_need_reset,
3671 .reset_chip = qla4_82xx_isp_reset, 3678 .reset_chip = qla4_82xx_isp_reset,
3672 .reset_firmware = qla4_8xxx_stop_firmware, 3679 .reset_firmware = qla4_8xxx_stop_firmware,
3673 .queue_iocb = qla4_82xx_queue_iocb, 3680 .queue_iocb = qla4_82xx_queue_iocb,
@@ -3675,6 +3682,15 @@ static struct isp_operations qla4_82xx_isp_ops = {
3675 .rd_shdw_req_q_out = qla4_82xx_rd_shdw_req_q_out, 3682 .rd_shdw_req_q_out = qla4_82xx_rd_shdw_req_q_out,
3676 .rd_shdw_rsp_q_in = qla4_82xx_rd_shdw_rsp_q_in, 3683 .rd_shdw_rsp_q_in = qla4_82xx_rd_shdw_rsp_q_in,
3677 .get_sys_info = qla4_8xxx_get_sys_info, 3684 .get_sys_info = qla4_8xxx_get_sys_info,
3685 .rd_reg_direct = qla4_82xx_rd_32,
3686 .wr_reg_direct = qla4_82xx_wr_32,
3687 .rd_reg_indirect = qla4_82xx_md_rd_32,
3688 .wr_reg_indirect = qla4_82xx_md_wr_32,
3689 .idc_lock = qla4_82xx_idc_lock,
3690 .idc_unlock = qla4_82xx_idc_unlock,
3691 .rom_lock_recovery = qla4_82xx_rom_lock_recovery,
3692 .queue_mailbox_command = qla4_82xx_queue_mbox_cmd,
3693 .process_mailbox_interrupt = qla4_82xx_process_mbox_intr,
3678}; 3694};
3679 3695
3680uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha) 3696uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
@@ -5075,6 +5091,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
5075 /* Setup Runtime configurable options */ 5091 /* Setup Runtime configurable options */
5076 if (is_qla8022(ha)) { 5092 if (is_qla8022(ha)) {
5077 ha->isp_ops = &qla4_82xx_isp_ops; 5093 ha->isp_ops = &qla4_82xx_isp_ops;
5094 ha->reg_tbl = (uint32_t *) qla4_82xx_reg_tbl;
5078 rwlock_init(&ha->hw_lock); 5095 rwlock_init(&ha->hw_lock);
5079 ha->qdr_sn_window = -1; 5096 ha->qdr_sn_window = -1;
5080 ha->ddr_mn_window = -1; 5097 ha->ddr_mn_window = -1;
@@ -5161,9 +5178,10 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
5161 init_retry_count++ < MAX_INIT_RETRIES) { 5178 init_retry_count++ < MAX_INIT_RETRIES) {
5162 5179
5163 if (is_qla8022(ha)) { 5180 if (is_qla8022(ha)) {
5164 qla4_82xx_idc_lock(ha); 5181 ha->isp_ops->idc_lock(ha);
5165 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 5182 dev_state = qla4_8xxx_rd_direct(ha,
5166 qla4_82xx_idc_unlock(ha); 5183 QLA82XX_CRB_DEV_STATE);
5184 ha->isp_ops->idc_unlock(ha);
5167 if (dev_state == QLA8XXX_DEV_FAILED) { 5185 if (dev_state == QLA8XXX_DEV_FAILED) {
5168 ql4_printk(KERN_WARNING, ha, "%s: don't retry " 5186 ql4_printk(KERN_WARNING, ha, "%s: don't retry "
5169 "initialize adapter. H/W is in failed state\n", 5187 "initialize adapter. H/W is in failed state\n",
@@ -5186,10 +5204,10 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
5186 if (is_qla8022(ha) && ql4xdontresethba) { 5204 if (is_qla8022(ha) && ql4xdontresethba) {
5187 /* Put the device in failed state. */ 5205 /* Put the device in failed state. */
5188 DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n")); 5206 DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n"));
5189 qla4_82xx_idc_lock(ha); 5207 ha->isp_ops->idc_lock(ha);
5190 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5208 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
5191 QLA8XXX_DEV_FAILED); 5209 QLA8XXX_DEV_FAILED);
5192 qla4_82xx_idc_unlock(ha); 5210 ha->isp_ops->idc_unlock(ha);
5193 } 5211 }
5194 ret = -ENODEV; 5212 ret = -ENODEV;
5195 goto remove_host; 5213 goto remove_host;
@@ -6033,31 +6051,29 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
6033 "0x%x is the owner\n", ha->host_no, __func__, 6051 "0x%x is the owner\n", ha->host_no, __func__,
6034 ha->pdev->devfn); 6052 ha->pdev->devfn);
6035 6053
6036 qla4_82xx_idc_lock(ha); 6054 ha->isp_ops->idc_lock(ha);
6037 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6055 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
6038 QLA8XXX_DEV_COLD); 6056 QLA8XXX_DEV_COLD);
6039 6057 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
6040 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6058 QLA82XX_IDC_VERSION);
6041 QLA82XX_IDC_VERSION); 6059 ha->isp_ops->idc_unlock(ha);
6042
6043 qla4_82xx_idc_unlock(ha);
6044 clear_bit(AF_FW_RECOVERY, &ha->flags); 6060 clear_bit(AF_FW_RECOVERY, &ha->flags);
6045 rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER); 6061 rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
6046 qla4_82xx_idc_lock(ha); 6062 ha->isp_ops->idc_lock(ha);
6047 6063
6048 if (rval != QLA_SUCCESS) { 6064 if (rval != QLA_SUCCESS) {
6049 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: " 6065 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
6050 "FAILED\n", ha->host_no, __func__); 6066 "FAILED\n", ha->host_no, __func__);
6051 qla4_8xxx_clear_drv_active(ha); 6067 qla4_8xxx_clear_drv_active(ha);
6052 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6068 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
6053 QLA8XXX_DEV_FAILED); 6069 QLA8XXX_DEV_FAILED);
6054 } else { 6070 } else {
6055 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: " 6071 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
6056 "READY\n", ha->host_no, __func__); 6072 "READY\n", ha->host_no, __func__);
6057 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6073 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
6058 QLA8XXX_DEV_READY); 6074 QLA8XXX_DEV_READY);
6059 /* Clear driver state register */ 6075 /* Clear driver state register */
6060 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6076 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, 0);
6061 qla4_8xxx_set_drv_active(ha); 6077 qla4_8xxx_set_drv_active(ha);
6062 ret = qla4xxx_request_irqs(ha); 6078 ret = qla4xxx_request_irqs(ha);
6063 if (ret) { 6079 if (ret) {
@@ -6070,13 +6086,13 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
6070 rval = QLA_SUCCESS; 6086 rval = QLA_SUCCESS;
6071 } 6087 }
6072 } 6088 }
6073 qla4_82xx_idc_unlock(ha); 6089 ha->isp_ops->idc_unlock(ha);
6074 } else { 6090 } else {
6075 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: devfn 0x%x is not " 6091 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: devfn 0x%x is not "
6076 "the reset owner\n", ha->host_no, __func__, 6092 "the reset owner\n", ha->host_no, __func__,
6077 ha->pdev->devfn); 6093 ha->pdev->devfn);
6078 if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6094 if ((qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE) ==
6079 QLA8XXX_DEV_READY)) { 6095 QLA8XXX_DEV_READY)) {
6080 clear_bit(AF_FW_RECOVERY, &ha->flags); 6096 clear_bit(AF_FW_RECOVERY, &ha->flags);
6081 rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER); 6097 rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
6082 if (rval == QLA_SUCCESS) { 6098 if (rval == QLA_SUCCESS) {
@@ -6091,9 +6107,9 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
6091 rval = QLA_SUCCESS; 6107 rval = QLA_SUCCESS;
6092 } 6108 }
6093 } 6109 }
6094 qla4_82xx_idc_lock(ha); 6110 ha->isp_ops->idc_lock(ha);
6095 qla4_8xxx_set_drv_active(ha); 6111 qla4_8xxx_set_drv_active(ha);
6096 qla4_82xx_idc_unlock(ha); 6112 ha->isp_ops->idc_unlock(ha);
6097 } 6113 }
6098 } 6114 }
6099 clear_bit(DPC_RESET_ACTIVE, &ha->dpc_flags); 6115 clear_bit(DPC_RESET_ACTIVE, &ha->dpc_flags);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 07:58:30 -0500