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-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c53
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c11
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c13
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h105
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c154
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c30
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c9
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c304
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h42
-rw-r--r--drivers/gpu/drm/i915/i915_ums.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1250
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c52
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h46
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c21
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c4
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c23
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c4
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c4
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c162
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c33
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h7
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c83
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c8
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c3
-rw-r--r--include/drm/i915_powerwell.h36
-rw-r--r--sound/pci/hda/Kconfig10
-rw-r--r--sound/pci/hda/Makefile2
-rw-r--r--sound/pci/hda/hda_i915.c75
-rw-r--r--sound/pci/hda/hda_i915.h35
-rw-r--r--sound/pci/hda/hda_intel.c87
33 files changed, 1799 insertions, 881 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 76255a69752a..d4e78b64ca87 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -196,6 +196,32 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
196 } \ 196 } \
197} while (0) 197} while (0)
198 198
199struct file_stats {
200 int count;
201 size_t total, active, inactive, unbound;
202};
203
204static int per_file_stats(int id, void *ptr, void *data)
205{
206 struct drm_i915_gem_object *obj = ptr;
207 struct file_stats *stats = data;
208
209 stats->count++;
210 stats->total += obj->base.size;
211
212 if (obj->gtt_space) {
213 if (!list_empty(&obj->ring_list))
214 stats->active += obj->base.size;
215 else
216 stats->inactive += obj->base.size;
217 } else {
218 if (!list_empty(&obj->global_list))
219 stats->unbound += obj->base.size;
220 }
221
222 return 0;
223}
224
199static int i915_gem_object_info(struct seq_file *m, void* data) 225static int i915_gem_object_info(struct seq_file *m, void* data)
200{ 226{
201 struct drm_info_node *node = (struct drm_info_node *) m->private; 227 struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -204,6 +230,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
204 u32 count, mappable_count, purgeable_count; 230 u32 count, mappable_count, purgeable_count;
205 size_t size, mappable_size, purgeable_size; 231 size_t size, mappable_size, purgeable_size;
206 struct drm_i915_gem_object *obj; 232 struct drm_i915_gem_object *obj;
233 struct drm_file *file;
207 int ret; 234 int ret;
208 235
209 ret = mutex_lock_interruptible(&dev->struct_mutex); 236 ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -215,7 +242,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
215 dev_priv->mm.object_memory); 242 dev_priv->mm.object_memory);
216 243
217 size = count = mappable_size = mappable_count = 0; 244 size = count = mappable_size = mappable_count = 0;
218 count_objects(&dev_priv->mm.bound_list, gtt_list); 245 count_objects(&dev_priv->mm.bound_list, global_list);
219 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", 246 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
220 count, mappable_count, size, mappable_size); 247 count, mappable_count, size, mappable_size);
221 248
@@ -230,7 +257,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
230 count, mappable_count, size, mappable_size); 257 count, mappable_count, size, mappable_size);
231 258
232 size = count = purgeable_size = purgeable_count = 0; 259 size = count = purgeable_size = purgeable_count = 0;
233 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) { 260 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
234 size += obj->base.size, ++count; 261 size += obj->base.size, ++count;
235 if (obj->madv == I915_MADV_DONTNEED) 262 if (obj->madv == I915_MADV_DONTNEED)
236 purgeable_size += obj->base.size, ++purgeable_count; 263 purgeable_size += obj->base.size, ++purgeable_count;
@@ -238,7 +265,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
238 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); 265 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
239 266
240 size = count = mappable_size = mappable_count = 0; 267 size = count = mappable_size = mappable_count = 0;
241 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 268 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
242 if (obj->fault_mappable) { 269 if (obj->fault_mappable) {
243 size += obj->gtt_space->size; 270 size += obj->gtt_space->size;
244 ++count; 271 ++count;
@@ -263,6 +290,21 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
263 dev_priv->gtt.total, 290 dev_priv->gtt.total,
264 dev_priv->gtt.mappable_end - dev_priv->gtt.start); 291 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
265 292
293 seq_printf(m, "\n");
294 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
295 struct file_stats stats;
296
297 memset(&stats, 0, sizeof(stats));
298 idr_for_each(&file->object_idr, per_file_stats, &stats);
299 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
300 get_pid_task(file->pid, PIDTYPE_PID)->comm,
301 stats.count,
302 stats.total,
303 stats.active,
304 stats.inactive,
305 stats.unbound);
306 }
307
266 mutex_unlock(&dev->struct_mutex); 308 mutex_unlock(&dev->struct_mutex);
267 309
268 return 0; 310 return 0;
@@ -283,7 +325,7 @@ static int i915_gem_gtt_info(struct seq_file *m, void* data)
283 return ret; 325 return ret;
284 326
285 total_obj_size = total_gtt_size = count = 0; 327 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 328 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
287 if (list == PINNED_LIST && obj->pin_count == 0) 329 if (list == PINNED_LIST && obj->pin_count == 0)
288 continue; 330 continue;
289 331
@@ -1944,7 +1986,8 @@ i915_drop_caches_set(void *data, u64 val)
1944 } 1986 }
1945 1987
1946 if (val & DROP_UNBOUND) { 1988 if (val & DROP_UNBOUND) {
1947 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) 1989 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1990 global_list)
1948 if (obj->pages_pin_count == 0) { 1991 if (obj->pages_pin_count == 0) {
1949 ret = i915_gem_object_put_pages(obj); 1992 ret = i915_gem_object_put_pages(obj);
1950 if (ret) 1993 if (ret)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c52d866dfdb0..adb319b53ecd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1001,8 +1001,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
1001 value = 1; 1001 value = 1;
1002 break; 1002 break;
1003 default: 1003 default:
1004 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 1004 DRM_DEBUG("Unknown parameter %d\n", param->param);
1005 param->param);
1006 return -EINVAL; 1005 return -EINVAL;
1007 } 1006 }
1008 1007
@@ -1633,6 +1632,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1633 /* Start out suspended */ 1632 /* Start out suspended */
1634 dev_priv->mm.suspended = 1; 1633 dev_priv->mm.suspended = 1;
1635 1634
1635 if (HAS_POWER_WELL(dev))
1636 i915_init_power_well(dev);
1637
1636 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1638 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1637 ret = i915_load_modeset_init(dev); 1639 ret = i915_load_modeset_init(dev);
1638 if (ret < 0) { 1640 if (ret < 0) {
@@ -1684,6 +1686,9 @@ int i915_driver_unload(struct drm_device *dev)
1684 1686
1685 intel_gpu_ips_teardown(); 1687 intel_gpu_ips_teardown();
1686 1688
1689 if (HAS_POWER_WELL(dev))
1690 i915_remove_power_well(dev);
1691
1687 i915_teardown_sysfs(dev); 1692 i915_teardown_sysfs(dev);
1688 1693
1689 if (dev_priv->mm.inactive_shrinker.shrink) 1694 if (dev_priv->mm.inactive_shrinker.shrink)
@@ -1775,7 +1780,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1775 struct drm_i915_file_private *file_priv; 1780 struct drm_i915_file_private *file_priv;
1776 1781
1777 DRM_DEBUG_DRIVER("\n"); 1782 DRM_DEBUG_DRIVER("\n");
1778 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); 1783 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1779 if (!file_priv) 1784 if (!file_priv)
1780 return -ENOMEM; 1785 return -ENOMEM;
1781 1786
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59ff7456bd70..deaa32e8113b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -457,7 +457,6 @@ void intel_detect_pch(struct drm_device *dev)
457 */ 457 */
458 if (INTEL_INFO(dev)->num_pipes == 0) { 458 if (INTEL_INFO(dev)->num_pipes == 0) {
459 dev_priv->pch_type = PCH_NOP; 459 dev_priv->pch_type = PCH_NOP;
460 dev_priv->num_pch_pll = 0;
461 return; 460 return;
462 } 461 }
463 462
@@ -476,34 +475,28 @@ void intel_detect_pch(struct drm_device *dev)
476 475
477 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 476 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
478 dev_priv->pch_type = PCH_IBX; 477 dev_priv->pch_type = PCH_IBX;
479 dev_priv->num_pch_pll = 2;
480 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 478 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
481 WARN_ON(!IS_GEN5(dev)); 479 WARN_ON(!IS_GEN5(dev));
482 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 480 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_CPT; 481 dev_priv->pch_type = PCH_CPT;
484 dev_priv->num_pch_pll = 2;
485 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 482 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
486 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 483 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
487 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 484 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
488 /* PantherPoint is CPT compatible */ 485 /* PantherPoint is CPT compatible */
489 dev_priv->pch_type = PCH_CPT; 486 dev_priv->pch_type = PCH_CPT;
490 dev_priv->num_pch_pll = 2;
491 DRM_DEBUG_KMS("Found PatherPoint PCH\n"); 487 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
492 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 488 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
493 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 489 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
494 dev_priv->pch_type = PCH_LPT; 490 dev_priv->pch_type = PCH_LPT;
495 dev_priv->num_pch_pll = 0;
496 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 491 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
497 WARN_ON(!IS_HASWELL(dev)); 492 WARN_ON(!IS_HASWELL(dev));
498 WARN_ON(IS_ULT(dev)); 493 WARN_ON(IS_ULT(dev));
499 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 494 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
500 dev_priv->pch_type = PCH_LPT; 495 dev_priv->pch_type = PCH_LPT;
501 dev_priv->num_pch_pll = 0;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 496 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
503 WARN_ON(!IS_HASWELL(dev)); 497 WARN_ON(!IS_HASWELL(dev));
504 WARN_ON(!IS_ULT(dev)); 498 WARN_ON(!IS_ULT(dev));
505 } 499 }
506 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
507 } 500 }
508 pci_dev_put(pch); 501 pci_dev_put(pch);
509 } 502 }
@@ -570,7 +563,7 @@ static int i915_drm_freeze(struct drm_device *dev)
570 intel_opregion_fini(dev); 563 intel_opregion_fini(dev);
571 564
572 console_lock(); 565 console_lock();
573 intel_fbdev_set_suspend(dev, 1); 566 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
574 console_unlock(); 567 console_unlock();
575 568
576 return 0; 569 return 0;
@@ -614,7 +607,7 @@ void intel_console_resume(struct work_struct *work)
614 struct drm_device *dev = dev_priv->dev; 607 struct drm_device *dev = dev_priv->dev;
615 608
616 console_lock(); 609 console_lock();
617 intel_fbdev_set_suspend(dev, 0); 610 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
618 console_unlock(); 611 console_unlock();
619} 612}
620 613
@@ -683,7 +676,7 @@ static int __i915_drm_thaw(struct drm_device *dev)
683 * path of resume if possible. 676 * path of resume if possible.
684 */ 677 */
685 if (console_trylock()) { 678 if (console_trylock()) {
686 intel_fbdev_set_suspend(dev, 0); 679 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
687 console_unlock(); 680 console_unlock();
688 } else { 681 } else {
689 schedule_work(&dev_priv->console_resume_work); 682 schedule_work(&dev_priv->console_resume_work);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 359a2003086b..9e1bf6dcbb2a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,15 +132,38 @@ enum hpd_pin {
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc)) 133 if ((intel_encoder)->base.crtc == (__crtc))
134 134
135struct intel_pch_pll { 135struct drm_i915_private;
136
137enum intel_dpll_id {
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
140 DPLL_ID_PCH_PLL_A,
141 DPLL_ID_PCH_PLL_B,
142};
143#define I915_NUM_PLLS 2
144
145struct intel_dpll_hw_state {
146 uint32_t dpll;
147 uint32_t fp0;
148 uint32_t fp1;
149};
150
151struct intel_shared_dpll {
136 int refcount; /* count of number of CRTCs sharing this PLL */ 152 int refcount; /* count of number of CRTCs sharing this PLL */
137 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 153 int active; /* count of number of active CRTCs (i.e. DPMS on) */
138 bool on; /* is the PLL actually active? Disabled during modeset */ 154 bool on; /* is the PLL actually active? Disabled during modeset */
139 int pll_reg; 155 const char *name;
140 int fp0_reg; 156 /* should match the index in the dev_priv->shared_dplls array */
141 int fp1_reg; 157 enum intel_dpll_id id;
158 struct intel_dpll_hw_state hw_state;
159 void (*enable)(struct drm_i915_private *dev_priv,
160 struct intel_shared_dpll *pll);
161 void (*disable)(struct drm_i915_private *dev_priv,
162 struct intel_shared_dpll *pll);
163 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
164 struct intel_shared_dpll *pll,
165 struct intel_dpll_hw_state *hw_state);
142}; 166};
143#define I915_NUM_PLLS 2
144 167
145/* Used by dp and fdi links */ 168/* Used by dp and fdi links */
146struct intel_link_m_n { 169struct intel_link_m_n {
@@ -195,7 +218,6 @@ struct opregion_header;
195struct opregion_acpi; 218struct opregion_acpi;
196struct opregion_swsci; 219struct opregion_swsci;
197struct opregion_asle; 220struct opregion_asle;
198struct drm_i915_private;
199 221
200struct intel_opregion { 222struct intel_opregion {
201 struct opregion_header __iomem *header; 223 struct opregion_header __iomem *header;
@@ -306,6 +328,8 @@ struct drm_i915_error_state {
306 328
307struct intel_crtc_config; 329struct intel_crtc_config;
308struct intel_crtc; 330struct intel_crtc;
331struct intel_limit;
332struct dpll;
309 333
310struct drm_i915_display_funcs { 334struct drm_i915_display_funcs {
311 bool (*fbc_enabled)(struct drm_device *dev); 335 bool (*fbc_enabled)(struct drm_device *dev);
@@ -313,6 +337,24 @@ struct drm_i915_display_funcs {
313 void (*disable_fbc)(struct drm_device *dev); 337 void (*disable_fbc)(struct drm_device *dev);
314 int (*get_display_clock_speed)(struct drm_device *dev); 338 int (*get_display_clock_speed)(struct drm_device *dev);
315 int (*get_fifo_size)(struct drm_device *dev, int plane); 339 int (*get_fifo_size)(struct drm_device *dev, int plane);
340 /**
341 * find_dpll() - Find the best values for the PLL
342 * @limit: limits for the PLL
343 * @crtc: current CRTC
344 * @target: target frequency in kHz
345 * @refclk: reference clock frequency in kHz
346 * @match_clock: if provided, @best_clock P divider must
347 * match the P divider from @match_clock
348 * used for LVDS downclocking
349 * @best_clock: best PLL values found
350 *
351 * Returns true on success, false on failure.
352 */
353 bool (*find_dpll)(const struct intel_limit *limit,
354 struct drm_crtc *crtc,
355 int target, int refclk,
356 struct dpll *match_clock,
357 struct dpll *best_clock);
316 void (*update_wm)(struct drm_device *dev); 358 void (*update_wm)(struct drm_device *dev);
317 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 359 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
318 uint32_t sprite_width, int pixel_size, 360 uint32_t sprite_width, int pixel_size,
@@ -466,6 +508,13 @@ struct i915_hw_ppgtt {
466 void (*cleanup)(struct i915_hw_ppgtt *ppgtt); 508 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
467}; 509};
468 510
511struct i915_ctx_hang_stats {
512 /* This context had batch pending when hang was declared */
513 unsigned batch_pending;
514
515 /* This context had batch active when hang was declared */
516 unsigned batch_active;
517};
469 518
470/* This must match up with the value previously used for execbuf2.rsvd1. */ 519/* This must match up with the value previously used for execbuf2.rsvd1. */
471#define DEFAULT_CONTEXT_ID 0 520#define DEFAULT_CONTEXT_ID 0
@@ -476,6 +525,7 @@ struct i915_hw_context {
476 struct drm_i915_file_private *file_priv; 525 struct drm_i915_file_private *file_priv;
477 struct intel_ring_buffer *ring; 526 struct intel_ring_buffer *ring;
478 struct drm_i915_gem_object *obj; 527 struct drm_i915_gem_object *obj;
528 struct i915_ctx_hang_stats hang_stats;
479}; 529};
480 530
481enum no_fbc_reason { 531enum no_fbc_reason {
@@ -720,6 +770,15 @@ struct intel_ilk_power_mgmt {
720 struct drm_i915_gem_object *renderctx; 770 struct drm_i915_gem_object *renderctx;
721}; 771};
722 772
773/* Power well structure for haswell */
774struct i915_power_well {
775 struct drm_device *device;
776 spinlock_t lock;
777 /* power well enable/disable usage count */
778 int count;
779 int i915_request;
780};
781
723struct i915_dri1_state { 782struct i915_dri1_state {
724 unsigned allow_batchbuffer : 1; 783 unsigned allow_batchbuffer : 1;
725 u32 __iomem *gfx_hws_cpu_addr; 784 u32 __iomem *gfx_hws_cpu_addr;
@@ -842,7 +901,6 @@ struct i915_gpu_error {
842#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 901#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
843#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 902#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
844 struct timer_list hangcheck_timer; 903 struct timer_list hangcheck_timer;
845 int hangcheck_count;
846 904
847 /* For reset and error_state handling. */ 905 /* For reset and error_state handling. */
848 spinlock_t lock; 906 spinlock_t lock;
@@ -998,7 +1056,6 @@ typedef struct drm_i915_private {
998 u32 hpd_event_bits; 1056 u32 hpd_event_bits;
999 struct timer_list hotplug_reenable_timer; 1057 struct timer_list hotplug_reenable_timer;
1000 1058
1001 int num_pch_pll;
1002 int num_plane; 1059 int num_plane;
1003 1060
1004 unsigned long cfb_size; 1061 unsigned long cfb_size;
@@ -1059,7 +1116,8 @@ typedef struct drm_i915_private {
1059 struct drm_crtc *pipe_to_crtc_mapping[3]; 1116 struct drm_crtc *pipe_to_crtc_mapping[3];
1060 wait_queue_head_t pending_flip_queue; 1117 wait_queue_head_t pending_flip_queue;
1061 1118
1062 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 1119 int num_shared_dpll;
1120 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1063 struct intel_ddi_plls ddi_plls; 1121 struct intel_ddi_plls ddi_plls;
1064 1122
1065 /* Reclocking support */ 1123 /* Reclocking support */
@@ -1080,6 +1138,9 @@ typedef struct drm_i915_private {
1080 * mchdev_lock in intel_pm.c */ 1138 * mchdev_lock in intel_pm.c */
1081 struct intel_ilk_power_mgmt ips; 1139 struct intel_ilk_power_mgmt ips;
1082 1140
1141 /* Haswell power well */
1142 struct i915_power_well power_well;
1143
1083 enum no_fbc_reason no_fbc_reason; 1144 enum no_fbc_reason no_fbc_reason;
1084 1145
1085 struct drm_mm_node *compressed_fb; 1146 struct drm_mm_node *compressed_fb;
@@ -1154,7 +1215,7 @@ struct drm_i915_gem_object {
1154 struct drm_mm_node *gtt_space; 1215 struct drm_mm_node *gtt_space;
1155 /** Stolen memory for this object, instead of being backed by shmem. */ 1216 /** Stolen memory for this object, instead of being backed by shmem. */
1156 struct drm_mm_node *stolen; 1217 struct drm_mm_node *stolen;
1157 struct list_head gtt_list; 1218 struct list_head global_list;
1158 1219
1159 /** This object's place on the active/inactive lists */ 1220 /** This object's place on the active/inactive lists */
1160 struct list_head ring_list; 1221 struct list_head ring_list;
@@ -1301,12 +1362,18 @@ struct drm_i915_gem_request {
1301 /** GEM sequence number associated with this request. */ 1362 /** GEM sequence number associated with this request. */
1302 uint32_t seqno; 1363 uint32_t seqno;
1303 1364
1304 /** Postion in the ringbuffer of the end of the request */ 1365 /** Position in the ringbuffer of the start of the request */
1366 u32 head;
1367
1368 /** Position in the ringbuffer of the end of the request */
1305 u32 tail; 1369 u32 tail;
1306 1370
1307 /** Context related to this request */ 1371 /** Context related to this request */
1308 struct i915_hw_context *ctx; 1372 struct i915_hw_context *ctx;
1309 1373
1374 /** Batch buffer related to this request if any */
1375 struct drm_i915_gem_object *batch_obj;
1376
1310 /** Time at which this request was emitted, in jiffies. */ 1377 /** Time at which this request was emitted, in jiffies. */
1311 unsigned long emitted_jiffies; 1378 unsigned long emitted_jiffies;
1312 1379
@@ -1324,6 +1391,8 @@ struct drm_i915_file_private {
1324 struct list_head request_list; 1391 struct list_head request_list;
1325 } mm; 1392 } mm;
1326 struct idr context_idr; 1393 struct idr context_idr;
1394
1395 struct i915_ctx_hang_stats hang_stats;
1327}; 1396};
1328 1397
1329#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1398#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
@@ -1660,6 +1729,7 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1660{ 1729{
1661 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1730 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1662 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1731 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1732 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1663 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1733 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1664 } 1734 }
1665} 1735}
@@ -1692,9 +1762,12 @@ void i915_gem_init_swizzling(struct drm_device *dev);
1692void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1762void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1693int __must_check i915_gpu_idle(struct drm_device *dev); 1763int __must_check i915_gpu_idle(struct drm_device *dev);
1694int __must_check i915_gem_idle(struct drm_device *dev); 1764int __must_check i915_gem_idle(struct drm_device *dev);
1695int i915_add_request(struct intel_ring_buffer *ring, 1765int __i915_add_request(struct intel_ring_buffer *ring,
1696 struct drm_file *file, 1766 struct drm_file *file,
1697 u32 *seqno); 1767 struct drm_i915_gem_object *batch_obj,
1768 u32 *seqno);
1769#define i915_add_request(ring, seqno) \
1770 __i915_add_request(ring, NULL, NULL, seqno)
1698int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1771int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1699 uint32_t seqno); 1772 uint32_t seqno);
1700int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1773int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
@@ -1748,6 +1821,10 @@ static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1748 kref_put(&ctx->ref, i915_gem_context_free); 1821 kref_put(&ctx->ref, i915_gem_context_free);
1749} 1822}
1750 1823
1824struct i915_ctx_hang_stats * __must_check
1825i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
1826 struct drm_file *file,
1827 u32 id);
1751int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1828int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1752 struct drm_file *file); 1829 struct drm_file *file);
1753int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1830int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5b6a92e7102..a6178baccb56 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -176,7 +176,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
176 176
177 pinned = 0; 177 pinned = 0;
178 mutex_lock(&dev->struct_mutex); 178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 179 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
180 if (obj->pin_count) 180 if (obj->pin_count)
181 pinned += obj->gtt_space->size; 181 pinned += obj->gtt_space->size;
182 mutex_unlock(&dev->struct_mutex); 182 mutex_unlock(&dev->struct_mutex);
@@ -956,7 +956,7 @@ i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
956 956
957 ret = 0; 957 ret = 0;
958 if (seqno == ring->outstanding_lazy_request) 958 if (seqno == ring->outstanding_lazy_request)
959 ret = i915_add_request(ring, NULL, NULL); 959 ret = i915_add_request(ring, NULL);
960 960
961 return ret; 961 return ret;
962} 962}
@@ -1676,7 +1676,7 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle 1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt 1677 * array, hence protect them from being reaped by removing them from gtt
1678 * lists early. */ 1678 * lists early. */
1679 list_del(&obj->gtt_list); 1679 list_del(&obj->global_list);
1680 1680
1681 ops->put_pages(obj); 1681 ops->put_pages(obj);
1682 obj->pages = NULL; 1682 obj->pages = NULL;
@@ -1696,7 +1696,7 @@ __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1696 1696
1697 list_for_each_entry_safe(obj, next, 1697 list_for_each_entry_safe(obj, next,
1698 &dev_priv->mm.unbound_list, 1698 &dev_priv->mm.unbound_list,
1699 gtt_list) { 1699 global_list) {
1700 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && 1700 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1701 i915_gem_object_put_pages(obj) == 0) { 1701 i915_gem_object_put_pages(obj) == 0) {
1702 count += obj->base.size >> PAGE_SHIFT; 1702 count += obj->base.size >> PAGE_SHIFT;
@@ -1733,7 +1733,8 @@ i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1733 1733
1734 i915_gem_evict_everything(dev_priv->dev); 1734 i915_gem_evict_everything(dev_priv->dev);
1735 1735
1736 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) 1736 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1737 global_list)
1737 i915_gem_object_put_pages(obj); 1738 i915_gem_object_put_pages(obj);
1738} 1739}
1739 1740
@@ -1858,7 +1859,7 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1858 if (ret) 1859 if (ret)
1859 return ret; 1860 return ret;
1860 1861
1861 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); 1862 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1862 return 0; 1863 return 0;
1863} 1864}
1864 1865
@@ -1996,17 +1997,18 @@ i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1996 return 0; 1997 return 0;
1997} 1998}
1998 1999
1999int 2000int __i915_add_request(struct intel_ring_buffer *ring,
2000i915_add_request(struct intel_ring_buffer *ring, 2001 struct drm_file *file,
2001 struct drm_file *file, 2002 struct drm_i915_gem_object *obj,
2002 u32 *out_seqno) 2003 u32 *out_seqno)
2003{ 2004{
2004 drm_i915_private_t *dev_priv = ring->dev->dev_private; 2005 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2005 struct drm_i915_gem_request *request; 2006 struct drm_i915_gem_request *request;
2006 u32 request_ring_position; 2007 u32 request_ring_position, request_start;
2007 int was_empty; 2008 int was_empty;
2008 int ret; 2009 int ret;
2009 2010
2011 request_start = intel_ring_get_tail(ring);
2010 /* 2012 /*
2011 * Emit any outstanding flushes - execbuf can fail to emit the flush 2013 * Emit any outstanding flushes - execbuf can fail to emit the flush
2012 * after having emitted the batchbuffer command. Hence we need to fix 2014 * after having emitted the batchbuffer command. Hence we need to fix
@@ -2038,8 +2040,17 @@ i915_add_request(struct intel_ring_buffer *ring,
2038 2040
2039 request->seqno = intel_ring_get_seqno(ring); 2041 request->seqno = intel_ring_get_seqno(ring);
2040 request->ring = ring; 2042 request->ring = ring;
2043 request->head = request_start;
2041 request->tail = request_ring_position; 2044 request->tail = request_ring_position;
2042 request->ctx = ring->last_context; 2045 request->ctx = ring->last_context;
2046 request->batch_obj = obj;
2047
2048 /* Whilst this request exists, batch_obj will be on the
2049 * active_list, and so will hold the active reference. Only when this
2050 * request is retired will the the batch_obj be moved onto the
2051 * inactive_list and lose its active reference. Hence we do not need
2052 * to explicitly hold another reference here.
2053 */
2043 2054
2044 if (request->ctx) 2055 if (request->ctx)
2045 i915_gem_context_reference(request->ctx); 2056 i915_gem_context_reference(request->ctx);
@@ -2096,6 +2107,94 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2096 spin_unlock(&file_priv->mm.lock); 2107 spin_unlock(&file_priv->mm.lock);
2097} 2108}
2098 2109
2110static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2111{
2112 if (acthd >= obj->gtt_offset &&
2113 acthd < obj->gtt_offset + obj->base.size)
2114 return true;
2115
2116 return false;
2117}
2118
2119static bool i915_head_inside_request(const u32 acthd_unmasked,
2120 const u32 request_start,
2121 const u32 request_end)
2122{
2123 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2124
2125 if (request_start < request_end) {
2126 if (acthd >= request_start && acthd < request_end)
2127 return true;
2128 } else if (request_start > request_end) {
2129 if (acthd >= request_start || acthd < request_end)
2130 return true;
2131 }
2132
2133 return false;
2134}
2135
2136static bool i915_request_guilty(struct drm_i915_gem_request *request,
2137 const u32 acthd, bool *inside)
2138{
2139 /* There is a possibility that unmasked head address
2140 * pointing inside the ring, matches the batch_obj address range.
2141 * However this is extremely unlikely.
2142 */
2143
2144 if (request->batch_obj) {
2145 if (i915_head_inside_object(acthd, request->batch_obj)) {
2146 *inside = true;
2147 return true;
2148 }
2149 }
2150
2151 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2152 *inside = false;
2153 return true;
2154 }
2155
2156 return false;
2157}
2158
2159static void i915_set_reset_status(struct intel_ring_buffer *ring,
2160 struct drm_i915_gem_request *request,
2161 u32 acthd)
2162{
2163 struct i915_ctx_hang_stats *hs = NULL;
2164 bool inside, guilty;
2165
2166 /* Innocent until proven guilty */
2167 guilty = false;
2168
2169 if (ring->hangcheck.action != wait &&
2170 i915_request_guilty(request, acthd, &inside)) {
2171 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2172 ring->name,
2173 inside ? "inside" : "flushing",
2174 request->batch_obj ?
2175 request->batch_obj->gtt_offset : 0,
2176 request->ctx ? request->ctx->id : 0,
2177 acthd);
2178
2179 guilty = true;
2180 }
2181
2182 /* If contexts are disabled or this is the default context, use
2183 * file_priv->reset_state
2184 */
2185 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2186 hs = &request->ctx->hang_stats;
2187 else if (request->file_priv)
2188 hs = &request->file_priv->hang_stats;
2189
2190 if (hs) {
2191 if (guilty)
2192 hs->batch_active++;
2193 else
2194 hs->batch_pending++;
2195 }
2196}
2197
2099static void i915_gem_free_request(struct drm_i915_gem_request *request) 2198static void i915_gem_free_request(struct drm_i915_gem_request *request)
2100{ 2199{
2101 list_del(&request->list); 2200 list_del(&request->list);
@@ -2110,6 +2209,12 @@ static void i915_gem_free_request(struct drm_i915_gem_request *request)
2110static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, 2209static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2111 struct intel_ring_buffer *ring) 2210 struct intel_ring_buffer *ring)
2112{ 2211{
2212 u32 completed_seqno;
2213 u32 acthd;
2214
2215 acthd = intel_ring_get_active_head(ring);
2216 completed_seqno = ring->get_seqno(ring, false);
2217
2113 while (!list_empty(&ring->request_list)) { 2218 while (!list_empty(&ring->request_list)) {
2114 struct drm_i915_gem_request *request; 2219 struct drm_i915_gem_request *request;
2115 2220
@@ -2117,6 +2222,9 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2117 struct drm_i915_gem_request, 2222 struct drm_i915_gem_request,
2118 list); 2223 list);
2119 2224
2225 if (request->seqno > completed_seqno)
2226 i915_set_reset_status(ring, request, acthd);
2227
2120 i915_gem_free_request(request); 2228 i915_gem_free_request(request);
2121 } 2229 }
2122 2230
@@ -2276,7 +2384,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
2276 idle = true; 2384 idle = true;
2277 for_each_ring(ring, dev_priv, i) { 2385 for_each_ring(ring, dev_priv, i) {
2278 if (ring->gpu_caches_dirty) 2386 if (ring->gpu_caches_dirty)
2279 i915_add_request(ring, NULL, NULL); 2387 i915_add_request(ring, NULL);
2280 2388
2281 idle &= list_empty(&ring->request_list); 2389 idle &= list_empty(&ring->request_list);
2282 } 2390 }
@@ -2508,9 +2616,10 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2508 obj->has_aliasing_ppgtt_mapping = 0; 2616 obj->has_aliasing_ppgtt_mapping = 0;
2509 } 2617 }
2510 i915_gem_gtt_finish_object(obj); 2618 i915_gem_gtt_finish_object(obj);
2619 i915_gem_object_unpin_pages(obj);
2511 2620
2512 list_del(&obj->mm_list); 2621 list_del(&obj->mm_list);
2513 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); 2622 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2514 /* Avoid an unnecessary call to unbind on rebind. */ 2623 /* Avoid an unnecessary call to unbind on rebind. */
2515 obj->map_and_fenceable = true; 2624 obj->map_and_fenceable = true;
2516 2625
@@ -2918,7 +3027,7 @@ static void i915_gem_verify_gtt(struct drm_device *dev)
2918 struct drm_i915_gem_object *obj; 3027 struct drm_i915_gem_object *obj;
2919 int err = 0; 3028 int err = 0;
2920 3029
2921 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { 3030 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
2922 if (obj->gtt_space == NULL) { 3031 if (obj->gtt_space == NULL) {
2923 printk(KERN_ERR "object found on GTT list with no space reserved\n"); 3032 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2924 err++; 3033 err++;
@@ -3042,7 +3151,7 @@ search_free:
3042 return ret; 3151 return ret;
3043 } 3152 }
3044 3153
3045 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); 3154 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3046 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); 3155 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3047 3156
3048 obj->gtt_space = node; 3157 obj->gtt_space = node;
@@ -3057,7 +3166,6 @@ search_free:
3057 3166
3058 obj->map_and_fenceable = mappable && fenceable; 3167 obj->map_and_fenceable = mappable && fenceable;
3059 3168
3060 i915_gem_object_unpin_pages(obj);
3061 trace_i915_gem_object_bind(obj, map_and_fenceable); 3169 trace_i915_gem_object_bind(obj, map_and_fenceable);
3062 i915_gem_verify_gtt(dev); 3170 i915_gem_verify_gtt(dev);
3063 return 0; 3171 return 0;
@@ -3757,7 +3865,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
3757 const struct drm_i915_gem_object_ops *ops) 3865 const struct drm_i915_gem_object_ops *ops)
3758{ 3866{
3759 INIT_LIST_HEAD(&obj->mm_list); 3867 INIT_LIST_HEAD(&obj->mm_list);
3760 INIT_LIST_HEAD(&obj->gtt_list); 3868 INIT_LIST_HEAD(&obj->global_list);
3761 INIT_LIST_HEAD(&obj->ring_list); 3869 INIT_LIST_HEAD(&obj->ring_list);
3762 INIT_LIST_HEAD(&obj->exec_list); 3870 INIT_LIST_HEAD(&obj->exec_list);
3763 3871
@@ -3857,7 +3965,13 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj)
3857 dev_priv->mm.interruptible = was_interruptible; 3965 dev_priv->mm.interruptible = was_interruptible;
3858 } 3966 }
3859 3967
3860 obj->pages_pin_count = 0; 3968 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3969 * before progressing. */
3970 if (obj->stolen)
3971 i915_gem_object_unpin_pages(obj);
3972
3973 if (WARN_ON(obj->pages_pin_count))
3974 obj->pages_pin_count = 0;
3861 i915_gem_object_put_pages(obj); 3975 i915_gem_object_put_pages(obj);
3862 i915_gem_object_free_mmap_offset(obj); 3976 i915_gem_object_free_mmap_offset(obj);
3863 i915_gem_object_release_stolen(obj); 3977 i915_gem_object_release_stolen(obj);
@@ -4498,10 +4612,10 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4498 } 4612 }
4499 4613
4500 cnt = 0; 4614 cnt = 0;
4501 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) 4615 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4502 if (obj->pages_pin_count == 0) 4616 if (obj->pages_pin_count == 0)
4503 cnt += obj->base.size >> PAGE_SHIFT; 4617 cnt += obj->base.size >> PAGE_SHIFT;
4504 list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list) 4618 list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list)
4505 if (obj->pin_count == 0 && obj->pages_pin_count == 0) 4619 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4506 cnt += obj->base.size >> PAGE_SHIFT; 4620 cnt += obj->base.size >> PAGE_SHIFT;
4507 4621
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 39bcc087db96..ff471454968d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -303,6 +303,34 @@ static int context_idr_cleanup(int id, void *p, void *data)
303 return 0; 303 return 0;
304} 304}
305 305
306struct i915_ctx_hang_stats *
307i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
308 struct drm_file *file,
309 u32 id)
310{
311 struct drm_i915_private *dev_priv = ring->dev->dev_private;
312 struct drm_i915_file_private *file_priv = file->driver_priv;
313 struct i915_hw_context *to;
314
315 if (dev_priv->hw_contexts_disabled)
316 return ERR_PTR(-ENOENT);
317
318 if (ring->id != RCS)
319 return ERR_PTR(-EINVAL);
320
321 if (file == NULL)
322 return ERR_PTR(-EINVAL);
323
324 if (id == DEFAULT_CONTEXT_ID)
325 return &file_priv->hang_stats;
326
327 to = i915_gem_context_get(file->driver_priv, id);
328 if (to == NULL)
329 return ERR_PTR(-ENOENT);
330
331 return &to->hang_stats;
332}
333
306void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) 334void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
307{ 335{
308 struct drm_i915_file_private *file_priv = file->driver_priv; 336 struct drm_i915_file_private *file_priv = file->driver_priv;
@@ -427,7 +455,7 @@ static int do_switch(struct i915_hw_context *to)
427 from->obj->dirty = 1; 455 from->obj->dirty = 1;
428 BUG_ON(from->obj->ring != ring); 456 BUG_ON(from->obj->ring != ring);
429 457
430 ret = i915_add_request(ring, NULL, NULL); 458 ret = i915_add_request(ring, NULL);
431 if (ret) { 459 if (ret) {
432 /* Too late, we've already scheduled a context switch. 460 /* Too late, we've already scheduled a context switch.
433 * Try to undo the change so that the hw state is 461 * Try to undo the change so that the hw state is
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a8bb62ca8756..87a3227e5179 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -786,7 +786,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
786 obj->dirty = 1; 786 obj->dirty = 1;
787 obj->last_write_seqno = intel_ring_get_seqno(ring); 787 obj->last_write_seqno = intel_ring_get_seqno(ring);
788 if (obj->pin_count) /* check for potential scanout */ 788 if (obj->pin_count) /* check for potential scanout */
789 intel_mark_fb_busy(obj); 789 intel_mark_fb_busy(obj, ring);
790 } 790 }
791 791
792 trace_i915_gem_object_change_domain(obj, old_read, old_write); 792 trace_i915_gem_object_change_domain(obj, old_read, old_write);
@@ -796,13 +796,14 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
796static void 796static void
797i915_gem_execbuffer_retire_commands(struct drm_device *dev, 797i915_gem_execbuffer_retire_commands(struct drm_device *dev,
798 struct drm_file *file, 798 struct drm_file *file,
799 struct intel_ring_buffer *ring) 799 struct intel_ring_buffer *ring,
800 struct drm_i915_gem_object *obj)
800{ 801{
801 /* Unconditionally force add_request to emit a full flush. */ 802 /* Unconditionally force add_request to emit a full flush. */
802 ring->gpu_caches_dirty = true; 803 ring->gpu_caches_dirty = true;
803 804
804 /* Add a breadcrumb for the completion of the batch buffer */ 805 /* Add a breadcrumb for the completion of the batch buffer */
805 (void)i915_add_request(ring, file, NULL); 806 (void)__i915_add_request(ring, file, obj, NULL);
806} 807}
807 808
808static int 809static int
@@ -1083,7 +1084,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1083 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); 1084 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1084 1085
1085 i915_gem_execbuffer_move_to_active(&eb->objects, ring); 1086 i915_gem_execbuffer_move_to_active(&eb->objects, ring);
1086 i915_gem_execbuffer_retire_commands(dev, file, ring); 1087 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1087 1088
1088err: 1089err:
1089 eb_destroy(eb); 1090 eb_destroy(eb);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ddad13fa3156..5101ab6869b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -439,7 +439,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
439 dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, 439 dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
440 dev_priv->gtt.total / PAGE_SIZE); 440 dev_priv->gtt.total / PAGE_SIZE);
441 441
442 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 442 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
443 i915_gem_clflush_object(obj); 443 i915_gem_clflush_object(obj);
444 i915_gem_gtt_bind_object(obj, obj->cache_level); 444 i915_gem_gtt_bind_object(obj, obj->cache_level);
445 } 445 }
@@ -631,7 +631,7 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
631 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; 631 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
632 632
633 /* Mark any preallocated objects as occupied */ 633 /* Mark any preallocated objects as occupied */
634 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 634 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
635 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", 635 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
636 obj->gtt_offset, obj->base.size); 636 obj->gtt_offset, obj->base.size);
637 637
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 89cbfab9570e..f713294618fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -279,7 +279,7 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
279 goto cleanup; 279 goto cleanup;
280 280
281 obj->has_dma_mapping = true; 281 obj->has_dma_mapping = true;
282 obj->pages_pin_count = 1; 282 i915_gem_object_pin_pages(obj);
283 obj->stolen = stolen; 283 obj->stolen = stolen;
284 284
285 obj->base.write_domain = I915_GEM_DOMAIN_GTT; 285 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
@@ -383,7 +383,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
383 obj->gtt_offset = gtt_offset; 383 obj->gtt_offset = gtt_offset;
384 obj->has_global_gtt_mapping = 1; 384 obj->has_global_gtt_mapping = 1;
385 385
386 list_add_tail(&obj->gtt_list, &dev_priv->mm.bound_list); 386 list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
387 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); 387 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
388 388
389 return obj; 389 return obj;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e17bbe201195..7857430943ec 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -683,7 +683,6 @@ static void notify_ring(struct drm_device *dev,
683 683
684 wake_up_all(&ring->irq_queue); 684 wake_up_all(&ring->irq_queue);
685 if (i915_enable_hangcheck) { 685 if (i915_enable_hangcheck) {
686 dev_priv->gpu_error.hangcheck_count = 0;
687 mod_timer(&dev_priv->gpu_error.hangcheck_timer, 686 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
688 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 687 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
689 } 688 }
@@ -1656,7 +1655,7 @@ static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1656 struct drm_i915_gem_object *obj; 1655 struct drm_i915_gem_object *obj;
1657 int i = 0; 1656 int i = 0;
1658 1657
1659 list_for_each_entry(obj, head, gtt_list) { 1658 list_for_each_entry(obj, head, global_list) {
1660 if (obj->pin_count == 0) 1659 if (obj->pin_count == 0)
1661 continue; 1660 continue;
1662 1661
@@ -1798,7 +1797,7 @@ static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1798 if (ring->id != RCS || !error->ccid) 1797 if (ring->id != RCS || !error->ccid)
1799 return; 1798 return;
1800 1799
1801 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { 1800 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1802 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) { 1801 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1803 ering->ctx = i915_error_object_create_sized(dev_priv, 1802 ering->ctx = i915_error_object_create_sized(dev_priv,
1804 obj, 1); 1803 obj, 1);
@@ -1935,7 +1934,7 @@ static void i915_capture_error_state(struct drm_device *dev)
1935 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 1934 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1936 i++; 1935 i++;
1937 error->active_bo_count = i; 1936 error->active_bo_count = i;
1938 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 1937 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1939 if (obj->pin_count) 1938 if (obj->pin_count)
1940 i++; 1939 i++;
1941 error->pinned_bo_count = i - error->active_bo_count; 1940 error->pinned_bo_count = i - error->active_bo_count;
@@ -2315,38 +2314,28 @@ ring_last_seqno(struct intel_ring_buffer *ring)
2315 struct drm_i915_gem_request, list)->seqno; 2314 struct drm_i915_gem_request, list)->seqno;
2316} 2315}
2317 2316
2318static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, 2317static bool
2319 u32 ring_seqno, bool *err) 2318ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2320{ 2319{
2321 if (list_empty(&ring->request_list) || 2320 return (list_empty(&ring->request_list) ||
2322 i915_seqno_passed(ring_seqno, ring_last_seqno(ring))) { 2321 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2323 /* Issue a wake-up to catch stuck h/w. */
2324 if (waitqueue_active(&ring->irq_queue)) {
2325 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2326 ring->name);
2327 wake_up_all(&ring->irq_queue);
2328 *err = true;
2329 }
2330 return true;
2331 }
2332 return false;
2333} 2322}
2334 2323
2335static bool semaphore_passed(struct intel_ring_buffer *ring) 2324static struct intel_ring_buffer *
2325semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2336{ 2326{
2337 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2327 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2338 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; 2328 u32 cmd, ipehr, acthd, acthd_min;
2339 struct intel_ring_buffer *signaller;
2340 u32 cmd, ipehr, acthd_min;
2341 2329
2342 ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 2330 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2343 if ((ipehr & ~(0x3 << 16)) != 2331 if ((ipehr & ~(0x3 << 16)) !=
2344 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) 2332 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2345 return false; 2333 return NULL;
2346 2334
2347 /* ACTHD is likely pointing to the dword after the actual command, 2335 /* ACTHD is likely pointing to the dword after the actual command,
2348 * so scan backwards until we find the MBOX. 2336 * so scan backwards until we find the MBOX.
2349 */ 2337 */
2338 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2350 acthd_min = max((int)acthd - 3 * 4, 0); 2339 acthd_min = max((int)acthd - 3 * 4, 0);
2351 do { 2340 do {
2352 cmd = ioread32(ring->virtual_start + acthd); 2341 cmd = ioread32(ring->virtual_start + acthd);
@@ -2355,128 +2344,216 @@ static bool semaphore_passed(struct intel_ring_buffer *ring)
2355 2344
2356 acthd -= 4; 2345 acthd -= 4;
2357 if (acthd < acthd_min) 2346 if (acthd < acthd_min)
2358 return false; 2347 return NULL;
2359 } while (1); 2348 } while (1);
2360 2349
2361 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; 2350 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2362 return i915_seqno_passed(signaller->get_seqno(signaller, false), 2351 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2363 ioread32(ring->virtual_start+acthd+4)+1);
2364} 2352}
2365 2353
2366static bool kick_ring(struct intel_ring_buffer *ring) 2354static int semaphore_passed(struct intel_ring_buffer *ring)
2367{ 2355{
2368 struct drm_device *dev = ring->dev; 2356 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2369 struct drm_i915_private *dev_priv = dev->dev_private; 2357 struct intel_ring_buffer *signaller;
2370 u32 tmp = I915_READ_CTL(ring); 2358 u32 seqno, ctl;
2371 if (tmp & RING_WAIT) {
2372 DRM_ERROR("Kicking stuck wait on %s\n",
2373 ring->name);
2374 I915_WRITE_CTL(ring, tmp);
2375 return true;
2376 }
2377 2359
2378 if (INTEL_INFO(dev)->gen >= 6 && 2360 ring->hangcheck.deadlock = true;
2379 tmp & RING_WAIT_SEMAPHORE && 2361
2380 semaphore_passed(ring)) { 2362 signaller = semaphore_waits_for(ring, &seqno);
2381 DRM_ERROR("Kicking stuck semaphore on %s\n", 2363 if (signaller == NULL || signaller->hangcheck.deadlock)
2382 ring->name); 2364 return -1;
2383 I915_WRITE_CTL(ring, tmp); 2365
2384 return true; 2366 /* cursory check for an unkickable deadlock */
2385 } 2367 ctl = I915_READ_CTL(signaller);
2386 return false; 2368 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2369 return -1;
2370
2371 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2387} 2372}
2388 2373
2389static bool i915_hangcheck_ring_hung(struct intel_ring_buffer *ring) 2374static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2390{ 2375{
2391 if (IS_GEN2(ring->dev)) 2376 struct intel_ring_buffer *ring;
2392 return false; 2377 int i;
2393 2378
2394 /* Is the chip hanging on a WAIT_FOR_EVENT? 2379 for_each_ring(ring, dev_priv, i)
2395 * If so we can simply poke the RB_WAIT bit 2380 ring->hangcheck.deadlock = false;
2396 * and break the hang. This should work on
2397 * all but the second generation chipsets.
2398 */
2399 return !kick_ring(ring);
2400} 2381}
2401 2382
2402static bool i915_hangcheck_hung(struct drm_device *dev) 2383static enum intel_ring_hangcheck_action
2384ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2403{ 2385{
2404 drm_i915_private_t *dev_priv = dev->dev_private; 2386 struct drm_device *dev = ring->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 u32 tmp;
2405 2389
2406 if (dev_priv->gpu_error.hangcheck_count++ > 1) { 2390 if (ring->hangcheck.acthd != acthd)
2407 bool hung = true; 2391 return active;
2408 struct intel_ring_buffer *ring;
2409 int i;
2410 2392
2411 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 2393 if (IS_GEN2(dev))
2412 i915_handle_error(dev, true); 2394 return hung;
2413 2395
2414 for_each_ring(ring, dev_priv, i) 2396 /* Is the chip hanging on a WAIT_FOR_EVENT?
2415 hung &= i915_hangcheck_ring_hung(ring); 2397 * If so we can simply poke the RB_WAIT bit
2398 * and break the hang. This should work on
2399 * all but the second generation chipsets.
2400 */
2401 tmp = I915_READ_CTL(ring);
2402 if (tmp & RING_WAIT) {
2403 DRM_ERROR("Kicking stuck wait on %s\n",
2404 ring->name);
2405 I915_WRITE_CTL(ring, tmp);
2406 return kick;
2407 }
2416 2408
2417 return hung; 2409 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2410 switch (semaphore_passed(ring)) {
2411 default:
2412 return hung;
2413 case 1:
2414 DRM_ERROR("Kicking stuck semaphore on %s\n",
2415 ring->name);
2416 I915_WRITE_CTL(ring, tmp);
2417 return kick;
2418 case 0:
2419 return wait;
2420 }
2418 } 2421 }
2419 2422
2420 return false; 2423 return hung;
2421} 2424}
2422 2425
2423/** 2426/**
2424 * This is called when the chip hasn't reported back with completed 2427 * This is called when the chip hasn't reported back with completed
2425 * batchbuffers in a long time. The first time this is called we simply record 2428 * batchbuffers in a long time. We keep track per ring seqno progress and
2426 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 2429 * if there are no progress, hangcheck score for that ring is increased.
2427 * again, we assume the chip is wedged and try to fix it. 2430 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2431 * we kick the ring. If we see no progress on three subsequent calls
2432 * we assume chip is wedged and try to fix it by resetting the chip.
2428 */ 2433 */
2429void i915_hangcheck_elapsed(unsigned long data) 2434void i915_hangcheck_elapsed(unsigned long data)
2430{ 2435{
2431 struct drm_device *dev = (struct drm_device *)data; 2436 struct drm_device *dev = (struct drm_device *)data;
2432 drm_i915_private_t *dev_priv = dev->dev_private; 2437 drm_i915_private_t *dev_priv = dev->dev_private;
2433 struct intel_ring_buffer *ring; 2438 struct intel_ring_buffer *ring;
2434 bool err = false, idle;
2435 int i; 2439 int i;
2436 u32 seqno[I915_NUM_RINGS]; 2440 int busy_count = 0, rings_hung = 0;
2437 bool work_done; 2441 bool stuck[I915_NUM_RINGS] = { 0 };
2442#define BUSY 1
2443#define KICK 5
2444#define HUNG 20
2445#define FIRE 30
2438 2446
2439 if (!i915_enable_hangcheck) 2447 if (!i915_enable_hangcheck)
2440 return; 2448 return;
2441 2449
2442 idle = true;
2443 for_each_ring(ring, dev_priv, i) { 2450 for_each_ring(ring, dev_priv, i) {
2444 seqno[i] = ring->get_seqno(ring, false); 2451 u32 seqno, acthd;
2445 idle &= i915_hangcheck_ring_idle(ring, seqno[i], &err); 2452 bool busy = true;
2446 } 2453
2447 2454 semaphore_clear_deadlocks(dev_priv);
2448 /* If all work is done then ACTHD clearly hasn't advanced. */ 2455
2449 if (idle) { 2456 seqno = ring->get_seqno(ring, false);
2450 if (err) { 2457 acthd = intel_ring_get_active_head(ring);
2451 if (i915_hangcheck_hung(dev)) 2458
2452 return; 2459 if (ring->hangcheck.seqno == seqno) {
2453 2460 if (ring_idle(ring, seqno)) {
2454 goto repeat; 2461 if (waitqueue_active(&ring->irq_queue)) {
2462 /* Issue a wake-up to catch stuck h/w. */
2463 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2464 ring->name);
2465 wake_up_all(&ring->irq_queue);
2466 ring->hangcheck.score += HUNG;
2467 } else
2468 busy = false;
2469 } else {
2470 int score;
2471
2472 /* We always increment the hangcheck score
2473 * if the ring is busy and still processing
2474 * the same request, so that no single request
2475 * can run indefinitely (such as a chain of
2476 * batches). The only time we do not increment
2477 * the hangcheck score on this ring, if this
2478 * ring is in a legitimate wait for another
2479 * ring. In that case the waiting ring is a
2480 * victim and we want to be sure we catch the
2481 * right culprit. Then every time we do kick
2482 * the ring, add a small increment to the
2483 * score so that we can catch a batch that is
2484 * being repeatedly kicked and so responsible
2485 * for stalling the machine.
2486 */
2487 ring->hangcheck.action = ring_stuck(ring,
2488 acthd);
2489
2490 switch (ring->hangcheck.action) {
2491 case wait:
2492 score = 0;
2493 break;
2494 case active:
2495 score = BUSY;
2496 break;
2497 case kick:
2498 score = KICK;
2499 break;
2500 case hung:
2501 score = HUNG;
2502 stuck[i] = true;
2503 break;
2504 }
2505 ring->hangcheck.score += score;
2506 }
2507 } else {
2508 /* Gradually reduce the count so that we catch DoS
2509 * attempts across multiple batches.
2510 */
2511 if (ring->hangcheck.score > 0)
2512 ring->hangcheck.score--;
2455 } 2513 }
2456 2514
2457 dev_priv->gpu_error.hangcheck_count = 0; 2515 ring->hangcheck.seqno = seqno;
2458 return; 2516 ring->hangcheck.acthd = acthd;
2517 busy_count += busy;
2459 } 2518 }
2460 2519
2461 work_done = false;
2462 for_each_ring(ring, dev_priv, i) { 2520 for_each_ring(ring, dev_priv, i) {
2463 if (ring->hangcheck.seqno != seqno[i]) { 2521 if (ring->hangcheck.score > FIRE) {
2464 work_done = true; 2522 DRM_ERROR("%s on %s\n",
2465 ring->hangcheck.seqno = seqno[i]; 2523 stuck[i] ? "stuck" : "no progress",
2524 ring->name);
2525 rings_hung++;
2466 } 2526 }
2467 } 2527 }
2468 2528
2469 if (!work_done) { 2529 if (rings_hung)
2470 if (i915_hangcheck_hung(dev)) 2530 return i915_handle_error(dev, true);
2471 return;
2472 } else {
2473 dev_priv->gpu_error.hangcheck_count = 0;
2474 }
2475 2531
2476repeat: 2532 if (busy_count)
2477 /* Reset timer case chip hangs without another request being added */ 2533 /* Reset timer case chip hangs without another request
2478 mod_timer(&dev_priv->gpu_error.hangcheck_timer, 2534 * being added */
2479 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 2535 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2536 round_jiffies_up(jiffies +
2537 DRM_I915_HANGCHECK_JIFFIES));
2538}
2539
2540static void ibx_irq_preinstall(struct drm_device *dev)
2541{
2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543
2544 if (HAS_PCH_NOP(dev))
2545 return;
2546
2547 /* south display irq */
2548 I915_WRITE(SDEIMR, 0xffffffff);
2549 /*
2550 * SDEIER is also touched by the interrupt handler to work around missed
2551 * PCH interrupts. Hence we can't update it after the interrupt handler
2552 * is enabled - instead we unconditionally enable all PCH interrupt
2553 * sources here, but then only unmask them as needed with SDEIMR.
2554 */
2555 I915_WRITE(SDEIER, 0xffffffff);
2556 POSTING_READ(SDEIER);
2480} 2557}
2481 2558
2482/* drm_dma.h hooks 2559/* drm_dma.h hooks
@@ -2500,16 +2577,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
2500 I915_WRITE(GTIER, 0x0); 2577 I915_WRITE(GTIER, 0x0);
2501 POSTING_READ(GTIER); 2578 POSTING_READ(GTIER);
2502 2579
2503 /* south display irq */ 2580 ibx_irq_preinstall(dev);
2504 I915_WRITE(SDEIMR, 0xffffffff);
2505 /*
2506 * SDEIER is also touched by the interrupt handler to work around missed
2507 * PCH interrupts. Hence we can't update it after the interrupt handler
2508 * is enabled - instead we unconditionally enable all PCH interrupt
2509 * sources here, but then only unmask them as needed with SDEIMR.
2510 */
2511 I915_WRITE(SDEIER, 0xffffffff);
2512 POSTING_READ(SDEIER);
2513} 2581}
2514 2582
2515static void ivybridge_irq_preinstall(struct drm_device *dev) 2583static void ivybridge_irq_preinstall(struct drm_device *dev)
@@ -2536,19 +2604,7 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
2536 I915_WRITE(GEN6_PMIER, 0x0); 2604 I915_WRITE(GEN6_PMIER, 0x0);
2537 POSTING_READ(GEN6_PMIER); 2605 POSTING_READ(GEN6_PMIER);
2538 2606
2539 if (HAS_PCH_NOP(dev)) 2607 ibx_irq_preinstall(dev);
2540 return;
2541
2542 /* south display irq */
2543 I915_WRITE(SDEIMR, 0xffffffff);
2544 /*
2545 * SDEIER is also touched by the interrupt handler to work around missed
2546 * PCH interrupts. Hence we can't update it after the interrupt handler
2547 * is enabled - instead we unconditionally enable all PCH interrupt
2548 * sources here, but then only unmask them as needed with SDEIMR.
2549 */
2550 I915_WRITE(SDEIER, 0xffffffff);
2551 POSTING_READ(SDEIER);
2552} 2608}
2553 2609
2554static void valleyview_irq_preinstall(struct drm_device *dev) 2610static void valleyview_irq_preinstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a593d20036c..2102ff32ee20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -147,15 +147,9 @@
147#define VGA_MSR_MEM_EN (1<<1) 147#define VGA_MSR_MEM_EN (1<<1)
148#define VGA_MSR_CGA_MODE (1<<0) 148#define VGA_MSR_CGA_MODE (1<<0)
149 149
150/* 150#define VGA_SR_INDEX 0x3c4
151 * SR01 is the only VGA register touched on non-UMS setups.
152 * VLV doesn't do UMS, so the sequencer index/data registers
153 * are the only VGA registers which need to include
154 * display_mmio_offset.
155 */
156#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
157#define SR01 1 151#define SR01 1
158#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5) 152#define VGA_SR_DATA 0x3c5
159 153
160#define VGA_AR_INDEX 0x3c0 154#define VGA_AR_INDEX 0x3c0
161#define VGA_AR_VID_EN (1<<5) 155#define VGA_AR_VID_EN (1<<5)
@@ -1026,6 +1020,10 @@
1026#define IPS_CTL 0x43408 1020#define IPS_CTL 0x43408
1027#define IPS_ENABLE (1 << 31) 1021#define IPS_ENABLE (1 << 31)
1028 1022
1023#define MSG_FBC_REND_STATE 0x50380
1024#define FBC_REND_NUKE (1<<2)
1025#define FBC_REND_CACHE_CLEAN (1<<1)
1026
1029#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 1027#define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
1030#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 1028#define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
1031#define HSW_BYPASS_FBC_QUEUE (1<<22) 1029#define HSW_BYPASS_FBC_QUEUE (1<<22)
@@ -1256,7 +1254,7 @@
1256#define DSTATE_PLL_D3_OFF (1<<3) 1254#define DSTATE_PLL_D3_OFF (1<<3)
1257#define DSTATE_GFX_CLOCK_GATING (1<<1) 1255#define DSTATE_GFX_CLOCK_GATING (1<<1)
1258#define DSTATE_DOT_CLOCK_GATING (1<<0) 1256#define DSTATE_DOT_CLOCK_GATING (1<<0)
1259#define DSPCLK_GATE_D 0x6200 1257#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
1260# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1258# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1261# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1259# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1262# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1260# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -1369,6 +1367,8 @@
1369#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 1367#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1370#define FW_CSPWRDWNEN (1<<15) 1368#define FW_CSPWRDWNEN (1<<15)
1371 1369
1370#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1371
1372/* 1372/*
1373 * Palette regs 1373 * Palette regs
1374 */ 1374 */
@@ -3672,9 +3672,9 @@
3672#define _GAMMA_MODE_B 0x4ac80 3672#define _GAMMA_MODE_B 0x4ac80
3673#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 3673#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3674#define GAMMA_MODE_MODE_MASK (3 << 0) 3674#define GAMMA_MODE_MODE_MASK (3 << 0)
3675#define GAMMA_MODE_MODE_8bit (0 << 0) 3675#define GAMMA_MODE_MODE_8BIT (0 << 0)
3676#define GAMMA_MODE_MODE_10bit (1 << 0) 3676#define GAMMA_MODE_MODE_10BIT (1 << 0)
3677#define GAMMA_MODE_MODE_12bit (2 << 0) 3677#define GAMMA_MODE_MODE_12BIT (2 << 0)
3678#define GAMMA_MODE_MODE_SPLIT (3 << 0) 3678#define GAMMA_MODE_MODE_SPLIT (3 << 0)
3679 3679
3680/* interrupts */ 3680/* interrupts */
@@ -3932,15 +3932,15 @@
3932 3932
3933#define _PCH_DPLL_A 0xc6014 3933#define _PCH_DPLL_A 0xc6014
3934#define _PCH_DPLL_B 0xc6018 3934#define _PCH_DPLL_B 0xc6018
3935#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3935#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3936 3936
3937#define _PCH_FPA0 0xc6040 3937#define _PCH_FPA0 0xc6040
3938#define FP_CB_TUNE (0x3<<22) 3938#define FP_CB_TUNE (0x3<<22)
3939#define _PCH_FPA1 0xc6044 3939#define _PCH_FPA1 0xc6044
3940#define _PCH_FPB0 0xc6048 3940#define _PCH_FPB0 0xc6048
3941#define _PCH_FPB1 0xc604c 3941#define _PCH_FPB1 0xc604c
3942#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 3942#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3943#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 3943#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
3944 3944
3945#define PCH_DPLL_TEST 0xc606c 3945#define PCH_DPLL_TEST 0xc606c
3946 3946
@@ -3980,15 +3980,9 @@
3980#define PCH_SSC4_AUX_PARMS 0xc6214 3980#define PCH_SSC4_AUX_PARMS 0xc6214
3981 3981
3982#define PCH_DPLL_SEL 0xc7000 3982#define PCH_DPLL_SEL 0xc7000
3983#define TRANSA_DPLL_ENABLE (1<<3) 3983#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
3984#define TRANSA_DPLLB_SEL (1<<0) 3984#define TRANS_DPLLA_SEL(pipe) 0
3985#define TRANSA_DPLLA_SEL 0 3985#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
3986#define TRANSB_DPLL_ENABLE (1<<7)
3987#define TRANSB_DPLLB_SEL (1<<4)
3988#define TRANSB_DPLLA_SEL (0)
3989#define TRANSC_DPLL_ENABLE (1<<11)
3990#define TRANSC_DPLLB_SEL (1<<8)
3991#define TRANSC_DPLLA_SEL (0)
3992 3986
3993/* transcoder */ 3987/* transcoder */
3994 3988
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 5ef30b2e6bc6..967da4772c44 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -41,7 +41,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
41 return false; 41 return false;
42 42
43 if (HAS_PCH_SPLIT(dev)) 43 if (HAS_PCH_SPLIT(dev))
44 dpll_reg = _PCH_DPLL(pipe); 44 dpll_reg = PCH_DPLL(pipe);
45 else 45 else
46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; 46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
47 47
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9649df806079..224ce25129ce 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -624,7 +624,7 @@ intel_ddi_calculate_wrpll(int clock /* in Hz */,
624 clock, *p_out, *n2_out, *r2_out); 624 clock, *p_out, *n2_out, *r2_out);
625} 625}
626 626
627bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) 627bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
628{ 628{
629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
630 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 630 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
@@ -634,6 +634,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
634 int type = intel_encoder->type; 634 int type = intel_encoder->type;
635 enum pipe pipe = intel_crtc->pipe; 635 enum pipe pipe = intel_crtc->pipe;
636 uint32_t reg, val; 636 uint32_t reg, val;
637 int clock = intel_crtc->config.port_clock;
637 638
638 /* TODO: reuse PLLs when possible (compare values) */ 639 /* TODO: reuse PLLs when possible (compare values) */
639 640
@@ -1278,7 +1279,6 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
1278 flags |= DRM_MODE_FLAG_NVSYNC; 1279 flags |= DRM_MODE_FLAG_NVSYNC;
1279 1280
1280 pipe_config->adjusted_mode.flags |= flags; 1281 pipe_config->adjusted_mode.flags |= flags;
1281 pipe_config->pixel_multiplier = 1;
1282} 1282}
1283 1283
1284static void intel_ddi_destroy(struct drm_encoder *encoder) 1284static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6eb99e13c37d..b08d1f9ce0de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -59,24 +59,6 @@ typedef struct intel_limit intel_limit_t;
59struct intel_limit { 59struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1; 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2; 61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80}; 62};
81 63
82/* FDI */ 64/* FDI */
@@ -92,20 +74,6 @@ intel_pch_rawclk(struct drm_device *dev)
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; 74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93} 75}
94 76
95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109static inline u32 /* units of 100MHz */ 77static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev) 78intel_fdi_link_freq(struct drm_device *dev)
111{ 79{
@@ -127,7 +95,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
127 .p1 = { .min = 2, .max = 33 }, 95 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000, 96 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 }, 97 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131}; 98};
132 99
133static const intel_limit_t intel_limits_i8xx_lvds = { 100static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -141,7 +108,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
141 .p1 = { .min = 1, .max = 6 }, 108 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000, 109 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 }, 110 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145}; 111};
146 112
147static const intel_limit_t intel_limits_i9xx_sdvo = { 113static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -155,7 +121,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
155 .p1 = { .min = 1, .max = 8 }, 121 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000, 122 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 }, 123 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159}; 124};
160 125
161static const intel_limit_t intel_limits_i9xx_lvds = { 126static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -169,7 +134,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
169 .p1 = { .min = 1, .max = 8 }, 134 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000, 135 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 }, 136 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173}; 137};
174 138
175 139
@@ -186,7 +150,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
186 .p2_slow = 10, 150 .p2_slow = 10,
187 .p2_fast = 10 151 .p2_fast = 10
188 }, 152 },
189 .find_pll = intel_g4x_find_best_PLL,
190}; 153};
191 154
192static const intel_limit_t intel_limits_g4x_hdmi = { 155static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -200,7 +163,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
200 .p1 = { .min = 1, .max = 8}, 163 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000, 164 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 }, 165 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204}; 166};
205 167
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -215,7 +177,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
215 .p2 = { .dot_limit = 0, 177 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14 178 .p2_slow = 14, .p2_fast = 14
217 }, 179 },
218 .find_pll = intel_g4x_find_best_PLL,
219}; 180};
220 181
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -230,7 +191,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
230 .p2 = { .dot_limit = 0, 191 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7 192 .p2_slow = 7, .p2_fast = 7
232 }, 193 },
233 .find_pll = intel_g4x_find_best_PLL,
234}; 194};
235 195
236static const intel_limit_t intel_limits_pineview_sdvo = { 196static const intel_limit_t intel_limits_pineview_sdvo = {
@@ -246,7 +206,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
246 .p1 = { .min = 1, .max = 8 }, 206 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000, 207 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 }, 208 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250}; 209};
251 210
252static const intel_limit_t intel_limits_pineview_lvds = { 211static const intel_limit_t intel_limits_pineview_lvds = {
@@ -260,7 +219,6 @@ static const intel_limit_t intel_limits_pineview_lvds = {
260 .p1 = { .min = 1, .max = 8 }, 219 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000, 220 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 }, 221 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264}; 222};
265 223
266/* Ironlake / Sandybridge 224/* Ironlake / Sandybridge
@@ -279,7 +237,6 @@ static const intel_limit_t intel_limits_ironlake_dac = {
279 .p1 = { .min = 1, .max = 8 }, 237 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000, 238 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 }, 239 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283}; 240};
284 241
285static const intel_limit_t intel_limits_ironlake_single_lvds = { 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
@@ -293,7 +250,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .p1 = { .min = 2, .max = 8 }, 250 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000, 251 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 }, 252 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297}; 253};
298 254
299static const intel_limit_t intel_limits_ironlake_dual_lvds = { 255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
@@ -307,7 +263,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .p1 = { .min = 2, .max = 8 }, 263 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000, 264 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 }, 265 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311}; 266};
312 267
313/* LVDS 100mhz refclk limits. */ 268/* LVDS 100mhz refclk limits. */
@@ -322,7 +277,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .p1 = { .min = 2, .max = 8 }, 277 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000, 278 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 }, 279 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326}; 280};
327 281
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
@@ -336,7 +290,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .p1 = { .min = 2, .max = 6 }, 290 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000, 291 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 }, 292 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340}; 293};
341 294
342static const intel_limit_t intel_limits_vlv_dac = { 295static const intel_limit_t intel_limits_vlv_dac = {
@@ -350,7 +303,6 @@ static const intel_limit_t intel_limits_vlv_dac = {
350 .p1 = { .min = 1, .max = 3 }, 303 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000, 304 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 }, 305 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354}; 306};
355 307
356static const intel_limit_t intel_limits_vlv_hdmi = { 308static const intel_limit_t intel_limits_vlv_hdmi = {
@@ -364,7 +316,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
364 .p1 = { .min = 2, .max = 3 }, 316 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000, 317 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 }, 318 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368}; 319};
369 320
370static const intel_limit_t intel_limits_vlv_dp = { 321static const intel_limit_t intel_limits_vlv_dp = {
@@ -378,7 +329,6 @@ static const intel_limit_t intel_limits_vlv_dp = {
378 .p1 = { .min = 1, .max = 3 }, 329 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000, 330 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 }, 331 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382}; 332};
383 333
384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
@@ -475,12 +425,8 @@ static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
476} 426}
477 427
478static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 428static void i9xx_clock(int refclk, intel_clock_t *clock)
479{ 429{
480 if (IS_PINEVIEW(dev)) {
481 pineview_clock(refclk, clock);
482 return;
483 }
484 clock->m = i9xx_dpll_compute_m(clock); 430 clock->m = i9xx_dpll_compute_m(clock);
485 clock->p = clock->p1 * clock->p2; 431 clock->p = clock->p1 * clock->p2;
486 clock->vco = refclk * clock->m / (clock->n + 2); 432 clock->vco = refclk * clock->m / (clock->n + 2);
@@ -538,10 +484,9 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
538} 484}
539 485
540static bool 486static bool
541intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
542 int target, int refclk, intel_clock_t *match_clock, 488 int target, int refclk, intel_clock_t *match_clock,
543 intel_clock_t *best_clock) 489 intel_clock_t *best_clock)
544
545{ 490{
546 struct drm_device *dev = crtc->dev; 491 struct drm_device *dev = crtc->dev;
547 intel_clock_t clock; 492 intel_clock_t clock;
@@ -570,8 +515,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
570 clock.m1++) { 515 clock.m1++) {
571 for (clock.m2 = limit->m2.min; 516 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) { 517 clock.m2 <= limit->m2.max; clock.m2++) {
573 /* m1 is always 0 in Pineview */ 518 if (clock.m2 >= clock.m1)
574 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
575 break; 519 break;
576 for (clock.n = limit->n.min; 520 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) { 521 clock.n <= limit->n.max; clock.n++) {
@@ -579,7 +523,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 clock.p1 <= limit->p1.max; clock.p1++) { 523 clock.p1 <= limit->p1.max; clock.p1++) {
580 int this_err; 524 int this_err;
581 525
582 intel_clock(dev, refclk, &clock); 526 i9xx_clock(refclk, &clock);
583 if (!intel_PLL_is_valid(dev, limit, 527 if (!intel_PLL_is_valid(dev, limit,
584 &clock)) 528 &clock))
585 continue; 529 continue;
@@ -601,9 +545,68 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
601} 545}
602 546
603static bool 547static bool
604intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
605 int target, int refclk, intel_clock_t *match_clock, 549 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock) 550 intel_clock_t *best_clock)
551{
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
588 continue;
589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
606static bool
607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
607{ 610{
608 struct drm_device *dev = crtc->dev; 611 struct drm_device *dev = crtc->dev;
609 intel_clock_t clock; 612 intel_clock_t clock;
@@ -638,7 +641,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
638 clock.p1 >= limit->p1.min; clock.p1--) { 641 clock.p1 >= limit->p1.min; clock.p1--) {
639 int this_err; 642 int this_err;
640 643
641 intel_clock(dev, refclk, &clock); 644 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit, 645 if (!intel_PLL_is_valid(dev, limit,
643 &clock)) 646 &clock))
644 continue; 647 continue;
@@ -658,9 +661,9 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
658} 661}
659 662
660static bool 663static bool
661intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
662 int target, int refclk, intel_clock_t *match_clock, 665 int target, int refclk, intel_clock_t *match_clock,
663 intel_clock_t *best_clock) 666 intel_clock_t *best_clock)
664{ 667{
665 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; 668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
666 u32 m, n, fastclk; 669 u32 m, n, fastclk;
@@ -906,14 +909,24 @@ static void assert_pll(struct drm_i915_private *dev_priv,
906#define assert_pll_enabled(d, p) assert_pll(d, p, true) 909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
907#define assert_pll_disabled(d, p) assert_pll(d, p, false) 910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
908 911
912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
917 if (crtc->config.shared_dpll < 0)
918 return NULL;
919
920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
921}
922
909/* For ILK+ */ 923/* For ILK+ */
910static void assert_pch_pll(struct drm_i915_private *dev_priv, 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
911 struct intel_pch_pll *pll, 925 struct intel_shared_dpll *pll,
912 struct intel_crtc *crtc, 926 bool state)
913 bool state)
914{ 927{
915 u32 val;
916 bool cur_state; 928 bool cur_state;
929 struct intel_dpll_hw_state hw_state;
917 930
918 if (HAS_PCH_LPT(dev_priv->dev)) { 931 if (HAS_PCH_LPT(dev_priv->dev)) {
919 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); 932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
@@ -921,36 +934,16 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
921 } 934 }
922 935
923 if (WARN (!pll, 936 if (WARN (!pll,
924 "asserting PCH PLL %s with no PLL\n", state_string(state))) 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
925 return; 938 return;
926 939
927 val = I915_READ(pll->pll_reg); 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state, 941 WARN(cur_state != state,
930 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", 942 "%s assertion failure (expected %s, current %s)\n",
931 pll->pll_reg, state_string(state), state_string(cur_state), val); 943 pll->name, state_string(state), state_string(cur_state));
932
933 /* Make sure the selected PLL is correctly attached to the transcoder */
934 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
935 u32 pch_dpll;
936
937 pch_dpll = I915_READ(PCH_DPLL_SEL);
938 cur_state = pll->pll_reg == _PCH_DPLL_B;
939 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
940 "PLL[%d] not attached to this transcoder %c: %08x\n",
941 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
942 cur_state = !!(val >> (4*crtc->pipe + 3));
943 WARN(cur_state != state,
944 "PLL[%d] not %s on this transcoder %c: %08x\n",
945 pll->pll_reg == _PCH_DPLL_B,
946 state_string(state),
947 pipe_name(crtc->pipe),
948 val);
949 }
950 }
951} 944}
952#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
953#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) 946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
954 947
955static void assert_fdi_tx(struct drm_i915_private *dev_priv, 948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
956 enum pipe pipe, bool state) 949 enum pipe pipe, bool state)
@@ -1102,12 +1095,13 @@ static void assert_plane(struct drm_i915_private *dev_priv,
1102static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103 enum pipe pipe) 1096 enum pipe pipe)
1104{ 1097{
1098 struct drm_device *dev = dev_priv->dev;
1105 int reg, i; 1099 int reg, i;
1106 u32 val; 1100 u32 val;
1107 int cur_pipe; 1101 int cur_pipe;
1108 1102
1109 /* Planes are fixed to pipes on ILK+ */ 1103 /* Primary planes are fixed to pipes on gen4+ */
1110 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { 1104 if (INTEL_INFO(dev)->gen >= 4) {
1111 reg = DSPCNTR(pipe); 1105 reg = DSPCNTR(pipe);
1112 val = I915_READ(reg); 1106 val = I915_READ(reg);
1113 WARN((val & DISPLAY_PLANE_ENABLE), 1107 WARN((val & DISPLAY_PLANE_ENABLE),
@@ -1117,7 +1111,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1117 } 1111 }
1118 1112
1119 /* Need to check both planes against the pipe */ 1113 /* Need to check both planes against the pipe */
1120 for (i = 0; i < 2; i++) { 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1121 reg = DSPCNTR(i); 1115 reg = DSPCNTR(i);
1122 val = I915_READ(reg); 1116 val = I915_READ(reg);
1123 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -1131,19 +1125,30 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1131static void assert_sprites_disabled(struct drm_i915_private *dev_priv, 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132 enum pipe pipe) 1126 enum pipe pipe)
1133{ 1127{
1128 struct drm_device *dev = dev_priv->dev;
1134 int reg, i; 1129 int reg, i;
1135 u32 val; 1130 u32 val;
1136 1131
1137 if (!IS_VALLEYVIEW(dev_priv->dev)) 1132 if (IS_VALLEYVIEW(dev)) {
1138 return; 1133 for (i = 0; i < dev_priv->num_plane; i++) {
1139 1134 reg = SPCNTR(pipe, i);
1140 /* Need to check both planes against the pipe */ 1135 val = I915_READ(reg);
1141 for (i = 0; i < dev_priv->num_plane; i++) { 1136 WARN((val & SP_ENABLE),
1142 reg = SPCNTR(pipe, i); 1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1143 val = I915_READ(reg); 1142 val = I915_READ(reg);
1144 WARN((val & SP_ENABLE), 1143 WARN((val & SPRITE_ENABLE),
1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n", 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 sprite_name(pipe, i), pipe_name(pipe)); 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
1147 } 1152 }
1148} 1153}
1149 1154
@@ -1382,94 +1387,71 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1382} 1387}
1383 1388
1384/** 1389/**
1385 * ironlake_enable_pch_pll - enable PCH PLL 1390 * ironlake_enable_shared_dpll - enable PCH PLL
1386 * @dev_priv: i915 private structure 1391 * @dev_priv: i915 private structure
1387 * @pipe: pipe PLL to enable 1392 * @pipe: pipe PLL to enable
1388 * 1393 *
1389 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390 * drives the transcoder clock. 1395 * drives the transcoder clock.
1391 */ 1396 */
1392static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1393{ 1398{
1394 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1395 struct intel_pch_pll *pll; 1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1396 int reg;
1397 u32 val;
1398 1401
1399 /* PCH PLLs only available on ILK, SNB and IVB */ 1402 /* PCH PLLs only available on ILK, SNB and IVB */
1400 BUG_ON(dev_priv->info->gen < 5); 1403 BUG_ON(dev_priv->info->gen < 5);
1401 pll = intel_crtc->pch_pll; 1404 if (WARN_ON(pll == NULL))
1402 if (pll == NULL)
1403 return; 1405 return;
1404 1406
1405 if (WARN_ON(pll->refcount == 0)) 1407 if (WARN_ON(pll->refcount == 0))
1406 return; 1408 return;
1407 1409
1408 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1409 pll->pll_reg, pll->active, pll->on, 1411 pll->name, pll->active, pll->on,
1410 intel_crtc->base.base.id); 1412 crtc->base.base.id);
1411
1412 /* PCH refclock must be enabled first */
1413 assert_pch_refclk_enabled(dev_priv);
1414 1413
1415 if (pll->active++ && pll->on) { 1414 if (pll->active++) {
1416 assert_pch_pll_enabled(dev_priv, pll, NULL); 1415 WARN_ON(!pll->on);
1416 assert_shared_dpll_enabled(dev_priv, pll);
1417 return; 1417 return;
1418 } 1418 }
1419 WARN_ON(pll->on);
1419 1420
1420 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1421 1422 pll->enable(dev_priv, pll);
1422 reg = pll->pll_reg;
1423 val = I915_READ(reg);
1424 val |= DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
1428
1429 pll->on = true; 1423 pll->on = true;
1430} 1424}
1431 1425
1432static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1433{ 1427{
1434 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1435 struct intel_pch_pll *pll = intel_crtc->pch_pll; 1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1436 int reg;
1437 u32 val;
1438 1430
1439 /* PCH only available on ILK+ */ 1431 /* PCH only available on ILK+ */
1440 BUG_ON(dev_priv->info->gen < 5); 1432 BUG_ON(dev_priv->info->gen < 5);
1441 if (pll == NULL) 1433 if (WARN_ON(pll == NULL))
1442 return; 1434 return;
1443 1435
1444 if (WARN_ON(pll->refcount == 0)) 1436 if (WARN_ON(pll->refcount == 0))
1445 return; 1437 return;
1446 1438
1447 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1448 pll->pll_reg, pll->active, pll->on, 1440 pll->name, pll->active, pll->on,
1449 intel_crtc->base.base.id); 1441 crtc->base.base.id);
1450 1442
1451 if (WARN_ON(pll->active == 0)) { 1443 if (WARN_ON(pll->active == 0)) {
1452 assert_pch_pll_disabled(dev_priv, pll, NULL); 1444 assert_shared_dpll_disabled(dev_priv, pll);
1453 return; 1445 return;
1454 } 1446 }
1455 1447
1456 if (--pll->active) { 1448 assert_shared_dpll_enabled(dev_priv, pll);
1457 assert_pch_pll_enabled(dev_priv, pll, NULL); 1449 WARN_ON(!pll->on);
1450 if (--pll->active)
1458 return; 1451 return;
1459 }
1460
1461 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463 /* Make sure transcoder isn't still depending on us */
1464 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1465
1466 reg = pll->pll_reg;
1467 val = I915_READ(reg);
1468 val &= ~DPLL_VCO_ENABLE;
1469 I915_WRITE(reg, val);
1470 POSTING_READ(reg);
1471 udelay(200);
1472 1452
1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454 pll->disable(dev_priv, pll);
1473 pll->on = false; 1455 pll->on = false;
1474} 1456}
1475 1457
@@ -1478,15 +1460,15 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1478{ 1460{
1479 struct drm_device *dev = dev_priv->dev; 1461 struct drm_device *dev = dev_priv->dev;
1480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1481 uint32_t reg, val, pipeconf_val; 1464 uint32_t reg, val, pipeconf_val;
1482 1465
1483 /* PCH only available on ILK+ */ 1466 /* PCH only available on ILK+ */
1484 BUG_ON(dev_priv->info->gen < 5); 1467 BUG_ON(dev_priv->info->gen < 5);
1485 1468
1486 /* Make sure PCH DPLL is enabled */ 1469 /* Make sure PCH DPLL is enabled */
1487 assert_pch_pll_enabled(dev_priv, 1470 assert_shared_dpll_enabled(dev_priv,
1488 to_intel_crtc(crtc)->pch_pll, 1471 intel_crtc_to_shared_dpll(intel_crtc));
1489 to_intel_crtc(crtc));
1490 1472
1491 /* FDI must be feeding us bits for PCH ports */ 1473 /* FDI must be feeding us bits for PCH ports */
1492 assert_fdi_tx_enabled(dev_priv, pipe); 1474 assert_fdi_tx_enabled(dev_priv, pipe);
@@ -1943,6 +1925,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1943 dspcntr &= ~DISPPLANE_TILED; 1925 dspcntr &= ~DISPPLANE_TILED;
1944 } 1926 }
1945 1927
1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
1946 I915_WRITE(reg, dspcntr); 1931 I915_WRITE(reg, dspcntr);
1947 1932
1948 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
@@ -2212,7 +2197,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2212 crtc->y = y; 2197 crtc->y = y;
2213 2198
2214 if (old_fb) { 2199 if (old_fb) {
2215 intel_wait_for_vblank(dev, intel_crtc->pipe); 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
2216 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2217 } 2203 }
2218 2204
@@ -2945,31 +2931,18 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
2945 * transcoder, and we actually should do this to not upset any PCH 2931 * transcoder, and we actually should do this to not upset any PCH
2946 * transcoder that already use the clock when we share it. 2932 * transcoder that already use the clock when we share it.
2947 * 2933 *
2948 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll 2934 * Note that enable_shared_dpll tries to do the right thing, but
2949 * unconditionally resets the pll - we need that to have the right LVDS 2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2950 * enable sequence. */ 2936 * the right LVDS enable sequence. */
2951 ironlake_enable_pch_pll(intel_crtc); 2937 ironlake_enable_shared_dpll(intel_crtc);
2952 2938
2953 if (HAS_PCH_CPT(dev)) { 2939 if (HAS_PCH_CPT(dev)) {
2954 u32 sel; 2940 u32 sel;
2955 2941
2956 temp = I915_READ(PCH_DPLL_SEL); 2942 temp = I915_READ(PCH_DPLL_SEL);
2957 switch (pipe) { 2943 temp |= TRANS_DPLL_ENABLE(pipe);
2958 default: 2944 sel = TRANS_DPLLB_SEL(pipe);
2959 case 0: 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2960 temp |= TRANSA_DPLL_ENABLE;
2961 sel = TRANSA_DPLLB_SEL;
2962 break;
2963 case 1:
2964 temp |= TRANSB_DPLL_ENABLE;
2965 sel = TRANSB_DPLLB_SEL;
2966 break;
2967 case 2:
2968 temp |= TRANSC_DPLL_ENABLE;
2969 sel = TRANSC_DPLLB_SEL;
2970 break;
2971 }
2972 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2973 temp |= sel; 2946 temp |= sel;
2974 else 2947 else
2975 temp &= ~sel; 2948 temp &= ~sel;
@@ -3038,69 +3011,72 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
3038 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3039} 3012}
3040 3013
3041static void intel_put_pch_pll(struct intel_crtc *intel_crtc) 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
3042{ 3015{
3043 struct intel_pch_pll *pll = intel_crtc->pch_pll; 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3044 3017
3045 if (pll == NULL) 3018 if (pll == NULL)
3046 return; 3019 return;
3047 3020
3048 if (pll->refcount == 0) { 3021 if (pll->refcount == 0) {
3049 WARN(1, "bad PCH PLL refcount\n"); 3022 WARN(1, "bad %s refcount\n", pll->name);
3050 return; 3023 return;
3051 } 3024 }
3052 3025
3053 --pll->refcount; 3026 if (--pll->refcount == 0) {
3054 intel_crtc->pch_pll = NULL; 3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3055} 3032}
3056 3033
3057static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3058{ 3035{
3059 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3060 struct intel_pch_pll *pll; 3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3061 int i; 3038 enum intel_dpll_id i;
3062 3039
3063 pll = intel_crtc->pch_pll;
3064 if (pll) { 3040 if (pll) {
3065 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3066 intel_crtc->base.base.id, pll->pll_reg); 3042 crtc->base.base.id, pll->name);
3067 goto prepare; 3043 intel_put_shared_dpll(crtc);
3068 } 3044 }
3069 3045
3070 if (HAS_PCH_IBX(dev_priv->dev)) { 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3071 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3072 i = intel_crtc->pipe; 3048 i = crtc->pipe;
3073 pll = &dev_priv->pch_plls[i]; 3049 pll = &dev_priv->shared_dplls[i];
3074 3050
3075 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3076 intel_crtc->base.base.id, pll->pll_reg); 3052 crtc->base.base.id, pll->name);
3077 3053
3078 goto found; 3054 goto found;
3079 } 3055 }
3080 3056
3081 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3082 pll = &dev_priv->pch_plls[i]; 3058 pll = &dev_priv->shared_dplls[i];
3083 3059
3084 /* Only want to check enabled timings first */ 3060 /* Only want to check enabled timings first */
3085 if (pll->refcount == 0) 3061 if (pll->refcount == 0)
3086 continue; 3062 continue;
3087 3063
3088 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && 3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3089 fp == I915_READ(pll->fp0_reg)) { 3065 fp == I915_READ(PCH_FP0(pll->id))) {
3090 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3091 intel_crtc->base.base.id, 3067 crtc->base.base.id,
3092 pll->pll_reg, pll->refcount, pll->active); 3068 pll->name, pll->refcount, pll->active);
3093 3069
3094 goto found; 3070 goto found;
3095 } 3071 }
3096 } 3072 }
3097 3073
3098 /* Ok no matching timings, maybe there's a free one? */ 3074 /* Ok no matching timings, maybe there's a free one? */
3099 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3100 pll = &dev_priv->pch_plls[i]; 3076 pll = &dev_priv->shared_dplls[i];
3101 if (pll->refcount == 0) { 3077 if (pll->refcount == 0) {
3102 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3103 intel_crtc->base.base.id, pll->pll_reg); 3079 crtc->base.base.id, pll->name);
3104 goto found; 3080 goto found;
3105 } 3081 }
3106 } 3082 }
@@ -3108,20 +3084,28 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3
3108 return NULL; 3084 return NULL;
3109 3085
3110found: 3086found:
3111 intel_crtc->pch_pll = pll; 3087 crtc->config.shared_dpll = i;
3112 pll->refcount++; 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3113 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe)); 3089 pipe_name(crtc->pipe));
3114prepare: /* separate function? */
3115 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3116 3090
3117 /* Wait for the clocks to stabilize before rewriting the regs */ 3091 if (pll->active == 0) {
3118 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3119 POSTING_READ(pll->pll_reg); 3093 sizeof(pll->hw_state));
3120 udelay(150); 3094
3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096 WARN_ON(pll->on);
3097 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099 /* Wait for the clocks to stabilize before rewriting the regs */
3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
3102 udelay(150);
3103
3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106 }
3107 pll->refcount++;
3121 3108
3122 I915_WRITE(pll->fp0_reg, fp);
3123 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3124 pll->on = false;
3125 return pll; 3109 return pll;
3126} 3110}
3127 3111
@@ -3160,6 +3144,28 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
3160 } 3144 }
3161} 3145}
3162 3146
3147static void intel_enable_planes(struct drm_crtc *crtc)
3148{
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156}
3157
3158static void intel_disable_planes(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167}
3168
3163static void ironlake_crtc_enable(struct drm_crtc *crtc) 3169static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164{ 3170{
3165 struct drm_device *dev = crtc->dev; 3171 struct drm_device *dev = crtc->dev;
@@ -3203,7 +3209,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3203 if (encoder->pre_enable) 3209 if (encoder->pre_enable)
3204 encoder->pre_enable(encoder); 3210 encoder->pre_enable(encoder);
3205 3211
3206 /* Enable panel fitting for LVDS */
3207 ironlake_pfit_enable(intel_crtc); 3212 ironlake_pfit_enable(intel_crtc);
3208 3213
3209 /* 3214 /*
@@ -3215,6 +3220,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3215 intel_enable_pipe(dev_priv, pipe, 3220 intel_enable_pipe(dev_priv, pipe,
3216 intel_crtc->config.has_pch_encoder); 3221 intel_crtc->config.has_pch_encoder);
3217 intel_enable_plane(dev_priv, plane, pipe); 3222 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_enable_planes(crtc);
3224 intel_crtc_update_cursor(crtc, true);
3218 3225
3219 if (intel_crtc->config.has_pch_encoder) 3226 if (intel_crtc->config.has_pch_encoder)
3220 ironlake_pch_enable(crtc); 3227 ironlake_pch_enable(crtc);
@@ -3223,8 +3230,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3223 intel_update_fbc(dev); 3230 intel_update_fbc(dev);
3224 mutex_unlock(&dev->struct_mutex); 3231 mutex_unlock(&dev->struct_mutex);
3225 3232
3226 intel_crtc_update_cursor(crtc, true);
3227
3228 for_each_encoder_on_crtc(dev, crtc, encoder) 3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3229 encoder->enable(encoder); 3234 encoder->enable(encoder);
3230 3235
@@ -3309,7 +3314,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3309 3314
3310 intel_ddi_enable_pipe_clock(intel_crtc); 3315 intel_ddi_enable_pipe_clock(intel_crtc);
3311 3316
3312 /* Enable panel fitting for eDP */
3313 ironlake_pfit_enable(intel_crtc); 3317 ironlake_pfit_enable(intel_crtc);
3314 3318
3315 /* 3319 /*
@@ -3324,6 +3328,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3324 intel_enable_pipe(dev_priv, pipe, 3328 intel_enable_pipe(dev_priv, pipe,
3325 intel_crtc->config.has_pch_encoder); 3329 intel_crtc->config.has_pch_encoder);
3326 intel_enable_plane(dev_priv, plane, pipe); 3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3327 3333
3328 hsw_enable_ips(intel_crtc); 3334 hsw_enable_ips(intel_crtc);
3329 3335
@@ -3334,8 +3340,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3334 intel_update_fbc(dev); 3340 intel_update_fbc(dev);
3335 mutex_unlock(&dev->struct_mutex); 3341 mutex_unlock(&dev->struct_mutex);
3336 3342
3337 intel_crtc_update_cursor(crtc, true);
3338
3339 for_each_encoder_on_crtc(dev, crtc, encoder) 3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3340 encoder->enable(encoder); 3344 encoder->enable(encoder);
3341 3345
@@ -3384,14 +3388,17 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
3384 3388
3385 intel_crtc_wait_for_pending_flips(crtc); 3389 intel_crtc_wait_for_pending_flips(crtc);
3386 drm_vblank_off(dev, pipe); 3390 drm_vblank_off(dev, pipe);
3387 intel_crtc_update_cursor(crtc, false);
3388
3389 intel_disable_plane(dev_priv, plane, pipe);
3390 3391
3391 if (dev_priv->cfb_plane == plane) 3392 if (dev_priv->cfb_plane == plane)
3392 intel_disable_fbc(dev); 3393 intel_disable_fbc(dev);
3393 3394
3394 intel_set_pch_fifo_underrun_reporting(dev, pipe, false); 3395 intel_crtc_update_cursor(crtc, false);
3396 intel_disable_planes(crtc);
3397 intel_disable_plane(dev_priv, plane, pipe);
3398
3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3401
3395 intel_disable_pipe(dev_priv, pipe); 3402 intel_disable_pipe(dev_priv, pipe);
3396 3403
3397 ironlake_pfit_disable(intel_crtc); 3404 ironlake_pfit_disable(intel_crtc);
@@ -3400,42 +3407,32 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
3400 if (encoder->post_disable) 3407 if (encoder->post_disable)
3401 encoder->post_disable(encoder); 3408 encoder->post_disable(encoder);
3402 3409
3403 ironlake_fdi_disable(crtc); 3410 if (intel_crtc->config.has_pch_encoder) {
3404 3411 ironlake_fdi_disable(crtc);
3405 ironlake_disable_pch_transcoder(dev_priv, pipe);
3406 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3407 3412
3408 if (HAS_PCH_CPT(dev)) { 3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3409 /* disable TRANS_DP_CTL */ 3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3410 reg = TRANS_DP_CTL(pipe);
3411 temp = I915_READ(reg);
3412 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3413 temp |= TRANS_DP_PORT_SEL_NONE;
3414 I915_WRITE(reg, temp);
3415 3415
3416 /* disable DPLL_SEL */ 3416 if (HAS_PCH_CPT(dev)) {
3417 temp = I915_READ(PCH_DPLL_SEL); 3417 /* disable TRANS_DP_CTL */
3418 switch (pipe) { 3418 reg = TRANS_DP_CTL(pipe);
3419 case 0: 3419 temp = I915_READ(reg);
3420 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3421 break; 3421 TRANS_DP_PORT_SEL_MASK);
3422 case 1: 3422 temp |= TRANS_DP_PORT_SEL_NONE;
3423 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 3423 I915_WRITE(reg, temp);
3424 break; 3424
3425 case 2: 3425 /* disable DPLL_SEL */
3426 /* C shares PLL A or B */ 3426 temp = I915_READ(PCH_DPLL_SEL);
3427 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3428 break; 3428 I915_WRITE(PCH_DPLL_SEL, temp);
3429 default:
3430 BUG(); /* wtf */
3431 } 3429 }
3432 I915_WRITE(PCH_DPLL_SEL, temp);
3433 }
3434 3430
3435 /* disable PCH DPLL */ 3431 /* disable PCH DPLL */
3436 intel_disable_pch_pll(intel_crtc); 3432 intel_disable_shared_dpll(intel_crtc);
3437 3433
3438 ironlake_fdi_pll_disable(intel_crtc); 3434 ironlake_fdi_pll_disable(intel_crtc);
3435 }
3439 3436
3440 intel_crtc->active = false; 3437 intel_crtc->active = false;
3441 intel_update_watermarks(dev); 3438 intel_update_watermarks(dev);
@@ -3463,7 +3460,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3463 3460
3464 intel_crtc_wait_for_pending_flips(crtc); 3461 intel_crtc_wait_for_pending_flips(crtc);
3465 drm_vblank_off(dev, pipe); 3462 drm_vblank_off(dev, pipe);
3466 intel_crtc_update_cursor(crtc, false);
3467 3463
3468 /* FBC must be disabled before disabling the plane on HSW. */ 3464 /* FBC must be disabled before disabling the plane on HSW. */
3469 if (dev_priv->cfb_plane == plane) 3465 if (dev_priv->cfb_plane == plane)
@@ -3471,6 +3467,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3471 3467
3472 hsw_disable_ips(intel_crtc); 3468 hsw_disable_ips(intel_crtc);
3473 3469
3470 intel_crtc_update_cursor(crtc, false);
3471 intel_disable_planes(crtc);
3474 intel_disable_plane(dev_priv, plane, pipe); 3472 intel_disable_plane(dev_priv, plane, pipe);
3475 3473
3476 if (intel_crtc->config.has_pch_encoder) 3474 if (intel_crtc->config.has_pch_encoder)
@@ -3504,7 +3502,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
3504static void ironlake_crtc_off(struct drm_crtc *crtc) 3502static void ironlake_crtc_off(struct drm_crtc *crtc)
3505{ 3503{
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 intel_put_pch_pll(intel_crtc); 3505 intel_put_shared_dpll(intel_crtc);
3508} 3506}
3509 3507
3510static void haswell_crtc_off(struct drm_crtc *crtc) 3508static void haswell_crtc_off(struct drm_crtc *crtc)
@@ -3611,19 +3609,17 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
3611 for_each_encoder_on_crtc(dev, crtc, encoder) 3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3612 encoder->enable(encoder); 3610 encoder->enable(encoder);
3613 3611
3614 /* Enable panel fitting for eDP */
3615 i9xx_pfit_enable(intel_crtc); 3612 i9xx_pfit_enable(intel_crtc);
3616 3613
3614 intel_crtc_load_lut(crtc);
3615
3617 intel_enable_pipe(dev_priv, pipe, false); 3616 intel_enable_pipe(dev_priv, pipe, false);
3618 intel_enable_plane(dev_priv, plane, pipe); 3617 intel_enable_plane(dev_priv, plane, pipe);
3618 intel_enable_planes(crtc);
3619 intel_crtc_update_cursor(crtc, true);
3619 3620
3620 intel_crtc_load_lut(crtc);
3621 intel_update_fbc(dev); 3621 intel_update_fbc(dev);
3622 3622
3623 /* Give the overlay scaler a chance to enable if it's on this pipe */
3624 intel_crtc_dpms_overlay(intel_crtc, true);
3625 intel_crtc_update_cursor(crtc, true);
3626
3627 mutex_unlock(&dev_priv->dpio_lock); 3623 mutex_unlock(&dev_priv->dpio_lock);
3628} 3624}
3629 3625
@@ -3650,20 +3646,22 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
3650 if (encoder->pre_enable) 3646 if (encoder->pre_enable)
3651 encoder->pre_enable(encoder); 3647 encoder->pre_enable(encoder);
3652 3648
3653 /* Enable panel fitting for LVDS */
3654 i9xx_pfit_enable(intel_crtc); 3649 i9xx_pfit_enable(intel_crtc);
3655 3650
3651 intel_crtc_load_lut(crtc);
3652
3656 intel_enable_pipe(dev_priv, pipe, false); 3653 intel_enable_pipe(dev_priv, pipe, false);
3657 intel_enable_plane(dev_priv, plane, pipe); 3654 intel_enable_plane(dev_priv, plane, pipe);
3655 intel_enable_planes(crtc);
3656 /* The fixup needs to happen before cursor is enabled */
3658 if (IS_G4X(dev)) 3657 if (IS_G4X(dev))
3659 g4x_fixup_plane(dev_priv, pipe); 3658 g4x_fixup_plane(dev_priv, pipe);
3660 3659 intel_crtc_update_cursor(crtc, true);
3661 intel_crtc_load_lut(crtc);
3662 intel_update_fbc(dev);
3663 3660
3664 /* Give the overlay scaler a chance to enable if it's on this pipe */ 3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3665 intel_crtc_dpms_overlay(intel_crtc, true); 3662 intel_crtc_dpms_overlay(intel_crtc, true);
3666 intel_crtc_update_cursor(crtc, true); 3663
3664 intel_update_fbc(dev);
3667 3665
3668 for_each_encoder_on_crtc(dev, crtc, encoder) 3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3669 encoder->enable(encoder); 3667 encoder->enable(encoder);
@@ -3702,13 +3700,15 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
3702 /* Give the overlay scaler a chance to disable if it's on this pipe */ 3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
3703 intel_crtc_wait_for_pending_flips(crtc); 3701 intel_crtc_wait_for_pending_flips(crtc);
3704 drm_vblank_off(dev, pipe); 3702 drm_vblank_off(dev, pipe);
3705 intel_crtc_dpms_overlay(intel_crtc, false);
3706 intel_crtc_update_cursor(crtc, false);
3707 3703
3708 if (dev_priv->cfb_plane == plane) 3704 if (dev_priv->cfb_plane == plane)
3709 intel_disable_fbc(dev); 3705 intel_disable_fbc(dev);
3710 3706
3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
3709 intel_disable_planes(crtc);
3711 intel_disable_plane(dev_priv, plane, pipe); 3710 intel_disable_plane(dev_priv, plane, pipe);
3711
3712 intel_disable_pipe(dev_priv, pipe); 3712 intel_disable_pipe(dev_priv, pipe);
3713 3713
3714 i9xx_pfit_disable(intel_crtc); 3714 i9xx_pfit_disable(intel_crtc);
@@ -3985,7 +3985,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3985{ 3985{
3986 struct drm_device *dev = intel_crtc->base.dev; 3986 struct drm_device *dev = intel_crtc->base.dev;
3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988 int target_clock, lane, link_bw; 3988 int lane, link_bw, fdi_dotclock;
3989 bool setup_ok, needs_recompute = false; 3989 bool setup_ok, needs_recompute = false;
3990 3990
3991retry: 3991retry:
@@ -3998,19 +3998,15 @@ retry:
3998 */ 3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000 4000
4001 if (pipe_config->pixel_target_clock) 4001 fdi_dotclock = adjusted_mode->clock;
4002 target_clock = pipe_config->pixel_target_clock; 4002 fdi_dotclock /= pipe_config->pixel_multiplier;
4003 else
4004 target_clock = adjusted_mode->clock;
4005 4003
4006 lane = ironlake_get_lanes_required(target_clock, link_bw, 4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4007 pipe_config->pipe_bpp); 4005 pipe_config->pipe_bpp);
4008 4006
4009 pipe_config->fdi_lanes = lane; 4007 pipe_config->fdi_lanes = lane;
4010 4008
4011 if (pipe_config->pixel_multiplier > 1) 4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4012 link_bw *= pipe_config->pixel_multiplier;
4013 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4014 link_bw, &pipe_config->fdi_m_n); 4010 link_bw, &pipe_config->fdi_m_n);
4015 4011
4016 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, 4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
@@ -4039,12 +4035,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
4039 pipe_config->pipe_bpp == 24; 4035 pipe_config->pipe_bpp == 24;
4040} 4036}
4041 4037
4042static int intel_crtc_compute_config(struct drm_crtc *crtc, 4038static int intel_crtc_compute_config(struct intel_crtc *crtc,
4043 struct intel_crtc_config *pipe_config) 4039 struct intel_crtc_config *pipe_config)
4044{ 4040{
4045 struct drm_device *dev = crtc->dev; 4041 struct drm_device *dev = crtc->base.dev;
4046 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4048 4043
4049 if (HAS_PCH_SPLIT(dev)) { 4044 if (HAS_PCH_SPLIT(dev)) {
4050 /* FDI link clock is fixed at 2.7G */ 4045 /* FDI link clock is fixed at 2.7G */
@@ -4075,10 +4070,15 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
4075 } 4070 }
4076 4071
4077 if (IS_HASWELL(dev)) 4072 if (IS_HASWELL(dev))
4078 hsw_compute_ips_config(intel_crtc, pipe_config); 4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
4079 4079
4080 if (pipe_config->has_pch_encoder) 4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(intel_crtc, pipe_config); 4081 return ironlake_fdi_compute_config(crtc, pipe_config);
4082 4082
4083 return 0; 4083 return 0;
4084} 4084}
@@ -4239,7 +4239,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4239 4239
4240static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) 4240static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241{ 4241{
4242 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2; 4242 return (1 << dpll->n) << 16 | dpll->m2;
4243} 4243}
4244 4244
4245static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) 4245static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
@@ -4351,8 +4351,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4351{ 4351{
4352 struct drm_device *dev = crtc->base.dev; 4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private; 4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct drm_display_mode *adjusted_mode =
4355 &crtc->config.adjusted_mode;
4356 struct intel_encoder *encoder; 4354 struct intel_encoder *encoder;
4357 int pipe = crtc->pipe; 4355 int pipe = crtc->pipe;
4358 u32 dpll, mdiv; 4356 u32 dpll, mdiv;
@@ -4405,7 +4403,7 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4405 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); 4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4406 4404
4407 /* Set HBR and RBR LPF coefficients */ 4405 /* Set HBR and RBR LPF coefficients */
4408 if (adjusted_mode->clock == 162000 || 4406 if (crtc->config.port_clock == 162000 ||
4409 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) 4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4410 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 4408 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4411 0x005f0021); 4409 0x005f0021);
@@ -4459,11 +4457,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4459 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 4457 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4460 DRM_ERROR("DPLL %d failed to lock\n", pipe); 4458 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4461 4459
4462 dpll_md = 0; 4460 dpll_md = (crtc->config.pixel_multiplier - 1)
4463 if (crtc->config.pixel_multiplier > 1) { 4461 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4464 dpll_md = (crtc->config.pixel_multiplier - 1)
4465 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4466 }
4467 I915_WRITE(DPLL_MD(pipe), dpll_md); 4462 I915_WRITE(DPLL_MD(pipe), dpll_md);
4468 POSTING_READ(DPLL_MD(pipe)); 4463 POSTING_READ(DPLL_MD(pipe));
4469 4464
@@ -4497,8 +4492,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4497 else 4492 else
4498 dpll |= DPLLB_MODE_DAC_SERIAL; 4493 dpll |= DPLLB_MODE_DAC_SERIAL;
4499 4494
4500 if ((crtc->config.pixel_multiplier > 1) && 4495 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4501 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4502 dpll |= (crtc->config.pixel_multiplier - 1) 4496 dpll |= (crtc->config.pixel_multiplier - 1)
4503 << SDVO_MULTIPLIER_SHIFT_HIRES; 4497 << SDVO_MULTIPLIER_SHIFT_HIRES;
4504 } 4498 }
@@ -4561,11 +4555,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4561 udelay(150); 4555 udelay(150);
4562 4556
4563 if (INTEL_INFO(dev)->gen >= 4) { 4557 if (INTEL_INFO(dev)->gen >= 4) {
4564 u32 dpll_md = 0; 4558 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4565 if (crtc->config.pixel_multiplier > 1) { 4559 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4566 dpll_md = (crtc->config.pixel_multiplier - 1)
4567 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4568 }
4569 I915_WRITE(DPLL_MD(pipe), dpll_md); 4560 I915_WRITE(DPLL_MD(pipe), dpll_md);
4570 } else { 4561 } else {
4571 /* The pixel multiplier can only be updated once the 4562 /* The pixel multiplier can only be updated once the
@@ -4578,7 +4569,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
4578} 4569}
4579 4570
4580static void i8xx_update_pll(struct intel_crtc *crtc, 4571static void i8xx_update_pll(struct intel_crtc *crtc,
4581 struct drm_display_mode *adjusted_mode,
4582 intel_clock_t *reduced_clock, 4572 intel_clock_t *reduced_clock,
4583 int num_connectors) 4573 int num_connectors)
4584{ 4574{
@@ -4633,14 +4623,15 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
4633 I915_WRITE(DPLL(pipe), dpll); 4623 I915_WRITE(DPLL(pipe), dpll);
4634} 4624}
4635 4625
4636static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, 4626static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4637 struct drm_display_mode *mode,
4638 struct drm_display_mode *adjusted_mode)
4639{ 4627{
4640 struct drm_device *dev = intel_crtc->base.dev; 4628 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private; 4629 struct drm_i915_private *dev_priv = dev->dev_private;
4642 enum pipe pipe = intel_crtc->pipe; 4630 enum pipe pipe = intel_crtc->pipe;
4643 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4631 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4632 struct drm_display_mode *adjusted_mode =
4633 &intel_crtc->config.adjusted_mode;
4634 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4644 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; 4635 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4645 4636
4646 /* We need to be careful not to changed the adjusted mode, for otherwise 4637 /* We need to be careful not to changed the adjusted mode, for otherwise
@@ -4741,7 +4732,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4741 struct drm_i915_private *dev_priv = dev->dev_private; 4732 struct drm_i915_private *dev_priv = dev->dev_private;
4742 uint32_t pipeconf; 4733 uint32_t pipeconf;
4743 4734
4744 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); 4735 pipeconf = 0;
4745 4736
4746 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { 4737 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4747 /* Enable pixel doubling when the dot clock is > 90% of the (display) 4738 /* Enable pixel doubling when the dot clock is > 90% of the (display)
@@ -4753,15 +4744,10 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4753 if (intel_crtc->config.requested_mode.clock > 4744 if (intel_crtc->config.requested_mode.clock >
4754 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 4745 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4755 pipeconf |= PIPECONF_DOUBLE_WIDE; 4746 pipeconf |= PIPECONF_DOUBLE_WIDE;
4756 else
4757 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4758 } 4747 }
4759 4748
4760 /* only g4x and later have fancy bpc/dither controls */ 4749 /* only g4x and later have fancy bpc/dither controls */
4761 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { 4750 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4762 pipeconf &= ~(PIPECONF_BPC_MASK |
4763 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4764
4765 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 4751 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4766 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) 4752 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4767 pipeconf |= PIPECONF_DITHER_EN | 4753 pipeconf |= PIPECONF_DITHER_EN |
@@ -4789,23 +4775,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4789 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4775 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4790 } else { 4776 } else {
4791 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4777 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4792 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4793 } 4778 }
4794 } 4779 }
4795 4780
4796 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4797 if (!IS_GEN2(dev) && 4781 if (!IS_GEN2(dev) &&
4798 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 4782 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4799 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 4783 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4800 else 4784 else
4801 pipeconf |= PIPECONF_PROGRESSIVE; 4785 pipeconf |= PIPECONF_PROGRESSIVE;
4802 4786
4803 if (IS_VALLEYVIEW(dev)) { 4787 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4804 if (intel_crtc->config.limited_color_range) 4788 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4805 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4806 else
4807 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4808 }
4809 4789
4810 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 4790 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4811 POSTING_READ(PIPECONF(intel_crtc->pipe)); 4791 POSTING_READ(PIPECONF(intel_crtc->pipe));
@@ -4818,8 +4798,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4818 struct drm_device *dev = crtc->dev; 4798 struct drm_device *dev = crtc->dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private; 4799 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821 struct drm_display_mode *adjusted_mode =
4822 &intel_crtc->config.adjusted_mode;
4823 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 4801 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4824 int pipe = intel_crtc->pipe; 4802 int pipe = intel_crtc->pipe;
4825 int plane = intel_crtc->plane; 4803 int plane = intel_crtc->plane;
@@ -4850,9 +4828,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4850 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 4828 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4851 */ 4829 */
4852 limit = intel_limit(crtc, refclk); 4830 limit = intel_limit(crtc, refclk);
4853 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4831 ok = dev_priv->display.find_dpll(limit, crtc,
4854 &clock); 4832 intel_crtc->config.port_clock,
4855 if (!ok) { 4833 refclk, NULL, &clock);
4834 if (!ok && !intel_crtc->config.clock_set) {
4856 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4835 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4857 return -EINVAL; 4836 return -EINVAL;
4858 } 4837 }
@@ -4867,10 +4846,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4867 * by using the FP0/FP1. In such case we will disable the LVDS 4846 * by using the FP0/FP1. In such case we will disable the LVDS
4868 * downclock feature. 4847 * downclock feature.
4869 */ 4848 */
4870 has_reduced_clock = limit->find_pll(limit, crtc, 4849 has_reduced_clock =
4850 dev_priv->display.find_dpll(limit, crtc,
4871 dev_priv->lvds_downclock, 4851 dev_priv->lvds_downclock,
4872 refclk, 4852 refclk, &clock,
4873 &clock,
4874 &reduced_clock); 4853 &reduced_clock);
4875 } 4854 }
4876 /* Compat-code for transition, will disappear. */ 4855 /* Compat-code for transition, will disappear. */
@@ -4883,7 +4862,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4883 } 4862 }
4884 4863
4885 if (IS_GEN2(dev)) 4864 if (IS_GEN2(dev))
4886 i8xx_update_pll(intel_crtc, adjusted_mode, 4865 i8xx_update_pll(intel_crtc,
4887 has_reduced_clock ? &reduced_clock : NULL, 4866 has_reduced_clock ? &reduced_clock : NULL,
4888 num_connectors); 4867 num_connectors);
4889 else if (IS_VALLEYVIEW(dev)) 4868 else if (IS_VALLEYVIEW(dev))
@@ -4903,7 +4882,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4903 dspcntr |= DISPPLANE_SEL_PIPE_B; 4882 dspcntr |= DISPPLANE_SEL_PIPE_B;
4904 } 4883 }
4905 4884
4906 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 4885 intel_set_pipe_timings(intel_crtc);
4907 4886
4908 /* pipesrc and dspsize control the size that is scaled from, 4887 /* pipesrc and dspsize control the size that is scaled from,
4909 * which should always be the user's requested size. 4888 * which should always be the user's requested size.
@@ -4963,6 +4942,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963 uint32_t tmp; 4942 uint32_t tmp;
4964 4943
4965 pipe_config->cpu_transcoder = crtc->pipe; 4944 pipe_config->cpu_transcoder = crtc->pipe;
4945 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4966 4946
4967 tmp = I915_READ(PIPECONF(crtc->pipe)); 4947 tmp = I915_READ(PIPECONF(crtc->pipe));
4968 if (!(tmp & PIPECONF_ENABLE)) 4948 if (!(tmp & PIPECONF_ENABLE))
@@ -4972,6 +4952,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4972 4952
4973 i9xx_get_pfit_config(crtc, pipe_config); 4953 i9xx_get_pfit_config(crtc, pipe_config);
4974 4954
4955 if (INTEL_INFO(dev)->gen >= 4) {
4956 tmp = I915_READ(DPLL_MD(crtc->pipe));
4957 pipe_config->pixel_multiplier =
4958 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4959 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4960 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4961 tmp = I915_READ(DPLL(crtc->pipe));
4962 pipe_config->pixel_multiplier =
4963 ((tmp & SDVO_MULTIPLIER_MASK)
4964 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4965 } else {
4966 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4967 * port and will be fixed up in the encoder->get_config
4968 * function. */
4969 pipe_config->pixel_multiplier = 1;
4970 }
4971
4975 return true; 4972 return true;
4976} 4973}
4977 4974
@@ -5330,9 +5327,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5330 int pipe = intel_crtc->pipe; 5327 int pipe = intel_crtc->pipe;
5331 uint32_t val; 5328 uint32_t val;
5332 5329
5333 val = I915_READ(PIPECONF(pipe)); 5330 val = 0;
5334 5331
5335 val &= ~PIPECONF_BPC_MASK;
5336 switch (intel_crtc->config.pipe_bpp) { 5332 switch (intel_crtc->config.pipe_bpp) {
5337 case 18: 5333 case 18:
5338 val |= PIPECONF_6BPC; 5334 val |= PIPECONF_6BPC;
@@ -5351,11 +5347,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5351 BUG(); 5347 BUG();
5352 } 5348 }
5353 5349
5354 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5355 if (intel_crtc->config.dither) 5350 if (intel_crtc->config.dither)
5356 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5351 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5357 5352
5358 val &= ~PIPECONF_INTERLACE_MASK;
5359 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5353 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5360 val |= PIPECONF_INTERLACED_ILK; 5354 val |= PIPECONF_INTERLACED_ILK;
5361 else 5355 else
@@ -5363,8 +5357,6 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5363 5357
5364 if (intel_crtc->config.limited_color_range) 5358 if (intel_crtc->config.limited_color_range)
5365 val |= PIPECONF_COLOR_RANGE_SELECT; 5359 val |= PIPECONF_COLOR_RANGE_SELECT;
5366 else
5367 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5368 5360
5369 I915_WRITE(PIPECONF(pipe), val); 5361 I915_WRITE(PIPECONF(pipe), val);
5370 POSTING_READ(PIPECONF(pipe)); 5362 POSTING_READ(PIPECONF(pipe));
@@ -5441,13 +5433,11 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
5441 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 5433 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5442 uint32_t val; 5434 uint32_t val;
5443 5435
5444 val = I915_READ(PIPECONF(cpu_transcoder)); 5436 val = 0;
5445 5437
5446 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5447 if (intel_crtc->config.dither) 5438 if (intel_crtc->config.dither)
5448 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5439 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5449 5440
5450 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5451 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 5441 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5452 val |= PIPECONF_INTERLACED_ILK; 5442 val |= PIPECONF_INTERLACED_ILK;
5453 else 5443 else
@@ -5455,10 +5445,12 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
5455 5445
5456 I915_WRITE(PIPECONF(cpu_transcoder), val); 5446 I915_WRITE(PIPECONF(cpu_transcoder), val);
5457 POSTING_READ(PIPECONF(cpu_transcoder)); 5447 POSTING_READ(PIPECONF(cpu_transcoder));
5448
5449 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5450 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5458} 5451}
5459 5452
5460static bool ironlake_compute_clocks(struct drm_crtc *crtc, 5453static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5461 struct drm_display_mode *adjusted_mode,
5462 intel_clock_t *clock, 5454 intel_clock_t *clock,
5463 bool *has_reduced_clock, 5455 bool *has_reduced_clock,
5464 intel_clock_t *reduced_clock) 5456 intel_clock_t *reduced_clock)
@@ -5486,8 +5478,9 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5486 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 5478 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5487 */ 5479 */
5488 limit = intel_limit(crtc, refclk); 5480 limit = intel_limit(crtc, refclk);
5489 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 5481 ret = dev_priv->display.find_dpll(limit, crtc,
5490 clock); 5482 to_intel_crtc(crtc)->config.port_clock,
5483 refclk, NULL, clock);
5491 if (!ret) 5484 if (!ret)
5492 return false; 5485 return false;
5493 5486
@@ -5498,11 +5491,11 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5498 * by using the FP0/FP1. In such case we will disable the LVDS 5491 * by using the FP0/FP1. In such case we will disable the LVDS
5499 * downclock feature. 5492 * downclock feature.
5500 */ 5493 */
5501 *has_reduced_clock = limit->find_pll(limit, crtc, 5494 *has_reduced_clock =
5502 dev_priv->lvds_downclock, 5495 dev_priv->display.find_dpll(limit, crtc,
5503 refclk, 5496 dev_priv->lvds_downclock,
5504 clock, 5497 refclk, clock,
5505 reduced_clock); 5498 reduced_clock);
5506 } 5499 }
5507 5500
5508 return true; 5501 return true;
@@ -5615,10 +5608,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5615 else 5608 else
5616 dpll |= DPLLB_MODE_DAC_SERIAL; 5609 dpll |= DPLLB_MODE_DAC_SERIAL;
5617 5610
5618 if (intel_crtc->config.pixel_multiplier > 1) { 5611 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5619 dpll |= (intel_crtc->config.pixel_multiplier - 1) 5612 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5620 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5621 }
5622 5613
5623 if (is_sdvo) 5614 if (is_sdvo)
5624 dpll |= DPLL_DVO_HIGH_SPEED; 5615 dpll |= DPLL_DVO_HIGH_SPEED;
@@ -5650,7 +5641,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5650 else 5641 else
5651 dpll |= PLL_REF_INPUT_DREFCLK; 5642 dpll |= PLL_REF_INPUT_DREFCLK;
5652 5643
5653 return dpll; 5644 return dpll | DPLL_VCO_ENABLE;
5654} 5645}
5655 5646
5656static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5647static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
@@ -5660,9 +5651,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5660 struct drm_device *dev = crtc->dev; 5651 struct drm_device *dev = crtc->dev;
5661 struct drm_i915_private *dev_priv = dev->dev_private; 5652 struct drm_i915_private *dev_priv = dev->dev_private;
5662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5663 struct drm_display_mode *adjusted_mode =
5664 &intel_crtc->config.adjusted_mode;
5665 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5666 int pipe = intel_crtc->pipe; 5654 int pipe = intel_crtc->pipe;
5667 int plane = intel_crtc->plane; 5655 int plane = intel_crtc->plane;
5668 int num_connectors = 0; 5656 int num_connectors = 0;
@@ -5671,6 +5659,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5671 bool ok, has_reduced_clock = false; 5659 bool ok, has_reduced_clock = false;
5672 bool is_lvds = false; 5660 bool is_lvds = false;
5673 struct intel_encoder *encoder; 5661 struct intel_encoder *encoder;
5662 struct intel_shared_dpll *pll;
5674 int ret; 5663 int ret;
5675 5664
5676 for_each_encoder_on_crtc(dev, crtc, encoder) { 5665 for_each_encoder_on_crtc(dev, crtc, encoder) {
@@ -5686,9 +5675,9 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5686 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 5675 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5687 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 5676 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5688 5677
5689 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, 5678 ok = ironlake_compute_clocks(crtc, &clock,
5690 &has_reduced_clock, &reduced_clock); 5679 &has_reduced_clock, &reduced_clock);
5691 if (!ok) { 5680 if (!ok && !intel_crtc->config.clock_set) {
5692 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 5681 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5693 return -EINVAL; 5682 return -EINVAL;
5694 } 5683 }
@@ -5706,8 +5695,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5706 5695
5707 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5696 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5708 if (intel_crtc->config.has_pch_encoder) { 5697 if (intel_crtc->config.has_pch_encoder) {
5709 struct intel_pch_pll *pll;
5710
5711 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); 5698 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5712 if (has_reduced_clock) 5699 if (has_reduced_clock)
5713 fp2 = i9xx_dpll_compute_fp(&reduced_clock); 5700 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
@@ -5716,14 +5703,21 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5716 &fp, &reduced_clock, 5703 &fp, &reduced_clock,
5717 has_reduced_clock ? &fp2 : NULL); 5704 has_reduced_clock ? &fp2 : NULL);
5718 5705
5719 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5706 intel_crtc->config.dpll_hw_state.dpll = dpll;
5707 intel_crtc->config.dpll_hw_state.fp0 = fp;
5708 if (has_reduced_clock)
5709 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5710 else
5711 intel_crtc->config.dpll_hw_state.fp1 = fp;
5712
5713 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5720 if (pll == NULL) { 5714 if (pll == NULL) {
5721 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 5715 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5722 pipe_name(pipe)); 5716 pipe_name(pipe));
5723 return -EINVAL; 5717 return -EINVAL;
5724 } 5718 }
5725 } else 5719 } else
5726 intel_put_pch_pll(intel_crtc); 5720 intel_put_shared_dpll(intel_crtc);
5727 5721
5728 if (intel_crtc->config.has_dp_encoder) 5722 if (intel_crtc->config.has_dp_encoder)
5729 intel_dp_set_m_n(intel_crtc); 5723 intel_dp_set_m_n(intel_crtc);
@@ -5732,11 +5726,18 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5732 if (encoder->pre_pll_enable) 5726 if (encoder->pre_pll_enable)
5733 encoder->pre_pll_enable(encoder); 5727 encoder->pre_pll_enable(encoder);
5734 5728
5735 if (intel_crtc->pch_pll) { 5729 if (is_lvds && has_reduced_clock && i915_powersave)
5736 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5730 intel_crtc->lowfreq_avail = true;
5731 else
5732 intel_crtc->lowfreq_avail = false;
5733
5734 if (intel_crtc->config.has_pch_encoder) {
5735 pll = intel_crtc_to_shared_dpll(intel_crtc);
5736
5737 I915_WRITE(PCH_DPLL(pll->id), dpll);
5737 5738
5738 /* Wait for the clocks to stabilize. */ 5739 /* Wait for the clocks to stabilize. */
5739 POSTING_READ(intel_crtc->pch_pll->pll_reg); 5740 POSTING_READ(PCH_DPLL(pll->id));
5740 udelay(150); 5741 udelay(150);
5741 5742
5742 /* The pixel multiplier can only be updated once the 5743 /* The pixel multiplier can only be updated once the
@@ -5744,20 +5745,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5744 * 5745 *
5745 * So write it again. 5746 * So write it again.
5746 */ 5747 */
5747 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5748 I915_WRITE(PCH_DPLL(pll->id), dpll);
5748 }
5749 5749
5750 intel_crtc->lowfreq_avail = false; 5750 if (has_reduced_clock)
5751 if (intel_crtc->pch_pll) { 5751 I915_WRITE(PCH_FP1(pll->id), fp2);
5752 if (is_lvds && has_reduced_clock && i915_powersave) { 5752 else
5753 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); 5753 I915_WRITE(PCH_FP1(pll->id), fp);
5754 intel_crtc->lowfreq_avail = true;
5755 } else {
5756 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5757 }
5758 } 5754 }
5759 5755
5760 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5756 intel_set_pipe_timings(intel_crtc);
5761 5757
5762 if (intel_crtc->config.has_pch_encoder) { 5758 if (intel_crtc->config.has_pch_encoder) {
5763 intel_cpu_transcoder_set_m_n(intel_crtc, 5759 intel_cpu_transcoder_set_m_n(intel_crtc,
@@ -5808,6 +5804,14 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5808 if (tmp & PF_ENABLE) { 5804 if (tmp & PF_ENABLE) {
5809 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); 5805 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5810 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); 5806 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5807
5808 /* We currently do not free assignements of panel fitters on
5809 * ivb/hsw (since we don't use the higher upscaling modes which
5810 * differentiates them) so just WARN about this case for now. */
5811 if (IS_GEN7(dev)) {
5812 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5813 PF_PIPE_SEL_IVB(crtc->pipe));
5814 }
5811 } 5815 }
5812} 5816}
5813 5817
@@ -5819,12 +5823,15 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5819 uint32_t tmp; 5823 uint32_t tmp;
5820 5824
5821 pipe_config->cpu_transcoder = crtc->pipe; 5825 pipe_config->cpu_transcoder = crtc->pipe;
5826 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5822 5827
5823 tmp = I915_READ(PIPECONF(crtc->pipe)); 5828 tmp = I915_READ(PIPECONF(crtc->pipe));
5824 if (!(tmp & PIPECONF_ENABLE)) 5829 if (!(tmp & PIPECONF_ENABLE))
5825 return false; 5830 return false;
5826 5831
5827 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { 5832 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5833 struct intel_shared_dpll *pll;
5834
5828 pipe_config->has_pch_encoder = true; 5835 pipe_config->has_pch_encoder = true;
5829 5836
5830 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); 5837 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
@@ -5832,6 +5839,27 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5832 FDI_DP_PORT_WIDTH_SHIFT) + 1; 5839 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5833 5840
5834 ironlake_get_fdi_m_n_config(crtc, pipe_config); 5841 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5842
5843 /* XXX: Can't properly read out the pch dpll pixel multiplier
5844 * since we don't have state tracking for pch clocks yet. */
5845 pipe_config->pixel_multiplier = 1;
5846
5847 if (HAS_PCH_IBX(dev_priv->dev)) {
5848 pipe_config->shared_dpll = crtc->pipe;
5849 } else {
5850 tmp = I915_READ(PCH_DPLL_SEL);
5851 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5852 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5853 else
5854 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5855 }
5856
5857 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5858
5859 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5860 &pipe_config->dpll_hw_state));
5861 } else {
5862 pipe_config->pixel_multiplier = 1;
5835 } 5863 }
5836 5864
5837 intel_get_pipe_timings(crtc, pipe_config); 5865 intel_get_pipe_timings(crtc, pipe_config);
@@ -5865,31 +5893,10 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5865 struct drm_device *dev = crtc->dev; 5893 struct drm_device *dev = crtc->dev;
5866 struct drm_i915_private *dev_priv = dev->dev_private; 5894 struct drm_i915_private *dev_priv = dev->dev_private;
5867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5868 struct drm_display_mode *adjusted_mode =
5869 &intel_crtc->config.adjusted_mode;
5870 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5871 int pipe = intel_crtc->pipe;
5872 int plane = intel_crtc->plane; 5896 int plane = intel_crtc->plane;
5873 int num_connectors = 0;
5874 bool is_cpu_edp = false;
5875 struct intel_encoder *encoder;
5876 int ret; 5897 int ret;
5877 5898
5878 for_each_encoder_on_crtc(dev, crtc, encoder) { 5899 if (!intel_ddi_pll_mode_set(crtc))
5879 switch (encoder->type) {
5880 case INTEL_OUTPUT_EDP:
5881 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5882 is_cpu_edp = true;
5883 break;
5884 }
5885
5886 num_connectors++;
5887 }
5888
5889 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5890 num_connectors, pipe_name(pipe));
5891
5892 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5893 return -EINVAL; 5900 return -EINVAL;
5894 5901
5895 /* Ensure that the cursor is valid for the new mode before changing... */ 5902 /* Ensure that the cursor is valid for the new mode before changing... */
@@ -5900,7 +5907,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5900 5907
5901 intel_crtc->lowfreq_avail = false; 5908 intel_crtc->lowfreq_avail = false;
5902 5909
5903 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5910 intel_set_pipe_timings(intel_crtc);
5904 5911
5905 if (intel_crtc->config.has_pch_encoder) { 5912 if (intel_crtc->config.has_pch_encoder) {
5906 intel_cpu_transcoder_set_m_n(intel_crtc, 5913 intel_cpu_transcoder_set_m_n(intel_crtc,
@@ -5931,6 +5938,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5931 uint32_t tmp; 5938 uint32_t tmp;
5932 5939
5933 pipe_config->cpu_transcoder = crtc->pipe; 5940 pipe_config->cpu_transcoder = crtc->pipe;
5941 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5942
5934 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 5943 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5935 if (tmp & TRANS_DDI_FUNC_ENABLE) { 5944 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5936 enum pipe trans_edp_pipe; 5945 enum pipe trans_edp_pipe;
@@ -5987,6 +5996,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5987 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && 5996 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5988 (I915_READ(IPS_CTL) & IPS_ENABLE); 5997 (I915_READ(IPS_CTL) & IPS_ENABLE);
5989 5998
5999 pipe_config->pixel_multiplier = 1;
6000
5990 return true; 6001 return true;
5991} 6002}
5992 6003
@@ -6300,6 +6311,9 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
6300 if (!crtc->enabled || !intel_crtc->active) 6311 if (!crtc->enabled || !intel_crtc->active)
6301 return; 6312 return;
6302 6313
6314 if (!HAS_PCH_SPLIT(dev_priv->dev))
6315 assert_pll_enabled(dev_priv, pipe);
6316
6303 /* use legacy palette for Ironlake */ 6317 /* use legacy palette for Ironlake */
6304 if (HAS_PCH_SPLIT(dev)) 6318 if (HAS_PCH_SPLIT(dev))
6305 palreg = LGC_PALETTE(pipe); 6319 palreg = LGC_PALETTE(pipe);
@@ -6909,8 +6923,10 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6909 return 0; 6923 return 0;
6910 } 6924 }
6911 6925
6912 /* XXX: Handle the 100Mhz refclk */ 6926 if (IS_PINEVIEW(dev))
6913 intel_clock(dev, 96000, &clock); 6927 pineview_clock(96000, &clock);
6928 else
6929 i9xx_clock(96000, &clock);
6914 } else { 6930 } else {
6915 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 6931 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6916 6932
@@ -6922,9 +6938,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6922 if ((dpll & PLL_REF_INPUT_MASK) == 6938 if ((dpll & PLL_REF_INPUT_MASK) ==
6923 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 6939 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6924 /* XXX: might not be 66MHz */ 6940 /* XXX: might not be 66MHz */
6925 intel_clock(dev, 66000, &clock); 6941 i9xx_clock(66000, &clock);
6926 } else 6942 } else
6927 intel_clock(dev, 48000, &clock); 6943 i9xx_clock(48000, &clock);
6928 } else { 6944 } else {
6929 if (dpll & PLL_P1_DIVIDE_BY_TWO) 6945 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6930 clock.p1 = 2; 6946 clock.p1 = 2;
@@ -6937,7 +6953,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6937 else 6953 else
6938 clock.p2 = 2; 6954 clock.p2 = 2;
6939 6955
6940 intel_clock(dev, 48000, &clock); 6956 i9xx_clock(48000, &clock);
6941 } 6957 }
6942 } 6958 }
6943 6959
@@ -7068,7 +7084,8 @@ void intel_mark_idle(struct drm_device *dev)
7068 } 7084 }
7069} 7085}
7070 7086
7071void intel_mark_fb_busy(struct drm_i915_gem_object *obj) 7087void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7088 struct intel_ring_buffer *ring)
7072{ 7089{
7073 struct drm_device *dev = obj->base.dev; 7090 struct drm_device *dev = obj->base.dev;
7074 struct drm_crtc *crtc; 7091 struct drm_crtc *crtc;
@@ -7080,8 +7097,12 @@ void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7080 if (!crtc->fb) 7097 if (!crtc->fb)
7081 continue; 7098 continue;
7082 7099
7083 if (to_intel_framebuffer(crtc->fb)->obj == obj) 7100 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7084 intel_increase_pllclock(crtc); 7101 continue;
7102
7103 intel_increase_pllclock(crtc);
7104 if (ring && intel_fbc_enabled(dev))
7105 ring->fbc_dirty = true;
7085 } 7106 }
7086} 7107}
7087 7108
@@ -7531,7 +7552,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
7531 goto cleanup_pending; 7552 goto cleanup_pending;
7532 7553
7533 intel_disable_fbc(dev); 7554 intel_disable_fbc(dev);
7534 intel_mark_fb_busy(obj); 7555 intel_mark_fb_busy(obj, NULL);
7535 mutex_unlock(&dev->struct_mutex); 7556 mutex_unlock(&dev->struct_mutex);
7536 7557
7537 trace_i915_flip_request(intel_crtc->plane, obj); 7558 trace_i915_flip_request(intel_crtc->plane, obj);
@@ -7562,28 +7583,6 @@ static struct drm_crtc_helper_funcs intel_helper_funcs = {
7562 .load_lut = intel_crtc_load_lut, 7583 .load_lut = intel_crtc_load_lut,
7563}; 7584};
7564 7585
7565bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7566{
7567 struct intel_encoder *other_encoder;
7568 struct drm_crtc *crtc = &encoder->new_crtc->base;
7569
7570 if (WARN_ON(!crtc))
7571 return false;
7572
7573 list_for_each_entry(other_encoder,
7574 &crtc->dev->mode_config.encoder_list,
7575 base.head) {
7576
7577 if (&other_encoder->new_crtc->base != crtc ||
7578 encoder == other_encoder)
7579 continue;
7580 else
7581 return true;
7582 }
7583
7584 return false;
7585}
7586
7587static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, 7586static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588 struct drm_crtc *crtc) 7587 struct drm_crtc *crtc)
7589{ 7588{
@@ -7651,13 +7650,39 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
7651 } 7650 }
7652} 7651}
7653 7652
7653static void
7654connected_sink_compute_bpp(struct intel_connector * connector,
7655 struct intel_crtc_config *pipe_config)
7656{
7657 int bpp = pipe_config->pipe_bpp;
7658
7659 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7660 connector->base.base.id,
7661 drm_get_connector_name(&connector->base));
7662
7663 /* Don't use an invalid EDID bpc value */
7664 if (connector->base.display_info.bpc &&
7665 connector->base.display_info.bpc * 3 < bpp) {
7666 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7667 bpp, connector->base.display_info.bpc*3);
7668 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7669 }
7670
7671 /* Clamp bpp to 8 on screens without EDID 1.4 */
7672 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7673 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7674 bpp);
7675 pipe_config->pipe_bpp = 24;
7676 }
7677}
7678
7654static int 7679static int
7655pipe_config_set_bpp(struct drm_crtc *crtc, 7680compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7656 struct drm_framebuffer *fb, 7681 struct drm_framebuffer *fb,
7657 struct intel_crtc_config *pipe_config) 7682 struct intel_crtc_config *pipe_config)
7658{ 7683{
7659 struct drm_device *dev = crtc->dev; 7684 struct drm_device *dev = crtc->base.dev;
7660 struct drm_connector *connector; 7685 struct intel_connector *connector;
7661 int bpp; 7686 int bpp;
7662 7687
7663 switch (fb->pixel_format) { 7688 switch (fb->pixel_format) {
@@ -7700,24 +7725,12 @@ pipe_config_set_bpp(struct drm_crtc *crtc,
7700 7725
7701 /* Clamp display bpp to EDID value */ 7726 /* Clamp display bpp to EDID value */
7702 list_for_each_entry(connector, &dev->mode_config.connector_list, 7727 list_for_each_entry(connector, &dev->mode_config.connector_list,
7703 head) { 7728 base.head) {
7704 if (connector->encoder && connector->encoder->crtc != crtc) 7729 if (!connector->new_encoder ||
7730 connector->new_encoder->new_crtc != crtc)
7705 continue; 7731 continue;
7706 7732
7707 /* Don't use an invalid EDID bpc value */ 7733 connected_sink_compute_bpp(connector, pipe_config);
7708 if (connector->display_info.bpc &&
7709 connector->display_info.bpc * 3 < bpp) {
7710 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7711 bpp, connector->display_info.bpc*3);
7712 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7713 }
7714
7715 /* Clamp bpp to 8 on screens without EDID 1.4 */
7716 if (connector->display_info.bpc == 0 && bpp > 24) {
7717 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7718 bpp);
7719 pipe_config->pipe_bpp = 24;
7720 }
7721 } 7734 }
7722 7735
7723 return bpp; 7736 return bpp;
@@ -7753,6 +7766,25 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
7753 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); 7766 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7754} 7767}
7755 7768
7769static bool check_encoder_cloning(struct drm_crtc *crtc)
7770{
7771 int num_encoders = 0;
7772 bool uncloneable_encoders = false;
7773 struct intel_encoder *encoder;
7774
7775 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7776 base.head) {
7777 if (&encoder->new_crtc->base != crtc)
7778 continue;
7779
7780 num_encoders++;
7781 if (!encoder->cloneable)
7782 uncloneable_encoders = true;
7783 }
7784
7785 return !(num_encoders > 1 && uncloneable_encoders);
7786}
7787
7756static struct intel_crtc_config * 7788static struct intel_crtc_config *
7757intel_modeset_pipe_config(struct drm_crtc *crtc, 7789intel_modeset_pipe_config(struct drm_crtc *crtc,
7758 struct drm_framebuffer *fb, 7790 struct drm_framebuffer *fb,
@@ -7765,6 +7797,11 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7765 int plane_bpp, ret = -EINVAL; 7797 int plane_bpp, ret = -EINVAL;
7766 bool retry = true; 7798 bool retry = true;
7767 7799
7800 if (!check_encoder_cloning(crtc)) {
7801 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7802 return ERR_PTR(-EINVAL);
7803 }
7804
7768 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); 7805 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7769 if (!pipe_config) 7806 if (!pipe_config)
7770 return ERR_PTR(-ENOMEM); 7807 return ERR_PTR(-ENOMEM);
@@ -7772,12 +7809,22 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
7772 drm_mode_copy(&pipe_config->adjusted_mode, mode); 7809 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7773 drm_mode_copy(&pipe_config->requested_mode, mode); 7810 drm_mode_copy(&pipe_config->requested_mode, mode);
7774 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe; 7811 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7775 7812 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7776 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); 7813
7814 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7815 * plane pixel format and any sink constraints into account. Returns the
7816 * source plane bpp so that dithering can be selected on mismatches
7817 * after encoders and crtc also have had their say. */
7818 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7819 fb, pipe_config);
7777 if (plane_bpp < 0) 7820 if (plane_bpp < 0)
7778 goto fail; 7821 goto fail;
7779 7822
7780encoder_retry: 7823encoder_retry:
7824 /* Ensure the port clock defaults are reset when retrying. */
7825 pipe_config->port_clock = 0;
7826 pipe_config->pixel_multiplier = 1;
7827
7781 /* Pass our mode to the connectors and the CRTC to give them a chance to 7828 /* Pass our mode to the connectors and the CRTC to give them a chance to
7782 * adjust it according to limitations or connector properties, and also 7829 * adjust it according to limitations or connector properties, and also
7783 * a chance to reject the mode entirely. 7830 * a chance to reject the mode entirely.
@@ -7806,7 +7853,12 @@ encoder_retry:
7806 } 7853 }
7807 } 7854 }
7808 7855
7809 ret = intel_crtc_compute_config(crtc, pipe_config); 7856 /* Set default port clock if not overwritten by the encoder. Needs to be
7857 * done afterwards in case the encoder adjusts the mode. */
7858 if (!pipe_config->port_clock)
7859 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7860
7861 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7810 if (ret < 0) { 7862 if (ret < 0) {
7811 DRM_DEBUG_KMS("CRTC fixup failed\n"); 7863 DRM_DEBUG_KMS("CRTC fixup failed\n");
7812 goto fail; 7864 goto fail;
@@ -8002,6 +8054,15 @@ intel_pipe_config_compare(struct drm_device *dev,
8002 struct intel_crtc_config *current_config, 8054 struct intel_crtc_config *current_config,
8003 struct intel_crtc_config *pipe_config) 8055 struct intel_crtc_config *pipe_config)
8004{ 8056{
8057#define PIPE_CONF_CHECK_X(name) \
8058 if (current_config->name != pipe_config->name) { \
8059 DRM_ERROR("mismatch in " #name " " \
8060 "(expected 0x%08x, found 0x%08x)\n", \
8061 current_config->name, \
8062 pipe_config->name); \
8063 return false; \
8064 }
8065
8005#define PIPE_CONF_CHECK_I(name) \ 8066#define PIPE_CONF_CHECK_I(name) \
8006 if (current_config->name != pipe_config->name) { \ 8067 if (current_config->name != pipe_config->name) { \
8007 DRM_ERROR("mismatch in " #name " " \ 8068 DRM_ERROR("mismatch in " #name " " \
@@ -8020,6 +8081,9 @@ intel_pipe_config_compare(struct drm_device *dev,
8020 return false; \ 8081 return false; \
8021 } 8082 }
8022 8083
8084#define PIPE_CONF_QUIRK(quirk) \
8085 ((current_config->quirks | pipe_config->quirks) & (quirk))
8086
8023 PIPE_CONF_CHECK_I(cpu_transcoder); 8087 PIPE_CONF_CHECK_I(cpu_transcoder);
8024 8088
8025 PIPE_CONF_CHECK_I(has_pch_encoder); 8089 PIPE_CONF_CHECK_I(has_pch_encoder);
@@ -8044,17 +8108,22 @@ intel_pipe_config_compare(struct drm_device *dev,
8044 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); 8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8045 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); 8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8046 8110
8111 if (!HAS_PCH_SPLIT(dev))
8112 PIPE_CONF_CHECK_I(pixel_multiplier);
8113
8047 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 8114 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8048 DRM_MODE_FLAG_INTERLACE); 8115 DRM_MODE_FLAG_INTERLACE);
8049 8116
8050 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 8117 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8051 DRM_MODE_FLAG_PHSYNC); 8118 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8052 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 8119 DRM_MODE_FLAG_PHSYNC);
8053 DRM_MODE_FLAG_NHSYNC); 8120 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8054 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 8121 DRM_MODE_FLAG_NHSYNC);
8055 DRM_MODE_FLAG_PVSYNC); 8122 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8056 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 8123 DRM_MODE_FLAG_PVSYNC);
8057 DRM_MODE_FLAG_NVSYNC); 8124 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8125 DRM_MODE_FLAG_NVSYNC);
8126 }
8058 8127
8059 PIPE_CONF_CHECK_I(requested_mode.hdisplay); 8128 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8060 PIPE_CONF_CHECK_I(requested_mode.vdisplay); 8129 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
@@ -8069,20 +8138,23 @@ intel_pipe_config_compare(struct drm_device *dev,
8069 8138
8070 PIPE_CONF_CHECK_I(ips_enabled); 8139 PIPE_CONF_CHECK_I(ips_enabled);
8071 8140
8141 PIPE_CONF_CHECK_I(shared_dpll);
8142 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8143 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8144 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8145
8146#undef PIPE_CONF_CHECK_X
8072#undef PIPE_CONF_CHECK_I 8147#undef PIPE_CONF_CHECK_I
8073#undef PIPE_CONF_CHECK_FLAGS 8148#undef PIPE_CONF_CHECK_FLAGS
8149#undef PIPE_CONF_QUIRK
8074 8150
8075 return true; 8151 return true;
8076} 8152}
8077 8153
8078void 8154static void
8079intel_modeset_check_state(struct drm_device *dev) 8155check_connector_state(struct drm_device *dev)
8080{ 8156{
8081 drm_i915_private_t *dev_priv = dev->dev_private;
8082 struct intel_crtc *crtc;
8083 struct intel_encoder *encoder;
8084 struct intel_connector *connector; 8157 struct intel_connector *connector;
8085 struct intel_crtc_config pipe_config;
8086 8158
8087 list_for_each_entry(connector, &dev->mode_config.connector_list, 8159 list_for_each_entry(connector, &dev->mode_config.connector_list,
8088 base.head) { 8160 base.head) {
@@ -8093,6 +8165,13 @@ intel_modeset_check_state(struct drm_device *dev)
8093 WARN(&connector->new_encoder->base != connector->base.encoder, 8165 WARN(&connector->new_encoder->base != connector->base.encoder,
8094 "connector's staged encoder doesn't match current encoder\n"); 8166 "connector's staged encoder doesn't match current encoder\n");
8095 } 8167 }
8168}
8169
8170static void
8171check_encoder_state(struct drm_device *dev)
8172{
8173 struct intel_encoder *encoder;
8174 struct intel_connector *connector;
8096 8175
8097 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 8176 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8098 base.head) { 8177 base.head) {
@@ -8144,6 +8223,15 @@ intel_modeset_check_state(struct drm_device *dev)
8144 tracked_pipe, pipe); 8223 tracked_pipe, pipe);
8145 8224
8146 } 8225 }
8226}
8227
8228static void
8229check_crtc_state(struct drm_device *dev)
8230{
8231 drm_i915_private_t *dev_priv = dev->dev_private;
8232 struct intel_crtc *crtc;
8233 struct intel_encoder *encoder;
8234 struct intel_crtc_config pipe_config;
8147 8235
8148 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 8236 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8149 base.head) { 8237 base.head) {
@@ -8165,9 +8253,8 @@ intel_modeset_check_state(struct drm_device *dev)
8165 enabled = true; 8253 enabled = true;
8166 if (encoder->connectors_active) 8254 if (encoder->connectors_active)
8167 active = true; 8255 active = true;
8168 if (encoder->get_config)
8169 encoder->get_config(encoder, &pipe_config);
8170 } 8256 }
8257
8171 WARN(active != crtc->active, 8258 WARN(active != crtc->active,
8172 "crtc's computed active state doesn't match tracked active state " 8259 "crtc's computed active state doesn't match tracked active state "
8173 "(expected %i, found %i)\n", active, crtc->active); 8260 "(expected %i, found %i)\n", active, crtc->active);
@@ -8182,6 +8269,14 @@ intel_modeset_check_state(struct drm_device *dev)
8182 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 8269 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8183 active = crtc->active; 8270 active = crtc->active;
8184 8271
8272 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8273 base.head) {
8274 if (encoder->base.crtc != &crtc->base)
8275 continue;
8276 if (encoder->get_config)
8277 encoder->get_config(encoder, &pipe_config);
8278 }
8279
8185 WARN(crtc->active != active, 8280 WARN(crtc->active != active,
8186 "crtc active state doesn't match with hw state " 8281 "crtc active state doesn't match with hw state "
8187 "(expected %i, found %i)\n", crtc->active, active); 8282 "(expected %i, found %i)\n", crtc->active, active);
@@ -8197,6 +8292,63 @@ intel_modeset_check_state(struct drm_device *dev)
8197 } 8292 }
8198} 8293}
8199 8294
8295static void
8296check_shared_dpll_state(struct drm_device *dev)
8297{
8298 drm_i915_private_t *dev_priv = dev->dev_private;
8299 struct intel_crtc *crtc;
8300 struct intel_dpll_hw_state dpll_hw_state;
8301 int i;
8302
8303 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8304 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8305 int enabled_crtcs = 0, active_crtcs = 0;
8306 bool active;
8307
8308 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8309
8310 DRM_DEBUG_KMS("%s\n", pll->name);
8311
8312 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8313
8314 WARN(pll->active > pll->refcount,
8315 "more active pll users than references: %i vs %i\n",
8316 pll->active, pll->refcount);
8317 WARN(pll->active && !pll->on,
8318 "pll in active use but not on in sw tracking\n");
8319 WARN(pll->on != active,
8320 "pll on state mismatch (expected %i, found %i)\n",
8321 pll->on, active);
8322
8323 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8324 base.head) {
8325 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8326 enabled_crtcs++;
8327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8328 active_crtcs++;
8329 }
8330 WARN(pll->active != active_crtcs,
8331 "pll active crtcs mismatch (expected %i, found %i)\n",
8332 pll->active, active_crtcs);
8333 WARN(pll->refcount != enabled_crtcs,
8334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8335 pll->refcount, enabled_crtcs);
8336
8337 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8338 sizeof(dpll_hw_state)),
8339 "pll hw state mismatch\n");
8340 }
8341}
8342
8343void
8344intel_modeset_check_state(struct drm_device *dev)
8345{
8346 check_connector_state(dev);
8347 check_encoder_state(dev);
8348 check_crtc_state(dev);
8349 check_shared_dpll_state(dev);
8350}
8351
8200static int __intel_set_mode(struct drm_crtc *crtc, 8352static int __intel_set_mode(struct drm_crtc *crtc,
8201 struct drm_display_mode *mode, 8353 struct drm_display_mode *mode,
8202 int x, int y, struct drm_framebuffer *fb) 8354 int x, int y, struct drm_framebuffer *fb)
@@ -8633,23 +8785,93 @@ static void intel_cpu_pll_init(struct drm_device *dev)
8633 intel_ddi_pll_init(dev); 8785 intel_ddi_pll_init(dev);
8634} 8786}
8635 8787
8636static void intel_pch_pll_init(struct drm_device *dev) 8788static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8789 struct intel_shared_dpll *pll,
8790 struct intel_dpll_hw_state *hw_state)
8637{ 8791{
8638 drm_i915_private_t *dev_priv = dev->dev_private; 8792 uint32_t val;
8639 int i;
8640 8793
8641 if (dev_priv->num_pch_pll == 0) { 8794 val = I915_READ(PCH_DPLL(pll->id));
8642 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 8795 hw_state->dpll = val;
8643 return; 8796 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8797 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8798
8799 return val & DPLL_VCO_ENABLE;
8800}
8801
8802static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8803 struct intel_shared_dpll *pll)
8804{
8805 uint32_t reg, val;
8806
8807 /* PCH refclock must be enabled first */
8808 assert_pch_refclk_enabled(dev_priv);
8809
8810 reg = PCH_DPLL(pll->id);
8811 val = I915_READ(reg);
8812 val |= DPLL_VCO_ENABLE;
8813 I915_WRITE(reg, val);
8814 POSTING_READ(reg);
8815 udelay(200);
8816}
8817
8818static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8819 struct intel_shared_dpll *pll)
8820{
8821 struct drm_device *dev = dev_priv->dev;
8822 struct intel_crtc *crtc;
8823 uint32_t reg, val;
8824
8825 /* Make sure no transcoder isn't still depending on us. */
8826 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8827 if (intel_crtc_to_shared_dpll(crtc) == pll)
8828 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8644 } 8829 }
8645 8830
8646 for (i = 0; i < dev_priv->num_pch_pll; i++) { 8831 reg = PCH_DPLL(pll->id);
8647 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 8832 val = I915_READ(reg);
8648 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 8833 val &= ~DPLL_VCO_ENABLE;
8649 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 8834 I915_WRITE(reg, val);
8835 POSTING_READ(reg);
8836 udelay(200);
8837}
8838
8839static char *ibx_pch_dpll_names[] = {
8840 "PCH DPLL A",
8841 "PCH DPLL B",
8842};
8843
8844static void ibx_pch_dpll_init(struct drm_device *dev)
8845{
8846 struct drm_i915_private *dev_priv = dev->dev_private;
8847 int i;
8848
8849 dev_priv->num_shared_dpll = 2;
8850
8851 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8852 dev_priv->shared_dplls[i].id = i;
8853 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8854 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8855 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8856 dev_priv->shared_dplls[i].get_hw_state =
8857 ibx_pch_dpll_get_hw_state;
8650 } 8858 }
8651} 8859}
8652 8860
8861static void intel_shared_dpll_init(struct drm_device *dev)
8862{
8863 struct drm_i915_private *dev_priv = dev->dev_private;
8864
8865 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8866 ibx_pch_dpll_init(dev);
8867 else
8868 dev_priv->num_shared_dpll = 0;
8869
8870 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8871 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8872 dev_priv->num_shared_dpll);
8873}
8874
8653static void intel_crtc_init(struct drm_device *dev, int pipe) 8875static void intel_crtc_init(struct drm_device *dev, int pipe)
8654{ 8876{
8655 drm_i915_private_t *dev_priv = dev->dev_private; 8877 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -8754,13 +8976,8 @@ static void intel_setup_outputs(struct drm_device *dev)
8754 struct drm_i915_private *dev_priv = dev->dev_private; 8976 struct drm_i915_private *dev_priv = dev->dev_private;
8755 struct intel_encoder *encoder; 8977 struct intel_encoder *encoder;
8756 bool dpd_is_edp = false; 8978 bool dpd_is_edp = false;
8757 bool has_lvds;
8758 8979
8759 has_lvds = intel_lvds_init(dev); 8980 intel_lvds_init(dev);
8760 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8761 /* disable the panel fitter on everything but LVDS */
8762 I915_WRITE(PFIT_CONTROL, 0);
8763 }
8764 8981
8765 if (!IS_ULT(dev)) 8982 if (!IS_ULT(dev))
8766 intel_crt_init(dev); 8983 intel_crt_init(dev);
@@ -9015,6 +9232,15 @@ static void intel_init_display(struct drm_device *dev)
9015{ 9232{
9016 struct drm_i915_private *dev_priv = dev->dev_private; 9233 struct drm_i915_private *dev_priv = dev->dev_private;
9017 9234
9235 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9236 dev_priv->display.find_dpll = g4x_find_best_dpll;
9237 else if (IS_VALLEYVIEW(dev))
9238 dev_priv->display.find_dpll = vlv_find_best_dpll;
9239 else if (IS_PINEVIEW(dev))
9240 dev_priv->display.find_dpll = pnv_find_best_dpll;
9241 else
9242 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9243
9018 if (HAS_DDI(dev)) { 9244 if (HAS_DDI(dev)) {
9019 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 9245 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9020 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; 9246 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
@@ -9333,7 +9559,7 @@ void intel_modeset_init(struct drm_device *dev)
9333 } 9559 }
9334 9560
9335 intel_cpu_pll_init(dev); 9561 intel_cpu_pll_init(dev);
9336 intel_pch_pll_init(dev); 9562 intel_shared_dpll_init(dev);
9337 9563
9338 /* Just disable it once at startup */ 9564 /* Just disable it once at startup */
9339 i915_disable_vga(dev); 9565 i915_disable_vga(dev);
@@ -9534,17 +9760,14 @@ void i915_redisable_vga(struct drm_device *dev)
9534 } 9760 }
9535} 9761}
9536 9762
9537/* Scan out the current hw modeset state, sanitizes it and maps it into the drm 9763static void intel_modeset_readout_hw_state(struct drm_device *dev)
9538 * and i915 state tracking structures. */
9539void intel_modeset_setup_hw_state(struct drm_device *dev,
9540 bool force_restore)
9541{ 9764{
9542 struct drm_i915_private *dev_priv = dev->dev_private; 9765 struct drm_i915_private *dev_priv = dev->dev_private;
9543 enum pipe pipe; 9766 enum pipe pipe;
9544 struct drm_plane *plane;
9545 struct intel_crtc *crtc; 9767 struct intel_crtc *crtc;
9546 struct intel_encoder *encoder; 9768 struct intel_encoder *encoder;
9547 struct intel_connector *connector; 9769 struct intel_connector *connector;
9770 int i;
9548 9771
9549 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 9772 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9550 base.head) { 9773 base.head) {
@@ -9560,9 +9783,26 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9560 crtc->active ? "enabled" : "disabled"); 9783 crtc->active ? "enabled" : "disabled");
9561 } 9784 }
9562 9785
9786 /* FIXME: Smash this into the new shared dpll infrastructure. */
9563 if (HAS_DDI(dev)) 9787 if (HAS_DDI(dev))
9564 intel_ddi_setup_hw_pll_state(dev); 9788 intel_ddi_setup_hw_pll_state(dev);
9565 9789
9790 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9791 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9792
9793 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9794 pll->active = 0;
9795 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9796 base.head) {
9797 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9798 pll->active++;
9799 }
9800 pll->refcount = pll->active;
9801
9802 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9803 pll->name, pll->refcount);
9804 }
9805
9566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9806 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9567 base.head) { 9807 base.head) {
9568 pipe = 0; 9808 pipe = 0;
@@ -9599,6 +9839,20 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
9599 drm_get_connector_name(&connector->base), 9839 drm_get_connector_name(&connector->base),
9600 connector->base.encoder ? "enabled" : "disabled"); 9840 connector->base.encoder ? "enabled" : "disabled");
9601 } 9841 }
9842}
9843
9844/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9845 * and i915 state tracking structures. */
9846void intel_modeset_setup_hw_state(struct drm_device *dev,
9847 bool force_restore)
9848{
9849 struct drm_i915_private *dev_priv = dev->dev_private;
9850 enum pipe pipe;
9851 struct drm_plane *plane;
9852 struct intel_crtc *crtc;
9853 struct intel_encoder *encoder;
9854
9855 intel_modeset_readout_hw_state(dev);
9602 9856
9603 /* HW state is read out, now we need to sanitize this mess. */ 9857 /* HW state is read out, now we need to sanitize this mess. */
9604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9858 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91a31b3b9829..98686005dcf6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -677,7 +677,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
678 int bpp, mode_rate; 678 int bpp, mode_rate;
679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
680 int target_clock, link_avail, link_clock; 680 int link_avail, link_clock;
681 681
682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
683 pipe_config->has_pch_encoder = true; 683 pipe_config->has_pch_encoder = true;
@@ -694,8 +694,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
694 intel_pch_panel_fitting(intel_crtc, pipe_config, 694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode); 695 intel_connector->panel.fitting_mode);
696 } 696 }
697 /* We need to take the panel's fixed mode into account. */
698 target_clock = adjusted_mode->clock;
699 697
700 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 698 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
701 return false; 699 return false;
@@ -706,12 +704,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
706 704
707 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 705 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
708 * bpc in between. */ 706 * bpc in between. */
709 bpp = min_t(int, 8*3, pipe_config->pipe_bpp); 707 bpp = pipe_config->pipe_bpp;
710 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) 708 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
711 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp); 709 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
712 710
713 for (; bpp >= 6*3; bpp -= 2*3) { 711 for (; bpp >= 6*3; bpp -= 2*3) {
714 mode_rate = intel_dp_link_required(target_clock, bpp); 712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
715 713
716 for (clock = 0; clock <= max_clock; clock++) { 714 for (clock = 0; clock <= max_clock; clock++) {
717 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
@@ -746,18 +744,17 @@ found:
746 744
747 intel_dp->link_bw = bws[clock]; 745 intel_dp->link_bw = bws[clock];
748 intel_dp->lane_count = lane_count; 746 intel_dp->lane_count = lane_count;
749 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
750 pipe_config->pipe_bpp = bpp; 747 pipe_config->pipe_bpp = bpp;
751 pipe_config->pixel_target_clock = target_clock; 748 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
752 749
753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 750 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp->link_bw, intel_dp->lane_count, 751 intel_dp->link_bw, intel_dp->lane_count,
755 adjusted_mode->clock, bpp); 752 pipe_config->port_clock, bpp);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 753 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate, link_avail); 754 mode_rate, link_avail);
758 755
759 intel_link_compute_m_n(bpp, lane_count, 756 intel_link_compute_m_n(bpp, lane_count,
760 target_clock, adjusted_mode->clock, 757 adjusted_mode->clock, pipe_config->port_clock,
761 &pipe_config->dp_m_n); 758 &pipe_config->dp_m_n);
762 759
763 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 760 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
@@ -780,24 +777,28 @@ void intel_dp_init_link_config(struct intel_dp *intel_dp)
780 } 777 }
781} 778}
782 779
783static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 780static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
784{ 781{
785 struct drm_device *dev = crtc->dev; 782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
783 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
784 struct drm_device *dev = crtc->base.dev;
786 struct drm_i915_private *dev_priv = dev->dev_private; 785 struct drm_i915_private *dev_priv = dev->dev_private;
787 u32 dpa_ctl; 786 u32 dpa_ctl;
788 787
789 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); 788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
790 dpa_ctl = I915_READ(DP_A); 789 dpa_ctl = I915_READ(DP_A);
791 dpa_ctl &= ~DP_PLL_FREQ_MASK; 790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
792 791
793 if (clock < 200000) { 792 if (crtc->config.port_clock == 162000) {
794 /* For a long time we've carried around a ILK-DevA w/a for the 793 /* For a long time we've carried around a ILK-DevA w/a for the
795 * 160MHz clock. If we're really unlucky, it's still required. 794 * 160MHz clock. If we're really unlucky, it's still required.
796 */ 795 */
797 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
798 dpa_ctl |= DP_PLL_FREQ_160MHZ; 797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
798 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
799 } else { 799 } else {
800 dpa_ctl |= DP_PLL_FREQ_270MHZ; 800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
801 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
801 } 802 }
802 803
803 I915_WRITE(DP_A, dpa_ctl); 804 I915_WRITE(DP_A, dpa_ctl);
@@ -814,8 +815,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
814 struct drm_i915_private *dev_priv = dev->dev_private; 815 struct drm_i915_private *dev_priv = dev->dev_private;
815 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
816 enum port port = dp_to_dig_port(intel_dp)->port; 817 enum port port = dp_to_dig_port(intel_dp)->port;
817 struct drm_crtc *crtc = encoder->crtc; 818 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
819 819
820 /* 820 /*
821 * There are four kinds of DP registers: 821 * There are four kinds of DP registers:
@@ -845,7 +845,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
845 845
846 if (intel_dp->has_audio) { 846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
848 pipe_name(intel_crtc->pipe)); 848 pipe_name(crtc->pipe));
849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
850 intel_write_eld(encoder, adjusted_mode); 850 intel_write_eld(encoder, adjusted_mode);
851 } 851 }
@@ -864,13 +864,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING; 865 intel_dp->DP |= DP_ENHANCED_FRAMING;
866 866
867 intel_dp->DP |= intel_crtc->pipe << 29; 867 intel_dp->DP |= crtc->pipe << 29;
868
869 /* don't miss out required setting for eDP */
870 if (adjusted_mode->clock < 200000)
871 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
872 else
873 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
874 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
875 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 869 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
876 intel_dp->DP |= intel_dp->color_range; 870 intel_dp->DP |= intel_dp->color_range;
@@ -884,22 +878,14 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING; 879 intel_dp->DP |= DP_ENHANCED_FRAMING;
886 880
887 if (intel_crtc->pipe == 1) 881 if (crtc->pipe == 1)
888 intel_dp->DP |= DP_PIPEB_SELECT; 882 intel_dp->DP |= DP_PIPEB_SELECT;
889
890 if (port == PORT_A && !IS_VALLEYVIEW(dev)) {
891 /* don't miss out required setting for eDP */
892 if (adjusted_mode->clock < 200000)
893 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
894 else
895 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
896 }
897 } else { 883 } else {
898 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 884 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
899 } 885 }
900 886
901 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 887 if (port == PORT_A && !IS_VALLEYVIEW(dev))
902 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 888 ironlake_set_pll_cpu_edp(intel_dp);
903} 889}
904 890
905#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 891#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fdf6303be0a9..ffe9d35b37b4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,7 +140,8 @@ struct intel_encoder {
140 * it is connected to in the pipe parameter. */ 140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
142 /* Reconstructs the equivalent mode flags for the current hardware 142 /* Reconstructs the equivalent mode flags for the current hardware
143 * state. */ 143 * state. This must be called _after_ display->get_pipe_config has
144 * pre-filled the pipe config. */
144 void (*get_config)(struct intel_encoder *, 145 void (*get_config)(struct intel_encoder *,
145 struct intel_crtc_config *pipe_config); 146 struct intel_crtc_config *pipe_config);
146 int crtc_mask; 147 int crtc_mask;
@@ -193,6 +194,17 @@ typedef struct dpll {
193} intel_clock_t; 194} intel_clock_t;
194 195
195struct intel_crtc_config { 196struct intel_crtc_config {
197 /**
198 * quirks - bitfield with hw state readout quirks
199 *
200 * For various reasons the hw state readout code might not be able to
201 * completely faithfully read out the current state. These cases are
202 * tracked with quirk flags so that fastboot and state checker can act
203 * accordingly.
204 */
205#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
206 unsigned long quirks;
207
196 struct drm_display_mode requested_mode; 208 struct drm_display_mode requested_mode;
197 struct drm_display_mode adjusted_mode; 209 struct drm_display_mode adjusted_mode;
198 /* This flag must be set by the encoder's compute_config callback if it 210 /* This flag must be set by the encoder's compute_config callback if it
@@ -241,14 +253,21 @@ struct intel_crtc_config {
241 * haswell. */ 253 * haswell. */
242 struct dpll dpll; 254 struct dpll dpll;
243 255
256 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
257 enum intel_dpll_id shared_dpll;
258
259 /* Actual register state of the dpll, for shared dpll cross-checking. */
260 struct intel_dpll_hw_state dpll_hw_state;
261
244 int pipe_bpp; 262 int pipe_bpp;
245 struct intel_link_m_n dp_m_n; 263 struct intel_link_m_n dp_m_n;
246 /** 264
247 * This is currently used by DP and HDMI encoders since those can have a 265 /*
248 * target pixel clock != the port link clock (which is currently stored 266 * Frequence the dpll for the port should run at. Differs from the
249 * in adjusted_mode->clock). 267 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
250 */ 268 */
251 int pixel_target_clock; 269 int port_clock;
270
252 /* Used by SDVO (and if we ever fix it, HDMI). */ 271 /* Used by SDVO (and if we ever fix it, HDMI). */
253 unsigned pixel_multiplier; 272 unsigned pixel_multiplier;
254 273
@@ -304,8 +323,6 @@ struct intel_crtc {
304 323
305 struct intel_crtc_config config; 324 struct intel_crtc_config config;
306 325
307 /* We can share PLLs across outputs if the timings match */
308 struct intel_pch_pll *pch_pll;
309 uint32_t ddi_pll_sel; 326 uint32_t ddi_pll_sel;
310 327
311 /* reset counter value when the last flip was submitted */ 328 /* reset counter value when the last flip was submitted */
@@ -562,9 +579,10 @@ extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
562extern void intel_dvo_init(struct drm_device *dev); 579extern void intel_dvo_init(struct drm_device *dev);
563extern void intel_tv_init(struct drm_device *dev); 580extern void intel_tv_init(struct drm_device *dev);
564extern void intel_mark_busy(struct drm_device *dev); 581extern void intel_mark_busy(struct drm_device *dev);
565extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); 582extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
583 struct intel_ring_buffer *ring);
566extern void intel_mark_idle(struct drm_device *dev); 584extern void intel_mark_idle(struct drm_device *dev);
567extern bool intel_lvds_init(struct drm_device *dev); 585extern void intel_lvds_init(struct drm_device *dev);
568extern bool intel_is_dual_link_lvds(struct drm_device *dev); 586extern bool intel_is_dual_link_lvds(struct drm_device *dev);
569extern void intel_dp_init(struct drm_device *dev, int output_reg, 587extern void intel_dp_init(struct drm_device *dev, int output_reg,
570 enum port port); 588 enum port port);
@@ -628,11 +646,11 @@ extern void intel_crtc_load_lut(struct drm_crtc *crtc);
628extern void intel_crtc_update_dpms(struct drm_crtc *crtc); 646extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
629extern void intel_encoder_destroy(struct drm_encoder *encoder); 647extern void intel_encoder_destroy(struct drm_encoder *encoder);
630extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); 648extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
631extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
632extern void intel_connector_dpms(struct drm_connector *, int mode); 649extern void intel_connector_dpms(struct drm_connector *, int mode);
633extern bool intel_connector_get_hw_state(struct intel_connector *connector); 650extern bool intel_connector_get_hw_state(struct intel_connector *connector);
634extern void intel_modeset_check_state(struct drm_device *dev); 651extern void intel_modeset_check_state(struct drm_device *dev);
635extern void intel_plane_restore(struct drm_plane *plane); 652extern void intel_plane_restore(struct drm_plane *plane);
653extern void intel_plane_disable(struct drm_plane *plane);
636 654
637 655
638static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 656static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
@@ -767,6 +785,10 @@ extern void intel_update_fbc(struct drm_device *dev);
767extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 785extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
768extern void intel_gpu_ips_teardown(void); 786extern void intel_gpu_ips_teardown(void);
769 787
788/* Power well */
789extern int i915_init_power_well(struct drm_device *dev);
790extern void i915_remove_power_well(struct drm_device *dev);
791
770extern bool intel_display_power_enabled(struct drm_device *dev, 792extern bool intel_display_power_enabled(struct drm_device *dev,
771 enum intel_display_power_domain domain); 793 enum intel_display_power_domain domain);
772extern void intel_init_power_well(struct drm_device *dev); 794extern void intel_init_power_well(struct drm_device *dev);
@@ -786,7 +808,7 @@ extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
786extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 808extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
787extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 809extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
788extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); 810extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
789extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); 811extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
790extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); 812extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
791extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 813extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
792extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 814extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 3b03c3c6cc5d..dff669e2387f 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -60,8 +60,9 @@ static struct fb_ops intelfb_ops = {
60static int intelfb_create(struct drm_fb_helper *helper, 60static int intelfb_create(struct drm_fb_helper *helper,
61 struct drm_fb_helper_surface_size *sizes) 61 struct drm_fb_helper_surface_size *sizes)
62{ 62{
63 struct intel_fbdev *ifbdev = (struct intel_fbdev *)helper; 63 struct intel_fbdev *ifbdev =
64 struct drm_device *dev = ifbdev->helper.dev; 64 container_of(helper, struct intel_fbdev, helper);
65 struct drm_device *dev = helper->dev;
65 struct drm_i915_private *dev_priv = dev->dev_private; 66 struct drm_i915_private *dev_priv = dev->dev_private;
66 struct fb_info *info; 67 struct fb_info *info;
67 struct drm_framebuffer *fb; 68 struct drm_framebuffer *fb;
@@ -108,7 +109,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
108 goto out_unpin; 109 goto out_unpin;
109 } 110 }
110 111
111 info->par = ifbdev; 112 info->par = helper;
112 113
113 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj); 114 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
114 if (ret) 115 if (ret)
@@ -217,7 +218,7 @@ static void intel_fbdev_destroy(struct drm_device *dev,
217int intel_fbdev_init(struct drm_device *dev) 218int intel_fbdev_init(struct drm_device *dev)
218{ 219{
219 struct intel_fbdev *ifbdev; 220 struct intel_fbdev *ifbdev;
220 drm_i915_private_t *dev_priv = dev->dev_private; 221 struct drm_i915_private *dev_priv = dev->dev_private;
221 int ret; 222 int ret;
222 223
223 ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); 224 ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
@@ -242,7 +243,7 @@ int intel_fbdev_init(struct drm_device *dev)
242 243
243void intel_fbdev_initial_config(struct drm_device *dev) 244void intel_fbdev_initial_config(struct drm_device *dev)
244{ 245{
245 drm_i915_private_t *dev_priv = dev->dev_private; 246 struct drm_i915_private *dev_priv = dev->dev_private;
246 247
247 /* Due to peculiar init order wrt to hpd handling this is separate. */ 248 /* Due to peculiar init order wrt to hpd handling this is separate. */
248 drm_fb_helper_initial_config(&dev_priv->fbdev->helper, 32); 249 drm_fb_helper_initial_config(&dev_priv->fbdev->helper, 32);
@@ -250,7 +251,7 @@ void intel_fbdev_initial_config(struct drm_device *dev)
250 251
251void intel_fbdev_fini(struct drm_device *dev) 252void intel_fbdev_fini(struct drm_device *dev)
252{ 253{
253 drm_i915_private_t *dev_priv = dev->dev_private; 254 struct drm_i915_private *dev_priv = dev->dev_private;
254 if (!dev_priv->fbdev) 255 if (!dev_priv->fbdev)
255 return; 256 return;
256 257
@@ -261,7 +262,7 @@ void intel_fbdev_fini(struct drm_device *dev)
261 262
262void intel_fbdev_set_suspend(struct drm_device *dev, int state) 263void intel_fbdev_set_suspend(struct drm_device *dev, int state)
263{ 264{
264 drm_i915_private_t *dev_priv = dev->dev_private; 265 struct drm_i915_private *dev_priv = dev->dev_private;
265 struct intel_fbdev *ifbdev = dev_priv->fbdev; 266 struct intel_fbdev *ifbdev = dev_priv->fbdev;
266 struct fb_info *info; 267 struct fb_info *info;
267 268
@@ -274,7 +275,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state)
274 * been restored from swap. If the object is stolen however, it will be 275 * been restored from swap. If the object is stolen however, it will be
275 * full of whatever garbage was left in there. 276 * full of whatever garbage was left in there.
276 */ 277 */
277 if (!state && ifbdev->ifb.obj->stolen) 278 if (state == FBINFO_STATE_RUNNING && ifbdev->ifb.obj->stolen)
278 memset_io(info->screen_base, 0, info->screen_size); 279 memset_io(info->screen_base, 0, info->screen_size);
279 280
280 fb_set_suspend(info, state); 281 fb_set_suspend(info, state);
@@ -284,14 +285,14 @@ MODULE_LICENSE("GPL and additional rights");
284 285
285void intel_fb_output_poll_changed(struct drm_device *dev) 286void intel_fb_output_poll_changed(struct drm_device *dev)
286{ 287{
287 drm_i915_private_t *dev_priv = dev->dev_private; 288 struct drm_i915_private *dev_priv = dev->dev_private;
288 drm_fb_helper_hotplug_event(&dev_priv->fbdev->helper); 289 drm_fb_helper_hotplug_event(&dev_priv->fbdev->helper);
289} 290}
290 291
291void intel_fb_restore_mode(struct drm_device *dev) 292void intel_fb_restore_mode(struct drm_device *dev)
292{ 293{
293 int ret; 294 int ret;
294 drm_i915_private_t *dev_priv = dev->dev_private; 295 struct drm_i915_private *dev_priv = dev->dev_private;
295 296
296 if (INTEL_INFO(dev)->num_pipes == 0) 297 if (INTEL_INFO(dev)->num_pipes == 0)
297 return; 298 return;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8062a92e6e80..bc12518a21b4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -835,9 +835,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
835 desired_bpp = 12*3; 835 desired_bpp = 12*3;
836 836
837 /* Need to adjust the port link by 1.5x for 12bpc. */ 837 /* Need to adjust the port link by 1.5x for 12bpc. */
838 adjusted_mode->clock = clock_12bpc; 838 pipe_config->port_clock = clock_12bpc;
839 pipe_config->pixel_target_clock =
840 pipe_config->requested_mode.clock;
841 } else { 839 } else {
842 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 840 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
843 desired_bpp = 8*3; 841 desired_bpp = 8*3;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 0ef8b4dc835f..2abb2d3c727b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -264,9 +264,6 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
264 return false; 264 return false;
265 } 265 }
266 266
267 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
268 return false;
269
270 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == 267 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
271 LVDS_A3_POWER_UP) 268 LVDS_A3_POWER_UP)
272 lvds_bpp = 8*3; 269 lvds_bpp = 8*3;
@@ -880,7 +877,7 @@ static bool intel_lvds_supported(struct drm_device *dev)
880 * Create the connector, register the LVDS DDC bus, and try to figure out what 877 * Create the connector, register the LVDS DDC bus, and try to figure out what
881 * modes we can display on the LVDS panel (if present). 878 * modes we can display on the LVDS panel (if present).
882 */ 879 */
883bool intel_lvds_init(struct drm_device *dev) 880void intel_lvds_init(struct drm_device *dev)
884{ 881{
885 struct drm_i915_private *dev_priv = dev->dev_private; 882 struct drm_i915_private *dev_priv = dev->dev_private;
886 struct intel_lvds_encoder *lvds_encoder; 883 struct intel_lvds_encoder *lvds_encoder;
@@ -898,35 +895,35 @@ bool intel_lvds_init(struct drm_device *dev)
898 u8 pin; 895 u8 pin;
899 896
900 if (!intel_lvds_supported(dev)) 897 if (!intel_lvds_supported(dev))
901 return false; 898 return;
902 899
903 /* Skip init on machines we know falsely report LVDS */ 900 /* Skip init on machines we know falsely report LVDS */
904 if (dmi_check_system(intel_no_lvds)) 901 if (dmi_check_system(intel_no_lvds))
905 return false; 902 return;
906 903
907 pin = GMBUS_PORT_PANEL; 904 pin = GMBUS_PORT_PANEL;
908 if (!lvds_is_present_in_vbt(dev, &pin)) { 905 if (!lvds_is_present_in_vbt(dev, &pin)) {
909 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 906 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
910 return false; 907 return;
911 } 908 }
912 909
913 if (HAS_PCH_SPLIT(dev)) { 910 if (HAS_PCH_SPLIT(dev)) {
914 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 911 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
915 return false; 912 return;
916 if (dev_priv->vbt.edp_support) { 913 if (dev_priv->vbt.edp_support) {
917 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 914 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
918 return false; 915 return;
919 } 916 }
920 } 917 }
921 918
922 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); 919 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
923 if (!lvds_encoder) 920 if (!lvds_encoder)
924 return false; 921 return;
925 922
926 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); 923 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
927 if (!lvds_connector) { 924 if (!lvds_connector) {
928 kfree(lvds_encoder); 925 kfree(lvds_encoder);
929 return false; 926 return;
930 } 927 }
931 928
932 lvds_encoder->attached_connector = lvds_connector; 929 lvds_encoder->attached_connector = lvds_connector;
@@ -1097,7 +1094,7 @@ out:
1097 intel_panel_init(&intel_connector->panel, fixed_mode); 1094 intel_panel_init(&intel_connector->panel, fixed_mode);
1098 intel_panel_setup_backlight(connector); 1095 intel_panel_setup_backlight(connector);
1099 1096
1100 return true; 1097 return;
1101 1098
1102failed: 1099failed:
1103 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1100 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
@@ -1107,5 +1104,5 @@ failed:
1107 drm_mode_destroy(dev, fixed_mode); 1104 drm_mode_destroy(dev, fixed_mode);
1108 kfree(lvds_encoder); 1105 kfree(lvds_encoder);
1109 kfree(lvds_connector); 1106 kfree(lvds_connector);
1110 return false; 1107 return;
1111} 1108}
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 5c2d6939600e..79be7cfd3152 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -312,7 +312,7 @@ static void intel_didl_outputs(struct drm_device *dev)
312 list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) { 312 list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
313 if (i >= 8) { 313 if (i >= 8) {
314 dev_printk(KERN_ERR, &dev->pdev->dev, 314 dev_printk(KERN_ERR, &dev->pdev->dev,
315 "More than 8 outputs detected\n"); 315 "More than 8 outputs detected via ACPI\n");
316 return; 316 return;
317 } 317 }
318 status = 318 status =
@@ -339,7 +339,7 @@ blind_set:
339 int output_type = ACPI_OTHER_OUTPUT; 339 int output_type = ACPI_OTHER_OUTPUT;
340 if (i >= 8) { 340 if (i >= 8) {
341 dev_printk(KERN_ERR, &dev->pdev->dev, 341 dev_printk(KERN_ERR, &dev->pdev->dev,
342 "More than 8 outputs detected\n"); 342 "More than 8 outputs in connector list\n");
343 return; 343 return;
344 } 344 }
345 switch (connector->connector_type) { 345 switch (connector->connector_type) {
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 836794b68fc6..a3698812e9c7 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -217,7 +217,7 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
217 int ret; 217 int ret;
218 218
219 BUG_ON(overlay->last_flip_req); 219 BUG_ON(overlay->last_flip_req);
220 ret = i915_add_request(ring, NULL, &overlay->last_flip_req); 220 ret = i915_add_request(ring, &overlay->last_flip_req);
221 if (ret) 221 if (ret)
222 return ret; 222 return ret;
223 223
@@ -286,7 +286,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
286 intel_ring_emit(ring, flip_addr); 286 intel_ring_emit(ring, flip_addr);
287 intel_ring_advance(ring); 287 intel_ring_advance(ring);
288 288
289 return i915_add_request(ring, NULL, &overlay->last_flip_req); 289 return i915_add_request(ring, &overlay->last_flip_req);
290} 290}
291 291
292static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 292static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 49a188718f9d..b27bda07f4ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -274,7 +274,7 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
274 struct drm_i915_gem_object *obj = intel_fb->obj; 274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276 276
277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset);
278 278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | 279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN | 280 IVB_DPFC_CTL_FENCE_EN |
@@ -431,7 +431,7 @@ void intel_disable_fbc(struct drm_device *dev)
431 * - no pixel mulitply/line duplication 431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard 432 * - no alpha buffer discard
433 * - no dual wide 433 * - no dual wide
434 * - framebuffer <= 2048 in width, 1536 in height 434 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
435 * 435 *
436 * We can't assume that any compression will take place (worst case), 436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed 437 * so the compressed buffer has to be the same size as the uncompressed
@@ -449,6 +449,7 @@ void intel_update_fbc(struct drm_device *dev)
449 struct intel_framebuffer *intel_fb; 449 struct intel_framebuffer *intel_fb;
450 struct drm_i915_gem_object *obj; 450 struct drm_i915_gem_object *obj;
451 int enable_fbc; 451 int enable_fbc;
452 unsigned int max_hdisplay, max_vdisplay;
452 453
453 if (!i915_powersave) 454 if (!i915_powersave)
454 return; 455 return;
@@ -507,8 +508,16 @@ void intel_update_fbc(struct drm_device *dev)
507 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 508 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
508 goto out_disable; 509 goto out_disable;
509 } 510 }
510 if ((crtc->mode.hdisplay > 2048) || 511
511 (crtc->mode.vdisplay > 1536)) { 512 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
513 max_hdisplay = 4096;
514 max_vdisplay = 2048;
515 } else {
516 max_hdisplay = 2048;
517 max_vdisplay = 1536;
518 }
519 if ((crtc->mode.hdisplay > max_hdisplay) ||
520 (crtc->mode.vdisplay > max_vdisplay)) {
512 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 521 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 522 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
514 goto out_disable; 523 goto out_disable;
@@ -2078,10 +2087,7 @@ static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 uint32_t pixel_rate, pfit_size; 2088 uint32_t pixel_rate, pfit_size;
2080 2089
2081 if (intel_crtc->config.pixel_target_clock) 2090 pixel_rate = intel_crtc->config.adjusted_mode.clock;
2082 pixel_rate = intel_crtc->config.pixel_target_clock;
2083 else
2084 pixel_rate = intel_crtc->config.adjusted_mode.clock;
2085 2091
2086 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 2092 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2087 * adjust the pixel_rate here. */ 2093 * adjust the pixel_rate here. */
@@ -4381,6 +4387,19 @@ static void ibx_init_clock_gating(struct drm_device *dev)
4381 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 4387 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4382} 4388}
4383 4389
4390static void g4x_disable_trickle_feed(struct drm_device *dev)
4391{
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393 int pipe;
4394
4395 for_each_pipe(pipe) {
4396 I915_WRITE(DSPCNTR(pipe),
4397 I915_READ(DSPCNTR(pipe)) |
4398 DISPPLANE_TRICKLE_FEED_DISABLE);
4399 intel_flush_display_plane(dev_priv, pipe);
4400 }
4401}
4402
4384static void ironlake_init_clock_gating(struct drm_device *dev) 4403static void ironlake_init_clock_gating(struct drm_device *dev)
4385{ 4404{
4386 struct drm_i915_private *dev_priv = dev->dev_private; 4405 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4444,6 +4463,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
4444 I915_WRITE(CACHE_MODE_0, 4463 I915_WRITE(CACHE_MODE_0,
4445 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4464 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4446 4465
4466 g4x_disable_trickle_feed(dev);
4467
4447 ibx_init_clock_gating(dev); 4468 ibx_init_clock_gating(dev);
4448} 4469}
4449 4470
@@ -4498,7 +4519,6 @@ static void gen6_check_mch_setup(struct drm_device *dev)
4498static void gen6_init_clock_gating(struct drm_device *dev) 4519static void gen6_init_clock_gating(struct drm_device *dev)
4499{ 4520{
4500 struct drm_i915_private *dev_priv = dev->dev_private; 4521 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int pipe;
4502 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 4522 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4503 4523
4504 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 4524 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
@@ -4574,12 +4594,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
4574 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 4594 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4575 GEN6_MBCTL_ENABLE_BOOT_FETCH); 4595 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4576 4596
4577 for_each_pipe(pipe) { 4597 g4x_disable_trickle_feed(dev);
4578 I915_WRITE(DSPCNTR(pipe),
4579 I915_READ(DSPCNTR(pipe)) |
4580 DISPPLANE_TRICKLE_FEED_DISABLE);
4581 intel_flush_display_plane(dev_priv, pipe);
4582 }
4583 4598
4584 /* The default value should be 0x200 according to docs, but the two 4599 /* The default value should be 0x200 according to docs, but the two
4585 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 4600 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
@@ -4640,7 +4655,6 @@ static void lpt_suspend_hw(struct drm_device *dev)
4640static void haswell_init_clock_gating(struct drm_device *dev) 4655static void haswell_init_clock_gating(struct drm_device *dev)
4641{ 4656{
4642 struct drm_i915_private *dev_priv = dev->dev_private; 4657 struct drm_i915_private *dev_priv = dev->dev_private;
4643 int pipe;
4644 4658
4645 I915_WRITE(WM3_LP_ILK, 0); 4659 I915_WRITE(WM3_LP_ILK, 0);
4646 I915_WRITE(WM2_LP_ILK, 0); 4660 I915_WRITE(WM2_LP_ILK, 0);
@@ -4666,12 +4680,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
4666 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 4680 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4667 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 4681 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4668 4682
4669 for_each_pipe(pipe) { 4683 g4x_disable_trickle_feed(dev);
4670 I915_WRITE(DSPCNTR(pipe),
4671 I915_READ(DSPCNTR(pipe)) |
4672 DISPPLANE_TRICKLE_FEED_DISABLE);
4673 intel_flush_display_plane(dev_priv, pipe);
4674 }
4675 4684
4676 /* WaVSRefCountFullforceMissDisable:hsw */ 4685 /* WaVSRefCountFullforceMissDisable:hsw */
4677 gen7_setup_fixed_func_scheduler(dev_priv); 4686 gen7_setup_fixed_func_scheduler(dev_priv);
@@ -4697,7 +4706,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
4697static void ivybridge_init_clock_gating(struct drm_device *dev) 4706static void ivybridge_init_clock_gating(struct drm_device *dev)
4698{ 4707{
4699 struct drm_i915_private *dev_priv = dev->dev_private; 4708 struct drm_i915_private *dev_priv = dev->dev_private;
4700 int pipe;
4701 uint32_t snpcr; 4709 uint32_t snpcr;
4702 4710
4703 I915_WRITE(WM3_LP_ILK, 0); 4711 I915_WRITE(WM3_LP_ILK, 0);
@@ -4766,12 +4774,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
4766 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 4774 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4767 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 4775 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4768 4776
4769 for_each_pipe(pipe) { 4777 g4x_disable_trickle_feed(dev);
4770 I915_WRITE(DSPCNTR(pipe),
4771 I915_READ(DSPCNTR(pipe)) |
4772 DISPPLANE_TRICKLE_FEED_DISABLE);
4773 intel_flush_display_plane(dev_priv, pipe);
4774 }
4775 4778
4776 /* WaMbcDriverBootEnable:ivb */ 4779 /* WaMbcDriverBootEnable:ivb */
4777 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 4780 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
@@ -4798,13 +4801,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
4798static void valleyview_init_clock_gating(struct drm_device *dev) 4801static void valleyview_init_clock_gating(struct drm_device *dev)
4799{ 4802{
4800 struct drm_i915_private *dev_priv = dev->dev_private; 4803 struct drm_i915_private *dev_priv = dev->dev_private;
4801 int pipe;
4802
4803 I915_WRITE(WM3_LP_ILK, 0);
4804 I915_WRITE(WM2_LP_ILK, 0);
4805 I915_WRITE(WM1_LP_ILK, 0);
4806 4804
4807 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 4805 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4808 4806
4809 /* WaDisableEarlyCull:vlv */ 4807 /* WaDisableEarlyCull:vlv */
4810 I915_WRITE(_3D_CHICKEN3, 4808 I915_WRITE(_3D_CHICKEN3,
@@ -4875,12 +4873,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
4875 4873
4876 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 4874 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4877 4875
4878 for_each_pipe(pipe) { 4876 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4879 I915_WRITE(DSPCNTR(pipe),
4880 I915_READ(DSPCNTR(pipe)) |
4881 DISPPLANE_TRICKLE_FEED_DISABLE);
4882 intel_flush_display_plane(dev_priv, pipe);
4883 }
4884 4877
4885 I915_WRITE(CACHE_MODE_1, 4878 I915_WRITE(CACHE_MODE_1,
4886 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 4879 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
@@ -4922,6 +4915,8 @@ static void g4x_init_clock_gating(struct drm_device *dev)
4922 /* WaDisableRenderCachePipelinedFlush */ 4915 /* WaDisableRenderCachePipelinedFlush */
4923 I915_WRITE(CACHE_MODE_0, 4916 I915_WRITE(CACHE_MODE_0,
4924 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4917 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4918
4919 g4x_disable_trickle_feed(dev);
4925} 4920}
4926 4921
4927static void crestline_init_clock_gating(struct drm_device *dev) 4922static void crestline_init_clock_gating(struct drm_device *dev)
@@ -4933,6 +4928,8 @@ static void crestline_init_clock_gating(struct drm_device *dev)
4933 I915_WRITE(DSPCLK_GATE_D, 0); 4928 I915_WRITE(DSPCLK_GATE_D, 0);
4934 I915_WRITE(RAMCLK_GATE_D, 0); 4929 I915_WRITE(RAMCLK_GATE_D, 0);
4935 I915_WRITE16(DEUC, 0); 4930 I915_WRITE16(DEUC, 0);
4931 I915_WRITE(MI_ARB_STATE,
4932 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4936} 4933}
4937 4934
4938static void broadwater_init_clock_gating(struct drm_device *dev) 4935static void broadwater_init_clock_gating(struct drm_device *dev)
@@ -4945,6 +4942,8 @@ static void broadwater_init_clock_gating(struct drm_device *dev)
4945 I965_ISC_CLOCK_GATE_DISABLE | 4942 I965_ISC_CLOCK_GATE_DISABLE |
4946 I965_FBC_CLOCK_GATE_DISABLE); 4943 I965_FBC_CLOCK_GATE_DISABLE);
4947 I915_WRITE(RENCLK_GATE_D2, 0); 4944 I915_WRITE(RENCLK_GATE_D2, 0);
4945 I915_WRITE(MI_ARB_STATE,
4946 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4948} 4947}
4949 4948
4950static void gen3_init_clock_gating(struct drm_device *dev) 4949static void gen3_init_clock_gating(struct drm_device *dev)
@@ -5022,18 +5021,12 @@ bool intel_display_power_enabled(struct drm_device *dev,
5022 } 5021 }
5023} 5022}
5024 5023
5025void intel_set_power_well(struct drm_device *dev, bool enable) 5024static void __intel_set_power_well(struct drm_device *dev, bool enable)
5026{ 5025{
5027 struct drm_i915_private *dev_priv = dev->dev_private; 5026 struct drm_i915_private *dev_priv = dev->dev_private;
5028 bool is_enabled, enable_requested; 5027 bool is_enabled, enable_requested;
5029 uint32_t tmp; 5028 uint32_t tmp;
5030 5029
5031 if (!HAS_POWER_WELL(dev))
5032 return;
5033
5034 if (!i915_disable_power_well && !enable)
5035 return;
5036
5037 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5030 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5038 is_enabled = tmp & HSW_PWR_WELL_STATE; 5031 is_enabled = tmp & HSW_PWR_WELL_STATE;
5039 enable_requested = tmp & HSW_PWR_WELL_ENABLE; 5032 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
@@ -5056,6 +5049,79 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
5056 } 5049 }
5057} 5050}
5058 5051
5052static struct i915_power_well *hsw_pwr;
5053
5054/* Display audio driver power well request */
5055void i915_request_power_well(void)
5056{
5057 if (WARN_ON(!hsw_pwr))
5058 return;
5059
5060 spin_lock_irq(&hsw_pwr->lock);
5061 if (!hsw_pwr->count++ &&
5062 !hsw_pwr->i915_request)
5063 __intel_set_power_well(hsw_pwr->device, true);
5064 spin_unlock_irq(&hsw_pwr->lock);
5065}
5066EXPORT_SYMBOL_GPL(i915_request_power_well);
5067
5068/* Display audio driver power well release */
5069void i915_release_power_well(void)
5070{
5071 if (WARN_ON(!hsw_pwr))
5072 return;
5073
5074 spin_lock_irq(&hsw_pwr->lock);
5075 WARN_ON(!hsw_pwr->count);
5076 if (!--hsw_pwr->count &&
5077 !hsw_pwr->i915_request)
5078 __intel_set_power_well(hsw_pwr->device, false);
5079 spin_unlock_irq(&hsw_pwr->lock);
5080}
5081EXPORT_SYMBOL_GPL(i915_release_power_well);
5082
5083int i915_init_power_well(struct drm_device *dev)
5084{
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086
5087 hsw_pwr = &dev_priv->power_well;
5088
5089 hsw_pwr->device = dev;
5090 spin_lock_init(&hsw_pwr->lock);
5091 hsw_pwr->count = 0;
5092
5093 return 0;
5094}
5095
5096void i915_remove_power_well(struct drm_device *dev)
5097{
5098 hsw_pwr = NULL;
5099}
5100
5101void intel_set_power_well(struct drm_device *dev, bool enable)
5102{
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct i915_power_well *power_well = &dev_priv->power_well;
5105
5106 if (!HAS_POWER_WELL(dev))
5107 return;
5108
5109 if (!i915_disable_power_well && !enable)
5110 return;
5111
5112 spin_lock_irq(&power_well->lock);
5113 power_well->i915_request = enable;
5114
5115 /* only reject "disable" power well request */
5116 if (power_well->count && !enable) {
5117 spin_unlock_irq(&power_well->lock);
5118 return;
5119 }
5120
5121 __intel_set_power_well(dev, enable);
5122 spin_unlock_irq(&power_well->lock);
5123}
5124
5059/* 5125/*
5060 * Starting with Haswell, we have a "Power Down Well" that can be turned off 5126 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5061 * when not needed anymore. We have 4 registers that can request the power well 5127 * when not needed anymore. We have 4 registers that can request the power well
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0e72da6ad0fa..e51ab552046c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -280,6 +280,27 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
280 return 0; 280 return 0;
281} 281}
282 282
283static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
284{
285 int ret;
286
287 if (!ring->fbc_dirty)
288 return 0;
289
290 ret = intel_ring_begin(ring, 4);
291 if (ret)
292 return ret;
293 intel_ring_emit(ring, MI_NOOP);
294 /* WaFbcNukeOn3DBlt:ivb/hsw */
295 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, value);
298 intel_ring_advance(ring);
299
300 ring->fbc_dirty = false;
301 return 0;
302}
303
283static int 304static int
284gen7_render_ring_flush(struct intel_ring_buffer *ring, 305gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains) 306 u32 invalidate_domains, u32 flush_domains)
@@ -336,6 +357,9 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
336 intel_ring_emit(ring, 0); 357 intel_ring_emit(ring, 0);
337 intel_ring_advance(ring); 358 intel_ring_advance(ring);
338 359
360 if (flush_domains)
361 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
362
339 return 0; 363 return 0;
340} 364}
341 365
@@ -429,6 +453,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
429 ring->last_retired_head = -1; 453 ring->last_retired_head = -1;
430 } 454 }
431 455
456 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
457
432out: 458out:
433 if (HAS_FORCE_WAKE(dev)) 459 if (HAS_FORCE_WAKE(dev))
434 gen6_gt_force_wake_put(dev_priv); 460 gen6_gt_force_wake_put(dev_priv);
@@ -1486,7 +1512,7 @@ int intel_ring_idle(struct intel_ring_buffer *ring)
1486 1512
1487 /* We need to add any requests required to flush the objects and ring */ 1513 /* We need to add any requests required to flush the objects and ring */
1488 if (ring->outstanding_lazy_request) { 1514 if (ring->outstanding_lazy_request) {
1489 ret = i915_add_request(ring, NULL, NULL); 1515 ret = i915_add_request(ring, NULL);
1490 if (ret) 1516 if (ret)
1491 return ret; 1517 return ret;
1492 } 1518 }
@@ -1685,6 +1711,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1685static int gen6_ring_flush(struct intel_ring_buffer *ring, 1711static int gen6_ring_flush(struct intel_ring_buffer *ring,
1686 u32 invalidate, u32 flush) 1712 u32 invalidate, u32 flush)
1687{ 1713{
1714 struct drm_device *dev = ring->dev;
1688 uint32_t cmd; 1715 uint32_t cmd;
1689 int ret; 1716 int ret;
1690 1717
@@ -1707,6 +1734,10 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
1707 intel_ring_emit(ring, 0); 1734 intel_ring_emit(ring, 0);
1708 intel_ring_emit(ring, MI_NOOP); 1735 intel_ring_emit(ring, MI_NOOP);
1709 intel_ring_advance(ring); 1736 intel_ring_advance(ring);
1737
1738 if (IS_GEN7(dev) && flush)
1739 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1740
1710 return 0; 1741 return 0;
1711} 1742}
1712 1743
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 022d07e43d12..799f04c9da45 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -37,8 +37,14 @@ struct intel_hw_status_page {
37#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) 37#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
38#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) 38#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
39 39
40enum intel_ring_hangcheck_action { wait, active, kick, hung };
41
40struct intel_ring_hangcheck { 42struct intel_ring_hangcheck {
43 bool deadlock;
41 u32 seqno; 44 u32 seqno;
45 u32 acthd;
46 int score;
47 enum intel_ring_hangcheck_action action;
42}; 48};
43 49
44struct intel_ring_buffer { 50struct intel_ring_buffer {
@@ -138,6 +144,7 @@ struct intel_ring_buffer {
138 */ 144 */
139 u32 outstanding_lazy_request; 145 u32 outstanding_lazy_request;
140 bool gpu_caches_dirty; 146 bool gpu_caches_dirty;
147 bool fbc_dirty;
141 148
142 wait_queue_head_t irq_queue; 149 wait_queue_head_t irq_queue;
143 150
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index c55841937705..2628d5622449 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -80,7 +80,7 @@ struct intel_sdvo {
80 80
81 /* 81 /*
82 * Capabilities of the SDVO device returned by 82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities() 83 * intel_sdvo_get_capabilities()
84 */ 84 */
85 struct intel_sdvo_caps caps; 85 struct intel_sdvo_caps caps;
86 86
@@ -1219,6 +1219,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
1219 1219
1220 switch (intel_crtc->config.pixel_multiplier) { 1220 switch (intel_crtc->config.pixel_multiplier) {
1221 default: 1221 default:
1222 WARN(1, "unknown pixel mutlipler specified\n");
1222 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1223 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1223 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1224 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1224 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1225 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
@@ -1276,7 +1277,7 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1276 struct intel_sdvo_connector *intel_sdvo_connector = 1277 struct intel_sdvo_connector *intel_sdvo_connector =
1277 to_intel_sdvo_connector(&connector->base); 1278 to_intel_sdvo_connector(&connector->base);
1278 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1279 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1279 u16 active_outputs; 1280 u16 active_outputs = 0;
1280 1281
1281 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1282 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1282 1283
@@ -1292,7 +1293,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1292 struct drm_device *dev = encoder->base.dev; 1293 struct drm_device *dev = encoder->base.dev;
1293 struct drm_i915_private *dev_priv = dev->dev_private; 1294 struct drm_i915_private *dev_priv = dev->dev_private;
1294 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1295 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1295 u16 active_outputs; 1296 u16 active_outputs = 0;
1296 u32 tmp; 1297 u32 tmp;
1297 1298
1298 tmp = I915_READ(intel_sdvo->sdvo_reg); 1299 tmp = I915_READ(intel_sdvo->sdvo_reg);
@@ -1312,28 +1313,69 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1312static void intel_sdvo_get_config(struct intel_encoder *encoder, 1313static void intel_sdvo_get_config(struct intel_encoder *encoder,
1313 struct intel_crtc_config *pipe_config) 1314 struct intel_crtc_config *pipe_config)
1314{ 1315{
1316 struct drm_device *dev = encoder->base.dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1315 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1318 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1316 struct intel_sdvo_dtd dtd; 1319 struct intel_sdvo_dtd dtd;
1317 u32 flags = 0; 1320 int encoder_pixel_multiplier = 0;
1321 u32 flags = 0, sdvox;
1322 u8 val;
1318 bool ret; 1323 bool ret;
1319 1324
1320 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1321 if (!ret) { 1326 if (!ret) {
1327 /* Some sdvo encoders are not spec compliant and don't
1328 * implement the mandatory get_timings function. */
1322 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1329 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1323 return; 1330 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1331 } else {
1332 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1334 else
1335 flags |= DRM_MODE_FLAG_NHSYNC;
1336
1337 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1339 else
1340 flags |= DRM_MODE_FLAG_NVSYNC;
1324 } 1341 }
1325 1342
1326 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1343 pipe_config->adjusted_mode.flags |= flags;
1327 flags |= DRM_MODE_FLAG_PHSYNC;
1328 else
1329 flags |= DRM_MODE_FLAG_NHSYNC;
1330 1344
1331 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1345 /*
1332 flags |= DRM_MODE_FLAG_PVSYNC; 1346 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1333 else 1347 * the sdvo port register, on all other platforms it is part of the dpll
1334 flags |= DRM_MODE_FLAG_NVSYNC; 1348 * state. Since the general pipe state readout happens before the
1349 * encoder->get_config we so already have a valid pixel multplier on all
1350 * other platfroms.
1351 */
1352 if (IS_I915G(dev) || IS_I915GM(dev)) {
1353 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1354 pipe_config->pixel_multiplier =
1355 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1356 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1357 }
1335 1358
1336 pipe_config->adjusted_mode.flags |= flags; 1359 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1360 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
1361 switch (val) {
1362 case SDVO_CLOCK_RATE_MULT_1X:
1363 encoder_pixel_multiplier = 1;
1364 break;
1365 case SDVO_CLOCK_RATE_MULT_2X:
1366 encoder_pixel_multiplier = 2;
1367 break;
1368 case SDVO_CLOCK_RATE_MULT_4X:
1369 encoder_pixel_multiplier = 4;
1370 break;
1371 }
1372
1373 if(HAS_PCH_SPLIT(dev))
1374 return; /* no pixel multiplier readout support yet */
1375
1376 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1377 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1378 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1337} 1379}
1338 1380
1339static void intel_disable_sdvo(struct intel_encoder *encoder) 1381static void intel_disable_sdvo(struct intel_encoder *encoder)
@@ -2819,7 +2861,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2819 struct drm_i915_private *dev_priv = dev->dev_private; 2861 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_encoder *intel_encoder; 2862 struct intel_encoder *intel_encoder;
2821 struct intel_sdvo *intel_sdvo; 2863 struct intel_sdvo *intel_sdvo;
2822 u32 hotplug_mask;
2823 int i; 2864 int i;
2824 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); 2865 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2825 if (!intel_sdvo) 2866 if (!intel_sdvo)
@@ -2848,18 +2889,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2848 } 2889 }
2849 } 2890 }
2850 2891
2851 hotplug_mask = 0;
2852 if (IS_G4X(dev)) {
2853 hotplug_mask = intel_sdvo->is_sdvob ?
2854 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2855 } else if (IS_GEN4(dev)) {
2856 hotplug_mask = intel_sdvo->is_sdvob ?
2857 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2858 } else {
2859 hotplug_mask = intel_sdvo->is_sdvob ?
2860 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2861 }
2862
2863 intel_encoder->compute_config = intel_sdvo_compute_config; 2892 intel_encoder->compute_config = intel_sdvo_compute_config;
2864 intel_encoder->disable = intel_disable_sdvo; 2893 intel_encoder->disable = intel_disable_sdvo;
2865 intel_encoder->mode_set = intel_sdvo_mode_set; 2894 intel_encoder->mode_set = intel_sdvo_mode_set;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 04d38d4d811a..1fa5612a4572 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -957,6 +957,14 @@ void intel_plane_restore(struct drm_plane *plane)
957 intel_plane->src_w, intel_plane->src_h); 957 intel_plane->src_w, intel_plane->src_h);
958} 958}
959 959
960void intel_plane_disable(struct drm_plane *plane)
961{
962 if (!plane->crtc || !plane->fb)
963 return;
964
965 intel_disable_plane(plane);
966}
967
960static const struct drm_plane_funcs intel_plane_funcs = { 968static const struct drm_plane_funcs intel_plane_funcs = {
961 .update_plane = intel_update_plane, 969 .update_plane = intel_update_plane,
962 .disable_plane = intel_disable_plane, 970 .disable_plane = intel_disable_plane,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 7d11a5adc985..39debd80d190 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -914,9 +914,6 @@ intel_tv_compute_config(struct intel_encoder *encoder,
914 if (!tv_mode) 914 if (!tv_mode)
915 return false; 915 return false;
916 916
917 if (intel_encoder_check_is_cloned(&intel_tv->base))
918 return false;
919
920 pipe_config->adjusted_mode.clock = tv_mode->clock; 917 pipe_config->adjusted_mode.clock = tv_mode->clock;
921 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); 918 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
922 pipe_config->pipe_bpp = 8*3; 919 pipe_config->pipe_bpp = 8*3;
diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
new file mode 100644
index 000000000000..cfdc884405b7
--- /dev/null
+++ b/include/drm/i915_powerwell.h
@@ -0,0 +1,36 @@
1/**************************************************************************
2 *
3 * Copyright 2013 Intel Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28
29#ifndef _I915_POWERWELL_H_
30#define _I915_POWERWELL_H_
31
32/* For use by hda_i915 driver */
33extern void i915_request_power_well(void);
34extern void i915_release_power_well(void);
35
36#endif /* _I915_POWERWELL_H_ */
diff --git a/sound/pci/hda/Kconfig b/sound/pci/hda/Kconfig
index 80a7d44bcf81..c5a872ca7703 100644
--- a/sound/pci/hda/Kconfig
+++ b/sound/pci/hda/Kconfig
@@ -152,6 +152,16 @@ config SND_HDA_CODEC_HDMI
152 snd-hda-codec-hdmi. 152 snd-hda-codec-hdmi.
153 This module is automatically loaded at probing. 153 This module is automatically loaded at probing.
154 154
155config SND_HDA_I915
156 bool "Build Display HD-audio controller/codec power well support for i915 cards"
157 depends on DRM_I915
158 help
159 Say Y here to include full HDMI and DisplayPort HD-audio controller/codec
160 power-well support for Intel Haswell graphics cards based on the i915 driver.
161
162 Note that this option must be enabled for Intel Haswell C+ stepping machines, otherwise
163 the GPU audio controller/codecs will not be initialized or damaged when exit from S3 mode.
164
155config SND_HDA_CODEC_CIRRUS 165config SND_HDA_CODEC_CIRRUS
156 bool "Build Cirrus Logic codec support" 166 bool "Build Cirrus Logic codec support"
157 default y 167 default y
diff --git a/sound/pci/hda/Makefile b/sound/pci/hda/Makefile
index 24a251497a1f..c091438286a3 100644
--- a/sound/pci/hda/Makefile
+++ b/sound/pci/hda/Makefile
@@ -1,4 +1,6 @@
1snd-hda-intel-objs := hda_intel.o 1snd-hda-intel-objs := hda_intel.o
2# for haswell power well
3snd-hda-intel-$(CONFIG_SND_HDA_I915) += hda_i915.o
2 4
3snd-hda-codec-y := hda_codec.o hda_jack.o hda_auto_parser.o 5snd-hda-codec-y := hda_codec.o hda_jack.o hda_auto_parser.o
4snd-hda-codec-$(CONFIG_SND_HDA_GENERIC) += hda_generic.o 6snd-hda-codec-$(CONFIG_SND_HDA_GENERIC) += hda_generic.o
diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c
new file mode 100644
index 000000000000..76c13d5b3ca0
--- /dev/null
+++ b/sound/pci/hda/hda_i915.c
@@ -0,0 +1,75 @@
1/*
2 * hda_i915.c - routines for Haswell HDA controller power well support
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <sound/core.h>
22#include <drm/i915_powerwell.h>
23#include "hda_i915.h"
24
25static void (*get_power)(void);
26static void (*put_power)(void);
27
28void hda_display_power(bool enable)
29{
30 if (!get_power || !put_power)
31 return;
32
33 snd_printdd("HDA display power %s \n",
34 enable ? "Enable" : "Disable");
35 if (enable)
36 get_power();
37 else
38 put_power();
39}
40
41int hda_i915_init(void)
42{
43 int err = 0;
44
45 get_power = symbol_request(i915_request_power_well);
46 if (!get_power) {
47 snd_printk(KERN_WARNING "hda-i915: get_power symbol get fail\n");
48 return -ENODEV;
49 }
50
51 put_power = symbol_request(i915_release_power_well);
52 if (!put_power) {
53 symbol_put(i915_request_power_well);
54 get_power = NULL;
55 return -ENODEV;
56 }
57
58 snd_printd("HDA driver get symbol successfully from i915 module\n");
59
60 return err;
61}
62
63int hda_i915_exit(void)
64{
65 if (get_power) {
66 symbol_put(i915_request_power_well);
67 get_power = NULL;
68 }
69 if (put_power) {
70 symbol_put(i915_release_power_well);
71 put_power = NULL;
72 }
73
74 return 0;
75}
diff --git a/sound/pci/hda/hda_i915.h b/sound/pci/hda/hda_i915.h
new file mode 100644
index 000000000000..5a63da2c53e5
--- /dev/null
+++ b/sound/pci/hda/hda_i915.h
@@ -0,0 +1,35 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the Free
4 * Software Foundation; either version 2 of the License, or (at your option)
5 * any later version.
6 *
7 * This program is distributed in the hope that it will be useful, but WITHOUT
8 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
10 * more details.
11 *
12 * You should have received a copy of the GNU General Public License along with
13 * this program; if not, write to the Free Software Foundation, Inc., 59
14 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 */
16#ifndef __SOUND_HDA_I915_H
17#define __SOUND_HDA_I915_H
18
19#ifdef CONFIG_SND_HDA_I915
20void hda_display_power(bool enable);
21int hda_i915_init(void);
22int hda_i915_exit(void);
23#else
24static inline void hda_display_power(bool enable) {}
25static inline int hda_i915_init(void)
26{
27 return -ENODEV;
28}
29static inline int hda_i915_exit(void)
30{
31 return 0;
32}
33#endif
34
35#endif
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index de18722c4873..35e9f8b010a7 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -62,6 +62,7 @@
62#include <linux/vga_switcheroo.h> 62#include <linux/vga_switcheroo.h>
63#include <linux/firmware.h> 63#include <linux/firmware.h>
64#include "hda_codec.h" 64#include "hda_codec.h"
65#include "hda_i915.h"
65 66
66 67
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 68static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
@@ -541,6 +542,10 @@ struct azx {
541 /* for pending irqs */ 542 /* for pending irqs */
542 struct work_struct irq_pending_work; 543 struct work_struct irq_pending_work;
543 544
545#ifdef CONFIG_SND_HDA_I915
546 struct work_struct probe_work;
547#endif
548
544 /* reboot notifier (for mysterious hangup problem at power-down) */ 549 /* reboot notifier (for mysterious hangup problem at power-down) */
545 struct notifier_block reboot_notifier; 550 struct notifier_block reboot_notifier;
546 551
@@ -594,6 +599,7 @@ enum {
594#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 599#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
595#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 600#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
596#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 601#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
602#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
597 603
598/* quirks for Intel PCH */ 604/* quirks for Intel PCH */
599#define AZX_DCAPS_INTEL_PCH_NOPM \ 605#define AZX_DCAPS_INTEL_PCH_NOPM \
@@ -2900,6 +2906,8 @@ static int azx_suspend(struct device *dev)
2900 pci_disable_device(pci); 2906 pci_disable_device(pci);
2901 pci_save_state(pci); 2907 pci_save_state(pci);
2902 pci_set_power_state(pci, PCI_D3hot); 2908 pci_set_power_state(pci, PCI_D3hot);
2909 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2910 hda_display_power(false);
2903 return 0; 2911 return 0;
2904} 2912}
2905 2913
@@ -2912,6 +2920,8 @@ static int azx_resume(struct device *dev)
2912 if (chip->disabled) 2920 if (chip->disabled)
2913 return 0; 2921 return 0;
2914 2922
2923 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2924 hda_display_power(true);
2915 pci_set_power_state(pci, PCI_D0); 2925 pci_set_power_state(pci, PCI_D0);
2916 pci_restore_state(pci); 2926 pci_restore_state(pci);
2917 if (pci_enable_device(pci) < 0) { 2927 if (pci_enable_device(pci) < 0) {
@@ -2944,6 +2954,8 @@ static int azx_runtime_suspend(struct device *dev)
2944 2954
2945 azx_stop_chip(chip); 2955 azx_stop_chip(chip);
2946 azx_clear_irq_pending(chip); 2956 azx_clear_irq_pending(chip);
2957 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2958 hda_display_power(false);
2947 return 0; 2959 return 0;
2948} 2960}
2949 2961
@@ -2952,6 +2964,8 @@ static int azx_runtime_resume(struct device *dev)
2952 struct snd_card *card = dev_get_drvdata(dev); 2964 struct snd_card *card = dev_get_drvdata(dev);
2953 struct azx *chip = card->private_data; 2965 struct azx *chip = card->private_data;
2954 2966
2967 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2968 hda_display_power(true);
2955 azx_init_pci(chip); 2969 azx_init_pci(chip);
2956 azx_init_chip(chip, 1); 2970 azx_init_chip(chip, 1);
2957 return 0; 2971 return 0;
@@ -3006,7 +3020,6 @@ static void azx_notifier_unregister(struct azx *chip)
3006 unregister_reboot_notifier(&chip->reboot_notifier); 3020 unregister_reboot_notifier(&chip->reboot_notifier);
3007} 3021}
3008 3022
3009static int azx_first_init(struct azx *chip);
3010static int azx_probe_continue(struct azx *chip); 3023static int azx_probe_continue(struct azx *chip);
3011 3024
3012#ifdef SUPPORT_VGA_SWITCHEROO 3025#ifdef SUPPORT_VGA_SWITCHEROO
@@ -3033,8 +3046,7 @@ static void azx_vs_set_state(struct pci_dev *pci,
3033 snd_printk(KERN_INFO SFX 3046 snd_printk(KERN_INFO SFX
3034 "%s: Start delayed initialization\n", 3047 "%s: Start delayed initialization\n",
3035 pci_name(chip->pci)); 3048 pci_name(chip->pci));
3036 if (azx_first_init(chip) < 0 || 3049 if (azx_probe_continue(chip) < 0) {
3037 azx_probe_continue(chip) < 0) {
3038 snd_printk(KERN_ERR SFX 3050 snd_printk(KERN_ERR SFX
3039 "%s: initialization error\n", 3051 "%s: initialization error\n",
3040 pci_name(chip->pci)); 3052 pci_name(chip->pci));
@@ -3120,8 +3132,13 @@ static int register_vga_switcheroo(struct azx *chip)
3120 */ 3132 */
3121static int azx_free(struct azx *chip) 3133static int azx_free(struct azx *chip)
3122{ 3134{
3135 struct pci_dev *pci = chip->pci;
3123 int i; 3136 int i;
3124 3137
3138 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3139 && chip->running)
3140 pm_runtime_get_noresume(&pci->dev);
3141
3125 azx_del_card_list(chip); 3142 azx_del_card_list(chip);
3126 3143
3127 azx_notifier_unregister(chip); 3144 azx_notifier_unregister(chip);
@@ -3173,6 +3190,10 @@ static int azx_free(struct azx *chip)
3173 if (chip->fw) 3190 if (chip->fw)
3174 release_firmware(chip->fw); 3191 release_firmware(chip->fw);
3175#endif 3192#endif
3193 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3194 hda_display_power(false);
3195 hda_i915_exit();
3196 }
3176 kfree(chip); 3197 kfree(chip);
3177 3198
3178 return 0; 3199 return 0;
@@ -3398,6 +3419,13 @@ static void azx_check_snoop_available(struct azx *chip)
3398 } 3419 }
3399} 3420}
3400 3421
3422#ifdef CONFIG_SND_HDA_I915
3423static void azx_probe_work(struct work_struct *work)
3424{
3425 azx_probe_continue(container_of(work, struct azx, probe_work));
3426}
3427#endif
3428
3401/* 3429/*
3402 * constructor 3430 * constructor
3403 */ 3431 */
@@ -3473,7 +3501,13 @@ static int azx_create(struct snd_card *card, struct pci_dev *pci,
3473 return err; 3501 return err;
3474 } 3502 }
3475 3503
3504#ifdef CONFIG_SND_HDA_I915
3505 /* continue probing in work context as may trigger request module */
3506 INIT_WORK(&chip->probe_work, azx_probe_work);
3507#endif
3508
3476 *rchip = chip; 3509 *rchip = chip;
3510
3477 return 0; 3511 return 0;
3478} 3512}
3479 3513
@@ -3730,11 +3764,6 @@ static int azx_probe(struct pci_dev *pci,
3730 } 3764 }
3731 3765
3732 probe_now = !chip->disabled; 3766 probe_now = !chip->disabled;
3733 if (probe_now) {
3734 err = azx_first_init(chip);
3735 if (err < 0)
3736 goto out_free;
3737 }
3738 3767
3739#ifdef CONFIG_SND_HDA_PATCH_LOADER 3768#ifdef CONFIG_SND_HDA_PATCH_LOADER
3740 if (patch[dev] && *patch[dev]) { 3769 if (patch[dev] && *patch[dev]) {
@@ -3749,15 +3778,22 @@ static int azx_probe(struct pci_dev *pci,
3749 } 3778 }
3750#endif /* CONFIG_SND_HDA_PATCH_LOADER */ 3779#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3751 3780
3781 /* continue probing in work context, avoid request_module deadlock */
3782 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3783#ifdef CONFIG_SND_HDA_I915
3784 probe_now = false;
3785 schedule_work(&chip->probe_work);
3786#else
3787 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3788#endif
3789 }
3790
3752 if (probe_now) { 3791 if (probe_now) {
3753 err = azx_probe_continue(chip); 3792 err = azx_probe_continue(chip);
3754 if (err < 0) 3793 if (err < 0)
3755 goto out_free; 3794 goto out_free;
3756 } 3795 }
3757 3796
3758 if (pci_dev_run_wake(pci))
3759 pm_runtime_put_noidle(&pci->dev);
3760
3761 dev++; 3797 dev++;
3762 complete_all(&chip->probe_wait); 3798 complete_all(&chip->probe_wait);
3763 return 0; 3799 return 0;
@@ -3770,9 +3806,24 @@ out_free:
3770 3806
3771static int azx_probe_continue(struct azx *chip) 3807static int azx_probe_continue(struct azx *chip)
3772{ 3808{
3809 struct pci_dev *pci = chip->pci;
3773 int dev = chip->dev_index; 3810 int dev = chip->dev_index;
3774 int err; 3811 int err;
3775 3812
3813 /* Request power well for Haswell HDA controller and codec */
3814 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3815 err = hda_i915_init();
3816 if (err < 0) {
3817 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3818 goto out_free;
3819 }
3820 hda_display_power(true);
3821 }
3822
3823 err = azx_first_init(chip);
3824 if (err < 0)
3825 goto out_free;
3826
3776#ifdef CONFIG_SND_HDA_INPUT_BEEP 3827#ifdef CONFIG_SND_HDA_INPUT_BEEP
3777 chip->beep_mode = beep_mode[dev]; 3828 chip->beep_mode = beep_mode[dev];
3778#endif 3829#endif
@@ -3817,6 +3868,8 @@ static int azx_probe_continue(struct azx *chip)
3817 power_down_all_codecs(chip); 3868 power_down_all_codecs(chip);
3818 azx_notifier_register(chip); 3869 azx_notifier_register(chip);
3819 azx_add_card_list(chip); 3870 azx_add_card_list(chip);
3871 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3872 pm_runtime_put_noidle(&pci->dev);
3820 3873
3821 return 0; 3874 return 0;
3822 3875
@@ -3829,9 +3882,6 @@ static void azx_remove(struct pci_dev *pci)
3829{ 3882{
3830 struct snd_card *card = pci_get_drvdata(pci); 3883 struct snd_card *card = pci_get_drvdata(pci);
3831 3884
3832 if (pci_dev_run_wake(pci))
3833 pm_runtime_get_noresume(&pci->dev);
3834
3835 if (card) 3885 if (card)
3836 snd_card_free(card); 3886 snd_card_free(card);
3837 pci_set_drvdata(pci, NULL); 3887 pci_set_drvdata(pci, NULL);
@@ -3864,11 +3914,14 @@ static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3864 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3914 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3865 /* Haswell */ 3915 /* Haswell */
3866 { PCI_DEVICE(0x8086, 0x0a0c), 3916 { PCI_DEVICE(0x8086, 0x0a0c),
3867 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3917 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3918 AZX_DCAPS_I915_POWERWELL },
3868 { PCI_DEVICE(0x8086, 0x0c0c), 3919 { PCI_DEVICE(0x8086, 0x0c0c),
3869 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3920 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3921 AZX_DCAPS_I915_POWERWELL },
3870 { PCI_DEVICE(0x8086, 0x0d0c), 3922 { PCI_DEVICE(0x8086, 0x0d0c),
3871 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH }, 3923 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3924 AZX_DCAPS_I915_POWERWELL },
3872 /* 5 Series/3400 */ 3925 /* 5 Series/3400 */
3873 { PCI_DEVICE(0x8086, 0x3b56), 3926 { PCI_DEVICE(0x8086, 0x3b56),
3874 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3927 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 01:27:04 -0500