diff options
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_common_data.c | 9 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/omap_hwmod.h | 10 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 51e5418899fb..6dd922ef80cc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c | |||
@@ -49,6 +49,15 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { | |||
49 | .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, | 49 | .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, |
50 | }; | 50 | }; |
51 | 51 | ||
52 | /** | ||
53 | * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme. | ||
54 | * Used by some IPs on AM33xx | ||
55 | */ | ||
56 | struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = { | ||
57 | .midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT, | ||
58 | .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT, | ||
59 | }; | ||
60 | |||
52 | struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { | 61 | struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { |
53 | .manager_count = 2, | 62 | .manager_count = 2, |
54 | .has_framedonetv_irq = 0 | 63 | .has_framedonetv_irq = 0 |
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff5..2c1710386963 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
@@ -41,6 +41,7 @@ struct omap_device; | |||
41 | 41 | ||
42 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; | 42 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; |
43 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; | 43 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; |
44 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; | ||
44 | 45 | ||
45 | /* | 46 | /* |
46 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant | 47 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant |
@@ -70,6 +71,15 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; | |||
70 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | 71 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 |
71 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | 72 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) |
72 | 73 | ||
74 | /* | ||
75 | * OCP SYSCONFIG bit shifts/masks TYPE3. | ||
76 | * This is applicable for some IPs present in AM33XX | ||
77 | */ | ||
78 | #define SYSC_TYPE3_SIDLEMODE_SHIFT 0 | ||
79 | #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) | ||
80 | #define SYSC_TYPE3_MIDLEMODE_SHIFT 2 | ||
81 | #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) | ||
82 | |||
73 | /* OCP SYSSTATUS bit shifts/masks */ | 83 | /* OCP SYSSTATUS bit shifts/masks */ |
74 | #define SYSS_RESETDONE_SHIFT 0 | 84 | #define SYSS_RESETDONE_SHIFT 0 |
75 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) | 85 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) |