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-rw-r--r--arch/arm/mach-omap1/mcbsp.c18
-rw-r--r--arch/arm/mach-omap2/Makefile16
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c3
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c24
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpll.c63
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c14
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c91
-rw-r--r--arch/arm/mach-omap2/clkt_iclk.c82
-rw-r--r--arch/arm/mach-omap2/clock.c28
-rw-r--r--arch/arm/mach-omap2/clock.h21
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c221
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c232
-rw-r--r--arch/arm/mach-omap2/clock34xx.c29
-rw-r--r--arch/arm/mach-omap2/clock34xx.h5
-rw-r--r--arch/arm/mach-omap2/clock3517.c4
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c3
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c165
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c57
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain.c439
-rw-r--r--arch/arm/mach-omap2/clockdomain.h70
-rw-r--r--arch/arm/mach-omap2/clockdomain2xxx_3xxx.c274
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c137
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c12
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c396
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h3
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.c69
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h8
-rw-r--r--arch/arm/mach-omap2/cm44xx.h1
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c21
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h6
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c4
-rw-r--r--arch/arm/mach-omap2/devices.c64
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c84
-rw-r--r--arch/arm/mach-omap2/io.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c78
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c56
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c38
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c253
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h132
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c314
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h338
-rw-r--r--arch/arm/mach-omap2/pm.c6
-rw-r--r--arch/arm/mach-omap2/pm24xx.c77
-rw-r--r--arch/arm/mach-omap2/pm34xx.c128
-rw-r--r--arch/arm/mach-omap2/powerdomain.c43
-rw-r--r--arch/arm/mach-omap2/powerdomain.h19
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c9
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_data.c18
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c38
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c88
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h4
-rw-r--r--arch/arm/plat-omap/clock.c99
-rw-r--r--arch/arm/plat-omap/dmtimer.c4
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h27
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h3
-rw-r--r--arch/arm/plat-omap/omap_device.c36
-rw-r--r--drivers/mmc/host/omap_hsmmc.c6
-rw-r--r--drivers/watchdog/omap_wdt.c25
62 files changed, 3416 insertions, 1103 deletions
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index e68f6c012fde..d9af9811dedd 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -136,6 +136,8 @@ struct resource omap7xx_mcbsp_res[][6] = {
136 }, 136 },
137}; 137};
138 138
139#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
140
139static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { 141static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
140 { 142 {
141 .ops = &omap1_mcbsp_ops, 143 .ops = &omap1_mcbsp_ops,
@@ -147,7 +149,7 @@ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
147#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) 149#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
148#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) 150#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
149#else 151#else
150#define omap7xx_mcbsp_res NULL 152#define omap7xx_mcbsp_res_0 NULL
151#define omap7xx_mcbsp_pdata NULL 153#define omap7xx_mcbsp_pdata NULL
152#define OMAP7XX_MCBSP_RES_SZ 0 154#define OMAP7XX_MCBSP_RES_SZ 0
153#define OMAP7XX_MCBSP_COUNT 0 155#define OMAP7XX_MCBSP_COUNT 0
@@ -238,6 +240,8 @@ struct resource omap15xx_mcbsp_res[][6] = {
238 }, 240 },
239}; 241};
240 242
243#define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
244
241static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 245static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
242 { 246 {
243 .ops = &omap1_mcbsp_ops, 247 .ops = &omap1_mcbsp_ops,
@@ -252,7 +256,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
252#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1]) 256#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
253#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res) 257#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
254#else 258#else
255#define omap15xx_mcbsp_res NULL 259#define omap15xx_mcbsp_res_0 NULL
256#define omap15xx_mcbsp_pdata NULL 260#define omap15xx_mcbsp_pdata NULL
257#define OMAP15XX_MCBSP_RES_SZ 0 261#define OMAP15XX_MCBSP_RES_SZ 0
258#define OMAP15XX_MCBSP_COUNT 0 262#define OMAP15XX_MCBSP_COUNT 0
@@ -343,6 +347,8 @@ struct resource omap16xx_mcbsp_res[][6] = {
343 }, 347 },
344}; 348};
345 349
350#define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
351
346static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 352static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
347 { 353 {
348 .ops = &omap1_mcbsp_ops, 354 .ops = &omap1_mcbsp_ops,
@@ -357,7 +363,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
357#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1]) 363#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
358#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res) 364#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
359#else 365#else
360#define omap16xx_mcbsp_res NULL 366#define omap16xx_mcbsp_res_0 NULL
361#define omap16xx_mcbsp_pdata NULL 367#define omap16xx_mcbsp_pdata NULL
362#define OMAP16XX_MCBSP_RES_SZ 0 368#define OMAP16XX_MCBSP_RES_SZ 0
363#define OMAP16XX_MCBSP_COUNT 0 369#define OMAP16XX_MCBSP_COUNT 0
@@ -381,19 +387,19 @@ static int __init omap1_mcbsp_init(void)
381 return -ENOMEM; 387 return -ENOMEM;
382 388
383 if (cpu_is_omap7xx()) 389 if (cpu_is_omap7xx())
384 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0], 390 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
385 OMAP7XX_MCBSP_RES_SZ, 391 OMAP7XX_MCBSP_RES_SZ,
386 omap7xx_mcbsp_pdata, 392 omap7xx_mcbsp_pdata,
387 OMAP7XX_MCBSP_COUNT); 393 OMAP7XX_MCBSP_COUNT);
388 394
389 if (cpu_is_omap15xx()) 395 if (cpu_is_omap15xx())
390 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0], 396 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
391 OMAP15XX_MCBSP_RES_SZ, 397 OMAP15XX_MCBSP_RES_SZ,
392 omap15xx_mcbsp_pdata, 398 omap15xx_mcbsp_pdata,
393 OMAP15XX_MCBSP_COUNT); 399 OMAP15XX_MCBSP_COUNT);
394 400
395 if (cpu_is_omap16xx()) 401 if (cpu_is_omap16xx())
396 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0], 402 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
397 OMAP16XX_MCBSP_RES_SZ, 403 OMAP16XX_MCBSP_RES_SZ,
398 omap16xx_mcbsp_pdata, 404 omap16xx_mcbsp_pdata,
399 OMAP16XX_MCBSP_COUNT); 405 OMAP16XX_MCBSP_COUNT);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1c3635d7f4cf..534d89a60dd9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -102,25 +102,31 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
102 102
103# PRCM clockdomain control 103# PRCM clockdomain control
104obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ 104obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
105 clockdomain2xxx_3xxx.o \
105 clockdomains2xxx_3xxx_data.o 106 clockdomains2xxx_3xxx_data.o
106obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ 107obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
108 clockdomain2xxx_3xxx.o \
107 clockdomains2xxx_3xxx_data.o 109 clockdomains2xxx_3xxx_data.o
108obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ 110obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
111 clockdomain44xx.o \
109 clockdomains44xx_data.o 112 clockdomains44xx_data.o
113
110# Clock framework 114# Clock framework
111obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ 115obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
112 clkt2xxx_sys.o \ 116 clkt2xxx_sys.o \
113 clkt2xxx_dpllcore.o \ 117 clkt2xxx_dpllcore.o \
114 clkt2xxx_virt_prcm_set.o \ 118 clkt2xxx_virt_prcm_set.o \
115 clkt2xxx_apll.o clkt2xxx_osc.o 119 clkt2xxx_apll.o clkt2xxx_osc.o \
120 clkt2xxx_dpll.o clkt_iclk.o
116obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o 121obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
117obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o 122obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
118obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ 123obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
119 clock34xx.o clkt34xx_dpll3m2.o \ 124 clock34xx.o clkt34xx_dpll3m2.o \
120 clock3517.o clock36xx.o \ 125 clock3517.o clock36xx.o \
121 dpll3xxx.o clock3xxx_data.o 126 dpll3xxx.o clock3xxx_data.o \
127 clkt_iclk.o
122obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ 128obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
123 dpll3xxx.o 129 dpll3xxx.o dpll44xx.o
124 130
125# OMAP2 clock rate set data (old "OPP" data) 131# OMAP2 clock rate set data (old "OPP" data)
126obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o 132obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
@@ -135,6 +141,10 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
135# EMU peripherals 141# EMU peripherals
136obj-$(CONFIG_OMAP3_EMU) += emu.o 142obj-$(CONFIG_OMAP3_EMU) += emu.o
137 143
144# L3 interconnect
145obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
146obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
147
138obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 148obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
139mailbox_mach-objs := mailbox.o 149mailbox_mach-objs := mailbox.o
140 150
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 30ec45193268..77541cf59bd4 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -200,6 +200,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
200}; 200};
201static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = { 201static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
202 { 202 {
203 I2C_BOARD_INFO("tlv320aic23", 0x1A),
204 },
205 {
203 I2C_BOARD_INFO("tca6416", 0x21), 206 I2C_BOARD_INFO("tca6416", 0x21),
204 .platform_data = &am3517evm_gpio_expander_info_0, 207 .platform_data = &am3517evm_gpio_expander_info_0,
205 }, 208 },
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index f51cffd1fc53..b19a1f7234ae 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); 78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
79} 79}
80 80
81static void _apll96_allow_idle(struct clk *clk)
82{
83 omap2xxx_cm_set_apll96_auto_low_power_stop();
84}
85
86static void _apll96_deny_idle(struct clk *clk)
87{
88 omap2xxx_cm_set_apll96_disable_autoidle();
89}
90
91static void _apll54_allow_idle(struct clk *clk)
92{
93 omap2xxx_cm_set_apll54_auto_low_power_stop();
94}
95
96static void _apll54_deny_idle(struct clk *clk)
97{
98 omap2xxx_cm_set_apll54_disable_autoidle();
99}
100
81/* Stop APLL */ 101/* Stop APLL */
82static void omap2_clk_apll_disable(struct clk *clk) 102static void omap2_clk_apll_disable(struct clk *clk)
83{ 103{
@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
93const struct clkops clkops_apll96 = { 113const struct clkops clkops_apll96 = {
94 .enable = omap2_clk_apll96_enable, 114 .enable = omap2_clk_apll96_enable,
95 .disable = omap2_clk_apll_disable, 115 .disable = omap2_clk_apll_disable,
116 .allow_idle = _apll96_allow_idle,
117 .deny_idle = _apll96_deny_idle,
96}; 118};
97 119
98const struct clkops clkops_apll54 = { 120const struct clkops clkops_apll54 = {
99 .enable = omap2_clk_apll54_enable, 121 .enable = omap2_clk_apll54_enable,
100 .disable = omap2_clk_apll_disable, 122 .disable = omap2_clk_apll_disable,
123 .allow_idle = _apll54_allow_idle,
124 .deny_idle = _apll54_deny_idle,
101}; 125};
102 126
103/* Public functions */ 127/* Public functions */
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
new file mode 100644
index 000000000000..1502a7bc20bb
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -0,0 +1,63 @@
1/*
2 * OMAP2-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16
17#include <plat/clock.h>
18
19#include "clock.h"
20#include "cm2xxx_3xxx.h"
21#include "cm-regbits-24xx.h"
22
23/* Private functions */
24
25/**
26 * _allow_idle - enable DPLL autoidle bits
27 * @clk: struct clk * of the DPLL to operate on
28 *
29 * Enable DPLL automatic idle control. The DPLL will enter low-power
30 * stop when its downstream clocks are gated. No return value.
31 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
32 * instead. Add some mechanism to optionally enter this mode.
33 */
34static void _allow_idle(struct clk *clk)
35{
36 if (!clk || !clk->dpll_data)
37 return;
38
39 omap2xxx_cm_set_dpll_auto_low_power_stop();
40}
41
42/**
43 * _deny_idle - prevent DPLL from automatically idling
44 * @clk: struct clk * of the DPLL to operate on
45 *
46 * Disable DPLL automatic idle control. No return value.
47 */
48static void _deny_idle(struct clk *clk)
49{
50 if (!clk || !clk->dpll_data)
51 return;
52
53 omap2xxx_cm_set_dpll_disable_autoidle();
54}
55
56
57/* Public data */
58
59const struct clkops clkops_omap2xxx_dpll_ops = {
60 .allow_idle = _allow_idle,
61 .deny_idle = _deny_idle,
62};
63
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index df7b80506483..c3460928b5e0 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -30,6 +30,13 @@
30#include "prm2xxx_3xxx.h" 30#include "prm2xxx_3xxx.h"
31#include "prm-regbits-24xx.h" 31#include "prm-regbits-24xx.h"
32 32
33/*
34 * XXX This does not actually enable the osc_ck, since the osc_ck must
35 * be running for this function to be called. Instead, this function
36 * is used to disable an autoidle mode on the osc_ck. The existing
37 * clk_enable/clk_disable()-based usecounting for osc_ck should be
38 * replaced with autoidle-based usecounting.
39 */
33static int omap2_enable_osc_ck(struct clk *clk) 40static int omap2_enable_osc_ck(struct clk *clk)
34{ 41{
35 u32 pcc; 42 u32 pcc;
@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
41 return 0; 48 return 0;
42} 49}
43 50
51/*
52 * XXX This does not actually disable the osc_ck, since doing so would
53 * immediately halt the system. Instead, this function is used to
54 * enable an autoidle mode on the osc_ck. The existing
55 * clk_enable/clk_disable()-based usecounting for osc_ck should be
56 * replaced with autoidle-based usecounting.
57 */
44static void omap2_disable_osc_ck(struct clk *clk) 58static void omap2_disable_osc_ck(struct clk *clk)
45{ 59{
46 u32 pcc; 60 u32 pcc;
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index acb7ae5b0a25..bcffee001bfa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
178 if (!dd) 178 if (!dd)
179 return; 179 return;
180 180
181 /* Return bypass rate if DPLL is bypassed */
182 v = __raw_readl(dd->control_reg); 181 v = __raw_readl(dd->control_reg);
183 v &= dd->enable_mask; 182 v &= dd->enable_mask;
184 v >>= __ffs(dd->enable_mask); 183 v >>= __ffs(dd->enable_mask);
185 184
186 /* Reparent in case the dpll is in bypass */ 185 /* Reparent the struct clk in case the dpll is in bypass */
187 if (cpu_is_omap24xx()) { 186 if (cpu_is_omap24xx()) {
188 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 187 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
189 v == OMAP2XXX_EN_DPLL_FRBYPASS) 188 v == OMAP2XXX_EN_DPLL_FRBYPASS)
@@ -260,50 +259,22 @@ u32 omap2_get_dpll_rate(struct clk *clk)
260/* DPLL rate rounding code */ 259/* DPLL rate rounding code */
261 260
262/** 261/**
263 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
264 * @clk: struct clk * of the DPLL
265 * @tolerance: maximum rate error tolerance
266 *
267 * Set the maximum DPLL rate error tolerance for the rate rounding
268 * algorithm. The rate tolerance is an attempt to balance DPLL power
269 * saving (the least divider value "n") vs. rate fidelity (the least
270 * difference between the desired DPLL target rate and the rounded
271 * rate out of the algorithm). So, increasing the tolerance is likely
272 * to decrease DPLL power consumption and increase DPLL rate error.
273 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
274 * DPLL; or 0 upon success.
275 */
276int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
277{
278 if (!clk || !clk->dpll_data)
279 return -EINVAL;
280
281 clk->dpll_data->rate_tolerance = tolerance;
282
283 return 0;
284}
285
286/**
287 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 262 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
288 * @clk: struct clk * for a DPLL 263 * @clk: struct clk * for a DPLL
289 * @target_rate: desired DPLL clock rate 264 * @target_rate: desired DPLL clock rate
290 * 265 *
291 * Given a DPLL, a desired target rate, and a rate tolerance, round 266 * Given a DPLL and a desired target rate, round the target rate to a
292 * the target rate to a possible, programmable rate for this DPLL. 267 * possible, programmable rate for this DPLL. Attempts to select the
293 * Rate tolerance is assumed to be set by the caller before this 268 * minimum possible n. Stores the computed (m, n) in the DPLL's
294 * function is called. Attempts to select the minimum possible n 269 * dpll_data structure so set_rate() will not need to call this
295 * within the tolerance to reduce power consumption. Stores the 270 * (expensive) function again. Returns ~0 if the target rate cannot
296 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 271 * be rounded, or the rounded rate upon success.
297 * will not need to call this (expensive) function again. Returns ~0
298 * if the target rate cannot be rounded, either because the rate is
299 * too low or because the rate tolerance is set too tightly; or the
300 * rounded rate upon success.
301 */ 272 */
302long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 273long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
303{ 274{
304 int m, n, r, e, scaled_max_m; 275 int m, n, r, scaled_max_m;
305 unsigned long scaled_rt_rp, new_rate; 276 unsigned long scaled_rt_rp;
306 int min_e = -1, min_e_m = -1, min_e_n = -1; 277 unsigned long new_rate = 0;
307 struct dpll_data *dd; 278 struct dpll_data *dd;
308 279
309 if (!clk || !clk->dpll_data) 280 if (!clk || !clk->dpll_data)
@@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
311 282
312 dd = clk->dpll_data; 283 dd = clk->dpll_data;
313 284
314 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 285 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
315 "%ld\n", clk->name, target_rate); 286 clk->name, target_rate);
316 287
317 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 288 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
318 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 289 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
@@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
347 if (r == DPLL_MULT_UNDERFLOW) 318 if (r == DPLL_MULT_UNDERFLOW)
348 continue; 319 continue;
349 320
350 e = target_rate - new_rate; 321 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
351 pr_debug("clock: n = %d: m = %d: rate error is %d " 322 clk->name, m, n, new_rate);
352 "(new_rate = %ld)\n", n, m, e, new_rate);
353
354 if (min_e == -1 ||
355 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
356 min_e = e;
357 min_e_m = m;
358 min_e_n = n;
359
360 pr_debug("clock: found new least error %d\n", min_e);
361 323
362 /* We found good settings -- bail out now */ 324 if (target_rate == new_rate) {
363 if (min_e <= dd->rate_tolerance) 325 dd->last_rounded_m = m;
364 break; 326 dd->last_rounded_n = n;
327 dd->last_rounded_rate = target_rate;
328 break;
365 } 329 }
366 } 330 }
367 331
368 if (min_e < 0) { 332 if (target_rate != new_rate) {
369 pr_debug("clock: error: target rate or tolerance too low\n"); 333 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
334 target_rate);
370 return ~0; 335 return ~0;
371 } 336 }
372 337
373 dd->last_rounded_m = min_e_m; 338 return target_rate;
374 dd->last_rounded_n = min_e_n;
375 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
376 min_e_m, min_e_n);
377
378 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
379 min_e, min_e_m, min_e_n);
380 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
381 dd->last_rounded_rate, target_rate);
382
383 return dd->last_rounded_rate;
384} 339}
385 340
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
new file mode 100644
index 000000000000..3d43fba2542f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -0,0 +1,82 @@
1/*
2 * OMAP2/3 interface clock control
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#undef DEBUG
12
13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16
17#include <plat/clock.h>
18#include <plat/prcm.h>
19
20#include "clock.h"
21#include "clock2xxx.h"
22#include "cm2xxx_3xxx.h"
23#include "cm-regbits-24xx.h"
24
25/* Private functions */
26
27/* XXX */
28void omap2_clkt_iclk_allow_idle(struct clk *clk)
29{
30 u32 v, r;
31
32 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
33
34 v = __raw_readl((__force void __iomem *)r);
35 v |= (1 << clk->enable_bit);
36 __raw_writel(v, (__force void __iomem *)r);
37}
38
39/* XXX */
40void omap2_clkt_iclk_deny_idle(struct clk *clk)
41{
42 u32 v, r;
43
44 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
45
46 v = __raw_readl((__force void __iomem *)r);
47 v &= ~(1 << clk->enable_bit);
48 __raw_writel(v, (__force void __iomem *)r);
49}
50
51/* Public data */
52
53const struct clkops clkops_omap2_iclk_dflt_wait = {
54 .enable = omap2_dflt_clk_enable,
55 .disable = omap2_dflt_clk_disable,
56 .find_companion = omap2_clk_dflt_find_companion,
57 .find_idlest = omap2_clk_dflt_find_idlest,
58 .allow_idle = omap2_clkt_iclk_allow_idle,
59 .deny_idle = omap2_clkt_iclk_deny_idle,
60};
61
62const struct clkops clkops_omap2_iclk_dflt = {
63 .enable = omap2_dflt_clk_enable,
64 .disable = omap2_dflt_clk_disable,
65 .allow_idle = omap2_clkt_iclk_allow_idle,
66 .deny_idle = omap2_clkt_iclk_deny_idle,
67};
68
69const struct clkops clkops_omap2_iclk_idle_only = {
70 .allow_idle = omap2_clkt_iclk_allow_idle,
71 .deny_idle = omap2_clkt_iclk_deny_idle,
72};
73
74const struct clkops clkops_omap2_mdmclk_dflt_wait = {
75 .enable = omap2_dflt_clk_enable,
76 .disable = omap2_dflt_clk_disable,
77 .find_companion = omap2_clk_dflt_find_companion,
78 .find_idlest = omap2_clk_dflt_find_idlest,
79 .allow_idle = omap2_clkt_iclk_allow_idle,
80 .deny_idle = omap2_clkt_iclk_deny_idle,
81};
82
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2a2f15213add..46d03ccc2806 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -261,10 +261,11 @@ void omap2_clk_disable(struct clk *clk)
261 261
262 pr_debug("clock: %s: disabling in hardware\n", clk->name); 262 pr_debug("clock: %s: disabling in hardware\n", clk->name);
263 263
264 clk->ops->disable(clk); 264 if (clk->ops && clk->ops->disable)
265 clk->ops->disable(clk);
265 266
266 if (clk->clkdm) 267 if (clk->clkdm)
267 omap2_clkdm_clk_disable(clk->clkdm, clk); 268 clkdm_clk_disable(clk->clkdm, clk);
268 269
269 if (clk->parent) 270 if (clk->parent)
270 omap2_clk_disable(clk->parent); 271 omap2_clk_disable(clk->parent);
@@ -304,7 +305,7 @@ int omap2_clk_enable(struct clk *clk)
304 } 305 }
305 306
306 if (clk->clkdm) { 307 if (clk->clkdm) {
307 ret = omap2_clkdm_clk_enable(clk->clkdm, clk); 308 ret = clkdm_clk_enable(clk->clkdm, clk);
308 if (ret) { 309 if (ret) {
309 WARN(1, "clock: %s: could not enable clockdomain %s: " 310 WARN(1, "clock: %s: could not enable clockdomain %s: "
310 "%d\n", clk->name, clk->clkdm->name, ret); 311 "%d\n", clk->name, clk->clkdm->name, ret);
@@ -312,17 +313,20 @@ int omap2_clk_enable(struct clk *clk)
312 } 313 }
313 } 314 }
314 315
315 ret = clk->ops->enable(clk); 316 if (clk->ops && clk->ops->enable) {
316 if (ret) { 317 ret = clk->ops->enable(clk);
317 WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); 318 if (ret) {
318 goto oce_err3; 319 WARN(1, "clock: %s: could not enable: %d\n",
320 clk->name, ret);
321 goto oce_err3;
322 }
319 } 323 }
320 324
321 return 0; 325 return 0;
322 326
323oce_err3: 327oce_err3:
324 if (clk->clkdm) 328 if (clk->clkdm)
325 omap2_clkdm_clk_disable(clk->clkdm, clk); 329 clkdm_clk_disable(clk->clkdm, clk);
326oce_err2: 330oce_err2:
327 if (clk->parent) 331 if (clk->parent)
328 omap2_clk_disable(clk->parent); 332 omap2_clk_disable(clk->parent);
@@ -373,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
373const struct clkops clkops_omap3_noncore_dpll_ops = { 377const struct clkops clkops_omap3_noncore_dpll_ops = {
374 .enable = omap3_noncore_dpll_enable, 378 .enable = omap3_noncore_dpll_enable,
375 .disable = omap3_noncore_dpll_disable, 379 .disable = omap3_noncore_dpll_disable,
380 .allow_idle = omap3_dpll_allow_idle,
381 .deny_idle = omap3_dpll_deny_idle,
376}; 382};
377 383
378#endif 384const struct clkops clkops_omap3_core_dpll_ops = {
385 .allow_idle = omap3_dpll_allow_idle,
386 .deny_idle = omap3_dpll_deny_idle,
387};
379 388
389#endif
380 390
381/* 391/*
382 * OMAP2+ clock reset and init functions 392 * OMAP2+ clock reset and init functions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 896584e3c4ab..e10ff2b54844 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -2,7 +2,7 @@
2 * linux/arch/arm/mach-omap2/clock.h 2 * linux/arch/arm/mach-omap2/clock.h
3 * 3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation 5 * Copyright (C) 2004-2011 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
@@ -18,9 +18,6 @@
18 18
19#include <plat/clock.h> 19#include <plat/clock.h>
20 20
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
24/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 21/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0 22#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1 23#define CORE_CLK_SRC_DPLL 0x1
@@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
55long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 52long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
56int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 53int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
57int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 54int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
58int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
59long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 55long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
60unsigned long omap3_dpll_recalc(struct clk *clk); 56unsigned long omap3_dpll_recalc(struct clk *clk);
61unsigned long omap3_clkoutx2_recalc(struct clk *clk); 57unsigned long omap3_clkoutx2_recalc(struct clk *clk);
@@ -65,6 +61,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
65int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); 61int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
66int omap3_noncore_dpll_enable(struct clk *clk); 62int omap3_noncore_dpll_enable(struct clk *clk);
67void omap3_noncore_dpll_disable(struct clk *clk); 63void omap3_noncore_dpll_disable(struct clk *clk);
64int omap4_dpllmx_gatectrl_read(struct clk *clk);
65void omap4_dpllmx_allow_gatectrl(struct clk *clk);
66void omap4_dpllmx_deny_gatectrl(struct clk *clk);
68 67
69#ifdef CONFIG_OMAP_RESET_CLOCKS 68#ifdef CONFIG_OMAP_RESET_CLOCKS
70void omap2_clk_disable_unused(struct clk *clk); 69void omap2_clk_disable_unused(struct clk *clk);
@@ -83,6 +82,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
83int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 82int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
84int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); 83int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
85 84
85/* clkt_iclk.c public functions */
86extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
87extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
88
86u32 omap2_get_dpll_rate(struct clk *clk); 89u32 omap2_get_dpll_rate(struct clk *clk);
87void omap2_init_dpll_parent(struct clk *clk); 90void omap2_init_dpll_parent(struct clk *clk);
88 91
@@ -136,6 +139,7 @@ extern struct clk *vclk, *sclk;
136extern const struct clksel_rate gpt_32k_rates[]; 139extern const struct clksel_rate gpt_32k_rates[];
137extern const struct clksel_rate gpt_sys_rates[]; 140extern const struct clksel_rate gpt_sys_rates[];
138extern const struct clksel_rate gfx_l3_rates[]; 141extern const struct clksel_rate gfx_l3_rates[];
142extern const struct clksel_rate dsp_ick_rates[];
139 143
140#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) 144#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
141extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); 145extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
@@ -145,6 +149,13 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
145#define omap2_clk_exit_cpufreq_table 0 149#define omap2_clk_exit_cpufreq_table 0
146#endif 150#endif
147 151
152extern const struct clkops clkops_omap2_iclk_dflt_wait;
153extern const struct clkops clkops_omap2_iclk_dflt;
154extern const struct clkops clkops_omap2_iclk_idle_only;
155extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
156extern const struct clkops clkops_omap2xxx_dpll_ops;
148extern const struct clkops clkops_omap3_noncore_dpll_ops; 157extern const struct clkops clkops_omap3_noncore_dpll_ops;
158extern const struct clkops clkops_omap3_core_dpll_ops;
159extern const struct clkops clkops_omap4_dpllmx_ops;
149 160
150#endif 161#endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 0a992bc8d0d8..b6f65d4ac97d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1,12 +1,12 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock2420_data.c 2 * OMAP2420 clock data
3 * 3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation 5 * Copyright (C) 2004-2011 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -34,18 +34,15 @@
34/* 34/*
35 * 2420 clock tree. 35 * 2420 clock tree.
36 * 36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In many 37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * cases the parent is selectable. The get/set parent calls will also 38 * many cases the parent is selectable. The set parent calls will
39 * switch sources. 39 * also switch sources.
40 *
41 * Many some clocks say always_enabled, but they can be auto idled for
42 * power savings. They will always be available upon clock request.
43 * 40 *
44 * Several sources are given initial rates which may be wrong, this will 41 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func. 42 * be fixed up in the init func.
46 * 43 *
47 * Things are broadly separated below by clock domains. It is 44 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most periferals have dependencies on multiple clock 45 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get 46 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived 47 * functional clocks from fixed sources or other core domain derived
51 * clocks. 48 * clocks.
@@ -55,7 +52,7 @@
55static struct clk func_32k_ck = { 52static struct clk func_32k_ck = {
56 .name = "func_32k_ck", 53 .name = "func_32k_ck",
57 .ops = &clkops_null, 54 .ops = &clkops_null,
58 .rate = 32000, 55 .rate = 32768,
59 .clkdm_name = "wkup_clkdm", 56 .clkdm_name = "wkup_clkdm",
60}; 57};
61 58
@@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
116 .max_multiplier = 1023, 113 .max_multiplier = 1023,
117 .min_divider = 1, 114 .min_divider = 1,
118 .max_divider = 16, 115 .max_divider = 16,
119 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
120}; 116};
121 117
122/* 118/*
@@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
125 */ 121 */
126static struct clk dpll_ck = { 122static struct clk dpll_ck = {
127 .name = "dpll_ck", 123 .name = "dpll_ck",
128 .ops = &clkops_null, 124 .ops = &clkops_omap2xxx_dpll_ops,
129 .parent = &sys_ck, /* Can be func_32k also */ 125 .parent = &sys_ck, /* Can be func_32k also */
130 .dpll_data = &dpll_dd, 126 .dpll_data = &dpll_dd,
131 .clkdm_name = "wkup_clkdm", 127 .clkdm_name = "wkup_clkdm",
@@ -455,36 +451,22 @@ static struct clk dsp_fck = {
455 .recalc = &omap2_clksel_recalc, 451 .recalc = &omap2_clksel_recalc,
456}; 452};
457 453
458/* DSP interface clock */ 454static const struct clksel dsp_ick_clksel[] = {
459static const struct clksel_rate dsp_irate_ick_rates[] = { 455 { .parent = &dsp_fck, .rates = dsp_ick_rates },
460 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
461 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
462 { .div = 0 },
463};
464
465static const struct clksel dsp_irate_ick_clksel[] = {
466 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
467 { .parent = NULL } 456 { .parent = NULL }
468}; 457};
469 458
470/* This clock does not exist as such in the TRM. */
471static struct clk dsp_irate_ick = {
472 .name = "dsp_irate_ick",
473 .ops = &clkops_null,
474 .parent = &dsp_fck,
475 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
476 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
477 .clksel = dsp_irate_ick_clksel,
478 .recalc = &omap2_clksel_recalc,
479};
480
481/* 2420 only */
482static struct clk dsp_ick = { 459static struct clk dsp_ick = {
483 .name = "dsp_ick", /* apparently ipi and isp */ 460 .name = "dsp_ick", /* apparently ipi and isp */
484 .ops = &clkops_omap2_dflt_wait, 461 .ops = &clkops_omap2_iclk_dflt_wait,
485 .parent = &dsp_irate_ick, 462 .parent = &dsp_fck,
463 .clkdm_name = "dsp_clkdm",
486 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 464 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
487 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 465 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
466 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
467 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
468 .clksel = dsp_ick_clksel,
469 .recalc = &omap2_clksel_recalc,
488}; 470};
489 471
490/* 472/*
@@ -579,7 +561,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
579/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 561/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
580static struct clk usb_l4_ick = { /* FS-USB interface clock */ 562static struct clk usb_l4_ick = { /* FS-USB interface clock */
581 .name = "usb_l4_ick", 563 .name = "usb_l4_ick",
582 .ops = &clkops_omap2_dflt_wait, 564 .ops = &clkops_omap2_iclk_dflt_wait,
583 .parent = &core_l3_ck, 565 .parent = &core_l3_ck,
584 .clkdm_name = "core_l4_clkdm", 566 .clkdm_name = "core_l4_clkdm",
585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,7 +643,7 @@ static struct clk ssi_ssr_sst_fck = {
661 */ 643 */
662static struct clk ssi_l4_ick = { 644static struct clk ssi_l4_ick = {
663 .name = "ssi_l4_ick", 645 .name = "ssi_l4_ick",
664 .ops = &clkops_omap2_dflt_wait, 646 .ops = &clkops_omap2_iclk_dflt_wait,
665 .parent = &l4_ck, 647 .parent = &l4_ck,
666 .clkdm_name = "core_l4_clkdm", 648 .clkdm_name = "core_l4_clkdm",
667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -716,6 +698,7 @@ static struct clk gfx_2d_fck = {
716 .recalc = &omap2_clksel_recalc, 698 .recalc = &omap2_clksel_recalc,
717}; 699};
718 700
701/* This interface clock does not have a CM_AUTOIDLE bit */
719static struct clk gfx_ick = { 702static struct clk gfx_ick = {
720 .name = "gfx_ick", /* From l3 */ 703 .name = "gfx_ick", /* From l3 */
721 .ops = &clkops_omap2_dflt_wait, 704 .ops = &clkops_omap2_dflt_wait,
@@ -763,7 +746,7 @@ static const struct clksel dss1_fck_clksel[] = {
763 746
764static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 747static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
765 .name = "dss_ick", 748 .name = "dss_ick",
766 .ops = &clkops_omap2_dflt, 749 .ops = &clkops_omap2_iclk_dflt,
767 .parent = &l4_ck, /* really both l3 and l4 */ 750 .parent = &l4_ck, /* really both l3 and l4 */
768 .clkdm_name = "dss_clkdm", 751 .clkdm_name = "dss_clkdm",
769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -825,6 +808,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
825 .recalc = &followparent_recalc, 808 .recalc = &followparent_recalc,
826}; 809};
827 810
811static struct clk wu_l4_ick = {
812 .name = "wu_l4_ick",
813 .ops = &clkops_null,
814 .parent = &sys_ck,
815 .clkdm_name = "wkup_clkdm",
816 .recalc = &followparent_recalc,
817};
818
828/* 819/*
829 * CORE power domain ICLK & FCLK defines. 820 * CORE power domain ICLK & FCLK defines.
830 * Many of the these can have more than one possible parent. Entries 821 * Many of the these can have more than one possible parent. Entries
@@ -845,9 +836,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
845 836
846static struct clk gpt1_ick = { 837static struct clk gpt1_ick = {
847 .name = "gpt1_ick", 838 .name = "gpt1_ick",
848 .ops = &clkops_omap2_dflt_wait, 839 .ops = &clkops_omap2_iclk_dflt_wait,
849 .parent = &l4_ck, 840 .parent = &wu_l4_ick,
850 .clkdm_name = "core_l4_clkdm", 841 .clkdm_name = "wkup_clkdm",
851 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 842 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
852 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 843 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
853 .recalc = &followparent_recalc, 844 .recalc = &followparent_recalc,
@@ -871,7 +862,7 @@ static struct clk gpt1_fck = {
871 862
872static struct clk gpt2_ick = { 863static struct clk gpt2_ick = {
873 .name = "gpt2_ick", 864 .name = "gpt2_ick",
874 .ops = &clkops_omap2_dflt_wait, 865 .ops = &clkops_omap2_iclk_dflt_wait,
875 .parent = &l4_ck, 866 .parent = &l4_ck,
876 .clkdm_name = "core_l4_clkdm", 867 .clkdm_name = "core_l4_clkdm",
877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -895,7 +886,7 @@ static struct clk gpt2_fck = {
895 886
896static struct clk gpt3_ick = { 887static struct clk gpt3_ick = {
897 .name = "gpt3_ick", 888 .name = "gpt3_ick",
898 .ops = &clkops_omap2_dflt_wait, 889 .ops = &clkops_omap2_iclk_dflt_wait,
899 .parent = &l4_ck, 890 .parent = &l4_ck,
900 .clkdm_name = "core_l4_clkdm", 891 .clkdm_name = "core_l4_clkdm",
901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -919,7 +910,7 @@ static struct clk gpt3_fck = {
919 910
920static struct clk gpt4_ick = { 911static struct clk gpt4_ick = {
921 .name = "gpt4_ick", 912 .name = "gpt4_ick",
922 .ops = &clkops_omap2_dflt_wait, 913 .ops = &clkops_omap2_iclk_dflt_wait,
923 .parent = &l4_ck, 914 .parent = &l4_ck,
924 .clkdm_name = "core_l4_clkdm", 915 .clkdm_name = "core_l4_clkdm",
925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -943,7 +934,7 @@ static struct clk gpt4_fck = {
943 934
944static struct clk gpt5_ick = { 935static struct clk gpt5_ick = {
945 .name = "gpt5_ick", 936 .name = "gpt5_ick",
946 .ops = &clkops_omap2_dflt_wait, 937 .ops = &clkops_omap2_iclk_dflt_wait,
947 .parent = &l4_ck, 938 .parent = &l4_ck,
948 .clkdm_name = "core_l4_clkdm", 939 .clkdm_name = "core_l4_clkdm",
949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -967,7 +958,7 @@ static struct clk gpt5_fck = {
967 958
968static struct clk gpt6_ick = { 959static struct clk gpt6_ick = {
969 .name = "gpt6_ick", 960 .name = "gpt6_ick",
970 .ops = &clkops_omap2_dflt_wait, 961 .ops = &clkops_omap2_iclk_dflt_wait,
971 .parent = &l4_ck, 962 .parent = &l4_ck,
972 .clkdm_name = "core_l4_clkdm", 963 .clkdm_name = "core_l4_clkdm",
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -991,8 +982,9 @@ static struct clk gpt6_fck = {
991 982
992static struct clk gpt7_ick = { 983static struct clk gpt7_ick = {
993 .name = "gpt7_ick", 984 .name = "gpt7_ick",
994 .ops = &clkops_omap2_dflt_wait, 985 .ops = &clkops_omap2_iclk_dflt_wait,
995 .parent = &l4_ck, 986 .parent = &l4_ck,
987 .clkdm_name = "core_l4_clkdm",
996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 988 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
997 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 989 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
998 .recalc = &followparent_recalc, 990 .recalc = &followparent_recalc,
@@ -1014,7 +1006,7 @@ static struct clk gpt7_fck = {
1014 1006
1015static struct clk gpt8_ick = { 1007static struct clk gpt8_ick = {
1016 .name = "gpt8_ick", 1008 .name = "gpt8_ick",
1017 .ops = &clkops_omap2_dflt_wait, 1009 .ops = &clkops_omap2_iclk_dflt_wait,
1018 .parent = &l4_ck, 1010 .parent = &l4_ck,
1019 .clkdm_name = "core_l4_clkdm", 1011 .clkdm_name = "core_l4_clkdm",
1020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1038,7 +1030,7 @@ static struct clk gpt8_fck = {
1038 1030
1039static struct clk gpt9_ick = { 1031static struct clk gpt9_ick = {
1040 .name = "gpt9_ick", 1032 .name = "gpt9_ick",
1041 .ops = &clkops_omap2_dflt_wait, 1033 .ops = &clkops_omap2_iclk_dflt_wait,
1042 .parent = &l4_ck, 1034 .parent = &l4_ck,
1043 .clkdm_name = "core_l4_clkdm", 1035 .clkdm_name = "core_l4_clkdm",
1044 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1062,7 +1054,7 @@ static struct clk gpt9_fck = {
1062 1054
1063static struct clk gpt10_ick = { 1055static struct clk gpt10_ick = {
1064 .name = "gpt10_ick", 1056 .name = "gpt10_ick",
1065 .ops = &clkops_omap2_dflt_wait, 1057 .ops = &clkops_omap2_iclk_dflt_wait,
1066 .parent = &l4_ck, 1058 .parent = &l4_ck,
1067 .clkdm_name = "core_l4_clkdm", 1059 .clkdm_name = "core_l4_clkdm",
1068 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1086,7 +1078,7 @@ static struct clk gpt10_fck = {
1086 1078
1087static struct clk gpt11_ick = { 1079static struct clk gpt11_ick = {
1088 .name = "gpt11_ick", 1080 .name = "gpt11_ick",
1089 .ops = &clkops_omap2_dflt_wait, 1081 .ops = &clkops_omap2_iclk_dflt_wait,
1090 .parent = &l4_ck, 1082 .parent = &l4_ck,
1091 .clkdm_name = "core_l4_clkdm", 1083 .clkdm_name = "core_l4_clkdm",
1092 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1084 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1110,7 +1102,7 @@ static struct clk gpt11_fck = {
1110 1102
1111static struct clk gpt12_ick = { 1103static struct clk gpt12_ick = {
1112 .name = "gpt12_ick", 1104 .name = "gpt12_ick",
1113 .ops = &clkops_omap2_dflt_wait, 1105 .ops = &clkops_omap2_iclk_dflt_wait,
1114 .parent = &l4_ck, 1106 .parent = &l4_ck,
1115 .clkdm_name = "core_l4_clkdm", 1107 .clkdm_name = "core_l4_clkdm",
1116 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1134,7 +1126,7 @@ static struct clk gpt12_fck = {
1134 1126
1135static struct clk mcbsp1_ick = { 1127static struct clk mcbsp1_ick = {
1136 .name = "mcbsp1_ick", 1128 .name = "mcbsp1_ick",
1137 .ops = &clkops_omap2_dflt_wait, 1129 .ops = &clkops_omap2_iclk_dflt_wait,
1138 .parent = &l4_ck, 1130 .parent = &l4_ck,
1139 .clkdm_name = "core_l4_clkdm", 1131 .clkdm_name = "core_l4_clkdm",
1140 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1132 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1174,7 +1166,7 @@ static struct clk mcbsp1_fck = {
1174 1166
1175static struct clk mcbsp2_ick = { 1167static struct clk mcbsp2_ick = {
1176 .name = "mcbsp2_ick", 1168 .name = "mcbsp2_ick",
1177 .ops = &clkops_omap2_dflt_wait, 1169 .ops = &clkops_omap2_iclk_dflt_wait,
1178 .parent = &l4_ck, 1170 .parent = &l4_ck,
1179 .clkdm_name = "core_l4_clkdm", 1171 .clkdm_name = "core_l4_clkdm",
1180 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1198,7 +1190,7 @@ static struct clk mcbsp2_fck = {
1198 1190
1199static struct clk mcspi1_ick = { 1191static struct clk mcspi1_ick = {
1200 .name = "mcspi1_ick", 1192 .name = "mcspi1_ick",
1201 .ops = &clkops_omap2_dflt_wait, 1193 .ops = &clkops_omap2_iclk_dflt_wait,
1202 .parent = &l4_ck, 1194 .parent = &l4_ck,
1203 .clkdm_name = "core_l4_clkdm", 1195 .clkdm_name = "core_l4_clkdm",
1204 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1218,7 +1210,7 @@ static struct clk mcspi1_fck = {
1218 1210
1219static struct clk mcspi2_ick = { 1211static struct clk mcspi2_ick = {
1220 .name = "mcspi2_ick", 1212 .name = "mcspi2_ick",
1221 .ops = &clkops_omap2_dflt_wait, 1213 .ops = &clkops_omap2_iclk_dflt_wait,
1222 .parent = &l4_ck, 1214 .parent = &l4_ck,
1223 .clkdm_name = "core_l4_clkdm", 1215 .clkdm_name = "core_l4_clkdm",
1224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1238,7 +1230,7 @@ static struct clk mcspi2_fck = {
1238 1230
1239static struct clk uart1_ick = { 1231static struct clk uart1_ick = {
1240 .name = "uart1_ick", 1232 .name = "uart1_ick",
1241 .ops = &clkops_omap2_dflt_wait, 1233 .ops = &clkops_omap2_iclk_dflt_wait,
1242 .parent = &l4_ck, 1234 .parent = &l4_ck,
1243 .clkdm_name = "core_l4_clkdm", 1235 .clkdm_name = "core_l4_clkdm",
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1258,7 +1250,7 @@ static struct clk uart1_fck = {
1258 1250
1259static struct clk uart2_ick = { 1251static struct clk uart2_ick = {
1260 .name = "uart2_ick", 1252 .name = "uart2_ick",
1261 .ops = &clkops_omap2_dflt_wait, 1253 .ops = &clkops_omap2_iclk_dflt_wait,
1262 .parent = &l4_ck, 1254 .parent = &l4_ck,
1263 .clkdm_name = "core_l4_clkdm", 1255 .clkdm_name = "core_l4_clkdm",
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1270,7 @@ static struct clk uart2_fck = {
1278 1270
1279static struct clk uart3_ick = { 1271static struct clk uart3_ick = {
1280 .name = "uart3_ick", 1272 .name = "uart3_ick",
1281 .ops = &clkops_omap2_dflt_wait, 1273 .ops = &clkops_omap2_iclk_dflt_wait,
1282 .parent = &l4_ck, 1274 .parent = &l4_ck,
1283 .clkdm_name = "core_l4_clkdm", 1275 .clkdm_name = "core_l4_clkdm",
1284 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1298,9 +1290,9 @@ static struct clk uart3_fck = {
1298 1290
1299static struct clk gpios_ick = { 1291static struct clk gpios_ick = {
1300 .name = "gpios_ick", 1292 .name = "gpios_ick",
1301 .ops = &clkops_omap2_dflt_wait, 1293 .ops = &clkops_omap2_iclk_dflt_wait,
1302 .parent = &l4_ck, 1294 .parent = &wu_l4_ick,
1303 .clkdm_name = "core_l4_clkdm", 1295 .clkdm_name = "wkup_clkdm",
1304 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1296 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1305 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 1297 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1306 .recalc = &followparent_recalc, 1298 .recalc = &followparent_recalc,
@@ -1318,9 +1310,9 @@ static struct clk gpios_fck = {
1318 1310
1319static struct clk mpu_wdt_ick = { 1311static struct clk mpu_wdt_ick = {
1320 .name = "mpu_wdt_ick", 1312 .name = "mpu_wdt_ick",
1321 .ops = &clkops_omap2_dflt_wait, 1313 .ops = &clkops_omap2_iclk_dflt_wait,
1322 .parent = &l4_ck, 1314 .parent = &wu_l4_ick,
1323 .clkdm_name = "core_l4_clkdm", 1315 .clkdm_name = "wkup_clkdm",
1324 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1316 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1325 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 1317 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1326 .recalc = &followparent_recalc, 1318 .recalc = &followparent_recalc,
@@ -1338,10 +1330,10 @@ static struct clk mpu_wdt_fck = {
1338 1330
1339static struct clk sync_32k_ick = { 1331static struct clk sync_32k_ick = {
1340 .name = "sync_32k_ick", 1332 .name = "sync_32k_ick",
1341 .ops = &clkops_omap2_dflt_wait, 1333 .ops = &clkops_omap2_iclk_dflt_wait,
1342 .parent = &l4_ck, 1334 .parent = &wu_l4_ick,
1335 .clkdm_name = "wkup_clkdm",
1343 .flags = ENABLE_ON_INIT, 1336 .flags = ENABLE_ON_INIT,
1344 .clkdm_name = "core_l4_clkdm",
1345 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1337 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1346 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 1338 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1347 .recalc = &followparent_recalc, 1339 .recalc = &followparent_recalc,
@@ -1349,9 +1341,9 @@ static struct clk sync_32k_ick = {
1349 1341
1350static struct clk wdt1_ick = { 1342static struct clk wdt1_ick = {
1351 .name = "wdt1_ick", 1343 .name = "wdt1_ick",
1352 .ops = &clkops_omap2_dflt_wait, 1344 .ops = &clkops_omap2_iclk_dflt_wait,
1353 .parent = &l4_ck, 1345 .parent = &wu_l4_ick,
1354 .clkdm_name = "core_l4_clkdm", 1346 .clkdm_name = "wkup_clkdm",
1355 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1347 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1356 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 1348 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1357 .recalc = &followparent_recalc, 1349 .recalc = &followparent_recalc,
@@ -1359,10 +1351,10 @@ static struct clk wdt1_ick = {
1359 1351
1360static struct clk omapctrl_ick = { 1352static struct clk omapctrl_ick = {
1361 .name = "omapctrl_ick", 1353 .name = "omapctrl_ick",
1362 .ops = &clkops_omap2_dflt_wait, 1354 .ops = &clkops_omap2_iclk_dflt_wait,
1363 .parent = &l4_ck, 1355 .parent = &wu_l4_ick,
1356 .clkdm_name = "wkup_clkdm",
1364 .flags = ENABLE_ON_INIT, 1357 .flags = ENABLE_ON_INIT,
1365 .clkdm_name = "core_l4_clkdm",
1366 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1358 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1367 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 1359 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1368 .recalc = &followparent_recalc, 1360 .recalc = &followparent_recalc,
@@ -1370,7 +1362,7 @@ static struct clk omapctrl_ick = {
1370 1362
1371static struct clk cam_ick = { 1363static struct clk cam_ick = {
1372 .name = "cam_ick", 1364 .name = "cam_ick",
1373 .ops = &clkops_omap2_dflt, 1365 .ops = &clkops_omap2_iclk_dflt,
1374 .parent = &l4_ck, 1366 .parent = &l4_ck,
1375 .clkdm_name = "core_l4_clkdm", 1367 .clkdm_name = "core_l4_clkdm",
1376 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1395,7 +1387,7 @@ static struct clk cam_fck = {
1395 1387
1396static struct clk mailboxes_ick = { 1388static struct clk mailboxes_ick = {
1397 .name = "mailboxes_ick", 1389 .name = "mailboxes_ick",
1398 .ops = &clkops_omap2_dflt_wait, 1390 .ops = &clkops_omap2_iclk_dflt_wait,
1399 .parent = &l4_ck, 1391 .parent = &l4_ck,
1400 .clkdm_name = "core_l4_clkdm", 1392 .clkdm_name = "core_l4_clkdm",
1401 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1405,7 +1397,7 @@ static struct clk mailboxes_ick = {
1405 1397
1406static struct clk wdt4_ick = { 1398static struct clk wdt4_ick = {
1407 .name = "wdt4_ick", 1399 .name = "wdt4_ick",
1408 .ops = &clkops_omap2_dflt_wait, 1400 .ops = &clkops_omap2_iclk_dflt_wait,
1409 .parent = &l4_ck, 1401 .parent = &l4_ck,
1410 .clkdm_name = "core_l4_clkdm", 1402 .clkdm_name = "core_l4_clkdm",
1411 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1425,7 +1417,7 @@ static struct clk wdt4_fck = {
1425 1417
1426static struct clk wdt3_ick = { 1418static struct clk wdt3_ick = {
1427 .name = "wdt3_ick", 1419 .name = "wdt3_ick",
1428 .ops = &clkops_omap2_dflt_wait, 1420 .ops = &clkops_omap2_iclk_dflt_wait,
1429 .parent = &l4_ck, 1421 .parent = &l4_ck,
1430 .clkdm_name = "core_l4_clkdm", 1422 .clkdm_name = "core_l4_clkdm",
1431 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1423 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1445,7 +1437,7 @@ static struct clk wdt3_fck = {
1445 1437
1446static struct clk mspro_ick = { 1438static struct clk mspro_ick = {
1447 .name = "mspro_ick", 1439 .name = "mspro_ick",
1448 .ops = &clkops_omap2_dflt_wait, 1440 .ops = &clkops_omap2_iclk_dflt_wait,
1449 .parent = &l4_ck, 1441 .parent = &l4_ck,
1450 .clkdm_name = "core_l4_clkdm", 1442 .clkdm_name = "core_l4_clkdm",
1451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1465,7 +1457,7 @@ static struct clk mspro_fck = {
1465 1457
1466static struct clk mmc_ick = { 1458static struct clk mmc_ick = {
1467 .name = "mmc_ick", 1459 .name = "mmc_ick",
1468 .ops = &clkops_omap2_dflt_wait, 1460 .ops = &clkops_omap2_iclk_dflt_wait,
1469 .parent = &l4_ck, 1461 .parent = &l4_ck,
1470 .clkdm_name = "core_l4_clkdm", 1462 .clkdm_name = "core_l4_clkdm",
1471 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1477,7 @@ static struct clk mmc_fck = {
1485 1477
1486static struct clk fac_ick = { 1478static struct clk fac_ick = {
1487 .name = "fac_ick", 1479 .name = "fac_ick",
1488 .ops = &clkops_omap2_dflt_wait, 1480 .ops = &clkops_omap2_iclk_dflt_wait,
1489 .parent = &l4_ck, 1481 .parent = &l4_ck,
1490 .clkdm_name = "core_l4_clkdm", 1482 .clkdm_name = "core_l4_clkdm",
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1505,7 +1497,7 @@ static struct clk fac_fck = {
1505 1497
1506static struct clk eac_ick = { 1498static struct clk eac_ick = {
1507 .name = "eac_ick", 1499 .name = "eac_ick",
1508 .ops = &clkops_omap2_dflt_wait, 1500 .ops = &clkops_omap2_iclk_dflt_wait,
1509 .parent = &l4_ck, 1501 .parent = &l4_ck,
1510 .clkdm_name = "core_l4_clkdm", 1502 .clkdm_name = "core_l4_clkdm",
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1525,7 +1517,7 @@ static struct clk eac_fck = {
1525 1517
1526static struct clk hdq_ick = { 1518static struct clk hdq_ick = {
1527 .name = "hdq_ick", 1519 .name = "hdq_ick",
1528 .ops = &clkops_omap2_dflt_wait, 1520 .ops = &clkops_omap2_iclk_dflt_wait,
1529 .parent = &l4_ck, 1521 .parent = &l4_ck,
1530 .clkdm_name = "core_l4_clkdm", 1522 .clkdm_name = "core_l4_clkdm",
1531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1545,7 +1537,7 @@ static struct clk hdq_fck = {
1545 1537
1546static struct clk i2c2_ick = { 1538static struct clk i2c2_ick = {
1547 .name = "i2c2_ick", 1539 .name = "i2c2_ick",
1548 .ops = &clkops_omap2_dflt_wait, 1540 .ops = &clkops_omap2_iclk_dflt_wait,
1549 .parent = &l4_ck, 1541 .parent = &l4_ck,
1550 .clkdm_name = "core_l4_clkdm", 1542 .clkdm_name = "core_l4_clkdm",
1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1565,7 +1557,7 @@ static struct clk i2c2_fck = {
1565 1557
1566static struct clk i2c1_ick = { 1558static struct clk i2c1_ick = {
1567 .name = "i2c1_ick", 1559 .name = "i2c1_ick",
1568 .ops = &clkops_omap2_dflt_wait, 1560 .ops = &clkops_omap2_iclk_dflt_wait,
1569 .parent = &l4_ck, 1561 .parent = &l4_ck,
1570 .clkdm_name = "core_l4_clkdm", 1562 .clkdm_name = "core_l4_clkdm",
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1583,12 +1575,18 @@ static struct clk i2c1_fck = {
1583 .recalc = &followparent_recalc, 1575 .recalc = &followparent_recalc,
1584}; 1576};
1585 1577
1578/*
1579 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1580 * accesses derived from this data.
1581 */
1586static struct clk gpmc_fck = { 1582static struct clk gpmc_fck = {
1587 .name = "gpmc_fck", 1583 .name = "gpmc_fck",
1588 .ops = &clkops_null, /* RMK: missing? */ 1584 .ops = &clkops_omap2_iclk_idle_only,
1589 .parent = &core_l3_ck, 1585 .parent = &core_l3_ck,
1590 .flags = ENABLE_ON_INIT, 1586 .flags = ENABLE_ON_INIT,
1591 .clkdm_name = "core_l3_clkdm", 1587 .clkdm_name = "core_l3_clkdm",
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1589 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1592 .recalc = &followparent_recalc, 1590 .recalc = &followparent_recalc,
1593}; 1591};
1594 1592
@@ -1600,17 +1598,38 @@ static struct clk sdma_fck = {
1600 .recalc = &followparent_recalc, 1598 .recalc = &followparent_recalc,
1601}; 1599};
1602 1600
1601/*
1602 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1603 * accesses derived from this data.
1604 */
1603static struct clk sdma_ick = { 1605static struct clk sdma_ick = {
1604 .name = "sdma_ick", 1606 .name = "sdma_ick",
1605 .ops = &clkops_null, /* RMK: missing? */ 1607 .ops = &clkops_omap2_iclk_idle_only,
1606 .parent = &l4_ck, 1608 .parent = &core_l3_ck,
1609 .clkdm_name = "core_l3_clkdm",
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1611 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1612 .recalc = &followparent_recalc,
1613};
1614
1615/*
1616 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1617 * accesses derived from this data.
1618 */
1619static struct clk sdrc_ick = {
1620 .name = "sdrc_ick",
1621 .ops = &clkops_omap2_iclk_idle_only,
1622 .parent = &core_l3_ck,
1623 .flags = ENABLE_ON_INIT,
1607 .clkdm_name = "core_l3_clkdm", 1624 .clkdm_name = "core_l3_clkdm",
1625 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1626 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1608 .recalc = &followparent_recalc, 1627 .recalc = &followparent_recalc,
1609}; 1628};
1610 1629
1611static struct clk vlynq_ick = { 1630static struct clk vlynq_ick = {
1612 .name = "vlynq_ick", 1631 .name = "vlynq_ick",
1613 .ops = &clkops_omap2_dflt_wait, 1632 .ops = &clkops_omap2_iclk_dflt_wait,
1614 .parent = &core_l3_ck, 1633 .parent = &core_l3_ck,
1615 .clkdm_name = "core_l3_clkdm", 1634 .clkdm_name = "core_l3_clkdm",
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1659,7 +1678,7 @@ static struct clk vlynq_fck = {
1659 1678
1660static struct clk des_ick = { 1679static struct clk des_ick = {
1661 .name = "des_ick", 1680 .name = "des_ick",
1662 .ops = &clkops_omap2_dflt_wait, 1681 .ops = &clkops_omap2_iclk_dflt_wait,
1663 .parent = &l4_ck, 1682 .parent = &l4_ck,
1664 .clkdm_name = "core_l4_clkdm", 1683 .clkdm_name = "core_l4_clkdm",
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1688,7 @@ static struct clk des_ick = {
1669 1688
1670static struct clk sha_ick = { 1689static struct clk sha_ick = {
1671 .name = "sha_ick", 1690 .name = "sha_ick",
1672 .ops = &clkops_omap2_dflt_wait, 1691 .ops = &clkops_omap2_iclk_dflt_wait,
1673 .parent = &l4_ck, 1692 .parent = &l4_ck,
1674 .clkdm_name = "core_l4_clkdm", 1693 .clkdm_name = "core_l4_clkdm",
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1698,7 @@ static struct clk sha_ick = {
1679 1698
1680static struct clk rng_ick = { 1699static struct clk rng_ick = {
1681 .name = "rng_ick", 1700 .name = "rng_ick",
1682 .ops = &clkops_omap2_dflt_wait, 1701 .ops = &clkops_omap2_iclk_dflt_wait,
1683 .parent = &l4_ck, 1702 .parent = &l4_ck,
1684 .clkdm_name = "core_l4_clkdm", 1703 .clkdm_name = "core_l4_clkdm",
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1708,7 @@ static struct clk rng_ick = {
1689 1708
1690static struct clk aes_ick = { 1709static struct clk aes_ick = {
1691 .name = "aes_ick", 1710 .name = "aes_ick",
1692 .ops = &clkops_omap2_dflt_wait, 1711 .ops = &clkops_omap2_iclk_dflt_wait,
1693 .parent = &l4_ck, 1712 .parent = &l4_ck,
1694 .clkdm_name = "core_l4_clkdm", 1713 .clkdm_name = "core_l4_clkdm",
1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1718,7 @@ static struct clk aes_ick = {
1699 1718
1700static struct clk pka_ick = { 1719static struct clk pka_ick = {
1701 .name = "pka_ick", 1720 .name = "pka_ick",
1702 .ops = &clkops_omap2_dflt_wait, 1721 .ops = &clkops_omap2_iclk_dflt_wait,
1703 .parent = &l4_ck, 1722 .parent = &l4_ck,
1704 .clkdm_name = "core_l4_clkdm", 1723 .clkdm_name = "core_l4_clkdm",
1705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1777,7 +1796,6 @@ static struct omap_clk omap2420_clks[] = {
1777 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), 1796 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1778 /* dsp domain clocks */ 1797 /* dsp domain clocks */
1779 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), 1798 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1780 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
1781 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), 1799 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1782 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), 1800 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1783 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), 1801 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
@@ -1797,6 +1815,7 @@ static struct omap_clk omap2420_clks[] = {
1797 /* L4 domain clocks */ 1815 /* L4 domain clocks */
1798 CLK(NULL, "l4_ck", &l4_ck, CK_242X), 1816 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1799 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), 1817 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1818 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1800 /* virtual meta-group clock */ 1819 /* virtual meta-group clock */
1801 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), 1820 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1802 /* general l4 interface ck, multi-parent functional clk */ 1821 /* general l4 interface ck, multi-parent functional clk */
@@ -1869,6 +1888,7 @@ static struct omap_clk omap2420_clks[] = {
1869 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), 1888 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1870 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), 1889 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1871 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), 1890 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1891 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
1872 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), 1892 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1873 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), 1893 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1874 CLK(NULL, "des_ick", &des_ick, CK_242X), 1894 CLK(NULL, "des_ick", &des_ick, CK_242X),
@@ -1913,6 +1933,9 @@ int __init omap2420_clk_init(void)
1913 omap2_init_clk_clkdm(c->lk.clk); 1933 omap2_init_clk_clkdm(c->lk.clk);
1914 } 1934 }
1915 1935
1936 /* Disable autoidle on all clocks; let the PM code enable it later */
1937 omap_clk_disable_autoidle_all();
1938
1916 /* Check the MPU rate set by bootloader */ 1939 /* Check the MPU rate set by bootloader */
1917 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); 1940 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1918 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 1941 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 5c647ce05b04..bba018331a71 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1,12 +1,12 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock2430_data.c 2 * OMAP2430 clock data
3 * 3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation 5 * Copyright (C) 2004-2011 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -34,18 +34,15 @@
34/* 34/*
35 * 2430 clock tree. 35 * 2430 clock tree.
36 * 36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In many 37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * cases the parent is selectable. The get/set parent calls will also 38 * many cases the parent is selectable. The set parent calls will
39 * switch sources. 39 * also switch sources.
40 *
41 * Many some clocks say always_enabled, but they can be auto idled for
42 * power savings. They will always be available upon clock request.
43 * 40 *
44 * Several sources are given initial rates which may be wrong, this will 41 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func. 42 * be fixed up in the init func.
46 * 43 *
47 * Things are broadly separated below by clock domains. It is 44 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most periferals have dependencies on multiple clock 45 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get 46 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived 47 * functional clocks from fixed sources or other core domain derived
51 * clocks. 48 * clocks.
@@ -55,7 +52,7 @@
55static struct clk func_32k_ck = { 52static struct clk func_32k_ck = {
56 .name = "func_32k_ck", 53 .name = "func_32k_ck",
57 .ops = &clkops_null, 54 .ops = &clkops_null,
58 .rate = 32000, 55 .rate = 32768,
59 .clkdm_name = "wkup_clkdm", 56 .clkdm_name = "wkup_clkdm",
60}; 57};
61 58
@@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
116 .max_multiplier = 1023, 113 .max_multiplier = 1023,
117 .min_divider = 1, 114 .min_divider = 1,
118 .max_divider = 16, 115 .max_divider = 16,
119 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
120}; 116};
121 117
122/* 118/*
@@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
125 */ 121 */
126static struct clk dpll_ck = { 122static struct clk dpll_ck = {
127 .name = "dpll_ck", 123 .name = "dpll_ck",
128 .ops = &clkops_null, 124 .ops = &clkops_omap2xxx_dpll_ops,
129 .parent = &sys_ck, /* Can be func_32k also */ 125 .parent = &sys_ck, /* Can be func_32k also */
130 .dpll_data = &dpll_dd, 126 .dpll_data = &dpll_dd,
131 .clkdm_name = "wkup_clkdm", 127 .clkdm_name = "wkup_clkdm",
@@ -434,37 +430,23 @@ static struct clk dsp_fck = {
434 .recalc = &omap2_clksel_recalc, 430 .recalc = &omap2_clksel_recalc,
435}; 431};
436 432
437/* DSP interface clock */ 433static const struct clksel dsp_ick_clksel[] = {
438static const struct clksel_rate dsp_irate_ick_rates[] = { 434 { .parent = &dsp_fck, .rates = dsp_ick_rates },
439 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
440 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
441 { .div = 3, .val = 3, .flags = RATE_IN_243X },
442 { .div = 0 },
443};
444
445static const struct clksel dsp_irate_ick_clksel[] = {
446 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
447 { .parent = NULL } 435 { .parent = NULL }
448}; 436};
449 437
450/* This clock does not exist as such in the TRM. */
451static struct clk dsp_irate_ick = {
452 .name = "dsp_irate_ick",
453 .ops = &clkops_null,
454 .parent = &dsp_fck,
455 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
456 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
457 .clksel = dsp_irate_ick_clksel,
458 .recalc = &omap2_clksel_recalc,
459};
460
461/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 438/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
462static struct clk iva2_1_ick = { 439static struct clk iva2_1_ick = {
463 .name = "iva2_1_ick", 440 .name = "iva2_1_ick",
464 .ops = &clkops_omap2_dflt_wait, 441 .ops = &clkops_omap2_dflt_wait,
465 .parent = &dsp_irate_ick, 442 .parent = &dsp_fck,
443 .clkdm_name = "dsp_clkdm",
466 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 444 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
467 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 445 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
446 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
447 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
448 .clksel = dsp_ick_clksel,
449 .recalc = &omap2_clksel_recalc,
468}; 450};
469 451
470/* 452/*
@@ -525,7 +507,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
525/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 507/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
526static struct clk usb_l4_ick = { /* FS-USB interface clock */ 508static struct clk usb_l4_ick = { /* FS-USB interface clock */
527 .name = "usb_l4_ick", 509 .name = "usb_l4_ick",
528 .ops = &clkops_omap2_dflt_wait, 510 .ops = &clkops_omap2_iclk_dflt_wait,
529 .parent = &core_l3_ck, 511 .parent = &core_l3_ck,
530 .clkdm_name = "core_l4_clkdm", 512 .clkdm_name = "core_l4_clkdm",
531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -606,7 +588,7 @@ static struct clk ssi_ssr_sst_fck = {
606 */ 588 */
607static struct clk ssi_l4_ick = { 589static struct clk ssi_l4_ick = {
608 .name = "ssi_l4_ick", 590 .name = "ssi_l4_ick",
609 .ops = &clkops_omap2_dflt_wait, 591 .ops = &clkops_omap2_iclk_dflt_wait,
610 .parent = &l4_ck, 592 .parent = &l4_ck,
611 .clkdm_name = "core_l4_clkdm", 593 .clkdm_name = "core_l4_clkdm",
612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,6 +643,7 @@ static struct clk gfx_2d_fck = {
661 .recalc = &omap2_clksel_recalc, 643 .recalc = &omap2_clksel_recalc,
662}; 644};
663 645
646/* This interface clock does not have a CM_AUTOIDLE bit */
664static struct clk gfx_ick = { 647static struct clk gfx_ick = {
665 .name = "gfx_ick", /* From l3 */ 648 .name = "gfx_ick", /* From l3 */
666 .ops = &clkops_omap2_dflt_wait, 649 .ops = &clkops_omap2_dflt_wait,
@@ -693,7 +676,7 @@ static const struct clksel mdm_ick_clksel[] = {
693 676
694static struct clk mdm_ick = { /* used both as a ick and fck */ 677static struct clk mdm_ick = { /* used both as a ick and fck */
695 .name = "mdm_ick", 678 .name = "mdm_ick",
696 .ops = &clkops_omap2_dflt_wait, 679 .ops = &clkops_omap2_iclk_dflt_wait,
697 .parent = &core_ck, 680 .parent = &core_ck,
698 .clkdm_name = "mdm_clkdm", 681 .clkdm_name = "mdm_clkdm",
699 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 682 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -706,7 +689,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
706 689
707static struct clk mdm_osc_ck = { 690static struct clk mdm_osc_ck = {
708 .name = "mdm_osc_ck", 691 .name = "mdm_osc_ck",
709 .ops = &clkops_omap2_dflt_wait, 692 .ops = &clkops_omap2_mdmclk_dflt_wait,
710 .parent = &osc_ck, 693 .parent = &osc_ck,
711 .clkdm_name = "mdm_clkdm", 694 .clkdm_name = "mdm_clkdm",
712 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 695 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -751,7 +734,7 @@ static const struct clksel dss1_fck_clksel[] = {
751 734
752static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 735static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
753 .name = "dss_ick", 736 .name = "dss_ick",
754 .ops = &clkops_omap2_dflt, 737 .ops = &clkops_omap2_iclk_dflt,
755 .parent = &l4_ck, /* really both l3 and l4 */ 738 .parent = &l4_ck, /* really both l3 and l4 */
756 .clkdm_name = "dss_clkdm", 739 .clkdm_name = "dss_clkdm",
757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -813,6 +796,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
813 .recalc = &followparent_recalc, 796 .recalc = &followparent_recalc,
814}; 797};
815 798
799static struct clk wu_l4_ick = {
800 .name = "wu_l4_ick",
801 .ops = &clkops_null,
802 .parent = &sys_ck,
803 .clkdm_name = "wkup_clkdm",
804 .recalc = &followparent_recalc,
805};
806
816/* 807/*
817 * CORE power domain ICLK & FCLK defines. 808 * CORE power domain ICLK & FCLK defines.
818 * Many of the these can have more than one possible parent. Entries 809 * Many of the these can have more than one possible parent. Entries
@@ -833,9 +824,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
833 824
834static struct clk gpt1_ick = { 825static struct clk gpt1_ick = {
835 .name = "gpt1_ick", 826 .name = "gpt1_ick",
836 .ops = &clkops_omap2_dflt_wait, 827 .ops = &clkops_omap2_iclk_dflt_wait,
837 .parent = &l4_ck, 828 .parent = &wu_l4_ick,
838 .clkdm_name = "core_l4_clkdm", 829 .clkdm_name = "wkup_clkdm",
839 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 830 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
840 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 831 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
841 .recalc = &followparent_recalc, 832 .recalc = &followparent_recalc,
@@ -859,7 +850,7 @@ static struct clk gpt1_fck = {
859 850
860static struct clk gpt2_ick = { 851static struct clk gpt2_ick = {
861 .name = "gpt2_ick", 852 .name = "gpt2_ick",
862 .ops = &clkops_omap2_dflt_wait, 853 .ops = &clkops_omap2_iclk_dflt_wait,
863 .parent = &l4_ck, 854 .parent = &l4_ck,
864 .clkdm_name = "core_l4_clkdm", 855 .clkdm_name = "core_l4_clkdm",
865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -883,7 +874,7 @@ static struct clk gpt2_fck = {
883 874
884static struct clk gpt3_ick = { 875static struct clk gpt3_ick = {
885 .name = "gpt3_ick", 876 .name = "gpt3_ick",
886 .ops = &clkops_omap2_dflt_wait, 877 .ops = &clkops_omap2_iclk_dflt_wait,
887 .parent = &l4_ck, 878 .parent = &l4_ck,
888 .clkdm_name = "core_l4_clkdm", 879 .clkdm_name = "core_l4_clkdm",
889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -907,7 +898,7 @@ static struct clk gpt3_fck = {
907 898
908static struct clk gpt4_ick = { 899static struct clk gpt4_ick = {
909 .name = "gpt4_ick", 900 .name = "gpt4_ick",
910 .ops = &clkops_omap2_dflt_wait, 901 .ops = &clkops_omap2_iclk_dflt_wait,
911 .parent = &l4_ck, 902 .parent = &l4_ck,
912 .clkdm_name = "core_l4_clkdm", 903 .clkdm_name = "core_l4_clkdm",
913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -931,7 +922,7 @@ static struct clk gpt4_fck = {
931 922
932static struct clk gpt5_ick = { 923static struct clk gpt5_ick = {
933 .name = "gpt5_ick", 924 .name = "gpt5_ick",
934 .ops = &clkops_omap2_dflt_wait, 925 .ops = &clkops_omap2_iclk_dflt_wait,
935 .parent = &l4_ck, 926 .parent = &l4_ck,
936 .clkdm_name = "core_l4_clkdm", 927 .clkdm_name = "core_l4_clkdm",
937 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -955,7 +946,7 @@ static struct clk gpt5_fck = {
955 946
956static struct clk gpt6_ick = { 947static struct clk gpt6_ick = {
957 .name = "gpt6_ick", 948 .name = "gpt6_ick",
958 .ops = &clkops_omap2_dflt_wait, 949 .ops = &clkops_omap2_iclk_dflt_wait,
959 .parent = &l4_ck, 950 .parent = &l4_ck,
960 .clkdm_name = "core_l4_clkdm", 951 .clkdm_name = "core_l4_clkdm",
961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -979,8 +970,9 @@ static struct clk gpt6_fck = {
979 970
980static struct clk gpt7_ick = { 971static struct clk gpt7_ick = {
981 .name = "gpt7_ick", 972 .name = "gpt7_ick",
982 .ops = &clkops_omap2_dflt_wait, 973 .ops = &clkops_omap2_iclk_dflt_wait,
983 .parent = &l4_ck, 974 .parent = &l4_ck,
975 .clkdm_name = "core_l4_clkdm",
984 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
985 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 977 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
986 .recalc = &followparent_recalc, 978 .recalc = &followparent_recalc,
@@ -1002,7 +994,7 @@ static struct clk gpt7_fck = {
1002 994
1003static struct clk gpt8_ick = { 995static struct clk gpt8_ick = {
1004 .name = "gpt8_ick", 996 .name = "gpt8_ick",
1005 .ops = &clkops_omap2_dflt_wait, 997 .ops = &clkops_omap2_iclk_dflt_wait,
1006 .parent = &l4_ck, 998 .parent = &l4_ck,
1007 .clkdm_name = "core_l4_clkdm", 999 .clkdm_name = "core_l4_clkdm",
1008 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1026,7 +1018,7 @@ static struct clk gpt8_fck = {
1026 1018
1027static struct clk gpt9_ick = { 1019static struct clk gpt9_ick = {
1028 .name = "gpt9_ick", 1020 .name = "gpt9_ick",
1029 .ops = &clkops_omap2_dflt_wait, 1021 .ops = &clkops_omap2_iclk_dflt_wait,
1030 .parent = &l4_ck, 1022 .parent = &l4_ck,
1031 .clkdm_name = "core_l4_clkdm", 1023 .clkdm_name = "core_l4_clkdm",
1032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1050,7 +1042,7 @@ static struct clk gpt9_fck = {
1050 1042
1051static struct clk gpt10_ick = { 1043static struct clk gpt10_ick = {
1052 .name = "gpt10_ick", 1044 .name = "gpt10_ick",
1053 .ops = &clkops_omap2_dflt_wait, 1045 .ops = &clkops_omap2_iclk_dflt_wait,
1054 .parent = &l4_ck, 1046 .parent = &l4_ck,
1055 .clkdm_name = "core_l4_clkdm", 1047 .clkdm_name = "core_l4_clkdm",
1056 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1074,7 +1066,7 @@ static struct clk gpt10_fck = {
1074 1066
1075static struct clk gpt11_ick = { 1067static struct clk gpt11_ick = {
1076 .name = "gpt11_ick", 1068 .name = "gpt11_ick",
1077 .ops = &clkops_omap2_dflt_wait, 1069 .ops = &clkops_omap2_iclk_dflt_wait,
1078 .parent = &l4_ck, 1070 .parent = &l4_ck,
1079 .clkdm_name = "core_l4_clkdm", 1071 .clkdm_name = "core_l4_clkdm",
1080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1098,7 +1090,7 @@ static struct clk gpt11_fck = {
1098 1090
1099static struct clk gpt12_ick = { 1091static struct clk gpt12_ick = {
1100 .name = "gpt12_ick", 1092 .name = "gpt12_ick",
1101 .ops = &clkops_omap2_dflt_wait, 1093 .ops = &clkops_omap2_iclk_dflt_wait,
1102 .parent = &l4_ck, 1094 .parent = &l4_ck,
1103 .clkdm_name = "core_l4_clkdm", 1095 .clkdm_name = "core_l4_clkdm",
1104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1122,7 +1114,7 @@ static struct clk gpt12_fck = {
1122 1114
1123static struct clk mcbsp1_ick = { 1115static struct clk mcbsp1_ick = {
1124 .name = "mcbsp1_ick", 1116 .name = "mcbsp1_ick",
1125 .ops = &clkops_omap2_dflt_wait, 1117 .ops = &clkops_omap2_iclk_dflt_wait,
1126 .parent = &l4_ck, 1118 .parent = &l4_ck,
1127 .clkdm_name = "core_l4_clkdm", 1119 .clkdm_name = "core_l4_clkdm",
1128 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1162,7 +1154,7 @@ static struct clk mcbsp1_fck = {
1162 1154
1163static struct clk mcbsp2_ick = { 1155static struct clk mcbsp2_ick = {
1164 .name = "mcbsp2_ick", 1156 .name = "mcbsp2_ick",
1165 .ops = &clkops_omap2_dflt_wait, 1157 .ops = &clkops_omap2_iclk_dflt_wait,
1166 .parent = &l4_ck, 1158 .parent = &l4_ck,
1167 .clkdm_name = "core_l4_clkdm", 1159 .clkdm_name = "core_l4_clkdm",
1168 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1186,7 +1178,7 @@ static struct clk mcbsp2_fck = {
1186 1178
1187static struct clk mcbsp3_ick = { 1179static struct clk mcbsp3_ick = {
1188 .name = "mcbsp3_ick", 1180 .name = "mcbsp3_ick",
1189 .ops = &clkops_omap2_dflt_wait, 1181 .ops = &clkops_omap2_iclk_dflt_wait,
1190 .parent = &l4_ck, 1182 .parent = &l4_ck,
1191 .clkdm_name = "core_l4_clkdm", 1183 .clkdm_name = "core_l4_clkdm",
1192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1184 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1210,7 +1202,7 @@ static struct clk mcbsp3_fck = {
1210 1202
1211static struct clk mcbsp4_ick = { 1203static struct clk mcbsp4_ick = {
1212 .name = "mcbsp4_ick", 1204 .name = "mcbsp4_ick",
1213 .ops = &clkops_omap2_dflt_wait, 1205 .ops = &clkops_omap2_iclk_dflt_wait,
1214 .parent = &l4_ck, 1206 .parent = &l4_ck,
1215 .clkdm_name = "core_l4_clkdm", 1207 .clkdm_name = "core_l4_clkdm",
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1234,7 +1226,7 @@ static struct clk mcbsp4_fck = {
1234 1226
1235static struct clk mcbsp5_ick = { 1227static struct clk mcbsp5_ick = {
1236 .name = "mcbsp5_ick", 1228 .name = "mcbsp5_ick",
1237 .ops = &clkops_omap2_dflt_wait, 1229 .ops = &clkops_omap2_iclk_dflt_wait,
1238 .parent = &l4_ck, 1230 .parent = &l4_ck,
1239 .clkdm_name = "core_l4_clkdm", 1231 .clkdm_name = "core_l4_clkdm",
1240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1258,7 +1250,7 @@ static struct clk mcbsp5_fck = {
1258 1250
1259static struct clk mcspi1_ick = { 1251static struct clk mcspi1_ick = {
1260 .name = "mcspi1_ick", 1252 .name = "mcspi1_ick",
1261 .ops = &clkops_omap2_dflt_wait, 1253 .ops = &clkops_omap2_iclk_dflt_wait,
1262 .parent = &l4_ck, 1254 .parent = &l4_ck,
1263 .clkdm_name = "core_l4_clkdm", 1255 .clkdm_name = "core_l4_clkdm",
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1270,7 @@ static struct clk mcspi1_fck = {
1278 1270
1279static struct clk mcspi2_ick = { 1271static struct clk mcspi2_ick = {
1280 .name = "mcspi2_ick", 1272 .name = "mcspi2_ick",
1281 .ops = &clkops_omap2_dflt_wait, 1273 .ops = &clkops_omap2_iclk_dflt_wait,
1282 .parent = &l4_ck, 1274 .parent = &l4_ck,
1283 .clkdm_name = "core_l4_clkdm", 1275 .clkdm_name = "core_l4_clkdm",
1284 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1298,7 +1290,7 @@ static struct clk mcspi2_fck = {
1298 1290
1299static struct clk mcspi3_ick = { 1291static struct clk mcspi3_ick = {
1300 .name = "mcspi3_ick", 1292 .name = "mcspi3_ick",
1301 .ops = &clkops_omap2_dflt_wait, 1293 .ops = &clkops_omap2_iclk_dflt_wait,
1302 .parent = &l4_ck, 1294 .parent = &l4_ck,
1303 .clkdm_name = "core_l4_clkdm", 1295 .clkdm_name = "core_l4_clkdm",
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1318,7 +1310,7 @@ static struct clk mcspi3_fck = {
1318 1310
1319static struct clk uart1_ick = { 1311static struct clk uart1_ick = {
1320 .name = "uart1_ick", 1312 .name = "uart1_ick",
1321 .ops = &clkops_omap2_dflt_wait, 1313 .ops = &clkops_omap2_iclk_dflt_wait,
1322 .parent = &l4_ck, 1314 .parent = &l4_ck,
1323 .clkdm_name = "core_l4_clkdm", 1315 .clkdm_name = "core_l4_clkdm",
1324 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1338,7 +1330,7 @@ static struct clk uart1_fck = {
1338 1330
1339static struct clk uart2_ick = { 1331static struct clk uart2_ick = {
1340 .name = "uart2_ick", 1332 .name = "uart2_ick",
1341 .ops = &clkops_omap2_dflt_wait, 1333 .ops = &clkops_omap2_iclk_dflt_wait,
1342 .parent = &l4_ck, 1334 .parent = &l4_ck,
1343 .clkdm_name = "core_l4_clkdm", 1335 .clkdm_name = "core_l4_clkdm",
1344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1358,7 +1350,7 @@ static struct clk uart2_fck = {
1358 1350
1359static struct clk uart3_ick = { 1351static struct clk uart3_ick = {
1360 .name = "uart3_ick", 1352 .name = "uart3_ick",
1361 .ops = &clkops_omap2_dflt_wait, 1353 .ops = &clkops_omap2_iclk_dflt_wait,
1362 .parent = &l4_ck, 1354 .parent = &l4_ck,
1363 .clkdm_name = "core_l4_clkdm", 1355 .clkdm_name = "core_l4_clkdm",
1364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1378,9 +1370,9 @@ static struct clk uart3_fck = {
1378 1370
1379static struct clk gpios_ick = { 1371static struct clk gpios_ick = {
1380 .name = "gpios_ick", 1372 .name = "gpios_ick",
1381 .ops = &clkops_omap2_dflt_wait, 1373 .ops = &clkops_omap2_iclk_dflt_wait,
1382 .parent = &l4_ck, 1374 .parent = &wu_l4_ick,
1383 .clkdm_name = "core_l4_clkdm", 1375 .clkdm_name = "wkup_clkdm",
1384 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1385 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 1377 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1386 .recalc = &followparent_recalc, 1378 .recalc = &followparent_recalc,
@@ -1398,9 +1390,9 @@ static struct clk gpios_fck = {
1398 1390
1399static struct clk mpu_wdt_ick = { 1391static struct clk mpu_wdt_ick = {
1400 .name = "mpu_wdt_ick", 1392 .name = "mpu_wdt_ick",
1401 .ops = &clkops_omap2_dflt_wait, 1393 .ops = &clkops_omap2_iclk_dflt_wait,
1402 .parent = &l4_ck, 1394 .parent = &wu_l4_ick,
1403 .clkdm_name = "core_l4_clkdm", 1395 .clkdm_name = "wkup_clkdm",
1404 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1405 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 1397 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1406 .recalc = &followparent_recalc, 1398 .recalc = &followparent_recalc,
@@ -1418,10 +1410,10 @@ static struct clk mpu_wdt_fck = {
1418 1410
1419static struct clk sync_32k_ick = { 1411static struct clk sync_32k_ick = {
1420 .name = "sync_32k_ick", 1412 .name = "sync_32k_ick",
1421 .ops = &clkops_omap2_dflt_wait, 1413 .ops = &clkops_omap2_iclk_dflt_wait,
1422 .parent = &l4_ck,
1423 .flags = ENABLE_ON_INIT, 1414 .flags = ENABLE_ON_INIT,
1424 .clkdm_name = "core_l4_clkdm", 1415 .parent = &wu_l4_ick,
1416 .clkdm_name = "wkup_clkdm",
1425 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1426 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 1418 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1427 .recalc = &followparent_recalc, 1419 .recalc = &followparent_recalc,
@@ -1429,9 +1421,9 @@ static struct clk sync_32k_ick = {
1429 1421
1430static struct clk wdt1_ick = { 1422static struct clk wdt1_ick = {
1431 .name = "wdt1_ick", 1423 .name = "wdt1_ick",
1432 .ops = &clkops_omap2_dflt_wait, 1424 .ops = &clkops_omap2_iclk_dflt_wait,
1433 .parent = &l4_ck, 1425 .parent = &wu_l4_ick,
1434 .clkdm_name = "core_l4_clkdm", 1426 .clkdm_name = "wkup_clkdm",
1435 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1436 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 1428 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1437 .recalc = &followparent_recalc, 1429 .recalc = &followparent_recalc,
@@ -1439,10 +1431,10 @@ static struct clk wdt1_ick = {
1439 1431
1440static struct clk omapctrl_ick = { 1432static struct clk omapctrl_ick = {
1441 .name = "omapctrl_ick", 1433 .name = "omapctrl_ick",
1442 .ops = &clkops_omap2_dflt_wait, 1434 .ops = &clkops_omap2_iclk_dflt_wait,
1443 .parent = &l4_ck,
1444 .flags = ENABLE_ON_INIT, 1435 .flags = ENABLE_ON_INIT,
1445 .clkdm_name = "core_l4_clkdm", 1436 .parent = &wu_l4_ick,
1437 .clkdm_name = "wkup_clkdm",
1446 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1447 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 1439 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1448 .recalc = &followparent_recalc, 1440 .recalc = &followparent_recalc,
@@ -1450,9 +1442,9 @@ static struct clk omapctrl_ick = {
1450 1442
1451static struct clk icr_ick = { 1443static struct clk icr_ick = {
1452 .name = "icr_ick", 1444 .name = "icr_ick",
1453 .ops = &clkops_omap2_dflt_wait, 1445 .ops = &clkops_omap2_iclk_dflt_wait,
1454 .parent = &l4_ck, 1446 .parent = &wu_l4_ick,
1455 .clkdm_name = "core_l4_clkdm", 1447 .clkdm_name = "wkup_clkdm",
1456 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1448 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1457 .enable_bit = OMAP2430_EN_ICR_SHIFT, 1449 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1458 .recalc = &followparent_recalc, 1450 .recalc = &followparent_recalc,
@@ -1460,7 +1452,7 @@ static struct clk icr_ick = {
1460 1452
1461static struct clk cam_ick = { 1453static struct clk cam_ick = {
1462 .name = "cam_ick", 1454 .name = "cam_ick",
1463 .ops = &clkops_omap2_dflt, 1455 .ops = &clkops_omap2_iclk_dflt,
1464 .parent = &l4_ck, 1456 .parent = &l4_ck,
1465 .clkdm_name = "core_l4_clkdm", 1457 .clkdm_name = "core_l4_clkdm",
1466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1477,7 @@ static struct clk cam_fck = {
1485 1477
1486static struct clk mailboxes_ick = { 1478static struct clk mailboxes_ick = {
1487 .name = "mailboxes_ick", 1479 .name = "mailboxes_ick",
1488 .ops = &clkops_omap2_dflt_wait, 1480 .ops = &clkops_omap2_iclk_dflt_wait,
1489 .parent = &l4_ck, 1481 .parent = &l4_ck,
1490 .clkdm_name = "core_l4_clkdm", 1482 .clkdm_name = "core_l4_clkdm",
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1495,7 +1487,7 @@ static struct clk mailboxes_ick = {
1495 1487
1496static struct clk wdt4_ick = { 1488static struct clk wdt4_ick = {
1497 .name = "wdt4_ick", 1489 .name = "wdt4_ick",
1498 .ops = &clkops_omap2_dflt_wait, 1490 .ops = &clkops_omap2_iclk_dflt_wait,
1499 .parent = &l4_ck, 1491 .parent = &l4_ck,
1500 .clkdm_name = "core_l4_clkdm", 1492 .clkdm_name = "core_l4_clkdm",
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1493 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1515,7 +1507,7 @@ static struct clk wdt4_fck = {
1515 1507
1516static struct clk mspro_ick = { 1508static struct clk mspro_ick = {
1517 .name = "mspro_ick", 1509 .name = "mspro_ick",
1518 .ops = &clkops_omap2_dflt_wait, 1510 .ops = &clkops_omap2_iclk_dflt_wait,
1519 .parent = &l4_ck, 1511 .parent = &l4_ck,
1520 .clkdm_name = "core_l4_clkdm", 1512 .clkdm_name = "core_l4_clkdm",
1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1535,7 +1527,7 @@ static struct clk mspro_fck = {
1535 1527
1536static struct clk fac_ick = { 1528static struct clk fac_ick = {
1537 .name = "fac_ick", 1529 .name = "fac_ick",
1538 .ops = &clkops_omap2_dflt_wait, 1530 .ops = &clkops_omap2_iclk_dflt_wait,
1539 .parent = &l4_ck, 1531 .parent = &l4_ck,
1540 .clkdm_name = "core_l4_clkdm", 1532 .clkdm_name = "core_l4_clkdm",
1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1555,7 +1547,7 @@ static struct clk fac_fck = {
1555 1547
1556static struct clk hdq_ick = { 1548static struct clk hdq_ick = {
1557 .name = "hdq_ick", 1549 .name = "hdq_ick",
1558 .ops = &clkops_omap2_dflt_wait, 1550 .ops = &clkops_omap2_iclk_dflt_wait,
1559 .parent = &l4_ck, 1551 .parent = &l4_ck,
1560 .clkdm_name = "core_l4_clkdm", 1552 .clkdm_name = "core_l4_clkdm",
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1579,7 +1571,7 @@ static struct clk hdq_fck = {
1579 */ 1571 */
1580static struct clk i2c2_ick = { 1572static struct clk i2c2_ick = {
1581 .name = "i2c2_ick", 1573 .name = "i2c2_ick",
1582 .ops = &clkops_omap2_dflt_wait, 1574 .ops = &clkops_omap2_iclk_dflt_wait,
1583 .parent = &l4_ck, 1575 .parent = &l4_ck,
1584 .clkdm_name = "core_l4_clkdm", 1576 .clkdm_name = "core_l4_clkdm",
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1603,7 +1595,7 @@ static struct clk i2chs2_fck = {
1603 */ 1595 */
1604static struct clk i2c1_ick = { 1596static struct clk i2c1_ick = {
1605 .name = "i2c1_ick", 1597 .name = "i2c1_ick",
1606 .ops = &clkops_omap2_dflt_wait, 1598 .ops = &clkops_omap2_iclk_dflt_wait,
1607 .parent = &l4_ck, 1599 .parent = &l4_ck,
1608 .clkdm_name = "core_l4_clkdm", 1600 .clkdm_name = "core_l4_clkdm",
1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1621,12 +1613,18 @@ static struct clk i2chs1_fck = {
1621 .recalc = &followparent_recalc, 1613 .recalc = &followparent_recalc,
1622}; 1614};
1623 1615
1616/*
1617 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1618 * accesses derived from this data.
1619 */
1624static struct clk gpmc_fck = { 1620static struct clk gpmc_fck = {
1625 .name = "gpmc_fck", 1621 .name = "gpmc_fck",
1626 .ops = &clkops_null, /* RMK: missing? */ 1622 .ops = &clkops_omap2_iclk_idle_only,
1627 .parent = &core_l3_ck, 1623 .parent = &core_l3_ck,
1628 .flags = ENABLE_ON_INIT, 1624 .flags = ENABLE_ON_INIT,
1629 .clkdm_name = "core_l3_clkdm", 1625 .clkdm_name = "core_l3_clkdm",
1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1627 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1630 .recalc = &followparent_recalc, 1628 .recalc = &followparent_recalc,
1631}; 1629};
1632 1630
@@ -1638,20 +1636,26 @@ static struct clk sdma_fck = {
1638 .recalc = &followparent_recalc, 1636 .recalc = &followparent_recalc,
1639}; 1637};
1640 1638
1639/*
1640 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1641 * accesses derived from this data.
1642 */
1641static struct clk sdma_ick = { 1643static struct clk sdma_ick = {
1642 .name = "sdma_ick", 1644 .name = "sdma_ick",
1643 .ops = &clkops_null, /* RMK: missing? */ 1645 .ops = &clkops_omap2_iclk_idle_only,
1644 .parent = &l4_ck, 1646 .parent = &core_l3_ck,
1645 .clkdm_name = "core_l3_clkdm", 1647 .clkdm_name = "core_l3_clkdm",
1648 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1649 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1646 .recalc = &followparent_recalc, 1650 .recalc = &followparent_recalc,
1647}; 1651};
1648 1652
1649static struct clk sdrc_ick = { 1653static struct clk sdrc_ick = {
1650 .name = "sdrc_ick", 1654 .name = "sdrc_ick",
1651 .ops = &clkops_omap2_dflt_wait, 1655 .ops = &clkops_omap2_iclk_idle_only,
1652 .parent = &l4_ck, 1656 .parent = &core_l3_ck,
1653 .flags = ENABLE_ON_INIT, 1657 .flags = ENABLE_ON_INIT,
1654 .clkdm_name = "core_l4_clkdm", 1658 .clkdm_name = "core_l3_clkdm",
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1656 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 1660 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1657 .recalc = &followparent_recalc, 1661 .recalc = &followparent_recalc,
@@ -1659,7 +1663,7 @@ static struct clk sdrc_ick = {
1659 1663
1660static struct clk des_ick = { 1664static struct clk des_ick = {
1661 .name = "des_ick", 1665 .name = "des_ick",
1662 .ops = &clkops_omap2_dflt_wait, 1666 .ops = &clkops_omap2_iclk_dflt_wait,
1663 .parent = &l4_ck, 1667 .parent = &l4_ck,
1664 .clkdm_name = "core_l4_clkdm", 1668 .clkdm_name = "core_l4_clkdm",
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1673,7 @@ static struct clk des_ick = {
1669 1673
1670static struct clk sha_ick = { 1674static struct clk sha_ick = {
1671 .name = "sha_ick", 1675 .name = "sha_ick",
1672 .ops = &clkops_omap2_dflt_wait, 1676 .ops = &clkops_omap2_iclk_dflt_wait,
1673 .parent = &l4_ck, 1677 .parent = &l4_ck,
1674 .clkdm_name = "core_l4_clkdm", 1678 .clkdm_name = "core_l4_clkdm",
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1683,7 @@ static struct clk sha_ick = {
1679 1683
1680static struct clk rng_ick = { 1684static struct clk rng_ick = {
1681 .name = "rng_ick", 1685 .name = "rng_ick",
1682 .ops = &clkops_omap2_dflt_wait, 1686 .ops = &clkops_omap2_iclk_dflt_wait,
1683 .parent = &l4_ck, 1687 .parent = &l4_ck,
1684 .clkdm_name = "core_l4_clkdm", 1688 .clkdm_name = "core_l4_clkdm",
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1693,7 @@ static struct clk rng_ick = {
1689 1693
1690static struct clk aes_ick = { 1694static struct clk aes_ick = {
1691 .name = "aes_ick", 1695 .name = "aes_ick",
1692 .ops = &clkops_omap2_dflt_wait, 1696 .ops = &clkops_omap2_iclk_dflt_wait,
1693 .parent = &l4_ck, 1697 .parent = &l4_ck,
1694 .clkdm_name = "core_l4_clkdm", 1698 .clkdm_name = "core_l4_clkdm",
1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1703,7 @@ static struct clk aes_ick = {
1699 1703
1700static struct clk pka_ick = { 1704static struct clk pka_ick = {
1701 .name = "pka_ick", 1705 .name = "pka_ick",
1702 .ops = &clkops_omap2_dflt_wait, 1706 .ops = &clkops_omap2_iclk_dflt_wait,
1703 .parent = &l4_ck, 1707 .parent = &l4_ck,
1704 .clkdm_name = "core_l4_clkdm", 1708 .clkdm_name = "core_l4_clkdm",
1705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1719,7 +1723,7 @@ static struct clk usb_fck = {
1719 1723
1720static struct clk usbhs_ick = { 1724static struct clk usbhs_ick = {
1721 .name = "usbhs_ick", 1725 .name = "usbhs_ick",
1722 .ops = &clkops_omap2_dflt_wait, 1726 .ops = &clkops_omap2_iclk_dflt_wait,
1723 .parent = &core_l3_ck, 1727 .parent = &core_l3_ck,
1724 .clkdm_name = "core_l3_clkdm", 1728 .clkdm_name = "core_l3_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1729,7 +1733,7 @@ static struct clk usbhs_ick = {
1729 1733
1730static struct clk mmchs1_ick = { 1734static struct clk mmchs1_ick = {
1731 .name = "mmchs1_ick", 1735 .name = "mmchs1_ick",
1732 .ops = &clkops_omap2_dflt_wait, 1736 .ops = &clkops_omap2_iclk_dflt_wait,
1733 .parent = &l4_ck, 1737 .parent = &l4_ck,
1734 .clkdm_name = "core_l4_clkdm", 1738 .clkdm_name = "core_l4_clkdm",
1735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1739 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1741,7 +1745,7 @@ static struct clk mmchs1_fck = {
1741 .name = "mmchs1_fck", 1745 .name = "mmchs1_fck",
1742 .ops = &clkops_omap2_dflt_wait, 1746 .ops = &clkops_omap2_dflt_wait,
1743 .parent = &func_96m_ck, 1747 .parent = &func_96m_ck,
1744 .clkdm_name = "core_l3_clkdm", 1748 .clkdm_name = "core_l4_clkdm",
1745 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1749 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1746 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 1750 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1747 .recalc = &followparent_recalc, 1751 .recalc = &followparent_recalc,
@@ -1749,7 +1753,7 @@ static struct clk mmchs1_fck = {
1749 1753
1750static struct clk mmchs2_ick = { 1754static struct clk mmchs2_ick = {
1751 .name = "mmchs2_ick", 1755 .name = "mmchs2_ick",
1752 .ops = &clkops_omap2_dflt_wait, 1756 .ops = &clkops_omap2_iclk_dflt_wait,
1753 .parent = &l4_ck, 1757 .parent = &l4_ck,
1754 .clkdm_name = "core_l4_clkdm", 1758 .clkdm_name = "core_l4_clkdm",
1755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1759 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1761,6 +1765,7 @@ static struct clk mmchs2_fck = {
1761 .name = "mmchs2_fck", 1765 .name = "mmchs2_fck",
1762 .ops = &clkops_omap2_dflt_wait, 1766 .ops = &clkops_omap2_dflt_wait,
1763 .parent = &func_96m_ck, 1767 .parent = &func_96m_ck,
1768 .clkdm_name = "core_l4_clkdm",
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1765 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 1770 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1766 .recalc = &followparent_recalc, 1771 .recalc = &followparent_recalc,
@@ -1768,7 +1773,7 @@ static struct clk mmchs2_fck = {
1768 1773
1769static struct clk gpio5_ick = { 1774static struct clk gpio5_ick = {
1770 .name = "gpio5_ick", 1775 .name = "gpio5_ick",
1771 .ops = &clkops_omap2_dflt_wait, 1776 .ops = &clkops_omap2_iclk_dflt_wait,
1772 .parent = &l4_ck, 1777 .parent = &l4_ck,
1773 .clkdm_name = "core_l4_clkdm", 1778 .clkdm_name = "core_l4_clkdm",
1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1788,7 +1793,7 @@ static struct clk gpio5_fck = {
1788 1793
1789static struct clk mdm_intc_ick = { 1794static struct clk mdm_intc_ick = {
1790 .name = "mdm_intc_ick", 1795 .name = "mdm_intc_ick",
1791 .ops = &clkops_omap2_dflt_wait, 1796 .ops = &clkops_omap2_iclk_dflt_wait,
1792 .parent = &l4_ck, 1797 .parent = &l4_ck,
1793 .clkdm_name = "core_l4_clkdm", 1798 .clkdm_name = "core_l4_clkdm",
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1880,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
1880 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), 1885 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1881 /* dsp domain clocks */ 1886 /* dsp domain clocks */
1882 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), 1887 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1883 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
1884 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), 1888 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1885 /* GFX domain clocks */ 1889 /* GFX domain clocks */
1886 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), 1890 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
@@ -1901,6 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
1901 /* L4 domain clocks */ 1905 /* L4 domain clocks */
1902 CLK(NULL, "l4_ck", &l4_ck, CK_243X), 1906 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1903 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), 1907 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1908 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1904 /* virtual meta-group clock */ 1909 /* virtual meta-group clock */
1905 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), 1910 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1906 /* general l4 interface ck, multi-parent functional clk */ 1911 /* general l4 interface ck, multi-parent functional clk */
@@ -2028,6 +2033,9 @@ int __init omap2430_clk_init(void)
2028 omap2_init_clk_clkdm(c->lk.clk); 2033 omap2_init_clk_clkdm(c->lk.clk);
2029 } 2034 }
2030 2035
2036 /* Disable autoidle on all clocks; let the PM code enable it later */
2037 omap_clk_disable_autoidle_all();
2038
2031 /* Check the MPU rate set by bootloader */ 2039 /* Check the MPU rate set by bootloader */
2032 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); 2040 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2033 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 2041 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 287abc480924..1fc96b9ee330 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
2 * OMAP3-specific clock framework functions 2 * OMAP3-specific clock framework functions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
8 * Jouni Högander 8 * Jouni Högander
@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
59 .find_companion = omap2_clk_dflt_find_companion, 59 .find_companion = omap2_clk_dflt_find_companion,
60}; 60};
61 61
62const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
63 .enable = omap2_dflt_clk_enable,
64 .disable = omap2_dflt_clk_disable,
65 .find_idlest = omap3430es2_clk_ssi_find_idlest,
66 .find_companion = omap2_clk_dflt_find_companion,
67 .allow_idle = omap2_clkt_iclk_allow_idle,
68 .deny_idle = omap2_clkt_iclk_deny_idle,
69};
70
62/** 71/**
63 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST 72 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
64 * @clk: struct clk * being enabled 73 * @clk: struct clk * being enabled
@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
94 .find_companion = omap2_clk_dflt_find_companion, 103 .find_companion = omap2_clk_dflt_find_companion,
95}; 104};
96 105
106const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
107 .enable = omap2_dflt_clk_enable,
108 .disable = omap2_dflt_clk_disable,
109 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
110 .find_companion = omap2_clk_dflt_find_companion,
111 .allow_idle = omap2_clkt_iclk_allow_idle,
112 .deny_idle = omap2_clkt_iclk_deny_idle,
113};
114
97/** 115/**
98 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB 116 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
99 * @clk: struct clk * being enabled 117 * @clk: struct clk * being enabled
@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
124 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, 142 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
125 .find_companion = omap2_clk_dflt_find_companion, 143 .find_companion = omap2_clk_dflt_find_companion,
126}; 144};
145
146const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
147 .enable = omap2_dflt_clk_enable,
148 .disable = omap2_dflt_clk_disable,
149 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
150 .find_companion = omap2_clk_dflt_find_companion,
151 .allow_idle = omap2_clkt_iclk_allow_idle,
152 .deny_idle = omap2_clkt_iclk_deny_idle,
153};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 628e8de57680..084ba71b2b31 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2,14 +2,17 @@
2 * OMAP34xx clock function prototypes and macros 2 * OMAP34xx clock function prototypes and macros
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 */ 6 */
7 7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
10 10
11extern const struct clkops clkops_omap3430es2_ssi_wait; 11extern const struct clkops clkops_omap3430es2_ssi_wait;
12extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
12extern const struct clkops clkops_omap3430es2_hsotgusb_wait; 13extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
14extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
13extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; 15extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
16extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
14 17
15#endif 18#endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 74116a3cf099..2e97d08f0e56 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -2,7 +2,7 @@
2 * OMAP3517/3505-specific clock framework functions 2 * OMAP3517/3505-specific clock framework functions
3 * 3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. 4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation 5 * Copyright (C) 2011 Nokia Corporation
6 * 6 *
7 * Ranjith Lohithakshan 7 * Ranjith Lohithakshan
8 * Paul Walmsley 8 * Paul Walmsley
@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
119 .disable = omap2_dflt_clk_disable, 119 .disable = omap2_dflt_clk_disable,
120 .find_idlest = am35xx_clk_ipss_find_idlest, 120 .find_idlest = am35xx_clk_ipss_find_idlest,
121 .find_companion = omap2_clk_dflt_find_companion, 121 .find_companion = omap2_clk_dflt_find_companion,
122 .allow_idle = omap2_clkt_iclk_allow_idle,
123 .deny_idle = omap2_clkt_iclk_deny_idle,
122}; 124};
123 125
124 126
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index e9f66b6dec18..952c3e01c9eb 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
65 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); 65 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
66 clk_enable(dpll5_clk); 66 clk_enable(dpll5_clk);
67 67
68 /* Enable autoidle to allow it to enter low power bypass */
69 omap3_dpll_allow_idle(dpll5_clk);
70
71 /* Program dpll5_m2_clk divider for no division */ 68 /* Program dpll5_m2_clk divider for no division */
72 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); 69 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
73 clk_enable(dpll5_m2_clk); 70 clk_enable(dpll5_m2_clk);
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 052ac329282f..d905ecc7989a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP3 clock data 2 * OMAP3 clock data
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander 8 * With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
291 .max_multiplier = OMAP3_MAX_DPLL_MULT, 291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1, 292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV, 293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295}; 294};
296 295
297static struct clk dpll1_ck = { 296static struct clk dpll1_ck = {
298 .name = "dpll1_ck", 297 .name = "dpll1_ck",
299 .ops = &clkops_null, 298 .ops = &clkops_omap3_noncore_dpll_ops,
300 .parent = &sys_ck, 299 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd, 300 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate, 301 .round_rate = &omap2_dpll_round_rate,
@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
364 .max_multiplier = OMAP3_MAX_DPLL_MULT, 363 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1, 364 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV, 365 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368}; 366};
369 367
370static struct clk dpll2_ck = { 368static struct clk dpll2_ck = {
@@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
424 .max_multiplier = OMAP3_MAX_DPLL_MULT, 422 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1, 423 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV, 424 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428}; 425};
429 426
430static struct clk dpll3_ck = { 427static struct clk dpll3_ck = {
431 .name = "dpll3_ck", 428 .name = "dpll3_ck",
432 .ops = &clkops_null, 429 .ops = &clkops_omap3_core_dpll_ops,
433 .parent = &sys_ck, 430 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd, 431 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate, 432 .round_rate = &omap2_dpll_round_rate,
@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
583 .max_multiplier = OMAP3_MAX_DPLL_MULT, 580 .max_multiplier = OMAP3_MAX_DPLL_MULT,
584 .min_divider = 1, 581 .min_divider = 1,
585 .max_divider = OMAP3_MAX_DPLL_DIV, 582 .max_divider = OMAP3_MAX_DPLL_DIV,
586 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
587}; 583};
588 584
589static struct dpll_data dpll4_dd_3630 __initdata = { 585static struct dpll_data dpll4_dd_3630 __initdata = {
@@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
607 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, 603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
608 .min_divider = 1, 604 .min_divider = 1,
609 .max_divider = OMAP3_MAX_DPLL_DIV, 605 .max_divider = OMAP3_MAX_DPLL_DIV,
610 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
611 .flags = DPLL_J_TYPE 606 .flags = DPLL_J_TYPE
612}; 607};
613 608
@@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
939 .max_multiplier = OMAP3_MAX_DPLL_MULT, 934 .max_multiplier = OMAP3_MAX_DPLL_MULT,
940 .min_divider = 1, 935 .min_divider = 1,
941 .max_divider = OMAP3_MAX_DPLL_DIV, 936 .max_divider = OMAP3_MAX_DPLL_DIV,
942 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
943}; 937};
944 938
945static struct clk dpll5_ck = { 939static struct clk dpll5_ck = {
@@ -1205,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
1205 { .parent = NULL } 1199 { .parent = NULL }
1206}; 1200};
1207 1201
1208/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1202/*
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1205 */
1209static struct clk gfx_l3_ck = { 1206static struct clk gfx_l3_ck = {
1210 .name = "gfx_l3_ck", 1207 .name = "gfx_l3_ck",
1211 .ops = &clkops_omap2_dflt_wait, 1208 .ops = &clkops_omap2_dflt_wait,
@@ -1304,6 +1301,7 @@ static struct clk sgx_fck = {
1304 .round_rate = &omap2_clksel_round_rate 1301 .round_rate = &omap2_clksel_round_rate
1305}; 1302};
1306 1303
1304/* This interface clock does not have a CM_AUTOIDLE bit */
1307static struct clk sgx_ick = { 1305static struct clk sgx_ick = {
1308 .name = "sgx_ick", 1306 .name = "sgx_ick",
1309 .ops = &clkops_omap2_dflt_wait, 1307 .ops = &clkops_omap2_dflt_wait,
@@ -1328,7 +1326,7 @@ static struct clk d2d_26m_fck = {
1328 1326
1329static struct clk modem_fck = { 1327static struct clk modem_fck = {
1330 .name = "modem_fck", 1328 .name = "modem_fck",
1331 .ops = &clkops_omap2_dflt_wait, 1329 .ops = &clkops_omap2_mdmclk_dflt_wait,
1332 .parent = &sys_ck, 1330 .parent = &sys_ck,
1333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1334 .enable_bit = OMAP3430_EN_MODEM_SHIFT, 1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
@@ -1338,7 +1336,7 @@ static struct clk modem_fck = {
1338 1336
1339static struct clk sad2d_ick = { 1337static struct clk sad2d_ick = {
1340 .name = "sad2d_ick", 1338 .name = "sad2d_ick",
1341 .ops = &clkops_omap2_dflt_wait, 1339 .ops = &clkops_omap2_iclk_dflt_wait,
1342 .parent = &l3_ick, 1340 .parent = &l3_ick,
1343 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1344 .enable_bit = OMAP3430_EN_SAD2D_SHIFT, 1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
@@ -1348,7 +1346,7 @@ static struct clk sad2d_ick = {
1348 1346
1349static struct clk mad2d_ick = { 1347static struct clk mad2d_ick = {
1350 .name = "mad2d_ick", 1348 .name = "mad2d_ick",
1351 .ops = &clkops_omap2_dflt_wait, 1349 .ops = &clkops_omap2_iclk_dflt_wait,
1352 .parent = &l3_ick, 1350 .parent = &l3_ick,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1354 .enable_bit = OMAP3430_EN_MAD2D_SHIFT, 1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
@@ -1718,7 +1716,7 @@ static struct clk core_l3_ick = {
1718 1716
1719static struct clk hsotgusb_ick_3430es1 = { 1717static struct clk hsotgusb_ick_3430es1 = {
1720 .name = "hsotgusb_ick", 1718 .name = "hsotgusb_ick",
1721 .ops = &clkops_omap2_dflt, 1719 .ops = &clkops_omap2_iclk_dflt,
1722 .parent = &core_l3_ick, 1720 .parent = &core_l3_ick,
1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1724 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1722 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1728,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
1728 1726
1729static struct clk hsotgusb_ick_3430es2 = { 1727static struct clk hsotgusb_ick_3430es2 = {
1730 .name = "hsotgusb_ick", 1728 .name = "hsotgusb_ick",
1731 .ops = &clkops_omap3430es2_hsotgusb_wait, 1729 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1732 .parent = &core_l3_ick, 1730 .parent = &core_l3_ick,
1733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1734 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1732 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1736,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
1736 .recalc = &followparent_recalc, 1734 .recalc = &followparent_recalc,
1737}; 1735};
1738 1736
1737/* This interface clock does not have a CM_AUTOIDLE bit */
1739static struct clk sdrc_ick = { 1738static struct clk sdrc_ick = {
1740 .name = "sdrc_ick", 1739 .name = "sdrc_ick",
1741 .ops = &clkops_omap2_dflt_wait, 1740 .ops = &clkops_omap2_dflt_wait,
@@ -1767,7 +1766,7 @@ static struct clk security_l3_ick = {
1767 1766
1768static struct clk pka_ick = { 1767static struct clk pka_ick = {
1769 .name = "pka_ick", 1768 .name = "pka_ick",
1770 .ops = &clkops_omap2_dflt_wait, 1769 .ops = &clkops_omap2_iclk_dflt_wait,
1771 .parent = &security_l3_ick, 1770 .parent = &security_l3_ick,
1772 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1773 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1772 .enable_bit = OMAP3430_EN_PKA_SHIFT,
@@ -1786,7 +1785,7 @@ static struct clk core_l4_ick = {
1786 1785
1787static struct clk usbtll_ick = { 1786static struct clk usbtll_ick = {
1788 .name = "usbtll_ick", 1787 .name = "usbtll_ick",
1789 .ops = &clkops_omap2_dflt_wait, 1788 .ops = &clkops_omap2_iclk_dflt_wait,
1790 .parent = &core_l4_ick, 1789 .parent = &core_l4_ick,
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1792 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1791 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1796,7 +1795,7 @@ static struct clk usbtll_ick = {
1796 1795
1797static struct clk mmchs3_ick = { 1796static struct clk mmchs3_ick = {
1798 .name = "mmchs3_ick", 1797 .name = "mmchs3_ick",
1799 .ops = &clkops_omap2_dflt_wait, 1798 .ops = &clkops_omap2_iclk_dflt_wait,
1800 .parent = &core_l4_ick, 1799 .parent = &core_l4_ick,
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1807,7 +1806,7 @@ static struct clk mmchs3_ick = {
1807/* Intersystem Communication Registers - chassis mode only */ 1806/* Intersystem Communication Registers - chassis mode only */
1808static struct clk icr_ick = { 1807static struct clk icr_ick = {
1809 .name = "icr_ick", 1808 .name = "icr_ick",
1810 .ops = &clkops_omap2_dflt_wait, 1809 .ops = &clkops_omap2_iclk_dflt_wait,
1811 .parent = &core_l4_ick, 1810 .parent = &core_l4_ick,
1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1812 .enable_bit = OMAP3430_EN_ICR_SHIFT,
@@ -1817,7 +1816,7 @@ static struct clk icr_ick = {
1817 1816
1818static struct clk aes2_ick = { 1817static struct clk aes2_ick = {
1819 .name = "aes2_ick", 1818 .name = "aes2_ick",
1820 .ops = &clkops_omap2_dflt_wait, 1819 .ops = &clkops_omap2_iclk_dflt_wait,
1821 .parent = &core_l4_ick, 1820 .parent = &core_l4_ick,
1822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1823 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1822 .enable_bit = OMAP3430_EN_AES2_SHIFT,
@@ -1827,7 +1826,7 @@ static struct clk aes2_ick = {
1827 1826
1828static struct clk sha12_ick = { 1827static struct clk sha12_ick = {
1829 .name = "sha12_ick", 1828 .name = "sha12_ick",
1830 .ops = &clkops_omap2_dflt_wait, 1829 .ops = &clkops_omap2_iclk_dflt_wait,
1831 .parent = &core_l4_ick, 1830 .parent = &core_l4_ick,
1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1832 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
@@ -1837,7 +1836,7 @@ static struct clk sha12_ick = {
1837 1836
1838static struct clk des2_ick = { 1837static struct clk des2_ick = {
1839 .name = "des2_ick", 1838 .name = "des2_ick",
1840 .ops = &clkops_omap2_dflt_wait, 1839 .ops = &clkops_omap2_iclk_dflt_wait,
1841 .parent = &core_l4_ick, 1840 .parent = &core_l4_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1842 .enable_bit = OMAP3430_EN_DES2_SHIFT,
@@ -1847,7 +1846,7 @@ static struct clk des2_ick = {
1847 1846
1848static struct clk mmchs2_ick = { 1847static struct clk mmchs2_ick = {
1849 .name = "mmchs2_ick", 1848 .name = "mmchs2_ick",
1850 .ops = &clkops_omap2_dflt_wait, 1849 .ops = &clkops_omap2_iclk_dflt_wait,
1851 .parent = &core_l4_ick, 1850 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1852 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1857,7 +1856,7 @@ static struct clk mmchs2_ick = {
1857 1856
1858static struct clk mmchs1_ick = { 1857static struct clk mmchs1_ick = {
1859 .name = "mmchs1_ick", 1858 .name = "mmchs1_ick",
1860 .ops = &clkops_omap2_dflt_wait, 1859 .ops = &clkops_omap2_iclk_dflt_wait,
1861 .parent = &core_l4_ick, 1860 .parent = &core_l4_ick,
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1862 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1867,7 +1866,7 @@ static struct clk mmchs1_ick = {
1867 1866
1868static struct clk mspro_ick = { 1867static struct clk mspro_ick = {
1869 .name = "mspro_ick", 1868 .name = "mspro_ick",
1870 .ops = &clkops_omap2_dflt_wait, 1869 .ops = &clkops_omap2_iclk_dflt_wait,
1871 .parent = &core_l4_ick, 1870 .parent = &core_l4_ick,
1872 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1872 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1877,7 +1876,7 @@ static struct clk mspro_ick = {
1877 1876
1878static struct clk hdq_ick = { 1877static struct clk hdq_ick = {
1879 .name = "hdq_ick", 1878 .name = "hdq_ick",
1880 .ops = &clkops_omap2_dflt_wait, 1879 .ops = &clkops_omap2_iclk_dflt_wait,
1881 .parent = &core_l4_ick, 1880 .parent = &core_l4_ick,
1882 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1887,7 +1886,7 @@ static struct clk hdq_ick = {
1887 1886
1888static struct clk mcspi4_ick = { 1887static struct clk mcspi4_ick = {
1889 .name = "mcspi4_ick", 1888 .name = "mcspi4_ick",
1890 .ops = &clkops_omap2_dflt_wait, 1889 .ops = &clkops_omap2_iclk_dflt_wait,
1891 .parent = &core_l4_ick, 1890 .parent = &core_l4_ick,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1897,7 +1896,7 @@ static struct clk mcspi4_ick = {
1897 1896
1898static struct clk mcspi3_ick = { 1897static struct clk mcspi3_ick = {
1899 .name = "mcspi3_ick", 1898 .name = "mcspi3_ick",
1900 .ops = &clkops_omap2_dflt_wait, 1899 .ops = &clkops_omap2_iclk_dflt_wait,
1901 .parent = &core_l4_ick, 1900 .parent = &core_l4_ick,
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1902 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1907,7 +1906,7 @@ static struct clk mcspi3_ick = {
1907 1906
1908static struct clk mcspi2_ick = { 1907static struct clk mcspi2_ick = {
1909 .name = "mcspi2_ick", 1908 .name = "mcspi2_ick",
1910 .ops = &clkops_omap2_dflt_wait, 1909 .ops = &clkops_omap2_iclk_dflt_wait,
1911 .parent = &core_l4_ick, 1910 .parent = &core_l4_ick,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1917,7 +1916,7 @@ static struct clk mcspi2_ick = {
1917 1916
1918static struct clk mcspi1_ick = { 1917static struct clk mcspi1_ick = {
1919 .name = "mcspi1_ick", 1918 .name = "mcspi1_ick",
1920 .ops = &clkops_omap2_dflt_wait, 1919 .ops = &clkops_omap2_iclk_dflt_wait,
1921 .parent = &core_l4_ick, 1920 .parent = &core_l4_ick,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1922 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1927,7 +1926,7 @@ static struct clk mcspi1_ick = {
1927 1926
1928static struct clk i2c3_ick = { 1927static struct clk i2c3_ick = {
1929 .name = "i2c3_ick", 1928 .name = "i2c3_ick",
1930 .ops = &clkops_omap2_dflt_wait, 1929 .ops = &clkops_omap2_iclk_dflt_wait,
1931 .parent = &core_l4_ick, 1930 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1932 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1937,7 +1936,7 @@ static struct clk i2c3_ick = {
1937 1936
1938static struct clk i2c2_ick = { 1937static struct clk i2c2_ick = {
1939 .name = "i2c2_ick", 1938 .name = "i2c2_ick",
1940 .ops = &clkops_omap2_dflt_wait, 1939 .ops = &clkops_omap2_iclk_dflt_wait,
1941 .parent = &core_l4_ick, 1940 .parent = &core_l4_ick,
1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1942 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1947,7 +1946,7 @@ static struct clk i2c2_ick = {
1947 1946
1948static struct clk i2c1_ick = { 1947static struct clk i2c1_ick = {
1949 .name = "i2c1_ick", 1948 .name = "i2c1_ick",
1950 .ops = &clkops_omap2_dflt_wait, 1949 .ops = &clkops_omap2_iclk_dflt_wait,
1951 .parent = &core_l4_ick, 1950 .parent = &core_l4_ick,
1952 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1952 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1957,7 +1956,7 @@ static struct clk i2c1_ick = {
1957 1956
1958static struct clk uart2_ick = { 1957static struct clk uart2_ick = {
1959 .name = "uart2_ick", 1958 .name = "uart2_ick",
1960 .ops = &clkops_omap2_dflt_wait, 1959 .ops = &clkops_omap2_iclk_dflt_wait,
1961 .parent = &core_l4_ick, 1960 .parent = &core_l4_ick,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1962 .enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1967,7 +1966,7 @@ static struct clk uart2_ick = {
1967 1966
1968static struct clk uart1_ick = { 1967static struct clk uart1_ick = {
1969 .name = "uart1_ick", 1968 .name = "uart1_ick",
1970 .ops = &clkops_omap2_dflt_wait, 1969 .ops = &clkops_omap2_iclk_dflt_wait,
1971 .parent = &core_l4_ick, 1970 .parent = &core_l4_ick,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1972 .enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1977,7 +1976,7 @@ static struct clk uart1_ick = {
1977 1976
1978static struct clk gpt11_ick = { 1977static struct clk gpt11_ick = {
1979 .name = "gpt11_ick", 1978 .name = "gpt11_ick",
1980 .ops = &clkops_omap2_dflt_wait, 1979 .ops = &clkops_omap2_iclk_dflt_wait,
1981 .parent = &core_l4_ick, 1980 .parent = &core_l4_ick,
1982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1982 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1987,7 +1986,7 @@ static struct clk gpt11_ick = {
1987 1986
1988static struct clk gpt10_ick = { 1987static struct clk gpt10_ick = {
1989 .name = "gpt10_ick", 1988 .name = "gpt10_ick",
1990 .ops = &clkops_omap2_dflt_wait, 1989 .ops = &clkops_omap2_iclk_dflt_wait,
1991 .parent = &core_l4_ick, 1990 .parent = &core_l4_ick,
1992 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1997,7 +1996,7 @@ static struct clk gpt10_ick = {
1997 1996
1998static struct clk mcbsp5_ick = { 1997static struct clk mcbsp5_ick = {
1999 .name = "mcbsp5_ick", 1998 .name = "mcbsp5_ick",
2000 .ops = &clkops_omap2_dflt_wait, 1999 .ops = &clkops_omap2_iclk_dflt_wait,
2001 .parent = &core_l4_ick, 2000 .parent = &core_l4_ick,
2002 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 2002 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2007,7 +2006,7 @@ static struct clk mcbsp5_ick = {
2007 2006
2008static struct clk mcbsp1_ick = { 2007static struct clk mcbsp1_ick = {
2009 .name = "mcbsp1_ick", 2008 .name = "mcbsp1_ick",
2010 .ops = &clkops_omap2_dflt_wait, 2009 .ops = &clkops_omap2_iclk_dflt_wait,
2011 .parent = &core_l4_ick, 2010 .parent = &core_l4_ick,
2012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 2012 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2017,7 +2016,7 @@ static struct clk mcbsp1_ick = {
2017 2016
2018static struct clk fac_ick = { 2017static struct clk fac_ick = {
2019 .name = "fac_ick", 2018 .name = "fac_ick",
2020 .ops = &clkops_omap2_dflt_wait, 2019 .ops = &clkops_omap2_iclk_dflt_wait,
2021 .parent = &core_l4_ick, 2020 .parent = &core_l4_ick,
2022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 2022 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2027,7 +2026,7 @@ static struct clk fac_ick = {
2027 2026
2028static struct clk mailboxes_ick = { 2027static struct clk mailboxes_ick = {
2029 .name = "mailboxes_ick", 2028 .name = "mailboxes_ick",
2030 .ops = &clkops_omap2_dflt_wait, 2029 .ops = &clkops_omap2_iclk_dflt_wait,
2031 .parent = &core_l4_ick, 2030 .parent = &core_l4_ick,
2032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 2032 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2037,7 +2036,7 @@ static struct clk mailboxes_ick = {
2037 2036
2038static struct clk omapctrl_ick = { 2037static struct clk omapctrl_ick = {
2039 .name = "omapctrl_ick", 2038 .name = "omapctrl_ick",
2040 .ops = &clkops_omap2_dflt_wait, 2039 .ops = &clkops_omap2_iclk_dflt_wait,
2041 .parent = &core_l4_ick, 2040 .parent = &core_l4_ick,
2042 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 2042 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2057,7 +2056,7 @@ static struct clk ssi_l4_ick = {
2057 2056
2058static struct clk ssi_ick_3430es1 = { 2057static struct clk ssi_ick_3430es1 = {
2059 .name = "ssi_ick", 2058 .name = "ssi_ick",
2060 .ops = &clkops_omap2_dflt, 2059 .ops = &clkops_omap2_iclk_dflt,
2061 .parent = &ssi_l4_ick, 2060 .parent = &ssi_l4_ick,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2062 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2067,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
2067 2066
2068static struct clk ssi_ick_3430es2 = { 2067static struct clk ssi_ick_3430es2 = {
2069 .name = "ssi_ick", 2068 .name = "ssi_ick",
2070 .ops = &clkops_omap3430es2_ssi_wait, 2069 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2071 .parent = &ssi_l4_ick, 2070 .parent = &ssi_l4_ick,
2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2072 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2085,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
2085 2084
2086static struct clk usb_l4_ick = { 2085static struct clk usb_l4_ick = {
2087 .name = "usb_l4_ick", 2086 .name = "usb_l4_ick",
2088 .ops = &clkops_omap2_dflt_wait, 2087 .ops = &clkops_omap2_iclk_dflt_wait,
2089 .parent = &l4_ick, 2088 .parent = &l4_ick,
2090 .init = &omap2_init_clksel_parent, 2089 .init = &omap2_init_clksel_parent,
2091 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2107,7 +2106,7 @@ static struct clk security_l4_ick2 = {
2107 2106
2108static struct clk aes1_ick = { 2107static struct clk aes1_ick = {
2109 .name = "aes1_ick", 2108 .name = "aes1_ick",
2110 .ops = &clkops_omap2_dflt_wait, 2109 .ops = &clkops_omap2_iclk_dflt_wait,
2111 .parent = &security_l4_ick2, 2110 .parent = &security_l4_ick2,
2112 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2113 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
@@ -2116,7 +2115,7 @@ static struct clk aes1_ick = {
2116 2115
2117static struct clk rng_ick = { 2116static struct clk rng_ick = {
2118 .name = "rng_ick", 2117 .name = "rng_ick",
2119 .ops = &clkops_omap2_dflt_wait, 2118 .ops = &clkops_omap2_iclk_dflt_wait,
2120 .parent = &security_l4_ick2, 2119 .parent = &security_l4_ick2,
2121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2122 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
@@ -2125,7 +2124,7 @@ static struct clk rng_ick = {
2125 2124
2126static struct clk sha11_ick = { 2125static struct clk sha11_ick = {
2127 .name = "sha11_ick", 2126 .name = "sha11_ick",
2128 .ops = &clkops_omap2_dflt_wait, 2127 .ops = &clkops_omap2_iclk_dflt_wait,
2129 .parent = &security_l4_ick2, 2128 .parent = &security_l4_ick2,
2130 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2131 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
@@ -2134,7 +2133,7 @@ static struct clk sha11_ick = {
2134 2133
2135static struct clk des1_ick = { 2134static struct clk des1_ick = {
2136 .name = "des1_ick", 2135 .name = "des1_ick",
2137 .ops = &clkops_omap2_dflt_wait, 2136 .ops = &clkops_omap2_iclk_dflt_wait,
2138 .parent = &security_l4_ick2, 2137 .parent = &security_l4_ick2,
2139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2140 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
@@ -2195,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
2195static struct clk dss_ick_3430es1 = { 2194static struct clk dss_ick_3430es1 = {
2196 /* Handles both L3 and L4 clocks */ 2195 /* Handles both L3 and L4 clocks */
2197 .name = "dss_ick", 2196 .name = "dss_ick",
2198 .ops = &clkops_omap2_dflt, 2197 .ops = &clkops_omap2_iclk_dflt,
2199 .parent = &l4_ick, 2198 .parent = &l4_ick,
2200 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2199 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2201 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2200 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2206,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
2206static struct clk dss_ick_3430es2 = { 2205static struct clk dss_ick_3430es2 = {
2207 /* Handles both L3 and L4 clocks */ 2206 /* Handles both L3 and L4 clocks */
2208 .name = "dss_ick", 2207 .name = "dss_ick",
2209 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2208 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2210 .parent = &l4_ick, 2209 .parent = &l4_ick,
2211 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2212 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2211 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2229,7 +2228,7 @@ static struct clk cam_mclk = {
2229static struct clk cam_ick = { 2228static struct clk cam_ick = {
2230 /* Handles both L3 and L4 clocks */ 2229 /* Handles both L3 and L4 clocks */
2231 .name = "cam_ick", 2230 .name = "cam_ick",
2232 .ops = &clkops_omap2_dflt, 2231 .ops = &clkops_omap2_iclk_dflt,
2233 .parent = &l4_ick, 2232 .parent = &l4_ick,
2234 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2235 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2234 .enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2272,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
2272static struct clk usbhost_ick = { 2271static struct clk usbhost_ick = {
2273 /* Handles both L3 and L4 clocks */ 2272 /* Handles both L3 and L4 clocks */
2274 .name = "usbhost_ick", 2273 .name = "usbhost_ick",
2275 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2274 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2276 .parent = &l4_ick, 2275 .parent = &l4_ick,
2277 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2278 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2277 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2372,7 +2371,7 @@ static struct clk wkup_l4_ick = {
2372/* Never specifically named in the TRM, so we have to infer a likely name */ 2371/* Never specifically named in the TRM, so we have to infer a likely name */
2373static struct clk usim_ick = { 2372static struct clk usim_ick = {
2374 .name = "usim_ick", 2373 .name = "usim_ick",
2375 .ops = &clkops_omap2_dflt_wait, 2374 .ops = &clkops_omap2_iclk_dflt_wait,
2376 .parent = &wkup_l4_ick, 2375 .parent = &wkup_l4_ick,
2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2377 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2382,7 +2381,7 @@ static struct clk usim_ick = {
2382 2381
2383static struct clk wdt2_ick = { 2382static struct clk wdt2_ick = {
2384 .name = "wdt2_ick", 2383 .name = "wdt2_ick",
2385 .ops = &clkops_omap2_dflt_wait, 2384 .ops = &clkops_omap2_iclk_dflt_wait,
2386 .parent = &wkup_l4_ick, 2385 .parent = &wkup_l4_ick,
2387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2387 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2392,7 +2391,7 @@ static struct clk wdt2_ick = {
2392 2391
2393static struct clk wdt1_ick = { 2392static struct clk wdt1_ick = {
2394 .name = "wdt1_ick", 2393 .name = "wdt1_ick",
2395 .ops = &clkops_omap2_dflt_wait, 2394 .ops = &clkops_omap2_iclk_dflt_wait,
2396 .parent = &wkup_l4_ick, 2395 .parent = &wkup_l4_ick,
2397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2397 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
@@ -2402,7 +2401,7 @@ static struct clk wdt1_ick = {
2402 2401
2403static struct clk gpio1_ick = { 2402static struct clk gpio1_ick = {
2404 .name = "gpio1_ick", 2403 .name = "gpio1_ick",
2405 .ops = &clkops_omap2_dflt_wait, 2404 .ops = &clkops_omap2_iclk_dflt_wait,
2406 .parent = &wkup_l4_ick, 2405 .parent = &wkup_l4_ick,
2407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2408 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2407 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2412,7 +2411,7 @@ static struct clk gpio1_ick = {
2412 2411
2413static struct clk omap_32ksync_ick = { 2412static struct clk omap_32ksync_ick = {
2414 .name = "omap_32ksync_ick", 2413 .name = "omap_32ksync_ick",
2415 .ops = &clkops_omap2_dflt_wait, 2414 .ops = &clkops_omap2_iclk_dflt_wait,
2416 .parent = &wkup_l4_ick, 2415 .parent = &wkup_l4_ick,
2417 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2416 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2418 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2417 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2423,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
2423/* XXX This clock no longer exists in 3430 TRM rev F */ 2422/* XXX This clock no longer exists in 3430 TRM rev F */
2424static struct clk gpt12_ick = { 2423static struct clk gpt12_ick = {
2425 .name = "gpt12_ick", 2424 .name = "gpt12_ick",
2426 .ops = &clkops_omap2_dflt_wait, 2425 .ops = &clkops_omap2_iclk_dflt_wait,
2427 .parent = &wkup_l4_ick, 2426 .parent = &wkup_l4_ick,
2428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2429 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2428 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
@@ -2433,7 +2432,7 @@ static struct clk gpt12_ick = {
2433 2432
2434static struct clk gpt1_ick = { 2433static struct clk gpt1_ick = {
2435 .name = "gpt1_ick", 2434 .name = "gpt1_ick",
2436 .ops = &clkops_omap2_dflt_wait, 2435 .ops = &clkops_omap2_iclk_dflt_wait,
2437 .parent = &wkup_l4_ick, 2436 .parent = &wkup_l4_ick,
2438 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2437 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2439 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2438 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2663,7 +2662,7 @@ static struct clk per_l4_ick = {
2663 2662
2664static struct clk gpio6_ick = { 2663static struct clk gpio6_ick = {
2665 .name = "gpio6_ick", 2664 .name = "gpio6_ick",
2666 .ops = &clkops_omap2_dflt_wait, 2665 .ops = &clkops_omap2_iclk_dflt_wait,
2667 .parent = &per_l4_ick, 2666 .parent = &per_l4_ick,
2668 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2669 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2668 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2673,7 +2672,7 @@ static struct clk gpio6_ick = {
2673 2672
2674static struct clk gpio5_ick = { 2673static struct clk gpio5_ick = {
2675 .name = "gpio5_ick", 2674 .name = "gpio5_ick",
2676 .ops = &clkops_omap2_dflt_wait, 2675 .ops = &clkops_omap2_iclk_dflt_wait,
2677 .parent = &per_l4_ick, 2676 .parent = &per_l4_ick,
2678 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2678 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2683,7 +2682,7 @@ static struct clk gpio5_ick = {
2683 2682
2684static struct clk gpio4_ick = { 2683static struct clk gpio4_ick = {
2685 .name = "gpio4_ick", 2684 .name = "gpio4_ick",
2686 .ops = &clkops_omap2_dflt_wait, 2685 .ops = &clkops_omap2_iclk_dflt_wait,
2687 .parent = &per_l4_ick, 2686 .parent = &per_l4_ick,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2688 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2693,7 +2692,7 @@ static struct clk gpio4_ick = {
2693 2692
2694static struct clk gpio3_ick = { 2693static struct clk gpio3_ick = {
2695 .name = "gpio3_ick", 2694 .name = "gpio3_ick",
2696 .ops = &clkops_omap2_dflt_wait, 2695 .ops = &clkops_omap2_iclk_dflt_wait,
2697 .parent = &per_l4_ick, 2696 .parent = &per_l4_ick,
2698 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2698 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2703,7 +2702,7 @@ static struct clk gpio3_ick = {
2703 2702
2704static struct clk gpio2_ick = { 2703static struct clk gpio2_ick = {
2705 .name = "gpio2_ick", 2704 .name = "gpio2_ick",
2706 .ops = &clkops_omap2_dflt_wait, 2705 .ops = &clkops_omap2_iclk_dflt_wait,
2707 .parent = &per_l4_ick, 2706 .parent = &per_l4_ick,
2708 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2708 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2713,7 +2712,7 @@ static struct clk gpio2_ick = {
2713 2712
2714static struct clk wdt3_ick = { 2713static struct clk wdt3_ick = {
2715 .name = "wdt3_ick", 2714 .name = "wdt3_ick",
2716 .ops = &clkops_omap2_dflt_wait, 2715 .ops = &clkops_omap2_iclk_dflt_wait,
2717 .parent = &per_l4_ick, 2716 .parent = &per_l4_ick,
2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2718 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2723,7 +2722,7 @@ static struct clk wdt3_ick = {
2723 2722
2724static struct clk uart3_ick = { 2723static struct clk uart3_ick = {
2725 .name = "uart3_ick", 2724 .name = "uart3_ick",
2726 .ops = &clkops_omap2_dflt_wait, 2725 .ops = &clkops_omap2_iclk_dflt_wait,
2727 .parent = &per_l4_ick, 2726 .parent = &per_l4_ick,
2728 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2728 .enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2733,7 +2732,7 @@ static struct clk uart3_ick = {
2733 2732
2734static struct clk uart4_ick = { 2733static struct clk uart4_ick = {
2735 .name = "uart4_ick", 2734 .name = "uart4_ick",
2736 .ops = &clkops_omap2_dflt_wait, 2735 .ops = &clkops_omap2_iclk_dflt_wait,
2737 .parent = &per_l4_ick, 2736 .parent = &per_l4_ick,
2738 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739 .enable_bit = OMAP3630_EN_UART4_SHIFT, 2738 .enable_bit = OMAP3630_EN_UART4_SHIFT,
@@ -2743,7 +2742,7 @@ static struct clk uart4_ick = {
2743 2742
2744static struct clk gpt9_ick = { 2743static struct clk gpt9_ick = {
2745 .name = "gpt9_ick", 2744 .name = "gpt9_ick",
2746 .ops = &clkops_omap2_dflt_wait, 2745 .ops = &clkops_omap2_iclk_dflt_wait,
2747 .parent = &per_l4_ick, 2746 .parent = &per_l4_ick,
2748 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2748 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2753,7 +2752,7 @@ static struct clk gpt9_ick = {
2753 2752
2754static struct clk gpt8_ick = { 2753static struct clk gpt8_ick = {
2755 .name = "gpt8_ick", 2754 .name = "gpt8_ick",
2756 .ops = &clkops_omap2_dflt_wait, 2755 .ops = &clkops_omap2_iclk_dflt_wait,
2757 .parent = &per_l4_ick, 2756 .parent = &per_l4_ick,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2758 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2763,7 +2762,7 @@ static struct clk gpt8_ick = {
2763 2762
2764static struct clk gpt7_ick = { 2763static struct clk gpt7_ick = {
2765 .name = "gpt7_ick", 2764 .name = "gpt7_ick",
2766 .ops = &clkops_omap2_dflt_wait, 2765 .ops = &clkops_omap2_iclk_dflt_wait,
2767 .parent = &per_l4_ick, 2766 .parent = &per_l4_ick,
2768 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2768 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2773,7 +2772,7 @@ static struct clk gpt7_ick = {
2773 2772
2774static struct clk gpt6_ick = { 2773static struct clk gpt6_ick = {
2775 .name = "gpt6_ick", 2774 .name = "gpt6_ick",
2776 .ops = &clkops_omap2_dflt_wait, 2775 .ops = &clkops_omap2_iclk_dflt_wait,
2777 .parent = &per_l4_ick, 2776 .parent = &per_l4_ick,
2778 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2778 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2783,7 +2782,7 @@ static struct clk gpt6_ick = {
2783 2782
2784static struct clk gpt5_ick = { 2783static struct clk gpt5_ick = {
2785 .name = "gpt5_ick", 2784 .name = "gpt5_ick",
2786 .ops = &clkops_omap2_dflt_wait, 2785 .ops = &clkops_omap2_iclk_dflt_wait,
2787 .parent = &per_l4_ick, 2786 .parent = &per_l4_ick,
2788 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2787 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2788 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2793,7 +2792,7 @@ static struct clk gpt5_ick = {
2793 2792
2794static struct clk gpt4_ick = { 2793static struct clk gpt4_ick = {
2795 .name = "gpt4_ick", 2794 .name = "gpt4_ick",
2796 .ops = &clkops_omap2_dflt_wait, 2795 .ops = &clkops_omap2_iclk_dflt_wait,
2797 .parent = &per_l4_ick, 2796 .parent = &per_l4_ick,
2798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2798 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2803,7 +2802,7 @@ static struct clk gpt4_ick = {
2803 2802
2804static struct clk gpt3_ick = { 2803static struct clk gpt3_ick = {
2805 .name = "gpt3_ick", 2804 .name = "gpt3_ick",
2806 .ops = &clkops_omap2_dflt_wait, 2805 .ops = &clkops_omap2_iclk_dflt_wait,
2807 .parent = &per_l4_ick, 2806 .parent = &per_l4_ick,
2808 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2808 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2813,7 +2812,7 @@ static struct clk gpt3_ick = {
2813 2812
2814static struct clk gpt2_ick = { 2813static struct clk gpt2_ick = {
2815 .name = "gpt2_ick", 2814 .name = "gpt2_ick",
2816 .ops = &clkops_omap2_dflt_wait, 2815 .ops = &clkops_omap2_iclk_dflt_wait,
2817 .parent = &per_l4_ick, 2816 .parent = &per_l4_ick,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2818 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2823,7 +2822,7 @@ static struct clk gpt2_ick = {
2823 2822
2824static struct clk mcbsp2_ick = { 2823static struct clk mcbsp2_ick = {
2825 .name = "mcbsp2_ick", 2824 .name = "mcbsp2_ick",
2826 .ops = &clkops_omap2_dflt_wait, 2825 .ops = &clkops_omap2_iclk_dflt_wait,
2827 .parent = &per_l4_ick, 2826 .parent = &per_l4_ick,
2828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2833,7 +2832,7 @@ static struct clk mcbsp2_ick = {
2833 2832
2834static struct clk mcbsp3_ick = { 2833static struct clk mcbsp3_ick = {
2835 .name = "mcbsp3_ick", 2834 .name = "mcbsp3_ick",
2836 .ops = &clkops_omap2_dflt_wait, 2835 .ops = &clkops_omap2_iclk_dflt_wait,
2837 .parent = &per_l4_ick, 2836 .parent = &per_l4_ick,
2838 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2837 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2838 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2843,7 +2842,7 @@ static struct clk mcbsp3_ick = {
2843 2842
2844static struct clk mcbsp4_ick = { 2843static struct clk mcbsp4_ick = {
2845 .name = "mcbsp4_ick", 2844 .name = "mcbsp4_ick",
2846 .ops = &clkops_omap2_dflt_wait, 2845 .ops = &clkops_omap2_iclk_dflt_wait,
2847 .parent = &per_l4_ick, 2846 .parent = &per_l4_ick,
2848 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3186,7 +3185,7 @@ static struct clk vpfe_fck = {
3186 */ 3185 */
3187static struct clk uart4_ick_am35xx = { 3186static struct clk uart4_ick_am35xx = {
3188 .name = "uart4_ick", 3187 .name = "uart4_ick",
3189 .ops = &clkops_omap2_dflt_wait, 3188 .ops = &clkops_omap2_iclk_dflt_wait,
3190 .parent = &core_l4_ick, 3189 .parent = &core_l4_ick,
3191 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 3190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3192 .enable_bit = AM35XX_EN_UART4_SHIFT, 3191 .enable_bit = AM35XX_EN_UART4_SHIFT,
@@ -3538,6 +3537,9 @@ int __init omap3xxx_clk_init(void)
3538 omap2_init_clk_clkdm(c->lk.clk); 3537 omap2_init_clk_clkdm(c->lk.clk);
3539 } 3538 }
3540 3539
3540 /* Disable autoidle on all clocks; let the PM code enable it later */
3541 omap_clk_disable_autoidle_all();
3542
3541 recalculate_root_clocks(); 3543 recalculate_root_clocks();
3542 3544
3543 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 3545 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@@ -3551,7 +3553,8 @@ int __init omap3xxx_clk_init(void)
3551 clk_enable_init_clocks(); 3553 clk_enable_init_clocks();
3552 3554
3553 /* 3555 /*
3554 * Lock DPLL5 and put it in autoidle. 3556 * Lock DPLL5 -- here only until other device init code can
3557 * handle this
3555 */ 3558 */
3556 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) 3559 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3557 omap3_clk_lock_dpll5(); 3560 omap3_clk_lock_dpll5();
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fdbc0426b6f4..f1fedb71ae08 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
278static struct clk dpll_abe_x2_ck = { 278static struct clk dpll_abe_x2_ck = {
279 .name = "dpll_abe_x2_ck", 279 .name = "dpll_abe_x2_ck",
280 .parent = &dpll_abe_ck, 280 .parent = &dpll_abe_ck,
281 .ops = &clkops_null, 281 .flags = CLOCK_CLKOUTX2,
282 .ops = &clkops_omap4_dpllmx_ops,
282 .recalc = &omap3_clkoutx2_recalc, 283 .recalc = &omap3_clkoutx2_recalc,
284 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
283}; 285};
284 286
285static const struct clksel_rate div31_1to31_rates[] = { 287static const struct clksel_rate div31_1to31_rates[] = {
@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
328 .clksel = dpll_abe_m2x2_div, 330 .clksel = dpll_abe_m2x2_div,
329 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, 331 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
330 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 332 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
331 .ops = &clkops_null, 333 .ops = &clkops_omap4_dpllmx_ops,
332 .recalc = &omap2_clksel_recalc, 334 .recalc = &omap2_clksel_recalc,
333 .round_rate = &omap2_clksel_round_rate, 335 .round_rate = &omap2_clksel_round_rate,
334 .set_rate = &omap2_clksel_set_rate, 336 .set_rate = &omap2_clksel_set_rate,
@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
395 .clksel = dpll_abe_m2x2_div, 397 .clksel = dpll_abe_m2x2_div,
396 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, 398 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
397 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 399 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
398 .ops = &clkops_null, 400 .ops = &clkops_omap4_dpllmx_ops,
399 .recalc = &omap2_clksel_recalc, 401 .recalc = &omap2_clksel_recalc,
400 .round_rate = &omap2_clksel_round_rate, 402 .round_rate = &omap2_clksel_round_rate,
401 .set_rate = &omap2_clksel_set_rate, 403 .set_rate = &omap2_clksel_set_rate,
@@ -443,13 +445,14 @@ static struct clk dpll_core_ck = {
443 .parent = &sys_clkin_ck, 445 .parent = &sys_clkin_ck,
444 .dpll_data = &dpll_core_dd, 446 .dpll_data = &dpll_core_dd,
445 .init = &omap2_init_dpll_parent, 447 .init = &omap2_init_dpll_parent,
446 .ops = &clkops_null, 448 .ops = &clkops_omap3_core_dpll_ops,
447 .recalc = &omap3_dpll_recalc, 449 .recalc = &omap3_dpll_recalc,
448}; 450};
449 451
450static struct clk dpll_core_x2_ck = { 452static struct clk dpll_core_x2_ck = {
451 .name = "dpll_core_x2_ck", 453 .name = "dpll_core_x2_ck",
452 .parent = &dpll_core_ck, 454 .parent = &dpll_core_ck,
455 .flags = CLOCK_CLKOUTX2,
453 .ops = &clkops_null, 456 .ops = &clkops_null,
454 .recalc = &omap3_clkoutx2_recalc, 457 .recalc = &omap3_clkoutx2_recalc,
455}; 458};
@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
465 .clksel = dpll_core_m6x2_div, 468 .clksel = dpll_core_m6x2_div,
466 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, 469 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
467 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 470 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
468 .ops = &clkops_null, 471 .ops = &clkops_omap4_dpllmx_ops,
469 .recalc = &omap2_clksel_recalc, 472 .recalc = &omap2_clksel_recalc,
470 .round_rate = &omap2_clksel_round_rate, 473 .round_rate = &omap2_clksel_round_rate,
471 .set_rate = &omap2_clksel_set_rate, 474 .set_rate = &omap2_clksel_set_rate,
@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
495 .clksel = dpll_core_m2_div, 498 .clksel = dpll_core_m2_div,
496 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, 499 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
497 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 500 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
498 .ops = &clkops_null, 501 .ops = &clkops_omap4_dpllmx_ops,
499 .recalc = &omap2_clksel_recalc, 502 .recalc = &omap2_clksel_recalc,
500 .round_rate = &omap2_clksel_round_rate, 503 .round_rate = &omap2_clksel_round_rate,
501 .set_rate = &omap2_clksel_set_rate, 504 .set_rate = &omap2_clksel_set_rate,
@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
515 .clksel = dpll_core_m6x2_div, 518 .clksel = dpll_core_m6x2_div,
516 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, 519 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
517 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 520 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
518 .ops = &clkops_null, 521 .ops = &clkops_omap4_dpllmx_ops,
519 .recalc = &omap2_clksel_recalc, 522 .recalc = &omap2_clksel_recalc,
520 .round_rate = &omap2_clksel_round_rate, 523 .round_rate = &omap2_clksel_round_rate,
521 .set_rate = &omap2_clksel_set_rate, 524 .set_rate = &omap2_clksel_set_rate,
@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
581 .clksel = dpll_core_m6x2_div, 584 .clksel = dpll_core_m6x2_div,
582 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, 585 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
583 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 586 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
584 .ops = &clkops_null, 587 .ops = &clkops_omap4_dpllmx_ops,
585 .recalc = &omap2_clksel_recalc, 588 .recalc = &omap2_clksel_recalc,
586 .round_rate = &omap2_clksel_round_rate, 589 .round_rate = &omap2_clksel_round_rate,
587 .set_rate = &omap2_clksel_set_rate, 590 .set_rate = &omap2_clksel_set_rate,
@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
606 .clksel = dpll_abe_m2_div, 609 .clksel = dpll_abe_m2_div,
607 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, 610 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
608 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 611 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
609 .ops = &clkops_null, 612 .ops = &clkops_omap4_dpllmx_ops,
610 .recalc = &omap2_clksel_recalc, 613 .recalc = &omap2_clksel_recalc,
611 .round_rate = &omap2_clksel_round_rate, 614 .round_rate = &omap2_clksel_round_rate,
612 .set_rate = &omap2_clksel_set_rate, 615 .set_rate = &omap2_clksel_set_rate,
@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
632 .clksel = dpll_core_m6x2_div, 635 .clksel = dpll_core_m6x2_div,
633 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, 636 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
634 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 637 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
635 .ops = &clkops_null, 638 .ops = &clkops_omap4_dpllmx_ops,
636 .recalc = &omap2_clksel_recalc, 639 .recalc = &omap2_clksel_recalc,
637 .round_rate = &omap2_clksel_round_rate, 640 .round_rate = &omap2_clksel_round_rate,
638 .set_rate = &omap2_clksel_set_rate, 641 .set_rate = &omap2_clksel_set_rate,
@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
689static struct clk dpll_iva_x2_ck = { 692static struct clk dpll_iva_x2_ck = {
690 .name = "dpll_iva_x2_ck", 693 .name = "dpll_iva_x2_ck",
691 .parent = &dpll_iva_ck, 694 .parent = &dpll_iva_ck,
695 .flags = CLOCK_CLKOUTX2,
692 .ops = &clkops_null, 696 .ops = &clkops_null,
693 .recalc = &omap3_clkoutx2_recalc, 697 .recalc = &omap3_clkoutx2_recalc,
694}; 698};
@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
704 .clksel = dpll_iva_m4x2_div, 708 .clksel = dpll_iva_m4x2_div,
705 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, 709 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
706 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 710 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
707 .ops = &clkops_null, 711 .ops = &clkops_omap4_dpllmx_ops,
708 .recalc = &omap2_clksel_recalc, 712 .recalc = &omap2_clksel_recalc,
709 .round_rate = &omap2_clksel_round_rate, 713 .round_rate = &omap2_clksel_round_rate,
710 .set_rate = &omap2_clksel_set_rate, 714 .set_rate = &omap2_clksel_set_rate,
@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
716 .clksel = dpll_iva_m4x2_div, 720 .clksel = dpll_iva_m4x2_div,
717 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, 721 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
718 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 722 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
719 .ops = &clkops_null, 723 .ops = &clkops_omap4_dpllmx_ops,
720 .recalc = &omap2_clksel_recalc, 724 .recalc = &omap2_clksel_recalc,
721 .round_rate = &omap2_clksel_round_rate, 725 .round_rate = &omap2_clksel_round_rate,
722 .set_rate = &omap2_clksel_set_rate, 726 .set_rate = &omap2_clksel_set_rate,
@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
764 .clksel = dpll_mpu_m2_div, 768 .clksel = dpll_mpu_m2_div,
765 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, 769 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
766 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 770 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
767 .ops = &clkops_null, 771 .ops = &clkops_omap4_dpllmx_ops,
768 .recalc = &omap2_clksel_recalc, 772 .recalc = &omap2_clksel_recalc,
769 .round_rate = &omap2_clksel_round_rate, 773 .round_rate = &omap2_clksel_round_rate,
770 .set_rate = &omap2_clksel_set_rate, 774 .set_rate = &omap2_clksel_set_rate,
@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
837 .clksel = dpll_per_m2_div, 841 .clksel = dpll_per_m2_div,
838 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, 842 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
839 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 843 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
840 .ops = &clkops_null, 844 .ops = &clkops_omap4_dpllmx_ops,
841 .recalc = &omap2_clksel_recalc, 845 .recalc = &omap2_clksel_recalc,
842 .round_rate = &omap2_clksel_round_rate, 846 .round_rate = &omap2_clksel_round_rate,
843 .set_rate = &omap2_clksel_set_rate, 847 .set_rate = &omap2_clksel_set_rate,
@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
846static struct clk dpll_per_x2_ck = { 850static struct clk dpll_per_x2_ck = {
847 .name = "dpll_per_x2_ck", 851 .name = "dpll_per_x2_ck",
848 .parent = &dpll_per_ck, 852 .parent = &dpll_per_ck,
849 .ops = &clkops_null, 853 .flags = CLOCK_CLKOUTX2,
854 .ops = &clkops_omap4_dpllmx_ops,
850 .recalc = &omap3_clkoutx2_recalc, 855 .recalc = &omap3_clkoutx2_recalc,
856 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
851}; 857};
852 858
853static const struct clksel dpll_per_m2x2_div[] = { 859static const struct clksel dpll_per_m2x2_div[] = {
@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
861 .clksel = dpll_per_m2x2_div, 867 .clksel = dpll_per_m2x2_div,
862 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, 868 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
863 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 869 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
864 .ops = &clkops_null, 870 .ops = &clkops_omap4_dpllmx_ops,
865 .recalc = &omap2_clksel_recalc, 871 .recalc = &omap2_clksel_recalc,
866 .round_rate = &omap2_clksel_round_rate, 872 .round_rate = &omap2_clksel_round_rate,
867 .set_rate = &omap2_clksel_set_rate, 873 .set_rate = &omap2_clksel_set_rate,
@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
887 .clksel = dpll_per_m2x2_div, 893 .clksel = dpll_per_m2x2_div,
888 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, 894 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
889 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, 895 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
890 .ops = &clkops_null, 896 .ops = &clkops_omap4_dpllmx_ops,
891 .recalc = &omap2_clksel_recalc, 897 .recalc = &omap2_clksel_recalc,
892 .round_rate = &omap2_clksel_round_rate, 898 .round_rate = &omap2_clksel_round_rate,
893 .set_rate = &omap2_clksel_set_rate, 899 .set_rate = &omap2_clksel_set_rate,
@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
899 .clksel = dpll_per_m2x2_div, 905 .clksel = dpll_per_m2x2_div,
900 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, 906 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
901 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, 907 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
902 .ops = &clkops_null, 908 .ops = &clkops_omap4_dpllmx_ops,
903 .recalc = &omap2_clksel_recalc, 909 .recalc = &omap2_clksel_recalc,
904 .round_rate = &omap2_clksel_round_rate, 910 .round_rate = &omap2_clksel_round_rate,
905 .set_rate = &omap2_clksel_set_rate, 911 .set_rate = &omap2_clksel_set_rate,
@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
911 .clksel = dpll_per_m2x2_div, 917 .clksel = dpll_per_m2x2_div,
912 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, 918 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
913 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, 919 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
914 .ops = &clkops_null, 920 .ops = &clkops_omap4_dpllmx_ops,
915 .recalc = &omap2_clksel_recalc, 921 .recalc = &omap2_clksel_recalc,
916 .round_rate = &omap2_clksel_round_rate, 922 .round_rate = &omap2_clksel_round_rate,
917 .set_rate = &omap2_clksel_set_rate, 923 .set_rate = &omap2_clksel_set_rate,
@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
923 .clksel = dpll_per_m2x2_div, 929 .clksel = dpll_per_m2x2_div,
924 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, 930 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
925 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, 931 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
926 .ops = &clkops_null, 932 .ops = &clkops_omap4_dpllmx_ops,
927 .recalc = &omap2_clksel_recalc, 933 .recalc = &omap2_clksel_recalc,
928 .round_rate = &omap2_clksel_round_rate, 934 .round_rate = &omap2_clksel_round_rate,
929 .set_rate = &omap2_clksel_set_rate, 935 .set_rate = &omap2_clksel_set_rate,
@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
964static struct clk dpll_unipro_x2_ck = { 970static struct clk dpll_unipro_x2_ck = {
965 .name = "dpll_unipro_x2_ck", 971 .name = "dpll_unipro_x2_ck",
966 .parent = &dpll_unipro_ck, 972 .parent = &dpll_unipro_ck,
973 .flags = CLOCK_CLKOUTX2,
967 .ops = &clkops_null, 974 .ops = &clkops_null,
968 .recalc = &omap3_clkoutx2_recalc, 975 .recalc = &omap3_clkoutx2_recalc,
969}; 976};
@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
979 .clksel = dpll_unipro_m2x2_div, 986 .clksel = dpll_unipro_m2x2_div,
980 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, 987 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
981 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 988 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
982 .ops = &clkops_null, 989 .ops = &clkops_omap4_dpllmx_ops,
983 .recalc = &omap2_clksel_recalc, 990 .recalc = &omap2_clksel_recalc,
984 .round_rate = &omap2_clksel_round_rate, 991 .round_rate = &omap2_clksel_round_rate,
985 .set_rate = &omap2_clksel_set_rate, 992 .set_rate = &omap2_clksel_set_rate,
@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
1028static struct clk dpll_usb_clkdcoldo_ck = { 1035static struct clk dpll_usb_clkdcoldo_ck = {
1029 .name = "dpll_usb_clkdcoldo_ck", 1036 .name = "dpll_usb_clkdcoldo_ck",
1030 .parent = &dpll_usb_ck, 1037 .parent = &dpll_usb_ck,
1031 .ops = &clkops_null, 1038 .ops = &clkops_omap4_dpllmx_ops,
1039 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
1032 .recalc = &followparent_recalc, 1040 .recalc = &followparent_recalc,
1033}; 1041};
1034 1042
@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
1043 .clksel = dpll_usb_m2_div, 1051 .clksel = dpll_usb_m2_div,
1044 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, 1052 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
1045 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, 1053 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1046 .ops = &clkops_null, 1054 .ops = &clkops_omap4_dpllmx_ops,
1047 .recalc = &omap2_clksel_recalc, 1055 .recalc = &omap2_clksel_recalc,
1048 .round_rate = &omap2_clksel_round_rate, 1056 .round_rate = &omap2_clksel_round_rate,
1049 .set_rate = &omap2_clksel_set_rate, 1057 .set_rate = &omap2_clksel_set_rate,
@@ -3301,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
3301 omap2_init_clk_clkdm(c->lk.clk); 3309 omap2_init_clk_clkdm(c->lk.clk);
3302 } 3310 }
3303 3311
3312 /* Disable autoidle on all clocks; let the PM code enable it later */
3313 omap_clk_disable_autoidle_all();
3314
3304 recalculate_root_clocks(); 3315 recalculate_root_clocks();
3305 3316
3306 /* 3317 /*
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 1cf8131205fa..6424d46be14a 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = {
37 { .div = 0 } 37 { .div = 0 }
38}; 38};
39 39
40const struct clksel_rate dsp_ick_rates[] = {
41 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
42 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
43 { .div = 3, .val = 3, .flags = RATE_IN_243X },
44 { .div = 0 },
45};
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 58e42f76603f..ab878545bd9b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -26,17 +26,8 @@
26 26
27#include <linux/bitops.h> 27#include <linux/bitops.h>
28 28
29#include "prm2xxx_3xxx.h"
30#include "prm-regbits-24xx.h"
31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-24xx.h"
33#include "cminst44xx.h"
34#include "prcm44xx.h"
35
36#include <plat/clock.h> 29#include <plat/clock.h>
37#include "powerdomain.h"
38#include "clockdomain.h" 30#include "clockdomain.h"
39#include <plat/prcm.h>
40 31
41/* clkdm_list contains all registered struct clockdomains */ 32/* clkdm_list contains all registered struct clockdomains */
42static LIST_HEAD(clkdm_list); 33static LIST_HEAD(clkdm_list);
@@ -44,6 +35,7 @@ static LIST_HEAD(clkdm_list);
44/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */ 35/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
45static struct clkdm_autodep *autodeps; 36static struct clkdm_autodep *autodeps;
46 37
38static struct clkdm_ops *arch_clkdm;
47 39
48/* Private functions */ 40/* Private functions */
49 41
@@ -177,11 +169,11 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
177 * XXX autodeps are deprecated and should be removed at the earliest 169 * XXX autodeps are deprecated and should be removed at the earliest
178 * opportunity 170 * opportunity
179 */ 171 */
180static void _clkdm_add_autodeps(struct clockdomain *clkdm) 172void _clkdm_add_autodeps(struct clockdomain *clkdm)
181{ 173{
182 struct clkdm_autodep *autodep; 174 struct clkdm_autodep *autodep;
183 175
184 if (!autodeps) 176 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
185 return; 177 return;
186 178
187 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 179 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -211,11 +203,11 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
211 * XXX autodeps are deprecated and should be removed at the earliest 203 * XXX autodeps are deprecated and should be removed at the earliest
212 * opportunity 204 * opportunity
213 */ 205 */
214static void _clkdm_del_autodeps(struct clockdomain *clkdm) 206void _clkdm_del_autodeps(struct clockdomain *clkdm)
215{ 207{
216 struct clkdm_autodep *autodep; 208 struct clkdm_autodep *autodep;
217 209
218 if (!autodeps) 210 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
219 return; 211 return;
220 212
221 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 213 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -235,55 +227,29 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
235} 227}
236 228
237/** 229/**
238 * _enable_hwsup - place a clockdomain into hardware-supervised idle 230 * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
239 * @clkdm: struct clockdomain * 231 * @clkdm: clockdomain that we are resolving dependencies for
240 * 232 * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
241 * Place the clockdomain into hardware-supervised idle mode. No return
242 * value.
243 * 233 *
244 * XXX Should this return an error if the clockdomain does not support 234 * Iterates through @clkdm_deps, looking up the struct clockdomain named by
245 * hardware-supervised idle mode? 235 * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
246 */
247static void _enable_hwsup(struct clockdomain *clkdm)
248{
249 if (cpu_is_omap24xx())
250 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
251 clkdm->clktrctrl_mask);
252 else if (cpu_is_omap34xx())
253 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
254 clkdm->clktrctrl_mask);
255 else if (cpu_is_omap44xx())
256 return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
257 clkdm->cm_inst,
258 clkdm->clkdm_offs);
259 else
260 BUG();
261}
262
263/**
264 * _disable_hwsup - place a clockdomain into software-supervised idle
265 * @clkdm: struct clockdomain *
266 *
267 * Place the clockdomain @clkdm into software-supervised idle mode.
268 * No return value. 236 * No return value.
269 *
270 * XXX Should this return an error if the clockdomain does not support
271 * software-supervised idle mode?
272 */ 237 */
273static void _disable_hwsup(struct clockdomain *clkdm) 238static void _resolve_clkdm_deps(struct clockdomain *clkdm,
239 struct clkdm_dep *clkdm_deps)
274{ 240{
275 if (cpu_is_omap24xx()) 241 struct clkdm_dep *cd;
276 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 242
277 clkdm->clktrctrl_mask); 243 for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
278 else if (cpu_is_omap34xx()) 244 if (!omap_chip_is(cd->omap_chip))
279 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 245 continue;
280 clkdm->clktrctrl_mask); 246 if (cd->clkdm)
281 else if (cpu_is_omap44xx()) 247 continue;
282 return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 248 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
283 clkdm->cm_inst, 249
284 clkdm->clkdm_offs); 250 WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
285 else 251 clkdm->name, cd->clkdm_name);
286 BUG(); 252 }
287} 253}
288 254
289/* Public functions */ 255/* Public functions */
@@ -292,6 +258,7 @@ static void _disable_hwsup(struct clockdomain *clkdm)
292 * clkdm_init - set up the clockdomain layer 258 * clkdm_init - set up the clockdomain layer
293 * @clkdms: optional pointer to an array of clockdomains to register 259 * @clkdms: optional pointer to an array of clockdomains to register
294 * @init_autodeps: optional pointer to an array of autodeps to register 260 * @init_autodeps: optional pointer to an array of autodeps to register
261 * @custom_funcs: func pointers for arch specfic implementations
295 * 262 *
296 * Set up internal state. If a pointer to an array of clockdomains 263 * Set up internal state. If a pointer to an array of clockdomains
297 * @clkdms was supplied, loop through the list of clockdomains, 264 * @clkdms was supplied, loop through the list of clockdomains,
@@ -300,12 +267,18 @@ static void _disable_hwsup(struct clockdomain *clkdm)
300 * @init_autodeps was provided, register those. No return value. 267 * @init_autodeps was provided, register those. No return value.
301 */ 268 */
302void clkdm_init(struct clockdomain **clkdms, 269void clkdm_init(struct clockdomain **clkdms,
303 struct clkdm_autodep *init_autodeps) 270 struct clkdm_autodep *init_autodeps,
271 struct clkdm_ops *custom_funcs)
304{ 272{
305 struct clockdomain **c = NULL; 273 struct clockdomain **c = NULL;
306 struct clockdomain *clkdm; 274 struct clockdomain *clkdm;
307 struct clkdm_autodep *autodep = NULL; 275 struct clkdm_autodep *autodep = NULL;
308 276
277 if (!custom_funcs)
278 WARN(1, "No custom clkdm functions registered\n");
279 else
280 arch_clkdm = custom_funcs;
281
309 if (clkdms) 282 if (clkdms)
310 for (c = clkdms; *c; c++) 283 for (c = clkdms; *c; c++)
311 _clkdm_register(*c); 284 _clkdm_register(*c);
@@ -321,11 +294,14 @@ void clkdm_init(struct clockdomain **clkdms,
321 */ 294 */
322 list_for_each_entry(clkdm, &clkdm_list, node) { 295 list_for_each_entry(clkdm, &clkdm_list, node) {
323 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) 296 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
324 omap2_clkdm_wakeup(clkdm); 297 clkdm_wakeup(clkdm);
325 else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) 298 else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
326 omap2_clkdm_deny_idle(clkdm); 299 clkdm_deny_idle(clkdm);
327 300
301 _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
328 clkdm_clear_all_wkdeps(clkdm); 302 clkdm_clear_all_wkdeps(clkdm);
303
304 _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
329 clkdm_clear_all_sleepdeps(clkdm); 305 clkdm_clear_all_sleepdeps(clkdm);
330 } 306 }
331} 307}
@@ -422,32 +398,32 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
422int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 398int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
423{ 399{
424 struct clkdm_dep *cd; 400 struct clkdm_dep *cd;
425 401 int ret = 0;
426 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
427 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
428 clkdm1->name, clkdm2->name, __func__);
429 return -EINVAL;
430 }
431 402
432 if (!clkdm1 || !clkdm2) 403 if (!clkdm1 || !clkdm2)
433 return -EINVAL; 404 return -EINVAL;
434 405
435 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 406 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
436 if (IS_ERR(cd)) { 407 if (IS_ERR(cd))
408 ret = PTR_ERR(cd);
409
410 if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
411 ret = -EINVAL;
412
413 if (ret) {
437 pr_debug("clockdomain: hardware cannot set/clear wake up of " 414 pr_debug("clockdomain: hardware cannot set/clear wake up of "
438 "%s when %s wakes up\n", clkdm1->name, clkdm2->name); 415 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
439 return PTR_ERR(cd); 416 return ret;
440 } 417 }
441 418
442 if (atomic_inc_return(&cd->wkdep_usecount) == 1) { 419 if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
443 pr_debug("clockdomain: hardware will wake up %s when %s wakes " 420 pr_debug("clockdomain: hardware will wake up %s when %s wakes "
444 "up\n", clkdm1->name, clkdm2->name); 421 "up\n", clkdm1->name, clkdm2->name);
445 422
446 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), 423 ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
447 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
448 } 424 }
449 425
450 return 0; 426 return ret;
451} 427}
452 428
453/** 429/**
@@ -463,32 +439,32 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
463int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 439int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
464{ 440{
465 struct clkdm_dep *cd; 441 struct clkdm_dep *cd;
466 442 int ret = 0;
467 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
468 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
469 clkdm1->name, clkdm2->name, __func__);
470 return -EINVAL;
471 }
472 443
473 if (!clkdm1 || !clkdm2) 444 if (!clkdm1 || !clkdm2)
474 return -EINVAL; 445 return -EINVAL;
475 446
476 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 447 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
477 if (IS_ERR(cd)) { 448 if (IS_ERR(cd))
449 ret = PTR_ERR(cd);
450
451 if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
452 ret = -EINVAL;
453
454 if (ret) {
478 pr_debug("clockdomain: hardware cannot set/clear wake up of " 455 pr_debug("clockdomain: hardware cannot set/clear wake up of "
479 "%s when %s wakes up\n", clkdm1->name, clkdm2->name); 456 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
480 return PTR_ERR(cd); 457 return ret;
481 } 458 }
482 459
483 if (atomic_dec_return(&cd->wkdep_usecount) == 0) { 460 if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
484 pr_debug("clockdomain: hardware will no longer wake up %s " 461 pr_debug("clockdomain: hardware will no longer wake up %s "
485 "after %s wakes up\n", clkdm1->name, clkdm2->name); 462 "after %s wakes up\n", clkdm1->name, clkdm2->name);
486 463
487 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), 464 ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
488 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
489 } 465 }
490 466
491 return 0; 467 return ret;
492} 468}
493 469
494/** 470/**
@@ -508,26 +484,26 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
508int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 484int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
509{ 485{
510 struct clkdm_dep *cd; 486 struct clkdm_dep *cd;
487 int ret = 0;
511 488
512 if (!clkdm1 || !clkdm2) 489 if (!clkdm1 || !clkdm2)
513 return -EINVAL; 490 return -EINVAL;
514 491
515 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
516 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
517 clkdm1->name, clkdm2->name, __func__);
518 return -EINVAL;
519 }
520
521 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 492 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
522 if (IS_ERR(cd)) { 493 if (IS_ERR(cd))
494 ret = PTR_ERR(cd);
495
496 if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
497 ret = -EINVAL;
498
499 if (ret) {
523 pr_debug("clockdomain: hardware cannot set/clear wake up of " 500 pr_debug("clockdomain: hardware cannot set/clear wake up of "
524 "%s when %s wakes up\n", clkdm1->name, clkdm2->name); 501 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
525 return PTR_ERR(cd); 502 return ret;
526 } 503 }
527 504
528 /* XXX It's faster to return the atomic wkdep_usecount */ 505 /* XXX It's faster to return the atomic wkdep_usecount */
529 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, 506 return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
530 (1 << clkdm2->dep_bit));
531} 507}
532 508
533/** 509/**
@@ -542,33 +518,13 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
542 */ 518 */
543int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) 519int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
544{ 520{
545 struct clkdm_dep *cd;
546 u32 mask = 0;
547
548 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
549 pr_err("clockdomain: %s: %s: not yet implemented\n",
550 clkdm->name, __func__);
551 return -EINVAL;
552 }
553
554 if (!clkdm) 521 if (!clkdm)
555 return -EINVAL; 522 return -EINVAL;
556 523
557 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 524 if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
558 if (!omap_chip_is(cd->omap_chip)) 525 return -EINVAL;
559 continue;
560
561 if (!cd->clkdm && cd->clkdm_name)
562 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
563
564 /* PRM accesses are slow, so minimize them */
565 mask |= 1 << cd->clkdm->dep_bit;
566 atomic_set(&cd->wkdep_usecount, 0);
567 }
568
569 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
570 526
571 return 0; 527 return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
572} 528}
573 529
574/** 530/**
@@ -586,31 +542,33 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
586int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 542int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
587{ 543{
588 struct clkdm_dep *cd; 544 struct clkdm_dep *cd;
589 545 int ret = 0;
590 if (!cpu_is_omap34xx())
591 return -EINVAL;
592 546
593 if (!clkdm1 || !clkdm2) 547 if (!clkdm1 || !clkdm2)
594 return -EINVAL; 548 return -EINVAL;
595 549
596 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); 550 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
597 if (IS_ERR(cd)) { 551 if (IS_ERR(cd))
552 ret = PTR_ERR(cd);
553
554 if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
555 ret = -EINVAL;
556
557 if (ret) {
598 pr_debug("clockdomain: hardware cannot set/clear sleep " 558 pr_debug("clockdomain: hardware cannot set/clear sleep "
599 "dependency affecting %s from %s\n", clkdm1->name, 559 "dependency affecting %s from %s\n", clkdm1->name,
600 clkdm2->name); 560 clkdm2->name);
601 return PTR_ERR(cd); 561 return ret;
602 } 562 }
603 563
604 if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { 564 if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
605 pr_debug("clockdomain: will prevent %s from sleeping if %s " 565 pr_debug("clockdomain: will prevent %s from sleeping if %s "
606 "is active\n", clkdm1->name, clkdm2->name); 566 "is active\n", clkdm1->name, clkdm2->name);
607 567
608 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), 568 ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
609 clkdm1->pwrdm.ptr->prcm_offs,
610 OMAP3430_CM_SLEEPDEP);
611 } 569 }
612 570
613 return 0; 571 return ret;
614} 572}
615 573
616/** 574/**
@@ -628,19 +586,23 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
628int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 586int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
629{ 587{
630 struct clkdm_dep *cd; 588 struct clkdm_dep *cd;
631 589 int ret = 0;
632 if (!cpu_is_omap34xx())
633 return -EINVAL;
634 590
635 if (!clkdm1 || !clkdm2) 591 if (!clkdm1 || !clkdm2)
636 return -EINVAL; 592 return -EINVAL;
637 593
638 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); 594 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
639 if (IS_ERR(cd)) { 595 if (IS_ERR(cd))
596 ret = PTR_ERR(cd);
597
598 if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
599 ret = -EINVAL;
600
601 if (ret) {
640 pr_debug("clockdomain: hardware cannot set/clear sleep " 602 pr_debug("clockdomain: hardware cannot set/clear sleep "
641 "dependency affecting %s from %s\n", clkdm1->name, 603 "dependency affecting %s from %s\n", clkdm1->name,
642 clkdm2->name); 604 clkdm2->name);
643 return PTR_ERR(cd); 605 return ret;
644 } 606 }
645 607
646 if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { 608 if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
@@ -648,12 +610,10 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
648 "sleeping if %s is active\n", clkdm1->name, 610 "sleeping if %s is active\n", clkdm1->name,
649 clkdm2->name); 611 clkdm2->name);
650 612
651 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), 613 ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
652 clkdm1->pwrdm.ptr->prcm_offs,
653 OMAP3430_CM_SLEEPDEP);
654 } 614 }
655 615
656 return 0; 616 return ret;
657} 617}
658 618
659/** 619/**
@@ -675,25 +635,27 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
675int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 635int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
676{ 636{
677 struct clkdm_dep *cd; 637 struct clkdm_dep *cd;
678 638 int ret = 0;
679 if (!cpu_is_omap34xx())
680 return -EINVAL;
681 639
682 if (!clkdm1 || !clkdm2) 640 if (!clkdm1 || !clkdm2)
683 return -EINVAL; 641 return -EINVAL;
684 642
685 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); 643 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
686 if (IS_ERR(cd)) { 644 if (IS_ERR(cd))
645 ret = PTR_ERR(cd);
646
647 if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
648 ret = -EINVAL;
649
650 if (ret) {
687 pr_debug("clockdomain: hardware cannot set/clear sleep " 651 pr_debug("clockdomain: hardware cannot set/clear sleep "
688 "dependency affecting %s from %s\n", clkdm1->name, 652 "dependency affecting %s from %s\n", clkdm1->name,
689 clkdm2->name); 653 clkdm2->name);
690 return PTR_ERR(cd); 654 return ret;
691 } 655 }
692 656
693 /* XXX It's faster to return the atomic sleepdep_usecount */ 657 /* XXX It's faster to return the atomic sleepdep_usecount */
694 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, 658 return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
695 OMAP3430_CM_SLEEPDEP,
696 (1 << clkdm2->dep_bit));
697} 659}
698 660
699/** 661/**
@@ -708,35 +670,17 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
708 */ 670 */
709int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) 671int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
710{ 672{
711 struct clkdm_dep *cd;
712 u32 mask = 0;
713
714 if (!cpu_is_omap34xx())
715 return -EINVAL;
716
717 if (!clkdm) 673 if (!clkdm)
718 return -EINVAL; 674 return -EINVAL;
719 675
720 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { 676 if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
721 if (!omap_chip_is(cd->omap_chip)) 677 return -EINVAL;
722 continue;
723
724 if (!cd->clkdm && cd->clkdm_name)
725 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
726
727 /* PRM accesses are slow, so minimize them */
728 mask |= 1 << cd->clkdm->dep_bit;
729 atomic_set(&cd->sleepdep_usecount, 0);
730 }
731
732 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
733 OMAP3430_CM_SLEEPDEP);
734 678
735 return 0; 679 return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
736} 680}
737 681
738/** 682/**
739 * omap2_clkdm_sleep - force clockdomain sleep transition 683 * clkdm_sleep - force clockdomain sleep transition
740 * @clkdm: struct clockdomain * 684 * @clkdm: struct clockdomain *
741 * 685 *
742 * Instruct the CM to force a sleep transition on the specified 686 * Instruct the CM to force a sleep transition on the specified
@@ -744,7 +688,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
744 * clockdomain does not support software-initiated sleep; 0 upon 688 * clockdomain does not support software-initiated sleep; 0 upon
745 * success. 689 * success.
746 */ 690 */
747int omap2_clkdm_sleep(struct clockdomain *clkdm) 691int clkdm_sleep(struct clockdomain *clkdm)
748{ 692{
749 if (!clkdm) 693 if (!clkdm)
750 return -EINVAL; 694 return -EINVAL;
@@ -755,33 +699,16 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
755 return -EINVAL; 699 return -EINVAL;
756 } 700 }
757 701
758 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); 702 if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
759 703 return -EINVAL;
760 if (cpu_is_omap24xx()) {
761
762 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
763 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
764
765 } else if (cpu_is_omap34xx()) {
766
767 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
768 clkdm->clktrctrl_mask);
769
770 } else if (cpu_is_omap44xx()) {
771
772 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
773 clkdm->cm_inst,
774 clkdm->clkdm_offs);
775 704
776 } else { 705 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
777 BUG();
778 };
779 706
780 return 0; 707 return arch_clkdm->clkdm_sleep(clkdm);
781} 708}
782 709
783/** 710/**
784 * omap2_clkdm_wakeup - force clockdomain wakeup transition 711 * clkdm_wakeup - force clockdomain wakeup transition
785 * @clkdm: struct clockdomain * 712 * @clkdm: struct clockdomain *
786 * 713 *
787 * Instruct the CM to force a wakeup transition on the specified 714 * Instruct the CM to force a wakeup transition on the specified
@@ -789,7 +716,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
789 * clockdomain does not support software-controlled wakeup; 0 upon 716 * clockdomain does not support software-controlled wakeup; 0 upon
790 * success. 717 * success.
791 */ 718 */
792int omap2_clkdm_wakeup(struct clockdomain *clkdm) 719int clkdm_wakeup(struct clockdomain *clkdm)
793{ 720{
794 if (!clkdm) 721 if (!clkdm)
795 return -EINVAL; 722 return -EINVAL;
@@ -800,33 +727,16 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
800 return -EINVAL; 727 return -EINVAL;
801 } 728 }
802 729
803 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); 730 if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
804 731 return -EINVAL;
805 if (cpu_is_omap24xx()) {
806
807 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
808 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
809
810 } else if (cpu_is_omap34xx()) {
811
812 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
813 clkdm->clktrctrl_mask);
814
815 } else if (cpu_is_omap44xx()) {
816
817 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
818 clkdm->cm_inst,
819 clkdm->clkdm_offs);
820 732
821 } else { 733 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
822 BUG();
823 };
824 734
825 return 0; 735 return arch_clkdm->clkdm_wakeup(clkdm);
826} 736}
827 737
828/** 738/**
829 * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm 739 * clkdm_allow_idle - enable hwsup idle transitions for clkdm
830 * @clkdm: struct clockdomain * 740 * @clkdm: struct clockdomain *
831 * 741 *
832 * Allow the hardware to automatically switch the clockdomain @clkdm into 742 * Allow the hardware to automatically switch the clockdomain @clkdm into
@@ -835,7 +745,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
835 * framework, wkdep/sleepdep autodependencies are added; this is so 745 * framework, wkdep/sleepdep autodependencies are added; this is so
836 * device drivers can read and write to the device. No return value. 746 * device drivers can read and write to the device. No return value.
837 */ 747 */
838void omap2_clkdm_allow_idle(struct clockdomain *clkdm) 748void clkdm_allow_idle(struct clockdomain *clkdm)
839{ 749{
840 if (!clkdm) 750 if (!clkdm)
841 return; 751 return;
@@ -846,27 +756,18 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
846 return; 756 return;
847 } 757 }
848 758
759 if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
760 return;
761
849 pr_debug("clockdomain: enabling automatic idle transitions for %s\n", 762 pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
850 clkdm->name); 763 clkdm->name);
851 764
852 /* 765 arch_clkdm->clkdm_allow_idle(clkdm);
853 * XXX This should be removed once TI adds wakeup/sleep
854 * dependency code and data for OMAP4.
855 */
856 if (cpu_is_omap44xx()) {
857 pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
858 } else {
859 if (atomic_read(&clkdm->usecount) > 0)
860 _clkdm_add_autodeps(clkdm);
861 }
862
863 _enable_hwsup(clkdm);
864
865 pwrdm_clkdm_state_switch(clkdm); 766 pwrdm_clkdm_state_switch(clkdm);
866} 767}
867 768
868/** 769/**
869 * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm 770 * clkdm_deny_idle - disable hwsup idle transitions for clkdm
870 * @clkdm: struct clockdomain * 771 * @clkdm: struct clockdomain *
871 * 772 *
872 * Prevent the hardware from automatically switching the clockdomain 773 * Prevent the hardware from automatically switching the clockdomain
@@ -874,7 +775,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
874 * downstream clocks enabled in the clock framework, wkdep/sleepdep 775 * downstream clocks enabled in the clock framework, wkdep/sleepdep
875 * autodependencies are removed. No return value. 776 * autodependencies are removed. No return value.
876 */ 777 */
877void omap2_clkdm_deny_idle(struct clockdomain *clkdm) 778void clkdm_deny_idle(struct clockdomain *clkdm)
878{ 779{
879 if (!clkdm) 780 if (!clkdm)
880 return; 781 return;
@@ -885,28 +786,20 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
885 return; 786 return;
886 } 787 }
887 788
789 if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
790 return;
791
888 pr_debug("clockdomain: disabling automatic idle transitions for %s\n", 792 pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
889 clkdm->name); 793 clkdm->name);
890 794
891 _disable_hwsup(clkdm); 795 arch_clkdm->clkdm_deny_idle(clkdm);
892
893 /*
894 * XXX This should be removed once TI adds wakeup/sleep
895 * dependency code and data for OMAP4.
896 */
897 if (cpu_is_omap44xx()) {
898 pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
899 } else {
900 if (atomic_read(&clkdm->usecount) > 0)
901 _clkdm_del_autodeps(clkdm);
902 }
903} 796}
904 797
905 798
906/* Clockdomain-to-clock framework interface code */ 799/* Clockdomain-to-clock framework interface code */
907 800
908/** 801/**
909 * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm 802 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
910 * @clkdm: struct clockdomain * 803 * @clkdm: struct clockdomain *
911 * @clk: struct clk * of the enabled downstream clock 804 * @clk: struct clk * of the enabled downstream clock
912 * 805 *
@@ -919,10 +812,8 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
919 * by on-chip processors. Returns -EINVAL if passed null pointers; 812 * by on-chip processors. Returns -EINVAL if passed null pointers;
920 * returns 0 upon success or if the clockdomain is in hwsup idle mode. 813 * returns 0 upon success or if the clockdomain is in hwsup idle mode.
921 */ 814 */
922int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) 815int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
923{ 816{
924 bool hwsup = false;
925
926 /* 817 /*
927 * XXX Rewrite this code to maintain a list of enabled 818 * XXX Rewrite this code to maintain a list of enabled
928 * downstream clocks for debugging purposes? 819 * downstream clocks for debugging purposes?
@@ -931,6 +822,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
931 if (!clkdm || !clk) 822 if (!clkdm || !clk)
932 return -EINVAL; 823 return -EINVAL;
933 824
825 if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
826 return -EINVAL;
827
934 if (atomic_inc_return(&clkdm->usecount) > 1) 828 if (atomic_inc_return(&clkdm->usecount) > 1)
935 return 0; 829 return 0;
936 830
@@ -939,31 +833,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
939 pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, 833 pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
940 clk->name); 834 clk->name);
941 835
942 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 836 arch_clkdm->clkdm_clk_enable(clkdm);
943
944 if (!clkdm->clktrctrl_mask)
945 return 0;
946
947 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
948 clkdm->clktrctrl_mask);
949
950 } else if (cpu_is_omap44xx()) {
951
952 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
953 clkdm->cm_inst,
954 clkdm->clkdm_offs);
955
956 }
957
958 if (hwsup) {
959 /* Disable HW transitions when we are changing deps */
960 _disable_hwsup(clkdm);
961 _clkdm_add_autodeps(clkdm);
962 _enable_hwsup(clkdm);
963 } else {
964 omap2_clkdm_wakeup(clkdm);
965 }
966
967 pwrdm_wait_transition(clkdm->pwrdm.ptr); 837 pwrdm_wait_transition(clkdm->pwrdm.ptr);
968 pwrdm_clkdm_state_switch(clkdm); 838 pwrdm_clkdm_state_switch(clkdm);
969 839
@@ -971,7 +841,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
971} 841}
972 842
973/** 843/**
974 * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm 844 * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
975 * @clkdm: struct clockdomain * 845 * @clkdm: struct clockdomain *
976 * @clk: struct clk * of the disabled downstream clock 846 * @clk: struct clk * of the disabled downstream clock
977 * 847 *
@@ -984,10 +854,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
984 * is enabled; or returns 0 upon success or if the clockdomain is in 854 * is enabled; or returns 0 upon success or if the clockdomain is in
985 * hwsup idle mode. 855 * hwsup idle mode.
986 */ 856 */
987int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) 857int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
988{ 858{
989 bool hwsup = false;
990
991 /* 859 /*
992 * XXX Rewrite this code to maintain a list of enabled 860 * XXX Rewrite this code to maintain a list of enabled
993 * downstream clocks for debugging purposes? 861 * downstream clocks for debugging purposes?
@@ -996,6 +864,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
996 if (!clkdm || !clk) 864 if (!clkdm || !clk)
997 return -EINVAL; 865 return -EINVAL;
998 866
867 if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
868 return -EINVAL;
869
999#ifdef DEBUG 870#ifdef DEBUG
1000 if (atomic_read(&clkdm->usecount) == 0) { 871 if (atomic_read(&clkdm->usecount) == 0) {
1001 WARN_ON(1); /* underflow */ 872 WARN_ON(1); /* underflow */
@@ -1011,31 +882,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
1011 pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, 882 pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
1012 clk->name); 883 clk->name);
1013 884
1014 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 885 arch_clkdm->clkdm_clk_disable(clkdm);
1015
1016 if (!clkdm->clktrctrl_mask)
1017 return 0;
1018
1019 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
1020 clkdm->clktrctrl_mask);
1021
1022 } else if (cpu_is_omap44xx()) {
1023
1024 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
1025 clkdm->cm_inst,
1026 clkdm->clkdm_offs);
1027
1028 }
1029
1030 if (hwsup) {
1031 /* Disable HW transitions when we are changing deps */
1032 _disable_hwsup(clkdm);
1033 _clkdm_del_autodeps(clkdm);
1034 _enable_hwsup(clkdm);
1035 } else {
1036 omap2_clkdm_sleep(clkdm);
1037 }
1038
1039 pwrdm_clkdm_state_switch(clkdm); 886 pwrdm_clkdm_state_switch(clkdm);
1040 887
1041 return 0; 888 return 0;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 9b459c26fb85..85b3dce65640 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -4,7 +4,7 @@
4 * OMAP2/3 clockdomain framework functions 4 * OMAP2/3 clockdomain framework functions
5 * 5 *
6 * Copyright (C) 2008 Texas Instruments, Inc. 6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008-2010 Nokia Corporation 7 * Copyright (C) 2008-2011 Nokia Corporation
8 * 8 *
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
@@ -22,11 +22,19 @@
22#include <plat/clock.h> 22#include <plat/clock.h>
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24 24
25/* Clockdomain capability flags */ 25/*
26 * Clockdomain flags
27 *
28 * XXX Document CLKDM_CAN_* flags
29 *
30 * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
31 * clockdomain. (Currently, this applies to OMAP3 clockdomains only.)
32 */
26#define CLKDM_CAN_FORCE_SLEEP (1 << 0) 33#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
27#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) 34#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
28#define CLKDM_CAN_ENABLE_AUTO (1 << 2) 35#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
29#define CLKDM_CAN_DISABLE_AUTO (1 << 3) 36#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
37#define CLKDM_NO_AUTODEPS (1 << 4)
30 38
31#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) 39#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
32#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) 40#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -116,7 +124,42 @@ struct clockdomain {
116 struct list_head node; 124 struct list_head node;
117}; 125};
118 126
119void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); 127/**
128 * struct clkdm_ops - Arch specfic function implementations
129 * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
130 * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
131 * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
132 * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
133 * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
134 * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
135 * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
136 * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
137 * @clkdm_sleep: Force a clockdomain to sleep
138 * @clkdm_wakeup: Force a clockdomain to wakeup
139 * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
140 * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
141 * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
142 * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
143 */
144struct clkdm_ops {
145 int (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
146 int (*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
147 int (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
148 int (*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
149 int (*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
150 int (*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
151 int (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
152 int (*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
153 int (*clkdm_sleep)(struct clockdomain *clkdm);
154 int (*clkdm_wakeup)(struct clockdomain *clkdm);
155 void (*clkdm_allow_idle)(struct clockdomain *clkdm);
156 void (*clkdm_deny_idle)(struct clockdomain *clkdm);
157 int (*clkdm_clk_enable)(struct clockdomain *clkdm);
158 int (*clkdm_clk_disable)(struct clockdomain *clkdm);
159};
160
161void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
162 struct clkdm_ops *custom_funcs);
120struct clockdomain *clkdm_lookup(const char *name); 163struct clockdomain *clkdm_lookup(const char *name);
121 164
122int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), 165int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
@@ -132,16 +175,23 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
132int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); 175int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
133int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); 176int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
134 177
135void omap2_clkdm_allow_idle(struct clockdomain *clkdm); 178void clkdm_allow_idle(struct clockdomain *clkdm);
136void omap2_clkdm_deny_idle(struct clockdomain *clkdm); 179void clkdm_deny_idle(struct clockdomain *clkdm);
137 180
138int omap2_clkdm_wakeup(struct clockdomain *clkdm); 181int clkdm_wakeup(struct clockdomain *clkdm);
139int omap2_clkdm_sleep(struct clockdomain *clkdm); 182int clkdm_sleep(struct clockdomain *clkdm);
140 183
141int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); 184int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
142int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); 185int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
143 186
144extern void __init omap2_clockdomains_init(void); 187extern void __init omap2xxx_clockdomains_init(void);
188extern void __init omap3xxx_clockdomains_init(void);
145extern void __init omap44xx_clockdomains_init(void); 189extern void __init omap44xx_clockdomains_init(void);
190extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
191extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
192
193extern struct clkdm_ops omap2_clkdm_operations;
194extern struct clkdm_ops omap3_clkdm_operations;
195extern struct clkdm_ops omap4_clkdm_operations;
146 196
147#endif 197#endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
new file mode 100644
index 000000000000..48d0db7e6069
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -0,0 +1,274 @@
1/*
2 * OMAP2 and OMAP3 clockdomain control
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/types.h>
16#include <plat/prcm.h>
17#include "prm.h"
18#include "prm2xxx_3xxx.h"
19#include "cm.h"
20#include "cm2xxx_3xxx.h"
21#include "cm-regbits-24xx.h"
22#include "cm-regbits-34xx.h"
23#include "prm-regbits-24xx.h"
24#include "clockdomain.h"
25
26static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
27 struct clockdomain *clkdm2)
28{
29 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
30 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
31 return 0;
32}
33
34static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
35 struct clockdomain *clkdm2)
36{
37 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
38 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
39 return 0;
40}
41
42static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
43 struct clockdomain *clkdm2)
44{
45 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
46 PM_WKDEP, (1 << clkdm2->dep_bit));
47}
48
49static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 /* PRM accesses are slow, so minimize them */
61 mask |= 1 << cd->clkdm->dep_bit;
62 atomic_set(&cd->wkdep_usecount, 0);
63 }
64
65 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
66 PM_WKDEP);
67 return 0;
68}
69
70static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
71 struct clockdomain *clkdm2)
72{
73 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
74 clkdm1->pwrdm.ptr->prcm_offs,
75 OMAP3430_CM_SLEEPDEP);
76 return 0;
77}
78
79static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
80 struct clockdomain *clkdm2)
81{
82 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
83 clkdm1->pwrdm.ptr->prcm_offs,
84 OMAP3430_CM_SLEEPDEP);
85 return 0;
86}
87
88static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
89 struct clockdomain *clkdm2)
90{
91 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
92 OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
93}
94
95static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
96{
97 struct clkdm_dep *cd;
98 u32 mask = 0;
99
100 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
101 if (!omap_chip_is(cd->omap_chip))
102 continue;
103 if (!cd->clkdm)
104 continue; /* only happens if data is erroneous */
105
106 /* PRM accesses are slow, so minimize them */
107 mask |= 1 << cd->clkdm->dep_bit;
108 atomic_set(&cd->sleepdep_usecount, 0);
109 }
110 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
111 OMAP3430_CM_SLEEPDEP);
112 return 0;
113}
114
115static int omap2_clkdm_sleep(struct clockdomain *clkdm)
116{
117 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
118 clkdm->pwrdm.ptr->prcm_offs,
119 OMAP2_PM_PWSTCTRL);
120 return 0;
121}
122
123static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
124{
125 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
126 clkdm->pwrdm.ptr->prcm_offs,
127 OMAP2_PM_PWSTCTRL);
128 return 0;
129}
130
131static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
132{
133 if (atomic_read(&clkdm->usecount) > 0)
134 _clkdm_add_autodeps(clkdm);
135
136 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
137 clkdm->clktrctrl_mask);
138}
139
140static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
141{
142 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
143 clkdm->clktrctrl_mask);
144
145 if (atomic_read(&clkdm->usecount) > 0)
146 _clkdm_del_autodeps(clkdm);
147}
148
149static void _enable_hwsup(struct clockdomain *clkdm)
150{
151 if (cpu_is_omap24xx())
152 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
153 clkdm->clktrctrl_mask);
154 else if (cpu_is_omap34xx())
155 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
156 clkdm->clktrctrl_mask);
157}
158
159static void _disable_hwsup(struct clockdomain *clkdm)
160{
161 if (cpu_is_omap24xx())
162 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
163 clkdm->clktrctrl_mask);
164 else if (cpu_is_omap34xx())
165 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
166 clkdm->clktrctrl_mask);
167}
168
169
170static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
171{
172 bool hwsup = false;
173
174 if (!clkdm->clktrctrl_mask)
175 return 0;
176
177 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
178 clkdm->clktrctrl_mask);
179
180 if (hwsup) {
181 /* Disable HW transitions when we are changing deps */
182 _disable_hwsup(clkdm);
183 _clkdm_add_autodeps(clkdm);
184 _enable_hwsup(clkdm);
185 } else {
186 clkdm_wakeup(clkdm);
187 }
188
189 return 0;
190}
191
192static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
193{
194 bool hwsup = false;
195
196 if (!clkdm->clktrctrl_mask)
197 return 0;
198
199 hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
200 clkdm->clktrctrl_mask);
201
202 if (hwsup) {
203 /* Disable HW transitions when we are changing deps */
204 _disable_hwsup(clkdm);
205 _clkdm_del_autodeps(clkdm);
206 _enable_hwsup(clkdm);
207 } else {
208 clkdm_sleep(clkdm);
209 }
210
211 return 0;
212}
213
214static int omap3_clkdm_sleep(struct clockdomain *clkdm)
215{
216 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
217 clkdm->clktrctrl_mask);
218 return 0;
219}
220
221static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
222{
223 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
224 clkdm->clktrctrl_mask);
225 return 0;
226}
227
228static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
229{
230 if (atomic_read(&clkdm->usecount) > 0)
231 _clkdm_add_autodeps(clkdm);
232
233 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
234 clkdm->clktrctrl_mask);
235}
236
237static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
238{
239 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
240 clkdm->clktrctrl_mask);
241
242 if (atomic_read(&clkdm->usecount) > 0)
243 _clkdm_del_autodeps(clkdm);
244}
245
246struct clkdm_ops omap2_clkdm_operations = {
247 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
248 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
249 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
250 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
251 .clkdm_sleep = omap2_clkdm_sleep,
252 .clkdm_wakeup = omap2_clkdm_wakeup,
253 .clkdm_allow_idle = omap2_clkdm_allow_idle,
254 .clkdm_deny_idle = omap2_clkdm_deny_idle,
255 .clkdm_clk_enable = omap2_clkdm_clk_enable,
256 .clkdm_clk_disable = omap2_clkdm_clk_disable,
257};
258
259struct clkdm_ops omap3_clkdm_operations = {
260 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
261 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
262 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
263 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
264 .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
265 .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
266 .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
267 .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
268 .clkdm_sleep = omap3_clkdm_sleep,
269 .clkdm_wakeup = omap3_clkdm_wakeup,
270 .clkdm_allow_idle = omap3_clkdm_allow_idle,
271 .clkdm_deny_idle = omap3_clkdm_deny_idle,
272 .clkdm_clk_enable = omap2_clkdm_clk_enable,
273 .clkdm_clk_disable = omap2_clkdm_clk_disable,
274};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
new file mode 100644
index 000000000000..a1a4ecd26544
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -0,0 +1,137 @@
1/*
2 * OMAP4 clockdomain control
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include "clockdomain.h"
17#include "cminst44xx.h"
18#include "cm44xx.h"
19
20static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
21 struct clockdomain *clkdm2)
22{
23 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
24 clkdm1->prcm_partition,
25 clkdm1->cm_inst, clkdm1->clkdm_offs +
26 OMAP4_CM_STATICDEP);
27 return 0;
28}
29
30static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
31 struct clockdomain *clkdm2)
32{
33 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
34 clkdm1->prcm_partition,
35 clkdm1->cm_inst, clkdm1->clkdm_offs +
36 OMAP4_CM_STATICDEP);
37 return 0;
38}
39
40static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
41 struct clockdomain *clkdm2)
42{
43 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
44 clkdm1->cm_inst, clkdm1->clkdm_offs +
45 OMAP4_CM_STATICDEP,
46 (1 << clkdm2->dep_bit));
47}
48
49static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 mask |= 1 << cd->clkdm->dep_bit;
61 atomic_set(&cd->wkdep_usecount, 0);
62 }
63
64 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
65 clkdm->cm_inst, clkdm->clkdm_offs +
66 OMAP4_CM_STATICDEP);
67 return 0;
68}
69
70static int omap4_clkdm_sleep(struct clockdomain *clkdm)
71{
72 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
73 clkdm->cm_inst, clkdm->clkdm_offs);
74 return 0;
75}
76
77static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
78{
79 omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
80 clkdm->cm_inst, clkdm->clkdm_offs);
81 return 0;
82}
83
84static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
85{
86 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
87 clkdm->cm_inst, clkdm->clkdm_offs);
88}
89
90static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
91{
92 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
93 clkdm->cm_inst, clkdm->clkdm_offs);
94}
95
96static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
97{
98 bool hwsup = false;
99
100 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
101 clkdm->cm_inst, clkdm->clkdm_offs);
102
103 if (!hwsup)
104 clkdm_wakeup(clkdm);
105
106 return 0;
107}
108
109static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
110{
111 bool hwsup = false;
112
113 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
114 clkdm->cm_inst, clkdm->clkdm_offs);
115
116 if (!hwsup)
117 clkdm_sleep(clkdm);
118
119 return 0;
120}
121
122struct clkdm_ops omap4_clkdm_operations = {
123 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
124 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
125 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
126 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
127 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
128 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
129 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
130 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
131 .clkdm_sleep = omap4_clkdm_sleep,
132 .clkdm_wakeup = omap4_clkdm_wakeup,
133 .clkdm_allow_idle = omap4_clkdm_allow_idle,
134 .clkdm_deny_idle = omap4_clkdm_deny_idle,
135 .clkdm_clk_enable = omap4_clkdm_clk_enable,
136 .clkdm_clk_disable = omap4_clkdm_clk_disable,
137};
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index e6f0d18d5e8d..13bde95b6790 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,6 +89,8 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
89 89
90/* 24XX-specific possible dependencies */ 90/* 24XX-specific possible dependencies */
91 91
92#ifdef CONFIG_ARCH_OMAP2
93
92/* Wakeup dependency source arrays */ 94/* Wakeup dependency source arrays */
93 95
94/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ 96/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
@@ -168,6 +170,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
168 { NULL }, 170 { NULL },
169}; 171};
170 172
173#endif /* CONFIG_ARCH_OMAP2 */
171 174
172/* 2430-specific possible wakeup dependencies */ 175/* 2430-specific possible wakeup dependencies */
173 176
@@ -854,7 +857,12 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
854 NULL, 857 NULL,
855}; 858};
856 859
857void __init omap2_clockdomains_init(void) 860void __init omap2xxx_clockdomains_init(void)
861{
862 clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
863}
864
865void __init omap3xxx_clockdomains_init(void)
858{ 866{
859 clkdm_init(clockdomains_omap2, clkdm_autodeps); 867 clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
860} 868}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 10622c914abc..a607ec196e8b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -18,11 +18,6 @@
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20 20
21/*
22 * To-Do List
23 * -> Populate the Sleep/Wakeup dependencies for the domains
24 */
25
26#include <linux/kernel.h> 21#include <linux/kernel.h>
27#include <linux/io.h> 22#include <linux/io.h>
28 23
@@ -35,6 +30,355 @@
35#include "prcm44xx.h" 30#include "prcm44xx.h"
36#include "prcm_mpu44xx.h" 31#include "prcm_mpu44xx.h"
37 32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep ducati_wkup_sleep_deps[] = {
36 {
37 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
39 },
40 {
41 .clkdm_name = "ivahd_clkdm",
42 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
43 },
44 {
45 .clkdm_name = "l3_1_clkdm",
46 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
47 },
48 {
49 .clkdm_name = "l3_2_clkdm",
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 },
52 {
53 .clkdm_name = "l3_dss_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 },
56 {
57 .clkdm_name = "l3_emif_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 },
60 {
61 .clkdm_name = "l3_gfx_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 },
64 {
65 .clkdm_name = "l3_init_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 },
68 {
69 .clkdm_name = "l4_cfg_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 },
72 {
73 .clkdm_name = "l4_per_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 },
76 {
77 .clkdm_name = "l4_secure_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 },
80 {
81 .clkdm_name = "l4_wkup_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 },
84 {
85 .clkdm_name = "tesla_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 {
93 .clkdm_name = "ivahd_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 },
96 {
97 .clkdm_name = "l3_1_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 },
100 {
101 .clkdm_name = "l3_emif_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 {
109 .clkdm_name = "l3_1_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 },
112 {
113 .clkdm_name = "l3_emif_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 {
121 .clkdm_name = "abe_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 },
124 {
125 .clkdm_name = "ivahd_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 },
128 {
129 .clkdm_name = "l3_1_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 },
132 {
133 .clkdm_name = "l3_2_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 },
136 {
137 .clkdm_name = "l3_emif_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 },
140 {
141 .clkdm_name = "l3_init_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 },
144 {
145 .clkdm_name = "l4_cfg_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 },
148 {
149 .clkdm_name = "l4_per_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 },
152 { NULL },
153};
154
155static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
156 {
157 .clkdm_name = "abe_clkdm",
158 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
159 },
160 {
161 .clkdm_name = "ducati_clkdm",
162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
163 },
164 {
165 .clkdm_name = "ivahd_clkdm",
166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
167 },
168 {
169 .clkdm_name = "l3_1_clkdm",
170 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
171 },
172 {
173 .clkdm_name = "l3_dss_clkdm",
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
175 },
176 {
177 .clkdm_name = "l3_emif_clkdm",
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
179 },
180 {
181 .clkdm_name = "l3_init_clkdm",
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
183 },
184 {
185 .clkdm_name = "l4_cfg_clkdm",
186 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
187 },
188 {
189 .clkdm_name = "l4_per_clkdm",
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
191 },
192 {
193 .clkdm_name = "l4_secure_clkdm",
194 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
195 },
196 {
197 .clkdm_name = "l4_wkup_clkdm",
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
199 },
200 { NULL },
201};
202
203static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
204 {
205 .clkdm_name = "ivahd_clkdm",
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
207 },
208 {
209 .clkdm_name = "l3_2_clkdm",
210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
211 },
212 {
213 .clkdm_name = "l3_emif_clkdm",
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
215 },
216 { NULL },
217};
218
219static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
220 {
221 .clkdm_name = "ivahd_clkdm",
222 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
223 },
224 {
225 .clkdm_name = "l3_1_clkdm",
226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
227 },
228 {
229 .clkdm_name = "l3_emif_clkdm",
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
231 },
232 { NULL },
233};
234
235static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
236 {
237 .clkdm_name = "abe_clkdm",
238 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
239 },
240 {
241 .clkdm_name = "ivahd_clkdm",
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
243 },
244 {
245 .clkdm_name = "l3_emif_clkdm",
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
247 },
248 {
249 .clkdm_name = "l4_cfg_clkdm",
250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
251 },
252 {
253 .clkdm_name = "l4_per_clkdm",
254 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
255 },
256 {
257 .clkdm_name = "l4_secure_clkdm",
258 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
259 },
260 {
261 .clkdm_name = "l4_wkup_clkdm",
262 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
263 },
264 { NULL },
265};
266
267static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
268 {
269 .clkdm_name = "l3_1_clkdm",
270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
271 },
272 {
273 .clkdm_name = "l3_emif_clkdm",
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
275 },
276 {
277 .clkdm_name = "l4_per_clkdm",
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
279 },
280 { NULL },
281};
282
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
284 {
285 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
287 },
288 {
289 .clkdm_name = "ducati_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
291 },
292 {
293 .clkdm_name = "ivahd_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
295 },
296 {
297 .clkdm_name = "l3_1_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
299 },
300 {
301 .clkdm_name = "l3_2_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
303 },
304 {
305 .clkdm_name = "l3_dss_clkdm",
306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
307 },
308 {
309 .clkdm_name = "l3_emif_clkdm",
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
311 },
312 {
313 .clkdm_name = "l3_gfx_clkdm",
314 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
315 },
316 {
317 .clkdm_name = "l3_init_clkdm",
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
319 },
320 {
321 .clkdm_name = "l4_cfg_clkdm",
322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
323 },
324 {
325 .clkdm_name = "l4_per_clkdm",
326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
327 },
328 {
329 .clkdm_name = "l4_secure_clkdm",
330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
331 },
332 {
333 .clkdm_name = "l4_wkup_clkdm",
334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
335 },
336 {
337 .clkdm_name = "tesla_clkdm",
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
339 },
340 { NULL },
341};
342
343static struct clkdm_dep tesla_wkup_sleep_deps[] = {
344 {
345 .clkdm_name = "abe_clkdm",
346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
347 },
348 {
349 .clkdm_name = "ivahd_clkdm",
350 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
351 },
352 {
353 .clkdm_name = "l3_1_clkdm",
354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
355 },
356 {
357 .clkdm_name = "l3_2_clkdm",
358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
359 },
360 {
361 .clkdm_name = "l3_emif_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
363 },
364 {
365 .clkdm_name = "l3_init_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
367 },
368 {
369 .clkdm_name = "l4_cfg_clkdm",
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
371 },
372 {
373 .clkdm_name = "l4_per_clkdm",
374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
375 },
376 {
377 .clkdm_name = "l4_wkup_clkdm",
378 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
379 },
380 { NULL },
381};
38 382
39static struct clockdomain l4_cefuse_44xx_clkdm = { 383static struct clockdomain l4_cefuse_44xx_clkdm = {
40 .name = "l4_cefuse_clkdm", 384 .name = "l4_cefuse_clkdm",
@@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
52 .prcm_partition = OMAP4430_CM2_PARTITION, 396 .prcm_partition = OMAP4430_CM2_PARTITION,
53 .cm_inst = OMAP4430_CM2_CORE_INST, 397 .cm_inst = OMAP4430_CM2_CORE_INST,
54 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, 398 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
399 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
55 .flags = CLKDM_CAN_HWSUP, 400 .flags = CLKDM_CAN_HWSUP,
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
57}; 402};
@@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = {
62 .prcm_partition = OMAP4430_CM1_PARTITION, 407 .prcm_partition = OMAP4430_CM1_PARTITION,
63 .cm_inst = OMAP4430_CM1_TESLA_INST, 408 .cm_inst = OMAP4430_CM1_TESLA_INST,
64 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, 409 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
410 .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
411 .wkdep_srcs = tesla_wkup_sleep_deps,
412 .sleepdep_srcs = tesla_wkup_sleep_deps,
65 .flags = CLKDM_CAN_HWSUP_SWSUP, 413 .flags = CLKDM_CAN_HWSUP_SWSUP,
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
67}; 415};
@@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
72 .prcm_partition = OMAP4430_CM2_PARTITION, 420 .prcm_partition = OMAP4430_CM2_PARTITION,
73 .cm_inst = OMAP4430_CM2_GFX_INST, 421 .cm_inst = OMAP4430_CM2_GFX_INST,
74 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, 422 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
423 .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
424 .wkdep_srcs = l3_gfx_wkup_sleep_deps,
425 .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
75 .flags = CLKDM_CAN_HWSUP_SWSUP, 426 .flags = CLKDM_CAN_HWSUP_SWSUP,
76 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 427 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
77}; 428};
@@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
82 .prcm_partition = OMAP4430_CM2_PARTITION, 433 .prcm_partition = OMAP4430_CM2_PARTITION,
83 .cm_inst = OMAP4430_CM2_IVAHD_INST, 434 .cm_inst = OMAP4430_CM2_IVAHD_INST,
84 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, 435 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
436 .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
437 .wkdep_srcs = ivahd_wkup_sleep_deps,
438 .sleepdep_srcs = ivahd_wkup_sleep_deps,
85 .flags = CLKDM_CAN_HWSUP_SWSUP, 439 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
87}; 441};
@@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
92 .prcm_partition = OMAP4430_CM2_PARTITION, 446 .prcm_partition = OMAP4430_CM2_PARTITION,
93 .cm_inst = OMAP4430_CM2_L4PER_INST, 447 .cm_inst = OMAP4430_CM2_L4PER_INST,
94 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, 448 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
449 .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
450 .wkdep_srcs = l4_secure_wkup_sleep_deps,
451 .sleepdep_srcs = l4_secure_wkup_sleep_deps,
95 .flags = CLKDM_CAN_HWSUP_SWSUP, 452 .flags = CLKDM_CAN_HWSUP_SWSUP,
96 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
97}; 454};
@@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
102 .prcm_partition = OMAP4430_CM2_PARTITION, 459 .prcm_partition = OMAP4430_CM2_PARTITION,
103 .cm_inst = OMAP4430_CM2_L4PER_INST, 460 .cm_inst = OMAP4430_CM2_L4PER_INST,
104 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, 461 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
462 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
105 .flags = CLKDM_CAN_HWSUP_SWSUP, 463 .flags = CLKDM_CAN_HWSUP_SWSUP,
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
107}; 465};
@@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = {
112 .prcm_partition = OMAP4430_CM1_PARTITION, 470 .prcm_partition = OMAP4430_CM1_PARTITION,
113 .cm_inst = OMAP4430_CM1_ABE_INST, 471 .cm_inst = OMAP4430_CM1_ABE_INST,
114 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, 472 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
473 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
115 .flags = CLKDM_CAN_HWSUP_SWSUP, 474 .flags = CLKDM_CAN_HWSUP_SWSUP,
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 475 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
117}; 476};
@@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
131 .prcm_partition = OMAP4430_CM2_PARTITION, 490 .prcm_partition = OMAP4430_CM2_PARTITION,
132 .cm_inst = OMAP4430_CM2_L3INIT_INST, 491 .cm_inst = OMAP4430_CM2_L3INIT_INST,
133 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, 492 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
493 .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
494 .wkdep_srcs = l3_init_wkup_sleep_deps,
495 .sleepdep_srcs = l3_init_wkup_sleep_deps,
134 .flags = CLKDM_CAN_HWSUP_SWSUP, 496 .flags = CLKDM_CAN_HWSUP_SWSUP,
135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
136}; 498};
@@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = {
141 .prcm_partition = OMAP4430_CM1_PARTITION, 503 .prcm_partition = OMAP4430_CM1_PARTITION,
142 .cm_inst = OMAP4430_CM1_MPU_INST, 504 .cm_inst = OMAP4430_CM1_MPU_INST,
143 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps,
144 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
145 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
146}; 510};
@@ -150,7 +514,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
150 .pwrdm = { .name = "cpu0_pwrdm" }, 514 .pwrdm = { .name = "cpu0_pwrdm" },
151 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 515 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
152 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, 516 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
153 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS, 517 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
154 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 518 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
155 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
156}; 520};
@@ -160,7 +524,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
160 .pwrdm = { .name = "cpu1_pwrdm" }, 524 .pwrdm = { .name = "cpu1_pwrdm" },
161 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 525 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
162 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, 526 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
163 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS, 527 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
164 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 528 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
166}; 530};
@@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
171 .prcm_partition = OMAP4430_CM2_PARTITION, 535 .prcm_partition = OMAP4430_CM2_PARTITION,
172 .cm_inst = OMAP4430_CM2_CORE_INST, 536 .cm_inst = OMAP4430_CM2_CORE_INST,
173 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, 537 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
538 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
174 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 539 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 540 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
176}; 541};
@@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = {
191 .prcm_partition = OMAP4430_CM2_PARTITION, 556 .prcm_partition = OMAP4430_CM2_PARTITION,
192 .cm_inst = OMAP4430_CM2_CORE_INST, 557 .cm_inst = OMAP4430_CM2_CORE_INST,
193 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, 558 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
559 .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
560 .wkdep_srcs = ducati_wkup_sleep_deps,
561 .sleepdep_srcs = ducati_wkup_sleep_deps,
194 .flags = CLKDM_CAN_HWSUP_SWSUP, 562 .flags = CLKDM_CAN_HWSUP_SWSUP,
195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
196}; 564};
@@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
201 .prcm_partition = OMAP4430_CM2_PARTITION, 569 .prcm_partition = OMAP4430_CM2_PARTITION,
202 .cm_inst = OMAP4430_CM2_CORE_INST, 570 .cm_inst = OMAP4430_CM2_CORE_INST,
203 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, 571 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
572 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
204 .flags = CLKDM_CAN_HWSUP, 573 .flags = CLKDM_CAN_HWSUP,
205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
206}; 575};
@@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
211 .prcm_partition = OMAP4430_CM2_PARTITION, 580 .prcm_partition = OMAP4430_CM2_PARTITION,
212 .cm_inst = OMAP4430_CM2_CORE_INST, 581 .cm_inst = OMAP4430_CM2_CORE_INST,
213 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, 582 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
583 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
214 .flags = CLKDM_CAN_HWSUP, 584 .flags = CLKDM_CAN_HWSUP,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216}; 586};
@@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
221 .prcm_partition = OMAP4430_CM2_PARTITION, 591 .prcm_partition = OMAP4430_CM2_PARTITION,
222 .cm_inst = OMAP4430_CM2_CORE_INST, 592 .cm_inst = OMAP4430_CM2_CORE_INST,
223 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, 593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
224 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
225 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
226}; 598};
@@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = {
231 .prcm_partition = OMAP4430_CM2_PARTITION, 603 .prcm_partition = OMAP4430_CM2_PARTITION,
232 .cm_inst = OMAP4430_CM2_CAM_INST, 604 .cm_inst = OMAP4430_CM2_CAM_INST,
233 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, 605 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
606 .wkdep_srcs = iss_wkup_sleep_deps,
607 .sleepdep_srcs = iss_wkup_sleep_deps,
234 .flags = CLKDM_CAN_HWSUP_SWSUP, 608 .flags = CLKDM_CAN_HWSUP_SWSUP,
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
236}; 610};
@@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
241 .prcm_partition = OMAP4430_CM2_PARTITION, 615 .prcm_partition = OMAP4430_CM2_PARTITION,
242 .cm_inst = OMAP4430_CM2_DSS_INST, 616 .cm_inst = OMAP4430_CM2_DSS_INST,
243 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, 617 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
618 .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
619 .wkdep_srcs = l3_dss_wkup_sleep_deps,
620 .sleepdep_srcs = l3_dss_wkup_sleep_deps,
244 .flags = CLKDM_CAN_HWSUP_SWSUP, 621 .flags = CLKDM_CAN_HWSUP_SWSUP,
245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
246}; 623};
@@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
251 .prcm_partition = OMAP4430_PRM_PARTITION, 628 .prcm_partition = OMAP4430_PRM_PARTITION,
252 .cm_inst = OMAP4430_PRM_WKUP_CM_INST, 629 .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
253 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 630 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
631 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
254 .flags = CLKDM_CAN_HWSUP, 632 .flags = CLKDM_CAN_HWSUP,
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256}; 634};
@@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = {
271 .prcm_partition = OMAP4430_CM2_PARTITION, 649 .prcm_partition = OMAP4430_CM2_PARTITION,
272 .cm_inst = OMAP4430_CM2_CORE_INST, 650 .cm_inst = OMAP4430_CM2_CORE_INST,
273 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, 651 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
652 .wkdep_srcs = l3_dma_wkup_sleep_deps,
653 .sleepdep_srcs = l3_dma_wkup_sleep_deps,
274 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 654 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
276}; 656};
@@ -305,5 +685,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
305 685
306void __init omap44xx_clockdomains_init(void) 686void __init omap44xx_clockdomains_init(void)
307{ 687{
308 clkdm_init(clockdomains_omap44xx, NULL); 688 clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
309} 689}
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index d70660e82fe6..686290437568 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -210,8 +210,11 @@
210#define OMAP24XX_AUTO_USB_MASK (1 << 0) 210#define OMAP24XX_AUTO_USB_MASK (1 << 0)
211 211
212/* CM_AUTOIDLE3_CORE */ 212/* CM_AUTOIDLE3_CORE */
213#define OMAP24XX_AUTO_SDRC_SHIFT 2
213#define OMAP24XX_AUTO_SDRC_MASK (1 << 2) 214#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
215#define OMAP24XX_AUTO_GPMC_SHIFT 1
214#define OMAP24XX_AUTO_GPMC_MASK (1 << 1) 216#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
217#define OMAP24XX_AUTO_SDMA_SHIFT 0
215#define OMAP24XX_AUTO_SDMA_MASK (1 << 0) 218#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
216 219
217/* CM_AUTOIDLE4_CORE */ 220/* CM_AUTOIDLE4_CORE */
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 96954aa48671..9d0dec806e92 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -25,6 +25,14 @@
25#include "cm-regbits-24xx.h" 25#include "cm-regbits-24xx.h"
26#include "cm-regbits-34xx.h" 26#include "cm-regbits-34xx.h"
27 27
28/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
29#define DPLL_AUTOIDLE_DISABLE 0x0
30#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
31
32/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
33#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
34#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
35
28static const u8 cm_idlest_offs[] = { 36static const u8 cm_idlest_offs[] = {
29 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 37 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
30}; 38};
@@ -125,6 +133,67 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
125 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); 133 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
126} 134}
127 135
136/*
137 * DPLL autoidle control
138 */
139
140static void _omap2xxx_set_dpll_autoidle(u8 m)
141{
142 u32 v;
143
144 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
145 v &= ~OMAP24XX_AUTO_DPLL_MASK;
146 v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
147 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
148}
149
150void omap2xxx_cm_set_dpll_disable_autoidle(void)
151{
152 _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
153}
154
155void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
156{
157 _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
158}
159
160/*
161 * APLL autoidle control
162 */
163
164static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
165{
166 u32 v;
167
168 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
169 v &= ~mask;
170 v |= m << __ffs(mask);
171 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
172}
173
174void omap2xxx_cm_set_apll54_disable_autoidle(void)
175{
176 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
177 OMAP24XX_AUTO_54M_MASK);
178}
179
180void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
181{
182 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
183 OMAP24XX_AUTO_54M_MASK);
184}
185
186void omap2xxx_cm_set_apll96_disable_autoidle(void)
187{
188 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
189 OMAP24XX_AUTO_96M_MASK);
190}
191
192void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
193{
194 _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
195 OMAP24XX_AUTO_96M_MASK);
196}
128 197
129/* 198/*
130 * 199 *
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 5e9ea5bd60b9..088bbad73db5 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -122,6 +122,14 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
122extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); 122extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
123extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); 123extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
124 124
125extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
126extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
127
128extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
129extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
130extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
131extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
132
125#endif 133#endif
126 134
127/* CM register bits shared between 24XX and 3430 */ 135/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 48fc3f426fbd..0b87ec82b41c 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -21,6 +21,7 @@
21#include "cm.h" 21#include "cm.h"
22 22
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004
24 25
25/* Function prototypes */ 26/* Function prototypes */
26# ifndef __ASSEMBLER__ 27# ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index c04bbbea17a5..a482bfa0a954 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -73,6 +73,27 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
73 return v; 73 return v;
74} 74}
75 75
76u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
77{
78 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
79}
80
81u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
82{
83 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
84}
85
86u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
87{
88 u32 v;
89
90 v = omap4_cminst_read_inst_reg(part, inst, idx);
91 v &= mask;
92 v >>= __ffs(mask);
93
94 return v;
95}
96
76/* 97/*
77 * 98 *
78 */ 99 */
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a6abd0a8cb82..2b32c181a2ee 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -25,6 +25,12 @@ extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
25extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); 25extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
26extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, 26extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
27 s16 inst, s16 idx); 27 s16 inst, s16 idx);
28extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
29 s16 idx);
30extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
31 s16 idx);
32extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
33 u32 mask);
28 34
29extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); 35extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
30 36
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f7b22a16f385..7cc80715ef12 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -99,14 +99,14 @@ static int omap3_idle_bm_check(void)
99static int _cpuidle_allow_idle(struct powerdomain *pwrdm, 99static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
100 struct clockdomain *clkdm) 100 struct clockdomain *clkdm)
101{ 101{
102 omap2_clkdm_allow_idle(clkdm); 102 clkdm_allow_idle(clkdm);
103 return 0; 103 return 0;
104} 104}
105 105
106static int _cpuidle_deny_idle(struct powerdomain *pwrdm, 106static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
107 struct clockdomain *clkdm) 107 struct clockdomain *clkdm)
108{ 108{
109 omap2_clkdm_deny_idle(clkdm); 109 clkdm_deny_idle(clkdm);
110 return 0; 110 return 0;
111} 111}
112 112
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2cb720b5b12e..0d2d6a9c303c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -36,6 +36,70 @@
36#include "mux.h" 36#include "mux.h"
37#include "control.h" 37#include "control.h"
38 38
39#define L3_MODULES_MAX_LEN 12
40#define L3_MODULES 3
41
42static int __init omap3_l3_init(void)
43{
44 int l;
45 struct omap_hwmod *oh;
46 struct omap_device *od;
47 char oh_name[L3_MODULES_MAX_LEN];
48
49 /*
50 * To avoid code running on other OMAPs in
51 * multi-omap builds
52 */
53 if (!(cpu_is_omap34xx()))
54 return -ENODEV;
55
56 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
57
58 oh = omap_hwmod_lookup(oh_name);
59
60 if (!oh)
61 pr_err("could not look up %s\n", oh_name);
62
63 od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
64 NULL, 0, 0);
65
66 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
67
68 return PTR_ERR(od);
69}
70postcore_initcall(omap3_l3_init);
71
72static int __init omap4_l3_init(void)
73{
74 int l, i;
75 struct omap_hwmod *oh[3];
76 struct omap_device *od;
77 char oh_name[L3_MODULES_MAX_LEN];
78
79 /*
80 * To avoid code running on other OMAPs in
81 * multi-omap builds
82 */
83 if (!(cpu_is_omap44xx()))
84 return -ENODEV;
85
86 for (i = 0; i < L3_MODULES; i++) {
87 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
88
89 oh[i] = omap_hwmod_lookup(oh_name);
90 if (!(oh[i]))
91 pr_err("could not look up %s\n", oh_name);
92 }
93
94 od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
95 0, NULL, 0, 0);
96
97 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
98
99 return PTR_ERR(od);
100}
101postcore_initcall(omap4_l3_init);
102
39#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 103#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
40 104
41static struct resource cam_resources[] = { 105static struct resource cam_resources[] = {
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 000000000000..4e4da6160d05
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,84 @@
1/*
2 * OMAP4-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Rajendra Nayak
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/bitops.h>
17
18#include <plat/cpu.h>
19#include <plat/clock.h>
20
21#include "clock.h"
22#include "cm-regbits-44xx.h"
23
24/* Supported only on OMAP4 */
25int omap4_dpllmx_gatectrl_read(struct clk *clk)
26{
27 u32 v;
28 u32 mask;
29
30 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
31 return -EINVAL;
32
33 mask = clk->flags & CLOCK_CLKOUTX2 ?
34 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
35 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
36
37 v = __raw_readl(clk->clksel_reg);
38 v &= mask;
39 v >>= __ffs(mask);
40
41 return v;
42}
43
44void omap4_dpllmx_allow_gatectrl(struct clk *clk)
45{
46 u32 v;
47 u32 mask;
48
49 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
50 return;
51
52 mask = clk->flags & CLOCK_CLKOUTX2 ?
53 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
54 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
55
56 v = __raw_readl(clk->clksel_reg);
57 /* Clear the bit to allow gatectrl */
58 v &= ~mask;
59 __raw_writel(v, clk->clksel_reg);
60}
61
62void omap4_dpllmx_deny_gatectrl(struct clk *clk)
63{
64 u32 v;
65 u32 mask;
66
67 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
68 return;
69
70 mask = clk->flags & CLOCK_CLKOUTX2 ?
71 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
72 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
73
74 v = __raw_readl(clk->clksel_reg);
75 /* Set the bit to deny gatectrl */
76 v |= mask;
77 __raw_writel(v, clk->clksel_reg);
78}
79
80const struct clkops clkops_omap4_dpllmx_ops = {
81 .allow_idle = omap4_dpllmx_allow_gatectrl,
82 .deny_idle = omap4_dpllmx_deny_gatectrl,
83};
84
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 657f3c84687c..441e79d043a7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -356,15 +356,15 @@ void __init omap2_init_common_infrastructure(void)
356 356
357 if (cpu_is_omap242x()) { 357 if (cpu_is_omap242x()) {
358 omap2xxx_powerdomains_init(); 358 omap2xxx_powerdomains_init();
359 omap2_clockdomains_init(); 359 omap2xxx_clockdomains_init();
360 omap2420_hwmod_init(); 360 omap2420_hwmod_init();
361 } else if (cpu_is_omap243x()) { 361 } else if (cpu_is_omap243x()) {
362 omap2xxx_powerdomains_init(); 362 omap2xxx_powerdomains_init();
363 omap2_clockdomains_init(); 363 omap2xxx_clockdomains_init();
364 omap2430_hwmod_init(); 364 omap2430_hwmod_init();
365 } else if (cpu_is_omap34xx()) { 365 } else if (cpu_is_omap34xx()) {
366 omap3xxx_powerdomains_init(); 366 omap3xxx_powerdomains_init();
367 omap2_clockdomains_init(); 367 omap3xxx_clockdomains_init();
368 omap3xxx_hwmod_init(); 368 omap3xxx_hwmod_init();
369 } else if (cpu_is_omap44xx()) { 369 } else if (cpu_is_omap44xx()) {
370 omap44xx_powerdomains_init(); 370 omap44xx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 1125134c9a7f..e39772beaedd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -457,14 +457,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
457 * will be accessed by a particular initiator (e.g., if a module will 457 * will be accessed by a particular initiator (e.g., if a module will
458 * be accessed by the IVA, there should be a sleepdep between the IVA 458 * be accessed by the IVA, there should be a sleepdep between the IVA
459 * initiator and the module). Only applies to modules in smart-idle 459 * initiator and the module). Only applies to modules in smart-idle
460 * mode. Returns -EINVAL upon error or passes along 460 * mode. If the clockdomain is marked as not needing autodeps, return
461 * clkdm_add_sleepdep() value upon success. 461 * 0 without doing anything. Otherwise, returns -EINVAL upon error or
462 * passes along clkdm_add_sleepdep() value upon success.
462 */ 463 */
463static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 464static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
464{ 465{
465 if (!oh->_clk) 466 if (!oh->_clk)
466 return -EINVAL; 467 return -EINVAL;
467 468
469 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
470 return 0;
471
468 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 472 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
469} 473}
470 474
@@ -477,14 +481,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
477 * be accessed by a particular initiator (e.g., if a module will not 481 * be accessed by a particular initiator (e.g., if a module will not
478 * be accessed by the IVA, there should be no sleepdep between the IVA 482 * be accessed by the IVA, there should be no sleepdep between the IVA
479 * initiator and the module). Only applies to modules in smart-idle 483 * initiator and the module). Only applies to modules in smart-idle
480 * mode. Returns -EINVAL upon error or passes along 484 * mode. If the clockdomain is marked as not needing autodeps, return
481 * clkdm_del_sleepdep() value upon success. 485 * 0 without doing anything. Returns -EINVAL upon error or passes
486 * along clkdm_del_sleepdep() value upon success.
482 */ 487 */
483static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 488static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
484{ 489{
485 if (!oh->_clk) 490 if (!oh->_clk)
486 return -EINVAL; 491 return -EINVAL;
487 492
493 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
494 return 0;
495
488 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 496 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
489} 497}
490 498
@@ -1283,6 +1291,42 @@ static int _idle(struct omap_hwmod *oh)
1283} 1291}
1284 1292
1285/** 1293/**
1294 * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
1295 * @oh: struct omap_hwmod *
1296 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
1297 *
1298 * Sets the IP block's OCP autoidle bit in hardware, and updates our
1299 * local copy. Intended to be used by drivers that require
1300 * direct manipulation of the AUTOIDLE bits.
1301 * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
1302 * along the return value from _set_module_autoidle().
1303 *
1304 * Any users of this function should be scrutinized carefully.
1305 */
1306int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
1307{
1308 u32 v;
1309 int retval = 0;
1310 unsigned long flags;
1311
1312 if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
1313 return -EINVAL;
1314
1315 spin_lock_irqsave(&oh->_lock, flags);
1316
1317 v = oh->_sysc_cache;
1318
1319 retval = _set_module_autoidle(oh, autoidle, &v);
1320
1321 if (!retval)
1322 _write_sysconfig(v, oh);
1323
1324 spin_unlock_irqrestore(&oh->_lock, flags);
1325
1326 return retval;
1327}
1328
1329/**
1286 * _shutdown - shutdown an omap_hwmod 1330 * _shutdown - shutdown an omap_hwmod
1287 * @oh: struct omap_hwmod * 1331 * @oh: struct omap_hwmod *
1288 * 1332 *
@@ -2286,3 +2330,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
2286 2330
2287 return ret; 2331 return ret;
2288} 2332}
2333
2334/**
2335 * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
2336 * @oh: struct omap_hwmod *
2337 *
2338 * Prevent the hwmod @oh from being reset during the setup process.
2339 * Intended for use by board-*.c files on boards with devices that
2340 * cannot tolerate being reset. Must be called before the hwmod has
2341 * been set up. Returns 0 upon success or negative error code upon
2342 * failure.
2343 */
2344int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
2345{
2346 if (!oh)
2347 return -EINVAL;
2348
2349 if (oh->_state != _HWMOD_STATE_REGISTERED) {
2350 pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
2351 oh->name);
2352 return -EINVAL;
2353 }
2354
2355 oh->flags |= HWMOD_INIT_NO_RESET;
2356
2357 return 0;
2358}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e0bc2c7a15de..61e58bd27aec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1410,6 +1410,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1410 .flags = OMAP_FIREWALL_L4, 1410 .flags = OMAP_FIREWALL_L4,
1411 } 1411 }
1412 }, 1412 },
1413 .flags = OCPIF_SWSUP_IDLE,
1413 .user = OCP_USER_MPU | OCP_USER_SDMA, 1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
1414}; 1415};
1415 1416
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4aa74d78289c..490789a6bed0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1485,6 +1485,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1485 .clk = "dss_54m_fck", 1485 .clk = "dss_54m_fck",
1486 .addr = omap2430_dss_venc_addrs, 1486 .addr = omap2430_dss_venc_addrs,
1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), 1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488 .flags = OCPIF_SWSUP_IDLE,
1488 .user = OCP_USER_MPU | OCP_USER_SDMA, 1489 .user = OCP_USER_MPU | OCP_USER_SDMA,
1489}; 1490};
1490 1491
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e2792cf9c54d..2e275cbcd654 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -100,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .user = OCP_USER_MPU | OCP_USER_SDMA, 100 .user = OCP_USER_MPU | OCP_USER_SDMA,
101}; 101};
102 102
103/* L3 taret configuration and error log registers */
104static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
105 { .irq = INT_34XX_L3_DBG_IRQ },
106 { .irq = INT_34XX_L3_APP_IRQ },
107};
108
109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110 {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
114 },
115};
116
103/* MPU -> L3 interface */ 117/* MPU -> L3 interface */
104static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 118static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
105 .master = &omap3xxx_mpu_hwmod, 119 .master = &omap3xxx_mpu_hwmod,
106 .slave = &omap3xxx_l3_main_hwmod, 120 .slave = &omap3xxx_l3_main_hwmod,
121 .addr = omap3xxx_l3_main_addrs,
122 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
107 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
108}; 124};
109 125
@@ -135,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
135static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
136 .name = "l3_main", 152 .name = "l3_main",
137 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
138 .masters = omap3xxx_l3_main_masters, 156 .masters = omap3xxx_l3_main_masters,
139 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 157 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
140 .slaves = omap3xxx_l3_main_slaves, 158 .slaves = omap3xxx_l3_main_slaves,
@@ -473,26 +491,12 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
473/* Slave interfaces on the L4_CORE interconnect */ 491/* Slave interfaces on the L4_CORE interconnect */
474static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 492static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
475 &omap3xxx_l3_main__l4_core, 493 &omap3xxx_l3_main__l4_core,
476 &omap3_l4_core__sr1,
477 &omap3_l4_core__sr2,
478};
479
480/* Master interfaces on the L4_CORE interconnect */
481static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
482 &omap3xxx_l4_core__l4_wkup,
483 &omap3_l4_core__uart1,
484 &omap3_l4_core__uart2,
485 &omap3_l4_core__i2c1,
486 &omap3_l4_core__i2c2,
487 &omap3_l4_core__i2c3,
488}; 494};
489 495
490/* L4 CORE */ 496/* L4 CORE */
491static struct omap_hwmod omap3xxx_l4_core_hwmod = { 497static struct omap_hwmod omap3xxx_l4_core_hwmod = {
492 .name = "l4_core", 498 .name = "l4_core",
493 .class = &l4_hwmod_class, 499 .class = &l4_hwmod_class,
494 .masters = omap3xxx_l4_core_masters,
495 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
496 .slaves = omap3xxx_l4_core_slaves, 500 .slaves = omap3xxx_l4_core_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), 501 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -504,18 +508,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
504 &omap3xxx_l3_main__l4_per, 508 &omap3xxx_l3_main__l4_per,
505}; 509};
506 510
507/* Master interfaces on the L4_PER interconnect */
508static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
509 &omap3_l4_per__uart3,
510 &omap3_l4_per__uart4,
511};
512
513/* L4 PER */ 511/* L4 PER */
514static struct omap_hwmod omap3xxx_l4_per_hwmod = { 512static struct omap_hwmod omap3xxx_l4_per_hwmod = {
515 .name = "l4_per", 513 .name = "l4_per",
516 .class = &l4_hwmod_class, 514 .class = &l4_hwmod_class,
517 .masters = omap3xxx_l4_per_masters,
518 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
519 .slaves = omap3xxx_l4_per_slaves, 515 .slaves = omap3xxx_l4_per_slaves,
520 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), 516 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -527,16 +523,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
527 &omap3xxx_l4_core__l4_wkup, 523 &omap3xxx_l4_core__l4_wkup,
528}; 524};
529 525
530/* Master interfaces on the L4_WKUP interconnect */
531static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
532};
533
534/* L4 WKUP */ 526/* L4 WKUP */
535static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 527static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
536 .name = "l4_wkup", 528 .name = "l4_wkup",
537 .class = &l4_hwmod_class, 529 .class = &l4_hwmod_class,
538 .masters = omap3xxx_l4_wkup_masters,
539 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
540 .slaves = omap3xxx_l4_wkup_slaves, 530 .slaves = omap3xxx_l4_wkup_slaves,
541 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), 531 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
542 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -1294,6 +1284,11 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1294 .slaves = omap3xxx_wd_timer2_slaves, 1284 .slaves = omap3xxx_wd_timer2_slaves,
1295 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), 1285 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1296 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287 /*
1288 * XXX: Use software supervised mode, HW supervised smartidle seems to
1289 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1290 */
1291 .flags = HWMOD_SWSUP_SIDLE,
1297}; 1292};
1298 1293
1299/* UART common */ 1294/* UART common */
@@ -1844,6 +1839,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1844 .flags = OMAP_FIREWALL_L4, 1839 .flags = OMAP_FIREWALL_L4,
1845 } 1840 }
1846 }, 1841 },
1842 .flags = OCPIF_SWSUP_IDLE,
1847 .user = OCP_USER_MPU | OCP_USER_SDMA, 1843 .user = OCP_USER_MPU | OCP_USER_SDMA,
1848}; 1844};
1849 1845
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7b72316781da..3e88dd3f8ef3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -264,11 +264,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 265};
266 266
267/* L3 target configuration and error log registers */
268static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271};
272
273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT,
278 },
279};
280
267/* mpu -> l3_main_1 */ 281/* mpu -> l3_main_1 */
268static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 282static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
269 .master = &omap44xx_mpu_hwmod, 283 .master = &omap44xx_mpu_hwmod,
270 .slave = &omap44xx_l3_main_1_hwmod, 284 .slave = &omap44xx_l3_main_1_hwmod,
271 .clk = "l3_div_ck", 285 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
272 .user = OCP_USER_MPU | OCP_USER_SDMA, 288 .user = OCP_USER_MPU | OCP_USER_SDMA,
273}; 289};
274 290
@@ -286,6 +302,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
286static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
287 .name = "l3_main_1", 303 .name = "l3_main_1",
288 .class = &omap44xx_l3_hwmod_class, 304 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
289 .slaves = omap44xx_l3_main_1_slaves, 307 .slaves = omap44xx_l3_main_1_slaves,
290 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -332,11 +350,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
332 .user = OCP_USER_MPU | OCP_USER_SDMA, 350 .user = OCP_USER_MPU | OCP_USER_SDMA,
333}; 351};
334 352
353static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 {
355 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT,
358 },
359};
360
335/* l3_main_1 -> l3_main_2 */ 361/* l3_main_1 -> l3_main_2 */
336static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 362static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
337 .master = &omap44xx_l3_main_1_hwmod, 363 .master = &omap44xx_l3_main_1_hwmod,
338 .slave = &omap44xx_l3_main_2_hwmod, 364 .slave = &omap44xx_l3_main_2_hwmod,
339 .clk = "l3_div_ck", 365 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
340 .user = OCP_USER_MPU | OCP_USER_SDMA, 368 .user = OCP_USER_MPU | OCP_USER_SDMA,
341}; 369};
342 370
@@ -377,11 +405,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
377}; 405};
378 406
379/* l3_main_3 interface data */ 407/* l3_main_3 interface data */
408static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 {
410 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT,
413 },
414};
415
380/* l3_main_1 -> l3_main_3 */ 416/* l3_main_1 -> l3_main_3 */
381static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 417static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
382 .master = &omap44xx_l3_main_1_hwmod, 418 .master = &omap44xx_l3_main_1_hwmod,
383 .slave = &omap44xx_l3_main_3_hwmod, 419 .slave = &omap44xx_l3_main_3_hwmod,
384 .clk = "l3_div_ck", 420 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
385 .user = OCP_USER_MPU | OCP_USER_SDMA, 423 .user = OCP_USER_MPU | OCP_USER_SDMA,
386}; 424};
387 425
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 000000000000..82632c24076f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,253 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29
30#include "omap_l3_noc.h"
31
32/*
33 * Interrupt Handler for L3 error detection.
34 * 1) Identify the L3 clockdomain partition to which the error belongs to.
35 * 2) Identify the slave where the error information is logged
36 * 3) Print the logged information.
37 * 4) Add dump stack to provide kernel trace.
38 *
39 * Two Types of errors :
40 * 1) Custom errors in L3 :
41 * Target like DMM/FW/EMIF generates SRESP=ERR error
42 * 2) Standard L3 error:
43 * - Unsupported CMD.
44 * L3 tries to access target while it is idle
45 * - OCP disconnect.
46 * - Address hole error:
47 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
48 * do not have connectivity, the error is logged in
49 * their default target which is DMM2.
50 *
51 * On High Secure devices, firewall errors are possible and those
52 * can be trapped as well. But the trapping is implemented as part
53 * secure software and hence need not be implemented here.
54 */
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{
57
58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j;
60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg;
62 u32 base, slave_addr, clear;
63 char *source_name;
64
65 /* Get the Type of interrupt */
66 if (irq == l3->app_irq)
67 inttype = L3_APPLICATION_ERROR;
68 else
69 inttype = L3_DEBUG_ERROR;
70
71 for (i = 0; i < L3_MODULES; i++) {
72 /*
73 * Read the regerr register of the clock domain
74 * to determine the source
75 */
76 base = (u32)l3->l3_base[i];
77 err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
78
79 /* Get the corresponding error and analyse */
80 if (err_reg) {
81 /* Identify the source from control status register */
82 for (j = 0; !(err_reg & (1 << j)); j++)
83 ;
84
85 err_src = j;
86 /* Read the stderrlog_main_source from clk domain */
87 std_err_main_addr = base + (*(l3_targ[i] + err_src));
88 std_err_main = readl(std_err_main_addr);
89
90 switch ((std_err_main & CUSTOM_ERROR)) {
91 case STANDARD_ERROR:
92 source_name =
93 l3_targ_stderrlog_main_name[i][err_src];
94
95 slave_addr = std_err_main_addr +
96 L3_SLAVE_ADDRESS_OFFSET;
97 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
98 source_name, readl(slave_addr));
99 /* clear the std error log*/
100 clear = std_err_main | CLEAR_STDERR_LOG;
101 writel(clear, std_err_main_addr);
102 break;
103
104 case CUSTOM_ERROR:
105 source_name =
106 l3_targ_stderrlog_main_name[i][err_src];
107
108 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
109 source_name);
110 /* clear the std error log*/
111 clear = std_err_main | CLEAR_STDERR_LOG;
112 writel(clear, std_err_main_addr);
113 break;
114
115 default:
116 /* Nothing to be handled here as of now */
117 break;
118 }
119 /* Error found so break the for loop */
120 break;
121 }
122 }
123 return IRQ_HANDLED;
124}
125
126static int __init omap4_l3_probe(struct platform_device *pdev)
127{
128 static struct omap4_l3 *l3;
129 struct resource *res;
130 int ret;
131 int irq;
132
133 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
134 if (!l3)
135 ret = -ENOMEM;
136
137 platform_set_drvdata(pdev, l3);
138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
139 if (!res) {
140 dev_err(&pdev->dev, "couldn't find resource 0\n");
141 ret = -ENODEV;
142 goto err1;
143 }
144
145 l3->l3_base[0] = ioremap(res->start, resource_size(res));
146 if (!(l3->l3_base[0])) {
147 dev_err(&pdev->dev, "ioremap failed\n");
148 ret = -ENOMEM;
149 goto err2;
150 }
151
152 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
153 if (!res) {
154 dev_err(&pdev->dev, "couldn't find resource 1\n");
155 ret = -ENODEV;
156 goto err3;
157 }
158
159 l3->l3_base[1] = ioremap(res->start, resource_size(res));
160 if (!(l3->l3_base[1])) {
161 dev_err(&pdev->dev, "ioremap failed\n");
162 ret = -ENOMEM;
163 goto err4;
164 }
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
167 if (!res) {
168 dev_err(&pdev->dev, "couldn't find resource 2\n");
169 ret = -ENODEV;
170 goto err5;
171 }
172
173 l3->l3_base[2] = ioremap(res->start, resource_size(res));
174 if (!(l3->l3_base[2])) {
175 dev_err(&pdev->dev, "ioremap failed\n");
176 ret = -ENOMEM;
177 goto err6;
178 }
179
180 /*
181 * Setup interrupt Handlers
182 */
183 irq = platform_get_irq(pdev, 0);
184 ret = request_irq(irq,
185 l3_interrupt_handler,
186 IRQF_DISABLED, "l3-dbg-irq", l3);
187 if (ret) {
188 pr_crit("L3: request_irq failed to register for 0x%x\n",
189 OMAP44XX_IRQ_L3_DBG);
190 goto err7;
191 }
192 l3->debug_irq = irq;
193
194 irq = platform_get_irq(pdev, 1);
195 ret = request_irq(irq,
196 l3_interrupt_handler,
197 IRQF_DISABLED, "l3-app-irq", l3);
198 if (ret) {
199 pr_crit("L3: request_irq failed to register for 0x%x\n",
200 OMAP44XX_IRQ_L3_APP);
201 goto err8;
202 }
203 l3->app_irq = irq;
204
205 goto err0;
206err8:
207err7:
208 iounmap(l3->l3_base[2]);
209err6:
210err5:
211 iounmap(l3->l3_base[1]);
212err4:
213err3:
214 iounmap(l3->l3_base[0]);
215err2:
216err1:
217 kfree(l3);
218err0:
219 return ret;
220}
221
222static int __exit omap4_l3_remove(struct platform_device *pdev)
223{
224 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
225
226 free_irq(l3->app_irq, l3);
227 free_irq(l3->debug_irq, l3);
228 iounmap(l3->l3_base[0]);
229 iounmap(l3->l3_base[1]);
230 iounmap(l3->l3_base[2]);
231 kfree(l3);
232
233 return 0;
234}
235
236static struct platform_driver omap4_l3_driver = {
237 .remove = __exit_p(omap4_l3_remove),
238 .driver = {
239 .name = "omap_l3_noc",
240 },
241};
242
243static int __init omap4_l3_init(void)
244{
245 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
246}
247postcore_initcall_sync(omap4_l3_init);
248
249static void __exit omap4_l3_exit(void)
250{
251 platform_driver_unregister(&omap4_l3_driver);
252}
253module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 000000000000..359b83348aed
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
1 /*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1
39
40u32 l3_flagmux[L3_MODULES] = {
41 0x50C,
42 0x100C,
43 0X020C
44};
45
46/*
47 * L3 Target standard Error register offsets
48 */
49u32 l3_targ_stderrlog_main_clk1[] = {
50 0x148, /* DMM1 */
51 0x248, /* DMM2 */
52 0x348, /* ABE */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55};
56
57u32 l3_targ_stderrlog_main_clk2[] = {
58 0x548, /* CORTEX M3 */
59 0x348, /* DSS */
60 0x148, /* GPMC */
61 0x448, /* ISS */
62 0x748, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/
65 0x248, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */
68 0x848, /* SL2 */
69 0x1648, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */
74 0xA48, /* L4 PER1*/
75 0xB48 /* L4 PER2*/
76};
77
78u32 l3_targ_stderrlog_main_clk3[] = {
79 0x0148 /* EMUSS */
80};
81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 {
84 "DMM1",
85 "DMM2",
86 "ABE",
87 "L4CFG",
88 "CLK2 PWR DISC",
89 },
90 {
91 "CORTEX M3" ,
92 "DSS ",
93 "GPMC ",
94 "ISS ",
95 "IVAHD ",
96 "AES1",
97 "L4 PER0",
98 "OCMRAM ",
99 "GPMC sERROR",
100 "SGX ",
101 "SL2 ",
102 "C2C ",
103 "PWR DISC CLK1",
104 "SHA1",
105 "AES2",
106 "L4 PER3",
107 "L4 PER1",
108 "L4 PER2",
109 },
110 {
111 "EMUSS",
112 },
113};
114
115u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1,
117 l3_targ_stderrlog_main_clk2,
118 l3_targ_stderrlog_main_clk3,
119};
120
121struct omap4_l3 {
122 struct device *dev;
123 struct clk *ick;
124
125 /* memory base */
126 void __iomem *l3_base[4];
127
128 int debug_irq;
129 int app_irq;
130};
131
132#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 000000000000..265bff3acb9e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,314 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include "omap_l3_smx.h"
31
32static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
33{
34 return __raw_readll(base + reg);
35}
36
37static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
38{
39 __raw_writell(value, base + reg);
40}
41
42static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
43{
44 return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
45}
46
47static inline u32 omap3_l3_decode_addr(u64 error_addr)
48{
49 return error_addr & 0xffffffff;
50}
51
52static inline unsigned omap3_l3_decode_cmd(u64 error)
53{
54 return (error & 0x07) >> L3_ERROR_LOG_CMD;
55}
56
57static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
58{
59 return (error & 0xff00) >> L3_ERROR_LOG_INITID;
60}
61
62static inline unsigned omap3_l3_decode_req_info(u64 error)
63{
64 return (error >> 32) & 0xffff;
65}
66
67static char *omap3_l3_code_string(u8 code)
68{
69 switch (code) {
70 case OMAP_L3_CODE_NOERROR:
71 return "No Error";
72 case OMAP_L3_CODE_UNSUP_CMD:
73 return "Unsupported Command";
74 case OMAP_L3_CODE_ADDR_HOLE:
75 return "Address Hole";
76 case OMAP_L3_CODE_PROTECT_VIOLATION:
77 return "Protection Violation";
78 case OMAP_L3_CODE_IN_BAND_ERR:
79 return "In-band Error";
80 case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
81 return "Request Timeout Not Accepted";
82 case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
83 return "Request Timeout, no response";
84 default:
85 return "UNKNOWN error";
86 }
87}
88
89static char *omap3_l3_initiator_string(u8 initid)
90{
91 switch (initid) {
92 case OMAP_L3_LCD:
93 return "LCD";
94 case OMAP_L3_SAD2D:
95 return "SAD2D";
96 case OMAP_L3_IA_MPU_SS_1:
97 case OMAP_L3_IA_MPU_SS_2:
98 case OMAP_L3_IA_MPU_SS_3:
99 case OMAP_L3_IA_MPU_SS_4:
100 case OMAP_L3_IA_MPU_SS_5:
101 return "MPU";
102 case OMAP_L3_IA_IVA_SS_1:
103 case OMAP_L3_IA_IVA_SS_2:
104 case OMAP_L3_IA_IVA_SS_3:
105 return "IVA_SS";
106 case OMAP_L3_IA_IVA_SS_DMA_1:
107 case OMAP_L3_IA_IVA_SS_DMA_2:
108 case OMAP_L3_IA_IVA_SS_DMA_3:
109 case OMAP_L3_IA_IVA_SS_DMA_4:
110 case OMAP_L3_IA_IVA_SS_DMA_5:
111 case OMAP_L3_IA_IVA_SS_DMA_6:
112 return "IVA_SS_DMA";
113 case OMAP_L3_IA_SGX:
114 return "SGX";
115 case OMAP_L3_IA_CAM_1:
116 case OMAP_L3_IA_CAM_2:
117 case OMAP_L3_IA_CAM_3:
118 return "CAM";
119 case OMAP_L3_IA_DAP:
120 return "DAP";
121 case OMAP_L3_SDMA_WR_1:
122 case OMAP_L3_SDMA_WR_2:
123 return "SDMA_WR";
124 case OMAP_L3_SDMA_RD_1:
125 case OMAP_L3_SDMA_RD_2:
126 case OMAP_L3_SDMA_RD_3:
127 case OMAP_L3_SDMA_RD_4:
128 return "SDMA_RD";
129 case OMAP_L3_USBOTG:
130 return "USB_OTG";
131 case OMAP_L3_USBHOST:
132 return "USB_HOST";
133 default:
134 return "UNKNOWN Initiator";
135 }
136}
137
138/**
139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 *
141 * @base: register block base address
142 * @error: L3_ERROR_LOG register of our block
143 *
144 * Called in hard-irq context. Caller should take care of locking
145 *
146 * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
147 * Analysis Sequence, we are following that sequence here, please
148 * refer to that Figure for more information on the subject.
149 */
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr)
152{
153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr);
157
158 WARN(true, "%s Error seen by %s %s at address %x\n",
159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "",
162 address);
163
164 return IRQ_HANDLED;
165}
166
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{
169 struct omap3_l3 *l3 = _l3;
170
171 u64 status, clear;
172 u64 error;
173 u64 error_addr;
174 u64 err_source = 0;
175 void __iomem *base;
176 int int_type;
177
178 irqreturn_t ret = IRQ_NONE;
179
180 if (irq == l3->app_irq)
181 int_type = L3_APPLICATION_ERROR;
182 else
183 int_type = L3_DEBUG_ERROR;
184
185 if (!int_type) {
186 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
187 /*
188 * if we have a timeout error, there's nothing we can
189 * do besides rebooting the board. So let's BUG on any
190 * of such errors and handle the others. timeout error
191 * is severe and not expected to occur.
192 */
193 BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
194 } else {
195 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
196 /* No timeout error for debug sources */
197 }
198
199 base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
200
201 /* identify the error source */
202 for (err_source = 0; !(status & (1 << err_source)); err_source++)
203 ;
204 error = omap3_l3_readll(base, L3_ERROR_LOG);
205
206 if (error) {
207 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
208
209 ret |= omap3_l3_block_irq(l3, error, error_addr);
210 }
211
212 /* Clear the status register */
213 clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
214 (L3_AGENT_STATUS_CLEAR_TA));
215
216 omap3_l3_writell(base, L3_AGENT_STATUS, clear);
217
218 /* clear the error log register */
219 omap3_l3_writell(base, L3_ERROR_LOG, error);
220
221 return ret;
222}
223
224static int __init omap3_l3_probe(struct platform_device *pdev)
225{
226 struct omap3_l3 *l3;
227 struct resource *res;
228 int ret;
229 int irq;
230
231 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
232 if (!l3) {
233 ret = -ENOMEM;
234 goto err0;
235 }
236
237 platform_set_drvdata(pdev, l3);
238
239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (!res) {
241 dev_err(&pdev->dev, "couldn't find resource\n");
242 ret = -ENODEV;
243 goto err1;
244 }
245 l3->rt = ioremap(res->start, resource_size(res));
246 if (!(l3->rt)) {
247 dev_err(&pdev->dev, "ioremap failed\n");
248 ret = -ENOMEM;
249 goto err2;
250 }
251
252 irq = platform_get_irq(pdev, 0);
253 ret = request_irq(irq, omap3_l3_app_irq,
254 IRQF_DISABLED | IRQF_TRIGGER_RISING,
255 "l3-debug-irq", l3);
256 if (ret) {
257 dev_err(&pdev->dev, "couldn't request debug irq\n");
258 goto err3;
259 }
260 l3->debug_irq = irq;
261
262 irq = platform_get_irq(pdev, 1);
263 ret = request_irq(irq, omap3_l3_app_irq,
264 IRQF_DISABLED | IRQF_TRIGGER_RISING,
265 "l3-app-irq", l3);
266
267 if (ret) {
268 dev_err(&pdev->dev, "couldn't request app irq\n");
269 goto err4;
270 }
271
272 l3->app_irq = irq;
273 goto err0;
274
275err4:
276err3:
277 iounmap(l3->rt);
278err2:
279err1:
280 kfree(l3);
281err0:
282 return ret;
283}
284
285static int __exit omap3_l3_remove(struct platform_device *pdev)
286{
287 struct omap3_l3 *l3 = platform_get_drvdata(pdev);
288
289 free_irq(l3->app_irq, l3);
290 free_irq(l3->debug_irq, l3);
291 iounmap(l3->rt);
292 kfree(l3);
293
294 return 0;
295}
296
297static struct platform_driver omap3_l3_driver = {
298 .remove = __exit_p(omap3_l3_remove),
299 .driver = {
300 .name = "omap_l3_smx",
301 },
302};
303
304static int __init omap3_l3_init(void)
305{
306 return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
307}
308postcore_initcall_sync(omap3_l3_init);
309
310static void __exit omap3_l3_exit(void)
311{
312 platform_driver_unregister(&omap3_l3_driver);
313}
314module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 000000000000..ba2ed9a850cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26
27/* Register definitions. All 64-bit wide */
28#define L3_COMPONENT 0x000
29#define L3_CORE 0x018
30#define L3_AGENT_CONTROL 0x020
31#define L3_AGENT_STATUS 0x028
32#define L3_ERROR_LOG 0x058
33
34#define L3_ERROR_LOG_MULTI (1 << 31)
35#define L3_ERROR_LOG_SECONDARY (1 << 30)
36
37#define L3_ERROR_LOG_ADDR 0x060
38
39/* Register definitions for Sideband Interconnect */
40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510
42
43const u64 shift = 1;
44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
47#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48#define L3_STATUS_0_IVAIA_BRST (shift << 6)
49#define L3_STATUS_0_IVAIA_RSP (shift << 7)
50#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51#define L3_STATUS_0_SGXIA_BRST (shift << 9)
52#define L3_STATUS_0_SGXIA_RSP (shift << 10)
53#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
54#define L3_STATUS_0_CAMIA_BRST (shift << 12)
55#define L3_STATUS_0_CAMIA_RSP (shift << 13)
56#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
57#define L3_STATUS_0_DISPIA_BRST (shift << 15)
58#define L3_STATUS_0_DISPIA_RSP (shift << 16)
59#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
60#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
61#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
62#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
63#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
64#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
65#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
66#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
67#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
68#define L3_STATUS_0_SMSTA_REQ (shift << 48)
69#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
70#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
71#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
72#define L3_STATUS_0_IVATA_REQ (shift << 54)
73#define L3_STATUS_0_SGXTA_REQ (shift << 55)
74#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
75#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
76#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
77#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ)
108
109#define L3_SI_FLAG_STATUS_1 0x530
110
111#define L3_STATUS_1_MPU_DATAIA (1 << 0)
112#define L3_STATUS_1_DAPIA0 (1 << 3)
113#define L3_STATUS_1_DAPIA1 (1 << 4)
114#define L3_STATUS_1_IVAIA (1 << 6)
115
116#define L3_PM_ERROR_LOG 0x020
117#define L3_PM_CONTROL 0x028
118#define L3_PM_ERROR_CLEAR_SINGLE 0x030
119#define L3_PM_ERROR_CLEAR_MULTI 0x038
120#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
121#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
122#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
123#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
124
125/* L3 error log bit fields. Common for IA and TA */
126#define L3_ERROR_LOG_CODE 24
127#define L3_ERROR_LOG_INITID 8
128#define L3_ERROR_LOG_CMD 0
129
130/* L3 agent status bit fields. */
131#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
132#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
133
134#define OMAP34xx_IRQ_L3_APP 10
135#define L3_APPLICATION_ERROR 0x0
136#define L3_DEBUG_ERROR 0x1
137
138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
156 OMAP_L3_IA_IVA_SS_DMA_3 = 17,
157 OMAP_L3_IA_IVA_SS_DMA_4 = 16,
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1,
180};
181
182enum omap3_l3_code {
183 OMAP_L3_CODE_NOERROR = 0,
184 OMAP_L3_CODE_UNSUP_CMD = 1,
185 OMAP_L3_CODE_ADDR_HOLE = 2,
186 OMAP_L3_CODE_PROTECT_VIOLATION = 3,
187 OMAP_L3_CODE_IN_BAND_ERR = 4,
188 /* codes 5 and 6 are reserved */
189 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
190 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
191 /* codes 9 - 15 are also reserved */
192};
193
194struct omap3_l3 {
195 struct device *dev;
196 struct clk *ick;
197
198 /* memory base*/
199 void __iomem *rt;
200
201 int debug_irq;
202 int app_irq;
203
204 /* true when and inband functional error occurs */
205 unsigned inband:1;
206};
207
208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = {
210 /* MPU IA */
211 0x1400,
212 0x1400,
213 0x1400,
214 /* RESERVED */
215 0,
216 0,
217 0,
218 /* IVA 2.2 IA */
219 0x1800,
220 0x1800,
221 0x1800,
222 /* SGX IA */
223 0x1c00,
224 0x1c00,
225 /* RESERVED */
226 0,
227 /* CAMERA IA */
228 0x5800,
229 0x5800,
230 0x5800,
231 /* DISPLAY IA */
232 0x5400,
233 0x5400,
234 /* RESERVED */
235 0,
236 /*SDMA RD IA */
237 0x4c00,
238 0x4c00,
239 /* RESERVED */
240 0,
241 /* SDMA WR IA */
242 0x5000,
243 0x5000,
244 /* RESERVED */
245 0,
246 /* USB OTG IA */
247 0x4400,
248 0x4400,
249 0x4400,
250 /* USB HOST IA */
251 0x4000,
252 0x4000,
253 /* RESERVED */
254 0,
255 0,
256 0,
257 0,
258 /* SAD2D IA */
259 0x3000,
260 0x3000,
261 0x3000,
262 /* RESERVED */
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 /* SMA TA */
276 0x2000,
277 /* GPMC TA */
278 0x2400,
279 /* OCM RAM TA */
280 0x2800,
281 /* OCM ROM TA */
282 0x2C00,
283 /* L4 CORE TA */
284 0x6800,
285 /* L4 PER TA */
286 0x6c00,
287 /* IVA 2.2 TA */
288 0x6000,
289 /* SGX TA */
290 0x6400,
291 /* L4 EMU TA */
292 0x7000,
293 /* GPMC TA */
294 0x2400,
295 /* L4 CORE TA */
296 0x6800,
297 /* L4 PER TA */
298 0x6c00,
299 /* L4 EMU TA */
300 0x7000,
301 /* MAD2D TA */
302 0x3400,
303 /* RESERVED */
304 0,
305 0,
306};
307
308unsigned int __iomem omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */
310 0x1400,
311 /* RESERVED */
312 0,
313 0,
314 /* DAP IA */
315 0x5c00,
316 0x5c00,
317 /* RESERVED */
318 0,
319 /* IVA 2.2 IA */
320 0x1800,
321 /* REST RESERVED */
322};
323
324u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases,
326 omap3_l3_debug_bases,
327};
328
329/*
330 * REVISIT define __raw_readll/__raw_writell here, but move them to
331 * <asm/io.h> at some point
332 */
333#define __raw_writell(v, a) (__chk_io_ptr(a), \
334 *(volatile u64 __force *)(a) = (v))
335#define __raw_readll(a) (__chk_io_ptr(a), \
336 *(volatile u64 __force *)(a))
337
338#endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c71989..7bb64d8121a7 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -124,7 +124,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
124 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { 124 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
125 sleep_switch = LOWPOWERSTATE_SWITCH; 125 sleep_switch = LOWPOWERSTATE_SWITCH;
126 } else { 126 } else {
127 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); 127 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
128 pwrdm_wait_transition(pwrdm); 128 pwrdm_wait_transition(pwrdm);
129 sleep_switch = FORCEWAKEUP_SWITCH; 129 sleep_switch = FORCEWAKEUP_SWITCH;
130 } 130 }
@@ -140,9 +140,9 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
140 switch (sleep_switch) { 140 switch (sleep_switch) {
141 case FORCEWAKEUP_SWITCH: 141 case FORCEWAKEUP_SWITCH:
142 if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) 142 if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
143 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 143 clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
144 else 144 else
145 omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]); 145 clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
146 break; 146 break;
147 case LOWPOWERSTATE_SWITCH: 147 case LOWPOWERSTATE_SWITCH:
148 pwrdm_set_lowpwrstchange(pwrdm); 148 pwrdm_set_lowpwrstchange(pwrdm);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 97feb3ab6a69..96907da1910a 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -367,10 +367,10 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
367 clkdm_clear_all_sleepdeps(clkdm); 367 clkdm_clear_all_sleepdeps(clkdm);
368 368
369 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 369 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
370 omap2_clkdm_allow_idle(clkdm); 370 clkdm_allow_idle(clkdm);
371 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 371 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
372 atomic_read(&clkdm->usecount) == 0) 372 atomic_read(&clkdm->usecount) == 0)
373 omap2_clkdm_sleep(clkdm); 373 clkdm_sleep(clkdm);
374 return 0; 374 return 0;
375} 375}
376 376
@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
379 int i, num_mem_banks; 379 int i, num_mem_banks;
380 struct powerdomain *pwrdm; 380 struct powerdomain *pwrdm;
381 381
382 /* Enable autoidle */ 382 /*
383 * Enable autoidle
384 * XXX This should be handled by hwmod code or PRCM init code
385 */
383 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, 386 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
384 OMAP2_PRCM_SYSCONFIG_OFFSET); 387 OMAP2_PRCM_SYSCONFIG_OFFSET);
385 388
@@ -405,11 +408,11 @@ static void __init prcm_setup_regs(void)
405 408
406 pwrdm = clkdm_get_pwrdm(dsp_clkdm); 409 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
407 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); 410 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
408 omap2_clkdm_sleep(dsp_clkdm); 411 clkdm_sleep(dsp_clkdm);
409 412
410 pwrdm = clkdm_get_pwrdm(gfx_clkdm); 413 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
411 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); 414 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
412 omap2_clkdm_sleep(gfx_clkdm); 415 clkdm_sleep(gfx_clkdm);
413 416
414 /* 417 /*
415 * Clear clockdomain wakeup dependencies and enable 418 * Clear clockdomain wakeup dependencies and enable
@@ -418,70 +421,6 @@ static void __init prcm_setup_regs(void)
418 clkdm_for_each(clkdms_setup, NULL); 421 clkdm_for_each(clkdms_setup, NULL);
419 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 422 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
420 423
421 /* Enable clock autoidle for all domains */
422 omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
423 OMAP24XX_AUTO_MAILBOXES_MASK |
424 OMAP24XX_AUTO_WDT4_MASK |
425 OMAP2420_AUTO_WDT3_MASK |
426 OMAP24XX_AUTO_MSPRO_MASK |
427 OMAP2420_AUTO_MMC_MASK |
428 OMAP24XX_AUTO_FAC_MASK |
429 OMAP2420_AUTO_EAC_MASK |
430 OMAP24XX_AUTO_HDQ_MASK |
431 OMAP24XX_AUTO_UART2_MASK |
432 OMAP24XX_AUTO_UART1_MASK |
433 OMAP24XX_AUTO_I2C2_MASK |
434 OMAP24XX_AUTO_I2C1_MASK |
435 OMAP24XX_AUTO_MCSPI2_MASK |
436 OMAP24XX_AUTO_MCSPI1_MASK |
437 OMAP24XX_AUTO_MCBSP2_MASK |
438 OMAP24XX_AUTO_MCBSP1_MASK |
439 OMAP24XX_AUTO_GPT12_MASK |
440 OMAP24XX_AUTO_GPT11_MASK |
441 OMAP24XX_AUTO_GPT10_MASK |
442 OMAP24XX_AUTO_GPT9_MASK |
443 OMAP24XX_AUTO_GPT8_MASK |
444 OMAP24XX_AUTO_GPT7_MASK |
445 OMAP24XX_AUTO_GPT6_MASK |
446 OMAP24XX_AUTO_GPT5_MASK |
447 OMAP24XX_AUTO_GPT4_MASK |
448 OMAP24XX_AUTO_GPT3_MASK |
449 OMAP24XX_AUTO_GPT2_MASK |
450 OMAP2420_AUTO_VLYNQ_MASK |
451 OMAP24XX_AUTO_DSS_MASK,
452 CORE_MOD, CM_AUTOIDLE1);
453 omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
454 OMAP24XX_AUTO_SSI_MASK |
455 OMAP24XX_AUTO_USB_MASK,
456 CORE_MOD, CM_AUTOIDLE2);
457 omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
458 OMAP24XX_AUTO_GPMC_MASK |
459 OMAP24XX_AUTO_SDMA_MASK,
460 CORE_MOD, CM_AUTOIDLE3);
461 omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
462 OMAP24XX_AUTO_AES_MASK |
463 OMAP24XX_AUTO_RNG_MASK |
464 OMAP24XX_AUTO_SHA_MASK |
465 OMAP24XX_AUTO_DES_MASK,
466 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
467
468 omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
469 CM_AUTOIDLE);
470
471 /* Put DPLL and both APLLs into autoidle mode */
472 omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
473 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
474 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
475 PLL_MOD, CM_AUTOIDLE);
476
477 omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
478 OMAP24XX_AUTO_WDT1_MASK |
479 OMAP24XX_AUTO_MPU_WDT_MASK |
480 OMAP24XX_AUTO_GPIOS_MASK |
481 OMAP24XX_AUTO_32KSYNC_MASK |
482 OMAP24XX_AUTO_GPT1_MASK,
483 WKUP_MOD, CM_AUTOIDLE);
484
485 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 424 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
486 * stabilisation */ 425 * stabilisation */
487 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 426 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4b085d..3d6a00e07a5b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -496,7 +496,7 @@ console_still_active:
496 496
497 pwrdm_post_transition(); 497 pwrdm_post_transition();
498 498
499 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); 499 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
500} 500}
501 501
502int omap3_can_sleep(void) 502int omap3_can_sleep(void)
@@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void)
688 688
689static void __init prcm_setup_regs(void) 689static void __init prcm_setup_regs(void)
690{ 690{
691 u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
692 OMAP3630_AUTO_UART4_MASK : 0;
693 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? 691 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_EN_UART4_MASK : 0; 692 OMAP3630_EN_UART4_MASK : 0;
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 693 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0; 694 OMAP3630_GRPSEL_UART4_MASK : 0;
697 695
698
699 /* XXX Reset all wkdeps. This should be done when initializing 696 /* XXX Reset all wkdeps. This should be done when initializing
700 * powerdomains */ 697 * powerdomains */
701 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); 698 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -710,127 +707,10 @@ static void __init prcm_setup_regs(void)
710 } else 707 } else
711 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); 708 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
712 709
713 /* 710 /* XXX This should be handled by hwmod code or SCM init code */
714 * Enable interface clock autoidle for all modules.
715 * Note that in the long run this should be done by clockfw
716 */
717 omap2_cm_write_mod_reg(
718 OMAP3430_AUTO_MODEM_MASK |
719 OMAP3430ES2_AUTO_MMC3_MASK |
720 OMAP3430ES2_AUTO_ICR_MASK |
721 OMAP3430_AUTO_AES2_MASK |
722 OMAP3430_AUTO_SHA12_MASK |
723 OMAP3430_AUTO_DES2_MASK |
724 OMAP3430_AUTO_MMC2_MASK |
725 OMAP3430_AUTO_MMC1_MASK |
726 OMAP3430_AUTO_MSPRO_MASK |
727 OMAP3430_AUTO_HDQ_MASK |
728 OMAP3430_AUTO_MCSPI4_MASK |
729 OMAP3430_AUTO_MCSPI3_MASK |
730 OMAP3430_AUTO_MCSPI2_MASK |
731 OMAP3430_AUTO_MCSPI1_MASK |
732 OMAP3430_AUTO_I2C3_MASK |
733 OMAP3430_AUTO_I2C2_MASK |
734 OMAP3430_AUTO_I2C1_MASK |
735 OMAP3430_AUTO_UART2_MASK |
736 OMAP3430_AUTO_UART1_MASK |
737 OMAP3430_AUTO_GPT11_MASK |
738 OMAP3430_AUTO_GPT10_MASK |
739 OMAP3430_AUTO_MCBSP5_MASK |
740 OMAP3430_AUTO_MCBSP1_MASK |
741 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
742 OMAP3430_AUTO_MAILBOXES_MASK |
743 OMAP3430_AUTO_OMAPCTRL_MASK |
744 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
745 OMAP3430_AUTO_HSOTGUSB_MASK |
746 OMAP3430_AUTO_SAD2D_MASK |
747 OMAP3430_AUTO_SSI_MASK,
748 CORE_MOD, CM_AUTOIDLE1);
749
750 omap2_cm_write_mod_reg(
751 OMAP3430_AUTO_PKA_MASK |
752 OMAP3430_AUTO_AES1_MASK |
753 OMAP3430_AUTO_RNG_MASK |
754 OMAP3430_AUTO_SHA11_MASK |
755 OMAP3430_AUTO_DES1_MASK,
756 CORE_MOD, CM_AUTOIDLE2);
757
758 if (omap_rev() > OMAP3430_REV_ES1_0) {
759 omap2_cm_write_mod_reg(
760 OMAP3430_AUTO_MAD2D_MASK |
761 OMAP3430ES2_AUTO_USBTLL_MASK,
762 CORE_MOD, CM_AUTOIDLE3);
763 }
764
765 omap2_cm_write_mod_reg(
766 OMAP3430_AUTO_WDT2_MASK |
767 OMAP3430_AUTO_WDT1_MASK |
768 OMAP3430_AUTO_GPIO1_MASK |
769 OMAP3430_AUTO_32KSYNC_MASK |
770 OMAP3430_AUTO_GPT12_MASK |
771 OMAP3430_AUTO_GPT1_MASK,
772 WKUP_MOD, CM_AUTOIDLE);
773
774 omap2_cm_write_mod_reg(
775 OMAP3430_AUTO_DSS_MASK,
776 OMAP3430_DSS_MOD,
777 CM_AUTOIDLE);
778
779 omap2_cm_write_mod_reg(
780 OMAP3430_AUTO_CAM_MASK,
781 OMAP3430_CAM_MOD,
782 CM_AUTOIDLE);
783
784 omap2_cm_write_mod_reg(
785 omap3630_auto_uart4_mask |
786 OMAP3430_AUTO_GPIO6_MASK |
787 OMAP3430_AUTO_GPIO5_MASK |
788 OMAP3430_AUTO_GPIO4_MASK |
789 OMAP3430_AUTO_GPIO3_MASK |
790 OMAP3430_AUTO_GPIO2_MASK |
791 OMAP3430_AUTO_WDT3_MASK |
792 OMAP3430_AUTO_UART3_MASK |
793 OMAP3430_AUTO_GPT9_MASK |
794 OMAP3430_AUTO_GPT8_MASK |
795 OMAP3430_AUTO_GPT7_MASK |
796 OMAP3430_AUTO_GPT6_MASK |
797 OMAP3430_AUTO_GPT5_MASK |
798 OMAP3430_AUTO_GPT4_MASK |
799 OMAP3430_AUTO_GPT3_MASK |
800 OMAP3430_AUTO_GPT2_MASK |
801 OMAP3430_AUTO_MCBSP4_MASK |
802 OMAP3430_AUTO_MCBSP3_MASK |
803 OMAP3430_AUTO_MCBSP2_MASK,
804 OMAP3430_PER_MOD,
805 CM_AUTOIDLE);
806
807 if (omap_rev() > OMAP3430_REV_ES1_0) {
808 omap2_cm_write_mod_reg(
809 OMAP3430ES2_AUTO_USBHOST_MASK,
810 OMAP3430ES2_USBHOST_MOD,
811 CM_AUTOIDLE);
812 }
813
814 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 711 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
815 712
816 /* 713 /*
817 * Set all plls to autoidle. This is needed until autoidle is
818 * enabled by clockfw
819 */
820 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
821 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
822 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
823 MPU_MOD,
824 CM_AUTOIDLE2);
825 omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
826 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
827 PLL_MOD,
828 CM_AUTOIDLE);
829 omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
830 PLL_MOD,
831 CM_AUTOIDLE2);
832
833 /*
834 * Enable control of expternal oscillator through 714 * Enable control of expternal oscillator through
835 * sys_clkreq. In the long run clock framework should 715 * sys_clkreq. In the long run clock framework should
836 * take care of this. 716 * take care of this.
@@ -990,10 +870,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
990static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 870static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
991{ 871{
992 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 872 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
993 omap2_clkdm_allow_idle(clkdm); 873 clkdm_allow_idle(clkdm);
994 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 874 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
995 atomic_read(&clkdm->usecount) == 0) 875 atomic_read(&clkdm->usecount) == 0)
996 omap2_clkdm_sleep(clkdm); 876 clkdm_sleep(clkdm);
997 return 0; 877 return 0;
998} 878}
999 879
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index eaed0df16699..a11be81997c5 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,7 +2,7 @@
2 * OMAP powerdomain control 2 * OMAP powerdomain control
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> 8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -938,3 +938,44 @@ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
938 938
939 return count; 939 return count;
940} 940}
941
942/**
943 * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
944 * @pwrdm: struct powerdomain *
945 *
946 * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
947 * can lose either memory or logic context or if @pwrdm is invalid, or
948 * returns 0 otherwise. This function is not concerned with how the
949 * powerdomain registers are programmed (i.e., to go off or not); it's
950 * concerned with whether it's ever possible for this powerdomain to
951 * go off while some other part of the chip is active. This function
952 * assumes that every powerdomain can go to either ON or INACTIVE.
953 */
954bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
955{
956 int i;
957
958 if (IS_ERR_OR_NULL(pwrdm)) {
959 pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
960 __func__);
961 return 1;
962 }
963
964 if (pwrdm->pwrsts & PWRSTS_OFF)
965 return 1;
966
967 if (pwrdm->pwrsts & PWRSTS_RET) {
968 if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
969 return 1;
970
971 for (i = 0; i < pwrdm->banks; i++)
972 if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
973 return 1;
974 }
975
976 for (i = 0; i < pwrdm->banks; i++)
977 if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
978 return 1;
979
980 return 0;
981}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index c66431edfeb7..027f40bd235d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -2,7 +2,7 @@
2 * OMAP2/3/4 powerdomain control 2 * OMAP2/3/4 powerdomain control
3 * 3 *
4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
8 * 8 *
@@ -34,17 +34,14 @@
34 34
35/* Powerdomain allowable state bitfields */ 35/* Powerdomain allowable state bitfields */
36#define PWRSTS_ON (1 << PWRDM_POWER_ON) 36#define PWRSTS_ON (1 << PWRDM_POWER_ON)
37#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
38#define PWRSTS_RET (1 << PWRDM_POWER_RET)
37#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) 39#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
38#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
39 (1 << PWRDM_POWER_ON))
40 40
41#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ 41#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
42 (1 << PWRDM_POWER_RET)) 42#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
43 43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ 44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
45 (1 << PWRDM_POWER_ON))
46
47#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
48 45
49 46
50/* Powerdomain flags */ 47/* Powerdomain flags */
@@ -165,7 +162,6 @@ struct pwrdm_ops {
165 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); 162 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
166}; 163};
167 164
168void pwrdm_fw_init(void);
169void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); 165void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
170 166
171struct powerdomain *pwrdm_lookup(const char *name); 167struct powerdomain *pwrdm_lookup(const char *name);
@@ -212,6 +208,7 @@ int pwrdm_pre_transition(void);
212int pwrdm_post_transition(void); 208int pwrdm_post_transition(void);
213int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 209int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
214u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 210u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
211bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
215 212
216extern void omap2xxx_powerdomains_init(void); 213extern void omap2xxx_powerdomains_init(void);
217extern void omap3xxx_powerdomains_init(void); 214extern void omap3xxx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 5b4dd971320a..4210c3399769 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP2/3 common powerdomain definitions 2 * OMAP2/3 common powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -62,13 +62,13 @@ struct powerdomain gfx_omap2_pwrdm = {
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | 62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
63 CHIP_IS_OMAP3430ES1), 63 CHIP_IS_OMAP3430ES1),
64 .pwrsts = PWRSTS_OFF_RET_ON, 64 .pwrsts = PWRSTS_OFF_RET_ON,
65 .pwrsts_logic_ret = PWRDM_POWER_RET, 65 .pwrsts_logic_ret = PWRSTS_RET,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 68 [0] = PWRSTS_RET, /* MEMRETSTATE */
69 }, 69 },
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 71 [0] = PWRSTS_ON, /* MEMONSTATE */
72 }, 72 },
73}; 73};
74 74
@@ -76,4 +76,5 @@ struct powerdomain wkup_omap2_pwrdm = {
76 .name = "wkup_pwrdm", 76 .name = "wkup_pwrdm",
77 .prcm_offs = WKUP_MOD, 77 .prcm_offs = WKUP_MOD,
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), 78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
79 .pwrsts = PWRSTS_ON,
79}; 80};
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 78739e10f5b9..cc389fb2005d 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP2XXX powerdomain definitions 2 * OMAP2XXX powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -30,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
30 .prcm_offs = OMAP24XX_DSP_MOD, 30 .prcm_offs = OMAP24XX_DSP_MOD,
31 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 31 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
32 .pwrsts = PWRSTS_OFF_RET_ON, 32 .pwrsts = PWRSTS_OFF_RET_ON,
33 .pwrsts_logic_ret = PWRDM_POWER_RET, 33 .pwrsts_logic_ret = PWRSTS_RET,
34 .banks = 1, 34 .banks = 1,
35 .pwrsts_mem_ret = { 35 .pwrsts_mem_ret = {
36 [0] = PWRDM_POWER_RET, 36 [0] = PWRSTS_RET,
37 }, 37 },
38 .pwrsts_mem_on = { 38 .pwrsts_mem_on = {
39 [0] = PWRDM_POWER_ON, 39 [0] = PWRSTS_ON,
40 }, 40 },
41}; 41};
42 42
@@ -48,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
48 .pwrsts_logic_ret = PWRSTS_OFF_RET, 48 .pwrsts_logic_ret = PWRSTS_OFF_RET,
49 .banks = 1, 49 .banks = 1,
50 .pwrsts_mem_ret = { 50 .pwrsts_mem_ret = {
51 [0] = PWRDM_POWER_RET, 51 [0] = PWRSTS_RET,
52 }, 52 },
53 .pwrsts_mem_on = { 53 .pwrsts_mem_on = {
54 [0] = PWRDM_POWER_ON, 54 [0] = PWRSTS_ON,
55 }, 55 },
56}; 56};
57 57
@@ -87,13 +87,13 @@ static struct powerdomain mdm_pwrdm = {
87 .prcm_offs = OMAP2430_MDM_MOD, 87 .prcm_offs = OMAP2430_MDM_MOD,
88 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 88 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
89 .pwrsts = PWRSTS_OFF_RET_ON, 89 .pwrsts = PWRSTS_OFF_RET_ON,
90 .pwrsts_logic_ret = PWRDM_POWER_RET, 90 .pwrsts_logic_ret = PWRSTS_RET,
91 .banks = 1, 91 .banks = 1,
92 .pwrsts_mem_ret = { 92 .pwrsts_mem_ret = {
93 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 93 [0] = PWRSTS_RET, /* MEMRETSTATE */
94 }, 94 },
95 .pwrsts_mem_on = { 95 .pwrsts_mem_on = {
96 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 96 [0] = PWRSTS_ON, /* MEMONSTATE */
97 }, 97 },
98}; 98};
99 99
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e1bec562625b..9c9c113788b9 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP3 powerdomain definitions 2 * OMAP3 powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -47,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
47 [3] = PWRSTS_OFF_RET, 47 [3] = PWRSTS_OFF_RET,
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, 50 [0] = PWRSTS_ON,
51 [1] = PWRDM_POWER_ON, 51 [1] = PWRSTS_ON,
52 [2] = PWRSTS_OFF_ON, 52 [2] = PWRSTS_OFF_ON,
53 [3] = PWRDM_POWER_ON, 53 [3] = PWRSTS_ON,
54 }, 54 },
55}; 55};
56 56
@@ -128,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
129 .prcm_offs = OMAP3430_DSS_MOD, 129 .prcm_offs = OMAP3430_DSS_MOD,
130 .pwrsts = PWRSTS_OFF_RET_ON, 130 .pwrsts = PWRSTS_OFF_RET_ON,
131 .pwrsts_logic_ret = PWRDM_POWER_RET, 131 .pwrsts_logic_ret = PWRSTS_RET,
132 .banks = 1, 132 .banks = 1,
133 .pwrsts_mem_ret = { 133 .pwrsts_mem_ret = {
134 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 134 [0] = PWRSTS_RET, /* MEMRETSTATE */
135 }, 135 },
136 .pwrsts_mem_on = { 136 .pwrsts_mem_on = {
137 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 137 [0] = PWRSTS_ON, /* MEMONSTATE */
138 }, 138 },
139}; 139};
140 140
@@ -149,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
149 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 149 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
150 /* XXX This is accurate for 3430 SGX, but what about GFX? */ 150 /* XXX This is accurate for 3430 SGX, but what about GFX? */
151 .pwrsts = PWRSTS_OFF_ON, 151 .pwrsts = PWRSTS_OFF_ON,
152 .pwrsts_logic_ret = PWRDM_POWER_RET, 152 .pwrsts_logic_ret = PWRSTS_RET,
153 .banks = 1, 153 .banks = 1,
154 .pwrsts_mem_ret = { 154 .pwrsts_mem_ret = {
155 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 155 [0] = PWRSTS_RET, /* MEMRETSTATE */
156 }, 156 },
157 .pwrsts_mem_on = { 157 .pwrsts_mem_on = {
158 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 158 [0] = PWRSTS_ON, /* MEMONSTATE */
159 }, 159 },
160}; 160};
161 161
@@ -164,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
165 .prcm_offs = OMAP3430_CAM_MOD, 165 .prcm_offs = OMAP3430_CAM_MOD,
166 .pwrsts = PWRSTS_OFF_RET_ON, 166 .pwrsts = PWRSTS_OFF_RET_ON,
167 .pwrsts_logic_ret = PWRDM_POWER_RET, 167 .pwrsts_logic_ret = PWRSTS_RET,
168 .banks = 1, 168 .banks = 1,
169 .pwrsts_mem_ret = { 169 .pwrsts_mem_ret = {
170 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 170 [0] = PWRSTS_RET, /* MEMRETSTATE */
171 }, 171 },
172 .pwrsts_mem_on = { 172 .pwrsts_mem_on = {
173 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 173 [0] = PWRSTS_ON, /* MEMONSTATE */
174 }, 174 },
175}; 175};
176 176
@@ -182,10 +182,10 @@ static struct powerdomain per_pwrdm = {
182 .pwrsts_logic_ret = PWRSTS_OFF_RET, 182 .pwrsts_logic_ret = PWRSTS_OFF_RET,
183 .banks = 1, 183 .banks = 1,
184 .pwrsts_mem_ret = { 184 .pwrsts_mem_ret = {
185 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 185 [0] = PWRSTS_RET, /* MEMRETSTATE */
186 }, 186 },
187 .pwrsts_mem_on = { 187 .pwrsts_mem_on = {
188 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 188 [0] = PWRSTS_ON, /* MEMONSTATE */
189 }, 189 },
190}; 190};
191 191
@@ -200,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
200 .prcm_offs = OMAP3430_NEON_MOD, 200 .prcm_offs = OMAP3430_NEON_MOD,
201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
202 .pwrsts = PWRSTS_OFF_RET_ON, 202 .pwrsts = PWRSTS_OFF_RET_ON,
203 .pwrsts_logic_ret = PWRDM_POWER_RET, 203 .pwrsts_logic_ret = PWRSTS_RET,
204}; 204};
205 205
206static struct powerdomain usbhost_pwrdm = { 206static struct powerdomain usbhost_pwrdm = {
@@ -208,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
208 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 208 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
209 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 209 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
210 .pwrsts = PWRSTS_OFF_RET_ON, 210 .pwrsts = PWRSTS_OFF_RET_ON,
211 .pwrsts_logic_ret = PWRDM_POWER_RET, 211 .pwrsts_logic_ret = PWRSTS_RET,
212 /* 212 /*
213 * REVISIT: Enabling usb host save and restore mechanism seems to 213 * REVISIT: Enabling usb host save and restore mechanism seems to
214 * leave the usb host domain permanently in ACTIVE mode after 214 * leave the usb host domain permanently in ACTIVE mode after
@@ -218,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
218 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ 218 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
219 .banks = 1, 219 .banks = 1,
220 .pwrsts_mem_ret = { 220 .pwrsts_mem_ret = {
221 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 221 [0] = PWRSTS_RET, /* MEMRETSTATE */
222 }, 222 },
223 .pwrsts_mem_on = { 223 .pwrsts_mem_on = {
224 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 224 [0] = PWRSTS_ON, /* MEMONSTATE */
225 }, 225 },
226}; 226};
227 227
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 26d7641076d7..c4222c7036a5 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -2,7 +2,7 @@
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
@@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
43 [0] = PWRDM_POWER_OFF, /* core_nret_bank */ 43 [0] = PWRSTS_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 44 [1] = PWRSTS_OFF_RET, /* core_ocmram */
45 [2] = PWRDM_POWER_RET, /* core_other_bank */ 45 [2] = PWRSTS_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ 46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */ 47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, /* core_nret_bank */ 50 [0] = PWRSTS_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 51 [1] = PWRSTS_OFF_RET, /* core_ocmram */
52 [2] = PWRDM_POWER_ON, /* core_other_bank */ 52 [2] = PWRSTS_ON, /* core_other_bank */
53 [3] = PWRDM_POWER_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRDM_POWER_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
55 }, 55 },
56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 57};
@@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
65 .pwrsts = PWRSTS_OFF_ON, 65 .pwrsts = PWRSTS_OFF_ON,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_OFF, /* gfx_mem */ 68 [0] = PWRSTS_OFF, /* gfx_mem */
69 }, 69 },
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* gfx_mem */ 71 [0] = PWRSTS_ON, /* gfx_mem */
72 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74}; 74};
@@ -80,15 +80,15 @@ static struct powerdomain abe_44xx_pwrdm = {
80 .prcm_partition = OMAP4430_PRM_PARTITION, 80 .prcm_partition = OMAP4430_PRM_PARTITION,
81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
82 .pwrsts = PWRSTS_OFF_RET_ON, 82 .pwrsts = PWRSTS_OFF_RET_ON,
83 .pwrsts_logic_ret = PWRDM_POWER_OFF, 83 .pwrsts_logic_ret = PWRSTS_OFF,
84 .banks = 2, 84 .banks = 2,
85 .pwrsts_mem_ret = { 85 .pwrsts_mem_ret = {
86 [0] = PWRDM_POWER_RET, /* aessmem */ 86 [0] = PWRSTS_RET, /* aessmem */
87 [1] = PWRDM_POWER_OFF, /* periphmem */ 87 [1] = PWRSTS_OFF, /* periphmem */
88 }, 88 },
89 .pwrsts_mem_on = { 89 .pwrsts_mem_on = {
90 [0] = PWRDM_POWER_ON, /* aessmem */ 90 [0] = PWRSTS_ON, /* aessmem */
91 [1] = PWRDM_POWER_ON, /* periphmem */ 91 [1] = PWRSTS_ON, /* periphmem */
92 }, 92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94}; 94};
@@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
103 .pwrsts_logic_ret = PWRSTS_OFF, 103 .pwrsts_logic_ret = PWRSTS_OFF,
104 .banks = 1, 104 .banks = 1,
105 .pwrsts_mem_ret = { 105 .pwrsts_mem_ret = {
106 [0] = PWRDM_POWER_OFF, /* dss_mem */ 106 [0] = PWRSTS_OFF, /* dss_mem */
107 }, 107 },
108 .pwrsts_mem_on = { 108 .pwrsts_mem_on = {
109 [0] = PWRDM_POWER_ON, /* dss_mem */ 109 [0] = PWRSTS_ON, /* dss_mem */
110 }, 110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112}; 112};
@@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
121 .pwrsts_logic_ret = PWRSTS_OFF_RET, 121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 3, 122 .banks = 3,
123 .pwrsts_mem_ret = { 123 .pwrsts_mem_ret = {
124 [0] = PWRDM_POWER_RET, /* tesla_edma */ 124 [0] = PWRSTS_RET, /* tesla_edma */
125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */ 125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */
126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */ 126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */
127 }, 127 },
128 .pwrsts_mem_on = { 128 .pwrsts_mem_on = {
129 [0] = PWRDM_POWER_ON, /* tesla_edma */ 129 [0] = PWRSTS_ON, /* tesla_edma */
130 [1] = PWRDM_POWER_ON, /* tesla_l1 */ 130 [1] = PWRSTS_ON, /* tesla_l1 */
131 [2] = PWRDM_POWER_ON, /* tesla_l2 */ 131 [2] = PWRSTS_ON, /* tesla_l2 */
132 }, 132 },
133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
134}; 134};
@@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
142 .pwrsts = PWRSTS_ON, 142 .pwrsts = PWRSTS_ON,
143 .banks = 1, 143 .banks = 1,
144 .pwrsts_mem_ret = { 144 .pwrsts_mem_ret = {
145 [0] = PWRDM_POWER_OFF, /* wkup_bank */ 145 [0] = PWRSTS_OFF, /* wkup_bank */
146 }, 146 },
147 .pwrsts_mem_on = { 147 .pwrsts_mem_on = {
148 [0] = PWRDM_POWER_ON, /* wkup_bank */ 148 [0] = PWRSTS_ON, /* wkup_bank */
149 }, 149 },
150}; 150};
151 151
@@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
163 }, 163 },
164 .pwrsts_mem_on = { 164 .pwrsts_mem_on = {
165 [0] = PWRDM_POWER_ON, /* cpu0_l1 */ 165 [0] = PWRSTS_ON, /* cpu0_l1 */
166 }, 166 },
167}; 167};
168 168
@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
180 }, 180 },
181 .pwrsts_mem_on = { 181 .pwrsts_mem_on = {
182 [0] = PWRDM_POWER_ON, /* cpu1_l1 */ 182 [0] = PWRSTS_ON, /* cpu1_l1 */
183 }, 183 },
184}; 184};
185 185
@@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
192 .pwrsts = PWRSTS_OFF_ON, 192 .pwrsts = PWRSTS_OFF_ON,
193 .banks = 1, 193 .banks = 1,
194 .pwrsts_mem_ret = { 194 .pwrsts_mem_ret = {
195 [0] = PWRDM_POWER_OFF, /* emu_bank */ 195 [0] = PWRSTS_OFF, /* emu_bank */
196 }, 196 },
197 .pwrsts_mem_on = { 197 .pwrsts_mem_on = {
198 [0] = PWRDM_POWER_ON, /* emu_bank */ 198 [0] = PWRSTS_ON, /* emu_bank */
199 }, 199 },
200}; 200};
201 201
@@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
211 .pwrsts_mem_ret = { 211 .pwrsts_mem_ret = {
212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */ 212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */ 213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
214 [2] = PWRDM_POWER_RET, /* mpu_ram */ 214 [2] = PWRSTS_RET, /* mpu_ram */
215 }, 215 },
216 .pwrsts_mem_on = { 216 .pwrsts_mem_on = {
217 [0] = PWRDM_POWER_ON, /* mpu_l1 */ 217 [0] = PWRSTS_ON, /* mpu_l1 */
218 [1] = PWRDM_POWER_ON, /* mpu_l2 */ 218 [1] = PWRSTS_ON, /* mpu_l2 */
219 [2] = PWRDM_POWER_ON, /* mpu_ram */ 219 [2] = PWRSTS_ON, /* mpu_ram */
220 }, 220 },
221}; 221};
222 222
@@ -227,19 +227,19 @@ static struct powerdomain ivahd_44xx_pwrdm = {
227 .prcm_partition = OMAP4430_PRM_PARTITION, 227 .prcm_partition = OMAP4430_PRM_PARTITION,
228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
229 .pwrsts = PWRSTS_OFF_RET_ON, 229 .pwrsts = PWRSTS_OFF_RET_ON,
230 .pwrsts_logic_ret = PWRDM_POWER_OFF, 230 .pwrsts_logic_ret = PWRSTS_OFF,
231 .banks = 4, 231 .banks = 4,
232 .pwrsts_mem_ret = { 232 .pwrsts_mem_ret = {
233 [0] = PWRDM_POWER_OFF, /* hwa_mem */ 233 [0] = PWRSTS_OFF, /* hwa_mem */
234 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 234 [1] = PWRSTS_OFF_RET, /* sl2_mem */
235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
237 }, 237 },
238 .pwrsts_mem_on = { 238 .pwrsts_mem_on = {
239 [0] = PWRDM_POWER_ON, /* hwa_mem */ 239 [0] = PWRSTS_ON, /* hwa_mem */
240 [1] = PWRDM_POWER_ON, /* sl2_mem */ 240 [1] = PWRSTS_ON, /* sl2_mem */
241 [2] = PWRDM_POWER_ON, /* tcm1_mem */ 241 [2] = PWRSTS_ON, /* tcm1_mem */
242 [3] = PWRDM_POWER_ON, /* tcm2_mem */ 242 [3] = PWRSTS_ON, /* tcm2_mem */
243 }, 243 },
244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 245};
@@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
253 .pwrsts = PWRSTS_OFF_ON, 253 .pwrsts = PWRSTS_OFF_ON,
254 .banks = 1, 254 .banks = 1,
255 .pwrsts_mem_ret = { 255 .pwrsts_mem_ret = {
256 [0] = PWRDM_POWER_OFF, /* cam_mem */ 256 [0] = PWRSTS_OFF, /* cam_mem */
257 }, 257 },
258 .pwrsts_mem_on = { 258 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* cam_mem */ 259 [0] = PWRSTS_ON, /* cam_mem */
260 }, 260 },
261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
262}; 262};
@@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
271 .pwrsts_logic_ret = PWRSTS_OFF_RET, 271 .pwrsts_logic_ret = PWRSTS_OFF_RET,
272 .banks = 1, 272 .banks = 1,
273 .pwrsts_mem_ret = { 273 .pwrsts_mem_ret = {
274 [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ 274 [0] = PWRSTS_OFF, /* l3init_bank1 */
275 }, 275 },
276 .pwrsts_mem_on = { 276 .pwrsts_mem_on = {
277 [0] = PWRDM_POWER_ON, /* l3init_bank1 */ 277 [0] = PWRSTS_ON, /* l3init_bank1 */
278 }, 278 },
279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
280}; 280};
@@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
289 .pwrsts_logic_ret = PWRSTS_OFF_RET, 289 .pwrsts_logic_ret = PWRSTS_OFF_RET,
290 .banks = 2, 290 .banks = 2,
291 .pwrsts_mem_ret = { 291 .pwrsts_mem_ret = {
292 [0] = PWRDM_POWER_OFF, /* nonretained_bank */ 292 [0] = PWRSTS_OFF, /* nonretained_bank */
293 [1] = PWRDM_POWER_RET, /* retained_bank */ 293 [1] = PWRSTS_RET, /* retained_bank */
294 }, 294 },
295 .pwrsts_mem_on = { 295 .pwrsts_mem_on = {
296 [0] = PWRDM_POWER_ON, /* nonretained_bank */ 296 [0] = PWRSTS_ON, /* nonretained_bank */
297 [1] = PWRDM_POWER_ON, /* retained_bank */ 297 [1] = PWRSTS_ON, /* retained_bank */
298 }, 298 },
299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
300}; 300};
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 3300ff6e3cfe..d22d1b43bccd 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* PRCM_MPU clockdomain register offsets (from instance start) */ 40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018 41#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018 42#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
43 43
44 44
45/* 45/*
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5fc20b..c9122dd6ee8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -37,14 +37,16 @@ static struct clk_functions *arch_clock;
37int clk_enable(struct clk *clk) 37int clk_enable(struct clk *clk)
38{ 38{
39 unsigned long flags; 39 unsigned long flags;
40 int ret = 0; 40 int ret;
41 41
42 if (clk == NULL || IS_ERR(clk)) 42 if (clk == NULL || IS_ERR(clk))
43 return -EINVAL; 43 return -EINVAL;
44 44
45 if (!arch_clock || !arch_clock->clk_enable)
46 return -EINVAL;
47
45 spin_lock_irqsave(&clockfw_lock, flags); 48 spin_lock_irqsave(&clockfw_lock, flags);
46 if (arch_clock->clk_enable) 49 ret = arch_clock->clk_enable(clk);
47 ret = arch_clock->clk_enable(clk);
48 spin_unlock_irqrestore(&clockfw_lock, flags); 50 spin_unlock_irqrestore(&clockfw_lock, flags);
49 51
50 return ret; 52 return ret;
@@ -58,6 +60,9 @@ void clk_disable(struct clk *clk)
58 if (clk == NULL || IS_ERR(clk)) 60 if (clk == NULL || IS_ERR(clk))
59 return; 61 return;
60 62
63 if (!arch_clock || !arch_clock->clk_disable)
64 return;
65
61 spin_lock_irqsave(&clockfw_lock, flags); 66 spin_lock_irqsave(&clockfw_lock, flags);
62 if (clk->usecount == 0) { 67 if (clk->usecount == 0) {
63 pr_err("Trying disable clock %s with 0 usecount\n", 68 pr_err("Trying disable clock %s with 0 usecount\n",
@@ -66,8 +71,7 @@ void clk_disable(struct clk *clk)
66 goto out; 71 goto out;
67 } 72 }
68 73
69 if (arch_clock->clk_disable) 74 arch_clock->clk_disable(clk);
70 arch_clock->clk_disable(clk);
71 75
72out: 76out:
73 spin_unlock_irqrestore(&clockfw_lock, flags); 77 spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -77,7 +81,7 @@ EXPORT_SYMBOL(clk_disable);
77unsigned long clk_get_rate(struct clk *clk) 81unsigned long clk_get_rate(struct clk *clk)
78{ 82{
79 unsigned long flags; 83 unsigned long flags;
80 unsigned long ret = 0; 84 unsigned long ret;
81 85
82 if (clk == NULL || IS_ERR(clk)) 86 if (clk == NULL || IS_ERR(clk))
83 return 0; 87 return 0;
@@ -97,14 +101,16 @@ EXPORT_SYMBOL(clk_get_rate);
97long clk_round_rate(struct clk *clk, unsigned long rate) 101long clk_round_rate(struct clk *clk, unsigned long rate)
98{ 102{
99 unsigned long flags; 103 unsigned long flags;
100 long ret = 0; 104 long ret;
101 105
102 if (clk == NULL || IS_ERR(clk)) 106 if (clk == NULL || IS_ERR(clk))
103 return ret; 107 return 0;
108
109 if (!arch_clock || !arch_clock->clk_round_rate)
110 return 0;
104 111
105 spin_lock_irqsave(&clockfw_lock, flags); 112 spin_lock_irqsave(&clockfw_lock, flags);
106 if (arch_clock->clk_round_rate) 113 ret = arch_clock->clk_round_rate(clk, rate);
107 ret = arch_clock->clk_round_rate(clk, rate);
108 spin_unlock_irqrestore(&clockfw_lock, flags); 114 spin_unlock_irqrestore(&clockfw_lock, flags);
109 115
110 return ret; 116 return ret;
@@ -119,14 +125,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
119 if (clk == NULL || IS_ERR(clk)) 125 if (clk == NULL || IS_ERR(clk))
120 return ret; 126 return ret;
121 127
128 if (!arch_clock || !arch_clock->clk_set_rate)
129 return ret;
130
122 spin_lock_irqsave(&clockfw_lock, flags); 131 spin_lock_irqsave(&clockfw_lock, flags);
123 if (arch_clock->clk_set_rate) 132 ret = arch_clock->clk_set_rate(clk, rate);
124 ret = arch_clock->clk_set_rate(clk, rate); 133 if (ret == 0)
125 if (ret == 0) {
126 if (clk->recalc)
127 clk->rate = clk->recalc(clk);
128 propagate_rate(clk); 134 propagate_rate(clk);
129 }
130 spin_unlock_irqrestore(&clockfw_lock, flags); 135 spin_unlock_irqrestore(&clockfw_lock, flags);
131 136
132 return ret; 137 return ret;
@@ -141,15 +146,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
141 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) 146 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
142 return ret; 147 return ret;
143 148
149 if (!arch_clock || !arch_clock->clk_set_parent)
150 return ret;
151
144 spin_lock_irqsave(&clockfw_lock, flags); 152 spin_lock_irqsave(&clockfw_lock, flags);
145 if (clk->usecount == 0) { 153 if (clk->usecount == 0) {
146 if (arch_clock->clk_set_parent) 154 ret = arch_clock->clk_set_parent(clk, parent);
147 ret = arch_clock->clk_set_parent(clk, parent); 155 if (ret == 0)
148 if (ret == 0) {
149 if (clk->recalc)
150 clk->rate = clk->recalc(clk);
151 propagate_rate(clk); 156 propagate_rate(clk);
152 }
153 } else 157 } else
154 ret = -EBUSY; 158 ret = -EBUSY;
155 spin_unlock_irqrestore(&clockfw_lock, flags); 159 spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -335,6 +339,38 @@ struct clk *omap_clk_get_by_name(const char *name)
335 return ret; 339 return ret;
336} 340}
337 341
342int omap_clk_enable_autoidle_all(void)
343{
344 struct clk *c;
345 unsigned long flags;
346
347 spin_lock_irqsave(&clockfw_lock, flags);
348
349 list_for_each_entry(c, &clocks, node)
350 if (c->ops->allow_idle)
351 c->ops->allow_idle(c);
352
353 spin_unlock_irqrestore(&clockfw_lock, flags);
354
355 return 0;
356}
357
358int omap_clk_disable_autoidle_all(void)
359{
360 struct clk *c;
361 unsigned long flags;
362
363 spin_lock_irqsave(&clockfw_lock, flags);
364
365 list_for_each_entry(c, &clocks, node)
366 if (c->ops->deny_idle)
367 c->ops->deny_idle(c);
368
369 spin_unlock_irqrestore(&clockfw_lock, flags);
370
371 return 0;
372}
373
338/* 374/*
339 * Low level helpers 375 * Low level helpers
340 */ 376 */
@@ -367,9 +403,11 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
367{ 403{
368 unsigned long flags; 404 unsigned long flags;
369 405
406 if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
407 return;
408
370 spin_lock_irqsave(&clockfw_lock, flags); 409 spin_lock_irqsave(&clockfw_lock, flags);
371 if (arch_clock->clk_init_cpufreq_table) 410 arch_clock->clk_init_cpufreq_table(table);
372 arch_clock->clk_init_cpufreq_table(table);
373 spin_unlock_irqrestore(&clockfw_lock, flags); 411 spin_unlock_irqrestore(&clockfw_lock, flags);
374} 412}
375 413
@@ -377,9 +415,11 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
377{ 415{
378 unsigned long flags; 416 unsigned long flags;
379 417
418 if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
419 return;
420
380 spin_lock_irqsave(&clockfw_lock, flags); 421 spin_lock_irqsave(&clockfw_lock, flags);
381 if (arch_clock->clk_exit_cpufreq_table) 422 arch_clock->clk_exit_cpufreq_table(table);
382 arch_clock->clk_exit_cpufreq_table(table);
383 spin_unlock_irqrestore(&clockfw_lock, flags); 423 spin_unlock_irqrestore(&clockfw_lock, flags);
384} 424}
385#endif 425#endif
@@ -397,6 +437,9 @@ static int __init clk_disable_unused(void)
397 struct clk *ck; 437 struct clk *ck;
398 unsigned long flags; 438 unsigned long flags;
399 439
440 if (!arch_clock || !arch_clock->clk_disable_unused)
441 return 0;
442
400 pr_info("clock: disabling unused clocks to save power\n"); 443 pr_info("clock: disabling unused clocks to save power\n");
401 list_for_each_entry(ck, &clocks, node) { 444 list_for_each_entry(ck, &clocks, node) {
402 if (ck->ops == &clkops_null) 445 if (ck->ops == &clkops_null)
@@ -406,14 +449,14 @@ static int __init clk_disable_unused(void)
406 continue; 449 continue;
407 450
408 spin_lock_irqsave(&clockfw_lock, flags); 451 spin_lock_irqsave(&clockfw_lock, flags);
409 if (arch_clock->clk_disable_unused) 452 arch_clock->clk_disable_unused(ck);
410 arch_clock->clk_disable_unused(ck);
411 spin_unlock_irqrestore(&clockfw_lock, flags); 453 spin_unlock_irqrestore(&clockfw_lock, flags);
412 } 454 }
413 455
414 return 0; 456 return 0;
415} 457}
416late_initcall(clk_disable_unused); 458late_initcall(clk_disable_unused);
459late_initcall(omap_clk_enable_autoidle_all);
417#endif 460#endif
418 461
419int __init clk_init(struct clk_functions * custom_clocks) 462int __init clk_init(struct clk_functions * custom_clocks)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf63ca0..ee9f6ebba29b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
342 l |= 0x02 << 3; /* Set to smart-idle mode */ 342 l |= 0x02 << 3; /* Set to smart-idle mode */
343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ 343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
344 344
345 /* Enable autoidle on OMAP2 / OMAP3 */
346 if (cpu_is_omap24xx() || cpu_is_omap34xx())
347 l |= 0x1 << 0;
348
345 /* 349 /*
346 * Enable wake-up on OMAP2 CPUs. 350 * Enable wake-up on OMAP2 CPUs.
347 */ 351 */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d43e6234dbbb..006e599c6613 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
25 * @disable: fn ptr that enables the current clock in hardware 25 * @disable: fn ptr that enables the current clock in hardware
26 * @find_idlest: function returning the IDLEST register for the clock's IP blk 26 * @find_idlest: function returning the IDLEST register for the clock's IP blk
27 * @find_companion: function returning the "companion" clk reg for the clock 27 * @find_companion: function returning the "companion" clk reg for the clock
28 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
29 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
28 * 30 *
29 * A "companion" clk is an accompanying clock to the one being queried 31 * A "companion" clk is an accompanying clock to the one being queried
30 * that must be enabled for the IP module connected to the clock to 32 * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
42 u8 *, u8 *); 44 u8 *, u8 *);
43 void (*find_companion)(struct clk *, void __iomem **, 45 void (*find_companion)(struct clk *, void __iomem **,
44 u8 *); 46 u8 *);
47 void (*allow_idle)(struct clk *);
48 void (*deny_idle)(struct clk *);
45}; 49};
46 50
47#ifdef CONFIG_ARCH_OMAP2PLUS 51#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -105,7 +109,6 @@ struct clksel {
105 * @clk_ref: struct clk pointer to the clock's reference clock input 109 * @clk_ref: struct clk pointer to the clock's reference clock input
106 * @control_reg: register containing the DPLL mode bitfield 110 * @control_reg: register containing the DPLL mode bitfield
107 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 111 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
108 * @rate_tolerance: maximum variance allowed from target rate (in Hz)
109 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 112 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
110 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 113 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
111 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 114 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
@@ -131,12 +134,9 @@ struct clksel {
131 * XXX Some DPLLs have multiple bypass inputs, so it's not technically 134 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
132 * correct to only have one @clk_bypass pointer. 135 * correct to only have one @clk_bypass pointer.
133 * 136 *
134 * XXX @rate_tolerance should probably be deprecated - currently there
135 * don't seem to be any usecases for DPLL rounding that is not exact.
136 *
137 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, 137 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
138 * @last_rounded_n) should be separated from the runtime-fixed fields 138 * @last_rounded_n) should be separated from the runtime-fixed fields
139 * and placed into a differenct structure, so that the runtime-fixed data 139 * and placed into a different structure, so that the runtime-fixed data
140 * can be placed into read-only space. 140 * can be placed into read-only space.
141 */ 141 */
142struct dpll_data { 142struct dpll_data {
@@ -147,7 +147,6 @@ struct dpll_data {
147 struct clk *clk_ref; 147 struct clk *clk_ref;
148 void __iomem *control_reg; 148 void __iomem *control_reg;
149 u32 enable_mask; 149 u32 enable_mask;
150 unsigned int rate_tolerance;
151 unsigned long last_rounded_rate; 150 unsigned long last_rounded_rate;
152 u16 last_rounded_m; 151 u16 last_rounded_m;
153 u16 max_multiplier; 152 u16 max_multiplier;
@@ -172,12 +171,24 @@ struct dpll_data {
172 171
173#endif 172#endif
174 173
175/* struct clk.flags possibilities */ 174/*
175 * struct clk.flags possibilities
176 *
177 * XXX document the rest of the clock flags here
178 *
179 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
180 * bits share the same register. This flag allows the
181 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
182 * should be used. This is a temporary solution - a better approach
183 * would be to associate clock type-specific data with the clock,
184 * similar to the struct dpll_data approach.
185 */
176#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 186#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
177#define CLOCK_IDLE_CONTROL (1 << 1) 187#define CLOCK_IDLE_CONTROL (1 << 1)
178#define CLOCK_NO_IDLE_PARENT (1 << 2) 188#define CLOCK_NO_IDLE_PARENT (1 << 2)
179#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 189#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
180#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 190#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
191#define CLOCK_CLKOUTX2 (1 << 5)
181 192
182/** 193/**
183 * struct clk - OMAP struct clk 194 * struct clk - OMAP struct clk
@@ -293,6 +304,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
293extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); 304extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
294#endif 305#endif
295extern struct clk *omap_clk_get_by_name(const char *name); 306extern struct clk *omap_clk_get_by_name(const char *name);
307extern int omap_clk_enable_autoidle_all(void);
308extern int omap_clk_disable_autoidle_all(void);
296 309
297extern const struct clkops clkops_null; 310extern const struct clkops clkops_null;
298 311
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 1b911681e911..d77928370463 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,6 +315,8 @@
315#define INT_34XX_SSM_ABORT_IRQ 6 315#define INT_34XX_SSM_ABORT_IRQ 6
316#define INT_34XX_SYS_NIRQ 7 316#define INT_34XX_SYS_NIRQ 7
317#define INT_34XX_D2D_FW_IRQ 8 317#define INT_34XX_D2D_FW_IRQ 8
318#define INT_34XX_L3_DBG_IRQ 9
319#define INT_34XX_L3_APP_IRQ 10
318#define INT_34XX_PRCM_MPU_IRQ 11 320#define INT_34XX_PRCM_MPU_IRQ 11
319#define INT_34XX_MCBSP1_IRQ 16 321#define INT_34XX_MCBSP1_IRQ 16
320#define INT_34XX_MCBSP2_IRQ 17 322#define INT_34XX_MCBSP2_IRQ 17
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 97aa8e763e16..8a1368fbbbd3 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -561,6 +561,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
561int omap_hwmod_disable_clocks(struct omap_hwmod *oh); 561int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
562 562
563int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); 563int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
564int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
564 565
565int omap_hwmod_reset(struct omap_hwmod *oh); 566int omap_hwmod_reset(struct omap_hwmod *oh);
566void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); 567void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
@@ -595,6 +596,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
595int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); 596int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
596u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); 597u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
597 598
599int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
600
598/* 601/*
599 * Chip variant-specific hwmod init routines - XXX should be converted 602 * Chip variant-specific hwmod init routines - XXX should be converted
600 * to use initcalls once the initial boot ordering is straightened out 603 * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 57adb270767b..9bbda9acb73b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -83,9 +83,11 @@
83#include <linux/err.h> 83#include <linux/err.h>
84#include <linux/io.h> 84#include <linux/io.h>
85#include <linux/clk.h> 85#include <linux/clk.h>
86#include <linux/clkdev.h>
86 87
87#include <plat/omap_device.h> 88#include <plat/omap_device.h>
88#include <plat/omap_hwmod.h> 89#include <plat/omap_hwmod.h>
90#include <plat/clock.h>
89 91
90/* These parameters are passed to _omap_device_{de,}activate() */ 92/* These parameters are passed to _omap_device_{de,}activate() */
91#define USE_WAKEUP_LAT 0 93#define USE_WAKEUP_LAT 0
@@ -239,12 +241,12 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
239} 241}
240 242
241/** 243/**
242 * _add_optional_clock_alias - Add clock alias for hwmod optional clocks 244 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
243 * @od: struct omap_device *od 245 * @od: struct omap_device *od
244 * 246 *
245 * For every optional clock present per hwmod per omap_device, this function 247 * For every optional clock present per hwmod per omap_device, this function
246 * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role> 248 * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
247 * if an entry is already present in it with the form <dev-id=NULL, con-id=role> 249 * if it does not exist already.
248 * 250 *
249 * The function is called from inside omap_device_build_ss(), after 251 * The function is called from inside omap_device_build_ss(), after
250 * omap_device_register. 252 * omap_device_register.
@@ -254,25 +256,39 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
254 * 256 *
255 * No return value. 257 * No return value.
256 */ 258 */
257static void _add_optional_clock_alias(struct omap_device *od, 259static void _add_optional_clock_clkdev(struct omap_device *od,
258 struct omap_hwmod *oh) 260 struct omap_hwmod *oh)
259{ 261{
260 int i; 262 int i;
261 263
262 for (i = 0; i < oh->opt_clks_cnt; i++) { 264 for (i = 0; i < oh->opt_clks_cnt; i++) {
263 struct omap_hwmod_opt_clk *oc; 265 struct omap_hwmod_opt_clk *oc;
264 int r; 266 struct clk *r;
267 struct clk_lookup *l;
265 268
266 oc = &oh->opt_clks[i]; 269 oc = &oh->opt_clks[i];
267 270
268 if (!oc->_clk) 271 if (!oc->_clk)
269 continue; 272 continue;
270 273
271 r = clk_add_alias(oc->role, dev_name(&od->pdev.dev), 274 r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
272 (char *)oc->clk, &od->pdev.dev); 275 if (!IS_ERR(r))
273 if (r) 276 continue; /* clkdev entry exists */
274 pr_err("omap_device: %s: clk_add_alias for %s failed\n", 277
278 r = omap_clk_get_by_name((char *)oc->clk);
279 if (IS_ERR(r)) {
280 pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
281 dev_name(&od->pdev.dev), oc->clk);
282 continue;
283 }
284
285 l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
286 if (!l) {
287 pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
275 dev_name(&od->pdev.dev), oc->role); 288 dev_name(&od->pdev.dev), oc->role);
289 return;
290 }
291 clkdev_add(l);
276 } 292 }
277} 293}
278 294
@@ -480,7 +496,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
480 496
481 for (i = 0; i < oh_cnt; i++) { 497 for (i = 0; i < oh_cnt; i++) {
482 hwmods[i]->od = od; 498 hwmods[i]->od = od;
483 _add_optional_clock_alias(od, hwmods[i]); 499 _add_optional_clock_clkdev(od, hwmods[i]);
484 } 500 }
485 501
486 if (ret) 502 if (ret)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 191332b845cc..158c0ee53b2c 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2117,14 +2117,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
2117 /* we start off in DISABLED state */ 2117 /* we start off in DISABLED state */
2118 host->dpm_state = DISABLED; 2118 host->dpm_state = DISABLED;
2119 2119
2120 if (mmc_host_enable(host->mmc) != 0) { 2120 if (clk_enable(host->iclk) != 0) {
2121 clk_put(host->iclk); 2121 clk_put(host->iclk);
2122 clk_put(host->fclk); 2122 clk_put(host->fclk);
2123 goto err1; 2123 goto err1;
2124 } 2124 }
2125 2125
2126 if (clk_enable(host->iclk) != 0) { 2126 if (mmc_host_enable(host->mmc) != 0) {
2127 mmc_host_disable(host->mmc); 2127 clk_disable(host->iclk);
2128 clk_put(host->iclk); 2128 clk_put(host->iclk);
2129 clk_put(host->fclk); 2129 clk_put(host->fclk);
2130 goto err1; 2130 goto err1;
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 3dd4971160ef..2b4acb86c191 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -124,6 +124,8 @@ static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
124 u32 pre_margin = GET_WLDR_VAL(timer_margin); 124 u32 pre_margin = GET_WLDR_VAL(timer_margin);
125 void __iomem *base = wdev->base; 125 void __iomem *base = wdev->base;
126 126
127 pm_runtime_get_sync(wdev->dev);
128
127 /* just count up at 32 KHz */ 129 /* just count up at 32 KHz */
128 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) 130 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
129 cpu_relax(); 131 cpu_relax();
@@ -131,6 +133,8 @@ static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
131 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); 133 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
132 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) 134 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
133 cpu_relax(); 135 cpu_relax();
136
137 pm_runtime_put_sync(wdev->dev);
134} 138}
135 139
136/* 140/*
@@ -160,6 +164,8 @@ static int omap_wdt_open(struct inode *inode, struct file *file)
160 omap_wdt_ping(wdev); /* trigger loading of new timeout value */ 164 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
161 omap_wdt_enable(wdev); 165 omap_wdt_enable(wdev);
162 166
167 pm_runtime_put_sync(wdev->dev);
168
163 return nonseekable_open(inode, file); 169 return nonseekable_open(inode, file);
164} 170}
165 171
@@ -171,6 +177,7 @@ static int omap_wdt_release(struct inode *inode, struct file *file)
171 * Shut off the timer unless NOWAYOUT is defined. 177 * Shut off the timer unless NOWAYOUT is defined.
172 */ 178 */
173#ifndef CONFIG_WATCHDOG_NOWAYOUT 179#ifndef CONFIG_WATCHDOG_NOWAYOUT
180 pm_runtime_get_sync(wdev->dev);
174 181
175 omap_wdt_disable(wdev); 182 omap_wdt_disable(wdev);
176 183
@@ -190,9 +197,11 @@ static ssize_t omap_wdt_write(struct file *file, const char __user *data,
190 197
191 /* Refresh LOAD_TIME. */ 198 /* Refresh LOAD_TIME. */
192 if (len) { 199 if (len) {
200 pm_runtime_get_sync(wdev->dev);
193 spin_lock(&wdt_lock); 201 spin_lock(&wdt_lock);
194 omap_wdt_ping(wdev); 202 omap_wdt_ping(wdev);
195 spin_unlock(&wdt_lock); 203 spin_unlock(&wdt_lock);
204 pm_runtime_put_sync(wdev->dev);
196 } 205 }
197 return len; 206 return len;
198} 207}
@@ -224,15 +233,18 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
224 return put_user(omap_prcm_get_reset_sources(), 233 return put_user(omap_prcm_get_reset_sources(),
225 (int __user *)arg); 234 (int __user *)arg);
226 case WDIOC_KEEPALIVE: 235 case WDIOC_KEEPALIVE:
236 pm_runtime_get_sync(wdev->dev);
227 spin_lock(&wdt_lock); 237 spin_lock(&wdt_lock);
228 omap_wdt_ping(wdev); 238 omap_wdt_ping(wdev);
229 spin_unlock(&wdt_lock); 239 spin_unlock(&wdt_lock);
240 pm_runtime_put_sync(wdev->dev);
230 return 0; 241 return 0;
231 case WDIOC_SETTIMEOUT: 242 case WDIOC_SETTIMEOUT:
232 if (get_user(new_margin, (int __user *)arg)) 243 if (get_user(new_margin, (int __user *)arg))
233 return -EFAULT; 244 return -EFAULT;
234 omap_wdt_adjust_timeout(new_margin); 245 omap_wdt_adjust_timeout(new_margin);
235 246
247 pm_runtime_get_sync(wdev->dev);
236 spin_lock(&wdt_lock); 248 spin_lock(&wdt_lock);
237 omap_wdt_disable(wdev); 249 omap_wdt_disable(wdev);
238 omap_wdt_set_timeout(wdev); 250 omap_wdt_set_timeout(wdev);
@@ -240,6 +252,7 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
240 252
241 omap_wdt_ping(wdev); 253 omap_wdt_ping(wdev);
242 spin_unlock(&wdt_lock); 254 spin_unlock(&wdt_lock);
255 pm_runtime_put_sync(wdev->dev);
243 /* Fall */ 256 /* Fall */
244 case WDIOC_GETTIMEOUT: 257 case WDIOC_GETTIMEOUT:
245 return put_user(timer_margin, (int __user *)arg); 258 return put_user(timer_margin, (int __user *)arg);
@@ -345,8 +358,11 @@ static void omap_wdt_shutdown(struct platform_device *pdev)
345{ 358{
346 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 359 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
347 360
348 if (wdev->omap_wdt_users) 361 if (wdev->omap_wdt_users) {
362 pm_runtime_get_sync(wdev->dev);
349 omap_wdt_disable(wdev); 363 omap_wdt_disable(wdev);
364 pm_runtime_put_sync(wdev->dev);
365 }
350} 366}
351 367
352static int __devexit omap_wdt_remove(struct platform_device *pdev) 368static int __devexit omap_wdt_remove(struct platform_device *pdev)
@@ -381,8 +397,11 @@ static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
381{ 397{
382 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 398 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
383 399
384 if (wdev->omap_wdt_users) 400 if (wdev->omap_wdt_users) {
401 pm_runtime_get_sync(wdev->dev);
385 omap_wdt_disable(wdev); 402 omap_wdt_disable(wdev);
403 pm_runtime_put_sync(wdev->dev);
404 }
386 405
387 return 0; 406 return 0;
388} 407}
@@ -392,8 +411,10 @@ static int omap_wdt_resume(struct platform_device *pdev)
392 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); 411 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
393 412
394 if (wdev->omap_wdt_users) { 413 if (wdev->omap_wdt_users) {
414 pm_runtime_get_sync(wdev->dev);
395 omap_wdt_enable(wdev); 415 omap_wdt_enable(wdev);
396 omap_wdt_ping(wdev); 416 omap_wdt_ping(wdev);
417 pm_runtime_put_sync(wdev->dev);
397 } 418 }
398 419
399 return 0; 420 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 07:43:08 -0500