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-rw-r--r--drivers/net/wireless/ath5k/ath5k.h59
-rw-r--r--drivers/net/wireless/ath5k/attach.c26
-rw-r--r--drivers/net/wireless/ath5k/base.c50
-rw-r--r--drivers/net/wireless/ath5k/qcu.c8
-rw-r--r--drivers/net/wireless/ath5k/reg.h577
-rw-r--r--drivers/net/wireless/ath5k/reset.c8
6 files changed, 490 insertions, 238 deletions
diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h
index 20018869051d..7134c40d6a69 100644
--- a/drivers/net/wireless/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath5k/ath5k.h
@@ -281,7 +281,9 @@ enum ath5k_radio {
281 AR5K_RF5112 = 2, 281 AR5K_RF5112 = 2,
282 AR5K_RF2413 = 3, 282 AR5K_RF2413 = 3,
283 AR5K_RF5413 = 4, 283 AR5K_RF5413 = 4,
284 AR5K_RF2425 = 5, 284 AR5K_RF2316 = 5,
285 AR5K_RF2317 = 6,
286 AR5K_RF2425 = 7,
285}; 287};
286 288
287/* 289/*
@@ -289,7 +291,7 @@ enum ath5k_radio {
289 */ 291 */
290 292
291enum ath5k_srev_type { 293enum ath5k_srev_type {
292 AR5K_VERSION_VER, 294 AR5K_VERSION_MAC,
293 AR5K_VERSION_RAD, 295 AR5K_VERSION_RAD,
294}; 296};
295 297
@@ -301,23 +303,24 @@ struct ath5k_srev_name {
301 303
302#define AR5K_SREV_UNKNOWN 0xffff 304#define AR5K_SREV_UNKNOWN 0xffff
303 305
304#define AR5K_SREV_VER_AR5210 0x00 306#define AR5K_SREV_AR5210 0x00 /* Crete */
305#define AR5K_SREV_VER_AR5311 0x10 307#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
306#define AR5K_SREV_VER_AR5311A 0x20 308#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
307#define AR5K_SREV_VER_AR5311B 0x30 309#define AR5K_SREV_AR5311B 0x30 /* Spirit */
308#define AR5K_SREV_VER_AR5211 0x40 310#define AR5K_SREV_AR5211 0x40 /* Oahu */
309#define AR5K_SREV_VER_AR5212 0x50 311#define AR5K_SREV_AR5212 0x50 /* Venice */
310#define AR5K_SREV_VER_AR5213 0x55 312#define AR5K_SREV_AR5213 0x55 /* ??? */
311#define AR5K_SREV_VER_AR5213A 0x59 313#define AR5K_SREV_AR5213A 0x59 /* Hainan */
312#define AR5K_SREV_VER_AR2413 0x78 314#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
313#define AR5K_SREV_VER_AR2414 0x79 315#define AR5K_SREV_AR2414 0x70 /* Griffin */
314#define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */ 316#define AR5K_SREV_AR5424 0x90 /* Condor */
315#define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */ 317#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
316#define AR5K_SREV_VER_AR5413 0xa4 318#define AR5K_SREV_AR5414 0xa0 /* Eagle */
317#define AR5K_SREV_VER_AR5414 0xa5 319#define AR5K_SREV_AR2415 0xb0 /* Cobra */
318#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */ 320#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
319#define AR5K_SREV_VER_AR5418 0xca /* PCI-E */ 321#define AR5K_SREV_AR5418 0xca /* PCI-E */
320#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */ 322#define AR5K_SREV_AR2425 0xe0 /* Swan */
323#define AR5K_SREV_AR2417 0xf0 /* Nala */
321 324
322#define AR5K_SREV_RAD_5110 0x00 325#define AR5K_SREV_RAD_5110 0x00
323#define AR5K_SREV_RAD_5111 0x10 326#define AR5K_SREV_RAD_5111 0x10
@@ -329,10 +332,20 @@ struct ath5k_srev_name {
329#define AR5K_SREV_RAD_2112 0x40 332#define AR5K_SREV_RAD_2112 0x40
330#define AR5K_SREV_RAD_2112A 0x45 333#define AR5K_SREV_RAD_2112A 0x45
331#define AR5K_SREV_RAD_2112B 0x46 334#define AR5K_SREV_RAD_2112B 0x46
332#define AR5K_SREV_RAD_SC0 0x50 /* Found on 2413/2414 */ 335#define AR5K_SREV_RAD_2413 0x50
333#define AR5K_SREV_RAD_SC1 0x60 /* Found on 5413/5414 */ 336#define AR5K_SREV_RAD_5413 0x60
334#define AR5K_SREV_RAD_SC2 0xa0 /* Found on 2424-5/5424 */ 337#define AR5K_SREV_RAD_2316 0x70
335#define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */ 338#define AR5K_SREV_RAD_2317 0x80
339#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
340#define AR5K_SREV_RAD_2425 0xa2
341#define AR5K_SREV_RAD_5133 0xc0
342
343#define AR5K_SREV_PHY_5211 0x30
344#define AR5K_SREV_PHY_5212 0x41
345#define AR5K_SREV_PHY_2112B 0x43
346#define AR5K_SREV_PHY_2413 0x45
347#define AR5K_SREV_PHY_5413 0x61
348#define AR5K_SREV_PHY_2425 0x70
336 349
337/* IEEE defs */ 350/* IEEE defs */
338#define IEEE80211_MAX_LEN 2500 351#define IEEE80211_MAX_LEN 2500
diff --git a/drivers/net/wireless/ath5k/attach.c b/drivers/net/wireless/ath5k/attach.c
index 153c4111fabe..d92b4a12567c 100644
--- a/drivers/net/wireless/ath5k/attach.c
+++ b/drivers/net/wireless/ath5k/attach.c
@@ -168,19 +168,19 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
168 CHANNEL_2GHZ); 168 CHANNEL_2GHZ);
169 169
170 /* Return on unsuported chips (unsupported eeprom etc) */ 170 /* Return on unsuported chips (unsupported eeprom etc) */
171 if ((srev >= AR5K_SREV_VER_AR5416) && 171 if ((srev >= AR5K_SREV_AR5416) &&
172 (srev < AR5K_SREV_VER_AR2425)) { 172 (srev < AR5K_SREV_AR2425)) {
173 ATH5K_ERR(sc, "Device not yet supported.\n"); 173 ATH5K_ERR(sc, "Device not yet supported.\n");
174 ret = -ENODEV; 174 ret = -ENODEV;
175 goto err_free; 175 goto err_free;
176 } else if (srev == AR5K_SREV_VER_AR2425) { 176 } else if (srev == AR5K_SREV_AR2425) {
177 ATH5K_WARN(sc, "Support for RF2425 is under development.\n"); 177 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
178 } 178 }
179 179
180 /* Identify single chip solutions */ 180 /* Identify single chip solutions */
181 if (((srev <= AR5K_SREV_VER_AR5414) && 181 if (((srev <= AR5K_SREV_AR5414) &&
182 (srev >= AR5K_SREV_VER_AR2413)) || 182 (srev >= AR5K_SREV_AR2413)) ||
183 (srev == AR5K_SREV_VER_AR2425)) { 183 (srev == AR5K_SREV_AR2425)) {
184 ah->ah_single_chip = true; 184 ah->ah_single_chip = true;
185 } else { 185 } else {
186 ah->ah_single_chip = false; 186 ah->ah_single_chip = false;
@@ -199,24 +199,24 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
199 * correctly. For now we are based on mac's srev to 199 * correctly. For now we are based on mac's srev to
200 * identify RF2425 radio. 200 * identify RF2425 radio.
201 */ 201 */
202 } else if (srev == AR5K_SREV_VER_AR2425) { 202 } else if (srev == AR5K_SREV_AR2425) {
203 ah->ah_radio = AR5K_RF2425; 203 ah->ah_radio = AR5K_RF2425;
204 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425; 204 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
205 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { 205 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
206 ah->ah_radio = AR5K_RF5111; 206 ah->ah_radio = AR5K_RF5111;
207 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111; 207 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
208 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) { 208 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2413) {
209 ah->ah_radio = AR5K_RF5112; 209 ah->ah_radio = AR5K_RF5112;
210 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112; 210 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
211 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { 211 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5413) {
212 ah->ah_radio = AR5K_RF2413; 212 ah->ah_radio = AR5K_RF2413;
213 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413; 213 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
214 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) { 214 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2316) {
215 ah->ah_radio = AR5K_RF5413; 215 ah->ah_radio = AR5K_RF5413;
216 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413; 216 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
217 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { 217 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
218 /* AR5424 */ 218 /* AR5424 */
219 if (srev >= AR5K_SREV_VER_AR5424) { 219 if (srev >= AR5K_SREV_AR5424) {
220 ah->ah_radio = AR5K_RF5413; 220 ah->ah_radio = AR5K_RF5413;
221 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413; 221 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
222 /* AR2424 */ 222 /* AR2424 */
@@ -252,8 +252,8 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
252 252
253 /* Write AR5K_PCICFG_UNK on 2112B and later chips */ 253 /* Write AR5K_PCICFG_UNK on 2112B and later chips */
254 if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B || 254 if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
255 srev > AR5K_SREV_VER_AR2413) { 255 srev > AR5K_SREV_AR2413) {
256 ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG); 256 ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
257 } 257 }
258 258
259 /* 259 /*
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c
index e09ed2ce6753..c8bb9bfb51fb 100644
--- a/drivers/net/wireless/ath5k/base.c
+++ b/drivers/net/wireless/ath5k/base.c
@@ -100,34 +100,40 @@ MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100 100
101/* Known SREVs */ 101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = { 102static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, 104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A }, 105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B }, 106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, 107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, 108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, 109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A }, 110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 }, 111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 }, 112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 }, 113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 }, 114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 }, 115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 }, 116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 }, 117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 }, 118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 }, 119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, 120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 }, 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 }, 132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 }, 133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
133}; 139};
@@ -536,7 +542,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
536 goto err_ah; 542 goto err_ah;
537 543
538 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 544 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
539 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev), 545 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
540 sc->ah->ah_mac_srev, 546 sc->ah->ah_mac_srev,
541 sc->ah->ah_phy_revision); 547 sc->ah->ah_phy_revision);
542 548
diff --git a/drivers/net/wireless/ath5k/qcu.c b/drivers/net/wireless/ath5k/qcu.c
index 2e20f7816ca7..01bf09176d23 100644
--- a/drivers/net/wireless/ath5k/qcu.c
+++ b/drivers/net/wireless/ath5k/qcu.c
@@ -375,7 +375,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
375 case AR5K_TX_QUEUE_BEACON: 375 case AR5K_TX_QUEUE_BEACON:
376 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 376 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
377 AR5K_QCU_MISC_FRSHED_DBA_GT | 377 AR5K_QCU_MISC_FRSHED_DBA_GT |
378 AR5K_QCU_MISC_CBREXP_BCN | 378 AR5K_QCU_MISC_CBREXP_BCN_DIS |
379 AR5K_QCU_MISC_BCN_ENABLE); 379 AR5K_QCU_MISC_BCN_ENABLE);
380 380
381 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 381 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
@@ -395,8 +395,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
395 case AR5K_TX_QUEUE_CAB: 395 case AR5K_TX_QUEUE_CAB:
396 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 396 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
397 AR5K_QCU_MISC_FRSHED_DBA_GT | 397 AR5K_QCU_MISC_FRSHED_DBA_GT |
398 AR5K_QCU_MISC_CBREXP | 398 AR5K_QCU_MISC_CBREXP_DIS |
399 AR5K_QCU_MISC_CBREXP_BCN); 399 AR5K_QCU_MISC_CBREXP_BCN_DIS);
400 400
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
402 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << 402 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
@@ -405,7 +405,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
405 405
406 case AR5K_TX_QUEUE_UAPSD: 406 case AR5K_TX_QUEUE_UAPSD:
407 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 407 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
408 AR5K_QCU_MISC_CBREXP); 408 AR5K_QCU_MISC_CBREXP_DIS);
409 break; 409 break;
410 410
411 case AR5K_TX_QUEUE_DATA: 411 case AR5K_TX_QUEUE_DATA:
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h
index 410f99a6d616..55054b575e83 100644
--- a/drivers/net/wireless/ath5k/reg.h
+++ b/drivers/net/wireless/ath5k/reg.h
@@ -29,6 +29,10 @@
29 * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf 29 * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf
30 * 30 *
31 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf 31 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
32 *
33 * This file also contains register values found on a memory dump of
34 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
35 * released by Atheros and on various debug messages found on the net.
32 */ 36 */
33 37
34 38
@@ -295,7 +299,7 @@
295#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ 299#define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
296#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ 300#define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
297#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 301#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
298#define AR5K_ISR_BRSSI 0x00020000 302#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
299#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 303#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
300#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 304#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
301#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 305#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
@@ -303,46 +307,56 @@
303#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 307#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
304#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 308#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
305#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 309#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */
306#define AR5K_ISR_TIM 0x00800000 /* [5210] */ 310#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
307#define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ 311#define AR5K_ISR_TIM 0x00800000 /* [5211+] */
308#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ 312#define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
309#define AR5K_ISR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ 313 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
310#define AR5K_ISR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ 314#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
311#define AR5K_ISR_QTRIG 0x08000000 /* [5211+] */ 315#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
316#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
317#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
312 318
313/* 319/*
314 * Secondary status registers [5211+] (0 - 4) 320 * Secondary status registers [5211+] (0 - 4)
315 * 321 *
316 * I guess from the names that these give the status for each 322 * These give the status for each QCU, only QCUs 0-9 are
317 * queue, that's why only masks are defined here, haven't got 323 * represented.
318 * any info about them (couldn't find them anywhere in ar5k code).
319 */ 324 */
320#define AR5K_SISR0 0x0084 /* Register Address [5211+] */ 325#define AR5K_SISR0 0x0084 /* Register Address [5211+] */
321#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 326#define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
327#define AR5K_SISR0_QCU_TXOK_S 0
322#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 328#define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
329#define AR5K_SISR0_QCU_TXDESC_S 16
323 330
324#define AR5K_SISR1 0x0088 /* Register Address [5211+] */ 331#define AR5K_SISR1 0x0088 /* Register Address [5211+] */
325#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 332#define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
333#define AR5K_SISR1_QCU_TXERR_S 0
326#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 334#define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
335#define AR5K_SISR1_QCU_TXEOL_S 16
327 336
328#define AR5K_SISR2 0x008c /* Register Address [5211+] */ 337#define AR5K_SISR2 0x008c /* Register Address [5211+] */
329#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 338#define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
339#define AR5K_SISR2_QCU_TXURN_S 0
330#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ 340#define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */
331#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ 341#define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */
332#define AR5K_SISR2_DPERR 0x00400000 /* Det par Error (?) */ 342#define AR5K_SISR2_DPERR 0x00400000 /* Bus parity error */
333#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ 343#define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
334#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ 344#define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
335#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ 345#define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
336#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 346#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
337#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 347#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
338#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 348#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
349#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */
339 350
340#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 351#define AR5K_SISR3 0x0090 /* Register Address [5211+] */
341#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 352#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
353#define AR5K_SISR3_QCBORN_S 0
342#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 354#define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
355#define AR5K_SISR3_QCBRURN_S 16
343 356
344#define AR5K_SISR4 0x0094 /* Register Address [5211+] */ 357#define AR5K_SISR4 0x0094 /* Register Address [5211+] */
345#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ 358#define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
359#define AR5K_SISR4_QTRIG_S 0
346 360
347/* 361/*
348 * Shadow read-and-clear interrupt status registers [5211+] 362 * Shadow read-and-clear interrupt status registers [5211+]
@@ -379,7 +393,7 @@
379#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ 393#define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
380#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ 394#define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
381#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ 395#define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
382#define AR5K_IMR_BRSSI 0x00020000 396#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
383#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 397#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
384#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 398#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
385#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 399#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
@@ -387,12 +401,14 @@
387#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ 401#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
388#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ 402#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
389#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 403#define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
404#define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
390#define AR5K_IMR_TIM 0x00800000 /* [5211+] */ 405#define AR5K_IMR_TIM 0x00800000 /* [5211+] */
391#define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ 406#define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
407 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
392#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ 408#define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
393#define AR5K_IMR_QCBRORN 0x02000000 /* CBR overrun (?) [5211+] */ 409#define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
394#define AR5K_IMR_QCBRURN 0x04000000 /* CBR underrun (?) [5211+] */ 410#define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
395#define AR5K_IMR_QTRIG 0x08000000 /* [5211+] */ 411#define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
396 412
397/* 413/*
398 * Secondary interrupt mask registers [5211+] (0 - 4) 414 * Secondary interrupt mask registers [5211+] (0 - 4)
@@ -414,13 +430,14 @@
414#define AR5K_SIMR2_QCU_TXURN_S 0 430#define AR5K_SIMR2_QCU_TXURN_S 0
415#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */ 431#define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */
416#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */ 432#define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */
417#define AR5K_SIMR2_DPERR 0x00400000 /* Det par Error (?) */ 433#define AR5K_SIMR2_DPERR 0x00400000 /* Bus parity error */
418#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ 434#define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
419#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ 435#define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
420#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ 436#define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
421#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 437#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
422#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 438#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
423#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ 439#define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
440#define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */
424 441
425#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ 442#define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
426#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 443#define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
@@ -586,15 +603,15 @@
586#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 603#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */
587#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 604#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
588#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 605#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
589#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ 606#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
590#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ 607#define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */
591#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ 608#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */
592#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ 609#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
593#define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ 610#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
594#define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ 611#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
595#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ 612#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
596#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled */ 613#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
597#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME enalbed */ 614#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
598#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ 615#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
599#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ 616#define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
600#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ 617#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
@@ -663,6 +680,7 @@
663#define AR5K_DCU_LCL_IFS_CW_MAX_S 10 680#define AR5K_DCU_LCL_IFS_CW_MAX_S 10
664#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ 681#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */
665#define AR5K_DCU_LCL_IFS_AIFS_S 20 682#define AR5K_DCU_LCL_IFS_AIFS_S 20
683#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */
666#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) 684#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
667 685
668/* 686/*
@@ -691,11 +709,7 @@
691/* 709/*
692 * DCU misc registers [5211+] 710 * DCU misc registers [5211+]
693 * 711 *
694 * For some of the registers i couldn't find in the code 712 * Note: Arbiter lockout control controls the
695 * (only backoff stuff is there realy) i tried to match the
696 * names with 802.11e parameters etc, so i guess VIRTCOL here
697 * means Virtual Collision and HCFPOLL means Hybrid Coordination
698 * factor Poll (CF- Poll). Arbiter lockout control controls the
699 * behaviour on low priority queues when we have multiple queues 713 * behaviour on low priority queues when we have multiple queues
700 * with pending frames. Intra-frame lockout means we wait until 714 * with pending frames. Intra-frame lockout means we wait until
701 * the queue's current frame transmits (with post frame backoff and bursting) 715 * the queue's current frame transmits (with post frame backoff and bursting)
@@ -705,15 +719,20 @@
705 * No lockout means there is no special handling. 719 * No lockout means there is no special handling.
706 */ 720 */
707#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ 721#define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
708#define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff threshold */ 722#define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
723#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series
724 station RTS/data failure count
725 reset policy (?) */
726#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series
727 CW reset policy */
728#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */
709#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ 729#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
710#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ 730#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
711#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ 731#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
712#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ 732#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
713#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ 733#define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
714#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 734#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
715#define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 735#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
716#define AR5K_DCU_MISC_VIRTCOL_IGNORE 2
717#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ 736#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
718#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ 737#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
719#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 738#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
@@ -768,8 +787,9 @@
768#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ 787#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
769#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ 788#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
770#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ 789#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
790#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
771#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ 791#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
772#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFC cnt reset policy (?) */ 792#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
773#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ 793#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
774#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ 794#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
775 795
@@ -831,9 +851,11 @@
831#define AR5K_SLEEP_CTL_SLE_S 16 851#define AR5K_SLEEP_CTL_SLE_S 16
832#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ 852#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
833#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ 853#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
834#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 854#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */
835#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ 855#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
836/* more bits */ 856#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
857#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
858#define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */
837 859
838/* 860/*
839 * Interrupt pending register 861 * Interrupt pending register
@@ -849,27 +871,28 @@
849 871
850/* 872/*
851 * PCI configuration register 873 * PCI configuration register
874 * TODO: Fix LED stuff
852 */ 875 */
853#define AR5K_PCICFG 0x4010 /* Register Address */ 876#define AR5K_PCICFG 0x4010 /* Register Address */
854#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ 877#define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
855#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock (?) */ 878#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
856#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ 879#define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
857#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ 880#define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
858#define AR5K_PCICFG_EESIZE_S 3 881#define AR5K_PCICFG_EESIZE_S 3
859#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ 882#define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
860#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ 883#define AR5K_PCICFG_EESIZE_8K 1 /* 8K */
861#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ 884#define AR5K_PCICFG_EESIZE_16K 2 /* 16K */
862#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size (?) [5211+] */ 885#define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */
863#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ 886#define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */
864#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ 887#define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */
865#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ 888#define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */
866#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ 889#define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */
867#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ 890#define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
868#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ 891#define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
869#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ 892#define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
870#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ 893#define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
871#define AR5K_PCICFG_UNK 0x00001000 /* Passed on some parts durring attach (?) */ 894#define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
872#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts (?) */ 895#define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/
873#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ 896#define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
874#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ 897#define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
875#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ 898#define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
@@ -882,7 +905,8 @@
882#define AR5K_PCICFG_LEDSTATE \ 905#define AR5K_PCICFG_LEDSTATE \
883 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ 906 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
884 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) 907 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
885#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate (field) */ 908#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */
909#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
886 910
887/* 911/*
888 * "General Purpose Input/Output" (GPIO) control register 912 * "General Purpose Input/Output" (GPIO) control register
@@ -904,8 +928,8 @@
904 928
905#define AR5K_GPIOCR 0x4014 /* Register Address */ 929#define AR5K_GPIOCR 0x4014 /* Register Address */
906#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 930#define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
907#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is off (?) */ 931#define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */
908#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is on */ 932#define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */
909#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ 933#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */
910#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ 934#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */
911#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ 935#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */
@@ -923,7 +947,6 @@
923#define AR5K_GPIODI 0x401c 947#define AR5K_GPIODI 0x401c
924#define AR5K_GPIODI_M 0x0000002f 948#define AR5K_GPIODI_M 0x0000002f
925 949
926
927/* 950/*
928 * Silicon revision register 951 * Silicon revision register
929 */ 952 */
@@ -933,7 +956,59 @@
933#define AR5K_SREV_VER 0x000000ff /* Mask for version */ 956#define AR5K_SREV_VER 0x000000ff /* Mask for version */
934#define AR5K_SREV_VER_S 4 957#define AR5K_SREV_VER_S 4
935 958
959/*
960 * TXE write posting register
961 */
962#define AR5K_TXEPOST 0x4028
963
964/*
965 * QCU sleep mask
966 */
967#define AR5K_QCU_SLEEP_MASK 0x402c
968
969/* 0x4068 is compression buffer configuration
970 * register on 5414 and pm configuration register
971 * on 5424 and newer pci-e chips. */
972
973/*
974 * Compression buffer configuration
975 * register (enable/disable) [5414]
976 */
977#define AR5K_5414_CBCFG 0x4068
978#define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */
979
980/*
981 * PCI-E Power managment configuration
982 * and status register [5424+]
983 */
984#define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
985/* Only 5424 */
986#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
987 when d2_sleep_en is asserted */
988#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */
989#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */
990#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
991 down */
992/* Wake On Wireless */
993#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
994#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */
995#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */
996#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
997#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
998#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
999#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
1000
1001/*
1002 * PCI-E Workaround enable register
1003 */
1004#define AR5K_PCIE_WAEN 0x407c
936 1005
1006/*
1007 * PCI-E Serializer/Desirializer
1008 * registers
1009 */
1010#define AR5K_PCIE_SERDES 0x4080
1011#define AR5K_PCIE_SERDES_RESET 0x4084
937 1012
938/*====EEPROM REGISTERS====*/ 1013/*====EEPROM REGISTERS====*/
939 1014
@@ -1006,14 +1081,28 @@
1006 * EEPROM config register 1081 * EEPROM config register
1007 */ 1082 */
1008#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ 1083#define AR5K_EEPROM_CFG 0x6010 /* Register Addres */
1009#define AR5K_EEPROM_CFG_SIZE_OVR 0x00000001 1084#define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */
1085#define AR5K_EEPROM_CFG_SIZE_AUTO 0
1086#define AR5K_EEPROM_CFG_SIZE_4KBIT 1
1087#define AR5K_EEPROM_CFG_SIZE_8KBIT 2
1088#define AR5K_EEPROM_CFG_SIZE_16KBIT 3
1010#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ 1089#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
1011#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ 1090#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
1012#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protectio key */ 1091#define AR5K_EEPROM_CFG_CLK_RATE_S 3
1092#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
1093#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
1094#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
1095#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */
1096#define AR5K_EEPROM_CFG_PROT_KEY_S 8
1013#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ 1097#define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
1014 1098
1015 1099
1016/* 1100/*
1101 * TODO: Wake On Wireless registers
1102 * Range 0x7000 - 0x7ce0
1103 */
1104
1105/*
1017 * Protocol Control Unit (PCU) registers 1106 * Protocol Control Unit (PCU) registers
1018 */ 1107 */
1019/* 1108/*
@@ -1045,11 +1134,13 @@
1045#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ 1134#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
1046#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ 1135#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
1047#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ 1136#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */
1048#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ 1137#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK/CTS [5211+] */
1049#define AR5K_STA_ID1_SELF_GEN_SECTORE 0x04000000 /* Self generate sectore (?) */ 1138#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */
1050#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ 1139#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
1051#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Keysearch mode (?) */ 1140#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */
1052#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ 1141#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
1142#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */
1143#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */
1053 1144
1054/* 1145/*
1055 * First BSSID register (MAC address, lower 32bits) 1146 * First BSSID register (MAC address, lower 32bits)
@@ -1308,16 +1399,16 @@
1308#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 1399#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1309#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ 1400#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1310 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) 1401 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
1311#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 1402#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */
1312#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 1403#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1313#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ 1404#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1314 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) 1405 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
1315#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 1406#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */
1316#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 1407#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1317#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 1408#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1318 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 1409 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
1319#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Enable scrambler seed */ 1410#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */
1320#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 1411#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
1321#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ 1412#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1322 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) 1413 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
1323#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ 1414#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */
@@ -1326,12 +1417,15 @@
1326#define AR5K_DIAG_SW_SCRAM_SEED_S 10 1417#define AR5K_DIAG_SW_SCRAM_SEED_S 10
1327#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ 1418#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */
1328#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 1419#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1329#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 1420#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1330#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ 1421#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1331 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 1422 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1332#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 1423#define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */
1333#define AR5K_DIAG_SW_OBSPT_S 18 1424#define AR5K_DIAG_SW_OBSPT_S 18
1334/* more bits */ 1425#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */
1426#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */
1427#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high (?) */
1428#define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */
1335 1429
1336/* 1430/*
1337 * TSF (clock) register (lower 32 bits) 1431 * TSF (clock) register (lower 32 bits)
@@ -1542,16 +1636,16 @@
1542 * 1636 *
1543 * XXX: PCDAC steps (0.5dbm) or DBM ? 1637 * XXX: PCDAC steps (0.5dbm) or DBM ?
1544 * 1638 *
1545 * XXX: Mask changes for newer chips to 7f
1546 * like tx power table ?
1547 */ 1639 */
1548#define AR5K_TXPC 0x80e8 /* Register Address */ 1640#define AR5K_TXPC 0x80e8 /* Register Address */
1549#define AR5K_TXPC_ACK_M 0x0000003f /* Mask for ACK tx power */ 1641#define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */
1550#define AR5K_TXPC_ACK_S 0 1642#define AR5K_TXPC_ACK_S 0
1551#define AR5K_TXPC_CTS_M 0x00003f00 /* Mask for CTS tx power */ 1643#define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */
1552#define AR5K_TXPC_CTS_S 8 1644#define AR5K_TXPC_CTS_S 8
1553#define AR5K_TXPC_CHIRP_M 0x003f0000 /* Mask for CHIRP tx power */ 1645#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */
1554#define AR5K_TXPC_CHIRP_S 22 1646#define AR5K_TXPC_CHIRP_S 16
1647#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */
1648#define AR5K_TXPC_DOPPLER_S 24
1555 1649
1556/* 1650/*
1557 * Profile count registers 1651 * Profile count registers
@@ -1562,14 +1656,19 @@
1562#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ 1656#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */
1563 1657
1564/* 1658/*
1565 * Quiet (period) control registers (?) 1659 * Quiet period control registers
1566 */ 1660 */
1567#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 1661#define AR5K_QUIET_CTL1 0x80fc /* Register Address */
1568#define AR5K_QUIET_CTL1_NEXT_QT 0x0000ffff /* Mask for next quiet (period?) (?) */ 1662#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */
1569#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet (period?) */ 1663#define AR5K_QUIET_CTL1_NEXT_QT_TSF_0
1664#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */
1665#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */
1666
1570#define AR5K_QUIET_CTL2 0x8100 /* Register Address */ 1667#define AR5K_QUIET_CTL2 0x8100 /* Register Address */
1571#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period (?) */ 1668#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */
1572#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet duration (?) */ 1669#define AR5K_QUIET_CTL2_QT_PER_S 0
1670#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */
1671#define AR5K_QUIET_CTL2_QT_DUR_S 16
1573 1672
1574/* 1673/*
1575 * TSF parameter register 1674 * TSF parameter register
@@ -1579,12 +1678,15 @@
1579#define AR5K_TSF_PARM_INC_S 0 1678#define AR5K_TSF_PARM_INC_S 0
1580 1679
1581/* 1680/*
1582 * QoS register (?) 1681 * QoS NOACK policy
1583 */ 1682 */
1584#define AR5K_QOS 0x8108 /* Register Address */ 1683#define AR5K_QOS_NOACK 0x8108 /* Register Address */
1585#define AR5K_QOS_NOACK_2BIT_VALUES 0x00000000 /* (field) */ 1684#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */
1586#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000020 /* (field) */ 1685#define AR5K_QOS_NOACK_2BIT_VALUES_S 0
1587#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000080 /* (field) */ 1686#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
1687#define AR5K_QOS_NOACK_BIT_OFFSET_S 4
1688#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
1689#define AR5K_QOS_NOACK_BYTE_OFFSET_S 8
1588 1690
1589/* 1691/*
1590 * PHY error filter register 1692 * PHY error filter register
@@ -1608,29 +1710,15 @@
1608/* 1710/*
1609 * MIC QoS control register (?) 1711 * MIC QoS control register (?)
1610 */ 1712 */
1611#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ 1713#define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */
1612#define AR5K_MIC_QOS_CTL_0 0x00000001 /* MIC QoS control 0 (?) */ 1714#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
1613#define AR5K_MIC_QOS_CTL_1 0x00000004 /* MIC QoS control 1 (?) */ 1715#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1614#define AR5K_MIC_QOS_CTL_2 0x00000010 /* MIC QoS control 2 (?) */
1615#define AR5K_MIC_QOS_CTL_3 0x00000040 /* MIC QoS control 3 (?) */
1616#define AR5K_MIC_QOS_CTL_4 0x00000100 /* MIC QoS control 4 (?) */
1617#define AR5K_MIC_QOS_CTL_5 0x00000400 /* MIC QoS control 5 (?) */
1618#define AR5K_MIC_QOS_CTL_6 0x00001000 /* MIC QoS control 6 (?) */
1619#define AR5K_MIC_QOS_CTL_7 0x00004000 /* MIC QoS control 7 (?) */
1620#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */
1621 1716
1622/* 1717/*
1623 * MIC QoS select register (?) 1718 * MIC QoS select register (?)
1624 */ 1719 */
1625#define AR5K_MIC_QOS_SEL 0x811c 1720#define AR5K_MIC_QOS_SEL 0x811c
1626#define AR5K_MIC_QOS_SEL_0 0x00000001 1721#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
1627#define AR5K_MIC_QOS_SEL_1 0x00000010
1628#define AR5K_MIC_QOS_SEL_2 0x00000100
1629#define AR5K_MIC_QOS_SEL_3 0x00001000
1630#define AR5K_MIC_QOS_SEL_4 0x00010000
1631#define AR5K_MIC_QOS_SEL_5 0x00100000
1632#define AR5K_MIC_QOS_SEL_6 0x01000000
1633#define AR5K_MIC_QOS_SEL_7 0x10000000
1634 1722
1635/* 1723/*
1636 * Misc mode control register (?) 1724 * Misc mode control register (?)
@@ -1665,6 +1753,11 @@
1665#define AR5K_TSF_THRES 0x813c 1753#define AR5K_TSF_THRES 0x813c
1666 1754
1667/* 1755/*
1756 * TODO: Wake On Wireless registers
1757 * Range: 0x8147 - 0x818c
1758 */
1759
1760/*
1668 * Rate -> ACK SIFS mapping table (32 entries) 1761 * Rate -> ACK SIFS mapping table (32 entries)
1669 */ 1762 */
1670#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ 1763#define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */
@@ -1779,7 +1872,8 @@
1779 */ 1872 */
1780#define AR5K_PHY_TURBO 0x9804 /* Register Address */ 1873#define AR5K_PHY_TURBO 0x9804 /* Register Address */
1781#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ 1874#define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */
1782#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Short mode (20Mhz channels) (?) */ 1875#define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */
1876#define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo mimo */
1783 1877
1784/* 1878/*
1785 * PHY agility command register 1879 * PHY agility command register
@@ -1789,6 +1883,11 @@
1789#define AR5K_PHY_TST1 0x9808 1883#define AR5K_PHY_TST1 0x9808
1790#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ 1884#define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/
1791#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ 1885#define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */
1886#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */
1887#define AR5K_PHY_TST1_TXSRC_SRC_S 1
1888#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */
1889#define AR5K_PHY_TST1_TXSRC_ALT_S 7
1890
1792 1891
1793/* 1892/*
1794 * PHY timing register 3 [5112+] 1893 * PHY timing register 3 [5112+]
@@ -1813,15 +1912,23 @@
1813 1912
1814/* 1913/*
1815 * PHY RF control registers 1914 * PHY RF control registers
1816 * (i think these are delay times,
1817 * these calibration values exist
1818 * in EEPROM)
1819 */ 1915 */
1820#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ 1916#define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */
1821#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* Mask for TX frame to TX d(esc?) start */ 1917#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */
1918#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
1822 1919
1823#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ 1920#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
1824#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* Mask for TX end to XLNA on */ 1921#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* TX end to XLNA on */
1922#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 0
1923
1924#define AR5K_PHY_ADC_CTL 0x982c
1925#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
1926#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
1927#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
1928#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
1929#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
1930#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
1931#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
1825 1932
1826#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ 1933#define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */
1827#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ 1934#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */
@@ -1843,14 +1950,19 @@
1843 * PHY settling register 1950 * PHY settling register
1844 */ 1951 */
1845#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1952#define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1846#define AR5K_PHY_SETTLING_AGC 0x0000007f /* Mask for AGC settling time */ 1953#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
1847#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Mask for Switch settlig time */ 1954#define AR5K_PHY_SETTLING_AGC_S 0
1955#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
1956#define AR5K_PHY_SETTLINK_SWITCH_S 7
1848 1957
1849/* 1958/*
1850 * PHY Gain registers 1959 * PHY Gain registers
1851 */ 1960 */
1852#define AR5K_PHY_GAIN 0x9848 /* Register Address */ 1961#define AR5K_PHY_GAIN 0x9848 /* Register Address */
1853#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* Mask for TX-RX Attenuation */ 1962#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1963#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
1964#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
1965#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
1854 1966
1855#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ 1967#define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */
1856#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ 1968#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
@@ -1860,18 +1972,21 @@
1860 * (for more infos read ANI patent) 1972 * (for more infos read ANI patent)
1861 */ 1973 */
1862#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ 1974#define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */
1863#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */ 1975#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */
1864#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */ 1976#define AR5K_PHY_DESIRED_SIZE_ADC_S 0
1865#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size */ 1977#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */
1978#define AR5K_PHY_DESIRED_SIZE_PGA_S 8
1979#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */
1980#define AR5K_PHY_DESIRED_SIZE_TOT_S 20
1866 1981
1867/* 1982/*
1868 * PHY signal register 1983 * PHY signal register
1869 * (for more infos read ANI patent) 1984 * (for more infos read ANI patent)
1870 */ 1985 */
1871#define AR5K_PHY_SIG 0x9858 /* Register Address */ 1986#define AR5K_PHY_SIG 0x9858 /* Register Address */
1872#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* Mask for FIRSTEP */ 1987#define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */
1873#define AR5K_PHY_SIG_FIRSTEP_S 12 1988#define AR5K_PHY_SIG_FIRSTEP_S 12
1874#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* Mask for FIPWR */ 1989#define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */
1875#define AR5K_PHY_SIG_FIRPWR_S 18 1990#define AR5K_PHY_SIG_FIRPWR_S 18
1876 1991
1877/* 1992/*
@@ -1879,9 +1994,9 @@
1879 * (for more infos read ANI patent) 1994 * (for more infos read ANI patent)
1880 */ 1995 */
1881#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ 1996#define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */
1882#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* Mask for AGC Coarse low */ 1997#define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */
1883#define AR5K_PHY_AGCCOARSE_LO_S 7 1998#define AR5K_PHY_AGCCOARSE_LO_S 7
1884#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* Mask for AGC Coarse high */ 1999#define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */
1885#define AR5K_PHY_AGCCOARSE_HI_S 15 2000#define AR5K_PHY_AGCCOARSE_HI_S 15
1886 2001
1887/* 2002/*
@@ -1890,6 +2005,8 @@
1890#define AR5K_PHY_AGCCTL 0x9860 /* Register address */ 2005#define AR5K_PHY_AGCCTL 0x9860 /* Register address */
1891#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ 2006#define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */
1892#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ 2007#define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */
2008#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */
2009#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */
1893 2010
1894/* 2011/*
1895 * PHY noise floor status register 2012 * PHY noise floor status register
@@ -1900,7 +2017,10 @@
1900#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) 2017#define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M)
1901#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) 2018#define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1)
1902#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) 2019#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
1903#define AR5K_PHY_NF_THRESH62 0x00001000 /* Thresh62 -check ANI patent- (field) */ 2020#define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2021#define AR5K_PHY_NF_THRESH62_S 12
2022#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* ??? */
2023#define AR5K_PHY_NF_MINCCA_PWR_S 19
1904 2024
1905/* 2025/*
1906 * PHY ADC saturation register [5110] 2026 * PHY ADC saturation register [5110]
@@ -1940,24 +2060,31 @@
1940 */ 2060 */
1941#define AR5K_PHY_SCR 0x9870 2061#define AR5K_PHY_SCR 0x9870
1942#define AR5K_PHY_SCR_32MHZ 0x0000001f 2062#define AR5K_PHY_SCR_32MHZ 0x0000001f
2063
1943#define AR5K_PHY_SLMT 0x9874 2064#define AR5K_PHY_SLMT 0x9874
1944#define AR5K_PHY_SLMT_32MHZ 0x0000007f 2065#define AR5K_PHY_SLMT_32MHZ 0x0000007f
2066
1945#define AR5K_PHY_SCAL 0x9878 2067#define AR5K_PHY_SCAL 0x9878
1946#define AR5K_PHY_SCAL_32MHZ 0x0000000e 2068#define AR5K_PHY_SCAL_32MHZ 0x0000000e
1947 2069
2070
1948/* 2071/*
1949 * PHY PLL (Phase Locked Loop) control register 2072 * PHY PLL (Phase Locked Loop) control register
1950 */ 2073 */
1951#define AR5K_PHY_PLL 0x987c 2074#define AR5K_PHY_PLL 0x987c
1952#define AR5K_PHY_PLL_20MHZ 0x13 /* For half rate (?) [5111+] */ 2075#define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */
1953#define AR5K_PHY_PLL_40MHZ_5211 0x18 /* For 802.11a */ 2076/* 40MHz -> 5GHz band */
2077#define AR5K_PHY_PLL_40MHZ_5211 0x00000018
1954#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa 2078#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
2079#define AR5K_PHY_PLL_40MHZ_5413 0x00000004
1955#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ 2080#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
1956 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) 2081 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
1957#define AR5K_PHY_PLL_44MHZ_5211 0x19 /* For 802.11b/g */ 2082/* 44MHz -> 2.4GHz band */
2083#define AR5K_PHY_PLL_44MHZ_5211 0x00000019
1958#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab 2084#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
1959#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ 2085#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
1960 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) 2086 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
2087
1961#define AR5K_PHY_PLL_RF5111 0x00000000 2088#define AR5K_PHY_PLL_RF5111 0x00000000
1962#define AR5K_PHY_PLL_RF5112 0x00000040 2089#define AR5K_PHY_PLL_RF5112 0x00000040
1963#define AR5K_PHY_PLL_HALF_RATE 0x00000100 2090#define AR5K_PHY_PLL_HALF_RATE 0x00000100
@@ -2024,6 +2151,19 @@
2024#define AR5K_PHY_RFSTG_DISABLE 0x00000021 2151#define AR5K_PHY_RFSTG_DISABLE 0x00000021
2025 2152
2026/* 2153/*
2154 * BIN masks (?)
2155 */
2156#define AR5K_PHY_BIN_MASK_1 0x9900
2157#define AR5K_PHY_BIN_MASK_2 0x9904
2158#define AR5K_PHY_BIN_MASK_3 0x9908
2159
2160#define AR5K_PHY_BIN_MASK_CTL 0x990c
2161#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
2162#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
2163#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
2164#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
2165
2166/*
2027 * PHY Antenna control register 2167 * PHY Antenna control register
2028 */ 2168 */
2029#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ 2169#define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */
@@ -2070,6 +2210,7 @@
2070#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ 2210#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
2071#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ 2211#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
2072#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ 2212#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
2213#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 0
2073#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ 2214#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
2074#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ 2215#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
2075#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ 2216#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
@@ -2116,7 +2257,6 @@
2116#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ 2257#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */
2117#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ 2258#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */
2118 2259
2119
2120/* 2260/*
2121 * PHY TX rate power registers [5112+] 2261 * PHY TX rate power registers [5112+]
2122 */ 2262 */
@@ -2138,6 +2278,8 @@
2138#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ 2278#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
2139#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 2279#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
2140#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ 2280#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */
2281#define AR5K_PHY_FRAME_CTL_EMU 0x80000000
2282#define AR5K_PHY_FRAME_CTL_EMU_S 31
2141/*---[5110/5111]---*/ 2283/*---[5110/5111]---*/
2142#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ 2284#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */
2143#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ 2285#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */
@@ -2156,48 +2298,36 @@
2156 * PHY radar detection register [5111+] 2298 * PHY radar detection register [5111+]
2157 */ 2299 */
2158#define AR5K_PHY_RADAR 0x9954 2300#define AR5K_PHY_RADAR 0x9954
2159
2160/* Radar enable ........ ........ ........ .......1 */
2161#define AR5K_PHY_RADAR_ENABLE 0x00000001 2301#define AR5K_PHY_RADAR_ENABLE 0x00000001
2162#define AR5K_PHY_RADAR_DISABLE 0x00000000 2302#define AR5K_PHY_RADAR_DISABLE 0x00000000
2163#define AR5K_PHY_RADAR_ENABLE_S 0 2303#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold
2164 2304 5-bits, units unknown {0..31}
2165/* This is the value found on the card .1.111.1 .1.1.... 111....1 1...1... 2305 (? MHz ?) */
2166at power on. */
2167#define AR5K_PHY_RADAR_PWONDEF_AR5213 0x5d50e188
2168
2169/* This is the value found on the card .1.1.111 ..11...1 .1...1.1 1...11.1
2170after DFS is enabled */
2171#define AR5K_PHY_RADAR_ENABLED_AR5213 0x5731458d
2172
2173/* Finite Impulse Response (FIR) filter .1111111 ........ ........ ........
2174 * power out threshold.
2175 * 7-bits, standard power range {0..127} in 1/2 dBm units. */
2176#define AR5K_PHY_RADAR_FIRPWROUTTHR 0x7f000000
2177#define AR5K_PHY_RADAR_FIRPWROUTTHR_S 24
2178
2179/* Radar RSSI/SNR threshold. ........ 111111.. ........ ........
2180 * 6-bits, dBm range {0..63} in dBm units. */
2181#define AR5K_PHY_RADAR_RADARRSSITHR 0x00fc0000
2182#define AR5K_PHY_RADAR_RADARRSSITHR_S 18
2183
2184/* Pulse height threshold ........ ......11 1111.... ........
2185 * 6-bits, dBm range {0..63} in dBm units. */
2186#define AR5K_PHY_RADAR_PULSEHEIGHTTHR 0x0003f000
2187#define AR5K_PHY_RADAR_PULSEHEIGHTTHR_S 12
2188
2189/* Pulse RSSI/SNR threshold ........ ........ ....1111 11......
2190 * 6-bits, dBm range {0..63} in dBm units. */
2191#define AR5K_PHY_RADAR_PULSERSSITHR 0x00000fc0
2192#define AR5K_PHY_RADAR_PULSERSSITHR_S 6
2193
2194/* Inband threshold ........ ........ ........ ..11111.
2195 * 5-bits, units unknown {0..31} (? MHz ?) */
2196#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
2197#define AR5K_PHY_RADAR_INBANDTHR_S 1 2306#define AR5K_PHY_RADAR_INBANDTHR_S 1
2198 2307
2308#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold
2309 6-bits, dBm range {0..63}
2310 in dBm units. */
2311#define AR5K_PHY_RADAR_PRSSI_THR_S 6
2312
2313#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold
2314 6-bits, dBm range {0..63}
2315 in dBm units. */
2316#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
2317
2318#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold.
2319 6-bits, dBm range {0..63}
2320 in dBm units. */
2321#define AR5K_PHY_RADAR_RSSI_THR_S 18
2322
2323#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response
2324 filter power out threshold.
2325 7-bits, standard power range
2326 {0..127} in 1/2 dBm units. */
2327#define AR5K_PHY_RADAR_FIRPWR_THRS 24
2328
2199/* 2329/*
2200 * PHY antenna switch table registers [5110] 2330 * PHY antenna switch table registers
2201 */ 2331 */
2202#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 2332#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
2203#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 2333#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
@@ -2208,25 +2338,65 @@ after DFS is enabled */
2208#define AR5K_PHY_NFTHRES 0x9968 2338#define AR5K_PHY_NFTHRES 0x9968
2209 2339
2210/* 2340/*
2211 * PHY clock sleep registers [5112+] 2341 * Sigma Delta register (?) [5213]
2212 */ 2342 */
2213#define AR5K_PHY_SCLOCK 0x99f0 2343#define AR5K_PHY_SIGMA_DELTA 0x996C
2214#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c 2344#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
2215#define AR5K_PHY_SDELAY 0x99f4 2345#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
2216#define AR5K_PHY_SDELAY_32MHZ 0x000000ff 2346#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
2217#define AR5K_PHY_SPENDING 0x99f8 2347#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
2218#define AR5K_PHY_SPENDING_14 0x00000014 2348#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
2219#define AR5K_PHY_SPENDING_18 0x00000018 2349#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
2220#define AR5K_PHY_SPENDING_RF5111 0x00000018 2350#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ff3000
2221#define AR5K_PHY_SPENDING_RF5112 0x00000014 2351#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
2222/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */ 2352
2223/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */ 2353/*
2224#define AR5K_PHY_SPENDING_RF5413 0x00000014 2354 * RF restart register [5112+] (?)
2225#define AR5K_PHY_SPENDING_RF2413 0x00000014 2355 */
2226#define AR5K_PHY_SPENDING_RF2425 0x00000018 2356#define AR5K_PHY_RESTART 0x9970 /* restart */
2357#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */
2358#define AR5K_PHY_RESTART_DIV_GC_S 18
2359
2360/*
2361 * RF Bus access request register (for synth-oly channel switching)
2362 */
2363#define AR5K_PHY_RFBUS_REQ 0x997C
2364#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
2227 2365
2228/* 2366/*
2229 * Misc PHY/radio registers [5110 - 5111] 2367 * Spur mitigation masks (?)
2368 */
2369#define AR5K_PHY_TIMING_7 0x9980
2370#define AR5K_PHY_TIMING_8 0x9984
2371#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
2372#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
2373
2374#define AR5K_PHY_BIN_MASK2_1 0x9988
2375#define AR5K_PHY_BIN_MASK2_2 0x998c
2376#define AR5K_PHY_BIN_MASK2_3 0x9990
2377
2378#define AR5K_PHY_BIN_MASK2_4 0x9994
2379#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2380#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2381
2382#define AR_PHY_TIMING_9 0x9998
2383#define AR_PHY_TIMING_10 0x999c
2384#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2385#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0
2386
2387/*
2388 * Spur mitigation control
2389 */
2390#define AR_PHY_TIMING_11 0x99a0 /* Register address */
2391#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
2392#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2393#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
2394#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20
2395#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
2396#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
2397
2398/*
2399 * Gain tables
2230 */ 2400 */
2231#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 2401#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */
2232#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 2402#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
@@ -2246,9 +2416,10 @@ after DFS is enabled */
2246#define AR5K_PHY_CURRENT_RSSI 0x9c1c 2416#define AR5K_PHY_CURRENT_RSSI 0x9c1c
2247 2417
2248/* 2418/*
2249 * PHY RF Bus grant register (?) 2419 * PHY RF Bus grant register
2250 */ 2420 */
2251#define AR5K_PHY_RFBUS_GRANT 0x9c20 2421#define AR5K_PHY_RFBUS_GRANT 0x9c20
2422#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
2252 2423
2253/* 2424/*
2254 * PHY ADC test register 2425 * PHY ADC test register
@@ -2292,6 +2463,31 @@ after DFS is enabled */
2292#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 2463#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2293 2464
2294/* 2465/*
2466 * Heavy clip enable register
2467 */
2468#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
2469
2470/*
2471 * PHY clock sleep registers [5112+]
2472 */
2473#define AR5K_PHY_SCLOCK 0x99f0
2474#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
2475#define AR5K_PHY_SDELAY 0x99f4
2476#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
2477#define AR5K_PHY_SPENDING 0x99f8
2478#define AR5K_PHY_SPENDING_14 0x00000014
2479#define AR5K_PHY_SPENDING_18 0x00000018
2480#define AR5K_PHY_SPENDING_RF5111 0x00000018
2481#define AR5K_PHY_SPENDING_RF5112 0x00000014
2482/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
2483/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
2484#define AR5K_PHY_SPENDING_RF5413 0x00000018
2485#define AR5K_PHY_SPENDING_RF2413 0x00000018
2486#define AR5K_PHY_SPENDING_RF2316 0x00000018
2487#define AR5K_PHY_SPENDING_RF2317 0x00000018
2488#define AR5K_PHY_SPENDING_RF2425 0x00000014
2489
2490/*
2295 * PHY PAPD I (power?) table (?) 2491 * PHY PAPD I (power?) table (?)
2296 * (92! entries) 2492 * (92! entries)
2297 */ 2493 */
@@ -2342,10 +2538,47 @@ after DFS is enabled */
2342#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f 2538#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f
2343#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 2539#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
2344 2540
2541/* Same address is used for antenna diversity activation */
2542#define AR5K_PHY_FAST_ANT_DIV 0xa208
2543#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
2544
2345/* 2545/*
2346 * PHY 2GHz gain register [5111+] 2546 * PHY 2GHz gain register [5111+]
2347 */ 2547 */
2348#define AR5K_PHY_GAIN_2GHZ 0xa20c 2548#define AR5K_PHY_GAIN_2GHZ 0xa20c
2349#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 2549#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
2350#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 2550#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
2351#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c 2551#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
2552
2553#define AR5K_PHY_CCK_RX_CTL_4 0xa21c
2554#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
2555#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
2556
2557#define AR5K_PHY_DAG_CCK_CTL 0xa228
2558#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
2559#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
2560#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
2561
2562#define AR5K_PHY_FAST_ADC 0xa24c
2563
2564#define AR5K_PHY_BLUETOOTH 0xa254
2565
2566/*
2567 * Transmit Power Control register
2568 * [2413+]
2569 */
2570#define AR5K_PHY_TPC_RG1 0xa258
2571#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
2572#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
2573
2574#define AR5K_PHY_TPC_RG5 0xa26C
2575#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
2576#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
2577#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
2578#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
2579#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
2580#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
2581#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
2582#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
2583#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2584#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
diff --git a/drivers/net/wireless/ath5k/reset.c b/drivers/net/wireless/ath5k/reset.c
index 953ba3b19ff7..8f1886834e61 100644
--- a/drivers/net/wireless/ath5k/reset.c
+++ b/drivers/net/wireless/ath5k/reset.c
@@ -543,13 +543,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
543 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c); 543 ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
544 544
545 if (channel->hw_value == CHANNEL_G) 545 if (channel->hw_value == CHANNEL_G)
546 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413) 546 if (ah->ah_mac_srev < AR5K_SREV_AR2413)
547 ath5k_hw_reg_write(ah, 0x00f80d80, 547 ath5k_hw_reg_write(ah, 0x00f80d80,
548 0x994c); 548 0x994c);
549 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424) 549 else if (ah->ah_mac_srev < AR5K_SREV_AR5424)
550 ath5k_hw_reg_write(ah, 0x00380140, 550 ath5k_hw_reg_write(ah, 0x00380140,
551 0x994c); 551 0x994c);
552 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425) 552 else if (ah->ah_mac_srev < AR5K_SREV_AR2425)
553 ath5k_hw_reg_write(ah, 0x00fc0ec0, 553 ath5k_hw_reg_write(ah, 0x00fc0ec0,
554 0x994c); 554 0x994c);
555 else /* 2425 */ 555 else /* 2425 */
@@ -915,7 +915,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
915 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118); 915 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
916 ath5k_hw_reg_write(ah, 0x00003210, 0x811c); 916 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
917 ath5k_hw_reg_write(ah, 0x00000052, 0x8108); 917 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
918 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413) 918 if (ah->ah_mac_srev >= AR5K_SREV_AR2413)
919 ath5k_hw_reg_write(ah, 0x00000004, 0x8120); 919 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
920 } 920 }
921 921
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 13:27:35 -0500