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-rw-r--r--arch/arm/mach-exynos/Makefile1
-rw-r--r--arch/arm/mach-exynos/clock.c88
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c9
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c4
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c10
-rw-r--r--arch/arm/mach-exynos/pm.c24
-rw-r--r--arch/arm/mach-exynos/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s3c2416/Makefile1
-rw-r--r--arch/arm/mach-s3c2416/clock.c68
-rw-r--r--arch/arm/mach-s3c2416/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig8
-rw-r--r--arch/arm/mach-s3c64xx/Makefile2
-rw-r--r--arch/arm/mach-s3c64xx/clock.c206
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c180
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c45
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig7
-rw-r--r--arch/arm/mach-s5p64x0/Makefile2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c61
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c49
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c224
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c55
-rw-r--r--arch/arm/mach-s5pc100/Kconfig5
-rw-r--r--arch/arm/mach-s5pc100/Makefile3
-rw-r--r--arch/arm/mach-s5pc100/clock.c254
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c227
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c23
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c65
-rw-r--r--arch/arm/mach-s5pv210/Kconfig5
-rw-r--r--arch/arm/mach-s5pv210/Makefile3
-rw-r--r--arch/arm/mach-s5pv210/clock.c217
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c175
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c3
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c6
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c10
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c51
-rw-r--r--arch/arm/plat-s3c24xx/dma.c3
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c16
-rw-r--r--arch/arm/plat-samsung/Kconfig16
-rw-r--r--arch/arm/plat-samsung/devs.c127
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h24
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h31
-rw-r--r--drivers/mmc/host/sdhci-s3c.c7
-rw-r--r--drivers/spi/spi-s3c64xx.c14
50 files changed, 1000 insertions, 1438 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index fd0d9e9be382..ca85a99c159d 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -61,6 +61,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
61obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o 61obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
62obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o 62obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
63obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 63obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
64obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
65obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 64obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
66obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 65obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index befee4e13391..5d5250df33fd 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = {
1157 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1157 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1158 }, { 1158 }, {
1159 .clk = { 1159 .clk = {
1160 .name = "sclk_mmc",
1161 .devname = "s3c-sdhci.0",
1162 .parent = &clk_dout_mmc0.clk,
1163 .enable = exynos4_clksrc_mask_fsys_ctrl,
1164 .ctrlbit = (1 << 0),
1165 },
1166 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1167 }, {
1168 .clk = {
1169 .name = "sclk_mmc",
1170 .devname = "s3c-sdhci.1",
1171 .parent = &clk_dout_mmc1.clk,
1172 .enable = exynos4_clksrc_mask_fsys_ctrl,
1173 .ctrlbit = (1 << 4),
1174 },
1175 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1176 }, {
1177 .clk = {
1178 .name = "sclk_mmc",
1179 .devname = "s3c-sdhci.2",
1180 .parent = &clk_dout_mmc2.clk,
1181 .enable = exynos4_clksrc_mask_fsys_ctrl,
1182 .ctrlbit = (1 << 8),
1183 },
1184 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1185 }, {
1186 .clk = {
1187 .name = "sclk_mmc",
1188 .devname = "s3c-sdhci.3",
1189 .parent = &clk_dout_mmc3.clk,
1190 .enable = exynos4_clksrc_mask_fsys_ctrl,
1191 .ctrlbit = (1 << 12),
1192 },
1193 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1194 }, {
1195 .clk = {
1196 .name = "sclk_dwmmc", 1160 .name = "sclk_dwmmc",
1197 .parent = &clk_dout_mmc4.clk, 1161 .parent = &clk_dout_mmc4.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl, 1162 .enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
1250 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, 1214 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1251}; 1215};
1252 1216
1217static struct clksrc_clk clk_sclk_mmc0 = {
1218 .clk = {
1219 .name = "sclk_mmc",
1220 .devname = "s3c-sdhci.0",
1221 .parent = &clk_dout_mmc0.clk,
1222 .enable = exynos4_clksrc_mask_fsys_ctrl,
1223 .ctrlbit = (1 << 0),
1224 },
1225 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1226};
1227
1228static struct clksrc_clk clk_sclk_mmc1 = {
1229 .clk = {
1230 .name = "sclk_mmc",
1231 .devname = "s3c-sdhci.1",
1232 .parent = &clk_dout_mmc1.clk,
1233 .enable = exynos4_clksrc_mask_fsys_ctrl,
1234 .ctrlbit = (1 << 4),
1235 },
1236 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1237};
1238
1239static struct clksrc_clk clk_sclk_mmc2 = {
1240 .clk = {
1241 .name = "sclk_mmc",
1242 .devname = "s3c-sdhci.2",
1243 .parent = &clk_dout_mmc2.clk,
1244 .enable = exynos4_clksrc_mask_fsys_ctrl,
1245 .ctrlbit = (1 << 8),
1246 },
1247 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1248};
1249
1250static struct clksrc_clk clk_sclk_mmc3 = {
1251 .clk = {
1252 .name = "sclk_mmc",
1253 .devname = "s3c-sdhci.3",
1254 .parent = &clk_dout_mmc3.clk,
1255 .enable = exynos4_clksrc_mask_fsys_ctrl,
1256 .ctrlbit = (1 << 12),
1257 },
1258 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1259};
1260
1253/* Clock initialization code */ 1261/* Clock initialization code */
1254static struct clksrc_clk *sysclks[] = { 1262static struct clksrc_clk *sysclks[] = {
1255 &clk_mout_apll, 1263 &clk_mout_apll,
@@ -1294,6 +1302,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
1294 &clk_sclk_uart1, 1302 &clk_sclk_uart1,
1295 &clk_sclk_uart2, 1303 &clk_sclk_uart2,
1296 &clk_sclk_uart3, 1304 &clk_sclk_uart3,
1305 &clk_sclk_mmc0,
1306 &clk_sclk_mmc1,
1307 &clk_sclk_mmc2,
1308 &clk_sclk_mmc3,
1297}; 1309};
1298 1310
1299static struct clk_lookup exynos4_clk_lookup[] = { 1311static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1301,6 +1313,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1301 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), 1313 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1302 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), 1314 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1303 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), 1315 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1316 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1317 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1318 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1319 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1304 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), 1320 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1305 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), 1321 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1306}; 1322};
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 635fb97e31ab..b895ec031105 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -249,13 +249,8 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
249 249
250static int nuri_bl_init(struct device *dev) 250static int nuri_bl_init(struct device *dev)
251{ 251{
252 int ret, gpio = EXYNOS4_GPE2(3); 252 return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
253 253 "LCD_LD0_EN");
254 ret = gpio_request(gpio, "LCD_LDO_EN");
255 if (!ret)
256 gpio_direction_output(gpio, 0);
257
258 return ret;
259} 254}
260 255
261static int nuri_bl_notify(struct device *dev, int brightness) 256static int nuri_bl_notify(struct device *dev, int brightness)
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 5b365613b470..a27b23eee9fa 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -131,9 +131,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
131 gpio_free(EXYNOS4_GPD0(1)); 131 gpio_free(EXYNOS4_GPD0(1));
132#endif 132#endif
133 /* fire nRESET on power up */ 133 /* fire nRESET on power up */
134 gpio_request(EXYNOS4_GPX0(6), "GPX0"); 134 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
135
136 gpio_direction_output(EXYNOS4_GPX0(6), 1);
137 mdelay(100); 135 mdelay(100);
138 136
139 gpio_set_value(EXYNOS4_GPX0(6), 0); 137 gpio_set_value(EXYNOS4_GPX0(6), 0);
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 52aea972746a..37ac93e8d6d9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -610,8 +610,7 @@ static void __init universal_tsp_init(void)
610 610
611 /* TSP_LDO_ON: XMDMADDR_11 */ 611 /* TSP_LDO_ON: XMDMADDR_11 */
612 gpio = EXYNOS4_GPE2(3); 612 gpio = EXYNOS4_GPE2(3);
613 gpio_request(gpio, "TSP_LDO_ON"); 613 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
614 gpio_direction_output(gpio, 1);
615 gpio_export(gpio, 0); 614 gpio_export(gpio, 0);
616 615
617 /* TSP_INT: XMDMADDR_7 */ 616 /* TSP_INT: XMDMADDR_7 */
@@ -671,8 +670,7 @@ static void __init universal_touchkey_init(void)
671 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); 670 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
672 671
673 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ 672 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
674 gpio_request(gpio, "3_TOUCH_EN"); 673 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
675 gpio_direction_output(gpio, 1);
676} 674}
677 675
678static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { 676static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
@@ -1002,9 +1000,7 @@ static void __init universal_map_io(void)
1002void s5p_tv_setup(void) 1000void s5p_tv_setup(void)
1003{ 1001{
1004 /* direct HPD to HDMI chip */ 1002 /* direct HPD to HDMI chip */
1005 gpio_request(EXYNOS4_GPX3(7), "hpd-plug"); 1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1006
1007 gpio_direction_input(EXYNOS4_GPX3(7));
1008 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 1004 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1009 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 1005 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1010 1006
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c4f792dcad19..a4f61a43c7ba 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
26#include <asm/smp_scu.h>
26 27
27#include <plat/cpu.h> 28#include <plat/cpu.h>
28#include <plat/pm.h> 29#include <plat/pm.h>
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct device *dev)
213 return 0; 214 return 0;
214} 215}
215 216
216/* This function copy from linux/arch/arm/kernel/smp_scu.c */
217
218void exynos4_scu_enable(void __iomem *scu_base)
219{
220 u32 scu_ctrl;
221
222 scu_ctrl = __raw_readl(scu_base);
223 /* already enabled? */
224 if (scu_ctrl & 1)
225 return;
226
227 scu_ctrl |= 1;
228 __raw_writel(scu_ctrl, scu_base);
229
230 /*
231 * Ensure that the data accessed by CPU0 before the SCU was
232 * initialised is visible to the other CPUs.
233 */
234 flush_cache_all();
235}
236
237static unsigned long pll_base_rate; 217static unsigned long pll_base_rate;
238 218
239static void exynos4_restore_pll(void) 219static void exynos4_restore_pll(void)
@@ -404,7 +384,7 @@ static void exynos4_pm_resume(void)
404 384
405 exynos4_restore_pll(); 385 exynos4_restore_pll();
406 386
407 exynos4_scu_enable(S5P_VA_SCU); 387 scu_enable(S5P_VA_SCU);
408 388
409#ifdef CONFIG_CACHE_L2X0 389#ifdef CONFIG_CACHE_L2X0
410 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b410906..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *exynos4_hsmmc_clksrcs[4] = {
18 [0] = NULL,
19 [1] = NULL,
20 [2] = "sclk_mmc", /* mmc_bus */
21 [3] = NULL,
22};
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b279caf..ca0cd227f873 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o
15#obj-$(CONFIG_S3C2416_DMA) += dma.o 15#obj-$(CONFIG_S3C2416_DMA) += dma.o
16 16
17# Device setup 17# Device setup
18obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
19obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 18obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
20 19
21# Machine support 20# Machine support
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d1..59f54d1d7f8b 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
90 }, 90 },
91}; 91};
92 92
93static struct clksrc_clk hsmmc_mux[] = { 93static struct clksrc_clk hsmmc_mux0 = {
94 [0] = { 94 .clk = {
95 .clk = { 95 .name = "hsmmc-if",
96 .name = "hsmmc-if", 96 .devname = "s3c-sdhci.0",
97 .devname = "s3c-sdhci.0", 97 .ctrlbit = (1 << 6),
98 .ctrlbit = (1 << 6), 98 .enable = s3c2443_clkcon_enable_s,
99 .enable = s3c2443_clkcon_enable_s,
100 },
101 .sources = &(struct clksrc_sources) {
102 .nr_sources = 2,
103 .sources = (struct clk *[]) {
104 [0] = &hsmmc_div[0].clk,
105 [1] = NULL, /* to fix */
106 },
107 },
108 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
109 }, 99 },
110 [1] = { 100 .sources = &(struct clksrc_sources) {
111 .clk = { 101 .nr_sources = 2,
112 .name = "hsmmc-if", 102 .sources = (struct clk * []) {
113 .devname = "s3c-sdhci.1", 103 [0] = &hsmmc_div[0].clk,
114 .ctrlbit = (1 << 12), 104 [1] = NULL, /* to fix */
115 .enable = s3c2443_clkcon_enable_s,
116 }, 105 },
117 .sources = &(struct clksrc_sources) { 106 },
118 .nr_sources = 2, 107 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
119 .sources = (struct clk *[]) { 108};
120 [0] = &hsmmc_div[1].clk, 109
121 [1] = NULL, /* to fix */ 110static struct clksrc_clk hsmmc_mux1 = {
122 }, 111 .clk = {
112 .name = "hsmmc-if",
113 .devname = "s3c-sdhci.1",
114 .ctrlbit = (1 << 12),
115 .enable = s3c2443_clkcon_enable_s,
116 },
117 .sources = &(struct clksrc_sources) {
118 .nr_sources = 2,
119 .sources = (struct clk * []) {
120 [0] = &hsmmc_div[1].clk,
121 [1] = NULL, /* to fix */
123 }, 122 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
125 }, 123 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
126}; 125};
127 126
128static struct clk hsmmc0_clk = { 127static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
144 &hsspi_mux, 143 &hsspi_mux,
145 &hsmmc_div[0], 144 &hsmmc_div[0],
146 &hsmmc_div[1], 145 &hsmmc_div[1],
147 &hsmmc_mux[0], 146 &hsmmc_mux0,
148 &hsmmc_mux[1], 147 &hsmmc_mux1,
148};
149
150static struct clk_lookup s3c2416_clk_lookup[] = {
151 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
152 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
153 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
149}; 154};
150 155
151void __init s3c2416_init_clocks(int xtal) 156void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
167 s3c_register_clksrc(clksrcs[ptr], 1); 172 s3c_register_clksrc(clksrcs[ptr], 1);
168 173
169 s3c24xx_register_clock(&hsmmc0_clk); 174 s3c24xx_register_clock(&hsmmc0_clk);
175 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170 176
171 s3c_pwmclk_init(); 177 s3c_pwmclk_init();
172 178
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee53955eb02..000000000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
2 *
3 * Copyright 2010 Promwad Innovation Company
4 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
5 *
6 * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * Based on mach-s3c64xx/setup-sdhci.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c2416_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "hsmmc-if",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 381586c7b1b2..e42e26d7fd38 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -78,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
78 help 78 help
79 Common setup code for S3C64XX SDHCI GPIO configurations 79 Common setup code for S3C64XX SDHCI GPIO configurations
80 80
81config S3C64XX_SETUP_SPI
82 bool
83 help
84 Common setup code for SPI GPIO configurations
85
81# S36400 Macchine support 86# S36400 Macchine support
82 87
83config MACH_SMDK6400 88config MACH_SMDK6400
@@ -277,6 +282,7 @@ config MACH_WLF_CRAGG_6410
277 select S3C64XX_SETUP_IDE 282 select S3C64XX_SETUP_IDE
278 select S3C64XX_SETUP_FB_24BPP 283 select S3C64XX_SETUP_FB_24BPP
279 select S3C64XX_SETUP_KEYPAD 284 select S3C64XX_SETUP_KEYPAD
285 select S3C64XX_SETUP_SPI
280 select SAMSUNG_DEV_ADC 286 select SAMSUNG_DEV_ADC
281 select SAMSUNG_DEV_KEYPAD 287 select SAMSUNG_DEV_KEYPAD
282 select S3C_DEV_USB_HOST 288 select S3C_DEV_USB_HOST
@@ -287,7 +293,7 @@ config MACH_WLF_CRAGG_6410
287 select S3C_DEV_I2C1 293 select S3C_DEV_I2C1
288 select S3C_DEV_WDT 294 select S3C_DEV_WDT
289 select S3C_DEV_RTC 295 select S3C_DEV_RTC
290 select S3C64XX_DEV_SPI 296 select S3C64XX_DEV_SPI0
291 select S3C24XX_GPIO_EXTRA128 297 select S3C24XX_GPIO_EXTRA128
292 select I2C 298 select I2C
293 help 299 help
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f37016cebbe3..1822ac2eba31 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,8 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
40obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o 40obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
41obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o 41obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
42obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o 42obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
43obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
44obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 43obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
44obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
45 45
46# Machine support 46# Machine support
47 47
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index a3aafb6768c9..31bb27dc4aeb 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
184 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, { 186 }, {
187 .name = "spi_48m",
188 .devname = "s3c64xx-spi.0",
189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
194 .devname = "s3c64xx-spi.1",
195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
199 .name = "48m", 187 .name = "48m",
200 .devname = "s3c-sdhci.0", 188 .devname = "s3c-sdhci.0",
201 .parent = &clk_48m, 189 .parent = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
226 }, 214 },
227}; 215};
228 216
217static struct clk clk_48m_spi0 = {
218 .name = "spi_48m",
219 .devname = "s3c64xx-spi.0",
220 .parent = &clk_48m,
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
223};
224
225static struct clk clk_48m_spi1 = {
226 .name = "spi_48m",
227 .devname = "s3c64xx-spi.1",
228 .parent = &clk_48m,
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
231};
232
229static struct clk init_clocks[] = { 233static struct clk init_clocks[] = {
230 { 234 {
231 .name = "lcd", 235 .name = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
243 .enable = s3c64xx_hclk_ctrl, 247 .enable = s3c64xx_hclk_ctrl,
244 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 248 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
245 }, { 249 }, {
246 .name = "hsmmc",
247 .devname = "s3c-sdhci.0",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
251 }, {
252 .name = "hsmmc",
253 .devname = "s3c-sdhci.1",
254 .parent = &clk_h,
255 .enable = s3c64xx_hclk_ctrl,
256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
257 }, {
258 .name = "hsmmc",
259 .devname = "s3c-sdhci.2",
260 .parent = &clk_h,
261 .enable = s3c64xx_hclk_ctrl,
262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
263 }, {
264 .name = "otg", 250 .name = "otg",
265 .parent = &clk_h, 251 .parent = &clk_h,
266 .enable = s3c64xx_hclk_ctrl, 252 .enable = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
310 } 296 }
311}; 297};
312 298
299static struct clk clk_hsmmc0 = {
300 .name = "hsmmc",
301 .devname = "s3c-sdhci.0",
302 .parent = &clk_h,
303 .enable = s3c64xx_hclk_ctrl,
304 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
305};
306
307static struct clk clk_hsmmc1 = {
308 .name = "hsmmc",
309 .devname = "s3c-sdhci.1",
310 .parent = &clk_h,
311 .enable = s3c64xx_hclk_ctrl,
312 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
313};
314
315static struct clk clk_hsmmc2 = {
316 .name = "hsmmc",
317 .devname = "s3c-sdhci.2",
318 .parent = &clk_h,
319 .enable = s3c64xx_hclk_ctrl,
320 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
321};
313 322
314static struct clk clk_fout_apll = { 323static struct clk clk_fout_apll = {
315 .name = "fout_apll", 324 .name = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
578static struct clksrc_clk clksrcs[] = { 587static struct clksrc_clk clksrcs[] = {
579 { 588 {
580 .clk = { 589 .clk = {
581 .name = "mmc_bus",
582 .devname = "s3c-sdhci.0",
583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
584 .enable = s3c64xx_sclk_ctrl,
585 },
586 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
587 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
588 .sources = &clkset_spi_mmc,
589 }, {
590 .clk = {
591 .name = "mmc_bus",
592 .devname = "s3c-sdhci.1",
593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
594 .enable = s3c64xx_sclk_ctrl,
595 },
596 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
597 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
598 .sources = &clkset_spi_mmc,
599 }, {
600 .clk = {
601 .name = "mmc_bus",
602 .devname = "s3c-sdhci.2",
603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
604 .enable = s3c64xx_sclk_ctrl,
605 },
606 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
607 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
608 .sources = &clkset_spi_mmc,
609 }, {
610 .clk = {
611 .name = "usb-bus-host", 590 .name = "usb-bus-host",
612 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 591 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
613 .enable = s3c64xx_sclk_ctrl, 592 .enable = s3c64xx_sclk_ctrl,
@@ -617,25 +596,6 @@ static struct clksrc_clk clksrcs[] = {
617 .sources = &clkset_uhost, 596 .sources = &clkset_uhost,
618 }, { 597 }, {
619 .clk = { 598 .clk = {
620 .name = "spi-bus",
621 .devname = "s3c64xx-spi.0",
622 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
623 .enable = s3c64xx_sclk_ctrl,
624 },
625 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
626 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
627 .sources = &clkset_spi_mmc,
628 }, {
629 .clk = {
630 .name = "spi-bus",
631 .devname = "s3c64xx-spi.1",
632 .enable = s3c64xx_sclk_ctrl,
633 },
634 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
635 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
636 .sources = &clkset_spi_mmc,
637 }, {
638 .clk = {
639 .name = "audio-bus", 599 .name = "audio-bus",
640 .devname = "samsung-i2s.0", 600 .devname = "samsung-i2s.0",
641 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
@@ -697,6 +657,66 @@ static struct clksrc_clk clk_sclk_uclk = {
697 .sources = &clkset_uart, 657 .sources = &clkset_uart,
698}; 658};
699 659
660static struct clksrc_clk clk_sclk_mmc0 = {
661 .clk = {
662 .name = "mmc_bus",
663 .devname = "s3c-sdhci.0",
664 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
665 .enable = s3c64xx_sclk_ctrl,
666 },
667 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
668 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
669 .sources = &clkset_spi_mmc,
670};
671
672static struct clksrc_clk clk_sclk_mmc1 = {
673 .clk = {
674 .name = "mmc_bus",
675 .devname = "s3c-sdhci.1",
676 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
677 .enable = s3c64xx_sclk_ctrl,
678 },
679 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
680 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
681 .sources = &clkset_spi_mmc,
682};
683
684static struct clksrc_clk clk_sclk_mmc2 = {
685 .clk = {
686 .name = "mmc_bus",
687 .devname = "s3c-sdhci.2",
688 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
689 .enable = s3c64xx_sclk_ctrl,
690 },
691 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
692 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
693 .sources = &clkset_spi_mmc,
694};
695
696static struct clksrc_clk clk_sclk_spi0 = {
697 .clk = {
698 .name = "spi-bus",
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
702 },
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
706};
707
708static struct clksrc_clk clk_sclk_spi1 = {
709 .clk = {
710 .name = "spi-bus",
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
714 },
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
718};
719
700/* Clock initialisation code */ 720/* Clock initialisation code */
701 721
702static struct clksrc_clk *init_parents[] = { 722static struct clksrc_clk *init_parents[] = {
@@ -707,11 +727,35 @@ static struct clksrc_clk *init_parents[] = {
707 727
708static struct clksrc_clk *clksrc_cdev[] = { 728static struct clksrc_clk *clksrc_cdev[] = {
709 &clk_sclk_uclk, 729 &clk_sclk_uclk,
730 &clk_sclk_mmc0,
731 &clk_sclk_mmc1,
732 &clk_sclk_mmc2,
733 &clk_sclk_spi0,
734 &clk_sclk_spi1,
735};
736
737static struct clk *clk_cdev[] = {
738 &clk_hsmmc0,
739 &clk_hsmmc1,
740 &clk_hsmmc2,
741 &clk_48m_spi0,
742 &clk_48m_spi1,
710}; 743};
711 744
712static struct clk_lookup s3c64xx_clk_lookup[] = { 745static struct clk_lookup s3c64xx_clk_lookup[] = {
713 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 746 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
714 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 747 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
715}; 759};
716 760
717#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +878,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
834 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 878 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
835 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 879 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
836 880
881 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883 s3c_disable_clocks(clk_cdev[cnt], 1);
884
837 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 885 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
838 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 886 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
839 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) 887 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd118723..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/export.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
22
23#include <plat/s3c64xx-spi.h>
24#include <plat/gpio-cfg.h>
25#include <plat/devs.h>
26
27static char *spi_src_clks[] = {
28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S3C64XX_GPC(0);
48 break;
49
50 case 1:
51 base = S3C64XX_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static struct resource s3c64xx_spi0_resource[] = {
66 [0] = {
67 .start = S3C64XX_PA_SPI0,
68 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
89 .cfg_gpio = s3c64xx_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x7f,
91 .rx_lvl_offset = 13,
92 .tx_st_done = 21,
93};
94
95static u64 spi_dmamask = DMA_BIT_MASK(32);
96
97struct platform_device s3c64xx_device_spi0 = {
98 .name = "s3c64xx-spi",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
101 .resource = s3c64xx_spi0_resource,
102 .dev = {
103 .dma_mask = &spi_dmamask,
104 .coherent_dma_mask = DMA_BIT_MASK(32),
105 .platform_data = &s3c64xx_spi0_pdata,
106 },
107};
108EXPORT_SYMBOL(s3c64xx_device_spi0);
109
110static struct resource s3c64xx_spi1_resource[] = {
111 [0] = {
112 .start = S3C64XX_PA_SPI1,
113 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = DMACH_SPI1_TX,
118 .end = DMACH_SPI1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = DMACH_SPI1_RX,
123 .end = DMACH_SPI1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126 [3] = {
127 .start = IRQ_SPI1,
128 .end = IRQ_SPI1,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
134 .cfg_gpio = s3c64xx_spi_cfg_gpio,
135 .fifo_lvl_mask = 0x7f,
136 .rx_lvl_offset = 13,
137 .tx_st_done = 21,
138};
139
140struct platform_device s3c64xx_device_spi1 = {
141 .name = "s3c64xx-spi",
142 .id = 1,
143 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
144 .resource = s3c64xx_spi1_resource,
145 .dev = {
146 .dma_mask = &spi_dmamask,
147 .coherent_dma_mask = DMA_BIT_MASK(32),
148 .platform_data = &s3c64xx_spi1_pdata,
149 },
150};
151EXPORT_SYMBOL(s3c64xx_device_spi1);
152
153void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
154{
155 struct s3c64xx_spi_info *pd;
156
157 /* Reject invalid configuration */
158 if (!num_cs || src_clk_nr < 0
159 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
160 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
161 return;
162 }
163
164 switch (cntrlr) {
165 case 0:
166 pd = &s3c64xx_spi0_pdata;
167 break;
168 case 1:
169 pd = &s3c64xx_spi1_pdata;
170 break;
171 default:
172 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
173 __func__, cntrlr);
174 return;
175 }
176
177 pd->num_cs = num_cs;
178 pd->src_clk_nr = src_clk_nr;
179 pd->src_clk_name = spi_src_clks[src_clk_nr];
180}
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d53..8e2097bb208a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
116#define S3C_PA_RTC S3C64XX_PA_RTC 116#define S3C_PA_RTC S3C64XX_PA_RTC
117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
118#define S3C_PA_SPI0 S3C64XX_PA_SPI0
119#define S3C_PA_SPI1 S3C64XX_PA_SPI1
118 120
119#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
120#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b21165..000000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c64xx_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "mmc_bus",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 000000000000..d9592ad7a825
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
1/* linux/arch/arm/mach-s3c64xx/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 return 0;
44}
45#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e6..dd8c85ef6dab 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,11 @@ config S5P64X0_SETUP_I2C1
36 help 36 help
37 Common setup code for i2c bus 1. 37 Common setup code for i2c bus 1.
38 38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
39# machine support 44# machine support
40 45
41config MACH_SMDK6440 46config MACH_SMDK6440
@@ -45,7 +50,6 @@ config MACH_SMDK6440
45 select S3C_DEV_I2C1 50 select S3C_DEV_I2C1
46 select S3C_DEV_RTC 51 select S3C_DEV_RTC
47 select S3C_DEV_WDT 52 select S3C_DEV_WDT
48 select S3C64XX_DEV_SPI
49 select SAMSUNG_DEV_ADC 53 select SAMSUNG_DEV_ADC
50 select SAMSUNG_DEV_BACKLIGHT 54 select SAMSUNG_DEV_BACKLIGHT
51 select SAMSUNG_DEV_PWM 55 select SAMSUNG_DEV_PWM
@@ -62,7 +66,6 @@ config MACH_SMDK6450
62 select S3C_DEV_I2C1 66 select S3C_DEV_I2C1
63 select S3C_DEV_RTC 67 select S3C_DEV_RTC
64 select S3C_DEV_WDT 68 select S3C_DEV_WDT
65 select S3C64XX_DEV_SPI
66 select SAMSUNG_DEV_ADC 69 select SAMSUNG_DEV_ADC
67 select SAMSUNG_DEV_BACKLIGHT 70 select SAMSUNG_DEV_BACKLIGHT
68 select SAMSUNG_DEV_PWM 71 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index d3f7409999f2..e167ca136f5d 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -28,8 +28,8 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
28# device support 28# device support
29 29
30obj-y += dev-audio.o 30obj-y += dev-audio.o
31obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
32 31
33obj-y += setup-i2c0.o 32obj-y += setup-i2c0.o
34obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 33obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
35obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 34obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 4c797ab3b3fd..925d2daa60c7 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -269,18 +269,6 @@ static struct clk init_clocks_off[] = {
269 .enable = s5p64x0_pclk_ctrl, 269 .enable = s5p64x0_pclk_ctrl,
270 .ctrlbit = (1 << 31), 270 .ctrlbit = (1 << 31),
271 }, { 271 }, {
272 .name = "sclk_spi_48",
273 .devname = "s3c64xx-spi.0",
274 .parent = &clk_48m,
275 .enable = s5p64x0_sclk_ctrl,
276 .ctrlbit = (1 << 22),
277 }, {
278 .name = "sclk_spi_48",
279 .devname = "s3c64xx-spi.1",
280 .parent = &clk_48m,
281 .enable = s5p64x0_sclk_ctrl,
282 .ctrlbit = (1 << 23),
283 }, {
284 .name = "mmc_48m", 272 .name = "mmc_48m",
285 .devname = "s3c-sdhci.0", 273 .devname = "s3c-sdhci.0",
286 .parent = &clk_48m, 274 .parent = &clk_48m,
@@ -422,26 +410,6 @@ static struct clksrc_clk clksrcs[] = {
422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 410 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
423 }, { 411 }, {
424 .clk = { 412 .clk = {
425 .name = "sclk_spi",
426 .devname = "s3c64xx-spi.0",
427 .ctrlbit = (1 << 20),
428 .enable = s5p64x0_sclk_ctrl,
429 },
430 .sources = &clkset_group1,
431 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
432 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
433 }, {
434 .clk = {
435 .name = "sclk_spi",
436 .devname = "s3c64xx-spi.1",
437 .ctrlbit = (1 << 21),
438 .enable = s5p64x0_sclk_ctrl,
439 },
440 .sources = &clkset_group1,
441 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
442 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
443 }, {
444 .clk = {
445 .name = "sclk_post", 413 .name = "sclk_post",
446 .ctrlbit = (1 << 10), 414 .ctrlbit = (1 << 10),
447 .enable = s5p64x0_sclk_ctrl, 415 .enable = s5p64x0_sclk_ctrl,
@@ -490,6 +458,30 @@ static struct clksrc_clk clk_sclk_uclk = {
490 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 458 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
491}; 459};
492 460
461static struct clksrc_clk clk_sclk_spi0 = {
462 .clk = {
463 .name = "sclk_spi",
464 .devname = "s3c64xx-spi.0",
465 .ctrlbit = (1 << 20),
466 .enable = s5p64x0_sclk_ctrl,
467 },
468 .sources = &clkset_group1,
469 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
470 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
471};
472
473static struct clksrc_clk clk_sclk_spi1 = {
474 .clk = {
475 .name = "sclk_spi",
476 .devname = "s3c64xx-spi.1",
477 .ctrlbit = (1 << 21),
478 .enable = s5p64x0_sclk_ctrl,
479 },
480 .sources = &clkset_group1,
481 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
482 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
483};
484
493/* Clock initialization code */ 485/* Clock initialization code */
494static struct clksrc_clk *sysclks[] = { 486static struct clksrc_clk *sysclks[] = {
495 &clk_mout_apll, 487 &clk_mout_apll,
@@ -510,11 +502,16 @@ static struct clk dummy_apb_pclk = {
510 502
511static struct clksrc_clk *clksrc_cdev[] = { 503static struct clksrc_clk *clksrc_cdev[] = {
512 &clk_sclk_uclk, 504 &clk_sclk_uclk,
505 &clk_sclk_spi0,
506 &clk_sclk_spi1,
513}; 507};
514 508
515static struct clk_lookup s5p6440_clk_lookup[] = { 509static struct clk_lookup s5p6440_clk_lookup[] = {
516 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 510 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
517 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 511 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
512 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
513 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
514 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
518}; 515};
519 516
520void __init_or_cpufreq s5p6440_setup_clocks(void) 517void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 26aa63402d6b..c390a59f68ac 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -444,26 +444,6 @@ static struct clksrc_clk clksrcs[] = {
444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
445 }, { 445 }, {
446 .clk = { 446 .clk = {
447 .name = "sclk_spi",
448 .devname = "s3c64xx-spi.0",
449 .ctrlbit = (1 << 20),
450 .enable = s5p64x0_sclk_ctrl,
451 },
452 .sources = &clkset_group2,
453 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
454 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
455 }, {
456 .clk = {
457 .name = "sclk_spi",
458 .devname = "s3c64xx-spi.1",
459 .ctrlbit = (1 << 21),
460 .enable = s5p64x0_sclk_ctrl,
461 },
462 .sources = &clkset_group2,
463 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
464 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
465 }, {
466 .clk = {
467 .name = "sclk_fimc", 447 .name = "sclk_fimc",
468 .ctrlbit = (1 << 10), 448 .ctrlbit = (1 << 10),
469 .enable = s5p64x0_sclk_ctrl, 449 .enable = s5p64x0_sclk_ctrl,
@@ -539,13 +519,42 @@ static struct clksrc_clk clk_sclk_uclk = {
539 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 519 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
540}; 520};
541 521
522static struct clksrc_clk clk_sclk_spi0 = {
523 .clk = {
524 .name = "sclk_spi",
525 .devname = "s3c64xx-spi.0",
526 .ctrlbit = (1 << 20),
527 .enable = s5p64x0_sclk_ctrl,
528 },
529 .sources = &clkset_group2,
530 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
531 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
532};
533
534static struct clksrc_clk clk_sclk_spi1 = {
535 .clk = {
536 .name = "sclk_spi",
537 .devname = "s3c64xx-spi.1",
538 .ctrlbit = (1 << 21),
539 .enable = s5p64x0_sclk_ctrl,
540 },
541 .sources = &clkset_group2,
542 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
543 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
544};
545
542static struct clksrc_clk *clksrc_cdev[] = { 546static struct clksrc_clk *clksrc_cdev[] = {
543 &clk_sclk_uclk, 547 &clk_sclk_uclk,
548 &clk_sclk_spi0,
549 &clk_sclk_spi1,
544}; 550};
545 551
546static struct clk_lookup s5p6450_clk_lookup[] = { 552static struct clk_lookup s5p6450_clk_lookup[] = {
547 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 553 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
548 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 554 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
555 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
556 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
557 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
549}; 558};
550 559
551/* Clock initialization code */ 560/* Clock initialization code */
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7dbc..000000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/cpu.h>
25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h>
27
28static char *s5p64x0_spi_src_clks[] = {
29 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
30 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the CS.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S5P6440_GPC(0);
48 break;
49
50 case 1:
51 base = S5P6440_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
66{
67 unsigned int base;
68
69 switch (pdev->id) {
70 case 0:
71 base = S5P6450_GPC(0);
72 break;
73
74 case 1:
75 base = S5P6450_GPC(4);
76 break;
77
78 default:
79 dev_err(&pdev->dev, "Invalid SPI Controller number!");
80 return -EINVAL;
81 }
82
83 s3c_gpio_cfgall_range(base, 3,
84 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
85
86 return 0;
87}
88
89static struct resource s5p64x0_spi0_resource[] = {
90 [0] = {
91 .start = S5P64X0_PA_SPI0,
92 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = DMACH_SPI0_TX,
97 .end = DMACH_SPI0_TX,
98 .flags = IORESOURCE_DMA,
99 },
100 [2] = {
101 .start = DMACH_SPI0_RX,
102 .end = DMACH_SPI0_RX,
103 .flags = IORESOURCE_DMA,
104 },
105 [3] = {
106 .start = IRQ_SPI0,
107 .end = IRQ_SPI0,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
113 .cfg_gpio = s5p6440_spi_cfg_gpio,
114 .fifo_lvl_mask = 0x1ff,
115 .rx_lvl_offset = 15,
116 .tx_st_done = 25,
117};
118
119static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
120 .cfg_gpio = s5p6450_spi_cfg_gpio,
121 .fifo_lvl_mask = 0x1ff,
122 .rx_lvl_offset = 15,
123 .tx_st_done = 25,
124};
125
126static u64 spi_dmamask = DMA_BIT_MASK(32);
127
128struct platform_device s5p64x0_device_spi0 = {
129 .name = "s3c64xx-spi",
130 .id = 0,
131 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
132 .resource = s5p64x0_spi0_resource,
133 .dev = {
134 .dma_mask = &spi_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137};
138
139static struct resource s5p64x0_spi1_resource[] = {
140 [0] = {
141 .start = S5P64X0_PA_SPI1,
142 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = DMACH_SPI1_TX,
147 .end = DMACH_SPI1_TX,
148 .flags = IORESOURCE_DMA,
149 },
150 [2] = {
151 .start = DMACH_SPI1_RX,
152 .end = DMACH_SPI1_RX,
153 .flags = IORESOURCE_DMA,
154 },
155 [3] = {
156 .start = IRQ_SPI1,
157 .end = IRQ_SPI1,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
163 .cfg_gpio = s5p6440_spi_cfg_gpio,
164 .fifo_lvl_mask = 0x7f,
165 .rx_lvl_offset = 15,
166 .tx_st_done = 25,
167};
168
169static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
170 .cfg_gpio = s5p6450_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173 .tx_st_done = 25,
174};
175
176struct platform_device s5p64x0_device_spi1 = {
177 .name = "s3c64xx-spi",
178 .id = 1,
179 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
180 .resource = s5p64x0_spi1_resource,
181 .dev = {
182 .dma_mask = &spi_dmamask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
188{
189 struct s3c64xx_spi_info *pd;
190
191 /* Reject invalid configuration */
192 if (!num_cs || src_clk_nr < 0
193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
194 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
195 return;
196 }
197
198 switch (cntrlr) {
199 case 0:
200 if (soc_is_s5p6450())
201 pd = &s5p6450_spi0_pdata;
202 else
203 pd = &s5p6440_spi0_pdata;
204
205 s5p64x0_device_spi0.dev.platform_data = pd;
206 break;
207 case 1:
208 if (soc_is_s5p6450())
209 pd = &s5p6450_spi1_pdata;
210 else
211 pd = &s5p6440_spi1_pdata;
212
213 s5p64x0_device_spi1.dev.platform_data = pd;
214 break;
215 default:
216 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
217 __func__, cntrlr);
218 return;
219 }
220
221 pd->num_cs = num_cs;
222 pd->src_clk_nr = src_clk_nr;
223 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
224}
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709d..0c0175dbfa34 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
67#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB 69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
70 72
71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
72#define S5P_PA_SROMC S5P64X0_PA_SROMC 74#define S5P_PA_SROMC S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 000000000000..e9b841240352
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/cpu.h>
17#include <plat/s3c64xx-spi.h>
18
19#ifdef CONFIG_S3C64XX_DEV_SPI0
20struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
21 .fifo_lvl_mask = 0x1ff,
22 .rx_lvl_offset = 15,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 if (soc_is_s5p6450())
29 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 else
32 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
33 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
34 return 0;
35}
36#endif
37
38#ifdef CONFIG_S3C64XX_DEV_SPI1
39struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
40 .fifo_lvl_mask = 0x7f,
41 .rx_lvl_offset = 15,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 if (soc_is_s5p6450())
48 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
49 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
50 else
51 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
52 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
53 return 0;
54}
55#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e538a4c67e9c..75a26eaf2633 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
45 help 45 help
46 Common setup code for SDHCI gpio. 46 Common setup code for SDHCI gpio.
47 47
48config S5PC100_SETUP_SPI
49 bool
50 help
51 Common setup code for SPI GPIO configurations.
52
48config MACH_SMDKC100 53config MACH_SMDKC100
49 bool "SMDKC100" 54 bool "SMDKC100"
50 select CPU_S5PC100 55 select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index c3166c4d2ace..118c711f74e8 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -22,12 +22,11 @@ obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
22# device support 22# device support
23 23
24obj-y += dev-audio.o 24obj-y += dev-audio.o
25obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
26 25
27obj-y += setup-i2c0.o 26obj-y += setup-i2c0.o
28obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o 27obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
29obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 28obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
30obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o 29obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
31obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o 30obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
32obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
33obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 31obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
32obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 49f8c30d58da..247194dd366c 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -427,24 +427,6 @@ static struct clk init_clocks_off[] = {
427 .enable = s5pc100_d0_2_ctrl, 427 .enable = s5pc100_d0_2_ctrl,
428 .ctrlbit = (1 << 1), 428 .ctrlbit = (1 << 1),
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.2",
432 .parent = &clk_div_d1_bus.clk,
433 .enable = s5pc100_d1_0_ctrl,
434 .ctrlbit = (1 << 7),
435 }, {
436 .name = "hsmmc",
437 .devname = "s3c-sdhci.1",
438 .parent = &clk_div_d1_bus.clk,
439 .enable = s5pc100_d1_0_ctrl,
440 .ctrlbit = (1 << 6),
441 }, {
442 .name = "hsmmc",
443 .devname = "s3c-sdhci.0",
444 .parent = &clk_div_d1_bus.clk,
445 .enable = s5pc100_d1_0_ctrl,
446 .ctrlbit = (1 << 5),
447 }, {
448 .name = "modemif", 430 .name = "modemif",
449 .parent = &clk_div_d1_bus.clk, 431 .parent = &clk_div_d1_bus.clk,
450 .enable = s5pc100_d1_0_ctrl, 432 .enable = s5pc100_d1_0_ctrl,
@@ -674,24 +656,6 @@ static struct clk init_clocks_off[] = {
674 .enable = s5pc100_d1_5_ctrl, 656 .enable = s5pc100_d1_5_ctrl,
675 .ctrlbit = (1 << 8), 657 .ctrlbit = (1 << 8),
676 }, { 658 }, {
677 .name = "spi_48m",
678 .devname = "s3c64xx-spi.0",
679 .parent = &clk_mout_48m.clk,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = (1 << 7),
682 }, {
683 .name = "spi_48m",
684 .devname = "s3c64xx-spi.1",
685 .parent = &clk_mout_48m.clk,
686 .enable = s5pc100_sclk0_ctrl,
687 .ctrlbit = (1 << 8),
688 }, {
689 .name = "spi_48m",
690 .devname = "s3c64xx-spi.2",
691 .parent = &clk_mout_48m.clk,
692 .enable = s5pc100_sclk0_ctrl,
693 .ctrlbit = (1 << 9),
694 }, {
695 .name = "mmc_48m", 659 .name = "mmc_48m",
696 .devname = "s3c-sdhci.0", 660 .devname = "s3c-sdhci.0",
697 .parent = &clk_mout_48m.clk, 661 .parent = &clk_mout_48m.clk,
@@ -712,6 +676,54 @@ static struct clk init_clocks_off[] = {
712 }, 676 },
713}; 677};
714 678
679static struct clk clk_hsmmc2 = {
680 .name = "hsmmc",
681 .devname = "s3c-sdhci.2",
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_0_ctrl,
684 .ctrlbit = (1 << 7),
685};
686
687static struct clk clk_hsmmc1 = {
688 .name = "hsmmc",
689 .devname = "s3c-sdhci.1",
690 .parent = &clk_div_d1_bus.clk,
691 .enable = s5pc100_d1_0_ctrl,
692 .ctrlbit = (1 << 6),
693};
694
695static struct clk clk_hsmmc0 = {
696 .name = "hsmmc",
697 .devname = "s3c-sdhci.0",
698 .parent = &clk_div_d1_bus.clk,
699 .enable = s5pc100_d1_0_ctrl,
700 .ctrlbit = (1 << 5),
701};
702
703static struct clk clk_48m_spi0 = {
704 .name = "spi_48m",
705 .devname = "s3c64xx-spi.0",
706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl,
708 .ctrlbit = (1 << 7),
709};
710
711static struct clk clk_48m_spi1 = {
712 .name = "spi_48m",
713 .devname = "s3c64xx-spi.1",
714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl,
716 .ctrlbit = (1 << 8),
717};
718
719static struct clk clk_48m_spi2 = {
720 .name = "spi_48m",
721 .devname = "s3c64xx-spi.2",
722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl,
724 .ctrlbit = (1 << 9),
725};
726
715static struct clk clk_vclk54m = { 727static struct clk clk_vclk54m = {
716 .name = "vclk_54m", 728 .name = "vclk_54m",
717 .rate = 54000000, 729 .rate = 54000000,
@@ -930,39 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = {
930static struct clksrc_clk clksrcs[] = { 942static struct clksrc_clk clksrcs[] = {
931 { 943 {
932 .clk = { 944 .clk = {
933 .name = "sclk_spi",
934 .devname = "s3c64xx-spi.0",
935 .ctrlbit = (1 << 4),
936 .enable = s5pc100_sclk0_ctrl,
937
938 },
939 .sources = &clk_src_group1,
940 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
941 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
942 }, {
943 .clk = {
944 .name = "sclk_spi",
945 .devname = "s3c64xx-spi.1",
946 .ctrlbit = (1 << 5),
947 .enable = s5pc100_sclk0_ctrl,
948
949 },
950 .sources = &clk_src_group1,
951 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
952 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
953 }, {
954 .clk = {
955 .name = "sclk_spi",
956 .devname = "s3c64xx-spi.2",
957 .ctrlbit = (1 << 6),
958 .enable = s5pc100_sclk0_ctrl,
959
960 },
961 .sources = &clk_src_group1,
962 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
963 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
964 }, {
965 .clk = {
966 .name = "sclk_mixer", 945 .name = "sclk_mixer",
967 .ctrlbit = (1 << 6), 946 .ctrlbit = (1 << 6),
968 .enable = s5pc100_sclk0_ctrl, 947 .enable = s5pc100_sclk0_ctrl,
@@ -1015,39 +994,6 @@ static struct clksrc_clk clksrcs[] = {
1015 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 994 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1016 }, { 995 }, {
1017 .clk = { 996 .clk = {
1018 .name = "sclk_mmc",
1019 .devname = "s3c-sdhci.0",
1020 .ctrlbit = (1 << 12),
1021 .enable = s5pc100_sclk1_ctrl,
1022
1023 },
1024 .sources = &clk_src_mmc0,
1025 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1026 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1027 }, {
1028 .clk = {
1029 .name = "sclk_mmc",
1030 .devname = "s3c-sdhci.1",
1031 .ctrlbit = (1 << 13),
1032 .enable = s5pc100_sclk1_ctrl,
1033
1034 },
1035 .sources = &clk_src_mmc12,
1036 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1037 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1038 }, {
1039 .clk = {
1040 .name = "sclk_mmc",
1041 .devname = "s3c-sdhci.2",
1042 .ctrlbit = (1 << 14),
1043 .enable = s5pc100_sclk1_ctrl,
1044
1045 },
1046 .sources = &clk_src_mmc12,
1047 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1048 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1049 }, {
1050 .clk = {
1051 .name = "sclk_irda", 997 .name = "sclk_irda",
1052 .ctrlbit = (1 << 10), 998 .ctrlbit = (1 << 10),
1053 .enable = s5pc100_sclk0_ctrl, 999 .enable = s5pc100_sclk0_ctrl,
@@ -1100,6 +1046,78 @@ static struct clksrc_clk clk_sclk_uart = {
1100 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 1046 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1101}; 1047};
1102 1048
1049static struct clksrc_clk clk_sclk_mmc0 = {
1050 .clk = {
1051 .name = "sclk_mmc",
1052 .devname = "s3c-sdhci.0",
1053 .ctrlbit = (1 << 12),
1054 .enable = s5pc100_sclk1_ctrl,
1055 },
1056 .sources = &clk_src_mmc0,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1059};
1060
1061static struct clksrc_clk clk_sclk_mmc1 = {
1062 .clk = {
1063 .name = "sclk_mmc",
1064 .devname = "s3c-sdhci.1",
1065 .ctrlbit = (1 << 13),
1066 .enable = s5pc100_sclk1_ctrl,
1067 },
1068 .sources = &clk_src_mmc12,
1069 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1070 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1071};
1072
1073static struct clksrc_clk clk_sclk_mmc2 = {
1074 .clk = {
1075 .name = "sclk_mmc",
1076 .devname = "s3c-sdhci.2",
1077 .ctrlbit = (1 << 14),
1078 .enable = s5pc100_sclk1_ctrl,
1079 },
1080 .sources = &clk_src_mmc12,
1081 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1083};
1084
1085static struct clksrc_clk clk_sclk_spi0 = {
1086 .clk = {
1087 .name = "sclk_spi",
1088 .devname = "s3c64xx-spi.0",
1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl,
1091 },
1092 .sources = &clk_src_group1,
1093 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1094 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1095};
1096
1097static struct clksrc_clk clk_sclk_spi1 = {
1098 .clk = {
1099 .name = "sclk_spi",
1100 .devname = "s3c64xx-spi.1",
1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl,
1103 },
1104 .sources = &clk_src_group1,
1105 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1106 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1107};
1108
1109static struct clksrc_clk clk_sclk_spi2 = {
1110 .clk = {
1111 .name = "sclk_spi",
1112 .devname = "s3c64xx-spi.2",
1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl,
1115 },
1116 .sources = &clk_src_group1,
1117 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1118 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1119};
1120
1103/* Clock initialisation code */ 1121/* Clock initialisation code */
1104static struct clksrc_clk *sysclks[] = { 1122static struct clksrc_clk *sysclks[] = {
1105 &clk_mout_apll, 1123 &clk_mout_apll,
@@ -1129,8 +1147,23 @@ static struct clksrc_clk *sysclks[] = {
1129 &clk_sclk_spdif, 1147 &clk_sclk_spdif,
1130}; 1148};
1131 1149
1150static struct clk *clk_cdev[] = {
1151 &clk_hsmmc0,
1152 &clk_hsmmc1,
1153 &clk_hsmmc2,
1154 &clk_48m_spi0,
1155 &clk_48m_spi1,
1156 &clk_48m_spi2,
1157};
1158
1132static struct clksrc_clk *clksrc_cdev[] = { 1159static struct clksrc_clk *clksrc_cdev[] = {
1133 &clk_sclk_uart, 1160 &clk_sclk_uart,
1161 &clk_sclk_mmc0,
1162 &clk_sclk_mmc1,
1163 &clk_sclk_mmc2,
1164 &clk_sclk_spi0,
1165 &clk_sclk_spi1,
1166 &clk_sclk_spi2,
1134}; 1167};
1135 1168
1136void __init_or_cpufreq s5pc100_setup_clocks(void) 1169void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1275,6 +1308,19 @@ static struct clk *clks[] __initdata = {
1275static struct clk_lookup s5pc100_clk_lookup[] = { 1308static struct clk_lookup s5pc100_clk_lookup[] = {
1276 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 1309 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1277 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), 1310 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1311 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1312 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1313 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1314 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1278}; 1324};
1279 1325
1280void __init s5pc100_register_clocks(void) 1326void __init s5pc100_register_clocks(void)
@@ -1295,6 +1341,10 @@ void __init s5pc100_register_clocks(void)
1295 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1341 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1296 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); 1342 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1297 1343
1344 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346 s3c_disable_clocks(clk_cdev[ptr], 1);
1347
1298 s3c24xx_register_clock(&dummy_apb_pclk); 1348 s3c24xx_register_clock(&dummy_apb_pclk);
1299 1349
1300 s3c_pwmclk_init(); 1350 s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index e5d6c4dceb56..000000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,227 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h>
23
24static char *spi_src_clks[] = {
25 [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
26 [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
27 [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
28};
29
30/* SPI Controller platform_devices */
31
32/* Since we emulate multi-cs capability, we do not touch the CS.
33 * The emulated CS is toggled by board specific mechanism, as it can
34 * be either some immediate GPIO or some signal out of some other
35 * chip in between ... or some yet another way.
36 * We simply do not assume anything about CS.
37 */
38static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
39{
40 switch (pdev->id) {
41 case 0:
42 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
43 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
44 break;
45
46 case 1:
47 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 break;
50
51 case 2:
52 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
53 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
54 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
55 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
56 break;
57
58 default:
59 dev_err(&pdev->dev, "Invalid SPI Controller number!");
60 return -EINVAL;
61 }
62
63 return 0;
64}
65
66static struct resource s5pc100_spi0_resource[] = {
67 [0] = {
68 .start = S5PC100_PA_SPI0,
69 .end = S5PC100_PA_SPI0 + 0x100 - 1,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = DMACH_SPI0_TX,
74 .end = DMACH_SPI0_TX,
75 .flags = IORESOURCE_DMA,
76 },
77 [2] = {
78 .start = DMACH_SPI0_RX,
79 .end = DMACH_SPI0_RX,
80 .flags = IORESOURCE_DMA,
81 },
82 [3] = {
83 .start = IRQ_SPI0,
84 .end = IRQ_SPI0,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
90 .cfg_gpio = s5pc100_spi_cfg_gpio,
91 .fifo_lvl_mask = 0x7f,
92 .rx_lvl_offset = 13,
93 .high_speed = 1,
94 .tx_st_done = 21,
95};
96
97static u64 spi_dmamask = DMA_BIT_MASK(32);
98
99struct platform_device s5pc100_device_spi0 = {
100 .name = "s3c64xx-spi",
101 .id = 0,
102 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
103 .resource = s5pc100_spi0_resource,
104 .dev = {
105 .dma_mask = &spi_dmamask,
106 .coherent_dma_mask = DMA_BIT_MASK(32),
107 .platform_data = &s5pc100_spi0_pdata,
108 },
109};
110
111static struct resource s5pc100_spi1_resource[] = {
112 [0] = {
113 .start = S5PC100_PA_SPI1,
114 .end = S5PC100_PA_SPI1 + 0x100 - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = DMACH_SPI1_TX,
119 .end = DMACH_SPI1_TX,
120 .flags = IORESOURCE_DMA,
121 },
122 [2] = {
123 .start = DMACH_SPI1_RX,
124 .end = DMACH_SPI1_RX,
125 .flags = IORESOURCE_DMA,
126 },
127 [3] = {
128 .start = IRQ_SPI1,
129 .end = IRQ_SPI1,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
135 .cfg_gpio = s5pc100_spi_cfg_gpio,
136 .fifo_lvl_mask = 0x7f,
137 .rx_lvl_offset = 13,
138 .high_speed = 1,
139 .tx_st_done = 21,
140};
141
142struct platform_device s5pc100_device_spi1 = {
143 .name = "s3c64xx-spi",
144 .id = 1,
145 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
146 .resource = s5pc100_spi1_resource,
147 .dev = {
148 .dma_mask = &spi_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 .platform_data = &s5pc100_spi1_pdata,
151 },
152};
153
154static struct resource s5pc100_spi2_resource[] = {
155 [0] = {
156 .start = S5PC100_PA_SPI2,
157 .end = S5PC100_PA_SPI2 + 0x100 - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = DMACH_SPI2_TX,
162 .end = DMACH_SPI2_TX,
163 .flags = IORESOURCE_DMA,
164 },
165 [2] = {
166 .start = DMACH_SPI2_RX,
167 .end = DMACH_SPI2_RX,
168 .flags = IORESOURCE_DMA,
169 },
170 [3] = {
171 .start = IRQ_SPI2,
172 .end = IRQ_SPI2,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
178 .cfg_gpio = s5pc100_spi_cfg_gpio,
179 .fifo_lvl_mask = 0x7f,
180 .rx_lvl_offset = 13,
181 .high_speed = 1,
182 .tx_st_done = 21,
183};
184
185struct platform_device s5pc100_device_spi2 = {
186 .name = "s3c64xx-spi",
187 .id = 2,
188 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
189 .resource = s5pc100_spi2_resource,
190 .dev = {
191 .dma_mask = &spi_dmamask,
192 .coherent_dma_mask = DMA_BIT_MASK(32),
193 .platform_data = &s5pc100_spi2_pdata,
194 },
195};
196
197void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
198{
199 struct s3c64xx_spi_info *pd;
200
201 /* Reject invalid configuration */
202 if (!num_cs || src_clk_nr < 0
203 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
204 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
205 return;
206 }
207
208 switch (cntrlr) {
209 case 0:
210 pd = &s5pc100_spi0_pdata;
211 break;
212 case 1:
213 pd = &s5pc100_spi1_pdata;
214 break;
215 case 2:
216 pd = &s5pc100_spi2_pdata;
217 break;
218 default:
219 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
220 __func__, cntrlr);
221 return;
222 }
223
224 pd->num_cs = num_cs;
225 pd->src_clk_nr = src_clk_nr;
226 pd->src_clk_name = spi_src_clks[src_clk_nr];
227}
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b767f7d..54bc4f82e17a 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG 102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
103#define S3C_PA_SPI0 S5PC100_PA_SPI0
104#define S3C_PA_SPI1 S5PC100_PA_SPI1
105#define S3C_PA_SPI2 S5PC100_PA_SPI2
103 106
104#define S5P_PA_CHIPID S5PC100_PA_CHIPID 107#define S5P_PA_CHIPID S5PC100_PA_CHIPID
105#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 108#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e8a7b7..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
2 *
3 * Copyright 2008 Samsung Electronics
4 *
5 * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
6 *
7 * Based on mach-s3c6410/setup-sdhci.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/types.h>
15
16/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
17
18char *s5pc100_hsmmc_clksrcs[4] = {
19 [0] = "hsmmc", /* HCLK */
20 /* [1] = "hsmmc", - duplicate HCLK entry */
21 [2] = "sclk_mmc", /* mmc_bus */
22 /* [3] = "48m", - note not successfully used yet */
23};
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644
index 000000000000..431a6f747caa
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-s5pc100/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .high_speed = 1,
22 .tx_st_done = 21,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
29 return 0;
30}
31#endif
32
33#ifdef CONFIG_S3C64XX_DEV_SPI1
34struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
35 .fifo_lvl_mask = 0x7f,
36 .rx_lvl_offset = 13,
37 .high_speed = 1,
38 .tx_st_done = 21,
39};
40
41int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
42{
43 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
44 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
45 return 0;
46}
47#endif
48
49#ifdef CONFIG_S3C64XX_DEV_SPI2
50struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
51 .fifo_lvl_mask = 0x7f,
52 .rx_lvl_offset = 13,
53 .high_speed = 1,
54 .tx_st_done = 21,
55};
56
57int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
58{
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
61 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
62 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
63 return 0;
64}
65#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 646057ab2e4c..2cdc42e838b8 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC
60 help 60 help
61 Common setup code for the camera interfaces. 61 Common setup code for the camera interfaces.
62 62
63config S5PV210_SETUP_SPI
64 bool
65 help
66 Common setup code for SPI GPIO configurations.
67
63menu "S5PC110 Machines" 68menu "S5PC110 Machines"
64 69
65config MACH_AQUILA 70config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 4c59186de957..76a121dd52b4 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
29# device support 29# device support
30 30
31obj-y += dev-audio.o 31obj-y += dev-audio.o
32obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
33 32
34obj-y += setup-i2c0.o 33obj-y += setup-i2c0.o
35obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 34obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
@@ -38,5 +37,5 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
38obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o 37obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
39obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o 38obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
40obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o 39obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
41obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o
42obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 40obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
41obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index d8df66887060..c78dfddd77fd 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -400,30 +400,6 @@ static struct clk init_clocks_off[] = {
400 .enable = s5pv210_clk_ip1_ctrl, 400 .enable = s5pv210_clk_ip1_ctrl,
401 .ctrlbit = (1<<25), 401 .ctrlbit = (1<<25),
402 }, { 402 }, {
403 .name = "hsmmc",
404 .devname = "s3c-sdhci.0",
405 .parent = &clk_hclk_psys.clk,
406 .enable = s5pv210_clk_ip2_ctrl,
407 .ctrlbit = (1<<16),
408 }, {
409 .name = "hsmmc",
410 .devname = "s3c-sdhci.1",
411 .parent = &clk_hclk_psys.clk,
412 .enable = s5pv210_clk_ip2_ctrl,
413 .ctrlbit = (1<<17),
414 }, {
415 .name = "hsmmc",
416 .devname = "s3c-sdhci.2",
417 .parent = &clk_hclk_psys.clk,
418 .enable = s5pv210_clk_ip2_ctrl,
419 .ctrlbit = (1<<18),
420 }, {
421 .name = "hsmmc",
422 .devname = "s3c-sdhci.3",
423 .parent = &clk_hclk_psys.clk,
424 .enable = s5pv210_clk_ip2_ctrl,
425 .ctrlbit = (1<<19),
426 }, {
427 .name = "systimer", 403 .name = "systimer",
428 .parent = &clk_pclk_psys.clk, 404 .parent = &clk_pclk_psys.clk,
429 .enable = s5pv210_clk_ip3_ctrl, 405 .enable = s5pv210_clk_ip3_ctrl,
@@ -560,6 +536,38 @@ static struct clk init_clocks[] = {
560 }, 536 },
561}; 537};
562 538
539static struct clk clk_hsmmc0 = {
540 .name = "hsmmc",
541 .devname = "s3c-sdhci.0",
542 .parent = &clk_hclk_psys.clk,
543 .enable = s5pv210_clk_ip2_ctrl,
544 .ctrlbit = (1<<16),
545};
546
547static struct clk clk_hsmmc1 = {
548 .name = "hsmmc",
549 .devname = "s3c-sdhci.1",
550 .parent = &clk_hclk_psys.clk,
551 .enable = s5pv210_clk_ip2_ctrl,
552 .ctrlbit = (1<<17),
553};
554
555static struct clk clk_hsmmc2 = {
556 .name = "hsmmc",
557 .devname = "s3c-sdhci.2",
558 .parent = &clk_hclk_psys.clk,
559 .enable = s5pv210_clk_ip2_ctrl,
560 .ctrlbit = (1<<18),
561};
562
563static struct clk clk_hsmmc3 = {
564 .name = "hsmmc",
565 .devname = "s3c-sdhci.3",
566 .parent = &clk_hclk_psys.clk,
567 .enable = s5pv210_clk_ip2_ctrl,
568 .ctrlbit = (1<<19),
569};
570
563static struct clk *clkset_uart_list[] = { 571static struct clk *clkset_uart_list[] = {
564 [6] = &clk_mout_mpll.clk, 572 [6] = &clk_mout_mpll.clk,
565 [7] = &clk_mout_epll.clk, 573 [7] = &clk_mout_epll.clk,
@@ -867,46 +875,6 @@ static struct clksrc_clk clksrcs[] = {
867 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 875 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
868 }, { 876 }, {
869 .clk = { 877 .clk = {
870 .name = "sclk_mmc",
871 .devname = "s3c-sdhci.0",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 8),
874 },
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
878 }, {
879 .clk = {
880 .name = "sclk_mmc",
881 .devname = "s3c-sdhci.1",
882 .enable = s5pv210_clk_mask0_ctrl,
883 .ctrlbit = (1 << 9),
884 },
885 .sources = &clkset_group2,
886 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
887 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
888 }, {
889 .clk = {
890 .name = "sclk_mmc",
891 .devname = "s3c-sdhci.2",
892 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 10),
894 },
895 .sources = &clkset_group2,
896 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
897 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
898 }, {
899 .clk = {
900 .name = "sclk_mmc",
901 .devname = "s3c-sdhci.3",
902 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 11),
904 },
905 .sources = &clkset_group2,
906 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
907 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
908 }, {
909 .clk = {
910 .name = "sclk_mfc", 878 .name = "sclk_mfc",
911 .devname = "s5p-mfc", 879 .devname = "s5p-mfc",
912 .enable = s5pv210_clk_ip0_ctrl, 880 .enable = s5pv210_clk_ip0_ctrl,
@@ -944,26 +912,6 @@ static struct clksrc_clk clksrcs[] = {
944 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 912 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
945 }, { 913 }, {
946 .clk = { 914 .clk = {
947 .name = "sclk_spi",
948 .devname = "s3c64xx-spi.0",
949 .enable = s5pv210_clk_mask0_ctrl,
950 .ctrlbit = (1 << 16),
951 },
952 .sources = &clkset_group2,
953 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
954 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
955 }, {
956 .clk = {
957 .name = "sclk_spi",
958 .devname = "s3c64xx-spi.1",
959 .enable = s5pv210_clk_mask0_ctrl,
960 .ctrlbit = (1 << 17),
961 },
962 .sources = &clkset_group2,
963 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
964 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
965 }, {
966 .clk = {
967 .name = "sclk_pwi", 915 .name = "sclk_pwi",
968 .enable = s5pv210_clk_mask0_ctrl, 916 .enable = s5pv210_clk_mask0_ctrl,
969 .ctrlbit = (1 << 29), 917 .ctrlbit = (1 << 29),
@@ -1031,11 +979,97 @@ static struct clksrc_clk clk_sclk_uart3 = {
1031 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, 979 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1032}; 980};
1033 981
982static struct clksrc_clk clk_sclk_mmc0 = {
983 .clk = {
984 .name = "sclk_mmc",
985 .devname = "s3c-sdhci.0",
986 .enable = s5pv210_clk_mask0_ctrl,
987 .ctrlbit = (1 << 8),
988 },
989 .sources = &clkset_group2,
990 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
991 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
992};
993
994static struct clksrc_clk clk_sclk_mmc1 = {
995 .clk = {
996 .name = "sclk_mmc",
997 .devname = "s3c-sdhci.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 9),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1004};
1005
1006static struct clksrc_clk clk_sclk_mmc2 = {
1007 .clk = {
1008 .name = "sclk_mmc",
1009 .devname = "s3c-sdhci.2",
1010 .enable = s5pv210_clk_mask0_ctrl,
1011 .ctrlbit = (1 << 10),
1012 },
1013 .sources = &clkset_group2,
1014 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1015 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1016};
1017
1018static struct clksrc_clk clk_sclk_mmc3 = {
1019 .clk = {
1020 .name = "sclk_mmc",
1021 .devname = "s3c-sdhci.3",
1022 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 11),
1024 },
1025 .sources = &clkset_group2,
1026 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1027 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1028};
1029
1030static struct clksrc_clk clk_sclk_spi0 = {
1031 .clk = {
1032 .name = "sclk_spi",
1033 .devname = "s3c64xx-spi.0",
1034 .enable = s5pv210_clk_mask0_ctrl,
1035 .ctrlbit = (1 << 16),
1036 },
1037 .sources = &clkset_group2,
1038 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1039 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1040 };
1041
1042static struct clksrc_clk clk_sclk_spi1 = {
1043 .clk = {
1044 .name = "sclk_spi",
1045 .devname = "s3c64xx-spi.1",
1046 .enable = s5pv210_clk_mask0_ctrl,
1047 .ctrlbit = (1 << 17),
1048 },
1049 .sources = &clkset_group2,
1050 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1051 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1052 };
1053
1054
1034static struct clksrc_clk *clksrc_cdev[] = { 1055static struct clksrc_clk *clksrc_cdev[] = {
1035 &clk_sclk_uart0, 1056 &clk_sclk_uart0,
1036 &clk_sclk_uart1, 1057 &clk_sclk_uart1,
1037 &clk_sclk_uart2, 1058 &clk_sclk_uart2,
1038 &clk_sclk_uart3, 1059 &clk_sclk_uart3,
1060 &clk_sclk_mmc0,
1061 &clk_sclk_mmc1,
1062 &clk_sclk_mmc2,
1063 &clk_sclk_mmc3,
1064 &clk_sclk_spi0,
1065 &clk_sclk_spi1,
1066};
1067
1068static struct clk *clk_cdev[] = {
1069 &clk_hsmmc0,
1070 &clk_hsmmc1,
1071 &clk_hsmmc2,
1072 &clk_hsmmc3,
1039}; 1073};
1040 1074
1041/* Clock initialisation code */ 1075/* Clock initialisation code */
@@ -1283,6 +1317,17 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1283 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), 1317 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1284 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), 1318 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1285 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), 1319 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1328 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1329 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1330 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1286}; 1331};
1287 1332
1288void __init s5pv210_register_clocks(void) 1333void __init s5pv210_register_clocks(void)
@@ -1307,6 +1352,10 @@ void __init s5pv210_register_clocks(void)
1307 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1352 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1308 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); 1353 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1309 1354
1355 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1356 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1357 s3c_disable_clocks(clk_cdev[ptr], 1);
1358
1310 s3c24xx_register_clock(&dummy_apb_pclk); 1359 s3c24xx_register_clock(&dummy_apb_pclk);
1311 s3c_pwmclk_init(); 1360 s3c_pwmclk_init();
1312} 1361}
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index eaf9a7bff7a0..000000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
25 [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
37{
38 unsigned int base;
39
40 switch (pdev->id) {
41 case 0:
42 base = S5PV210_GPB(0);
43 break;
44
45 case 1:
46 base = S5PV210_GPB(4);
47 break;
48
49 default:
50 dev_err(&pdev->dev, "Invalid SPI Controller number!");
51 return -EINVAL;
52 }
53
54 s3c_gpio_cfgall_range(base, 3,
55 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
56
57 return 0;
58}
59
60static struct resource s5pv210_spi0_resource[] = {
61 [0] = {
62 .start = S5PV210_PA_SPI0,
63 .end = S5PV210_PA_SPI0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_SPI0_TX,
68 .end = DMACH_SPI0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_SPI0_RX,
73 .end = DMACH_SPI0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = IRQ_SPI0,
78 .end = IRQ_SPI0,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
84 .cfg_gpio = s5pv210_spi_cfg_gpio,
85 .fifo_lvl_mask = 0x1ff,
86 .rx_lvl_offset = 15,
87 .high_speed = 1,
88 .tx_st_done = 25,
89};
90
91static u64 spi_dmamask = DMA_BIT_MASK(32);
92
93struct platform_device s5pv210_device_spi0 = {
94 .name = "s3c64xx-spi",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(s5pv210_spi0_resource),
97 .resource = s5pv210_spi0_resource,
98 .dev = {
99 .dma_mask = &spi_dmamask,
100 .coherent_dma_mask = DMA_BIT_MASK(32),
101 .platform_data = &s5pv210_spi0_pdata,
102 },
103};
104
105static struct resource s5pv210_spi1_resource[] = {
106 [0] = {
107 .start = S5PV210_PA_SPI1,
108 .end = S5PV210_PA_SPI1 + 0x100 - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = DMACH_SPI1_TX,
113 .end = DMACH_SPI1_TX,
114 .flags = IORESOURCE_DMA,
115 },
116 [2] = {
117 .start = DMACH_SPI1_RX,
118 .end = DMACH_SPI1_RX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = IRQ_SPI1,
123 .end = IRQ_SPI1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
129 .cfg_gpio = s5pv210_spi_cfg_gpio,
130 .fifo_lvl_mask = 0x7f,
131 .rx_lvl_offset = 15,
132 .high_speed = 1,
133 .tx_st_done = 25,
134};
135
136struct platform_device s5pv210_device_spi1 = {
137 .name = "s3c64xx-spi",
138 .id = 1,
139 .num_resources = ARRAY_SIZE(s5pv210_spi1_resource),
140 .resource = s5pv210_spi1_resource,
141 .dev = {
142 .dma_mask = &spi_dmamask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = &s5pv210_spi1_pdata,
145 },
146};
147
148void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
149{
150 struct s3c64xx_spi_info *pd;
151
152 /* Reject invalid configuration */
153 if (!num_cs || src_clk_nr < 0
154 || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
155 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
156 return;
157 }
158
159 switch (cntrlr) {
160 case 0:
161 pd = &s5pv210_spi0_pdata;
162 break;
163 case 1:
164 pd = &s5pv210_spi1_pdata;
165 break;
166 default:
167 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
168 __func__, cntrlr);
169 return;
170 }
171
172 pd->num_cs = num_cs;
173 pd->src_clk_nr = src_clk_nr;
174 pd->src_clk_name = spi_src_clks[src_clk_nr];
175}
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 7ff609f1568b..89c34b8f73bf 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -109,6 +109,8 @@
109#define S3C_PA_RTC S5PV210_PA_RTC 109#define S3C_PA_RTC S5PV210_PA_RTC
110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG 110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
111#define S3C_PA_WDT S5PV210_PA_WATCHDOG 111#define S3C_PA_WDT S5PV210_PA_WATCHDOG
112#define S3C_PA_SPI0 S5PV210_PA_SPI0
113#define S3C_PA_SPI1 S5PV210_PA_SPI1
112 114
113#define S5P_PA_CHIPID S5PV210_PA_CHIPID 115#define S5P_PA_CHIPID S5PV210_PA_CHIPID
114#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 116#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 6f7dfe993c12..5e734d025a6a 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -597,8 +597,7 @@ static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
597 597
598static void aquila_setup_sdhci(void) 598static void aquila_setup_sdhci(void)
599{ 599{
600 gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN"); 600 gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
601 gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
602 601
603 s3c_sdhci0_set_platdata(&aquila_hsmmc0_data); 602 s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
604 s3c_sdhci1_set_platdata(&aquila_hsmmc1_data); 603 s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 12c693717398..ff9152610439 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -229,8 +229,7 @@ static void __init goni_radio_init(void)
229 i2c1_devs[0].irq = gpio_to_irq(gpio); 229 i2c1_devs[0].irq = gpio_to_irq(gpio);
230 230
231 gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */ 231 gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
232 gpio_request(gpio, "FM_RST"); 232 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
233 gpio_direction_output(gpio, 1);
234} 233}
235 234
236/* TSP */ 235/* TSP */
@@ -266,8 +265,7 @@ static void __init goni_tsp_init(void)
266 int gpio; 265 int gpio;
267 266
268 gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */ 267 gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
269 gpio_request(gpio, "TSP_LDO_ON"); 268 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
270 gpio_direction_output(gpio, 1);
271 gpio_export(gpio, 0); 269 gpio_export(gpio, 0);
272 270
273 gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */ 271 gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index b4021dd802a8..dff9ea7b5bba 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -155,15 +155,12 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
155{ 155{
156 if (power) { 156 if (power) {
157#if !defined(CONFIG_BACKLIGHT_PWM) 157#if !defined(CONFIG_BACKLIGHT_PWM)
158 gpio_request(S5PV210_GPD0(3), "GPD0"); 158 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
159 gpio_direction_output(S5PV210_GPD0(3), 1);
160 gpio_free(S5PV210_GPD0(3)); 159 gpio_free(S5PV210_GPD0(3));
161#endif 160#endif
162 161
163 /* fire nRESET on power up */ 162 /* fire nRESET on power up */
164 gpio_request(S5PV210_GPH0(6), "GPH0"); 163 gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
165
166 gpio_direction_output(S5PV210_GPH0(6), 1);
167 164
168 gpio_set_value(S5PV210_GPH0(6), 0); 165 gpio_set_value(S5PV210_GPH0(6), 0);
169 mdelay(10); 166 mdelay(10);
@@ -174,8 +171,7 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
174 gpio_free(S5PV210_GPH0(6)); 171 gpio_free(S5PV210_GPH0(6));
175 } else { 172 } else {
176#if !defined(CONFIG_BACKLIGHT_PWM) 173#if !defined(CONFIG_BACKLIGHT_PWM)
177 gpio_request(S5PV210_GPD0(3), "GPD0"); 174 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
178 gpio_direction_output(S5PV210_GPD0(3), 0);
179 gpio_free(S5PV210_GPD0(3)); 175 gpio_free(S5PV210_GPD0(3));
180#endif 176#endif
181 } 177 }
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4d35fd..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *s5pv210_hsmmc_clksrcs[4] = {
18 [0] = "hsmmc", /* HCLK */
19 /* [1] = "hsmmc", - duplicate HCLK entry */
20 [2] = "sclk_mmc", /* mmc_bus */
21 /* [3] = NULL, - reserved */
22};
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
new file mode 100644
index 000000000000..f43c5048a37d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -0,0 +1,51 @@
1/* linux/arch/arm/mach-s5pv210/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .tx_st_done = 25,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
28 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
29 s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 return 0;
32}
33#endif
34
35#ifdef CONFIG_S3C64XX_DEV_SPI1
36struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
37 .fifo_lvl_mask = 0x7f,
38 .rx_lvl_offset = 15,
39 .high_speed = 1,
40 .tx_st_done = 25,
41};
42
43int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
44{
45 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
47 s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 return 0;
50}
51#endif
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 53754bcf15a7..9fe35348e03b 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1437,11 +1437,10 @@ int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1437 size_t map_sz = sizeof(*nmap) * sel->map_size; 1437 size_t map_sz = sizeof(*nmap) * sel->map_size;
1438 int ptr; 1438 int ptr;
1439 1439
1440 nmap = kmalloc(map_sz, GFP_KERNEL); 1440 nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
1441 if (nmap == NULL) 1441 if (nmap == NULL)
1442 return -ENOMEM; 1442 return -ENOMEM;
1443 1443
1444 memcpy(nmap, sel->map, map_sz);
1445 memcpy(&dma_sel, sel, sizeof(*sel)); 1444 memcpy(&dma_sel, sel, sizeof(*sel));
1446 1445
1447 dma_sel.map = nmap; 1446 dma_sel.map = nmap;
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4eab2cca2d92..95e68190d593 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -427,12 +427,6 @@ static struct clk init_clocks[] = {
427 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_h,
433 .enable = s3c2443_clkcon_enable_h,
434 .ctrlbit = S3C2443_HCLKCON_HSMMC,
435 }, {
436 .name = "gpio", 430 .name = "gpio",
437 .parent = &clk_p, 431 .parent = &clk_p,
438 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -514,6 +508,14 @@ static struct clk init_clocks[] = {
514 } 508 }
515}; 509};
516 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
517static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
518{ 520{
519 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -579,6 +581,7 @@ static struct clk *clks[] __initdata = {
579 &clk_epll, 581 &clk_epll,
580 &clk_usb_bus, 582 &clk_usb_bus,
581 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
582}; 585};
583 586
584static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -595,6 +598,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
595 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), 598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
596 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
597 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
598}; 602};
599 603
600void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 313eb26cfa62..160eea15a6ef 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -226,11 +226,23 @@ config SAMSUNG_DEV_IDE
226 help 226 help
227 Compile in platform device definitions for IDE 227 Compile in platform device definitions for IDE
228 228
229config S3C64XX_DEV_SPI 229config S3C64XX_DEV_SPI0
230 bool 230 bool
231 help 231 help
232 Compile in platform device definitions for S3C64XX's type 232 Compile in platform device definitions for S3C64XX's type
233 SPI controllers. 233 SPI controller 0
234
235config S3C64XX_DEV_SPI1
236 bool
237 help
238 Compile in platform device definitions for S3C64XX's type
239 SPI controller 1
240
241config S3C64XX_DEV_SPI2
242 bool
243 help
244 Compile in platform device definitions for S3C64XX's type
245 SPI controller 2
234 246
235config SAMSUNG_DEV_TS 247config SAMSUNG_DEV_TS
236 bool 248 bool
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 92b4c025d37a..32a6e394db24 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -62,6 +62,7 @@
62#include <plat/regs-iic.h> 62#include <plat/regs-iic.h>
63#include <plat/regs-serial.h> 63#include <plat/regs-serial.h>
64#include <plat/regs-spi.h> 64#include <plat/regs-spi.h>
65#include <plat/s3c64xx-spi.h>
65 66
66static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 67static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
67 68
@@ -1462,3 +1463,129 @@ struct platform_device s3c_device_wdt = {
1462 .resource = s3c_wdt_resource, 1463 .resource = s3c_wdt_resource,
1463}; 1464};
1464#endif /* CONFIG_S3C_DEV_WDT */ 1465#endif /* CONFIG_S3C_DEV_WDT */
1466
1467#ifdef CONFIG_S3C64XX_DEV_SPI0
1468static struct resource s3c64xx_spi0_resource[] = {
1469 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1470 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1471 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1472 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1473};
1474
1475struct platform_device s3c64xx_device_spi0 = {
1476 .name = "s3c64xx-spi",
1477 .id = 0,
1478 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1479 .resource = s3c64xx_spi0_resource,
1480 .dev = {
1481 .dma_mask = &samsung_device_dma_mask,
1482 .coherent_dma_mask = DMA_BIT_MASK(32),
1483 },
1484};
1485
1486void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1487 int src_clk_nr, int num_cs)
1488{
1489 if (!pd) {
1490 pr_err("%s:Need to pass platform data\n", __func__);
1491 return;
1492 }
1493
1494 /* Reject invalid configuration */
1495 if (!num_cs || src_clk_nr < 0) {
1496 pr_err("%s: Invalid SPI configuration\n", __func__);
1497 return;
1498 }
1499
1500 pd->num_cs = num_cs;
1501 pd->src_clk_nr = src_clk_nr;
1502 if (!pd->cfg_gpio)
1503 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1504
1505 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1506}
1507#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1508
1509#ifdef CONFIG_S3C64XX_DEV_SPI1
1510static struct resource s3c64xx_spi1_resource[] = {
1511 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1512 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1513 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1514 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1515};
1516
1517struct platform_device s3c64xx_device_spi1 = {
1518 .name = "s3c64xx-spi",
1519 .id = 1,
1520 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1521 .resource = s3c64xx_spi1_resource,
1522 .dev = {
1523 .dma_mask = &samsung_device_dma_mask,
1524 .coherent_dma_mask = DMA_BIT_MASK(32),
1525 },
1526};
1527
1528void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1529 int src_clk_nr, int num_cs)
1530{
1531 if (!pd) {
1532 pr_err("%s:Need to pass platform data\n", __func__);
1533 return;
1534 }
1535
1536 /* Reject invalid configuration */
1537 if (!num_cs || src_clk_nr < 0) {
1538 pr_err("%s: Invalid SPI configuration\n", __func__);
1539 return;
1540 }
1541
1542 pd->num_cs = num_cs;
1543 pd->src_clk_nr = src_clk_nr;
1544 if (!pd->cfg_gpio)
1545 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1546
1547 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1548}
1549#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1550
1551#ifdef CONFIG_S3C64XX_DEV_SPI2
1552static struct resource s3c64xx_spi2_resource[] = {
1553 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1554 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1555 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1556 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1557};
1558
1559struct platform_device s3c64xx_device_spi2 = {
1560 .name = "s3c64xx-spi",
1561 .id = 2,
1562 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1563 .resource = s3c64xx_spi2_resource,
1564 .dev = {
1565 .dma_mask = &samsung_device_dma_mask,
1566 .coherent_dma_mask = DMA_BIT_MASK(32),
1567 },
1568};
1569
1570void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1571 int src_clk_nr, int num_cs)
1572{
1573 if (!pd) {
1574 pr_err("%s:Need to pass platform data\n", __func__);
1575 return;
1576 }
1577
1578 /* Reject invalid configuration */
1579 if (!num_cs || src_clk_nr < 0) {
1580 pr_err("%s: Invalid SPI configuration\n", __func__);
1581 return;
1582 }
1583
1584 pd->num_cs = num_cs;
1585 pd->src_clk_nr = src_clk_nr;
1586 if (!pd->cfg_gpio)
1587 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1588
1589 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1590}
1591#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ab633c9c2aec..83b1e31696d9 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0;
39extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0; 40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1; 41extern struct platform_device s3c64xx_device_spi1;
42extern struct platform_device s3c64xx_device_spi2;
42 43
43extern struct platform_device s3c_device_adc; 44extern struct platform_device s3c_device_adc;
44extern struct platform_device s3c_device_cfcon; 45extern struct platform_device s3c_device_cfcon;
@@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1;
98extern struct platform_device s5p6450_device_iis2; 99extern struct platform_device s5p6450_device_iis2;
99extern struct platform_device s5p6450_device_pcm0; 100extern struct platform_device s5p6450_device_pcm0;
100 101
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103 102
104extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
105extern struct platform_device s5pc100_device_iis0; 104extern struct platform_device s5pc100_device_iis0;
@@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0; 107extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1; 108extern struct platform_device s5pc100_device_pcm1;
110extern struct platform_device s5pc100_device_spdif; 109extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
114 110
115extern struct platform_device s5pv210_device_ac97; 111extern struct platform_device s5pv210_device_ac97;
116extern struct platform_device s5pv210_device_iis0; 112extern struct platform_device s5pv210_device_iis0;
@@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0;
120extern struct platform_device s5pv210_device_pcm1; 116extern struct platform_device s5pv210_device_pcm1;
121extern struct platform_device s5pv210_device_pcm2; 117extern struct platform_device s5pv210_device_pcm2;
122extern struct platform_device s5pv210_device_spdif; 118extern struct platform_device s5pv210_device_spdif;
123extern struct platform_device s5pv210_device_spi0;
124extern struct platform_device s5pv210_device_spi1;
125 119
126extern struct platform_device exynos4_device_ac97; 120extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci; 121extern struct platform_device exynos4_device_ahci;
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621bb..aea68b60ef98 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
31/** 31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
35 * @clk_from_cmu: If the SPI clock/prescalar control block is present 34 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller. 35 * by the platform's clock-management-unit and not in SPI controller.
37 * @num_cs: Number of CS this controller emulates. 36 * @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
43 */ 42 */
44struct s3c64xx_spi_info { 43struct s3c64xx_spi_info {
45 int src_clk_nr; 44 int src_clk_nr;
46 char *src_clk_name;
47 bool clk_from_cmu; 45 bool clk_from_cmu;
48 46
49 int num_cs; 47 int num_cs;
@@ -58,18 +56,28 @@ struct s3c64xx_spi_info {
58}; 56};
59 57
60/** 58/**
61 * s3c64xx_spi_set_info - SPI Controller configure callback by the board 59 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
62 * initialization code. 60 * initialization code.
63 * @cntrlr: SPI controller number the configuration is for. 61 * @pd: SPI platform data to set.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 62 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array. 63 * @num_cs: Number of elements in the 'cs' array.
66 * 64 *
67 * Call this from machine init code for each SPI Controller that 65 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it. 66 * has some chips attached to it.
69 */ 67 */
70extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69 int src_clk_nr, int num_cs);
72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71 int src_clk_nr, int num_cs);
72extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
73 int src_clk_nr, int num_cs);
74 74
75/* defined by architecture to configure gpio */
76extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
77extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
78extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
79
80extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
81extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
82extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
75#endif /* __S3C64XX_PLAT_SPI_H */ 83#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c752e919..dcff7dd1ae8a 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -66,8 +66,6 @@ struct s3c_sdhci_platdata {
66 enum cd_types cd_type; 66 enum cd_types cd_type;
67 enum clk_types clk_type; 67 enum clk_types clk_type;
68 68
69 char **clocks; /* set of clock sources */
70
71 int ext_cd_gpio; 69 int ext_cd_gpio;
72 bool ext_cd_gpio_invert; 70 bool ext_cd_gpio_invert;
73 int (*ext_cd_init)(void (*notify_func)(struct platform_device *, 71 int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
129/* S3C2416 SDHCI setup */ 127/* S3C2416 SDHCI setup */
130 128
131#ifdef CONFIG_S3C2416_SETUP_SDHCI 129#ifdef CONFIG_S3C2416_SETUP_SDHCI
132extern char *s3c2416_hsmmc_clksrcs[4];
133
134static inline void s3c2416_default_sdhci0(void) 130static inline void s3c2416_default_sdhci0(void)
135{ 131{
136#ifdef CONFIG_S3C_DEV_HSMMC 132#ifdef CONFIG_S3C_DEV_HSMMC
137 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
138 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; 133 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
139#endif /* CONFIG_S3C_DEV_HSMMC */ 134#endif /* CONFIG_S3C_DEV_HSMMC */
140} 135}
@@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void)
142static inline void s3c2416_default_sdhci1(void) 137static inline void s3c2416_default_sdhci1(void)
143{ 138{
144#ifdef CONFIG_S3C_DEV_HSMMC1 139#ifdef CONFIG_S3C_DEV_HSMMC1
145 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
146 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; 140 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
147#endif /* CONFIG_S3C_DEV_HSMMC1 */ 141#endif /* CONFIG_S3C_DEV_HSMMC1 */
148} 142}
@@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { }
155/* S3C64XX SDHCI setup */ 149/* S3C64XX SDHCI setup */
156 150
157#ifdef CONFIG_S3C64XX_SETUP_SDHCI 151#ifdef CONFIG_S3C64XX_SETUP_SDHCI
158extern char *s3c64xx_hsmmc_clksrcs[4];
159
160static inline void s3c6400_default_sdhci0(void) 152static inline void s3c6400_default_sdhci0(void)
161{ 153{
162#ifdef CONFIG_S3C_DEV_HSMMC 154#ifdef CONFIG_S3C_DEV_HSMMC
163 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
164 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 155 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
165#endif 156#endif
166} 157}
@@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void)
168static inline void s3c6400_default_sdhci1(void) 159static inline void s3c6400_default_sdhci1(void)
169{ 160{
170#ifdef CONFIG_S3C_DEV_HSMMC1 161#ifdef CONFIG_S3C_DEV_HSMMC1
171 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
172 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 162 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
173#endif 163#endif
174} 164}
@@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void)
176static inline void s3c6400_default_sdhci2(void) 166static inline void s3c6400_default_sdhci2(void)
177{ 167{
178#ifdef CONFIG_S3C_DEV_HSMMC2 168#ifdef CONFIG_S3C_DEV_HSMMC2
179 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
180 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 169 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
181#endif 170#endif
182} 171}
@@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void)
184static inline void s3c6410_default_sdhci0(void) 173static inline void s3c6410_default_sdhci0(void)
185{ 174{
186#ifdef CONFIG_S3C_DEV_HSMMC 175#ifdef CONFIG_S3C_DEV_HSMMC
187 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
188 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 176 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
189#endif 177#endif
190} 178}
@@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void)
192static inline void s3c6410_default_sdhci1(void) 180static inline void s3c6410_default_sdhci1(void)
193{ 181{
194#ifdef CONFIG_S3C_DEV_HSMMC1 182#ifdef CONFIG_S3C_DEV_HSMMC1
195 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
196 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 183 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
197#endif 184#endif
198} 185}
@@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void)
200static inline void s3c6410_default_sdhci2(void) 187static inline void s3c6410_default_sdhci2(void)
201{ 188{
202#ifdef CONFIG_S3C_DEV_HSMMC2 189#ifdef CONFIG_S3C_DEV_HSMMC2
203 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
204 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 190 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
205#endif 191#endif
206} 192}
@@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { }
218/* S5PC100 SDHCI setup */ 204/* S5PC100 SDHCI setup */
219 205
220#ifdef CONFIG_S5PC100_SETUP_SDHCI 206#ifdef CONFIG_S5PC100_SETUP_SDHCI
221extern char *s5pc100_hsmmc_clksrcs[4];
222
223static inline void s5pc100_default_sdhci0(void) 207static inline void s5pc100_default_sdhci0(void)
224{ 208{
225#ifdef CONFIG_S3C_DEV_HSMMC 209#ifdef CONFIG_S3C_DEV_HSMMC
226 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
227 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; 210 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
228#endif 211#endif
229} 212}
@@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void)
231static inline void s5pc100_default_sdhci1(void) 214static inline void s5pc100_default_sdhci1(void)
232{ 215{
233#ifdef CONFIG_S3C_DEV_HSMMC1 216#ifdef CONFIG_S3C_DEV_HSMMC1
234 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
235 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; 217 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
236#endif 218#endif
237} 219}
@@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void)
239static inline void s5pc100_default_sdhci2(void) 221static inline void s5pc100_default_sdhci2(void)
240{ 222{
241#ifdef CONFIG_S3C_DEV_HSMMC2 223#ifdef CONFIG_S3C_DEV_HSMMC2
242 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
243 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; 224 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
244#endif 225#endif
245} 226}
@@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { }
254/* S5PV210 SDHCI setup */ 235/* S5PV210 SDHCI setup */
255 236
256#ifdef CONFIG_S5PV210_SETUP_SDHCI 237#ifdef CONFIG_S5PV210_SETUP_SDHCI
257extern char *s5pv210_hsmmc_clksrcs[4];
258
259static inline void s5pv210_default_sdhci0(void) 238static inline void s5pv210_default_sdhci0(void)
260{ 239{
261#ifdef CONFIG_S3C_DEV_HSMMC 240#ifdef CONFIG_S3C_DEV_HSMMC
262 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; 241 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
264#endif 242#endif
265} 243}
@@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void)
267static inline void s5pv210_default_sdhci1(void) 245static inline void s5pv210_default_sdhci1(void)
268{ 246{
269#ifdef CONFIG_S3C_DEV_HSMMC1 247#ifdef CONFIG_S3C_DEV_HSMMC1
270 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
271 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; 248 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
272#endif 249#endif
273} 250}
@@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void)
275static inline void s5pv210_default_sdhci2(void) 252static inline void s5pv210_default_sdhci2(void)
276{ 253{
277#ifdef CONFIG_S3C_DEV_HSMMC2 254#ifdef CONFIG_S3C_DEV_HSMMC2
278 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
279 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; 255 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
280#endif 256#endif
281} 257}
@@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void)
283static inline void s5pv210_default_sdhci3(void) 259static inline void s5pv210_default_sdhci3(void)
284{ 260{
285#ifdef CONFIG_S3C_DEV_HSMMC3 261#ifdef CONFIG_S3C_DEV_HSMMC3
286 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
287 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; 262 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
288#endif 263#endif
289} 264}
@@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { }
298 273
299/* EXYNOS4 SDHCI setup */ 274/* EXYNOS4 SDHCI setup */
300#ifdef CONFIG_EXYNOS4_SETUP_SDHCI 275#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
301extern char *exynos4_hsmmc_clksrcs[4];
302
303static inline void exynos4_default_sdhci0(void) 276static inline void exynos4_default_sdhci0(void)
304{ 277{
305#ifdef CONFIG_S3C_DEV_HSMMC 278#ifdef CONFIG_S3C_DEV_HSMMC
306 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
307 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; 279 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
308#endif 280#endif
309} 281}
@@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void)
311static inline void exynos4_default_sdhci1(void) 283static inline void exynos4_default_sdhci1(void)
312{ 284{
313#ifdef CONFIG_S3C_DEV_HSMMC1 285#ifdef CONFIG_S3C_DEV_HSMMC1
314 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
315 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; 286 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
316#endif 287#endif
317} 288}
@@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void)
319static inline void exynos4_default_sdhci2(void) 290static inline void exynos4_default_sdhci2(void)
320{ 291{
321#ifdef CONFIG_S3C_DEV_HSMMC2 292#ifdef CONFIG_S3C_DEV_HSMMC2
322 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
323 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; 293 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
324#endif 294#endif
325} 295}
@@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void)
327static inline void exynos4_default_sdhci3(void) 297static inline void exynos4_default_sdhci3(void)
328{ 298{
329#ifdef CONFIG_S3C_DEV_HSMMC3 299#ifdef CONFIG_S3C_DEV_HSMMC3
330 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
331 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; 300 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
332#endif 301#endif
333} 302}
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d33ff0d67fb..9a20d1f55bb7 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -435,14 +435,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
435 435
436 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 436 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
437 struct clk *clk; 437 struct clk *clk;
438 char *name = pdata->clocks[ptr]; 438 char name[14];
439
440 if (name == NULL)
441 continue;
442 439
440 snprintf(name, 14, "mmc_busclk.%d", ptr);
443 clk = clk_get(dev, name); 441 clk = clk_get(dev, name);
444 if (IS_ERR(clk)) { 442 if (IS_ERR(clk)) {
445 dev_err(dev, "failed to get clock %s\n", name);
446 continue; 443 continue;
447 } 444 }
448 445
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 019a7163572f..dcf7e1006426 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -971,6 +971,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
971 struct s3c64xx_spi_info *sci; 971 struct s3c64xx_spi_info *sci;
972 struct spi_master *master; 972 struct spi_master *master;
973 int ret; 973 int ret;
974 char clk_name[16];
974 975
975 if (pdev->id < 0) { 976 if (pdev->id < 0) {
976 dev_err(&pdev->dev, 977 dev_err(&pdev->dev,
@@ -984,11 +985,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
984 } 985 }
985 986
986 sci = pdev->dev.platform_data; 987 sci = pdev->dev.platform_data;
987 if (!sci->src_clk_name) {
988 dev_err(&pdev->dev,
989 "Board init must call s3c64xx_spi_set_info()\n");
990 return -EINVAL;
991 }
992 988
993 /* Check for availability of necessary resource */ 989 /* Check for availability of necessary resource */
994 990
@@ -1073,17 +1069,17 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1073 goto err4; 1069 goto err4;
1074 } 1070 }
1075 1071
1076 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); 1072 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1073 sdd->src_clk = clk_get(&pdev->dev, clk_name);
1077 if (IS_ERR(sdd->src_clk)) { 1074 if (IS_ERR(sdd->src_clk)) {
1078 dev_err(&pdev->dev, 1075 dev_err(&pdev->dev,
1079 "Unable to acquire clock '%s'\n", sci->src_clk_name); 1076 "Unable to acquire clock '%s'\n", clk_name);
1080 ret = PTR_ERR(sdd->src_clk); 1077 ret = PTR_ERR(sdd->src_clk);
1081 goto err5; 1078 goto err5;
1082 } 1079 }
1083 1080
1084 if (clk_enable(sdd->src_clk)) { 1081 if (clk_enable(sdd->src_clk)) {
1085 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", 1082 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1086 sci->src_clk_name);
1087 ret = -EBUSY; 1083 ret = -EBUSY;
1088 goto err6; 1084 goto err6;
1089 } 1085 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 05:44:05 -0500