diff options
-rw-r--r-- | arch/arm/mach-omap2/cpuidle34xx.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 1120494064d5..b0bee34c5107 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <plat/powerdomain.h> | 28 | #include <plat/powerdomain.h> |
29 | #include <plat/irqs.h> | 29 | #include <plat/irqs.h> |
30 | #include <plat/control.h> | 30 | #include <plat/control.h> |
31 | #include <plat/serial.h> | ||
31 | 32 | ||
32 | #include "pm.h" | 33 | #include "pm.h" |
33 | 34 | ||
@@ -124,11 +125,15 @@ return_sleep_time: | |||
124 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, | 125 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
125 | struct cpuidle_state *state) | 126 | struct cpuidle_state *state) |
126 | { | 127 | { |
128 | struct cpuidle_state *new_state = state; | ||
129 | |||
127 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { | 130 | if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { |
128 | if (dev->safe_state) | 131 | BUG_ON(!dev->safe_state); |
129 | return dev->safe_state->enter(dev, dev->safe_state); | 132 | new_state = dev->safe_state; |
130 | } | 133 | } |
131 | return omap3_enter_idle(dev, state); | 134 | |
135 | dev->last_state = new_state; | ||
136 | return omap3_enter_idle(dev, new_state); | ||
132 | } | 137 | } |
133 | 138 | ||
134 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | 139 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
@@ -163,7 +168,8 @@ void omap_init_power_states(void) | |||
163 | omap3_power_states[OMAP3_STATE_C2].threshold = 300; | 168 | omap3_power_states[OMAP3_STATE_C2].threshold = 300; |
164 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; | 169 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET; |
165 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; | 170 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; |
166 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; | 171 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | |
172 | CPUIDLE_FLAG_CHECK_BM; | ||
167 | 173 | ||
168 | /* C3 . MPU OFF + Core active */ | 174 | /* C3 . MPU OFF + Core active */ |
169 | omap3_power_states[OMAP3_STATE_C3].valid = 1; | 175 | omap3_power_states[OMAP3_STATE_C3].valid = 1; |
@@ -173,7 +179,8 @@ void omap_init_power_states(void) | |||
173 | omap3_power_states[OMAP3_STATE_C3].threshold = 4000; | 179 | omap3_power_states[OMAP3_STATE_C3].threshold = 4000; |
174 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; | 180 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF; |
175 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; | 181 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; |
176 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID; | 182 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | |
183 | CPUIDLE_FLAG_CHECK_BM; | ||
177 | 184 | ||
178 | /* C4 . MPU CSWR + Core CSWR*/ | 185 | /* C4 . MPU CSWR + Core CSWR*/ |
179 | omap3_power_states[OMAP3_STATE_C4].valid = 1; | 186 | omap3_power_states[OMAP3_STATE_C4].valid = 1; |
@@ -198,7 +205,7 @@ void omap_init_power_states(void) | |||
198 | CPUIDLE_FLAG_CHECK_BM; | 205 | CPUIDLE_FLAG_CHECK_BM; |
199 | 206 | ||
200 | /* C6 . MPU OFF + Core OFF */ | 207 | /* C6 . MPU OFF + Core OFF */ |
201 | omap3_power_states[OMAP3_STATE_C6].valid = 0; | 208 | omap3_power_states[OMAP3_STATE_C6].valid = 1; |
202 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; | 209 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; |
203 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; | 210 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000; |
204 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; | 211 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000; |