diff options
-rw-r--r-- | drivers/dma/mv_xor.c | 28 | ||||
-rw-r--r-- | drivers/dma/mv_xor.h | 22 |
2 files changed, 30 insertions, 20 deletions
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index a30e221ed1ba..4ee5bb194fd5 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c | |||
@@ -50,9 +50,9 @@ static void mv_desc_init(struct mv_xor_desc_slot *desc, | |||
50 | { | 50 | { |
51 | struct mv_xor_desc *hw_desc = desc->hw_desc; | 51 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
52 | 52 | ||
53 | hw_desc->status = (1 << 31); | 53 | hw_desc->status = XOR_DESC_DMA_OWNED; |
54 | hw_desc->phy_next_desc = 0; | 54 | hw_desc->phy_next_desc = 0; |
55 | hw_desc->desc_command = (1 << 31); | 55 | hw_desc->desc_command = XOR_DESC_EOD_INT_EN; |
56 | hw_desc->phy_dest_addr = addr; | 56 | hw_desc->phy_dest_addr = addr; |
57 | hw_desc->byte_count = byte_count; | 57 | hw_desc->byte_count = byte_count; |
58 | } | 58 | } |
@@ -105,17 +105,9 @@ static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |||
105 | return intr_cause; | 105 | return intr_cause; |
106 | } | 106 | } |
107 | 107 | ||
108 | static int mv_is_err_intr(u32 intr_cause) | ||
109 | { | ||
110 | if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9))) | ||
111 | return 1; | ||
112 | |||
113 | return 0; | ||
114 | } | ||
115 | |||
116 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) | 108 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
117 | { | 109 | { |
118 | u32 val = ~(1 << (chan->idx * 16)); | 110 | u32 val = ~(XOR_INT_END_OF_DESC << (chan->idx * 16)); |
119 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); | 111 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
120 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); | 112 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
121 | } | 113 | } |
@@ -627,18 +619,16 @@ static void mv_dump_xor_regs(struct mv_xor_chan *chan) | |||
627 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, | 619 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, |
628 | u32 intr_cause) | 620 | u32 intr_cause) |
629 | { | 621 | { |
630 | if (intr_cause & (1 << 4)) { | 622 | if (intr_cause & XOR_INT_ERR_DECODE) { |
631 | dev_dbg(mv_chan_to_devp(chan), | 623 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); |
632 | "ignore this error\n"); | 624 | return; |
633 | return; | ||
634 | } | 625 | } |
635 | 626 | ||
636 | dev_err(mv_chan_to_devp(chan), | 627 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
637 | "error on chan %d. intr cause 0x%08x\n", | ||
638 | chan->idx, intr_cause); | 628 | chan->idx, intr_cause); |
639 | 629 | ||
640 | mv_dump_xor_regs(chan); | 630 | mv_dump_xor_regs(chan); |
641 | BUG(); | 631 | WARN_ON(1); |
642 | } | 632 | } |
643 | 633 | ||
644 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | 634 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
@@ -648,7 +638,7 @@ static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |||
648 | 638 | ||
649 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); | 639 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
650 | 640 | ||
651 | if (mv_is_err_intr(intr_cause)) | 641 | if (intr_cause & XOR_INTR_ERRORS) |
652 | mv_xor_err_interrupt_handler(chan, intr_cause); | 642 | mv_xor_err_interrupt_handler(chan, intr_cause); |
653 | 643 | ||
654 | tasklet_schedule(&chan->irq_tasklet); | 644 | tasklet_schedule(&chan->irq_tasklet); |
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index e03021ebed9a..ae41c31c6ea5 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h | |||
@@ -34,6 +34,9 @@ | |||
34 | #define XOR_OPERATION_MODE_MEMCPY 2 | 34 | #define XOR_OPERATION_MODE_MEMCPY 2 |
35 | #define XOR_DESCRIPTOR_SWAP BIT(14) | 35 | #define XOR_DESCRIPTOR_SWAP BIT(14) |
36 | 36 | ||
37 | #define XOR_DESC_DMA_OWNED BIT(31) | ||
38 | #define XOR_DESC_EOD_INT_EN BIT(31) | ||
39 | |||
37 | #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) | 40 | #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) |
38 | #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) | 41 | #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) |
39 | #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) | 42 | #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) |
@@ -48,7 +51,24 @@ | |||
48 | #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) | 51 | #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) |
49 | #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) | 52 | #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) |
50 | #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) | 53 | #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) |
51 | #define XOR_INTR_MASK_VALUE 0x3F5 | 54 | |
55 | #define XOR_INT_END_OF_DESC BIT(0) | ||
56 | #define XOR_INT_END_OF_CHAIN BIT(1) | ||
57 | #define XOR_INT_STOPPED BIT(2) | ||
58 | #define XOR_INT_PAUSED BIT(3) | ||
59 | #define XOR_INT_ERR_DECODE BIT(4) | ||
60 | #define XOR_INT_ERR_RDPROT BIT(5) | ||
61 | #define XOR_INT_ERR_WRPROT BIT(6) | ||
62 | #define XOR_INT_ERR_OWN BIT(7) | ||
63 | #define XOR_INT_ERR_PAR BIT(8) | ||
64 | #define XOR_INT_ERR_MBUS BIT(9) | ||
65 | |||
66 | #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \ | ||
67 | XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \ | ||
68 | XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS) | ||
69 | |||
70 | #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | \ | ||
71 | XOR_INT_STOPPED | XOR_INTR_ERRORS) | ||
52 | 72 | ||
53 | #define WINDOW_BASE(w) (0x50 + ((w) << 2)) | 73 | #define WINDOW_BASE(w) (0x50 + ((w) << 2)) |
54 | #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) | 74 | #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) |