18 files changed, 594 insertions, 105 deletions

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 756af4d7ec74..7496d245f28c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1439,6 +1439,8 @@ EXPORT_SYMBOL(drm_detect_monitor_audio);
 static void drm_add_display_info(struct edid *edid,
                                  struct drm_display_info *info)
 {
+        u8 *edid_ext;
+
         info->width_mm = edid->width_cm * 10;
         info->height_mm = edid->height_cm * 10;
 
@@ -1483,6 +1485,13 @@ static void drm_add_display_info(struct edid *edid,
                 info->color_formats = DRM_COLOR_FORMAT_YCRCB444;
         if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422)
                 info->color_formats = DRM_COLOR_FORMAT_YCRCB422;
+
+        /* Get data from CEA blocks if present */
+        edid_ext = drm_find_cea_extension(edid);
+        if (!edid_ext)
+                return;
+
+        info->cea_rev = edid_ext[1];
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e2662497d50f..a8ab6263e0d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1338,6 +1338,155 @@ static const struct file_operations i915_wedged_fops = {
         .llseek = default_llseek,
 };
 
+static int
+i915_max_freq_open(struct inode *inode,
+                   struct file *filp)
+{
+        filp->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t
+i915_max_freq_read(struct file *filp,
+                   char __user *ubuf,
+                   size_t max,
+                   loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        char buf[80];
+        int len;
+
+        len = snprintf(buf, sizeof (buf),
+                       "max freq: %d\n", dev_priv->max_delay * 50);
+
+        if (len > sizeof (buf))
+                len = sizeof (buf);
+
+        return simple_read_from_buffer(ubuf, max, ppos, buf, len);
+}
+
+static ssize_t
+i915_max_freq_write(struct file *filp,
+                  const char __user *ubuf,
+                  size_t cnt,
+                  loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        char buf[20];
+        int val = 1;
+
+        if (cnt > 0) {
+                if (cnt > sizeof (buf) - 1)
+                        return -EINVAL;
+
+                if (copy_from_user(buf, ubuf, cnt))
+                        return -EFAULT;
+                buf[cnt] = 0;
+
+                val = simple_strtoul(buf, NULL, 0);
+        }
+
+        DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
+
+        /*
+         * Turbo will still be enabled, but won't go above the set value.
+         */
+        dev_priv->max_delay = val / 50;
+
+        gen6_set_rps(dev, val / 50);
+
+        return cnt;
+}
+
+static const struct file_operations i915_max_freq_fops = {
+        .owner = THIS_MODULE,
+        .open = i915_max_freq_open,
+        .read = i915_max_freq_read,
+        .write = i915_max_freq_write,
+        .llseek = default_llseek,
+};
+
+static int
+i915_cache_sharing_open(struct inode *inode,
+                   struct file *filp)
+{
+        filp->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t
+i915_cache_sharing_read(struct file *filp,
+                   char __user *ubuf,
+                   size_t max,
+                   loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        char buf[80];
+        u32 snpcr;
+        int len;
+
+        mutex_lock(&dev_priv->dev->struct_mutex);
+        snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
+        mutex_unlock(&dev_priv->dev->struct_mutex);
+
+        len = snprintf(buf, sizeof (buf),
+                       "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
+                       GEN6_MBC_SNPCR_SHIFT);
+
+        if (len > sizeof (buf))
+                len = sizeof (buf);
+
+        return simple_read_from_buffer(ubuf, max, ppos, buf, len);
+}
+
+static ssize_t
+i915_cache_sharing_write(struct file *filp,
+                  const char __user *ubuf,
+                  size_t cnt,
+                  loff_t *ppos)
+{
+        struct drm_device *dev = filp->private_data;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        char buf[20];
+        u32 snpcr;
+        int val = 1;
+
+        if (cnt > 0) {
+                if (cnt > sizeof (buf) - 1)
+                        return -EINVAL;
+
+                if (copy_from_user(buf, ubuf, cnt))
+                        return -EFAULT;
+                buf[cnt] = 0;
+
+                val = simple_strtoul(buf, NULL, 0);
+        }
+
+        if (val < 0 || val > 3)
+                return -EINVAL;
+
+        DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
+
+        /* Update the cache sharing policy here as well */
+        snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
+        snpcr &= ~GEN6_MBC_SNPCR_MASK;
+        snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
+        I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+
+        return cnt;
+}
+
+static const struct file_operations i915_cache_sharing_fops = {
+        .owner = THIS_MODULE,
+        .open = i915_cache_sharing_open,
+        .read = i915_cache_sharing_read,
+        .write = i915_cache_sharing_write,
+        .llseek = default_llseek,
+};
+
 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  * allocated we need to hook into the minor for release. */
 static int
@@ -1437,6 +1586,36 @@ static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
 }
 
+static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
+{
+        struct drm_device *dev = minor->dev;
+        struct dentry *ent;
+
+        ent = debugfs_create_file("i915_max_freq",
+                                  S_IRUGO | S_IWUSR,
+                                  root, dev,
+                                  &i915_max_freq_fops);
+        if (IS_ERR(ent))
+                return PTR_ERR(ent);
+
+        return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
+}
+
+static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
+{
+        struct drm_device *dev = minor->dev;
+        struct dentry *ent;
+
+        ent = debugfs_create_file("i915_cache_sharing",
+                                  S_IRUGO | S_IWUSR,
+                                  root, dev,
+                                  &i915_cache_sharing_fops);
+        if (IS_ERR(ent))
+                return PTR_ERR(ent);
+
+        return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
+}
+
 static struct drm_info_list i915_debugfs_list[] = {
         {"i915_capabilities", i915_capabilities, 0},
         {"i915_gem_objects", i915_gem_object_info, 0},
@@ -1490,6 +1669,12 @@ int i915_debugfs_init(struct drm_minor *minor)
         ret = i915_forcewake_create(minor->debugfs_root, minor);
         if (ret)
                 return ret;
+        ret = i915_max_freq_create(minor->debugfs_root, minor);
+        if (ret)
+                return ret;
+        ret = i915_cache_sharing_create(minor->debugfs_root, minor);
+        if (ret)
+                return ret;
 
         return drm_debugfs_create_files(i915_debugfs_list,
                                         I915_DEBUGFS_ENTRIES,
@@ -1504,6 +1689,10 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
                                  1, minor);
         drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
                                  1, minor);
+        drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
+                                 1, minor);
+        drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
+                                 1, minor);
 }
 
 #endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12712824a6d2..8a3942c4f099 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -61,7 +61,6 @@ static void i915_write_hws_pga(struct drm_device *dev)
 static int i915_init_phys_hws(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
         /* Program Hardware Status Page */
         dev_priv->status_page_dmah =
@@ -71,10 +70,9 @@ static int i915_init_phys_hws(struct drm_device *dev)
                 DRM_ERROR("Can not allocate hardware status page\n");
                 return -ENOMEM;
         }
-        ring->status_page.page_addr =
-                (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
 
-        memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
+        memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
+                  0, PAGE_SIZE);
 
         i915_write_hws_pga(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ce045a8cf82c..60e4b9ef618b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -62,7 +62,7 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
 MODULE_PARM_DESC(semaphores,
                 "Use semaphores for inter-ring sync (default: false)");
 
-unsigned int i915_enable_rc6 __read_mostly = 0;
+unsigned int i915_enable_rc6 __read_mostly = 1;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
                 "Enable power-saving render C-state 6 (default: true)");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6867e193d85e..feb4f164fd1b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -544,6 +544,7 @@ typedef struct drm_i915_private {
         u32 savePIPEB_LINK_M1;
         u32 savePIPEB_LINK_N1;
         u32 saveMCHBAR_RENDER_STANDBY;
+        u32 savePCH_PORT_HOTPLUG;
 
         struct {
                 /** Bridge to intel-gtt-ko */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d1cd8b89f47d..a546a71fb060 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3112,7 +3112,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 
         if (pipelined != obj->ring) {
                 ret = i915_gem_object_wait_rendering(obj);
-                if (ret)
+                if (ret == -ERESTARTSYS)
                         return ret;
         }
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 23d1ae67d279..02f96fd0d52d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -306,12 +306,15 @@ static void i915_hotplug_work_func(struct work_struct *work)
         struct drm_mode_config *mode_config = &dev->mode_config;
         struct intel_encoder *encoder;
 
+        mutex_lock(&mode_config->mutex);
         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 
         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
                 if (encoder->hot_plug)
                         encoder->hot_plug(encoder);
 
+        mutex_unlock(&mode_config->mutex);
+
         /* Just fire off a uevent and let userspace tell us what to do */
         drm_helper_hpd_irq_event(dev);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02db299f621a..d1331f771e2f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -78,6 +78,14 @@
 #define  GRDOM_RENDER   (1<<2)
 #define  GRDOM_MEDIA    (3<<2)
 
+#define GEN6_MBCUNIT_SNPCR      0x900c /* for LLC config */
+#define   GEN6_MBC_SNPCR_SHIFT  21
+#define   GEN6_MBC_SNPCR_MASK   (3<<21)
+#define   GEN6_MBC_SNPCR_MAX    (0<<21)
+#define   GEN6_MBC_SNPCR_MED    (1<<21)
+#define   GEN6_MBC_SNPCR_LOW    (2<<21)
+#define   GEN6_MBC_SNPCR_MIN    (3<<21) /* only 1/16th of the cache is shared */
+
 #define GEN6_GDRST      0x941c
 #define  GEN6_GRDOM_FULL                (1 << 0)
 #define  GEN6_GRDOM_RENDER              (1 << 1)
@@ -1506,6 +1514,7 @@
 #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
 #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
 #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
+#define   VIDEO_DIP_SELECT_MASK         (3 << 19)
 #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
 #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
 #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
@@ -2084,9 +2093,6 @@
 #define   DP_PIPEB_SELECT               (1 << 30)
 #define   DP_PIPE_MASK                  (1 << 30)
 
-#define DP_PIPE_ENABLED(V, P) \
-        (((V) & (DP_PIPE_MASK | DP_PORT_EN)) == ((P) << 30 | DP_PORT_EN))
-
 /* Link training mode - select a suitable mode for each stage */
 #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
 #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
@@ -3024,6 +3030,20 @@
 #define _TRANSA_DP_LINK_M2       0xe0048
 #define _TRANSA_DP_LINK_N2       0xe004c
 
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008
@@ -3076,6 +3096,16 @@
 #define  TRANS_6BPC             (2<<5)
 #define  TRANS_12BPC            (3<<5)
 
+#define _TRANSA_CHICKEN2         0xf0064
+#define _TRANSB_CHICKEN2         0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+
+#define SOUTH_CHICKEN1          0xc2000
+#define  FDIA_PHASE_SYNC_SHIFT_OVR      19
+#define  FDIA_PHASE_SYNC_SHIFT_EN       18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define SOUTH_CHICKEN2          0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
 
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 285758603ac8..87677d60d0df 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -812,6 +812,7 @@ int i915_save_state(struct drm_device *dev)
                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
                 dev_priv->saveMCHBAR_RENDER_STANDBY =
                         I915_READ(RSTDBYCTL);
+                dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
         } else {
                 dev_priv->saveIER = I915_READ(IER);
                 dev_priv->saveIMR = I915_READ(IMR);
@@ -863,6 +864,7 @@ int i915_restore_state(struct drm_device *dev)
                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
+                I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
         } else {
                 I915_WRITE(IER, dev_priv->saveIER);
                 I915_WRITE(IMR, dev_priv->saveIMR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 393a39922e53..35364e68a091 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -980,11 +980,29 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
              pipe_name(pipe));
 }
 
+static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
+                            int reg, u32 port_sel, u32 val)
+{
+        if ((val & DP_PORT_EN) == 0)
+                return false;
+
+        if (HAS_PCH_CPT(dev_priv->dev)) {
+                u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
+                u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
+                if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
+                        return false;
+        } else {
+                if ((val & DP_PIPE_MASK) != (pipe << 30))
+                        return false;
+        }
+        return true;
+}
+
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
-                                   enum pipe pipe, int reg)
+                                   enum pipe pipe, int reg, u32 port_sel)
 {
         u32 val = I915_READ(reg);
-        WARN(DP_PIPE_ENABLED(val, pipe),
+        WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
              reg, pipe_name(pipe));
 }
@@ -1004,9 +1022,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
         int reg;
         u32 val;
 
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
-        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
+        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
         reg = PCH_ADPA;
         val = I915_READ(reg);
@@ -1276,6 +1294,17 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
         intel_wait_for_pipe_off(dev_priv->dev, pipe);
 }
 
+/*
+ * Plane regs are double buffered, going from enabled->disabled needs a
+ * trigger in order to latch.  The display address reg provides this.
+ */
+static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
+                                      enum plane plane)
+{
+        I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
+        I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
+}
+
 /**
  * intel_enable_plane - enable a display plane on a given pipe
  * @dev_priv: i915 private structure
@@ -1299,20 +1328,10 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
                 return;
 
         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
+        intel_flush_display_plane(dev_priv, plane);
         intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 
-/*
- * Plane regs are double buffered, going from enabled->disabled needs a
- * trigger in order to latch.  The display address reg provides this.
- */
-static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
-                                      enum plane plane)
-{
-        u32 reg = DSPADDR(plane);
-        I915_WRITE(reg, I915_READ(reg));
-}
-
 /**
  * intel_disable_plane - disable a display plane
  * @dev_priv: i915 private structure
@@ -1338,19 +1357,24 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
 }
 
 static void disable_pch_dp(struct drm_i915_private *dev_priv,
-                           enum pipe pipe, int reg)
+                           enum pipe pipe, int reg, u32 port_sel)
 {
         u32 val = I915_READ(reg);
-        if (DP_PIPE_ENABLED(val, pipe))
+        if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
+                DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
                 I915_WRITE(reg, val & ~DP_PORT_EN);
+        }
 }
 
 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
                              enum pipe pipe, int reg)
 {
         u32 val = I915_READ(reg);
-        if (HDMI_PIPE_ENABLED(val, pipe))
+        if (HDMI_PIPE_ENABLED(val, pipe)) {
+                DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
+                              reg, pipe);
                 I915_WRITE(reg, val & ~PORT_ENABLE);
+        }
 }
 
 /* Disable any ports connected to this transcoder */
@@ -1362,9 +1386,9 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
         val = I915_READ(PCH_PP_CONTROL);
         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
 
-        disable_pch_dp(dev_priv, pipe, PCH_DP_B);
-        disable_pch_dp(dev_priv, pipe, PCH_DP_C);
-        disable_pch_dp(dev_priv, pipe, PCH_DP_D);
+        disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
+        disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
+        disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
         reg = PCH_ADPA;
         val = I915_READ(reg);
@@ -2096,7 +2120,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 
         /* no fb bound */
         if (!crtc->fb) {
-                DRM_DEBUG_KMS("No FB bound\n");
+                DRM_ERROR("No FB bound\n");
                 return 0;
         }
 
@@ -2105,6 +2129,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         case 1:
                 break;
         default:
+                DRM_ERROR("no plane for crtc\n");
                 return -EINVAL;
         }
 
@@ -2114,6 +2139,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                                          NULL);
         if (ret != 0) {
                 mutex_unlock(&dev->struct_mutex);
+                DRM_ERROR("pin & fence failed\n");
                 return ret;
         }
 
@@ -2142,6 +2168,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         if (ret) {
                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
                 mutex_unlock(&dev->struct_mutex);
+                DRM_ERROR("failed to update base address\n");
                 return ret;
         }
 
@@ -2248,6 +2275,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
                            FDI_FE_ERRC_ENABLE);
 }
 
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+        flags |= FDI_PHASE_SYNC_OVR(pipe);
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+        flags |= FDI_PHASE_SYNC_EN(pipe);
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+        POSTING_READ(SOUTH_CHICKEN1);
+}
+
 /* The FDI link training functions for ILK/Ibexpeak. */
 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -2398,6 +2437,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
+        if (HAS_PCH_CPT(dev))
+                cpt_phase_pointer_enable(dev, pipe);
+
         for (i = 0; i < 4; i++ ) {
                 reg = FDI_TX_CTL(pipe);
                 temp = I915_READ(reg);
@@ -2514,6 +2556,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
+        if (HAS_PCH_CPT(dev))
+                cpt_phase_pointer_enable(dev, pipe);
+
         for (i = 0; i < 4; i++ ) {
                 reg = FDI_TX_CTL(pipe);
                 temp = I915_READ(reg);
@@ -2623,6 +2668,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
         }
 }
 
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+        flags &= ~(FDI_PHASE_SYNC_EN(pipe));
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+        flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
+        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+        POSTING_READ(SOUTH_CHICKEN1);
+}
 static void ironlake_fdi_disable(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
@@ -2652,6 +2708,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
                 I915_WRITE(FDI_RX_CHICKEN(pipe),
                            I915_READ(FDI_RX_CHICKEN(pipe) &
                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
+        } else if (HAS_PCH_CPT(dev)) {
+                cpt_phase_pointer_disable(dev, pipe);
         }
 
         /* still set train pattern 1 */
@@ -2862,14 +2920,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
         }
 
+        /*
+         * On ILK+ LUT must be loaded before the pipe is running but with
+         * clocks enabled
+         */
+        intel_crtc_load_lut(crtc);
+
         intel_enable_pipe(dev_priv, pipe, is_pch_port);
         intel_enable_plane(dev_priv, plane, pipe);
 
         if (is_pch_port)
                 ironlake_pch_enable(crtc);
 
-        intel_crtc_load_lut(crtc);
-
         mutex_lock(&dev->struct_mutex);
         intel_update_fbc(dev);
         mutex_unlock(&dev->struct_mutex);
@@ -4538,7 +4600,9 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         if (connector->encoder != encoder)
                                 continue;
 
-                        if (connector->display_info.bpc < display_bpc) {
+                        /* Don't use an invalid EDID bpc value */
+                        if (connector->display_info.bpc &&
+                            connector->display_info.bpc < display_bpc) {
                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
                                 display_bpc = connector->display_info.bpc;
                         }
@@ -5153,7 +5217,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                 temp |= PIPE_12BPC;
                 break;
         default:
-                WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
+                WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
+                        pipe_bpp);
                 temp |= PIPE_8BPC;
                 pipe_bpp = 24;
                 break;
@@ -5238,7 +5303,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
         } else if (is_sdvo && is_tv)
                 factor = 20;
 
-        if (clock.m1 < factor * clock.n)
+        if (clock.m < factor * clock.n)
                 fp |= FP_CB_TUNE;
 
         dpll = 0;
@@ -5516,6 +5581,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
         drm_vblank_post_modeset(dev, pipe);
 
+        intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
+
         return ret;
 }
 
@@ -7714,10 +7781,12 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                    ILK_DPARB_CLK_GATE  |
                    ILK_DPFD_CLK_GATE);
 
-        for_each_pipe(pipe)
+        for_each_pipe(pipe) {
                 I915_WRITE(DSPCNTR(pipe),
                            I915_READ(DSPCNTR(pipe)) |
                            DISPPLANE_TRICKLE_FEED_DISABLE);
+                intel_flush_display_plane(dev_priv, pipe);
+        }
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)
@@ -7734,10 +7803,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 
         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
 
-        for_each_pipe(pipe)
+        for_each_pipe(pipe) {
                 I915_WRITE(DSPCNTR(pipe),
                            I915_READ(DSPCNTR(pipe)) |
                            DISPPLANE_TRICKLE_FEED_DISABLE);
+                intel_flush_display_plane(dev_priv, pipe);
+        }
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
@@ -7820,6 +7891,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
 static void cpt_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+        int pipe;
 
         /*
          * On Ibex Peak and Cougar Point, we need to disable clock
@@ -7829,6 +7901,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
                    DPLS_EDP_PPS_FIX_DIS);
+        /* Without this, mode sets may fail silently on FDI */
+        for_each_pipe(pipe)
+                I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
 }
 
 static void ironlake_teardown_rc6(struct drm_device *dev)
@@ -8178,6 +8253,9 @@ struct intel_quirk intel_quirks[] = {
 
         /* Lenovo U160 cannot use SSC on LVDS */
         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
+
+        /* Sony Vaio Y cannot use SSC on LVDS */
+        { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f797fb58ba9c..0feae908bb37 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -50,9 +50,10 @@ struct intel_dp {
         bool has_audio;
         int force_audio;
         uint32_t color_range;
+        int dpms_mode;
         uint8_t link_bw;
         uint8_t lane_count;
-        uint8_t dpcd[4];
+        uint8_t dpcd[8];
         struct i2c_adapter adapter;
         struct i2c_algo_dp_aux_data algo;
         bool is_pch_edp;
@@ -316,9 +317,17 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         else
                 precharge = 5;
 
-        if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
-                DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
-                          I915_READ(ch_ctl));
+        /* Try to wait for any previous AUX channel activity */
+        for (try = 0; try < 3; try++) {
+                status = I915_READ(ch_ctl);
+                if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
+                        break;
+                msleep(1);
+        }
+
+        if (try == 3) {
+                WARN(1, "dp_aux_ch not started status 0x%08x\n",
+                     I915_READ(ch_ctl));
                 return -EBUSY;
         }
 
@@ -770,6 +779,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
         intel_dp->link_configuration[0] = intel_dp->link_bw;
         intel_dp->link_configuration[1] = intel_dp->lane_count;
+        intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 
         /*
          * Check for DPCD version > 1.1 and enhanced framing support
@@ -1011,6 +1021,8 @@ static void intel_dp_commit(struct drm_encoder *encoder)
 
         if (is_edp(intel_dp))
                 ironlake_edp_backlight_on(dev);
+
+        intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
 static void
@@ -1045,6 +1057,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
                 if (is_edp(intel_dp))
                         ironlake_edp_backlight_on(dev);
         }
+        intel_dp->dpms_mode = mode;
 }
 
 /*
@@ -1334,10 +1347,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
         u32 reg;
         uint32_t DP = intel_dp->DP;
 
-        /* Enable output, wait for it to become active */
-        I915_WRITE(intel_dp->output_reg, intel_dp->DP);
-        POSTING_READ(intel_dp->output_reg);
-        intel_wait_for_vblank(dev, intel_crtc->pipe);
+        /*
+         * On CPT we have to enable the port in training pattern 1, which
+         * will happen below in intel_dp_set_link_train.  Otherwise, enable
+         * the port and wait for it to become active.
+         */
+        if (!HAS_PCH_CPT(dev)) {
+                I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+                POSTING_READ(intel_dp->output_reg);
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
+        }
 
         /* Write the link configuration data */
         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
@@ -1370,7 +1389,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                         reg = DP | DP_LINK_TRAIN_PAT_1;
 
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_1))
+                                             DP_TRAINING_PATTERN_1 |
+                                             DP_LINK_SCRAMBLING_DISABLE))
                         break;
                 /* Set training pattern 1 */
 
@@ -1445,7 +1465,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
                 /* channel eq pattern */
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_2))
+                                             DP_TRAINING_PATTERN_2 |
+                                             DP_LINK_SCRAMBLING_DISABLE))
                         break;
 
                 udelay(400);
@@ -1559,6 +1580,18 @@ intel_dp_link_down(struct intel_dp *intel_dp)
         POSTING_READ(intel_dp->output_reg);
 }
 
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp)
+{
+        if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
+                                           sizeof (intel_dp->dpcd)) &&
+            (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
+                return true;
+        }
+
+        return false;
+}
+
 /*
  * According to DP spec
  * 5.1.2:
@@ -1571,36 +1604,44 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 static void
 intel_dp_check_link_status(struct intel_dp *intel_dp)
 {
-        int ret;
+        if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
+                return;
 
         if (!intel_dp->base.base.crtc)
                 return;
 
+        /* Try to read receiver status if the link appears to be up */
         if (!intel_dp_get_link_status(intel_dp)) {
                 intel_dp_link_down(intel_dp);
                 return;
         }
 
-        /* Try to read receiver status if the link appears to be up */
-        ret = intel_dp_aux_native_read(intel_dp,
-                                       0x000, intel_dp->dpcd,
-                                       sizeof (intel_dp->dpcd));
-        if (ret != sizeof(intel_dp->dpcd)) {
+        /* Now read the DPCD to see if it's actually running */
+        if (!intel_dp_get_dpcd(intel_dp)) {
                 intel_dp_link_down(intel_dp);
                 return;
         }
 
         if (!intel_channel_eq_ok(intel_dp)) {
+                DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
+                              drm_get_encoder_name(&intel_dp->base.base));
                 intel_dp_start_link_train(intel_dp);
                 intel_dp_complete_link_train(intel_dp);
         }
 }
 
 static enum drm_connector_status
+intel_dp_detect_dpcd(struct intel_dp *intel_dp)
+{
+        if (intel_dp_get_dpcd(intel_dp))
+                return connector_status_connected;
+        return connector_status_disconnected;
+}
+
+static enum drm_connector_status
 ironlake_dp_detect(struct intel_dp *intel_dp)
 {
         enum drm_connector_status status;
-        bool ret;
 
         /* Can't disconnect eDP, but you can close the lid... */
         if (is_edp(intel_dp)) {
@@ -1610,15 +1651,7 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
                 return status;
         }
 
-        status = connector_status_disconnected;
-        ret = intel_dp_aux_native_read_retry(intel_dp,
-                                             0x000, intel_dp->dpcd,
-                                             sizeof (intel_dp->dpcd));
-        if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
-                status = connector_status_connected;
-        DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
-                      intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
-        return status;
+        return intel_dp_detect_dpcd(intel_dp);
 }
 
 static enum drm_connector_status
@@ -1626,7 +1659,6 @@ g4x_dp_detect(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp->base.base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        enum drm_connector_status status;
         uint32_t temp, bit;
 
         switch (intel_dp->output_reg) {
@@ -1648,15 +1680,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
         if ((temp & bit) == 0)
                 return connector_status_disconnected;
 
-        status = connector_status_disconnected;
-        if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
-                                     sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
-        {
-                if (intel_dp->dpcd[DP_DPCD_REV] != 0)
-                        status = connector_status_connected;
-        }
-
-        return status;
+        return intel_dp_detect_dpcd(intel_dp);
 }
 
 /**
@@ -1679,6 +1703,12 @@ intel_dp_detect(struct drm_connector *connector, bool force)
                 status = ironlake_dp_detect(intel_dp);
         else
                 status = g4x_dp_detect(intel_dp);
+
+        DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
+                      intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
+                      intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
+                      intel_dp->dpcd[6], intel_dp->dpcd[7]);
+
         if (status != connector_status_connected)
                 return status;
 
@@ -1924,6 +1954,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                 return;
 
         intel_dp->output_reg = output_reg;
+        intel_dp->dpms_mode = -1;
 
         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
         if (!intel_connector) {
@@ -2000,7 +2031,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
         /* Cache some DPCD data in the eDP case */
         if (is_edp(intel_dp)) {
-                int ret;
+                bool ret;
                 u32 pp_on, pp_div;
 
                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
@@ -2013,11 +2044,9 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
 
                 ironlake_edp_panel_vdd_on(intel_dp);
-                ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
-                                               intel_dp->dpcd,
-                                               sizeof(intel_dp->dpcd));
+                ret = intel_dp_get_dpcd(intel_dp);
                 ironlake_edp_panel_vdd_off(intel_dp);
-                if (ret == sizeof(intel_dp->dpcd)) {
+                if (ret) {
                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
                                 dev_priv->no_aux_handshake =
                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e990f9760ef..7b330e76a435 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -178,10 +178,28 @@ struct intel_crtc {
 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 
+#define DIP_HEADER_SIZE 5
+
 #define DIP_TYPE_AVI    0x82
 #define DIP_VERSION_AVI 0x2
 #define DIP_LEN_AVI     13
 
+#define DIP_TYPE_SPD    0x3
+#define DIP_VERSION_SPD 0x1
+#define DIP_LEN_SPD     25
+#define DIP_SPD_UNKNOWN 0
+#define DIP_SPD_DSTB    0x1
+#define DIP_SPD_DVDP    0x2
+#define DIP_SPD_DVHS    0x3
+#define DIP_SPD_HDDVR   0x4
+#define DIP_SPD_DVC     0x5
+#define DIP_SPD_DSC     0x6
+#define DIP_SPD_VCD     0x7
+#define DIP_SPD_GAME    0x8
+#define DIP_SPD_PC      0x9
+#define DIP_SPD_BD      0xa
+#define DIP_SPD_SCD     0xb
+
 struct dip_infoframe {
         uint8_t type;           /* HB0 */
         uint8_t ver;            /* HB1 */
@@ -206,6 +224,11 @@ struct dip_infoframe {
                         uint16_t left_bar_end;
                         uint16_t right_bar_start;
                 } avi;
+                struct {
+                        uint8_t vn[8];
+                        uint8_t pd[16];
+                        uint8_t sdi;
+                } spd;
                 uint8_t payload[27];
         } __attribute__ ((packed)) body;
 } __attribute__((packed));
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1ed8e6903915..226ba830f383 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -45,6 +45,8 @@ struct intel_hdmi {
         bool has_hdmi_sink;
         bool has_audio;
         int force_audio;
+        void (*write_infoframe)(struct drm_encoder *encoder,
+                                struct dip_infoframe *frame);
 };
 
 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
@@ -58,37 +60,70 @@ static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
                             struct intel_hdmi, base);
 }
 
-void intel_dip_infoframe_csum(struct dip_infoframe *avi_if)
+void intel_dip_infoframe_csum(struct dip_infoframe *frame)
 {
-        uint8_t *data = (uint8_t *)avi_if;
+        uint8_t *data = (uint8_t *)frame;
         uint8_t sum = 0;
         unsigned i;
 
-        avi_if->checksum = 0;
-        avi_if->ecc = 0;
+        frame->checksum = 0;
+        frame->ecc = 0;
 
-        for (i = 0; i < sizeof(*avi_if); i++)
+        /* Header isn't part of the checksum */
+        for (i = 5; i < frame->len; i++)
                 sum += data[i];
 
-        avi_if->checksum = 0x100 - sum;
+        frame->checksum = 0x100 - sum;
 }
 
-static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
+static u32 intel_infoframe_index(struct dip_infoframe *frame)
 {
-        struct dip_infoframe avi_if = {
-                .type = DIP_TYPE_AVI,
-                .ver = DIP_VERSION_AVI,
-                .len = DIP_LEN_AVI,
-        };
-        uint32_t *data = (uint32_t *)&avi_if;
+        u32 flags = 0;
+
+        switch (frame->type) {
+        case DIP_TYPE_AVI:
+                flags |= VIDEO_DIP_SELECT_AVI;
+                break;
+        case DIP_TYPE_SPD:
+                flags |= VIDEO_DIP_SELECT_SPD;
+                break;
+        default:
+                DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
+                break;
+        }
+
+        return flags;
+}
+
+static u32 intel_infoframe_flags(struct dip_infoframe *frame)
+{
+        u32 flags = 0;
+
+        switch (frame->type) {
+        case DIP_TYPE_AVI:
+                flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
+                break;
+        case DIP_TYPE_SPD:
+                flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC;
+                break;
+        default:
+                DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
+                break;
+        }
+
+        return flags;
+}
+
+static void i9xx_write_infoframe(struct drm_encoder *encoder,
+                                 struct dip_infoframe *frame)
+{
+        uint32_t *data = (uint32_t *)frame;
         struct drm_device *dev = encoder->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-        u32 port;
-        unsigned i;
+        u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
+        unsigned i, len = DIP_HEADER_SIZE + frame->len;
 
-        if (!intel_hdmi->has_hdmi_sink)
-                return;
 
         /* XXX first guess at handling video port, is this corrent? */
         if (intel_hdmi->sdvox_reg == SDVOB)
@@ -98,18 +133,87 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
         else
                 return;
 
-        I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
-                   VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC);
+        flags = intel_infoframe_index(frame);
+
+        val &= ~VIDEO_DIP_SELECT_MASK;
 
-        intel_dip_infoframe_csum(&avi_if);
-        for (i = 0; i < sizeof(avi_if); i += 4) {
+        I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
+
+        for (i = 0; i < len; i += 4) {
                 I915_WRITE(VIDEO_DIP_DATA, *data);
                 data++;
         }
 
-        I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | port |
-                   VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC |
-                   VIDEO_DIP_ENABLE_AVI);
+        flags |= intel_infoframe_flags(frame);
+
+        I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
+}
+
+static void ironlake_write_infoframe(struct drm_encoder *encoder,
+                                     struct dip_infoframe *frame)
+{
+        uint32_t *data = (uint32_t *)frame;
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = encoder->crtc;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+        unsigned i, len = DIP_HEADER_SIZE + frame->len;
+        u32 flags, val = I915_READ(reg);
+
+        intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+        flags = intel_infoframe_index(frame);
+
+        val &= ~VIDEO_DIP_SELECT_MASK;
+
+        I915_WRITE(reg, val | flags);
+
+        for (i = 0; i < len; i += 4) {
+                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+                data++;
+        }
+
+        flags |= intel_infoframe_flags(frame);
+
+        I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+}
+static void intel_set_infoframe(struct drm_encoder *encoder,
+                                struct dip_infoframe *frame)
+{
+        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+
+        if (!intel_hdmi->has_hdmi_sink)
+                return;
+
+        intel_dip_infoframe_csum(frame);
+        intel_hdmi->write_infoframe(encoder, frame);
+}
+
+static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
+{
+        struct dip_infoframe avi_if = {
+                .type = DIP_TYPE_AVI,
+                .ver = DIP_VERSION_AVI,
+                .len = DIP_LEN_AVI,
+        };
+
+        intel_set_infoframe(encoder, &avi_if);
+}
+
+static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
+{
+        struct dip_infoframe spd_if;
+
+        memset(&spd_if, 0, sizeof(spd_if));
+        spd_if.type = DIP_TYPE_SPD;
+        spd_if.ver = DIP_VERSION_SPD;
+        spd_if.len = DIP_LEN_SPD;
+        strcpy(spd_if.body.spd.vn, "Intel");
+        strcpy(spd_if.body.spd.pd, "Integrated gfx");
+        spd_if.body.spd.sdi = DIP_SPD_PC;
+
+        intel_set_infoframe(encoder, &spd_if);
 }
 
 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
@@ -156,6 +260,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
         POSTING_READ(intel_hdmi->sdvox_reg);
 
         intel_hdmi_set_avi_infoframe(encoder);
+        intel_hdmi_set_spd_infoframe(encoder);
 }
 
 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
@@ -433,6 +538,11 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 
         intel_hdmi->sdvox_reg = sdvox_reg;
 
+        if (!HAS_PCH_SPLIT(dev))
+                intel_hdmi->write_infoframe = i9xx_write_infoframe;
+        else
+                intel_hdmi->write_infoframe = ironlake_write_infoframe;
+
         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
 
         intel_hdmi_add_properties(intel_hdmi, connector);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b28f7bd9f88a..2e8ddfcba40c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -690,6 +690,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
         },
         {
                 .callback = intel_no_lvds_dmi_callback,
+                .ident = "Dell OptiPlex FX170",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
+                },
+        },
+        {
+                .callback = intel_no_lvds_dmi_callback,
                 .ident = "AOpen Mini PC",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a06ff07a4d3b..05f500cd9c24 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev,
                         u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
                         if (scaled_width > scaled_height) { /* pillar */
                                 width = scaled_height / mode->vdisplay;
+                                if (width & 1)
+                                        width++;
                                 x = (adjusted_mode->hdisplay - width + 1) / 2;
                                 y = 0;
                                 height = adjusted_mode->vdisplay;
                         } else if (scaled_width < scaled_height) { /* letter */
                                 height = scaled_width / mode->hdisplay;
+                                if (height & 1)
+                                    height++;
                                 y = (adjusted_mode->vdisplay - height + 1) / 2;
                                 x = 0;
                                 width = adjusted_mode->hdisplay;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9615685a39c..47b9b2777038 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1321,6 +1321,9 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
                 ring->get_seqno = pc_render_get_seqno;
         }
 
+        if (!I915_NEED_GFX_HWS(dev))
+                ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
+
         ring->dev = dev;
         INIT_LIST_HEAD(&ring->active_list);
         INIT_LIST_HEAD(&ring->request_list);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 33d12f87f0e0..d515bc8f4ba7 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -205,6 +205,8 @@ struct drm_display_info {
         enum subpixel_order subpixel_order;
         u32 color_formats;
 
+        u8 cea_rev;
+
         char *raw_edid; /* if any */
 };
 
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c4d6dbfa3ff4..28c0d114cb52 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -237,7 +237,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
-#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
+#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
 #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying