diff options
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_ecc.h | 38 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_lcdc.h | 148 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_rstc.h | 39 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_rtt.h | 32 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_shdwc.h | 33 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_wdt.h | 34 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | 78 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | 62 | ||||
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | 134 |
9 files changed, 598 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h new file mode 100644 index 000000000000..fddf256a98d3 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_ecc.h | ||
3 | * | ||
4 | * Error Corrected Code Controller (ECC) - System peripherals regsters. | ||
5 | * Based on AT91SAM9260 datasheet revision B. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_ECC_H | ||
14 | #define AT91_ECC_H | ||
15 | |||
16 | #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ | ||
17 | #define AT91_ECC_RST (1 << 0) /* Reset parity */ | ||
18 | |||
19 | #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ | ||
20 | #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ | ||
21 | #define AT91_ECC_PAGESIZE_528 (0) | ||
22 | #define AT91_ECC_PAGESIZE_1056 (1) | ||
23 | #define AT91_ECC_PAGESIZE_2112 (2) | ||
24 | #define AT91_ECC_PAGESIZE_4224 (3) | ||
25 | |||
26 | #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ | ||
27 | #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ | ||
28 | #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ | ||
29 | #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ | ||
30 | |||
31 | #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ | ||
32 | #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ | ||
33 | #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ | ||
34 | |||
35 | #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ | ||
36 | #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ | ||
37 | |||
38 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_lcdc.h b/include/asm-arm/arch-at91rm9200/at91_lcdc.h new file mode 100644 index 000000000000..9cbfcdd3c471 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_lcdc.h | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_lcdc.h | ||
3 | * | ||
4 | * LCD Controller (LCDC). | ||
5 | * Based on AT91SAM9261 datasheet revision E. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_LCDC_H | ||
14 | #define AT91_LCDC_H | ||
15 | |||
16 | #define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */ | ||
17 | #define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */ | ||
18 | #define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */ | ||
19 | #define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */ | ||
20 | #define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */ | ||
21 | #define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */ | ||
22 | |||
23 | #define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */ | ||
24 | #define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */ | ||
25 | #define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */ | ||
26 | |||
27 | #define AT91_LCDC_DMACON 0x1c /* DMA Control Register */ | ||
28 | #define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */ | ||
29 | #define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */ | ||
30 | #define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */ | ||
31 | |||
32 | #define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */ | ||
33 | #define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */ | ||
34 | #define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */ | ||
35 | #define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */ | ||
36 | |||
37 | #define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */ | ||
38 | #define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */ | ||
39 | #define AT91_LCDC_DISTYPE_STNMONO (0 << 0) | ||
40 | #define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0) | ||
41 | #define AT91_LCDC_DISTYPE_TFT (2 << 0) | ||
42 | #define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */ | ||
43 | #define AT91_LCDC_SCANMOD_SINGLE (0 << 2) | ||
44 | #define AT91_LCDC_SCANMOD_DUAL (1 << 2) | ||
45 | #define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */ | ||
46 | #define AT91_LCDC_IFWIDTH_4 (0 << 3) | ||
47 | #define AT91_LCDC_IFWIDTH_8 (1 << 3) | ||
48 | #define AT91_LCDC_IFWIDTH_16 (2 << 3) | ||
49 | #define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */ | ||
50 | #define AT91_LCDC_PIXELSIZE_1 (0 << 5) | ||
51 | #define AT91_LCDC_PIXELSIZE_2 (1 << 5) | ||
52 | #define AT91_LCDC_PIXELSIZE_4 (2 << 5) | ||
53 | #define AT91_LCDC_PIXELSIZE_8 (3 << 5) | ||
54 | #define AT91_LCDC_PIXELSIZE_16 (4 << 5) | ||
55 | #define AT91_LCDC_PIXELSIZE_24 (5 << 5) | ||
56 | #define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */ | ||
57 | #define AT91_LCDC_INVVD_NORMAL (0 << 8) | ||
58 | #define AT91_LCDC_INVVD_INVERTED (1 << 8) | ||
59 | #define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */ | ||
60 | #define AT91_LCDC_INVFRAME_NORMAL (0 << 9) | ||
61 | #define AT91_LCDC_INVFRAME_INVERTED (1 << 9) | ||
62 | #define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */ | ||
63 | #define AT91_LCDC_INVLINE_NORMAL (0 << 10) | ||
64 | #define AT91_LCDC_INVLINE_INVERTED (1 << 10) | ||
65 | #define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */ | ||
66 | #define AT91_LCDC_INVCLK_NORMAL (0 << 11) | ||
67 | #define AT91_LCDC_INVCLK_INVERTED (1 << 11) | ||
68 | #define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */ | ||
69 | #define AT91_LCDC_INVDVAL_NORMAL (0 << 12) | ||
70 | #define AT91_LCDC_INVDVAL_INVERTED (1 << 12) | ||
71 | #define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */ | ||
72 | #define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) | ||
73 | #define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) | ||
74 | #define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */ | ||
75 | #define AT91_LCDC_MEMOR_BIG (0 << 31) | ||
76 | #define AT91_LCDC_MEMOR_LITTLE (1 << 31) | ||
77 | |||
78 | #define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */ | ||
79 | #define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */ | ||
80 | #define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */ | ||
81 | #define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */ | ||
82 | #define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */ | ||
83 | |||
84 | #define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */ | ||
85 | #define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */ | ||
86 | #define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */ | ||
87 | #define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */ | ||
88 | |||
89 | #define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */ | ||
90 | #define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */ | ||
91 | #define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */ | ||
92 | |||
93 | #define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */ | ||
94 | #define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */ | ||
95 | |||
96 | #define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */ | ||
97 | #define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */ | ||
98 | #define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */ | ||
99 | #define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */ | ||
100 | #define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */ | ||
101 | #define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */ | ||
102 | #define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */ | ||
103 | #define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */ | ||
104 | #define AT91_LCDC_DP1_2_VAL (0xff) | ||
105 | #define AT91_LCDC_DP4_7_VAL (0xfffffff) | ||
106 | #define AT91_LCDC_DP3_5_VAL (0xfffff) | ||
107 | #define AT91_LCDC_DP2_3_VAL (0xfff) | ||
108 | #define AT91_LCDC_DP5_7_VAL (0xfffffff) | ||
109 | #define AT91_LCDC_DP3_4_VAL (0xffff) | ||
110 | #define AT91_LCDC_DP4_5_VAL (0xfffff) | ||
111 | #define AT91_LCDC_DP6_7_VAL (0xfffffff) | ||
112 | |||
113 | #define AT91_LCDC_PWRCON 0x083c /* Power Control Register */ | ||
114 | #define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */ | ||
115 | #define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */ | ||
116 | #define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */ | ||
117 | |||
118 | #define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */ | ||
119 | #define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */ | ||
120 | #define AT91_LCDC_PS_DIV1 (0 << 0) | ||
121 | #define AT91_LCDC_PS_DIV2 (1 << 0) | ||
122 | #define AT91_LCDC_PS_DIV4 (2 << 0) | ||
123 | #define AT91_LCDC_PS_DIV8 (3 << 0) | ||
124 | #define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */ | ||
125 | #define AT91_LCDC_POL_NEGATIVE (0 << 2) | ||
126 | #define AT91_LCDC_POL_POSITIVE (1 << 2) | ||
127 | #define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */ | ||
128 | #define AT91_LCDC_ENA_PWMDISABLE (0 << 3) | ||
129 | #define AT91_LCDC_ENA_PWMENABLE (1 << 3) | ||
130 | |||
131 | #define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */ | ||
132 | #define AT91_LCDC_CVAL (0xff) /* PWM compare value */ | ||
133 | |||
134 | #define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */ | ||
135 | #define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */ | ||
136 | #define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */ | ||
137 | #define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */ | ||
138 | #define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */ | ||
139 | #define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */ | ||
140 | #define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */ | ||
141 | #define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */ | ||
142 | #define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */ | ||
143 | #define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */ | ||
144 | #define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */ | ||
145 | |||
146 | #define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */ | ||
147 | |||
148 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rstc.h b/include/asm-arm/arch-at91rm9200/at91_rstc.h new file mode 100644 index 000000000000..ccdc52da973d --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rstc.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_rstc.h | ||
3 | * | ||
4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_RSTC_H | ||
14 | #define AT91_RSTC_H | ||
15 | |||
16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
20 | #define AT01_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
21 | |||
22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
32 | |||
33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
37 | #define AT91_RSTC_KEY (0xff << 24) /* KEY Password */ | ||
38 | |||
39 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtt.h b/include/asm-arm/arch-at91rm9200/at91_rtt.h new file mode 100644 index 000000000000..c6751ba3cccc --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_rtt.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_rtt.h | ||
3 | * | ||
4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_RTT_H | ||
14 | #define AT91_RTT_H | ||
15 | |||
16 | #define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ | ||
17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
21 | |||
22 | #define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ | ||
23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
24 | |||
25 | #define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ | ||
26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
27 | |||
28 | #define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ | ||
29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
31 | |||
32 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_shdwc.h b/include/asm-arm/arch-at91rm9200/at91_shdwc.h new file mode 100644 index 000000000000..0439250553c9 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_shdwc.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_shdwc.h | ||
3 | * | ||
4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_SHDWC_H | ||
14 | #define AT91_SHDWC_H | ||
15 | |||
16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
17 | #define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ | ||
18 | #define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ | ||
19 | |||
20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
27 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
28 | |||
29 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
30 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
31 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
32 | |||
33 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91_wdt.h b/include/asm-arm/arch-at91rm9200/at91_wdt.h new file mode 100644 index 000000000000..ac63e775772c --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_wdt.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_wdt.h | ||
3 | * | ||
4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91_WDT_H | ||
14 | #define AT91_WDT_H | ||
15 | |||
16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
18 | #define AT91_WDT_KEY (0xff << 24) /* KEY Password */ | ||
19 | |||
20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
29 | |||
30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
33 | |||
34 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h new file mode 100644 index 000000000000..746d973705bf --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h | ||
3 | * | ||
4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
5 | * Based on AT91SAM9260 datasheet revision B. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91SAM9260_MATRIX_H | ||
14 | #define AT91SAM9260_MATRIX_H | ||
15 | |||
16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */ | ||
22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
28 | |||
29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
43 | |||
44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
55 | |||
56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
59 | |||
60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
70 | #define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ | ||
71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
77 | |||
78 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h new file mode 100644 index 000000000000..270a5dcdf1cd --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h | ||
3 | * | ||
4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91SAM9261_MATRIX_H | ||
14 | #define AT91SAM9261_MATRIX_H | ||
15 | |||
16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
18 | #define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
19 | |||
20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
31 | |||
32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
43 | |||
44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
58 | |||
59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
61 | |||
62 | #endif | ||
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h new file mode 100644 index 000000000000..7d94968b5d57 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | ||
3 | * | ||
4 | * Memory Controllers (SMC, SDRAMC) - System peripherals registers. | ||
5 | * Based on AT91SAM9261 datasheet revision D. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef AT91SAM926x_MC_H | ||
14 | #define AT91SAM926x_MC_H | ||
15 | |||
16 | /* SDRAM Controller (SDRAMC) registers */ | ||
17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
26 | |||
27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
29 | |||
30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
56 | |||
57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */ | ||
66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
70 | |||
71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
76 | |||
77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
81 | |||
82 | |||
83 | /* Static Memory Controller (SMC) registers */ | ||
84 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
85 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
86 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
87 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
88 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
89 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
90 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
91 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
92 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
93 | |||
94 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
95 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
96 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
97 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
98 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
99 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
100 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
101 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
102 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
103 | |||
104 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
105 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
106 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
107 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
108 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
109 | |||
110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
113 | #define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ | ||
114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 5) | ||
115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 5) | ||
116 | #define AT91_SMC_EXNWMODE_READY (3 << 5) | ||
117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
118 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
119 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
120 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
121 | #define AT91_SMC_DBW_8 (0 << 12) | ||
122 | #define AT91_SMC_DBW_16 (1 << 12) | ||
123 | #define AT91_SMC_DBW_32 (2 << 12) | ||
124 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
125 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
126 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
127 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
128 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
129 | #define AT91_SMC_PS_4 (0 << 28) | ||
130 | #define AT91_SMC_PS_8 (1 << 28) | ||
131 | #define AT91_SMC_PS_16 (2 << 28) | ||
132 | #define AT91_SMC_PS_32 (3 << 28) | ||
133 | |||
134 | #endif | ||