826 files changed, 65680 insertions, 12522 deletions

diff --git a/CREDITS b/CREDITS
index abe05a0be4ed..939da46a87fb 100644
--- a/CREDITS
+++ b/CREDITS
@@ -464,6 +464,11 @@ S: 1200 Goldenrod Dr.
 S: Nampa, Idaho 83686
 S: USA
 
+N: Dirk J. Brandewie
+E: dirk.j.brandewie@intel.com
+E: linux-wimax@intel.com
+D: Intel Wireless WiMAX Connection 2400 SDIO driver
+
 N: Derrick J. Brashear
 E: shadow@dementia.org
 W: http://www.dementia.org/~shadow
@@ -1681,7 +1686,7 @@ E: ajoshi@shell.unixbox.com
 D: fbdev hacking
 
 N: Jesper Juhl
-E: jesper.juhl@gmail.com
+E: jj@chaosbits.net
 D: Various fixes, cleanups and minor features all over the tree.
 D: Wrote initial version of the hdaps driver (since passed on to others).
 S: Lemnosvej 1, 3.tv
@@ -2119,6 +2124,11 @@ N: H.J. Lu
 E: hjl@gnu.ai.mit.edu
 D: GCC + libraries hacker
 
+N: Yanir Lubetkin
+E: yanirx.lubatkin@intel.com
+E: linux-wimax@intel.com
+D: Intel Wireless WiMAX Connection 2400 driver
+
 N: Michal Ludvig
 E: michal@logix.cz
 E: michal.ludvig@asterisk.co.nz
@@ -2693,6 +2703,13 @@ S: RR #5, 497 Pole Line Road
 S: Thunder Bay, Ontario
 S: CANADA P7C 5M9
 
+N: Inaky Perez-Gonzalez
+E: inaky.perez-gonzalez@intel.com
+E: linux-wimax@intel.com
+E: inakypg@yahoo.com
+D: WiMAX stack
+D: Intel Wireless WiMAX Connection 2400 driver
+
 N: Yuri Per
 E: yuri@pts.mipt.ru
 D: Some smbfs fixes
diff --git a/Documentation/DocBook/networking.tmpl b/Documentation/DocBook/networking.tmpl
index 627707a3cb9d..59ad69a9d777 100644
--- a/Documentation/DocBook/networking.tmpl
+++ b/Documentation/DocBook/networking.tmpl
@@ -74,6 +74,14 @@
 !Enet/sunrpc/rpcb_clnt.c
 !Enet/sunrpc/clnt.c
      </sect1>
+     <sect1><title>WiMAX</title>
+!Enet/wimax/op-msg.c
+!Enet/wimax/op-reset.c
+!Enet/wimax/op-rfkill.c
+!Enet/wimax/stack.c
+!Iinclude/net/wimax.h
+!Iinclude/linux/wimax.h
+     </sect1>
   </chapter>
 
   <chapter id="netdev">
diff --git a/Documentation/blackfin/00-INDEX b/Documentation/blackfin/00-INDEX
index 7cb3b356b249..d6840a91e1e1 100644
--- a/Documentation/blackfin/00-INDEX
+++ b/Documentation/blackfin/00-INDEX
@@ -9,3 +9,6 @@ cachefeatures.txt
 
 Filesystems
         - Requirements for mounting the root file system.
+
+bfin-gpio-note.txt
+        - Notes in developing/using bfin-gpio driver.
diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt
new file mode 100644
index 000000000000..9898c7ded7d3
--- /dev/null
+++ b/Documentation/blackfin/bfin-gpio-notes.txt
@@ -0,0 +1,71 @@
+/*
+ * File:         Documentation/blackfin/bfin-gpio-note.txt
+ * Based on:
+ * Author:
+ *
+ * Created:      $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $
+ * Description:  This file contains the notes in developing/using bfin-gpio.
+ *
+ *
+ * Rev:
+ *
+ * Modified:
+ *               Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ */
+
+
+1. Blackfin GPIO introduction
+
+    There are many GPIO pins on Blackfin. Most of these pins are muxed to
+    multi-functions. They can be configured as peripheral, or just as GPIO,
+    configured to input with interrupt enabled, or output.
+
+    For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c",
+    or the relevant HRM.
+
+
+2. Avoiding resource conflict
+
+    Followed function groups are used to avoiding resource conflict,
+    - Use the pin as peripheral,
+        int peripheral_request(unsigned short per, const char *label);
+        int peripheral_request_list(const unsigned short per[], const char *label);
+        void peripheral_free(unsigned short per);
+        void peripheral_free_list(const unsigned short per[]);
+    - Use the pin as GPIO,
+        int bfin_gpio_request(unsigned gpio, const char *label);
+        void bfin_gpio_free(unsigned gpio);
+    - Use the pin as GPIO interrupt,
+        int bfin_gpio_irq_request(unsigned gpio, const char *label);
+        void bfin_gpio_irq_free(unsigned gpio);
+
+    The request functions will record the function state for a certain pin,
+    the free functions will clear it's function state.
+    Once a pin is requested, it can't be requested again before it is freed by
+    previous caller, otherwise kernel will dump stacks, and the request
+    function fail.
+    These functions are wrapped by other functions, most of the users need not
+    care.
+
+
+3. But there are some exceptions
+    - Kernel permit the identical GPIO be requested both as GPIO and GPIO
+    interrut.
+    Some drivers, like gpio-keys, need this behavior. Kernel only print out
+    warning messages like,
+        bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are
+configuring it as IRQ!
+
+        Note: Consider the case that, if there are two drivers need the
+        identical GPIO, one of them use it as GPIO, the other use it as
+        GPIO interrupt. This will really cause resource conflict. So if
+        there is any abnormal driver behavior, please check the bfin-gpio
+        warning messages.
+
+    - Kernel permit the identical GPIO be requested from the same driver twice.
+
+
+
diff --git a/Documentation/dell_rbu.txt b/Documentation/dell_rbu.txt
index 2c0d631de0cf..c11b931f8f98 100644
--- a/Documentation/dell_rbu.txt
+++ b/Documentation/dell_rbu.txt
@@ -81,8 +81,8 @@ Until this step is completed the driver cannot be unloaded.
 Also echoing either mono ,packet or init in to image_type will free up the
 memory allocated by the driver.
 
-If an user by accident executes steps 1 and 3 above without executing step 2;
-it will make the /sys/class/firmware/dell_rbu/ entries to disappear.
+If a user by accident executes steps 1 and 3 above without executing step 2;
+it will make the /sys/class/firmware/dell_rbu/ entries disappear.
 The entries can be recreated by doing the following
 echo init > /sys/devices/platform/dell_rbu/image_type
 NOTE: echoing init in image_type does not change it original value.
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 2193be53e773..5ddbe350487a 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -318,6 +318,14 @@ Who:	Jean Delvare <khali@linux-fr.org>
 
 ---------------------------
 
+What:   fscher and fscpos drivers
+When:   June 2009
+Why:    Deprecated by the new fschmd driver.
+Who:    Hans de Goede <hdegoede@redhat.com>
+        Jean Delvare <khali@linux-fr.org>
+
+---------------------------
+
 What:   SELinux "compat_net" functionality
 When:   2.6.30 at the earliest
 Why:    In 2.6.18 the Secmark concept was introduced to replace the "compat_net"
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
index 32e94635484f..d105eb45282a 100644
--- a/Documentation/filesystems/proc.txt
+++ b/Documentation/filesystems/proc.txt
@@ -140,6 +140,7 @@ Table 1-1: Process specific entries in /proc
  statm          Process memory status information
  status         Process status in human readable form
  wchan          If CONFIG_KALLSYMS is set, a pre-decoded wchan
+ stack          Report full stack trace, enable via CONFIG_STACKTRACE
  smaps          Extension based on maps, the rss size for each mapped file
 ..............................................................................
 
diff --git a/Documentation/hwmon/abituguru-datasheet b/Documentation/hwmon/abituguru-datasheet
index aef5a9b36846..4d184f2db0ea 100644
--- a/Documentation/hwmon/abituguru-datasheet
+++ b/Documentation/hwmon/abituguru-datasheet
@@ -74,7 +74,7 @@ a sensor.
 Notice that some banks have both a read and a write address this is how the
 uGuru determines if a read from or a write to the bank is taking place, thus
 when reading you should always use the read address and when writing the
-write address. The write address is always one (1) more then the read address.
+write address. The write address is always one (1) more than the read address.
 
 
 uGuru ready
@@ -224,7 +224,7 @@ Bit 3: Beep if alarm							(RW)
 Bit 4: 1 if alarm cause measured temp is over the warning threshold     (R)
 Bit 5: 1 if alarm cause measured volt is over the max threshold         (R)
 Bit 6: 1 if alarm cause measured volt is under the min threshold        (R)
-Bit 7: Volt sensor: Shutdown if alarm persist for more then 4 seconds   (RW)
+Bit 7: Volt sensor: Shutdown if alarm persist for more than 4 seconds   (RW)
        Temp sensor: Shutdown if temp is over the shutdown threshold     (RW)
 
 *  This bit is only honored/used by the uGuru if a temp sensor is connected
@@ -293,7 +293,7 @@ Byte 0:
 Alarm behaviour for the selected sensor. A 1 enables the described behaviour.
 Bit 0: Give an alarm if measured rpm is under the min threshold (RW)
 Bit 3: Beep if alarm                                            (RW)
-Bit 7: Shutdown if alarm persist for more then 4 seconds        (RW)
+Bit 7: Shutdown if alarm persist for more than 4 seconds        (RW)
 
 Byte 1:
 min threshold (scale as bank 0x26)
diff --git a/Documentation/hwmon/f71882fg b/Documentation/hwmon/f71882fg
new file mode 100644
index 000000000000..a8321267b5b6
--- /dev/null
+++ b/Documentation/hwmon/f71882fg
@@ -0,0 +1,89 @@
+Kernel driver f71882fg
+======================
+
+Supported chips:
+  * Fintek F71882FG and F71883FG
+    Prefix: 'f71882fg'
+    Addresses scanned: none, address read from Super I/O config space
+    Datasheet: Available from the Fintek website
+  * Fintek F71862FG and F71863FG
+    Prefix: 'f71862fg'
+    Addresses scanned: none, address read from Super I/O config space
+    Datasheet: Available from the Fintek website
+  * Fintek F8000
+    Prefix: 'f8000'
+    Addresses scanned: none, address read from Super I/O config space
+    Datasheet: Not public
+
+Author: Hans de Goede <hdegoede@redhat.com>
+
+
+Description
+-----------
+
+Fintek F718xxFG/F8000 Super I/O chips include complete hardware monitoring
+capabilities. They can monitor up to 9 voltages (3 for the F8000), 4 fans and
+3 temperature sensors.
+
+These chips also have fan controlling features, using either DC or PWM, in
+three different modes (one manual, two automatic).
+
+The driver assumes that no more than one chip is present, which seems
+reasonable.
+
+
+Monitoring
+----------
+
+The Voltage, Fan and Temperature Monitoring uses the standard sysfs
+interface as documented in sysfs-interface, without any exceptions.
+
+
+Fan Control
+-----------
+
+Both PWM (pulse-width modulation) and DC fan speed control methods are
+supported. The right one to use depends on external circuitry on the
+motherboard, so the driver assumes that the BIOS set the method
+properly.
+
+There are 2 modes to specify the speed of the fan, PWM duty cycle (or DC
+voltage) mode, where 0-100% duty cycle (0-100% of 12V) is specified. And RPM
+mode where the actual RPM of the fan (as measured) is controlled and the speed
+gets specified as 0-100% of the fan#_full_speed file.
+
+Since both modes work in a 0-100% (mapped to 0-255) scale, there isn't a
+whole lot of a difference when modifying fan control settings. The only
+important difference is that in RPM mode the 0-100% controls the fan speed
+between 0-100% of fan#_full_speed. It is assumed that if the BIOS programs
+RPM mode, it will also set fan#_full_speed properly, if it does not then
+fan control will not work properly, unless you set a sane fan#_full_speed
+value yourself.
+
+Switching between these modes requires re-initializing a whole bunch of
+registers, so the mode which the BIOS has set is kept. The mode is
+printed when loading the driver.
+
+Three different fan control modes are supported; the mode number is written
+to the pwm#_enable file. Note that not all modes are supported on all
+chips, and some modes may only be available in RPM / PWM mode on the F8000.
+Writing an unsupported mode will result in an invalid parameter error.
+
+* 1: Manual mode
+  You ask for a specific PWM duty cycle / DC voltage or a specific % of
+  fan#_full_speed by writing to the pwm# file. This mode is only
+  available on the F8000 if the fan channel is in RPM mode.
+
+* 2: Normal auto mode
+  You can define a number of temperature/fan speed trip points, which % the
+  fan should run at at this temp and which temp a fan should follow using the
+  standard sysfs interface. The number and type of trip points is chip
+  depended, see which files are available in sysfs.
+  Fan/PWM channel 3 of the F8000 is always in this mode!
+
+* 3: Thermostat mode (Only available on the F8000 when in duty cycle mode)
+  The fan speed is regulated to keep the temp the fan is mapped to between
+  temp#_auto_point2_temp and temp#_auto_point3_temp.
+
+Both of the automatic modes require that pwm1 corresponds to fan1, pwm2 to
+fan2 and pwm3 to fan3.
diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87
index 042c0415140b..659315d98e00 100644
--- a/Documentation/hwmon/it87
+++ b/Documentation/hwmon/it87
@@ -26,6 +26,10 @@ Supported chips:
     Datasheet: Publicly available at the ITE website
                http://www.ite.com.tw/product_info/file/pc/IT8718F_V0.2.zip
                http://www.ite.com.tw/product_info/file/pc/IT8718F_V0%203_(for%20C%20version).zip
+  * IT8720F
+    Prefix: 'it8720'
+    Addresses scanned: from Super I/O config space (8 I/O ports)
+    Datasheet: Not yet publicly available.
   * SiS950   [clone of IT8705F]
     Prefix: 'it87'
     Addresses scanned: from Super I/O config space (8 I/O ports)
@@ -71,7 +75,7 @@ Description
 -----------
 
 This driver implements support for the IT8705F, IT8712F, IT8716F,
-IT8718F, IT8726F and SiS950 chips.
+IT8718F, IT8720F, IT8726F and SiS950 chips.
 
 These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
 joysticks and other miscellaneous stuff. For hardware monitoring, they
@@ -84,19 +88,19 @@ the IT8716F and late IT8712F have 6. They are shared with other functions
 though, so the functionality may not be available on a given system.
 The driver dumbly assume it is there.
 
-The IT8718F also features VID inputs (up to 8 pins) but the value is
-stored in the Super-I/O configuration space. Due to technical limitations,
+The IT8718F and IT8720F also features VID inputs (up to 8 pins) but the value
+is stored in the Super-I/O configuration space. Due to technical limitations,
 this value can currently only be read once at initialization time, so
 the driver won't notice and report changes in the VID value. The two
 upper VID bits share their pins with voltage inputs (in5 and in6) so you
 can't have both on a given board.
 
-The IT8716F, IT8718F and later IT8712F revisions have support for
+The IT8716F, IT8718F, IT8720F and later IT8712F revisions have support for
 2 additional fans. The additional fans are supported by the driver.
 
-The IT8716F and IT8718F, and late IT8712F and IT8705F also have optional
-16-bit tachometer counters for fans 1 to 3. This is better (no more fan
-clock divider mess) but not compatible with the older chips and
+The IT8716F, IT8718F and IT8720F, and late IT8712F and IT8705F also have
+optional 16-bit tachometer counters for fans 1 to 3. This is better (no more
+fan clock divider mess) but not compatible with the older chips and
 revisions. The 16-bit tachometer mode is enabled by the driver when one
 of the above chips is detected.
 
@@ -122,7 +126,7 @@ zero'; this is important for negative voltage measurements. All voltage
 inputs can measure voltages between 0 and 4.08 volts, with a resolution of
 0.016 volt. The battery voltage in8 does not have limit registers.
 
-The VID lines (IT8712F/IT8716F/IT8718F) encode the core voltage value:
+The VID lines (IT8712F/IT8716F/IT8718F/IT8720F) encode the core voltage value:
 the voltage level your processor should work with. This is hardcoded by
 the mainboard and/or processor itself. It is a value in volts.
 
diff --git a/Documentation/hwmon/lm70 b/Documentation/hwmon/lm70
index 2bdd3feebf53..0d240291e3cc 100644
--- a/Documentation/hwmon/lm70
+++ b/Documentation/hwmon/lm70
@@ -1,9 +1,11 @@
 Kernel driver lm70
 ==================
 
-Supported chip:
+Supported chips:
   * National Semiconductor LM70
     Datasheet: http://www.national.com/pf/LM/LM70.html
+  * Texas Instruments TMP121/TMP123
+    Information: http://focus.ti.com/docs/prod/folders/print/tmp121.html
 
 Author:
         Kaiwan N Billimoria <kaiwan@designergraphix.com>
@@ -25,6 +27,14 @@ complement digital temperature (sent via the SIO line), is available in the
 driver for interpretation. This driver makes use of the kernel's in-core
 SPI support.
 
+As a real (in-tree) example of this "SPI protocol driver" interfacing
+with a "SPI master controller driver", see drivers/spi/spi_lm70llp.c
+and its associated documentation.
+
+The TMP121/TMP123 are very similar; main differences are 4 wire SPI inter-
+face (read only) and 13-bit temperature data (0.0625 degrees celsius reso-
+lution).
+
 Thanks to
 ---------
 Jean Delvare <khali@linux-fr.org> for mentoring the hwmon-side driver
diff --git a/Documentation/hwmon/lm85 b/Documentation/hwmon/lm85
index 400620741290..a13680871bc7 100644
--- a/Documentation/hwmon/lm85
+++ b/Documentation/hwmon/lm85
@@ -164,7 +164,7 @@ configured individually according to the following options.
                       temperature. (PWM value from 0 to 255)
 
 * pwm#_auto_pwm_minctl - this flags selects for temp#_auto_temp_off temperature
-                         the bahaviour of fans. Write 1 to let fans spinning at
+                         the behaviour of fans. Write 1 to let fans spinning at
                          pwm#_auto_pwm_min or write 0 to let them off.
 
 NOTE: It has been reported that there is a bug in the LM85 that causes the flag
diff --git a/Documentation/hwmon/ltc4245 b/Documentation/hwmon/ltc4245
new file mode 100644
index 000000000000..bae7a3adc5d8
--- /dev/null
+++ b/Documentation/hwmon/ltc4245
@@ -0,0 +1,81 @@
+Kernel driver ltc4245
+=====================
+
+Supported chips:
+  * Linear Technology LTC4245
+    Prefix: 'ltc4245'
+    Addresses scanned: 0x20-0x3f
+    Datasheet:
+        http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1006,C1140,P19392,D13517
+
+Author: Ira W. Snyder <iws@ovro.caltech.edu>
+
+
+Description
+-----------
+
+The LTC4245 controller allows a board to be safely inserted and removed
+from a live backplane in multiple supply systems such as CompactPCI and
+PCI Express.
+
+
+Usage Notes
+-----------
+
+This driver does not probe for LTC4245 devices, due to the fact that some
+of the possible addresses are unfriendly to probing. You will need to use
+the "force" parameter to tell the driver where to find the device.
+
+Example: the following will load the driver for an LTC4245 at address 0x23
+on I2C bus #1:
+$ modprobe ltc4245 force=1,0x23
+
+
+Sysfs entries
+-------------
+
+The LTC4245 has built-in limits for over and under current warnings. This
+makes it very likely that the reference circuit will be used.
+
+This driver uses the values in the datasheet to change the register values
+into the values specified in the sysfs-interface document. The current readings
+rely on the sense resistors listed in Table 2: "Sense Resistor Values".
+
+in1_input               12v input voltage (mV)
+in2_input               5v  input voltage (mV)
+in3_input               3v  input voltage (mV)
+in4_input               Vee (-12v) input voltage (mV)
+
+in1_min_alarm           12v input undervoltage alarm
+in2_min_alarm           5v  input undervoltage alarm
+in3_min_alarm           3v  input undervoltage alarm
+in4_min_alarm           Vee (-12v) input undervoltage alarm
+
+curr1_input             12v current (mA)
+curr2_input             5v  current (mA)
+curr3_input             3v  current (mA)
+curr4_input             Vee (-12v) current (mA)
+
+curr1_max_alarm         12v overcurrent alarm
+curr2_max_alarm         5v  overcurrent alarm
+curr3_max_alarm         3v  overcurrent alarm
+curr4_max_alarm         Vee (-12v) overcurrent alarm
+
+in5_input               12v output voltage (mV)
+in6_input               5v  output voltage (mV)
+in7_input               3v  output voltage (mV)
+in8_input               Vee (-12v) output voltage (mV)
+
+in5_min_alarm           12v output undervoltage alarm
+in6_min_alarm           5v  output undervoltage alarm
+in7_min_alarm           3v  output undervoltage alarm
+in8_min_alarm           Vee (-12v) output undervoltage alarm
+
+in9_input               GPIO #1 voltage data
+in10_input              GPIO #2 voltage data
+in11_input              GPIO #3 voltage data
+
+power1_input            12v power usage (mW)
+power2_input            5v  power usage (mW)
+power3_input            3v  power usage (mW)
+power4_input            Vee (-12v) power usage (mW)
diff --git a/Documentation/kbuild/kbuild.txt b/Documentation/kbuild/kbuild.txt
index 51771847e816..923f9ddee8f6 100644
--- a/Documentation/kbuild/kbuild.txt
+++ b/Documentation/kbuild/kbuild.txt
@@ -124,3 +124,10 @@ KBUILD_EXTRA_SYMBOLS
 --------------------------------------------------
 For modules use symbols from another modules.
 See more details in modules.txt.
+
+ALLSOURCE_ARCHS
+--------------------------------------------------
+For tags/TAGS/cscope targets, you can specify more than one archs
+to be included in the databases, separated by blankspace. e.g.
+
+    $ make ALLSOURCE_ARCHS="x86 mips arm" tags
diff --git a/Documentation/kbuild/modules.txt b/Documentation/kbuild/modules.txt
index 1821c077b435..b1096da953c8 100644
--- a/Documentation/kbuild/modules.txt
+++ b/Documentation/kbuild/modules.txt
@@ -253,7 +253,7 @@ following files:
 
                 # Module specific targets
                 genbin:
-                        echo "X" > 8123_bin_shipped
+                        echo "X" > 8123_bin.o_shipped
 
 
         In example 2, we are down to two fairly simple files and for simple
@@ -279,7 +279,7 @@ following files:
 
                 # Module specific targets
                 genbin:
-                        echo "X" > 8123_bin_shipped
+                        echo "X" > 8123_bin.o_shipped
 
                 endif
 
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 0072fabb1dd1..532eacbbed62 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -91,6 +91,7 @@ parameter is applicable:
         SUSPEND System suspend states are enabled.
         FTRACE  Function tracing enabled.
         TS      Appropriate touchscreen support is enabled.
+        UMS     USB Mass Storage support is enabled.
         USB     USB support is enabled.
         USBHID  USB Human Interface Device support is enabled.
         V4L     Video For Linux support is enabled.
@@ -2387,6 +2388,41 @@ and is between 256 and 4096 characters. It is defined in the file
         usbhid.mousepoll=
                         [USBHID] The interval which mice are to be polled at.
 
+        usb-storage.delay_use=
+                        [UMS] The delay in seconds before a new device is
+                        scanned for Logical Units (default 5).
+
+        usb-storage.quirks=
+                        [UMS] A list of quirks entries to supplement or
+                        override the built-in unusual_devs list.  List
+                        entries are separated by commas.  Each entry has
+                        the form VID:PID:Flags where VID and PID are Vendor
+                        and Product ID values (4-digit hex numbers) and
+                        Flags is a set of characters, each corresponding
+                        to a common usb-storage quirk flag as follows:
+                                a = SANE_SENSE (collect more than 18 bytes
+                                        of sense data);
+                                c = FIX_CAPACITY (decrease the reported
+                                        device capacity by one sector);
+                                h = CAPACITY_HEURISTICS (decrease the
+                                        reported device capacity by one
+                                        sector if the number is odd);
+                                i = IGNORE_DEVICE (don't bind to this
+                                        device);
+                                l = NOT_LOCKABLE (don't try to lock and
+                                        unlock ejectable media);
+                                m = MAX_SECTORS_64 (don't transfer more
+                                        than 64 sectors = 32 KB at a time);
+                                o = CAPACITY_OK (accept the capacity
+                                        reported by the device);
+                                r = IGNORE_RESIDUE (the device reports
+                                        bogus residue values);
+                                s = SINGLE_LUN (the device has only one
+                                        Logical Unit);
+                                w = NO_WP_DETECT (don't test whether the
+                                        medium is write-protected).
+                        Example: quirks=0419:aaf5:rl,0421:0433:rc
+
         add_efi_memmap  [EFI; x86-32,X86-64] Include EFI memory map in
                         kernel's map of available physical RAM.
 
diff --git a/Documentation/laptops/thinkpad-acpi.txt b/Documentation/laptops/thinkpad-acpi.txt
index 71f0fe1fc1b0..898b4987bb80 100644
--- a/Documentation/laptops/thinkpad-acpi.txt
+++ b/Documentation/laptops/thinkpad-acpi.txt
@@ -1475,7 +1475,7 @@ Sysfs interface changelog:
 
 0x020100:       Marker for thinkpad-acpi with hot key NVRAM polling
                 support.  If you must, use it to know you should not
-                start an userspace NVRAM poller (allows to detect when
+                start a userspace NVRAM poller (allows to detect when
                 NVRAM is compiled out by the user because it is
                 unneeded/undesired in the first place).
 0x020101:       Marker for thinkpad-acpi with hot key NVRAM polling
diff --git a/Documentation/networking/rxrpc.txt b/Documentation/networking/rxrpc.txt
index c3669a3fb4af..60d05eb77c64 100644
--- a/Documentation/networking/rxrpc.txt
+++ b/Documentation/networking/rxrpc.txt
@@ -540,7 +540,7 @@ A client would issue an operation by:
      MSG_MORE should be set in msghdr::msg_flags on all but the last part of
      the request.  Multiple requests may be made simultaneously.
 
-     If a call is intended to go to a destination other then the default
+     If a call is intended to go to a destination other than the default
      specified through connect(), then msghdr::msg_name should be set on the
      first request message of that call.
 
diff --git a/Documentation/networking/tuntap.txt b/Documentation/networking/tuntap.txt
index 839cbb71388b..c0aab985bad9 100644
--- a/Documentation/networking/tuntap.txt
+++ b/Documentation/networking/tuntap.txt
@@ -118,7 +118,7 @@ As mentioned above, main purpose of TUN/TAP driver is tunneling.
 It is used by VTun (http://vtun.sourceforge.net).
 
 Another interesting application using TUN/TAP is pipsecd
-(http://perso.enst.fr/~beyssac/pipsec/), an userspace IPSec
+(http://perso.enst.fr/~beyssac/pipsec/), a userspace IPSec
 implementation that can use complete kernel routing (unlike FreeS/WAN).
 
 3. How does Virtual network device actually work ? 
diff --git a/Documentation/scsi/ChangeLog.lpfc b/Documentation/scsi/ChangeLog.lpfc
index ae3f962a7cfc..ff19a52fe004 100644
--- a/Documentation/scsi/ChangeLog.lpfc
+++ b/Documentation/scsi/ChangeLog.lpfc
@@ -733,7 +733,7 @@ Changes from 20040920 to 20041018
           I/O completion path a little more, especially taking care of
           fast-pathing the non-error case.  Also removes tons of dead
           members and defines from lpfc_scsi.h - e.g. lpfc_target is down
-          to nothing more then the lpfc_nodelist pointer.
+          to nothing more than the lpfc_nodelist pointer.
         * Added binary sysfs file to issue mbox commands
         * Replaced #if __BIG_ENDIAN with #if __BIG_ENDIAN_BITFIELD for
           compatibility with the user space applications.
diff --git a/Documentation/scsi/ChangeLog.ncr53c8xx b/Documentation/scsi/ChangeLog.ncr53c8xx
index a9f721aeb11c..8b278c10edfd 100644
--- a/Documentation/scsi/ChangeLog.ncr53c8xx
+++ b/Documentation/scsi/ChangeLog.ncr53c8xx
@@ -19,7 +19,7 @@ Sun Sep 24 21:30 2000 Gerard Roudier (groudier@club-internet.fr)
 
 Wed Jul 26 23:30 2000 Gerard Roudier (groudier@club-internet.fr)
         * version ncr53c8xx-3.4.1
-        - Provide OpenFirmare path through the proc FS on PPC.
+        - Provide OpenFirmware path through the proc FS on PPC.
         - Remove trailing argument #2 from a couple of #undefs.
 
 Sun Jul 09 16:30 2000 Gerard Roudier (groudier@club-internet.fr)
diff --git a/Documentation/scsi/ChangeLog.sym53c8xx b/Documentation/scsi/ChangeLog.sym53c8xx
index ef985ec348e6..02ffbc1e8a84 100644
--- a/Documentation/scsi/ChangeLog.sym53c8xx
+++ b/Documentation/scsi/ChangeLog.sym53c8xx
@@ -81,7 +81,7 @@ Sun Sep 24 21:30 2000 Gerard Roudier (groudier@club-internet.fr)
 
 Wed Jul 26 23:30 2000 Gerard Roudier (groudier@club-internet.fr)
         * version sym53c8xx-1.7.1
-        - Provide OpenFirmare path through the proc FS on PPC.
+        - Provide OpenFirmware path through the proc FS on PPC.
         - Download of on-chip SRAM using memcpy_toio() doesn't work 
           on PPC. Restore previous method (MEMORY MOVE from SCRIPTS).
         - Remove trailing argument #2 from a couple of #undefs.
diff --git a/Documentation/spi/spi-lm70llp b/Documentation/spi/spi-lm70llp
index 154bd02220b9..34a9cfd746bd 100644
--- a/Documentation/spi/spi-lm70llp
+++ b/Documentation/spi/spi-lm70llp
@@ -13,10 +13,20 @@ Description
 This driver provides glue code connecting a National Semiconductor LM70 LLP
 temperature sensor evaluation board to the kernel's SPI core subsystem.
 
+This is a SPI master controller driver. It can be used in conjunction with
+(layered under) the LM70 logical driver (a "SPI protocol driver").
 In effect, this driver turns the parallel port interface on the eval board
 into a SPI bus with a single device, which will be driven by the generic
 LM70 driver (drivers/hwmon/lm70.c).
 
+
+Hardware Interfacing
+--------------------
+The schematic for this particular board (the LM70EVAL-LLP) is
+available (on page 4) here:
+
+  http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
+
 The hardware interfacing on the LM70 LLP eval board is as follows:
 
    Parallel                 LM70 LLP
diff --git a/Documentation/usb/power-management.txt b/Documentation/usb/power-management.txt
index e48ea1d51010..ad642615ad4c 100644
--- a/Documentation/usb/power-management.txt
+++ b/Documentation/usb/power-management.txt
@@ -313,11 +313,13 @@ three of the methods listed above.  In addition, a driver indicates
 that it supports autosuspend by setting the .supports_autosuspend flag
 in its usb_driver structure.  It is then responsible for informing the
 USB core whenever one of its interfaces becomes busy or idle.  The
-driver does so by calling these three functions:
+driver does so by calling these five functions:
 
         int  usb_autopm_get_interface(struct usb_interface *intf);
         void usb_autopm_put_interface(struct usb_interface *intf);
         int  usb_autopm_set_interface(struct usb_interface *intf);
+        int  usb_autopm_get_interface_async(struct usb_interface *intf);
+        void usb_autopm_put_interface_async(struct usb_interface *intf);
 
 The functions work by maintaining a counter in the usb_interface
 structure.  When intf->pm_usage_count is > 0 then the interface is
@@ -330,10 +332,12 @@ associated with the device itself rather than any of its interfaces.
 This field is used only by the USB core.)
 
 The driver owns intf->pm_usage_count; it can modify the value however
-and whenever it likes.  A nice aspect of the usb_autopm_* routines is
-that the changes they make are protected by the usb_device structure's
-PM mutex (udev->pm_mutex); however drivers may change pm_usage_count
-without holding the mutex.
+and whenever it likes.  A nice aspect of the non-async usb_autopm_*
+routines is that the changes they make are protected by the usb_device
+structure's PM mutex (udev->pm_mutex); however drivers may change
+pm_usage_count without holding the mutex.  Drivers using the async
+routines are responsible for their own synchronization and mutual
+exclusion.
 
         usb_autopm_get_interface() increments pm_usage_count and
         attempts an autoresume if the new value is > 0 and the
@@ -348,6 +352,14 @@ without holding the mutex.
         is suspended, and it attempts an autosuspend if the value is
         <= 0 and the device isn't suspended.
 
+        usb_autopm_get_interface_async() and
+        usb_autopm_put_interface_async() do almost the same things as
+        their non-async counterparts.  The differences are: they do
+        not acquire the PM mutex, and they use a workqueue to do their
+        jobs.  As a result they can be called in an atomic context,
+        such as an URB's completion handler, but when they return the
+        device will not generally not yet be in the desired state.
+
 There also are a couple of utility routines drivers can use:
 
         usb_autopm_enable() sets pm_usage_cnt to 0 and then calls
diff --git a/Documentation/wimax/README.i2400m b/Documentation/wimax/README.i2400m
new file mode 100644
index 000000000000..7dffd8919cb0
--- /dev/null
+++ b/Documentation/wimax/README.i2400m
@@ -0,0 +1,260 @@
+
+   Driver for the Intel Wireless Wimax Connection 2400m
+
+   (C) 2008 Intel Corporation < linux-wimax@intel.com >
+
+   This provides a driver for the Intel Wireless WiMAX Connection 2400m
+   and a basic Linux kernel WiMAX stack.
+
+1. Requirements
+
+     * Linux installation with Linux kernel 2.6.22 or newer (if building
+       from a separate tree)
+     * Intel i2400m Echo Peak or Baxter Peak; this includes the Intel
+       Wireless WiMAX/WiFi Link 5x50 series.
+     * build tools:
+          + Linux kernel development package for the target kernel; to
+            build against your currently running kernel, you need to have
+            the kernel development package corresponding to the running
+            image installed (usually if your kernel is named
+            linux-VERSION, the development package is called
+            linux-dev-VERSION or linux-headers-VERSION).
+          + GNU C Compiler, make
+
+2. Compilation and installation
+
+2.1. Compilation of the drivers included in the kernel
+
+   Configure the kernel; to enable the WiMAX drivers select Drivers >
+   Networking Drivers > WiMAX device support. Enable all of them as
+   modules (easier).
+
+   If USB or SDIO are not enabled in the kernel configuration, the options
+   to build the i2400m USB or SDIO drivers will not show. Enable said
+   subsystems and go back to the WiMAX menu to enable the drivers.
+
+   Compile and install your kernel as usual.
+
+2.2. Compilation of the drivers distributed as an standalone module
+
+   To compile
+
+$ cd source/directory
+$ make
+
+   Once built you can load and unload using the provided load.sh script;
+   load.sh will load the modules, load.sh u will unload them.
+
+   To install in the default kernel directories (and enable auto loading
+   when the device is plugged):
+
+$ make install
+$ depmod -a
+
+   If your kernel development files are located in a non standard
+   directory or if you want to build for a kernel that is not the
+   currently running one, set KDIR to the right location:
+
+$ make KDIR=/path/to/kernel/dev/tree
+
+   For more information, please contact linux-wimax@intel.com.
+
+3. Installing the firmware
+
+   The firmware can be obtained from http://linuxwimax.org or might have
+   been supplied with your hardware.
+
+   It has to be installed in the target system:
+     *
+$ cp FIRMWAREFILE.sbcf /lib/firmware/i2400m-fw-BUSTYPE-1.3.sbcf
+
+     * NOTE: if your firmware came in an .rpm or .deb file, just install
+       it as normal, with the rpm (rpm -i FIRMWARE.rpm) or dpkg
+       (dpkg -i FIRMWARE.deb) commands. No further action is needed.
+     * BUSTYPE will be usb or sdio, depending on the hardware you have.
+       Each hardware type comes with its own firmware and will not work
+       with other types.
+
+4. Design
+
+   This package contains two major parts: a WiMAX kernel stack and a
+   driver for the Intel i2400m.
+
+   The WiMAX stack is designed to provide for common WiMAX control
+   services to current and future WiMAX devices from any vendor; please
+   see README.wimax for details.
+
+   The i2400m kernel driver is broken up in two main parts: the bus
+   generic driver and the bus-specific drivers. The bus generic driver
+   forms the drivercore and contain no knowledge of the actual method we
+   use to connect to the device. The bus specific drivers are just the
+   glue to connect the bus-generic driver and the device. Currently only
+   USB and SDIO are supported. See drivers/net/wimax/i2400m/i2400m.h for
+   more information.
+
+   The bus generic driver is logically broken up in two parts: OS-glue and
+   hardware-glue. The OS-glue interfaces with Linux. The hardware-glue
+   interfaces with the device on using an interface provided by the
+   bus-specific driver. The reason for this breakup is to be able to
+   easily reuse the hardware-glue to write drivers for other OSes; note
+   the hardware glue part is written as a native Linux driver; no
+   abstraction layers are used, so to port to another OS, the Linux kernel
+   API calls should be replaced with the target OS's.
+
+5. Usage
+
+   To load the driver, follow the instructions in the install section;
+   once the driver is loaded, plug in the device (unless it is permanently
+   plugged in). The driver will enumerate the device, upload the firmware
+   and output messages in the kernel log (dmesg, /var/log/messages or
+   /var/log/kern.log) such as:
+
+...
+i2400m_usb 5-4:1.0: firmware interface version 8.0.0
+i2400m_usb 5-4:1.0: WiMAX interface wmx0 (00:1d:e1:01:94:2c) ready
+
+   At this point the device is ready to work.
+
+   Current versions require the Intel WiMAX Network Service in userspace
+   to make things work. See the network service's README for instructions
+   on how to scan, connect and disconnect.
+
+5.1. Module parameters
+
+   Module parameters can be set at kernel or module load time or by
+   echoing values:
+
+$ echo VALUE > /sys/module/MODULENAME/parameters/PARAMETERNAME
+
+   To make changes permanent, for example, for the i2400m module, you can
+   also create a file named /etc/modprobe.d/i2400m containing:
+
+options i2400m idle_mode_disabled=1
+
+   To find which parameters are supported by a module, run:
+
+$ modinfo path/to/module.ko
+
+   During kernel bootup (if the driver is linked in the kernel), specify
+   the following to the kernel command line:
+
+i2400m.PARAMETER=VALUE
+
+5.1.1. i2400m: idle_mode_disabled
+
+   The i2400m module supports a parameter to disable idle mode. This
+   parameter, once set, will take effect only when the device is
+   reinitialized by the driver (eg: following a reset or a reconnect).
+
+5.2. Debug operations: debugfs entries
+
+   The driver will register debugfs entries that allow the user to tweak
+   debug settings. There are three main container directories where
+   entries are placed, which correspond to the three blocks a i2400m WiMAX
+   driver has:
+     * /sys/kernel/debug/wimax:DEVNAME/ for the generic WiMAX stack
+       controls
+     * /sys/kernel/debug/wimax:DEVNAME/i2400m for the i2400m generic
+       driver controls
+     * /sys/kernel/debug/wimax:DEVNAME/i2400m-usb (or -sdio) for the
+       bus-specific i2400m-usb or i2400m-sdio controls).
+
+   Of course, if debugfs is mounted in a directory other than
+   /sys/kernel/debug, those paths will change.
+
+5.2.1. Increasing debug output
+
+   The files named *dl_* indicate knobs for controlling the debug output
+   of different submodules:
+     *
+# find /sys/kernel/debug/wimax\:wmx0 -name \*dl_\*
+/sys/kernel/debug/wimax:wmx0/i2400m-usb/dl_tx
+/sys/kernel/debug/wimax:wmx0/i2400m-usb/dl_rx
+/sys/kernel/debug/wimax:wmx0/i2400m-usb/dl_notif
+/sys/kernel/debug/wimax:wmx0/i2400m-usb/dl_fw
+/sys/kernel/debug/wimax:wmx0/i2400m-usb/dl_usb
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_tx
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_rx
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_rfkill
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_netdev
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_fw
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_debugfs
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_driver
+/sys/kernel/debug/wimax:wmx0/i2400m/dl_control
+/sys/kernel/debug/wimax:wmx0/wimax_dl_stack
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_rfkill
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_reset
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_msg
+/sys/kernel/debug/wimax:wmx0/wimax_dl_id_table
+/sys/kernel/debug/wimax:wmx0/wimax_dl_debugfs
+
+   By reading the file you can obtain the current value of said debug
+   level; by writing to it, you can set it.
+
+   To increase the debug level of, for example, the i2400m's generic TX
+   engine, just write:
+
+$ echo 3 > /sys/kernel/debug/wimax:wmx0/i2400m/dl_tx
+
+   Increasing numbers yield increasing debug information; for details of
+   what is printed and the available levels, check the source. The code
+   uses 0 for disabled and increasing values until 8.
+
+5.2.2. RX and TX statistics
+
+   The i2400m/rx_stats and i2400m/tx_stats provide statistics about the
+   data reception/delivery from the device:
+
+$ cat /sys/kernel/debug/wimax:wmx0/i2400m/rx_stats
+45 1 3 34 3104 48 480
+
+   The numbers reported are
+     * packets/RX-buffer: total, min, max
+     * RX-buffers: total RX buffers received, accumulated RX buffer size
+       in bytes, min size received, max size received
+
+   Thus, to find the average buffer size received, divide accumulated
+   RX-buffer / total RX-buffers.
+
+   To clear the statistics back to 0, write anything to the rx_stats file:
+
+$ echo 1 > /sys/kernel/debug/wimax:wmx0/i2400m_rx_stats
+
+   Likewise for TX.
+
+   Note the packets this debug file refers to are not network packet, but
+   packets in the sense of the device-specific protocol for communication
+   to the host. See drivers/net/wimax/i2400m/tx.c.
+
+5.2.3. Tracing messages received from user space
+
+   To echo messages received from user space into the trace pipe that the
+   i2400m driver creates, set the debug file i2400m/trace_msg_from_user to
+   1:
+     *
+$ echo 1 > /sys/kernel/debug/wimax:wmx0/i2400m/trace_msg_from_user
+
+5.2.4. Performing a device reset
+
+   By writing a 0, a 1 or a 2 to the file
+   /sys/kernel/debug/wimax:wmx0/reset, the driver performs a warm (without
+   disconnecting from the bus), cold (disconnecting from the bus) or bus
+   (bus specific) reset on the device.
+
+5.2.5. Asking the device to enter power saving mode
+
+   By writing any value to the /sys/kernel/debug/wimax:wmx0 file, the
+   device will attempt to enter power saving mode.
+
+6. Troubleshooting
+
+6.1. Driver complains about 'i2400m-fw-usb-1.2.sbcf: request failed'
+
+   If upon connecting the device, the following is output in the kernel
+   log:
+
+i2400m_usb 5-4:1.0: fw i2400m-fw-usb-1.3.sbcf: request failed: -2
+
+   This means that the driver cannot locate the firmware file named
+   /lib/firmware/i2400m-fw-usb-1.2.sbcf. Check that the file is present in
+   the right location.
diff --git a/Documentation/wimax/README.wimax b/Documentation/wimax/README.wimax
new file mode 100644
index 000000000000..b78c4378084e
--- /dev/null
+++ b/Documentation/wimax/README.wimax
@@ -0,0 +1,81 @@
+
+   Linux kernel WiMAX stack
+
+   (C) 2008 Intel Corporation < linux-wimax@intel.com >
+
+   This provides a basic Linux kernel WiMAX stack to provide a common
+   control API for WiMAX devices, usable from kernel and user space.
+
+1. Design
+
+   The WiMAX stack is designed to provide for common WiMAX control
+   services to current and future WiMAX devices from any vendor.
+
+   Because currently there is only one and we don't know what would be the
+   common services, the APIs it currently provides are very minimal.
+   However, it is done in such a way that it is easily extensible to
+   accommodate future requirements.
+
+   The stack works by embedding a struct wimax_dev in your device's
+   control structures. This provides a set of callbacks that the WiMAX
+   stack will call in order to implement control operations requested by
+   the user. As well, the stack provides API functions that the driver
+   calls to notify about changes of state in the device.
+
+   The stack exports the API calls needed to control the device to user
+   space using generic netlink as a marshalling mechanism. You can access
+   them using your own code or use the wrappers provided for your
+   convenience in libwimax (in the wimax-tools package).
+
+   For detailed information on the stack, please see
+   include/linux/wimax.h.
+
+2. Usage
+
+   For usage in a driver (registration, API, etc) please refer to the
+   instructions in the header file include/linux/wimax.h.
+
+   When a device is registered with the WiMAX stack, a set of debugfs
+   files will appear in /sys/kernel/debug/wimax:wmxX can tweak for
+   control.
+
+2.1. Obtaining debug information: debugfs entries
+
+   The WiMAX stack is compiled, by default, with debug messages that can
+   be used to diagnose issues. By default, said messages are disabled.
+
+   The drivers will register debugfs entries that allow the user to tweak
+   debug settings.
+
+   Each driver, when registering with the stack, will cause a debugfs
+   directory named wimax:DEVICENAME to be created; optionally, it might
+   create more subentries below it.
+
+2.1.1. Increasing debug output
+
+   The files named *dl_* indicate knobs for controlling the debug output
+   of different submodules of the WiMAX stack:
+     *
+# find /sys/kernel/debug/wimax\:wmx0 -name \*dl_\*
+/sys/kernel/debug/wimax:wmx0/wimax_dl_stack
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_rfkill
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_reset
+/sys/kernel/debug/wimax:wmx0/wimax_dl_op_msg
+/sys/kernel/debug/wimax:wmx0/wimax_dl_id_table
+/sys/kernel/debug/wimax:wmx0/wimax_dl_debugfs
+/sys/kernel/debug/wimax:wmx0/.... # other driver specific files
+
+       NOTE: Of course, if debugfs is mounted in a directory other than
+       /sys/kernel/debug, those paths will change.
+
+   By reading the file you can obtain the current value of said debug
+   level; by writing to it, you can set it.
+
+   To increase the debug level of, for example, the id-table submodule,
+   just write:
+
+$ echo 3 > /sys/kernel/debug/wimax:wmx0/wimax_dl_id_table
+
+   Increasing numbers yield increasing debug information; for details of
+   what is printed and the available levels, check the source. The code
+   uses 0 for disabled and increasing values until 8.
diff --git a/MAINTAINERS b/MAINTAINERS
index 094dd52d7309..ee3871e204e7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2305,6 +2305,14 @@ W:	http://lists.sourceforge.net/mailman/listinfo/ipw2100-devel
 W:      http://ipw2200.sourceforge.net
 S:      Supported
 
+INTEL WIRELESS WIMAX CONNECTION 2400
+P:      Inaky Perez-Gonzalez
+M:      inaky.perez-gonzalez@intel.com
+M:      linux-wimax@intel.com
+L:      wimax@linuxwimax.org
+S:      Supported
+W:      http://linuxwimax.org
+
 INTEL WIRELESS WIFI LINK (iwlwifi)
 P:      Zhu Yi
 M:      yi.zhu@intel.com
@@ -2982,6 +2990,7 @@ MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER
 P:      Felipe Balbi
 M:      felipe.balbi@nokia.com
 L:      linux-usb@vger.kernel.org
+T:      git gitorious.org:/musb/mainline.git
 S:      Maintained
 
 MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
@@ -4229,9 +4238,10 @@ L:	tpmdd-devel@lists.sourceforge.net (moderated for non-subscribers)
 S:      Maintained
 
 TRIVIAL PATCHES
-P:      Jesper Juhl
+P:      Jiri Kosina
 M:      trivial@kernel.org
 L:      linux-kernel@vger.kernel.org
+T:      git kernel.org:/pub/scm/linux/kernel/git/jikos/trivial.git
 S:      Maintained
 
 TTY LAYER
@@ -4732,6 +4742,14 @@ M:	zaga@fly.cc.fer.hr
 L:      linux-scsi@vger.kernel.org
 S:      Maintained
 
+WIMAX STACK
+P:      Inaky Perez-Gonzalez
+M:      inaky.perez-gonzalez@intel.com
+M:      linux-wimax@intel.com
+L:      wimax@linuxwimax.org
+S:      Supported
+W:      http://linuxwimax.org
+
 WIMEDIA LLC PROTOCOL (WLP) SUBSYSTEM
 P:      David Vrabel
 M:      david.vrabel@csr.com
diff --git a/Makefile b/Makefile
index f9006663f01e..28331288341f 100644
--- a/Makefile
+++ b/Makefile
@@ -965,6 +965,7 @@ ifneq ($(KBUILD_SRC),)
             mkdir -p include2;                                          \
             ln -fsn $(srctree)/include/asm-$(SRCARCH) include2/asm;     \
         fi
+        ln -fsn $(srctree) source
 endif
 
 # prepare2 creates a makefile if using a separate output directory
@@ -1008,7 +1009,7 @@ define check-symlink
 endef
 
 # We create the target directory of the symlink if it does
-# not exist so the test in chack-symlink works and we have a
+# not exist so the test in check-symlink works and we have a
 # directory for generated filesas used by some architectures.
 define create-symlink
         if [ ! -L include/asm ]; then                                      \
diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/arch/arm/plat-mxc/include/mach/usb.h
new file mode 100644
index 000000000000..2dacb3086f1c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/usb.h
@@ -0,0 +1,23 @@
+/*
+ *      Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>
+ *
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *
+ *      This program is distributed in the hope that it will be useful,
+ *      but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *      GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MXC_USB
+#define __ASM_ARCH_MXC_USB
+
+struct imxusb_platform_data {
+        int (*init)(struct device *);
+        int (*exit)(struct device *);
+};
+
+#endif /* __ASM_ARCH_MXC_USB */
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 67ca1e216df7..add0485703b5 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -77,38 +77,6 @@
 
 /*-------------------------------------------------------------------------*/
 
-#if     defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
-
-static struct otg_transceiver *xceiv;
-
-/**
- * otg_get_transceiver - find the (single) OTG transceiver driver
- *
- * Returns the transceiver driver, after getting a refcount to it; or
- * null if there is no such transceiver.  The caller is responsible for
- * releasing that count.
- */
-struct otg_transceiver *otg_get_transceiver(void)
-{
-        if (xceiv)
-                get_device(xceiv->dev);
-        return xceiv;
-}
-EXPORT_SYMBOL(otg_get_transceiver);
-
-int otg_set_transceiver(struct otg_transceiver *x)
-{
-        if (xceiv && x)
-                return -EBUSY;
-        xceiv = x;
-        return 0;
-}
-EXPORT_SYMBOL(otg_set_transceiver);
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
 
 static void omap2_usb_devconf_clear(u8 port, u32 mask)
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 26eca87f6735..b189680d18b0 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -122,6 +122,24 @@ config BOARD_ATNGW100
         bool "ATNGW100 Network Gateway"
         select CPU_AT32AP7000
 
+config BOARD_HAMMERHEAD
+        bool "Hammerhead board"
+        select CPU_AT32AP7000
+        select USB_ARCH_HAS_HCD
+        help
+          The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel.
+          It offers versatile peripherals, such as ethernet, usb device, usb host etc.
+
+          The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered
+          Device (PD).
+
+          Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is
+          mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
+          will cover even the most exceptional need of memory bandwidth. Together with the onboard
+          video decoder the board is ready for video processing.
+
+          For more information see: http://www.miromico.com/hammerhead
+
 config BOARD_FAVR_32
         bool "Favr-32 LCD-board"
         select CPU_AT32AP7000
@@ -133,6 +151,7 @@ endchoice
 
 source "arch/avr32/boards/atstk1000/Kconfig"
 source "arch/avr32/boards/atngw100/Kconfig"
+source "arch/avr32/boards/hammerhead/Kconfig"
 source "arch/avr32/boards/favr-32/Kconfig"
 
 choice
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
index b088e103e753..f3ef3bbf797c 100644
--- a/arch/avr32/Makefile
+++ b/arch/avr32/Makefile
@@ -33,6 +33,7 @@ head-y					+= arch/avr32/kernel/head.o
 core-y                                  += $(machdirs)
 core-$(CONFIG_BOARD_ATSTK1000)          += arch/avr32/boards/atstk1000/
 core-$(CONFIG_BOARD_ATNGW100)           += arch/avr32/boards/atngw100/
+core-$(CONFIG_BOARD_HAMMERHEAD)         += arch/avr32/boards/hammerhead/
 core-$(CONFIG_BOARD_FAVR_32)            += arch/avr32/boards/favr-32/
 core-$(CONFIG_BOARD_MIMC200)            += arch/avr32/boards/mimc200/
 core-$(CONFIG_LOADER_U_BOOT)            += arch/avr32/boot/u-boot/
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index 32fb9ba0fbdf..05d3722fff18 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -19,8 +19,8 @@
 #include <linux/types.h>
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
+#include <linux/atmel-mci.h>
 
-#include <asm/atmel-mci.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index 5c5cdf3b464f..1f33a106905c 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -16,12 +16,12 @@
 #include <linux/types.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
+#include <linux/atmel-mci.h>
 
 #include <video/atmel_lcdc.h>
 
 #include <asm/io.h>
 #include <asm/setup.h>
-#include <asm/atmel-mci.h>
 
 #include <mach/at32ap700x.h>
 #include <mach/board.h>
@@ -287,23 +287,7 @@ static int __init atstk1002_init(void)
          * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
          * SDRAM-specific pins so that nobody messes with them.
          */
-        at32_reserve_pin(GPIO_PIN_PE(0));       /* DATA[16]     */
-        at32_reserve_pin(GPIO_PIN_PE(1));       /* DATA[17]     */
-        at32_reserve_pin(GPIO_PIN_PE(2));       /* DATA[18]     */
-        at32_reserve_pin(GPIO_PIN_PE(3));       /* DATA[19]     */
-        at32_reserve_pin(GPIO_PIN_PE(4));       /* DATA[20]     */
-        at32_reserve_pin(GPIO_PIN_PE(5));       /* DATA[21]     */
-        at32_reserve_pin(GPIO_PIN_PE(6));       /* DATA[22]     */
-        at32_reserve_pin(GPIO_PIN_PE(7));       /* DATA[23]     */
-        at32_reserve_pin(GPIO_PIN_PE(8));       /* DATA[24]     */
-        at32_reserve_pin(GPIO_PIN_PE(9));       /* DATA[25]     */
-        at32_reserve_pin(GPIO_PIN_PE(10));      /* DATA[26]     */
-        at32_reserve_pin(GPIO_PIN_PE(11));      /* DATA[27]     */
-        at32_reserve_pin(GPIO_PIN_PE(12));      /* DATA[28]     */
-        at32_reserve_pin(GPIO_PIN_PE(13));      /* DATA[29]     */
-        at32_reserve_pin(GPIO_PIN_PE(14));      /* DATA[30]     */
-        at32_reserve_pin(GPIO_PIN_PE(15));      /* DATA[31]     */
-        at32_reserve_pin(GPIO_PIN_PE(26));      /* SDCS         */
+        at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
 
 #ifdef CONFIG_BOARD_ATSTK1006
         smc_set_timing(&nand_config, &nand_timing);
diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c
index 134b566630b0..b3a23c88bcfe 100644
--- a/arch/avr32/boards/atstk1000/atstk1003.c
+++ b/arch/avr32/boards/atstk1000/atstk1003.c
@@ -17,9 +17,9 @@
 
 #include <linux/spi/at73c213.h>
 #include <linux/spi/spi.h>
+#include <linux/atmel-mci.h>
 
 #include <asm/setup.h>
-#include <asm/atmel-mci.h>
 
 #include <mach/at32ap700x.h>
 #include <mach/board.h>
@@ -131,23 +131,7 @@ static int __init atstk1003_init(void)
          * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
          * SDRAM-specific pins so that nobody messes with them.
          */
-        at32_reserve_pin(GPIO_PIN_PE(0));       /* DATA[16]     */
-        at32_reserve_pin(GPIO_PIN_PE(1));       /* DATA[17]     */
-        at32_reserve_pin(GPIO_PIN_PE(2));       /* DATA[18]     */
-        at32_reserve_pin(GPIO_PIN_PE(3));       /* DATA[19]     */
-        at32_reserve_pin(GPIO_PIN_PE(4));       /* DATA[20]     */
-        at32_reserve_pin(GPIO_PIN_PE(5));       /* DATA[21]     */
-        at32_reserve_pin(GPIO_PIN_PE(6));       /* DATA[22]     */
-        at32_reserve_pin(GPIO_PIN_PE(7));       /* DATA[23]     */
-        at32_reserve_pin(GPIO_PIN_PE(8));       /* DATA[24]     */
-        at32_reserve_pin(GPIO_PIN_PE(9));       /* DATA[25]     */
-        at32_reserve_pin(GPIO_PIN_PE(10));      /* DATA[26]     */
-        at32_reserve_pin(GPIO_PIN_PE(11));      /* DATA[27]     */
-        at32_reserve_pin(GPIO_PIN_PE(12));      /* DATA[28]     */
-        at32_reserve_pin(GPIO_PIN_PE(13));      /* DATA[29]     */
-        at32_reserve_pin(GPIO_PIN_PE(14));      /* DATA[30]     */
-        at32_reserve_pin(GPIO_PIN_PE(15));      /* DATA[31]     */
-        at32_reserve_pin(GPIO_PIN_PE(26));      /* SDCS         */
+        at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
 
 #ifdef  CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
         at32_add_device_usart(1);
diff --git a/arch/avr32/boards/atstk1000/atstk1004.c b/arch/avr32/boards/atstk1000/atstk1004.c
index cb32eb844aa7..29b35aca96cd 100644
--- a/arch/avr32/boards/atstk1000/atstk1004.c
+++ b/arch/avr32/boards/atstk1000/atstk1004.c
@@ -17,11 +17,11 @@
 
 #include <linux/spi/at73c213.h>
 #include <linux/spi/spi.h>
+#include <linux/atmel-mci.h>
 
 #include <video/atmel_lcdc.h>
 
 #include <asm/setup.h>
-#include <asm/atmel-mci.h>
 
 #include <mach/at32ap700x.h>
 #include <mach/board.h>
diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c
index 1ee4faf0742d..745c408c2ac5 100644
--- a/arch/avr32/boards/favr-32/setup.c
+++ b/arch/avr32/boards/favr-32/setup.c
@@ -17,6 +17,7 @@
 #include <linux/linkage.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/atmel-mci.h>
 #include <linux/atmel-pwm-bl.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -79,6 +80,14 @@ static struct spi_board_info __initdata spi1_board_info[] = {
         },
 };
 
+static struct mci_platform_data __initdata mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -ENODEV,
+                .wp_pin         = -ENODEV,
+        },
+};
+
 static struct fb_videomode __initdata lb104v03_modes[] = {
         {
                 .name           = "640x480 @ 50",
@@ -307,28 +316,10 @@ static int __init favr32_init(void)
          * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific
          * pins so that nobody messes with them.
          */
-        at32_reserve_pin(GPIO_PIN_PE(0));       /* DATA[16]     */
-        at32_reserve_pin(GPIO_PIN_PE(1));       /* DATA[17]     */
-        at32_reserve_pin(GPIO_PIN_PE(2));       /* DATA[18]     */
-        at32_reserve_pin(GPIO_PIN_PE(3));       /* DATA[19]     */
-        at32_reserve_pin(GPIO_PIN_PE(4));       /* DATA[20]     */
-        at32_reserve_pin(GPIO_PIN_PE(5));       /* DATA[21]     */
-        at32_reserve_pin(GPIO_PIN_PE(6));       /* DATA[22]     */
-        at32_reserve_pin(GPIO_PIN_PE(7));       /* DATA[23]     */
-        at32_reserve_pin(GPIO_PIN_PE(8));       /* DATA[24]     */
-        at32_reserve_pin(GPIO_PIN_PE(9));       /* DATA[25]     */
-        at32_reserve_pin(GPIO_PIN_PE(10));      /* DATA[26]     */
-        at32_reserve_pin(GPIO_PIN_PE(11));      /* DATA[27]     */
-        at32_reserve_pin(GPIO_PIN_PE(12));      /* DATA[28]     */
-        at32_reserve_pin(GPIO_PIN_PE(13));      /* DATA[29]     */
-        at32_reserve_pin(GPIO_PIN_PE(14));      /* DATA[30]     */
-        at32_reserve_pin(GPIO_PIN_PE(15));      /* DATA[31]     */
-        at32_reserve_pin(GPIO_PIN_PE(26));      /* SDCS         */
+        at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
 
         at32_select_gpio(GPIO_PIN_PB(3), 0);    /* IRQ from ADS7843 */
 
-        at32_add_system_devices();
-
         at32_add_device_usart(0);
 
         set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
@@ -339,7 +330,7 @@ static int __init favr32_init(void)
 
         at32_add_device_pwm(1 << atmel_pwm_bl_pdata.pwm_channel);
         at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
-        at32_add_device_mci(0, NULL);
+        at32_add_device_mci(0, &mci0_data);
         at32_add_device_usba(0, NULL);
         at32_add_device_lcdc(0, &favr32_lcdc_data, fbmem_start, fbmem_size, 0);
 
diff --git a/arch/avr32/boards/hammerhead/Kconfig b/arch/avr32/boards/hammerhead/Kconfig
new file mode 100644
index 000000000000..fda2331f9789
--- /dev/null
+++ b/arch/avr32/boards/hammerhead/Kconfig
@@ -0,0 +1,43 @@
+# Hammerhead customization
+
+if BOARD_HAMMERHEAD
+
+config BOARD_HAMMERHEAD_USB
+        bool "Philips ISP116x-hcd USB support"
+        help
+          This enables USB support for Hammerheads internal ISP116x
+          controller from Philips.
+
+          Choose 'Y' here if you want to have your board USB driven.
+
+config BOARD_HAMMERHEAD_LCD
+        bool "Atmel AT91/AT32 LCD support"
+        help
+          This enables LCD support for the Hammerhead board. You may
+          also add support for framebuffer devices (AT91/AT32 LCD Controller)
+          and framebuffer console support to get the most out of your LCD.
+
+          Choose 'Y' here if you have ordered a Corona daugther board and
+          want to have support for your Hantronix HDA-351T-LV LCD.
+
+config BOARD_HAMMERHEAD_SND
+        bool "Atmel AC97 Sound support"
+        help
+          This enables Sound support for the Hammerhead board. You may
+          also go trough the ALSA settings to get it working.
+
+          Choose 'Y' here if you have ordered a Corona daugther board and
+          want to make your board funky.
+
+config BOARD_HAMMERHEAD_FPGA
+        bool "Hammerhead FPGA Support"
+        default y
+        help
+          This adds support for the Cyclone III FPGA from Altera
+          found on Miromico's Hammerhead board.
+
+          Choose 'Y' here if you want to have FPGA support enabled.
+          You will have to choose the "Hammerhead FPGA Device Support" in
+          Device Drivers->Misc to be able to use FPGA functionality.
+
+endif   # BOARD_ATNGW100
diff --git a/arch/avr32/boards/hammerhead/Makefile b/arch/avr32/boards/hammerhead/Makefile
new file mode 100644
index 000000000000..c740aa116755
--- /dev/null
+++ b/arch/avr32/boards/hammerhead/Makefile
@@ -0,0 +1 @@
+obj-y                           += setup.o flash.o
diff --git a/arch/avr32/boards/hammerhead/flash.c b/arch/avr32/boards/hammerhead/flash.c
new file mode 100644
index 000000000000..a98c6dd3a028
--- /dev/null
+++ b/arch/avr32/boards/hammerhead/flash.c
@@ -0,0 +1,377 @@
+/*
+ * Hammerhead board-specific flash initialization
+ *
+ * Copyright (C) 2008 Miromico AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/usb/isp116x.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/portmux.h>
+#include <mach/at32ap700x.h>
+#include <mach/smc.h>
+
+#include "../../mach-at32ap/clock.h"
+#include "flash.h"
+
+
+#define HAMMERHEAD_USB_PERIPH_GCLK0     0x40000000
+#define HAMMERHEAD_USB_PERIPH_CS2       0x02000000
+#define HAMMERHEAD_USB_PERIPH_EXTINT0   0x02000000
+
+#define HAMMERHEAD_FPGA_PERIPH_MOSI     0x00000002
+#define HAMMERHEAD_FPGA_PERIPH_SCK      0x00000020
+#define HAMMERHEAD_FPGA_PERIPH_EXTINT3  0x10000000
+
+static struct smc_timing flash_timing __initdata = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 40,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 10,
+
+        .ncs_read_pulse         = 80,
+        .nrd_pulse              = 40,
+        .ncs_write_pulse        = 65,
+        .nwe_pulse              = 55,
+
+        .read_cycle             = 120,
+        .write_cycle            = 120,
+};
+
+static struct smc_config flash_config __initdata = {
+        .bus_width              = 2,
+        .nrd_controlled         = 1,
+        .nwe_controlled         = 1,
+        .byte_write             = 1,
+};
+
+static struct mtd_partition flash_parts[] = {
+        {
+                .name           = "u-boot",
+                .offset         = 0x00000000,
+                .size           = 0x00020000,           /* 128 KiB */
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "root",
+                .offset         = 0x00020000,
+                .size           = 0x007d0000,
+        },
+        {
+                .name           = "env",
+                .offset         = 0x007f0000,
+                .size           = 0x00010000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data flash_data = {
+        .width          = 2,
+        .nr_parts       = ARRAY_SIZE(flash_parts),
+        .parts          = flash_parts,
+};
+
+static struct resource flash_resource = {
+        .start          = 0x00000000,
+        .end            = 0x007fffff,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = &flash_resource,
+        .num_resources  = 1,
+        .dev            = { .platform_data = &flash_data, },
+};
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_USB
+
+static struct smc_timing isp1160_timing __initdata = {
+        .ncs_read_setup         = 75,
+        .nrd_setup              = 75,
+        .ncs_write_setup        = 75,
+        .nwe_setup              = 75,
+
+
+        /* We use conservative timing settings, as the minimal settings aren't
+           stable. There may be room for tweaking. */
+        .ncs_read_pulse         = 75,  /* min. 33ns */
+        .nrd_pulse              = 75,  /* min. 33ns */
+        .ncs_write_pulse        = 75,  /* min. 26ns */
+        .nwe_pulse              = 75,  /* min. 26ns */
+
+        .read_cycle             = 225, /* min. 143ns */
+        .write_cycle            = 225, /* min. 136ns */
+};
+
+static struct smc_config isp1160_config __initdata = {
+        .bus_width              = 2,
+        .nrd_controlled         = 1,
+        .nwe_controlled         = 1,
+        .byte_write             = 0,
+};
+
+/*
+ * The platform delay function is only used to enforce the strange
+ * read to write delay. This can not be configured in the SMC. All other
+ * timings are controlled by the SMC (see timings obove)
+ * So in isp116x-hcd.c we should comment out USE_PLATFORM_DELAY
+ */
+void isp116x_delay(struct device *dev, int delay)
+{
+        if (delay > 150)
+                ndelay(delay - 150);
+}
+
+static struct  isp116x_platform_data isp1160_data = {
+        .sel15Kres              = 1,    /* use internal downstream resistors */
+        .oc_enable              = 0,    /* external overcurrent detection */
+        .int_edge_triggered     = 0,    /* interrupt is level triggered */
+        .int_act_high           = 0,    /* interrupt is active low */
+        .delay = isp116x_delay,         /* platform delay function */
+};
+
+static struct resource isp1160_resource[] = {
+        {
+                .start          = 0x08000000,
+                .end            = 0x08000001,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 0x08000002,
+                .end            = 0x08000003,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 64,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device isp1160_device = {
+        .name           = "isp116x-hcd",
+        .id             = 0,
+        .resource       = isp1160_resource,
+        .num_resources  = 3,
+        .dev            = {
+                .platform_data = &isp1160_data,
+        },
+};
+#endif
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_USB
+static int __init hammerhead_usbh_init(void)
+{
+        struct clk *gclk;
+        struct clk *osc;
+
+        int ret;
+
+        /* setup smc for usbh */
+        smc_set_timing(&isp1160_config, &isp1160_timing);
+        ret = smc_set_configuration(2, &isp1160_config);
+
+        if (ret < 0) {
+                printk(KERN_ERR
+                       "hammerhead: failed to set ISP1160 USBH timing\n");
+                return ret;
+        }
+
+        /* setup gclk0 to run from osc1 */
+        gclk = clk_get(NULL, "gclk0");
+        if (IS_ERR(gclk))
+                goto err_gclk;
+
+        osc = clk_get(NULL, "osc1");
+        if (IS_ERR(osc))
+                goto err_osc;
+
+        if (clk_set_parent(gclk, osc)) {
+                pr_debug("hammerhead: failed to set osc1 for USBH clock\n");
+                goto err_set_clk;
+        }
+
+        /* set clock to 6MHz */
+        clk_set_rate(gclk, 6000000);
+
+        /* and enable */
+        clk_enable(gclk);
+
+        /* select GCLK0 peripheral function */
+        at32_select_periph(GPIO_PIOA_BASE, HAMMERHEAD_USB_PERIPH_GCLK0,
+                           GPIO_PERIPH_A, 0);
+
+        /* enable CS2 peripheral function */
+        at32_select_periph(GPIO_PIOE_BASE, HAMMERHEAD_USB_PERIPH_CS2,
+                           GPIO_PERIPH_A, 0);
+
+        /* H_WAKEUP must be driven low */
+        at32_select_gpio(GPIO_PIN_PA(8), AT32_GPIOF_OUTPUT);
+
+        /* Select EXTINT0 for PB25 */
+        at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_USB_PERIPH_EXTINT0,
+                           GPIO_PERIPH_A, 0);
+
+        /* register usbh device driver */
+        platform_device_register(&isp1160_device);
+
+ err_set_clk:
+        clk_put(osc);
+ err_osc:
+        clk_put(gclk);
+ err_gclk:
+        return ret;
+}
+#endif
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA
+static struct smc_timing fpga_timing __initdata = {
+        .ncs_read_setup         = 16,
+        .nrd_setup              = 32,
+        .ncs_read_pulse         = 48,
+        .nrd_pulse              = 32,
+        .read_cycle             = 64,
+
+        .ncs_write_setup        = 16,
+        .nwe_setup              = 16,
+        .ncs_write_pulse        = 32,
+        .nwe_pulse              = 32,
+        .write_cycle            = 64,
+};
+
+static struct smc_config fpga_config __initdata = {
+        .bus_width              = 4,
+        .nrd_controlled         = 1,
+        .nwe_controlled         = 1,
+        .byte_write             = 0,
+};
+
+static struct resource hh_fpga0_resource[] = {
+        {
+                .start          = 0xffe00400,
+                .end            = 0xffe00400 + 0x3ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 4,
+                .end            = 4,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = 0x0c000000,
+                .end            = 0x0c000100,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = 67,
+                .end            = 67,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 hh_fpga0_dma_mask = DMA_32BIT_MASK;
+static struct platform_device hh_fpga0_device = {
+        .name           = "hh_fpga",
+        .id             = 0,
+        .dev            = {
+                .dma_mask = &hh_fpga0_dma_mask,
+                .coherent_dma_mask = DMA_32BIT_MASK,
+        },
+        .resource       = hh_fpga0_resource,
+        .num_resources  = ARRAY_SIZE(hh_fpga0_resource),
+};
+
+static struct clk hh_fpga0_spi_clk = {
+        .name           = "spi_clk",
+        .dev            = &hh_fpga0_device.dev,
+        .mode           = pba_clk_mode,
+        .get_rate       = pba_clk_get_rate,
+        .index          = 1,
+};
+
+struct platform_device *__init at32_add_device_hh_fpga(void)
+{
+        /* Select peripheral functionallity for SPI SCK and MOSI */
+        at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_SCK,
+                           GPIO_PERIPH_B, 0);
+        at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_MOSI,
+                           GPIO_PERIPH_B, 0);
+
+        /* reserve all other needed gpio
+         * We have on board pull ups, so there is no need
+         * to enable gpio pull ups */
+        /* INIT_DONE (input) */
+        at32_select_gpio(GPIO_PIN_PB(0), 0);
+
+        /* nSTATUS (input) */
+        at32_select_gpio(GPIO_PIN_PB(2), 0);
+
+        /* nCONFIG (output, low) */
+        at32_select_gpio(GPIO_PIN_PB(3), AT32_GPIOF_OUTPUT);
+
+        /* CONF_DONE (input) */
+        at32_select_gpio(GPIO_PIN_PB(4), 0);
+
+        /* Select EXTINT3 for PB28 (Interrupt from FPGA) */
+        at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_EXTINT3,
+                           GPIO_PERIPH_A, 0);
+
+        /* Get our parent clock */
+        hh_fpga0_spi_clk.parent = clk_get(NULL, "pba");
+        clk_put(hh_fpga0_spi_clk.parent);
+
+        /* Register clock in at32 clock tree */
+        at32_clk_register(&hh_fpga0_spi_clk);
+
+        platform_device_register(&hh_fpga0_device);
+        return &hh_fpga0_device;
+}
+#endif
+
+/* This needs to be called after the SMC has been initialized */
+static int __init hammerhead_flash_init(void)
+{
+        int ret;
+
+        smc_set_timing(&flash_config, &flash_timing);
+        ret = smc_set_configuration(0, &flash_config);
+
+        if (ret < 0) {
+                printk(KERN_ERR "hammerhead: failed to set NOR flash timing\n");
+                return ret;
+        }
+
+        platform_device_register(&flash_device);
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_USB
+        hammerhead_usbh_init();
+#endif
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA
+        /* Setup SMC for FPGA interface */
+        smc_set_timing(&fpga_config, &fpga_timing);
+        ret = smc_set_configuration(3, &fpga_config);
+#endif
+
+
+        if (ret < 0) {
+                printk(KERN_ERR "hammerhead: failed to set FPGA timing\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+device_initcall(hammerhead_flash_init);
diff --git a/arch/avr32/boards/hammerhead/flash.h b/arch/avr32/boards/hammerhead/flash.h
new file mode 100644
index 000000000000..ea70c626587b
--- /dev/null
+++ b/arch/avr32/boards/hammerhead/flash.h
@@ -0,0 +1,6 @@
+#ifndef __BOARDS_HAMMERHEAD_FLASH_H
+#define __BOARDS_HAMMERHEAD_FLASH_H
+
+struct platform_device *at32_add_device_hh_fpga(void);
+
+#endif /* __BOARDS_HAMMERHEAD_FLASH_H */
diff --git a/arch/avr32/boards/hammerhead/setup.c b/arch/avr32/boards/hammerhead/setup.c
new file mode 100644
index 000000000000..4d2fe82b2029
--- /dev/null
+++ b/arch/avr32/boards/hammerhead/setup.c
@@ -0,0 +1,245 @@
+/*
+ * Board-specific setup code for the Miromico Hammerhead board
+ *
+ * Copyright (C) 2008 Miromico AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/atmel-mci.h>
+#include <linux/clk.h>
+#include <linux/fb.h>
+#include <linux/etherdevice.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/spi/spi.h>
+
+#include <video/atmel_lcdc.h>
+
+#include <linux/io.h>
+#include <asm/setup.h>
+
+#include <mach/at32ap700x.h>
+#include <mach/board.h>
+#include <mach/init.h>
+#include <mach/portmux.h>
+
+#include "../../mach-at32ap/clock.h"
+#include "flash.h"
+
+/* Oscillator frequencies. These are board-specific */
+unsigned long at32_board_osc_rates[3] = {
+        [0] = 32768,    /* 32.768 kHz on RTC osc */
+        [1] = 25000000, /* 25MHz on osc0 */
+        [2] = 12000000, /* 12 MHz on osc1 */
+};
+
+/* Initialized by bootloader-specific startup code. */
+struct tag *bootloader_tags __initdata;
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_LCD
+static struct fb_videomode __initdata hda350tlv_modes[] = {
+        {
+                .name           = "320x240 @ 75",
+                .refresh        = 75,
+                .xres           = 320,
+                .yres           = 240,
+                .pixclock       = KHZ2PICOS(6891),
+
+                .left_margin    = 48,
+                .right_margin   = 18,
+                .upper_margin   = 18,
+                .lower_margin   = 4,
+                .hsync_len      = 20,
+                .vsync_len      = 2,
+
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+};
+
+static struct fb_monspecs __initdata hammerhead_hda350t_monspecs = {
+        .manufacturer           = "HAN",
+        .monitor                = "HDA350T-LV",
+        .modedb                 = hda350tlv_modes,
+        .modedb_len             = ARRAY_SIZE(hda350tlv_modes),
+        .hfmin                  = 14900,
+        .hfmax                  = 22350,
+        .vfmin                  = 60,
+        .vfmax                  = 90,
+        .dclkmax                = 10000000,
+};
+
+struct atmel_lcdfb_info __initdata hammerhead_lcdc_data = {
+        .default_bpp            = 24,
+        .default_dmacon         = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
+        .default_lcdcon2        = (ATMEL_LCDC_DISTYPE_TFT
+                                   | ATMEL_LCDC_INVCLK
+                                   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
+                                   | ATMEL_LCDC_MEMOR_BIG),
+        .default_monspecs       = &hammerhead_hda350t_monspecs,
+        .guard_time             = 2,
+};
+#endif
+
+static struct mci_platform_data __initdata mci0_data = {
+        .slot[0] = {
+                .bus_width      = 4,
+                .detect_pin     = -ENODEV,
+                .wp_pin         = -ENODEV,
+        },
+};
+
+struct eth_addr {
+        u8 addr[6];
+};
+
+static struct eth_addr __initdata hw_addr[1];
+static struct eth_platform_data __initdata eth_data[1];
+
+/*
+ * The next two functions should go away as the boot loader is
+ * supposed to initialize the macb address registers with a valid
+ * ethernet address. But we need to keep it around for a while until
+ * we can be reasonably sure the boot loader does this.
+ *
+ * The phy_id is ignored as the driver will probe for it.
+ */
+static int __init parse_tag_ethernet(struct tag *tag)
+{
+        int i = tag->u.ethernet.mac_index;
+
+        if (i < ARRAY_SIZE(hw_addr))
+                memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
+                       sizeof(hw_addr[i].addr));
+
+        return 0;
+}
+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
+
+static void __init set_hw_addr(struct platform_device *pdev)
+{
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        const u8 *addr;
+        void __iomem *regs;
+        struct clk *pclk;
+
+        if (!res)
+                return;
+
+        if (pdev->id >= ARRAY_SIZE(hw_addr))
+                return;
+
+        addr = hw_addr[pdev->id].addr;
+
+        if (!is_valid_ether_addr(addr))
+                return;
+
+        /*
+         * Since this is board-specific code, we'll cheat and use the
+         * physical address directly as we happen to know that it's
+         * the same as the virtual address.
+         */
+        regs = (void __iomem __force *)res->start;
+        pclk = clk_get(&pdev->dev, "pclk");
+
+        if (!pclk)
+                return;
+
+        clk_enable(pclk);
+
+        __raw_writel((addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) |
+                     addr[0], regs + 0x98);
+        __raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
+
+        clk_disable(pclk);
+        clk_put(pclk);
+}
+
+void __init setup_board(void)
+{
+        at32_map_usart(1, 0);   /* USART 1: /dev/ttyS0, DB9 */
+        at32_setup_serial_console(0);
+}
+
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+        .sda_pin                = GPIO_PIN_PA(6),
+        .scl_pin                = GPIO_PIN_PA(7),
+        .sda_is_open_drain      = 1,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,    /* close to 100 kHz */
+};
+
+static struct platform_device i2c_gpio_device = {
+        .name           = "i2c-gpio",
+        .id             = 0,
+        .dev            = { .platform_data = &i2c_gpio_data, },
+};
+
+static struct i2c_board_info __initdata i2c_info[] = {};
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_SND
+static struct ac97c_platform_data ac97c_data = {
+        .reset_pin = GPIO_PIN_PA(16),
+};
+#endif
+
+static int __init hammerhead_init(void)
+{
+        /*
+         * Hammerhead uses 32-bit SDRAM interface. Reserve the
+         * SDRAM-specific pins so that nobody messes with them.
+         */
+        at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
+
+        at32_add_device_usart(0);
+
+        /* Reserve PB29 (GCLK3). This pin is used as clock source
+         * for ETH PHY (25MHz). GCLK3 setup is done by U-Boot.
+         */
+        at32_reserve_pin(GPIO_PIOB_BASE, (1<<29));
+
+        /*
+         * Hammerhead uses only one ethernet port, so we don't set
+         * address of second port
+         */
+        set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA
+        at32_add_device_hh_fpga();
+#endif
+        at32_add_device_mci(0, &mci0_data);
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_USB
+        at32_add_device_usba(0, NULL);
+#endif
+#ifdef CONFIG_BOARD_HAMMERHEAD_LCD
+        at32_add_device_lcdc(0, &hammerhead_lcdc_data, fbmem_start,
+                             fbmem_size, ATMEL_LCDC_PRI_24BIT);
+#endif
+
+        at32_select_gpio(i2c_gpio_data.sda_pin,
+                         AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT |
+                         AT32_GPIOF_HIGH);
+        at32_select_gpio(i2c_gpio_data.scl_pin,
+                         AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT |
+                         AT32_GPIOF_HIGH);
+        platform_device_register(&i2c_gpio_device);
+        i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
+
+#ifdef CONFIG_BOARD_HAMMERHEAD_SND
+        at32_add_device_ac97c(0, &ac97c_data);
+#endif
+
+        /* Select the Touchscreen interrupt pin mode */
+        at32_select_periph(GPIO_PIOB_BASE, 0x08000000, GPIO_PERIPH_A, 0);
+
+        return 0;
+}
+
+postcore_initcall(hammerhead_init);
diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c
index 397cbb8f44c8..2b58d61f0afc 100644
--- a/arch/avr32/boards/mimc200/setup.c
+++ b/arch/avr32/boards/mimc200/setup.c
@@ -24,7 +24,7 @@ extern struct atmel_lcdfb_info mimc200_lcdc_data;
 #include <video/atmel_lcdc.h>
 #include <linux/fb.h>
 
-#include <asm/atmel-mci.h>
+#include <linux/atmel-mci.h>
 #include <linux/io.h>
 #include <asm/setup.h>
 
@@ -207,8 +207,6 @@ static int __init mimc200_init(void)
          * reserve any pins for it.
          */
 
-        at32_add_system_devices();
-
         at32_add_device_usart(0);
         at32_add_device_usart(1);
         at32_add_device_usart(2);
diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
index 541520912c55..164e2814ae78 100644
--- a/arch/avr32/configs/atngw100_defconfig
+++ b/arch/avr32/configs/atngw100_defconfig
@@ -892,7 +892,7 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
-CONFIG_DMATEST=m
+# CONFIG_DMATEST is not set
 # CONFIG_UIO is not set
 
 #
diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
index 69fce6b6a783..c9dc64832a19 100644
--- a/arch/avr32/configs/atstk1002_defconfig
+++ b/arch/avr32/configs/atstk1002_defconfig
@@ -964,7 +964,7 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
-CONFIG_DMATEST=m
+# CONFIG_DMATEST is not set
 # CONFIG_UIO is not set
 
 #
diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
index 5477ed3183b4..29ea1327b498 100644
--- a/arch/avr32/configs/atstk1003_defconfig
+++ b/arch/avr32/configs/atstk1003_defconfig
@@ -882,7 +882,7 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
-CONFIG_DMATEST=m
+# CONFIG_DMATEST is not set
 # CONFIG_UIO is not set
 
 #
diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
index 6c45a3b77aa3..361c31c2af10 100644
--- a/arch/avr32/configs/atstk1006_defconfig
+++ b/arch/avr32/configs/atstk1006_defconfig
@@ -1014,7 +1014,7 @@ CONFIG_DMA_ENGINE=y
 # DMA Clients
 #
 # CONFIG_NET_DMA is not set
-CONFIG_DMATEST=m
+# CONFIG_DMATEST is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 CONFIG_STAGING_EXCLUDE_BUILD=y
diff --git a/arch/avr32/configs/hammerhead_defconfig b/arch/avr32/configs/hammerhead_defconfig
new file mode 100644
index 000000000000..0d3d2982c8f5
--- /dev/null
+++ b/arch/avr32/configs/hammerhead_defconfig
@@ -0,0 +1,1467 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27
+# Tue Dec  9 15:37:30 2008
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP700X=y
+CONFIG_CPU_AT32AP7000=y
+# CONFIG_BOARD_ATSTK1000 is not set
+# CONFIG_BOARD_ATNGW100 is not set
+CONFIG_BOARD_HAMMERHEAD=y
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
+CONFIG_BOARD_HAMMERHEAD_USB=y
+CONFIG_BOARD_HAMMERHEAD_LCD=y
+CONFIG_BOARD_HAMMERHEAD_SND=y
+# CONFIG_BOARD_HAMMERHEAD_FPGA is not set
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+# CONFIG_AP700X_32_BIT_SMC is not set
+CONFIG_AP700X_16_BIT_SMC=y
+# CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_OWNERSHIP_TRACE is not set
+# CONFIG_NMI_DEBUGGING is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x80000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AT32PSIF is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT32AP700X_WDT=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BRIGHT=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DELL=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_THRUSTMASTER_FF=m
+CONFIG_ZEROPLUS_FF=m
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_ISP116X_HCD=m
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_ATMELMCI=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT32AP700X=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/avr32/include/asm/kdebug.h b/arch/avr32/include/asm/kdebug.h
index ca4f9542365a..f930ce286803 100644
--- a/arch/avr32/include/asm/kdebug.h
+++ b/arch/avr32/include/asm/kdebug.h
@@ -6,6 +6,7 @@ enum die_val {
         DIE_BREAKPOINT,
         DIE_SSTEP,
         DIE_NMI,
+        DIE_OOPS,
 };
 
 #endif /* __ASM_AVR32_KDEBUG_H */
diff --git a/arch/avr32/include/asm/syscalls.h b/arch/avr32/include/asm/syscalls.h
new file mode 100644
index 000000000000..483d666c27c0
--- /dev/null
+++ b/arch/avr32/include/asm/syscalls.h
@@ -0,0 +1,39 @@
+/*
+ * syscalls.h - Linux syscall interfaces (arch-specific)
+ *
+ * Copyright (c) 2008 Jaswinder Singh
+ *
+ * This file is released under the GPLv2.
+ * See the file COPYING for more details.
+ */
+
+#ifndef _ASM_AVR32_SYSCALLS_H
+#define _ASM_AVR32_SYSCALLS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/signal.h>
+
+/* kernel/process.c */
+asmlinkage int sys_fork(struct pt_regs *);
+asmlinkage int sys_clone(unsigned long, unsigned long,
+                         unsigned long, unsigned long,
+                         struct pt_regs *);
+asmlinkage int sys_vfork(struct pt_regs *);
+asmlinkage int sys_execve(char __user *, char __user *__user *,
+                          char __user *__user *, struct pt_regs *);
+
+/* kernel/signal.c */
+asmlinkage int sys_sigaltstack(const stack_t __user *, stack_t __user *,
+                               struct pt_regs *);
+asmlinkage int sys_rt_sigreturn(struct pt_regs *);
+
+/* kernel/sys_avr32.c */
+asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long,
+                          unsigned long, unsigned long, off_t);
+
+/* mm/cache.c */
+asmlinkage int sys_cacheflush(int, void __user *, size_t);
+
+#endif /* _ASM_AVR32_SYSCALLS_H */
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index 134d5302b6dd..43ae555ecb33 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -18,6 +18,7 @@
 
 #include <asm/sysreg.h>
 #include <asm/ocd.h>
+#include <asm/syscalls.h>
 
 #include <mach/pm.h>
 
diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c
index c5b11f9067f1..803d7be0938f 100644
--- a/arch/avr32/kernel/signal.c
+++ b/arch/avr32/kernel/signal.c
@@ -19,6 +19,7 @@
 
 #include <asm/uaccess.h>
 #include <asm/ucontext.h>
+#include <asm/syscalls.h>
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
diff --git a/arch/avr32/kernel/sys_avr32.c b/arch/avr32/kernel/sys_avr32.c
index 8e8911e55c8f..5d2daeaf356f 100644
--- a/arch/avr32/kernel/sys_avr32.c
+++ b/arch/avr32/kernel/sys_avr32.c
@@ -13,6 +13,7 @@
 
 #include <asm/mman.h>
 #include <asm/uaccess.h>
+#include <asm/syscalls.h>
 
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                           unsigned long prot, unsigned long flags,
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 066252eebf61..ea7bc1e8562b 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -15,8 +15,8 @@
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/atmel_usba_udc.h>
+#include <linux/atmel-mci.h>
 
-#include <asm/atmel-mci.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
@@ -421,7 +421,7 @@ static unsigned long hsb_clk_get_rate(struct clk *clk)
         return bus_clk_get_rate(clk, shift);
 }
 
-static void pba_clk_mode(struct clk *clk, int enabled)
+void pba_clk_mode(struct clk *clk, int enabled)
 {
         unsigned long flags;
         u32 mask;
@@ -436,7 +436,7 @@ static void pba_clk_mode(struct clk *clk, int enabled)
         spin_unlock_irqrestore(&pm_lock, flags);
 }
 
-static unsigned long pba_clk_get_rate(struct clk *clk)
+unsigned long pba_clk_get_rate(struct clk *clk)
 {
         unsigned long cksel, shift = 0;
 
diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
index 623bf0e9a1e7..4c7ebbdc6dfa 100644
--- a/arch/avr32/mach-at32ap/clock.h
+++ b/arch/avr32/mach-at32ap/clock.h
@@ -30,3 +30,6 @@ struct clk {
         u16             users;          /* Enabled if non-zero */
         u16             index;          /* Sibling index */
 };
+
+unsigned long pba_clk_get_rate(struct clk *clk);
+void pba_clk_mode(struct clk *clk, int enabled);
diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
index a77d372f6f3e..5c4c971eed8e 100644
--- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
+++ b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
@@ -211,4 +211,7 @@
 
 #define ATMEL_LCDC_ALT_15BIT    (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
 
+/* Bitmask for all EBI data (D16..D31) pins on port E */
+#define ATMEL_EBI_PE_DATA_ALL  (0x0000FFFF)
+
 #endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h
index 21c79373b53f..4873024e3b96 100644
--- a/arch/avr32/mach-at32ap/include/mach/portmux.h
+++ b/arch/avr32/mach-at32ap/include/mach/portmux.h
@@ -25,6 +25,6 @@ void at32_select_periph(unsigned int port, unsigned int pin,
                         unsigned int periph, unsigned long flags);
 void at32_select_gpio(unsigned int pin, unsigned long flags);
 void at32_deselect_pin(unsigned int pin);
-void at32_reserve_pin(unsigned int pin);
+void at32_reserve_pin(unsigned int port, u32 pin_mask);
 
 #endif /* __ASM_ARCH_PORTMUX_H__ */
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index ed81a8bcb22d..09a274c9d0b7 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -167,22 +167,29 @@ void at32_deselect_pin(unsigned int pin)
 }
 
 /* Reserve a pin, preventing anyone else from changing its configuration. */
-void __init at32_reserve_pin(unsigned int pin)
+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
 {
         struct pio_device *pio;
-        unsigned int pin_index = pin & 0x1f;
 
-        pio = gpio_to_pio(pin);
+        /* assign and verify pio */
+        pio = gpio_to_pio(port);
         if (unlikely(!pio)) {
-                printk("pio: invalid pin %u\n", pin);
+                printk(KERN_WARNING "pio: invalid port %u\n", port);
                 goto fail;
         }
 
-        if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
-                printk("%s: pin %u is busy\n", pio->name, pin_index);
+        /* Test if any of the requested pins is already muxed */
+        spin_lock(&pio_lock);
+        if (unlikely(pio->pinmux_mask & pin_mask)) {
+                printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
+                       pio->name, pin_mask, pio->pinmux_mask & pin_mask);
+                spin_unlock(&pio_lock);
                 goto fail;
         }
 
+        /* Reserve pins */
+        pio->pinmux_mask |= pin_mask;
+        spin_unlock(&pio_lock);
         return;
 
 fail:
diff --git a/arch/avr32/mm/cache.c b/arch/avr32/mm/cache.c
index 15a4e5e142c1..24a74d1ca7d9 100644
--- a/arch/avr32/mm/cache.c
+++ b/arch/avr32/mm/cache.c
@@ -13,6 +13,7 @@
 #include <asm/cachectl.h>
 #include <asm/processor.h>
 #include <asm/uaccess.h>
+#include <asm/syscalls.h>
 
 /*
  * If you attempt to flush anything more than this, you need superuser
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index fa92ff6d95f7..e819fa69a90e 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -97,7 +97,6 @@ void __init paging_init(void)
 
         mem_map = NODE_DATA(0)->node_mem_map;
 
-        memset(zero_page, 0, PAGE_SIZE);
         empty_zero_page = virt_to_page(zero_page);
         flush_dcache_page(empty_zero_page);
 }
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 29e71ed6b8a7..a949c4fbbddd 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -26,6 +26,7 @@ config BLACKFIN
         default y
         select HAVE_IDE
         select HAVE_OPROFILE
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ZONE_DMA
         bool
@@ -59,10 +60,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config HARDWARE_PM
-        def_bool y
-        depends on OPROFILE
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.preempt"
@@ -77,6 +74,26 @@ choice
         prompt "CPU"
         default BF533
 
+config BF512
+        bool "BF512"
+        help
+          BF512 Processor Support.
+
+config BF514
+        bool "BF514"
+        help
+          BF514 Processor Support.
+
+config BF516
+        bool "BF516"
+        help
+          BF516 Processor Support.
+
+config BF518
+        bool "BF518"
+        help
+          BF518 Processor Support.
+
 config BF522
         bool "BF522"
         help
@@ -137,6 +154,16 @@ config BF537
         help
           BF537 Processor Support.
 
+config BF538
+        bool "BF538"
+        help
+          BF538 Processor Support.
+
+config BF539
+        bool "BF539"
+        help
+          BF539 Processor Support.
+
 config BF542
         bool "BF542"
         help
@@ -169,28 +196,55 @@ config BF561
 
 endchoice
 
+config SMP
+        depends on BF561
+        bool "Symmetric multi-processing support"
+        ---help---
+          This enables support for systems with more than one CPU,
+          like the dual core BF561. If you have a system with only one
+          CPU, say N. If you have a system with more than one CPU, say Y.
+
+          If you don't know what to do here, say N.
+
+config NR_CPUS
+        int
+        depends on SMP
+        default 2 if BF561
+
+config IRQ_PER_CPU
+        bool
+        depends on SMP
+        default y
+
+config TICK_SOURCE_SYSTMR0
+        bool
+        select BFIN_GPTIMERS
+        depends on SMP
+        default y
+
 config BF_REV_MIN
         int
-        default 0 if (BF52x || BF54x)
+        default 0 if (BF51x || BF52x || BF54x)
         default 2 if (BF537 || BF536 || BF534)
         default 3 if (BF561 ||BF533 || BF532 || BF531)
+        default 4 if (BF538 || BF539)
 
 config BF_REV_MAX
         int
-        default 2 if (BF52x || BF54x)
+        default 2 if (BF51x || BF52x || BF54x)
         default 3 if (BF537 || BF536 || BF534)
-        default 5 if (BF561)
+        default 5 if (BF561 || BF538 || BF539)
         default 6 if (BF533 || BF532 || BF531)
 
 choice
         prompt "Silicon Rev"
-        default BF_REV_0_1 if (BF52x || BF54x)
+        default BF_REV_0_1 if (BF51x || BF52x || BF54x)
         default BF_REV_0_2 if (BF534 || BF536 || BF537)
         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 
 config BF_REV_0_0
         bool "0.0"
-        depends on (BF52x || BF54x)
+        depends on (BF51x || BF52x || BF54x)
 
 config BF_REV_0_1
         bool "0.1"
@@ -206,11 +260,11 @@ config BF_REV_0_3
 
 config BF_REV_0_4
         bool "0.4"
-        depends on (BF561 || BF533 || BF532 || BF531)
+        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 
 config BF_REV_0_5
         bool "0.5"
-        depends on (BF561 || BF533 || BF532 || BF531)
+        depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 
 config BF_REV_0_6
         bool "0.6"
@@ -224,6 +278,11 @@ config BF_REV_NONE
 
 endchoice
 
+config BF51x
+        bool
+        depends on (BF512 || BF514 || BF516 || BF518)
+        default y
+
 config BF52x
         bool
         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
@@ -258,7 +317,7 @@ config MEM_MT48LC16M16A2TG_75
 
 config MEM_MT48LC32M8A2_75
         bool
-        depends on (BFIN537_STAMP || PNAV10)
+        depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
         default y
 
 config MEM_MT48LC8M32B2B5_7
@@ -271,10 +330,17 @@ config MEM_MT48LC32M16A2TG_75
         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
         default y
 
+config MEM_MT48LC32M8A2_75
+        bool
+        depends on (BFIN518F_EZBRD)
+        default y
+
+source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
 source "arch/blackfin/mach-bf561/Kconfig"
 source "arch/blackfin/mach-bf537/Kconfig"
+source "arch/blackfin/mach-bf538/Kconfig"
 source "arch/blackfin/mach-bf548/Kconfig"
 
 menu "Board customizations"
@@ -307,6 +373,7 @@ config BOOT_LOAD
 
 config ROM_BASE
         hex "Kernel ROM Base"
+        depends on ROMKERNEL
         default "0x20040000"
         range 0x20000000 0x20400000 if !(BF54x || BF561)
         range 0x20000000 0x30000000 if (BF54x || BF561)
@@ -318,7 +385,7 @@ config CLKIN_HZ
         int "Frequency of the crystal on the board in Hz"
         default "11059200" if BFIN533_STAMP
         default "27000000" if BFIN533_EZKIT
-        default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
+        default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
         default "30000000" if BFIN561_EZKIT
         default "24576000" if PNAV10
         default "10000000" if BFIN532_IP0X
@@ -354,11 +421,11 @@ config VCO_MULT
         range 1 64
         default "22" if BFIN533_EZKIT
         default "45" if BFIN533_STAMP
-        default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
+        default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
         default "22" if BFIN533_BLUETECHNIX_CM
         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
         default "20" if BFIN561_EZKIT
-        default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
+        default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
         help
           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
           PLL Frequency = (Crystal Frequency) * (this setting)
@@ -407,19 +474,70 @@ config MEM_MT46V32M16_5B
         bool "MT46V32M16_5B"
 endchoice
 
-config MAX_MEM_SIZE
-        int "Max SDRAM Memory Size in MBytes"
-        depends on !MPU
-        default 512
+choice
+        prompt "DDR/SDRAM Timing"
+        depends on BFIN_KERNEL_CLOCK
+        default BFIN_KERNEL_CLOCK_MEMINIT_CALC
         help
-          This is the max memory size that the kernel will create CPLB
-          tables for.  Your system will not be able to handle any more.
+          This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+          The calculated SDRAM timing parameters may not be 100%
+          accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+        bool "Calculate Timings (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+        bool "Provide accurate Timings based on target SCLK"
+        help
+          Please consult the Blackfin Hardware Reference Manuals as well
+          as the memory device datasheet.
+          http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+        depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+        depends on BF54x
+        hex "DDRCTL0"
+        default 0x0
+
+config MEM_DDRCTL1
+        depends on BF54x
+        hex "DDRCTL1"
+        default 0x0
+
+config MEM_DDRCTL2
+        depends on BF54x
+        hex "DDRCTL2"
+        default 0x0
+
+config MEM_EBIU_DDRQUE
+        depends on BF54x
+        hex "DDRQUE"
+        default 0x0
+
+config MEM_SDRRC
+        depends on !BF54x
+        hex "SDRRC"
+        default 0x0
+
+config MEM_SDGCTL
+        depends on !BF54x
+        hex "SDGCTL"
+        default 0x0
+endmenu
 
 #
 # Max & Min Speeds for various Chips
 #
 config MAX_VCO_HZ
         int
+        default 400000000 if BF512
+        default 400000000 if BF514
+        default 400000000 if BF516
+        default 400000000 if BF518
         default 600000000 if BF522
         default 400000000 if BF523
         default 400000000 if BF524
@@ -459,6 +577,7 @@ source kernel/Kconfig.hz
 
 config GENERIC_TIME
         bool "Generic time"
+        depends on !SMP
         default y
 
 config GENERIC_CLOCKEVENTS
@@ -533,6 +652,7 @@ endmenu
 
 
 menu "Blackfin Kernel Optimizations"
+        depends on !SMP
 
 comment "Memory Optimizations"
 
@@ -655,6 +775,17 @@ config APP_STACK_L1
 
           Currently only works with FLAT binaries.
 
+config EXCEPTION_L1_SCRATCH
+        bool "Locate exception stack in L1 Scratch Memory"
+        default n
+        depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
+        help
+          Whenever an exception occurs, use the L1 Scratch memory for
+          stack storage.  You cannot place the stacks of FLAT binaries
+          in L1 when using this option.
+
+          If you don't use L1 Scratch, then you should say Y here.
+
 comment "Speed Optimizations"
 config BFIN_INS_LOWOVERHEAD
         bool "ins[bwl] low overhead, higher interrupt latency"
@@ -684,7 +815,6 @@ config BFIN_INS_LOWOVERHEAD
 
 endmenu
 
-
 choice
         prompt "Kernel executes from"
         help
@@ -714,17 +844,9 @@ config BFIN_GPTIMERS
           To compile this driver as a module, choose M here: the module
           will be called gptimers.ko.
 
-config BFIN_DMA_5XX
-        bool "Enable DMA Support"
-        depends on (BF52x || BF53x || BF561 || BF54x)
-        default y
-        help
-          DMA driver for BF5xx.
-
 choice
-        prompt "Uncached SDRAM region"
+        prompt "Uncached DMA region"
         default DMA_UNCACHED_1M
-        depends on BFIN_DMA_5XX
 config DMA_UNCACHED_4M
         bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M
@@ -751,9 +873,11 @@ config BFIN_ICACHE_LOCK
 choice
         prompt "Policy"
         depends on BFIN_DCACHE
-        default BFIN_WB
+        default BFIN_WB if !SMP
+        default BFIN_WT if SMP
 config BFIN_WB
         bool "Write back"
+        depends on !SMP
         help
           Write Back Policy:
             Cached data will be written back to SDRAM only when needed.
@@ -790,7 +914,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
         bool "Cache L2 SRAM"
-        depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+        depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
         default n
         help
           Select to make L2 SRAM cacheable in L1 data and instruction cache.
@@ -980,7 +1104,7 @@ config PM_WAKEUP_GPIO_NUMBER
         int "GPIO number"
         range 0 47
         depends on PM_WAKEUP_BY_GPIO
-        default 2 if BFIN537_STAMP
+        default 2
 
 choice
         prompt "GPIO Polarity"
@@ -1003,7 +1127,7 @@ comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
 
 config PM_BFIN_WAKE_PH6
         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
-        depends on PM && (BF52x || BF534 || BF536 || BF537)
+        depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
         default n
         help
           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
@@ -1020,15 +1144,21 @@ menu "CPU Frequency scaling"
 
 source "drivers/cpufreq/Kconfig"
 
+config BFIN_CPU_FREQ
+        bool
+        depends on CPU_FREQ
+        select CPU_FREQ_TABLE
+        default y
+
 config CPU_VOLTAGE
         bool "CPU Voltage scaling"
-        depends on EXPERIMENTAL 
+        depends on EXPERIMENTAL
         depends on CPU_FREQ
         default n
         help
           Say Y here if you want CPU voltage scaling according to the CPU frequency.
           This option violates the PLL BYPASS recommendation in the Blackfin Processor
-          manuals. There is a theoretical risk that during VDDINT transitions 
+          manuals. There is a theoretical risk that during VDDINT transitions
           the PLL may unlock.
 
 endmenu
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 3ad25983ec97..5f981d9ca625 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -2,8 +2,30 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
+config DEBUG_STACKOVERFLOW
+        bool "Check for stack overflows"
+        depends on DEBUG_KERNEL
+        help
+          This option will cause messages to be printed if free stack space
+          drops below a certain limit.
+
+config DEBUG_STACK_USAGE
+        bool "Enable stack utilization instrumentation"
+        depends on DEBUG_KERNEL
+        help
+          Enables the display of the minimum amount of free stack which each
+          task has ever had available in the sysrq-T output.
+
+          This option will slow down process creation somewhat.
+
 config HAVE_ARCH_KGDB
-       def_bool y
+        def_bool y
+
+config KGDB_TESTCASE
+        tristate "KGDB: for test case in expect"
+        default n
+        help
+          This is a kgdb test case for automated testing.
 
 config DEBUG_VERBOSE
         bool "Verbose fault messages"
@@ -182,11 +204,11 @@ config DEBUG_BFIN_HWTRACE_EXPAND_LEN
           4 for (2^4) 16k, or 4096 entries
 
 config DEBUG_BFIN_NO_KERN_HWTRACE
-        bool "Trace user apps (turn off hwtrace in kernel)"
+        bool "Turn off hwtrace in CPLB handlers"
         depends on DEBUG_BFIN_HWTRACE_ON
-        default n
+        default y
         help
-          Some pieces of the kernel contain a lot of flow changes which can
+          The CPLB error handler contains a lot of flow changes which can
           quickly fill up the hardware trace buffer.  When debugging crashes,
           the hardware trace may indicate that the problem lies in kernel
           space when in reality an application is buggy.
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 6bf50977850c..e550c8d46066 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -21,6 +21,10 @@ KALLSYMS         += --symbol-prefix=_
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
 
 # setup the machine name and the machine dependent settings
+machine-$(CONFIG_BF512) := bf518
+machine-$(CONFIG_BF514) := bf518
+machine-$(CONFIG_BF516) := bf518
+machine-$(CONFIG_BF518) := bf518
 machine-$(CONFIG_BF522) := bf527
 machine-$(CONFIG_BF523) := bf527
 machine-$(CONFIG_BF524) := bf527
@@ -33,6 +37,8 @@ machine-$(CONFIG_BF533) := bf533
 machine-$(CONFIG_BF534) := bf537
 machine-$(CONFIG_BF536) := bf537
 machine-$(CONFIG_BF537) := bf537
+machine-$(CONFIG_BF538) := bf538
+machine-$(CONFIG_BF539) := bf538
 machine-$(CONFIG_BF542) := bf548
 machine-$(CONFIG_BF544) := bf548
 machine-$(CONFIG_BF547) := bf548
@@ -42,6 +48,10 @@ machine-$(CONFIG_BF561) := bf561
 MACHINE := $(machine-y)
 export MACHINE
 
+cpu-$(CONFIG_BF512) := bf512
+cpu-$(CONFIG_BF514) := bf514
+cpu-$(CONFIG_BF516) := bf516
+cpu-$(CONFIG_BF518) := bf518
 cpu-$(CONFIG_BF522) := bf522
 cpu-$(CONFIG_BF523) := bf523
 cpu-$(CONFIG_BF524) := bf524
@@ -54,6 +64,8 @@ cpu-$(CONFIG_BF533) := bf533
 cpu-$(CONFIG_BF534) := bf534
 cpu-$(CONFIG_BF536) := bf536
 cpu-$(CONFIG_BF537) := bf537
+cpu-$(CONFIG_BF538) := bf538
+cpu-$(CONFIG_BF539) := bf539
 cpu-$(CONFIG_BF542) := bf542
 cpu-$(CONFIG_BF544) := bf544
 cpu-$(CONFIG_BF547) := bf547
@@ -79,7 +91,7 @@ KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
 CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__
 
-head-y   := arch/$(ARCH)/mach-$(MACHINE)/head.o arch/$(ARCH)/kernel/init_task.o
+head-y   := arch/$(ARCH)/kernel/init_task.o
 
 core-y   += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
 
@@ -95,10 +107,10 @@ else
 core-y  += arch/$(ARCH)/kernel/cplb-nompu/
 endif
 
-libs-y   += arch/$(ARCH)/lib/
-
 drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
 
+libs-y   += arch/$(ARCH)/lib/
+
 machdirs        := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
 
 KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
new file mode 100644
index 000000000000..e0b3f242b555
--- /dev/null
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -0,0 +1,1191 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc2
+#
+# CONFIG_MMU is not set
+# CONFIG_FPU is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_BLACKFIN=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
+
+#
+# Blackfin Processor Options
+#
+
+#
+# Processor and Board Settings
+#
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+CONFIG_BF518=y
+# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
+# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
+# CONFIG_BF527 is not set
+# CONFIG_BF531 is not set
+# CONFIG_BF532 is not set
+# CONFIG_BF533 is not set
+# CONFIG_BF534 is not set
+# CONFIG_BF536 is not set
+# CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
+# CONFIG_BF542 is not set
+# CONFIG_BF544 is not set
+# CONFIG_BF547 is not set
+# CONFIG_BF548 is not set
+# CONFIG_BF549 is not set
+# CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=0
+CONFIG_BF_REV_MAX=2
+CONFIG_BF_REV_0_0=y
+# CONFIG_BF_REV_0_1 is not set
+# CONFIG_BF_REV_0_2 is not set
+# CONFIG_BF_REV_0_3 is not set
+# CONFIG_BF_REV_0_4 is not set
+# CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
+# CONFIG_BF_REV_ANY is not set
+# CONFIG_BF_REV_NONE is not set
+CONFIG_BF51x=y
+CONFIG_BFIN518F_EZBRD=y
+
+#
+# BF518 Specific Configuration
+#
+
+#
+# Alternative Multiplexing Scheme
+#
+# CONFIG_BF518_SPORT0_PORTF is not set
+CONFIG_BF518_SPORT0_PORTG=y
+CONFIG_BF518_SPORT0_TSCLK_PG10=y
+# CONFIG_BF518_SPORT0_TSCLK_PG14 is not set
+CONFIG_BF518_UART1_PORTF=y
+# CONFIG_BF518_UART1_PORTG is not set
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_PLL_WAKEUP=7
+CONFIG_IRQ_DMA0_ERROR=7
+CONFIG_IRQ_DMAR0_BLK=7
+CONFIG_IRQ_DMAR1_BLK=7
+CONFIG_IRQ_DMAR0_OVR=7
+CONFIG_IRQ_DMAR1_OVR=7
+CONFIG_IRQ_PPI_ERROR=7
+CONFIG_IRQ_MAC_ERROR=7
+CONFIG_IRQ_SPORT0_ERROR=7
+CONFIG_IRQ_SPORT1_ERROR=7
+CONFIG_IRQ_PTP_ERROR=7
+CONFIG_IRQ_UART0_ERROR=7
+CONFIG_IRQ_UART1_ERROR=7
+CONFIG_IRQ_RTC=8
+CONFIG_IRQ_PPI=8
+CONFIG_IRQ_SPORT0_RX=9
+CONFIG_IRQ_SPORT0_TX=9
+CONFIG_IRQ_SPORT1_RX=9
+CONFIG_IRQ_SPORT1_TX=9
+CONFIG_IRQ_TWI=10
+CONFIG_IRQ_SPI0=10
+CONFIG_IRQ_UART0_RX=10
+CONFIG_IRQ_UART0_TX=10
+CONFIG_IRQ_UART1_RX=10
+CONFIG_IRQ_UART1_TX=10
+CONFIG_IRQ_OPTSEC=11
+CONFIG_IRQ_CNT=11
+CONFIG_IRQ_MAC_RX=11
+CONFIG_IRQ_PORTH_INTA=11
+CONFIG_IRQ_MAC_TX=11
+CONFIG_IRQ_PORTH_INTB=11
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
+CONFIG_IRQ_PORTG_INTA=12
+CONFIG_IRQ_PORTG_INTB=12
+CONFIG_IRQ_MEM_DMA0=13
+CONFIG_IRQ_MEM_DMA1=13
+CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_PORTF_INTA=13
+CONFIG_IRQ_PORTF_INTB=13
+CONFIG_IRQ_SPI0_ERROR=7
+CONFIG_IRQ_SPI1_ERROR=7
+CONFIG_IRQ_RSI_INT0=7
+CONFIG_IRQ_RSI_INT1=7
+CONFIG_IRQ_PWM_TRIP=10
+CONFIG_IRQ_PWM_SYNC=10
+CONFIG_IRQ_PTP_STAT=10
+
+#
+# Board customizations
+#
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
+
+#
+# Clock/PLL Setup
+#
+CONFIG_CLKIN_HZ=25000000
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+CONFIG_MAX_VCO_HZ=400000000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133333333
+CONFIG_MIN_SCLK_HZ=27000000
+
+#
+# Kernel Timer/Scheduler
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# Misc
+#
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+
+#
+# Blackfin Kernel Optimizations
+#
+
+#
+# Memory Optimizations
+#
+CONFIG_I_ENTRY_L1=y
+CONFIG_EXCPT_IRQ_SYSC_L1=y
+CONFIG_DO_IRQ_L1=y
+CONFIG_CORE_TIMER_IRQ_L1=y
+CONFIG_IDLE_L1=y
+# CONFIG_SCHEDULE_L1 is not set
+CONFIG_ARITHMETIC_OPS_L1=y
+CONFIG_ACCESS_OK_L1=y
+# CONFIG_MEMSET_L1 is not set
+# CONFIG_MEMCPY_L1 is not set
+# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
+# CONFIG_IP_CHECKSUM_L1 is not set
+CONFIG_CACHELINE_ALIGNED_L1=y
+# CONFIG_SYSCALL_TAB_L1 is not set
+# CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
+CONFIG_RAMKERNEL=y
+# CONFIG_ROMKERNEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_VIRT_TO_BUS=y
+CONFIG_BFIN_GPTIMERS=y
+# CONFIG_DMA_UNCACHED_4M is not set
+# CONFIG_DMA_UNCACHED_2M is not set
+CONFIG_DMA_UNCACHED_1M=y
+# CONFIG_DMA_UNCACHED_NONE is not set
+
+#
+# Cache Support
+#
+CONFIG_BFIN_ICACHE=y
+CONFIG_BFIN_DCACHE=y
+# CONFIG_BFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
+CONFIG_BFIN_WB=y
+# CONFIG_BFIN_WT is not set
+# CONFIG_MPU is not set
+
+#
+# Asynchonous Memory Configuration
+#
+
+#
+# EBIU_AMGCTL Global Control
+#
+CONFIG_C_AMCKEN=y
+CONFIG_C_CDPRIO=y
+# CONFIG_C_AMBEN is not set
+# CONFIG_C_AMBEN_B0 is not set
+# CONFIG_C_AMBEN_B0_B1 is not set
+# CONFIG_C_AMBEN_B0_B1_B2 is not set
+CONFIG_C_AMBEN_ALL=y
+
+#
+# EBIU_AMBCTL Control
+#
+CONFIG_BANK_0=0x7BB0
+CONFIG_BANK_1=0x5554
+CONFIG_BANK_2=0x7BB0
+CONFIG_BANK_3=0xFFC0
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF_FDPIC=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM_WAKEUP_BY_GPIO is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=m
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_UCLINUX is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_BFIN_MAC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_AD9960 is not set
+# CONFIG_SPI_ADC_BF533 is not set
+# CONFIG_BF5xx_PPIFCD is not set
+# CONFIG_BFIN_SIMPLE_TIMER is not set
+# CONFIG_BF5xx_PPI is not set
+# CONFIG_BFIN_SPORT is not set
+# CONFIG_BFIN_TIMER_LATENCY is not set
+# CONFIG_TWI_LCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+CONFIG_SIMPLE_GPIO=m
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_DMA=y
+# CONFIG_SERIAL_BFIN_PIO is not set
+CONFIG_SERIAL_BFIN_UART0=y
+# CONFIG_BFIN_UART0_CTSRTS is not set
+# CONFIG_SERIAL_BFIN_UART1 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_BFIN_SPORT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# CAN, the car bus and industrial fieldbus
+#
+# CONFIG_CAN4LINUX is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_AD5252 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_BFIN_WDT=y
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_BFIN=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_YAFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
+CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
+CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
+# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_ACCESS_CHECK=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 4443a47e516f..69f66c35b2a5 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -1,7 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26.3
-# Thu Aug 28 16:49:53 2008
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -37,8 +36,7 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -48,13 +46,13 @@ CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
@@ -63,6 +61,7 @@ CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -70,9 +69,7 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
-# CONFIG_HAVE_KPROBES is not set
-# CONFIG_HAVE_KRETPROBES is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
@@ -89,6 +86,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -106,6 +104,7 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -114,6 +113,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -126,49 +129,27 @@ CONFIG_BF526=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=0
+CONFIG_BF_REV_MAX=2
 CONFIG_BF_REV_0_0=y
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF52x=y
 CONFIG_MEM_MT48LC32M16A2TG_75=y
-# CONFIG_BFIN527_EZKIT is not set
-# CONFIG_BFIN527_BLUETECHNIX_CM is not set
-CONFIG_BFIN526_EZBRD=y
-
-#
-# BF527 Specific Configuration
-#
-
-#
-# Alternative Multiplexing Scheme
-#
-# CONFIG_BF527_SPORT0_PORTF is not set
-CONFIG_BF527_SPORT0_PORTG=y
-CONFIG_BF527_SPORT0_TSCLK_PG10=y
-# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
-CONFIG_BF527_UART1_PORTF=y
-# CONFIG_BF527_UART1_PORTG is not set
-# CONFIG_BF527_NAND_D_PORTF is not set
-CONFIG_BF527_NAND_D_PORTH=y
-
-#
-# Interrupt Priority Assignment
-#
-
-#
-# Priority
-#
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_DMA0_ERROR=7
 CONFIG_IRQ_DMAR0_BLK=7
@@ -188,7 +169,6 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
@@ -199,14 +179,14 @@ CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_PORTH_INTA=11
 CONFIG_IRQ_MAC_TX=11
 CONFIG_IRQ_PORTH_INTB=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTA=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
@@ -214,6 +194,34 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_PORTF_INTA=13
 CONFIG_IRQ_PORTF_INTB=13
+# CONFIG_BFIN527_EZKIT is not set
+# CONFIG_BFIN527_BLUETECHNIX_CM is not set
+CONFIG_BFIN526_EZBRD=y
+
+#
+# BF527 Specific Configuration
+#
+
+#
+# Alternative Multiplexing Scheme
+#
+# CONFIG_BF527_SPORT0_PORTF is not set
+CONFIG_BF527_SPORT0_PORTG=y
+CONFIG_BF527_SPORT0_TSCLK_PG10=y
+# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
+CONFIG_BF527_UART1_PORTF=y
+# CONFIG_BF527_UART1_PORTG is not set
+# CONFIG_BF527_NAND_D_PORTF is not set
+CONFIG_BF527_NAND_D_PORTH=y
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_SPI=10
 CONFIG_IRQ_SPI_ERROR=7
 CONFIG_IRQ_NFC_ERROR=7
 CONFIG_IRQ_HDMA_ERROR=7
@@ -235,7 +243,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=25000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=400000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -253,16 +260,11 @@ CONFIG_HZ=250
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
-# Memory Setup
-#
-
-#
 # Misc
 #
 CONFIG_BFIN_SCRATCH_REG_RETN=y
@@ -291,6 +293,7 @@ CONFIG_ACCESS_OK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
 
 #
 # Speed Optimizations
@@ -304,15 +307,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_BFIN_GPTIMERS=y
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -365,6 +366,7 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
@@ -378,10 +380,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -432,6 +430,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -452,11 +451,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -474,6 +472,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -534,7 +534,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -579,6 +580,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -595,7 +597,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -633,9 +634,10 @@ CONFIG_BFIN_MAC_RMII=y
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
-# CONFIG_E1000E_ENABLED is not set
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
 
@@ -667,7 +669,7 @@ CONFIG_NETDEV_10000=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_POLLDEV is not set
 
 #
@@ -692,8 +694,9 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_UINPUT is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
@@ -712,12 +715,15 @@ CONFIG_INPUT_MISC=y
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_TWI_LCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -760,25 +766,39 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C Hardware Bus support
 #
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
 # CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
@@ -787,12 +807,14 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -801,11 +823,15 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -834,6 +860,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -871,16 +898,14 @@ CONFIG_BFIN_WDT=y
 # CONFIG_USBPCWATCHDOG is not set
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
@@ -915,15 +940,8 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -937,56 +955,40 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# SPI devices
-#
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
-# CONFIG_SND_BFIN_AD73311 is not set
 # CONFIG_SND_BFIN_AD73322 is not set
-
-#
-# USB devices
-#
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
 CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_BF5XX_I2S=m
 CONFIG_SND_BF5XX_SOC_SSM2602=m
-# CONFIG_SND_BF5XX_AC97 is not set
+# CONFIG_SND_BF5XX_SOC_AD73311 is not set
+CONFIG_SND_BF5XX_AC97=m
+CONFIG_SND_BF5XX_MMAP_SUPPORT=y
+# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
 CONFIG_SND_BF5XX_SOC_SPORT=m
 CONFIG_SND_BF5XX_SOC_I2S=m
+CONFIG_SND_BF5XX_SOC_AC97=m
+CONFIG_SND_BF5XX_SOC_AD1980=m
 CONFIG_SND_BF5XX_SPORT_NUM=0
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# SoC Audio for the Texas Instruments OMAP
-#
+# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_AD1980=m
 CONFIG_SND_SOC_SSM2602=m
-
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
@@ -996,9 +998,36 @@ CONFIG_HID=y
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
+# CONFIG_HID_PID is not set
 # CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_THRUSTMASTER_FF=m
+CONFIG_ZEROPLUS_FF=m
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -1016,6 +1045,9 @@ CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
@@ -1026,6 +1058,7 @@ CONFIG_USB_OTG_BLACKLIST_HUB=y
 # CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_SOC=y
 
@@ -1037,7 +1070,7 @@ CONFIG_USB_MUSB_HOST=y
 # CONFIG_USB_MUSB_OTG is not set
 CONFIG_USB_MUSB_HDRC_HCD=y
 CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_LOGLEVEL=0
+# CONFIG_USB_MUSB_DEBUG is not set
 
 #
 # USB Device Class drivers
@@ -1045,6 +1078,7 @@ CONFIG_USB_MUSB_LOGLEVEL=0
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 # CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1059,7 +1093,6 @@ CONFIG_USB_MUSB_LOGLEVEL=0
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-CONFIG_USB_MON=y
 
 #
 # USB port drivers
@@ -1072,7 +1105,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1089,6 +1122,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -1128,36 +1162,45 @@ CONFIG_RTC_INTF_DEV=y
 #
 # SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_DNOTIFY is not set
@@ -1225,6 +1268,7 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -1240,7 +1284,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1308,10 +1352,48 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1329,8 +1411,9 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_SECURITY_ROOTPLUG is not set
 CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
 CONFIG_CRYPTO=y
@@ -1338,6 +1421,7 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 # CONFIG_CRYPTO_MANAGER is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
@@ -1376,6 +1460,10 @@ CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
@@ -1406,15 +1494,20 @@ CONFIG_CRYPTO=y
 #
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 4a2a660a6b35..f92668af00b0 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +87,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,47 +130,27 @@ CONFIG_BF527=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=0
+CONFIG_BF_REV_MAX=2
 CONFIG_BF_REV_0_0=y
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF52x=y
 CONFIG_MEM_MT48LC32M16A2TG_75=y
-CONFIG_BFIN527_EZKIT=y
-
-#
-# BF527 Specific Configuration
-#
-
-#
-# Alternative Multiplexing Scheme
-#
-# CONFIG_BF527_SPORT0_PORTF is not set
-CONFIG_BF527_SPORT0_PORTG=y
-CONFIG_BF527_SPORT0_TSCLK_PG10=y
-# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
-CONFIG_BF527_UART1_PORTF=y
-# CONFIG_BF527_UART1_PORTG is not set
-# CONFIG_BF527_NAND_D_PORTF is not set
-CONFIG_BF527_NAND_D_PORTH=y
-
-#
-# Interrupt Priority Assignment
-#
-
-#
-# Priority
-#
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_DMA0_ERROR=7
 CONFIG_IRQ_DMAR0_BLK=7
@@ -177,7 +170,6 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
@@ -188,14 +180,14 @@ CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_PORTH_INTA=11
 CONFIG_IRQ_MAC_TX=11
 CONFIG_IRQ_PORTH_INTB=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=8
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTA=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
@@ -203,6 +195,34 @@ CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
 CONFIG_IRQ_PORTF_INTA=13
 CONFIG_IRQ_PORTF_INTB=13
+CONFIG_BFIN527_EZKIT=y
+# CONFIG_BFIN527_BLUETECHNIX_CM is not set
+# CONFIG_BFIN526_EZBRD is not set
+
+#
+# BF527 Specific Configuration
+#
+
+#
+# Alternative Multiplexing Scheme
+#
+# CONFIG_BF527_SPORT0_PORTF is not set
+CONFIG_BF527_SPORT0_PORTG=y
+CONFIG_BF527_SPORT0_TSCLK_PG10=y
+# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
+CONFIG_BF527_UART1_PORTF=y
+# CONFIG_BF527_UART1_PORTG is not set
+# CONFIG_BF527_NAND_D_PORTF is not set
+CONFIG_BF527_NAND_D_PORTH=y
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_SPI=10
 CONFIG_IRQ_SPI_ERROR=7
 CONFIG_IRQ_NFC_ERROR=7
 CONFIG_IRQ_HDMA_ERROR=7
@@ -224,7 +244,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=25000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -238,10 +257,10 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -275,6 +294,12 @@ CONFIG_ACCESS_OK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -283,14 +308,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_BFIN_GPTIMERS=y
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -305,7 +329,6 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
 # CONFIG_MPU is not set
 
 #
@@ -334,7 +357,6 @@ CONFIG_BANK_3=0xFFC0
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -345,23 +367,20 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -374,6 +393,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -403,8 +423,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -413,6 +431,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -429,6 +448,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -467,15 +487,6 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_KS959_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_USB_IRDA is not set
@@ -483,11 +494,10 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_MCS_FIR is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -505,6 +515,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -513,6 +525,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -556,6 +569,7 @@ CONFIG_MTD_ROM=m
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -563,7 +577,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -605,11 +620,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -622,7 +640,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -643,6 +660,7 @@ CONFIG_PHYLIB=y
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -655,11 +673,14 @@ CONFIG_BFIN_MAC_RMII=y
 # CONFIG_SMC91X is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -669,6 +690,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -681,7 +703,6 @@ CONFIG_NETDEV_10000=y
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -692,7 +713,7 @@ CONFIG_NETDEV_10000=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_POLLDEV is not set
 
 #
@@ -717,8 +738,9 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_UINPUT is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
@@ -734,16 +756,18 @@ CONFIG_INPUT_MISC=y
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
-CONFIG_BFIN_OTP=y
-# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_TWI_LCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -766,6 +790,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_BFIN_OTP=y
+# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
 
 #
 # CAN, the car bus and industrial fieldbus
@@ -773,44 +799,49 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
 
 #
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8575 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -819,17 +850,15 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -838,11 +867,15 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -850,6 +883,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -870,6 +904,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -878,6 +913,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -885,9 +921,12 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -903,21 +942,29 @@ CONFIG_BFIN_WDT=y
 # CONFIG_USBPCWATCHDOG is not set
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -928,6 +975,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -935,8 +983,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -947,12 +995,18 @@ CONFIG_FB_DEFERRED_IO=y
 # Frame buffer hardware drivers
 #
 CONFIG_FB_BFIN_T350MCQB=y
+# CONFIG_FB_BFIN_LQ035Q1 is not set
 # CONFIG_FB_BFIN_7393 is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=m
 CONFIG_LCD_LTV350QV=m
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=m
 # CONFIG_BACKLIGHT_CORGI is not set
 
@@ -977,15 +1031,8 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 # CONFIG_LOGO_BLACKFIN_VGA16 is not set
 CONFIG_LOGO_BLACKFIN_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -997,62 +1044,38 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# SPI devices
-#
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
-# CONFIG_SND_BLACKFIN_AD1836_TDM is not set
-# CONFIG_SND_BLACKFIN_AD1836_I2S is not set
-# CONFIG_SND_BLACKFIN_AD1836_MULSUB is not set
-# CONFIG_SND_BLACKFIN_AD1836_5P1 is not set
-# CONFIG_SND_BFIN_AD73311 is not set
 # CONFIG_SND_BFIN_AD73322 is not set
-
-#
-# USB devices
-#
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
-CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_SOC=m
-CONFIG_SND_MMAP_SUPPORT=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_BF5XX_I2S=m
+CONFIG_SND_BF5XX_SOC_SSM2602=m
+# CONFIG_SND_BF5XX_SOC_AD73311 is not set
+CONFIG_SND_BF5XX_AC97=m
+CONFIG_SND_BF5XX_MMAP_SUPPORT=y
+# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
+CONFIG_SND_BF5XX_SOC_SPORT=m
 CONFIG_SND_BF5XX_SOC_I2S=m
 CONFIG_SND_BF5XX_SOC_AC97=m
-# CONFIG_SND_BF5XX_SOC_WM8750 is not set
-# CONFIG_SND_BF5XX_SOC_WM8731 is not set
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_SOC_BF5xx=m
+CONFIG_SND_BF5XX_SOC_AD1980=m
 CONFIG_SND_BF5XX_SPORT_NUM=0
 # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
-
-#
-# SoC Audio support for SuperH
-#
-CONFIG_SND_SOC_SSM2602=m
-# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=m
-
-#
-# Open Sound System
-#
+CONFIG_SND_SOC_SSM2602=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
@@ -1064,15 +1087,43 @@ CONFIG_HID=y
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
+# CONFIG_HID_PID is not set
 # CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_THRUSTMASTER_FF=m
+CONFIG_ZEROPLUS_FF=m
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1083,15 +1134,20 @@ CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_SOC=y
 
@@ -1103,13 +1159,15 @@ CONFIG_USB_MUSB_HOST=y
 # CONFIG_USB_MUSB_OTG is not set
 CONFIG_USB_MUSB_HDRC_HCD=y
 CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_LOGLEVEL=0
+# CONFIG_USB_MUSB_DEBUG is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1124,15 +1182,10 @@ CONFIG_USB_MUSB_LOGLEVEL=0
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
-CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1141,7 +1194,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1157,17 +1210,13 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1196,51 +1245,57 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1280,11 +1335,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -1301,8 +1356,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1310,13 +1368,12 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1372,9 +1429,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1382,14 +1436,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1407,10 +1500,95 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_SECURITY_ROOTPLUG is not set
-# CONFIG_CRYPTO is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1418,6 +1596,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index deeb5e45effb..92afd988449b 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +87,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+CONFIG_FREEZER=y
 
 #
 # Blackfin Processor Options
@@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,24 +130,30 @@ CONFIG_BF533=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=6
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 CONFIG_BF_REV_0_3=y
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
 CONFIG_MEM_MT48LC16M16A2TG_75=y
 CONFIG_BFIN533_EZKIT=y
 # CONFIG_BFIN533_STAMP is not set
+# CONFIG_BLACKSTAMP is not set
 # CONFIG_BFIN533_BLUETECHNIX_CM is not set
 # CONFIG_H8606_HVSISTEMAS is not set
 # CONFIG_BFIN532_IP0X is not set
@@ -187,7 +206,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=27000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=750000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -201,6 +219,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
@@ -238,6 +257,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -246,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -268,7 +292,6 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
 # CONFIG_MPU is not set
 
 #
@@ -297,7 +320,6 @@ CONFIG_BANK_3=0xAAC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -308,29 +330,30 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND_UP_POSSIBLE=y
 CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM_BFIN_SLEEP_DEEPER=y
 # CONFIG_PM_BFIN_SLEEP is not set
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
-# CPU Frequency scaling
+# Possible Suspend Mem / Hibernate Wake-Up Sources
 #
-# CONFIG_CPU_FREQ is not set
 
 #
-# Networking
+# CPU Frequency scaling
 #
+# CONFIG_CPU_FREQ is not set
 CONFIG_NET=y
 
 #
@@ -343,6 +366,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -372,8 +396,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -382,6 +404,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -398,6 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -430,24 +454,14 @@ CONFIG_IRTTY_SIR=m
 # CONFIG_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -465,6 +479,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -473,6 +489,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -516,6 +533,7 @@ CONFIG_MTD_ROM=m
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -550,11 +568,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -567,7 +588,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -580,11 +600,14 @@ CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -594,10 +617,10 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -645,8 +668,11 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_BF5xx_PPI is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -675,22 +701,19 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -699,14 +722,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -715,6 +742,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -725,21 +754,28 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -754,18 +790,22 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -784,47 +824,51 @@ CONFIG_RTC_INTF_DEV=y
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -864,11 +908,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -885,8 +929,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -894,13 +941,12 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -956,9 +1002,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -966,14 +1009,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -991,9 +1073,94 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1001,6 +1168,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index c23267ed880b..49eabb41e9e5 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +87,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+CONFIG_FREEZER=y
 
 #
 # Blackfin Processor Options
@@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,24 +130,30 @@ CONFIG_BF533=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=6
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 CONFIG_BF_REV_0_3=y
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
 CONFIG_MEM_MT48LC64M4A2FB_7E=y
 # CONFIG_BFIN533_EZKIT is not set
 CONFIG_BFIN533_STAMP=y
+# CONFIG_BLACKSTAMP is not set
 # CONFIG_BFIN533_BLUETECHNIX_CM is not set
 # CONFIG_H8606_HVSISTEMAS is not set
 # CONFIG_BFIN532_IP0X is not set
@@ -187,7 +206,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=11059200
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=750000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -201,6 +219,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
@@ -238,6 +257,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -246,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -268,7 +292,6 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
 # CONFIG_MPU is not set
 
 #
@@ -297,7 +320,6 @@ CONFIG_BANK_3=0xAAC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -308,29 +330,30 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND_UP_POSSIBLE=y
 CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM_BFIN_SLEEP_DEEPER=y
 # CONFIG_PM_BFIN_SLEEP is not set
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
-# CPU Frequency scaling
+# Possible Suspend Mem / Hibernate Wake-Up Sources
 #
-# CONFIG_CPU_FREQ is not set
 
 #
-# Networking
+# CPU Frequency scaling
 #
+# CONFIG_CPU_FREQ is not set
 CONFIG_NET=y
 
 #
@@ -343,6 +366,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -372,8 +396,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -382,6 +404,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -398,6 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -432,24 +456,14 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -467,6 +481,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -475,6 +491,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -520,6 +537,7 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_PHYSMAP is not set
 CONFIG_MTD_BFIN_ASYNC=m
+# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -554,11 +572,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -571,7 +592,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -584,11 +604,14 @@ CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -598,10 +621,10 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -633,7 +656,7 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_UINPUT is not set
-CONFIG_TWI_KEYPAD=m
+CONFIG_CONFIG_INPUT_PCF8574=m
 
 #
 # Hardware I/O ports
@@ -652,8 +675,11 @@ CONFIG_TWI_KEYPAD=m
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 CONFIG_TWI_LCD=m
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -682,41 +708,46 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-CONFIG_I2C_ALGOBIT=m
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8575 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -725,17 +756,15 @@ CONFIG_I2C_ALGOBIT=m
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -744,11 +773,15 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -756,6 +789,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -776,6 +810,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -784,6 +819,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -791,9 +827,12 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -804,21 +843,29 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -829,6 +876,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=m
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=m
 CONFIG_FB_CFB_COPYAREA=m
 CONFIG_FB_CFB_IMAGEBLIT=m
@@ -836,8 +884,8 @@ CONFIG_FB_CFB_IMAGEBLIT=m
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -848,6 +896,7 @@ CONFIG_FB_DEFERRED_IO=y
 # Frame buffer hardware drivers
 #
 # CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_BFIN_LQ035Q1 is not set
 CONFIG_FB_BFIN_7393=m
 CONFIG_NTSC=y
 # CONFIG_PAL is not set
@@ -859,6 +908,7 @@ CONFIG_ADV7393_1XMEM=y
 # CONFIG_ADV7393_2XMEM is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -866,15 +916,8 @@ CONFIG_ADV7393_1XMEM=y
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -888,18 +931,12 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# SPI devices
-#
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
@@ -911,46 +948,46 @@ CONFIG_SND_BLACKFIN_AD1836_MULSUB=y
 # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set
 CONFIG_SND_BLACKFIN_SPORT=0
 CONFIG_SND_BLACKFIN_SPI_PFBIT=4
-CONFIG_SND_BFIN_AD73311=m
 CONFIG_SND_BFIN_SPORT=0
-CONFIG_SND_BFIN_AD73311_SE=4
 CONFIG_SND_BFIN_AD73322=m
 CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
 CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
 CONFIG_SND_BFIN_AD73322_RESET=12
-
-#
-# System on Chip audio support
-#
-CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_SOC=m
-CONFIG_SND_MMAP_SUPPORT=y
-CONFIG_SND_BF5XX_SOC_AC97=m
-# CONFIG_SND_BF5XX_SOC_WM8750 is not set
-# CONFIG_SND_BF5XX_SOC_WM8731 is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_BF5XX_I2S=m
 # CONFIG_SND_BF5XX_SOC_SSM2602 is not set
-CONFIG_SND_BF5XX_SOC_BF5xx=m
+CONFIG_SND_BF5XX_SOC_AD73311=m
+CONFIG_SND_BFIN_AD73311_SE=4
+CONFIG_SND_BF5XX_AC97=m
+CONFIG_SND_BF5XX_MMAP_SUPPORT=y
+# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
+CONFIG_SND_BF5XX_SOC_SPORT=m
+CONFIG_SND_BF5XX_SOC_I2S=m
+CONFIG_SND_BF5XX_SOC_AC97=m
+CONFIG_SND_BF5XX_SOC_AD1980=m
 CONFIG_SND_BF5XX_SPORT_NUM=0
 # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
-
-#
-# SoC Audio support for SuperH
-#
+# CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=m
-
-#
-# Open Sound System
-#
+CONFIG_SND_SOC_AD73311=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -979,51 +1016,57 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1063,11 +1106,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -1084,8 +1127,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1093,13 +1139,12 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1155,9 +1200,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1165,14 +1207,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1190,9 +1271,94 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1200,6 +1366,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 63a0f854745c..332142f7f9b4 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -1,6 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
+# Tue Dec 30 17:24:37 2008
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +9,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +31,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +49,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +88,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +102,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+CONFIG_FREEZER=y
 
 #
 # Blackfin Processor Options
@@ -105,6 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,18 +131,23 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 CONFIG_BF537=y
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=2
+CONFIG_BF_REV_MAX=3
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 CONFIG_BF_REV_0_2=y
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
@@ -141,27 +160,28 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=8
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_SPI=10
 CONFIG_BFIN537_STAMP=y
 # CONFIG_BFIN537_BLUETECHNIX_CM is not set
+# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
 # CONFIG_PNAV10 is not set
 # CONFIG_CAMSIG_MINOTAUR is not set
 # CONFIG_GENERIC_BF537_BOARD is not set
@@ -194,7 +214,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=25000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -208,6 +227,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
@@ -245,6 +265,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -253,14 +279,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
-# CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
+CONFIG_BFIN_GPTIMERS=m
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -275,7 +300,6 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
 # CONFIG_MPU is not set
 
 #
@@ -304,7 +328,6 @@ CONFIG_BANK_3=0x99B2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -315,29 +338,31 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND_UP_POSSIBLE=y
 CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_PM_BFIN_SLEEP_DEEPER=y
 # CONFIG_PM_BFIN_SLEEP is not set
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
-# CPU Frequency scaling
+# Possible Suspend Mem / Hibernate Wake-Up Sources
 #
-# CONFIG_CPU_FREQ is not set
+# CONFIG_PM_BFIN_WAKE_PH6 is not set
 
 #
-# Networking
+# CPU Frequency scaling
 #
+# CONFIG_CPU_FREQ is not set
 CONFIG_NET=y
 
 #
@@ -350,6 +375,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -379,8 +405,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -389,6 +413,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -405,6 +430,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -440,24 +466,14 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -475,6 +491,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -483,6 +501,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -553,15 +572,11 @@ CONFIG_MTD_NAND=m
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
-CONFIG_MTD_NAND_BFIN=m
-CONFIG_BFIN_NAND_BASE=0x20212000
-CONFIG_BFIN_NAND_CLE=2
-CONFIG_BFIN_NAND_ALE=1
-CONFIG_BFIN_NAND_READY=3
+# CONFIG_MTD_NAND_BFIN is not set
 CONFIG_MTD_NAND_IDS=m
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_PLATFORM=m
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -576,11 +591,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -593,7 +611,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -614,6 +631,7 @@ CONFIG_PHYLIB=y
 CONFIG_SMSC_PHY=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
@@ -626,11 +644,14 @@ CONFIG_BFIN_RX_DESC_NUM=20
 # CONFIG_SMC91X is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -640,10 +661,10 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -675,12 +696,15 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_UINPUT is not set
-CONFIG_TWI_KEYPAD=m
+CONFIG_CONFIG_INPUT_PCF8574=m
 
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -691,11 +715,14 @@ CONFIG_TWI_KEYPAD=m
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
-CONFIG_BFIN_SPORT=y
+CONFIG_BFIN_SPORT=m
 # CONFIG_BFIN_TIMER_LATENCY is not set
 CONFIG_TWI_LCD=m
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -727,48 +754,51 @@ CONFIG_CAN4LINUX=y
 #
 # linux embedded drivers
 #
-# CONFIG_CAN_MCF5282 is not set
-# CONFIG_CAN_UNCTWINCAN is not set
 CONFIG_CAN_BLACKFIN=m
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 CONFIG_SENSORS_AD5252=m
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8575 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -777,17 +807,15 @@ CONFIG_SENSORS_AD5252=m
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -796,11 +824,15 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -808,6 +840,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -828,6 +861,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -836,6 +870,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -843,9 +878,12 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -856,21 +894,29 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -881,6 +927,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=m
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=m
 CONFIG_FB_CFB_COPYAREA=m
 CONFIG_FB_CFB_IMAGEBLIT=m
@@ -888,8 +935,8 @@ CONFIG_FB_CFB_IMAGEBLIT=m
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -899,8 +946,12 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # Frame buffer hardware drivers
 #
-# CONFIG_FB_HITACHI_TX09 is not set
 # CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_BFIN_LQ035Q1 is not set
+CONFIG_FB_BF537_LQ035=m
+CONFIG_LQ035_SLAVE_ADDR=0x58
+# CONFIG_FB_BFIN_LANDSCAPE is not set
+# CONFIG_FB_BFIN_BGR is not set
 CONFIG_FB_BFIN_7393=m
 CONFIG_NTSC=y
 # CONFIG_PAL is not set
@@ -910,15 +961,17 @@ CONFIG_NTSC=y
 # CONFIG_PAL_YCBCR is not set
 CONFIG_ADV7393_1XMEM=y
 # CONFIG_ADV7393_2XMEM is not set
-CONFIG_FB_BF537_LQ035=m
-CONFIG_LQ035_SLAVE_ADDR=0x58
-# CONFIG_FB_BFIN_LANDSCAPE is not set
-# CONFIG_FB_BFIN_BGR is not set
+# CONFIG_FB_HITACHI_TX09 is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=m
 # CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=m
 CONFIG_BACKLIGHT_CORGI=m
 
@@ -927,15 +980,8 @@ CONFIG_BACKLIGHT_CORGI=m
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_LOGO is not set
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -949,18 +995,12 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# SPI devices
-#
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
@@ -972,51 +1012,46 @@ CONFIG_SND_BLACKFIN_AD1836_MULSUB=y
 # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set
 CONFIG_SND_BLACKFIN_SPORT=0
 CONFIG_SND_BLACKFIN_SPI_PFBIT=4
-CONFIG_SND_BFIN_AD73311=m
 CONFIG_SND_BFIN_SPORT=0
-CONFIG_SND_BFIN_AD73311_SE=4
 CONFIG_SND_BFIN_AD73322=m
 CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
 CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
 CONFIG_SND_BFIN_AD73322_RESET=12
-
-#
-# System on Chip audio support
-#
-CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_SOC=m
-CONFIG_SND_MMAP_SUPPORT=y
-CONFIG_SND_BF5XX_SOC_AC97=m
-# CONFIG_SND_BF5XX_SOC_WM8750 is not set
-# CONFIG_SND_BF5XX_SOC_WM8731 is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_BF5XX_I2S=m
 # CONFIG_SND_BF5XX_SOC_SSM2602 is not set
-CONFIG_SND_BF5XX_SOC_BF5xx=m
+CONFIG_SND_BF5XX_SOC_AD73311=m
+CONFIG_SND_BFIN_AD73311_SE=4
+CONFIG_SND_BF5XX_AC97=m
+CONFIG_SND_BF5XX_MMAP_SUPPORT=y
+# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
+CONFIG_SND_BF5XX_SOC_SPORT=m
+CONFIG_SND_BF5XX_SOC_I2S=m
+CONFIG_SND_BF5XX_SOC_AC97=m
+CONFIG_SND_BF5XX_SOC_AD1980=m
 CONFIG_SND_BF5XX_SPORT_NUM=0
 # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
-
-#
-# SoC Audio support for SuperH
-#
+# CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=m
-
-#
-# Open Sound System
-#
+CONFIG_SND_SOC_AD73311=m
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
-# CONFIG_NO_DUMMY_DELAY is not set
-# CONFIG_DUMMY_DELAY_BANK0 is not set
-# CONFIG_DUMMY_DELAY_BANK1 is not set
-# CONFIG_DUMMY_DELAY_BANK2 is not set
-# CONFIG_DUMMY_DELAY_BANK3 is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1045,51 +1080,57 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1129,11 +1170,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -1150,8 +1191,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1159,13 +1203,12 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1221,9 +1264,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1231,14 +1271,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1256,9 +1335,94 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1266,6 +1430,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
new file mode 100644
index 000000000000..ed15934c67c2
--- /dev/null
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -0,0 +1,1368 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc2
+#
+# CONFIG_MMU is not set
+# CONFIG_FPU is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_BLACKFIN=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
+
+#
+# Blackfin Processor Options
+#
+
+#
+# Processor and Board Settings
+#
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
+# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
+# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
+# CONFIG_BF527 is not set
+# CONFIG_BF531 is not set
+# CONFIG_BF532 is not set
+# CONFIG_BF533 is not set
+# CONFIG_BF534 is not set
+# CONFIG_BF536 is not set
+# CONFIG_BF537 is not set
+CONFIG_BF538=y
+# CONFIG_BF539 is not set
+# CONFIG_BF542 is not set
+# CONFIG_BF544 is not set
+# CONFIG_BF547 is not set
+# CONFIG_BF548 is not set
+# CONFIG_BF549 is not set
+# CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=4
+CONFIG_BF_REV_MAX=5
+# CONFIG_BF_REV_0_0 is not set
+# CONFIG_BF_REV_0_1 is not set
+# CONFIG_BF_REV_0_2 is not set
+# CONFIG_BF_REV_0_3 is not set
+CONFIG_BF_REV_0_4=y
+# CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
+# CONFIG_BF_REV_ANY is not set
+# CONFIG_BF_REV_NONE is not set
+CONFIG_MEM_MT48LC32M8A2_75=y
+CONFIG_IRQ_PLL_WAKEUP=7
+CONFIG_IRQ_DMA0_ERROR=7
+CONFIG_IRQ_PPI_ERROR=7
+CONFIG_IRQ_SPORT0_ERROR=7
+CONFIG_IRQ_SPORT1_ERROR=7
+CONFIG_IRQ_UART0_ERROR=7
+CONFIG_IRQ_UART1_ERROR=7
+CONFIG_IRQ_RTC=8
+CONFIG_IRQ_PPI=8
+CONFIG_IRQ_SPORT0_RX=9
+CONFIG_IRQ_SPORT0_TX=9
+CONFIG_IRQ_SPORT1_RX=9
+CONFIG_IRQ_SPORT1_TX=9
+CONFIG_IRQ_SPI0=10
+CONFIG_IRQ_UART0_RX=10
+CONFIG_IRQ_UART0_TX=10
+CONFIG_IRQ_UART1_RX=10
+CONFIG_IRQ_UART1_TX=10
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_PORTF_INTA=12
+CONFIG_IRQ_PORTF_INTB=12
+CONFIG_IRQ_SPI0_ERROR=7
+CONFIG_IRQ_SPI1_ERROR=7
+CONFIG_IRQ_DMA1_ERROR=7
+CONFIG_IRQ_CAN_RX=11
+CONFIG_IRQ_CAN_TX=11
+CONFIG_BFIN538_EZKIT=y
+
+#
+# BF538 Specific Configuration
+#
+
+#
+# Interrupt Priority Assignment
+#
+
+#
+# Priority
+#
+CONFIG_IRQ_MEM0_DMA0=13
+CONFIG_IRQ_MEM0_DMA1=13
+CONFIG_IRQ_SPORT2_ERROR=7
+CONFIG_IRQ_SPORT3_ERROR=7
+CONFIG_IRQ_SPI2_ERROR=7
+CONFIG_IRQ_UART2_ERROR=7
+CONFIG_IRQ_CAN_ERROR=7
+CONFIG_IRQ_SPORT2_RX=9
+CONFIG_IRQ_SPORT2_TX=9
+CONFIG_IRQ_SPORT3_RX=9
+CONFIG_IRQ_SPORT3_TX=9
+CONFIG_IRQ_SPI1=10
+CONFIG_IRQ_SPI2=10
+CONFIG_IRQ_UART2_RX=10
+CONFIG_IRQ_UART2_TX=10
+CONFIG_IRQ_TWI0=11
+CONFIG_IRQ_TWI1=11
+CONFIG_IRQ_MEM1_DMA0=13
+CONFIG_IRQ_MEM1_DMA1=13
+
+#
+# Board customizations
+#
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
+
+#
+# Clock/PLL Setup
+#
+CONFIG_CLKIN_HZ=25000000
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+CONFIG_MAX_VCO_HZ=533333333
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133333333
+CONFIG_MIN_SCLK_HZ=27000000
+
+#
+# Kernel Timer/Scheduler
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# Misc
+#
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+
+#
+# Blackfin Kernel Optimizations
+#
+
+#
+# Memory Optimizations
+#
+CONFIG_I_ENTRY_L1=y
+CONFIG_EXCPT_IRQ_SYSC_L1=y
+CONFIG_DO_IRQ_L1=y
+CONFIG_CORE_TIMER_IRQ_L1=y
+CONFIG_IDLE_L1=y
+CONFIG_SCHEDULE_L1=y
+CONFIG_ARITHMETIC_OPS_L1=y
+CONFIG_ACCESS_OK_L1=y
+CONFIG_MEMSET_L1=y
+CONFIG_MEMCPY_L1=y
+CONFIG_SYS_BFIN_SPINLOCK_L1=y
+# CONFIG_IP_CHECKSUM_L1 is not set
+CONFIG_CACHELINE_ALIGNED_L1=y
+# CONFIG_SYSCALL_TAB_L1 is not set
+# CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
+CONFIG_RAMKERNEL=y
+# CONFIG_ROMKERNEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_VIRT_TO_BUS=y
+CONFIG_BFIN_GPTIMERS=y
+# CONFIG_DMA_UNCACHED_4M is not set
+# CONFIG_DMA_UNCACHED_2M is not set
+CONFIG_DMA_UNCACHED_1M=y
+# CONFIG_DMA_UNCACHED_NONE is not set
+
+#
+# Cache Support
+#
+CONFIG_BFIN_ICACHE=y
+CONFIG_BFIN_DCACHE=y
+# CONFIG_BFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
+# CONFIG_BFIN_WB is not set
+CONFIG_BFIN_WT=y
+# CONFIG_MPU is not set
+
+#
+# Asynchonous Memory Configuration
+#
+
+#
+# EBIU_AMGCTL Global Control
+#
+CONFIG_C_AMCKEN=y
+CONFIG_C_CDPRIO=y
+# CONFIG_C_AMBEN is not set
+# CONFIG_C_AMBEN_B0 is not set
+# CONFIG_C_AMBEN_B0_B1 is not set
+# CONFIG_C_AMBEN_B0_B1_B2 is not set
+CONFIG_C_AMBEN_ALL=y
+
+#
+# EBIU_AMBCTL Control
+#
+CONFIG_BANK_0=0x7BB0
+CONFIG_BANK_1=0x7BB0
+CONFIG_BANK_2=0x7BB0
+CONFIG_BANK_3=0x99B2
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF_FDPIC=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM_WAKEUP_BY_GPIO is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+CONFIG_BFIN_SIR=m
+CONFIG_SIR_BFIN_DMA=y
+# CONFIG_SIR_BFIN_PIO is not set
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=m
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=m
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x20000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_UCLINUX is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_BFIN=m
+CONFIG_BFIN_NAND_BASE=0x20212000
+CONFIG_BFIN_NAND_CLE=2
+CONFIG_BFIN_NAND_ALE=1
+CONFIG_BFIN_NAND_READY=3
+CONFIG_MTD_NAND_IDS=m
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_SMC91X=y
+# CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+CONFIG_TOUCHSCREEN_AD7879_SPI=y
+CONFIG_TOUCHSCREEN_AD7879=m
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_AD9960 is not set
+# CONFIG_SPI_ADC_BF533 is not set
+# CONFIG_BF5xx_PPIFCD is not set
+# CONFIG_BFIN_SIMPLE_TIMER is not set
+# CONFIG_BF5xx_PPI is not set
+CONFIG_BFIN_SPORT=y
+# CONFIG_BFIN_TIMER_LATENCY is not set
+# CONFIG_TWI_LCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+CONFIG_SIMPLE_GPIO=m
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_DMA=y
+# CONFIG_SERIAL_BFIN_PIO is not set
+CONFIG_SERIAL_BFIN_UART0=y
+# CONFIG_BFIN_UART0_CTSRTS is not set
+CONFIG_SERIAL_BFIN_UART1=y
+# CONFIG_BFIN_UART1_CTSRTS is not set
+CONFIG_SERIAL_BFIN_UART2=y
+# CONFIG_BFIN_UART2_CTSRTS is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_BFIN_SPORT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# CAN, the car bus and industrial fieldbus
+#
+# CONFIG_CAN4LINUX is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_AD5252 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_BFIN_WDT=y
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=m
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_BFIN_T350MCQB is not set
+CONFIG_FB_BFIN_LQ035Q1=m
+# CONFIG_FB_BFIN_7393 is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_BFIN=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=m
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
+CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
+CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
+# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_ACCESS_CHECK=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index bf63660815b9..d4ed9ce1f62f 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +87,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,18 +130,23 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 CONFIG_BF548=y
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=0
+CONFIG_BF_REV_MAX=2
 CONFIG_BF_REV_0_0=y
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF54x=y
@@ -138,15 +156,12 @@ CONFIG_IRQ_SPORT0_RX=9
 CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
+CONFIG_IRQ_SPI0=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_CNT=8
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
 CONFIG_IRQ_TIMER0=11
 CONFIG_IRQ_TIMER1=11
 CONFIG_IRQ_TIMER2=11
@@ -155,9 +170,21 @@ CONFIG_IRQ_TIMER4=11
 CONFIG_IRQ_TIMER5=11
 CONFIG_IRQ_TIMER6=11
 CONFIG_IRQ_TIMER7=11
+CONFIG_IRQ_USB_INT0=11
+CONFIG_IRQ_USB_INT1=11
+CONFIG_IRQ_USB_INT2=11
+CONFIG_IRQ_USB_DMA=11
 CONFIG_IRQ_TIMER8=11
 CONFIG_IRQ_TIMER9=11
 CONFIG_IRQ_TIMER10=11
+CONFIG_IRQ_SPORT2_RX=9
+CONFIG_IRQ_SPORT2_TX=9
+CONFIG_IRQ_SPORT3_RX=9
+CONFIG_IRQ_SPORT3_TX=9
+CONFIG_IRQ_SPI1=10
+CONFIG_IRQ_SPI2=10
+CONFIG_IRQ_TWI0=11
+CONFIG_IRQ_TWI1=11
 CONFIG_BFIN548_EZKIT=y
 # CONFIG_BFIN548_BLUETECHNIX_CM is not set
 
@@ -180,7 +207,6 @@ CONFIG_IRQ_SPORT1_ERR=7
 CONFIG_IRQ_SPI0_ERR=7
 CONFIG_IRQ_UART0_ERR=7
 CONFIG_IRQ_EPPI0=8
-CONFIG_IRQ_SPI0=10
 CONFIG_IRQ_PINT0=12
 CONFIG_IRQ_PINT1=12
 CONFIG_IRQ_MDMAS0=13
@@ -195,18 +221,10 @@ CONFIG_IRQ_SPI2_ERR=7
 CONFIG_IRQ_UART1_ERR=7
 CONFIG_IRQ_UART2_ERR=7
 CONFIG_IRQ_CAN0_ERR=7
-CONFIG_IRQ_SPORT2_RX=9
-CONFIG_IRQ_SPORT2_TX=9
-CONFIG_IRQ_SPORT3_RX=9
-CONFIG_IRQ_SPORT3_TX=9
 CONFIG_IRQ_EPPI1=9
 CONFIG_IRQ_EPPI2=9
-CONFIG_IRQ_SPI1=10
-CONFIG_IRQ_SPI2=10
 CONFIG_IRQ_ATAPI_RX=10
 CONFIG_IRQ_ATAPI_TX=10
-CONFIG_IRQ_TWI0=11
-CONFIG_IRQ_TWI1=11
 CONFIG_IRQ_CAN0_RX=11
 CONFIG_IRQ_CAN0_TX=11
 CONFIG_IRQ_MDMAS2=13
@@ -260,7 +278,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=25000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -274,10 +291,10 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -311,6 +328,12 @@ CONFIG_ACCESS_OK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -319,14 +342,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 CONFIG_DMA_UNCACHED_2M=y
 # CONFIG_DMA_UNCACHED_1M is not set
@@ -341,7 +363,7 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
+# CONFIG_BFIN_L2_CACHEABLE is not set
 # CONFIG_MPU is not set
 
 #
@@ -373,7 +395,6 @@ CONFIG_EBIU_FCTLVAL=0x6
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -384,23 +405,20 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -413,6 +431,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -442,8 +461,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -452,6 +469,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -468,6 +486,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -493,9 +512,9 @@ CONFIG_IRCOMM=m
 #
 CONFIG_IRTTY_SIR=m
 CONFIG_BFIN_SIR=m
+CONFIG_BFIN_SIR3=y
 # CONFIG_BFIN_SIR0 is not set
 # CONFIG_BFIN_SIR2 is not set
-CONFIG_BFIN_SIR3=y
 CONFIG_SIR_BFIN_DMA=y
 # CONFIG_SIR_BFIN_PIO is not set
 
@@ -508,15 +527,6 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_KS959_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_USB_IRDA is not set
@@ -524,11 +534,10 @@ CONFIG_SIR_BFIN_DMA=y
 # CONFIG_MCS_FIR is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -546,6 +555,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -554,6 +565,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -601,6 +613,7 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_START=0x20000000
 CONFIG_MTD_PHYSMAP_LEN=0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 
@@ -608,7 +621,8 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -648,11 +662,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -696,13 +713,16 @@ CONFIG_SCSI_WAIT_SCAN=m
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
 # CONFIG_PATA_PLATFORM is not set
 CONFIG_PATA_BF54X=y
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -715,11 +735,14 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 CONFIG_SMSC911X=y
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -729,6 +752,7 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # USB Network Adapters
@@ -741,7 +765,6 @@ CONFIG_NETDEV_10000=y
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -752,7 +775,7 @@ CONFIG_NETDEV_10000=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_POLLDEV is not set
 
 #
@@ -776,30 +799,37 @@ CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_GPIO is not set
 CONFIG_KEYBOARD_BFIN=y
 # CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_ADP5588 is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
 CONFIG_TOUCHSCREEN_AD7877=m
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
 # CONFIG_INPUT_ATI_REMOTE2 is not set
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 # CONFIG_INPUT_UINPUT is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
@@ -815,16 +845,18 @@ CONFIG_INPUT_MISC=y
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
-CONFIG_BFIN_OTP=y
-# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_TWI_LCD is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -849,6 +881,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_BFIN_SPORT is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_BFIN_OTP=y
+# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
 
 #
 # CAN, the car bus and industrial fieldbus
@@ -856,44 +890,49 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
 # CONFIG_I2C_TINY_USB is not set
 
 #
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8575 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -902,17 +941,15 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -921,11 +958,15 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -933,6 +974,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
@@ -953,6 +995,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
@@ -961,6 +1004,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
@@ -968,9 +1012,12 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -986,23 +1033,30 @@ CONFIG_BFIN_WDT=y
 # CONFIG_USBPCWATCHDOG is not set
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
-# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
@@ -1012,6 +1066,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -1019,8 +1074,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -1032,9 +1087,11 @@ CONFIG_FB_DEFERRED_IO=y
 #
 CONFIG_FB_BF54X_LQ043=y
 # CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_BFIN_LQ035Q1 is not set
 # CONFIG_FB_BFIN_7393 is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -1066,15 +1123,8 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 # CONFIG_LOGO_BLACKFIN_VGA16 is not set
 CONFIG_LOGO_BLACKFIN_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
@@ -1088,56 +1138,35 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# SPI devices
-#
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
-# CONFIG_SND_BFIN_AD73311 is not set
 # CONFIG_SND_BFIN_AD73322 is not set
-
-#
-# USB devices
-#
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
-CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_SOC=y
-CONFIG_SND_MMAP_SUPPORT=y
+CONFIG_SND_SOC_AC97_BUS=y
+# CONFIG_SND_BF5XX_I2S is not set
+CONFIG_SND_BF5XX_AC97=y
+CONFIG_SND_BF5XX_MMAP_SUPPORT=y
+# CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set
+CONFIG_SND_BF5XX_SOC_SPORT=y
 CONFIG_SND_BF5XX_SOC_AC97=y
-CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y
-# CONFIG_SND_BF5XX_SOC_WM8750 is not set
-# CONFIG_SND_BF5XX_SOC_WM8731 is not set
-# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
+CONFIG_SND_BF5XX_SOC_AD1980=y
 CONFIG_SND_BF5XX_SPORT_NUM=0
 CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
 CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
-
-#
-# SoC Audio support for SuperH
-#
+# CONFIG_SND_SOC_ALL_CODECS is not set
 CONFIG_SND_SOC_AD1980=y
-
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
 CONFIG_HID_SUPPORT=y
@@ -1149,15 +1178,43 @@ CONFIG_HID=y
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
+# CONFIG_HID_PID is not set
 # CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_THRUSTMASTER_FF=m
+CONFIG_ZEROPLUS_FF=m
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
@@ -1168,15 +1225,20 @@ CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_SOC=y
 
@@ -1190,13 +1252,15 @@ CONFIG_USB_MUSB_HDRC_HCD=y
 # CONFIG_MUSB_PIO_ONLY is not set
 CONFIG_USB_INVENTRA_DMA=y
 # CONFIG_USB_TI_CPPI_DMA is not set
-CONFIG_USB_MUSB_LOGLEVEL=0
+# CONFIG_USB_MUSB_DEBUG is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1218,6 +1282,7 @@ CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 
 #
@@ -1225,15 +1290,10 @@ CONFIG_USB_STORAGE=m
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1242,7 +1302,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1258,34 +1318,31 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
 CONFIG_SDH_BFIN=m
 # CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set
 # CONFIG_MMC_SPI is not set
-# CONFIG_SPI_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1314,32 +1371,40 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -1352,22 +1417,20 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
 # CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1414,11 +1477,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -1435,8 +1498,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -1444,18 +1510,16 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1533,9 +1597,6 @@ CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -1543,14 +1604,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1568,10 +1668,95 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_SECURITY_ROOTPLUG is not set
-# CONFIG_CRYPTO is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1579,6 +1764,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 3c70d6230a12..1ecb7a38c905 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -81,6 +87,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -117,24 +130,38 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 # CONFIG_BF537 is not set
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 CONFIG_BF561=y
+# CONFIG_SMP is not set
+CONFIG_BF_REV_MIN=3
+CONFIG_BF_REV_MAX=5
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 # CONFIG_BF_REV_0_2 is not set
 CONFIG_BF_REV_0_3=y
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_MEM_MT48LC16M16A2TG_75=y
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_SPORT0_ERROR=7
 CONFIG_IRQ_SPORT1_ERROR=7
+CONFIG_IRQ_TIMER0=10
+CONFIG_IRQ_TIMER1=10
+CONFIG_IRQ_TIMER2=10
+CONFIG_IRQ_TIMER3=10
+CONFIG_IRQ_TIMER4=10
+CONFIG_IRQ_TIMER5=10
+CONFIG_IRQ_TIMER6=10
+CONFIG_IRQ_TIMER7=10
 CONFIG_IRQ_SPI_ERROR=7
 CONFIG_BFIN561_EZKIT=y
 # CONFIG_BFIN561_TEPLA is not set
@@ -148,10 +175,6 @@ CONFIG_BFIN561_EZKIT=y
 #
 # Core B Support
 #
-
-#
-# Core B Support
-#
 CONFIG_BF561_COREB=y
 CONFIG_BF561_COREB_RESET=y
 
@@ -193,14 +216,6 @@ CONFIG_IRQ_DMA2_8=9
 CONFIG_IRQ_DMA2_9=9
 CONFIG_IRQ_DMA2_10=9
 CONFIG_IRQ_DMA2_11=9
-CONFIG_IRQ_TIMER0=10
-CONFIG_IRQ_TIMER1=10
-CONFIG_IRQ_TIMER2=10
-CONFIG_IRQ_TIMER3=10
-CONFIG_IRQ_TIMER4=10
-CONFIG_IRQ_TIMER5=10
-CONFIG_IRQ_TIMER6=10
-CONFIG_IRQ_TIMER7=10
 CONFIG_IRQ_TIMER8=10
 CONFIG_IRQ_TIMER9=10
 CONFIG_IRQ_TIMER10=10
@@ -230,7 +245,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=30000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=512
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -244,6 +258,7 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
@@ -281,6 +296,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
 # CONFIG_CPLB_SWITCH_TAB_L1 is not set
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -289,14 +310,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -311,7 +331,7 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 # CONFIG_BFIN_WB is not set
 CONFIG_BFIN_WT=y
-CONFIG_L1_MAX_PIECE=16
+# CONFIG_BFIN_L2_CACHEABLE is not set
 # CONFIG_MPU is not set
 
 #
@@ -344,7 +364,6 @@ CONFIG_BANK_3=0xAAC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
@@ -355,23 +374,20 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -384,6 +400,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -413,8 +430,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -423,6 +438,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -439,6 +455,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
@@ -471,24 +488,14 @@ CONFIG_IRTTY_SIR=m
 # CONFIG_DONGLE is not set
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
@@ -506,6 +513,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -514,6 +523,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -595,11 +605,14 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -612,7 +625,6 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -625,11 +637,14 @@ CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_AX88180 is not set
 CONFIG_NETDEV_10000=y
@@ -639,10 +654,10 @@ CONFIG_NETDEV_10000=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -690,8 +705,11 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_BF5xx_PPI is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -720,22 +738,19 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -744,14 +759,18 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -760,6 +779,8 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -770,21 +791,28 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -799,43 +827,43 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
 # CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -875,11 +903,11 @@ CONFIG_SYSFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=m
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
@@ -896,8 +924,11 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -905,13 +936,12 @@ CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -967,9 +997,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
@@ -977,14 +1004,53 @@ CONFIG_INSTRUMENTATION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_HWERR is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -994,7 +1060,6 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
 CONFIG_EARLY_PRINTK=y
-# CONFIG_DUAL_CORE_TEST_MODULE is not set
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
 
@@ -1003,9 +1068,94 @@ CONFIG_ACCESS_CHECK=y
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1013,6 +1163,7 @@ CONFIG_SECURITY=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 2921f9952d5f..9683b2e13097 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -53,7 +53,7 @@ CONFIG_KALLSYMS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
@@ -276,7 +276,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_BFIN_GPTIMERS=y
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index b6a14635fb91..a041e7eba770 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FAIR_USER_SCHED=y
 # CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
@@ -56,7 +56,7 @@ CONFIG_KALLSYMS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -190,14 +190,14 @@ CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_PORTH_INTA=11
 CONFIG_IRQ_MAC_TX=11
 CONFIG_IRQ_PORTH_INTB=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTA=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
@@ -292,7 +292,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_BFIN_GPTIMERS=y
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -650,6 +649,7 @@ CONFIG_BFIN_OTP=y
 # CONFIG_TWI_LCD is not set
 CONFIG_SIMPLE_GPIO=m
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -699,7 +699,7 @@ CONFIG_I2C_CHARDEV=m
 # I2C Hardware Bus support
 #
 CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index c3ba9066b935..085211b9e4e4 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -254,7 +254,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -598,6 +597,7 @@ CONFIG_NETDEV_10000=y
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index cdc6b7feb59e..750203e27a46 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
@@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -627,6 +626,7 @@ CONFIG_NETDEV_10000=y
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index f074bdcd1ce5..dec8a7d5cc0e 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
@@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -607,6 +606,7 @@ CONFIG_NETDEV_10000=y
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index 5c44fdb8e6e3..efd68bc78f35 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -41,7 +41,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FAIR_USER_SCHED=y
 # CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -325,7 +325,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -544,7 +543,7 @@ CONFIG_MTD_RAM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_START=0x20000000
-CONFIG_MTD_PHYSMAP_LEN=0x800000
+CONFIG_MTD_PHYSMAP_LEN=0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -732,6 +731,7 @@ CONFIG_BFIN_OTP=y
 # CONFIG_TWI_LCD is not set
 # CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -782,7 +782,7 @@ CONFIG_I2C_CHARDEV=y
 # I2C Hardware Bus support
 #
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index 086fe5dda495..346bc7af8f42 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FAIR_USER_SCHED=y
 # CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_SYSFS_DEPRECATED is not set
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -300,7 +300,6 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 CONFIG_LARGE_ALLOCS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -612,6 +611,7 @@ CONFIG_NETDEV_10000=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 # CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index 1fc31f1b762b..5d3901d23fd1 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -54,7 +54,7 @@ CONFIG_KALLSYMS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -250,7 +250,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 CONFIG_BFIN_GPTIMERS=y
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index 285d2241df26..e66f5daaa828 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index bffca7de65d4..ce5dde9de9db 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.28-rc2
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -8,41 +8,37 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -54,40 +50,41 @@ CONFIG_KALLSYMS=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=9
-# CONFIG_NP2 is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -101,9 +98,11 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -112,8 +111,15 @@ CONFIG_PREEMPT_VOLUNTARY=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
 # CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
 # CONFIG_BF527 is not set
 # CONFIG_BF531 is not set
 # CONFIG_BF532 is not set
@@ -121,22 +127,26 @@ CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 CONFIG_BF537=y
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=2
+CONFIG_BF_REV_MAX=3
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 CONFIG_BF_REV_0_2=y
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
-CONFIG_BFIN_SINGLE_CORE=y
 CONFIG_MEM_MT48LC32M8A2_75=y
 CONFIG_IRQ_PLL_WAKEUP=7
 CONFIG_IRQ_RTC=8
@@ -146,28 +156,30 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
 # CONFIG_BFIN537_BLUETECHNIX_CM is not set
+# CONFIG_BFIN537_BLUETECHNIX_TCM is not set
 CONFIG_PNAV10=y
+# CONFIG_CAMSIG_MINOTAUR is not set
 # CONFIG_GENERIC_BF537_BOARD is not set
 
 #
@@ -191,6 +203,7 @@ CONFIG_IRQ_PROG_INTA=12
 # Board customizations
 #
 # CONFIG_CMDLINE_BOOL is not set
+CONFIG_BOOT_LOAD=0x1000
 
 #
 # Clock/PLL Setup
@@ -199,7 +212,7 @@ CONFIG_CLKIN_HZ=24576000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
 CONFIG_MIN_SCLK_HZ=27000000
 
 #
@@ -210,13 +223,17 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 
 #
-# Memory Setup
+# Misc
 #
-CONFIG_MAX_MEM_SIZE=64
-CONFIG_MEM_ADD_WIDTH=10
-CONFIG_BOOT_LOAD=0x1000
 CONFIG_BFIN_SCRATCH_REG_RETN=y
 # CONFIG_BFIN_SCRATCH_REG_RETE is not set
 # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
@@ -243,6 +260,12 @@ CONFIG_IP_CHECKSUM_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -251,13 +274,14 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
-CONFIG_LARGE_ALLOCS=y
-# CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_BFIN_GPTIMERS=y
+# CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -271,7 +295,7 @@ CONFIG_BFIN_DCACHE=y
 # CONFIG_BFIN_ICACHE_LOCK is not set
 CONFIG_BFIN_WB=y
 # CONFIG_BFIN_WT is not set
-CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
 
 #
 # Asynchonous Memory Configuration
@@ -299,12 +323,7 @@ CONFIG_BANK_3=0x99B2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 
 #
@@ -314,21 +333,20 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 # CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -341,6 +359,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -362,6 +381,7 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -369,8 +389,6 @@ CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
@@ -379,6 +397,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -388,10 +407,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -399,18 +414,19 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
 # CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -419,14 +435,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
@@ -434,6 +447,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -446,6 +460,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -470,7 +485,7 @@ CONFIG_MTD_RAM=y
 # Mapping drivers for chip access
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_BF5xx is not set
+# CONFIG_MTD_GPIO_ADDR is not set
 CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_PLATRAM is not set
 
@@ -509,33 +524,22 @@ CONFIG_MTD_NAND_IDS=y
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -543,22 +547,17 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
 #
@@ -572,46 +571,45 @@ CONFIG_PHYLIB=y
 # CONFIG_VITESSE_PHY is not set
 # CONFIG_SMSC_PHY is not set
 # CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-# CONFIG_SMC91X is not set
 CONFIG_BFIN_MAC=y
 # CONFIG_BFIN_MAC_USE_L1 is not set
 CONFIG_BFIN_TX_DESC_NUM=100
 CONFIG_BFIN_RX_DESC_NUM=100
 CONFIG_BFIN_MAC_RMII=y
+# CONFIG_SMC91X is not set
 # CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
 # CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
 
 #
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -626,9 +624,6 @@ CONFIG_INPUT=y
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -642,24 +637,29 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
 CONFIG_TOUCHSCREEN_AD7877=y
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_ATI_REMOTE is not set
 # CONFIG_INPUT_ATI_REMOTE2 is not set
 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
 CONFIG_INPUT_UINPUT=y
-# CONFIG_BF53X_PFBUTTONS is not set
-# CONFIG_TWI_KEYPAD is not set
+# CONFIG_CONFIG_INPUT_PCF8574 is not set
 
 #
 # Hardware I/O ports
@@ -672,18 +672,17 @@ CONFIG_INPUT_UINPUT=y
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BFIN_SIMPLE_TIMER is not set
 # CONFIG_BF5xx_PPI is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
 CONFIG_TWI_LCD=m
-CONFIG_TWI_LCD_SLAVE_ADDR=34
-# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_TEA5764 is not set
-# CONFIG_BF5xx_FBDMA is not set
+CONFIG_BFIN_DMA_INTERFACE=m
+# CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -716,68 +715,59 @@ CONFIG_CAN4LINUX=y
 #
 # linux embedded drivers
 #
-# CONFIG_CAN_MCF5282 is not set
-# CONFIG_CAN_UNCTWINCAN is not set
 CONFIG_CAN_BLACKFIN=m
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 
 #
-# I2C Algorithms
+# I2C Hardware Bus support
 #
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Bus support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_I2C_BLACKFIN_GPIO is not set
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_AD5252 is not set
 # CONFIG_SENSORS_EEPROM is not set
 CONFIG_SENSORS_PCF8574=m
-CONFIG_SENSORS_PCF8575=y
-# CONFIG_SENSORS_PCA9543 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 
@@ -785,6 +775,7 @@ CONFIG_SPI_MASTER=y
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -792,27 +783,29 @@ CONFIG_SPI_BFIN=y
 #
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7414 is not set
 # CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
 # CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -827,58 +820,76 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Graphics support
+# Multimedia drivers
 #
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_DAB=y
 
 #
-# Display device support
+# Graphics support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
 # CONFIG_FB_SYS_FILLRECT is not set
 # CONFIG_FB_SYS_COPYAREA is not set
 # CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -888,25 +899,34 @@ CONFIG_FB_DEFERRED_IO=y
 #
 # Frame buffer hardware drivers
 #
-# CONFIG_FB_BFIN_7171 is not set
-# CONFIG_FB_BFIN_7393 is not set
+# CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_BFIN_LQ035Q1 is not set
 CONFIG_FB_BF537_LQ035=y
 CONFIG_LQ035_SLAVE_ADDR=0x58
 CONFIG_FB_BFIN_LANDSCAPE=y
 # CONFIG_FB_BFIN_BGR is not set
-# CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_BFIN_7393 is not set
+# CONFIG_FB_HITACHI_TX09 is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
-# CONFIG_LOGO is not set
+# CONFIG_FB_METRONOME is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
 
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_LOGO is not set
 CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
+CONFIG_SOUND_OSS_CORE=y
 CONFIG_SND=m
 # CONFIG_SND_SEQUENCER is not set
 # CONFIG_SND_MIXER_OSS is not set
@@ -916,46 +936,30 @@ CONFIG_SND=m
 # CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
+CONFIG_SND_SPI=y
 
 #
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
-# CONFIG_SND_BFIN_AD73311 is not set
-
-#
-# System on Chip audio support
-#
+# CONFIG_SND_BFIN_AD73322 is not set
 # CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
 CONFIG_SOUND_PRIME=y
-# CONFIG_OSS_OBSOLETE is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-
-#
-# HID Devices
-#
+CONFIG_HID_SUPPORT=y
 # CONFIG_HID is not set
-
-#
-# USB support
-#
+# CONFIG_HID_PID is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB_ARCH_HAS_OHCI is not set
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 # CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
 # Enable Host or Gadget support to see Inventra options
@@ -964,37 +968,11 @@ CONFIG_USB_ARCH_HAS_HCD=y
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1014,6 +992,7 @@ CONFIG_RTC_INTF_DEV=y
 # I2C RTC drivers
 #
 # CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
 # CONFIG_RTC_DRV_MAX6900 is not set
 # CONFIG_RTC_DRV_RS5C372 is not set
@@ -1021,43 +1000,41 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
 #
-# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
 
 #
 # Platform RTC drivers
 #
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_BFIN=y
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# PBX support
-#
-# CONFIG_PBX is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -1067,20 +1044,18 @@ CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT2_FS_POSIX_ACL is not set
 # CONFIG_EXT2_FS_SECURITY is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -1106,7 +1081,6 @@ CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1121,36 +1095,35 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_YAFFS_FS=y
 CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
 # CONFIG_YAFFS_DOES_ECC is not set
 CONFIG_YAFFS_YAFFS2=y
 CONFIG_YAFFS_AUTO_YAFFS2=y
 # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
-CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
 # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
 # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
 CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1159,17 +1132,12 @@ CONFIG_SMB_FS=m
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=m
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
@@ -1210,29 +1178,30 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
 # CONFIG_DEBUG_MMRS is not set
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 # CONFIG_DEBUG_HUNT_FOR_ZERO is not set
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -1250,13 +1219,94 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
 #
 # CONFIG_KEYS is not set
 CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
 
 #
-# Cryptographic options
+# Random Number Generation
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
@@ -1264,8 +1314,10 @@ CONFIG_SECURITY_CAPABILITIES=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index b1309f878fcd..7c8250d6fa66 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -59,7 +59,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
@@ -172,14 +172,14 @@ CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
@@ -271,7 +271,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_LARGE_ALLOCS=y
-CONFIG_BFIN_DMA_5XX=y
 CONFIG_DMA_UNCACHED_2M=y
 # CONFIG_DMA_UNCACHED_1M is not set
 # CONFIG_DMA_UNCACHED_NONE is not set
@@ -786,7 +785,7 @@ CONFIG_I2C_CHARDEV=y
 #
 # CONFIG_I2C_BLACKFIN_GPIO is not set
 CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 # CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index c482ee171f9e..9af522c7dadf 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24.7
-# Thu Jul 31 00:53:15 2008
+# Linux kernel version: 2.6.28-rc2
+# Tue Jan  6 09:22:17 2009
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -9,7 +9,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 CONFIG_BLACKFIN=y
 CONFIG_ZONE_DMA=y
-CONFIG_SEMAPHORE_SLEEPERS=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -30,17 +29,14 @@ CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
@@ -52,22 +48,30 @@ CONFIG_KALLSYMS=y
 # CONFIG_HOTPLUG is not set
 CONFIG_PRINTK=y
 CONFIG_BUG=y
-CONFIG_ELF_CORE=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -78,6 +82,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -91,9 +96,11 @@ CONFIG_IOSCHED_CFQ=y
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_FREEZER is not set
 
 #
 # Blackfin Processor Options
@@ -102,6 +109,10 @@ CONFIG_PREEMPT_NONE=y
 #
 # Processor and Board Settings
 #
+# CONFIG_BF512 is not set
+# CONFIG_BF514 is not set
+# CONFIG_BF516 is not set
+# CONFIG_BF518 is not set
 # CONFIG_BF522 is not set
 # CONFIG_BF523 is not set
 # CONFIG_BF524 is not set
@@ -114,18 +125,23 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_BF534 is not set
 # CONFIG_BF536 is not set
 CONFIG_BF537=y
+# CONFIG_BF538 is not set
+# CONFIG_BF539 is not set
 # CONFIG_BF542 is not set
 # CONFIG_BF544 is not set
 # CONFIG_BF547 is not set
 # CONFIG_BF548 is not set
 # CONFIG_BF549 is not set
 # CONFIG_BF561 is not set
+CONFIG_BF_REV_MIN=2
+CONFIG_BF_REV_MAX=3
 # CONFIG_BF_REV_0_0 is not set
 # CONFIG_BF_REV_0_1 is not set
 CONFIG_BF_REV_0_2=y
 # CONFIG_BF_REV_0_3 is not set
 # CONFIG_BF_REV_0_4 is not set
 # CONFIG_BF_REV_0_5 is not set
+# CONFIG_BF_REV_0_6 is not set
 # CONFIG_BF_REV_ANY is not set
 # CONFIG_BF_REV_NONE is not set
 CONFIG_BF53x=y
@@ -137,25 +153,25 @@ CONFIG_IRQ_SPORT0_TX=9
 CONFIG_IRQ_SPORT1_RX=9
 CONFIG_IRQ_SPORT1_TX=9
 CONFIG_IRQ_TWI=10
-CONFIG_IRQ_SPI=10
 CONFIG_IRQ_UART0_RX=10
 CONFIG_IRQ_UART0_TX=10
 CONFIG_IRQ_UART1_RX=10
 CONFIG_IRQ_UART1_TX=10
 CONFIG_IRQ_MAC_RX=11
 CONFIG_IRQ_MAC_TX=11
-CONFIG_IRQ_TMR0=12
-CONFIG_IRQ_TMR1=12
-CONFIG_IRQ_TMR2=12
-CONFIG_IRQ_TMR3=12
-CONFIG_IRQ_TMR4=12
-CONFIG_IRQ_TMR5=12
-CONFIG_IRQ_TMR6=12
-CONFIG_IRQ_TMR7=12
+CONFIG_IRQ_TIMER0=12
+CONFIG_IRQ_TIMER1=12
+CONFIG_IRQ_TIMER2=12
+CONFIG_IRQ_TIMER3=12
+CONFIG_IRQ_TIMER4=12
+CONFIG_IRQ_TIMER5=12
+CONFIG_IRQ_TIMER6=12
+CONFIG_IRQ_TIMER7=12
 CONFIG_IRQ_PORTG_INTB=12
 CONFIG_IRQ_MEM_DMA0=13
 CONFIG_IRQ_MEM_DMA1=13
 CONFIG_IRQ_WATCH=13
+CONFIG_IRQ_SPI=10
 # CONFIG_BFIN537_STAMP is not set
 # CONFIG_BFIN537_BLUETECHNIX_CM is not set
 CONFIG_BFIN537_BLUETECHNIX_TCM=y
@@ -191,7 +207,6 @@ CONFIG_BOOT_LOAD=0x1000
 #
 CONFIG_CLKIN_HZ=25000000
 # CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_MEM_SIZE=32
 CONFIG_MAX_VCO_HZ=600000000
 CONFIG_MIN_VCO_HZ=50000000
 CONFIG_MAX_SCLK_HZ=133333333
@@ -205,10 +220,10 @@ CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 # CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_TICK_ONESHOT is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -242,6 +257,12 @@ CONFIG_IP_CHECKSUM_L1=y
 CONFIG_CACHELINE_ALIGNED_L1=y
 CONFIG_SYSCALL_TAB_L1=y
 CONFIG_CPLB_SWITCH_TAB_L1=y
+CONFIG_APP_STACK_L1=y
+
+#
+# Speed Optimizations
+#
+CONFIG_BFIN_INS_LOWOVERHEAD=y
 CONFIG_RAMKERNEL=y
 # CONFIG_ROMKERNEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
@@ -250,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_BFIN_GPTIMERS is not set
-CONFIG_BFIN_DMA_5XX=y
 # CONFIG_DMA_UNCACHED_4M is not set
 # CONFIG_DMA_UNCACHED_2M is not set
 CONFIG_DMA_UNCACHED_1M=y
@@ -300,7 +320,6 @@ CONFIG_BANK_3=0xFFC2
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
-# CONFIG_PCI is not set
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
@@ -310,23 +329,20 @@ CONFIG_BINFMT_ELF_FDPIC=y
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 
 #
 # Power management options
 #
 # CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM_WAKEUP_BY_GPIO is not set
 
 #
 # CPU Frequency scaling
 #
 # CONFIG_CPU_FREQ is not set
-
-#
-# Networking
-#
 # CONFIG_NET is not set
 
 #
@@ -345,6 +361,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -362,8 +379,10 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -374,6 +393,10 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
@@ -381,8 +404,9 @@ CONFIG_MTD_RAM=y
 #
 # Mapping drivers for chip access
 #
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_GPIO_ADDR is not set
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_GPIO_ADDR=y
 CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_PLATRAM is not set
 
@@ -416,10 +440,13 @@ CONFIG_BLK_DEV=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -454,8 +481,11 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_BF5xx_PPI is not set
 CONFIG_BFIN_SPORT=y
 # CONFIG_BFIN_TIMER_LATENCY is not set
+CONFIG_BFIN_DMA_INTERFACE=m
 # CONFIG_SIMPLE_GPIO is not set
 # CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_BFIN_JTAG_COMM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -486,15 +516,10 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_CAN4LINUX is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 
@@ -502,6 +527,7 @@ CONFIG_SPI_MASTER=y
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BFIN_LOCK is not set
 # CONFIG_SPI_BITBANG is not set
 
 #
@@ -510,9 +536,13 @@ CONFIG_SPI_BFIN=y
 # CONFIG_SPI_AT25 is not set
 # CONFIG_SPI_SPIDEV is not set
 # CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
 
@@ -523,20 +553,27 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 
 #
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_WM8400 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
 # CONFIG_DAB is not set
 
 #
@@ -551,20 +588,16 @@ CONFIG_SSB_POSSIBLE=y
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
-
-#
-# Userspace I/O
-#
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
@@ -574,19 +607,17 @@ CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT2_FS_POSIX_ACL is not set
 # CONFIG_EXT2_FS_SECURITY is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -628,8 +659,11 @@ CONFIG_SYSFS=y
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
 
@@ -639,7 +673,6 @@ CONFIG_SYSFS=y
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
-# CONFIG_INSTRUMENTATION is not set
 
 #
 # Kernel hacking
@@ -647,14 +680,22 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_PRINTK_TIME is not set
 CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_VERBOSE=y
 CONFIG_DEBUG_MMRS=y
+# CONFIG_DEBUG_DOUBLEFAULT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
 CONFIG_DEBUG_BFIN_HWTRACE_ON=y
 CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
@@ -671,9 +712,8 @@ CONFIG_ACCESS_CHECK=y
 # Security options
 #
 # CONFIG_KEYS is not set
-CONFIG_SECURITY=y
-# CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
@@ -682,6 +722,7 @@ CONFIG_SECURITY_CAPABILITIES=y
 #
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 # CONFIG_CRC32 is not set
 # CONFIG_CRC7 is not set
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index 25776c19064b..94b2a9b19451 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -15,104 +15,159 @@
  */
 
 #define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
 #define atomic_set(v, i)        (((v)->counter) = i)
 
-static __inline__ void atomic_add(int i, atomic_t * v)
+#ifdef CONFIG_SMP
+
+#define atomic_read(v)  __raw_uncached_fetch_asm(&(v)->counter)
+
+asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
+
+asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
+
+asmlinkage int __raw_atomic_clear_asm(volatile int *ptr, int value);
+
+asmlinkage int __raw_atomic_set_asm(volatile int *ptr, int value);
+
+asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
+
+asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+        __raw_atomic_update_asm(&v->counter, i);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        __raw_atomic_update_asm(&v->counter, -i);
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        return __raw_atomic_update_asm(&v->counter, i);
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        return __raw_atomic_update_asm(&v->counter, -i);
+}
+
+static inline void atomic_inc(volatile atomic_t *v)
+{
+        __raw_atomic_update_asm(&v->counter, 1);
+}
+
+static inline void atomic_dec(volatile atomic_t *v)
+{
+        __raw_atomic_update_asm(&v->counter, -1);
+}
+
+static inline void atomic_clear_mask(int mask, atomic_t *v)
+{
+        __raw_atomic_clear_asm(&v->counter, mask);
+}
+
+static inline void atomic_set_mask(int mask, atomic_t *v)
+{
+        __raw_atomic_set_asm(&v->counter, mask);
+}
+
+static inline int atomic_test_mask(int mask, atomic_t *v)
+{
+        return __raw_atomic_test_asm(&v->counter, mask);
+}
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec()    barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc()    barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#else /* !CONFIG_SMP */
+
+#define atomic_read(v)  ((v)->counter)
+
+static inline void atomic_add(int i, atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter += i;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ void atomic_sub(int i, atomic_t * v)
+static inline void atomic_sub(int i, atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter -= i;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
 }
 
-static inline int atomic_add_return(int i, atomic_t * v)
+static inline int atomic_add_return(int i, atomic_t *v)
 {
         int __temp = 0;
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter += i;
         __temp = v->counter;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
 
         return __temp;
 }
 
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-static inline int atomic_sub_return(int i, atomic_t * v)
+static inline int atomic_sub_return(int i, atomic_t *v)
 {
         int __temp = 0;
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter -= i;
         __temp = v->counter;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return __temp;
 }
 
-static __inline__ void atomic_inc(volatile atomic_t * v)
+static inline void atomic_inc(volatile atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter++;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-static __inline__ void atomic_dec(volatile atomic_t * v)
+static inline void atomic_dec(volatile atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter--;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
+static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter &= ~mask;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
+static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
         long flags;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         v->counter |= mask;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 /* Atomic operations are already serializing */
@@ -121,9 +176,25 @@ static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
 #define smp_mb__before_atomic_inc()    barrier()
 #define smp_mb__after_atomic_inc() barrier()
 
+#endif /* !CONFIG_SMP */
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
 #define atomic_dec_return(v) atomic_sub_return(1,(v))
 #define atomic_inc_return(v) atomic_add_return(1,(v))
 
+#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define atomic_add_unless(v, a, u)                              \
+({                                                              \
+        int c, old;                                             \
+        c = atomic_read(v);                                     \
+        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
+                c = old;                                        \
+        c != (u);                                               \
+})
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
 /*
  * atomic_inc_and_test - increment and test
  * @v: pointer of type atomic_t
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 77295666c34b..daffc0684e75 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -47,6 +47,9 @@
 # define DMA_UNCACHED_REGION (0)
 #endif
 
+extern void bfin_setup_caches(unsigned int cpu);
+extern void bfin_setup_cpudata(unsigned int cpu);
+
 extern unsigned long get_cclk(void);
 extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
@@ -58,8 +61,6 @@ extern void dump_bfin_trace_buffer(void);
 
 /* init functions only */
 extern int init_arch_irq(void);
-extern void bfin_icache_init(void);
-extern void bfin_dcache_init(void);
 extern void init_exception_vectors(void);
 extern void program_IAR(void);
 
@@ -110,7 +111,7 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
 
 #ifdef CONFIG_BFIN_ICACHE_LOCK
 extern void cache_grab_lock(int way);
-extern void cache_lock(int way);
+extern void bfin_cache_lock(int way);
 #endif
 
 #endif
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index 9fa19158e38d..1306e6b22946 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -1,22 +1,12 @@
-/************************************************************
-
-* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
-*
-* FILE bfin5xx_spi.h
-* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
-*
-*
-* DATE OF CREATION: March. 10th 2006
-*
-* SYNOPSIS:
-*
-* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
-**************************************************************
-
-* MODIFICATION HISTORY:
-* March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
-
-************************************************************/
+/*
+ * Blackfin On-Chip SPI Driver
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _SPI_CHANNEL_H_
 #define _SPI_CHANNEL_H_
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
new file mode 100644
index 000000000000..d61d5497c590
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -0,0 +1,19 @@
+/*
+ * bfin_sdh.h - Blackfin SDH definitions
+ *
+ * Copyright 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_SDH_H__
+#define __BFIN_SDH_H__
+
+struct bfin_sd_host {
+        int dma_chan;
+        int irq_int0;
+        int irq_int1;
+        u16 pin_req[7];
+};
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index c76ed8def302..fe88a2c19213 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -120,9 +120,6 @@ struct sport_register {
 #define SPORT_IOC_MAGIC         'P'
 #define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
 
-/* Test purpose */
-#define ENABLE_AD73311          _IOWR('P', 0x02, int)
-
 struct sport_dev {
         struct cdev cdev;       /* Char device structure */
 
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h
index cfe8024c3b2f..9e4be5e5e767 100644
--- a/arch/blackfin/include/asm/bfrom.h
+++ b/arch/blackfin/include/asm/bfrom.h
@@ -43,6 +43,11 @@ __attribute__((__noreturn__))
 static inline void bfrom_SoftReset(void *new_stack)
 {
         while (1)
+                /*
+                 * We don't declare the SP as clobbered on purpose, since
+                 * it confuses the heck out of the compiler, and this function
+                 * never returns
+                 */
                 __asm__ __volatile__(
                         "sp = %[stack];"
                         "jump (%[bfrom_syscontrol]);"
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index c428e4106f89..21b036eadab1 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -7,7 +7,6 @@
 
 #include <linux/compiler.h>
 #include <asm/byteorder.h>      /* swab32 */
-#include <asm/system.h>         /* save_flags */
 
 #ifdef __KERNEL__
 
@@ -20,80 +19,107 @@
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffz.h>
 
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
+#ifdef CONFIG_SMP
+
+#include <linux/linkage.h>
+
+asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
+
+asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
+
+static inline void set_bit(int nr, volatile unsigned long *addr)
 {
-        int *a = (int *)addr;
-        int mask;
-        unsigned long flags;
+        volatile unsigned long *a = addr + (nr >> 5);
+        __raw_bit_set_asm(a, nr & 0x1f);
+}
 
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a |= mask;
-        local_irq_restore(flags);
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr + (nr >> 5);
+        __raw_bit_clear_asm(a, nr & 0x1f);
 }
 
-static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
+static inline void change_bit(int nr, volatile unsigned long *addr)
 {
-        int *a = (int *)addr;
-        int mask;
+        volatile unsigned long *a = addr + (nr >> 5);
+        __raw_bit_toggle_asm(a, nr & 0x1f);
+}
 
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        *a |= mask;
+static inline int test_bit(int nr, const volatile unsigned long *addr)
+{
+        volatile const unsigned long *a = addr + (nr >> 5);
+        return __raw_bit_test_asm(a, nr & 0x1f) != 0;
 }
 
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr + (nr >> 5);
+        return __raw_bit_test_set_asm(a, nr & 0x1f);
+}
+
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr + (nr >> 5);
+        return __raw_bit_test_clear_asm(a, nr & 0x1f);
+}
+
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+        volatile unsigned long *a = addr + (nr >> 5);
+        return __raw_bit_test_toggle_asm(a, nr & 0x1f);
+}
+
+#else /* !CONFIG_SMP */
+
+#include <asm/system.h>         /* save_flags */
 
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
+static inline void set_bit(int nr, volatile unsigned long *addr)
 {
         int *a = (int *)addr;
         int mask;
         unsigned long flags;
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a &= ~mask;
-        local_irq_restore(flags);
+        local_irq_save_hw(flags);
+        *a |= mask;
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
+static inline void clear_bit(int nr, volatile unsigned long *addr)
 {
         int *a = (int *)addr;
         int mask;
-
+        unsigned long flags;
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
+        local_irq_save_hw(flags);
         *a &= ~mask;
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
+static inline void change_bit(int nr, volatile unsigned long *addr)
 {
         int mask, flags;
         unsigned long *ADDR = (unsigned long *)addr;
 
         ADDR += nr >> 5;
         mask = 1 << (nr & 31);
-        local_irq_save(flags);
-        *ADDR ^= mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask;
-        unsigned long *ADDR = (unsigned long *)addr;
-
-        ADDR += nr >> 5;
-        mask = 1 << (nr & 31);
+        local_irq_save_hw(flags);
         *ADDR ^= mask;
+        local_irq_restore_hw(flags);
 }
 
-static __inline__ int test_and_set_bit(int nr, void *addr)
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
         int mask, retval;
         volatile unsigned int *a = (volatile unsigned int *)addr;
@@ -101,27 +127,31 @@ static __inline__ int test_and_set_bit(int nr, void *addr)
 
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         retval = (mask & *a) != 0;
         *a |= mask;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return retval;
 }
 
-static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
         int mask, retval;
         volatile unsigned int *a = (volatile unsigned int *)addr;
+        unsigned long flags;
 
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
+        local_irq_save_hw(flags);
         retval = (mask & *a) != 0;
-        *a |= mask;
+        *a &= ~mask;
+        local_irq_restore_hw(flags);
+
         return retval;
 }
 
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
         int mask, retval;
         volatile unsigned int *a = (volatile unsigned int *)addr;
@@ -129,15 +159,52 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
 
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         retval = (mask & *a) != 0;
+        *a ^= mask;
+        local_irq_restore_hw(flags);
+        return retval;
+}
+
+#endif /* CONFIG_SMP */
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        *a |= mask;
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
         *a &= ~mask;
-        local_irq_restore(flags);
+}
 
-        return retval;
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+        int mask;
+        unsigned long *ADDR = (unsigned long *)addr;
+
+        ADDR += nr >> 5;
+        mask = 1 << (nr & 31);
+        *ADDR ^= mask;
 }
 
-static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
 {
         int mask, retval;
         volatile unsigned int *a = (volatile unsigned int *)addr;
@@ -145,26 +212,23 @@ static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
         retval = (mask & *a) != 0;
-        *a &= ~mask;
+        *a |= mask;
         return retval;
 }
 
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
         int mask, retval;
         volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
 
         a += nr >> 5;
         mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
         retval = (mask & *a) != 0;
-        *a ^= mask;
-        local_irq_restore(flags);
+        *a &= ~mask;
         return retval;
 }
 
-static __inline__ int __test_and_change_bit(int nr,
+static inline int __test_and_change_bit(int nr,
                                             volatile unsigned long *addr)
 {
         int mask, retval;
@@ -177,16 +241,7 @@ static __inline__ int __test_and_change_bit(int nr,
         return retval;
 }
 
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const void *addr)
-{
-        return ((1UL << (nr & 31)) &
-                (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, const void *addr)
+static inline int __test_bit(int nr, const void *addr)
 {
         int *a = (int *)addr;
         int mask;
@@ -196,10 +251,16 @@ static __inline__ int __test_bit(int nr, const void *addr)
         return ((mask & *a) != 0);
 }
 
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
+#ifndef CONFIG_SMP
+/*
+ * This routine doesn't need irq save and restore ops in UP
+ * context.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+        return __test_bit(nr, addr);
+}
+#endif
 
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/hweight.h>
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 8749b0e321ab..8bb2cb139756 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -6,11 +6,6 @@
 #ifndef _BLACKFIN_H_
 #define _BLACKFIN_H_
 
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
 #include <mach/anomaly.h>
 
 #ifndef __ASSEMBLY__
@@ -65,6 +60,11 @@ static inline void CSYNC(void)
 
 #else  /* __ASSEMBLY__ */
 
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
 /* SSYNC & CSYNC implementations for assembly files */
 
 #define ssync(x) SSYNC(x)
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 023d72133b5a..86637814cf25 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -12,6 +12,11 @@
 #define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 
+#ifdef CONFIG_SMP
+#define __cacheline_aligned
+#else
+#define ____cacheline_aligned
+
 /*
  * Put cacheline_aliged data to L1 data memory
  */
@@ -21,9 +26,33 @@
                 __section__(".data_l1.cacheline_aligned")))
 #endif
 
+#endif
+
 /*
  * largest L1 which this arch supports
  */
 #define L1_CACHE_SHIFT_MAX      5
 
+#if defined(CONFIG_SMP) && \
+    !defined(CONFIG_BFIN_CACHE_COHERENT) && \
+    defined(CONFIG_BFIN_DCACHE)
+#define __ARCH_SYNC_CORE_DCACHE
+#ifndef __ASSEMBLY__
+asmlinkage void __raw_smp_mark_barrier_asm(void);
+asmlinkage void __raw_smp_check_barrier_asm(void);
+
+static inline void smp_mark_barrier(void)
+{
+        __raw_smp_mark_barrier_asm();
+}
+static inline void smp_check_barrier(void)
+{
+        __raw_smp_check_barrier_asm();
+}
+
+void resync_core_dcache(void);
+#endif
+#endif
+
+
 #endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 4403415583fa..1b040f5b4feb 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -35,6 +35,7 @@ extern void blackfin_icache_flush_range(unsigned long start_address, unsigned lo
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dflush_page(void *page);
+extern void blackfin_invalidate_entire_dcache(void);
 
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
@@ -44,12 +45,20 @@ extern void blackfin_dflush_page(void *page);
 #define flush_cache_vmap(start, end)            do { } while (0)
 #define flush_cache_vunmap(start, end)          do { } while (0)
 
+#ifdef CONFIG_SMP
+#define flush_icache_range_others(start, end)   \
+        smp_icache_flush_range_others((start), (end))
+#else
+#define flush_icache_range_others(start, end)   do { } while (0)
+#endif
+
 static inline void flush_icache_range(unsigned start, unsigned end)
 {
 #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
 
 # if defined(CONFIG_BFIN_WT)
         blackfin_icache_flush_range((start), (end));
+        flush_icache_range_others(start, end);
 # else
         blackfin_icache_dcache_flush_range((start), (end));
 # endif
@@ -58,6 +67,7 @@ static inline void flush_icache_range(unsigned start, unsigned end)
 
 # if defined(CONFIG_BFIN_ICACHE)
         blackfin_icache_flush_range((start), (end));
+        flush_icache_range_others(start, end);
 # endif
 # if defined(CONFIG_BFIN_DCACHE)
         blackfin_dcache_flush_range((start), (end));
@@ -66,10 +76,12 @@ static inline void flush_icache_range(unsigned start, unsigned end)
 #endif
 }
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
-     flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
+do { memcpy(dst, src, len);                                             \
+     flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len));    \
+     flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\
 } while (0)
+
 #define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
 
 #if defined(CONFIG_BFIN_DCACHE)
@@ -82,7 +94,7 @@ do { memcpy(dst, src, len); \
 # define flush_dcache_page(page)                        blackfin_dflush_page(page_address(page))
 #else
 # define flush_dcache_range(start,end)          do { } while (0)
-# define flush_dcache_page(page)                        do { } while (0)
+# define flush_dcache_page(page)                do { } while (0)
 #endif
 
 extern unsigned long reserved_mem_dcache_on;
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
index 6f6af2b8e9e0..f67289a0d8d2 100644
--- a/arch/blackfin/include/asm/checksum.h
+++ b/arch/blackfin/include/asm/checksum.h
@@ -78,7 +78,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
                  "%0 = %0 + %4;\n\t"
                  "NOP;\n\t"
                  : "=d" (sum)
-                 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
+                 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum)
+                 : "CC");
 
         return (sum);
 }
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index c0e630edfb9a..16561ab18b38 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -303,9 +303,14 @@
         RETI = [sp++];
         RETS = [sp++];
 
-        p0.h = _irq_flags;
-        p0.l = _irq_flags;
+#ifdef CONFIG_SMP
+        GET_PDA(p0, r0);
+        r0 = [p0 + PDA_IRQFLAGS];
+#else
+        p0.h = _bfin_irq_flags;
+        p0.l = _bfin_irq_flags;
         r0 = [p0];
+#endif
         sti r0;
 
         sp += 4;        /* Skip Reserved */
@@ -353,3 +358,41 @@
         csync;
 .endm
 
+.macro save_context_cplb
+        [--sp] = (R7:0, P5:0);
+        [--sp] = fp;
+
+        [--sp] = a0.x;
+        [--sp] = a0.w;
+        [--sp] = a1.x;
+        [--sp] = a1.w;
+
+        [--sp] = LC0;
+        [--sp] = LC1;
+        [--sp] = LT0;
+        [--sp] = LT1;
+        [--sp] = LB0;
+        [--sp] = LB1;
+
+        [--sp] = RETS;
+.endm
+
+.macro restore_context_cplb
+        RETS = [sp++];
+
+        LB1 = [sp++];
+        LB0 = [sp++];
+        LT1 = [sp++];
+        LT0 = [sp++];
+        LC1 = [sp++];
+        LC0 = [sp++];
+
+        a1.w = [sp++];
+        a1.x = [sp++];
+        a0.w = [sp++];
+        a0.x = [sp++];
+
+        fp = [sp++];
+
+        (R7:0, P5:0) = [SP++];
+.endm
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h
deleted file mode 100644
index 75c67b99d607..000000000000
--- a/arch/blackfin/include/asm/cplb-mpu.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplbinit.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#ifndef __ASM_BFIN_CPLB_MPU_H
-#define __ASM_BFIN_CPLB_MPU_H
-
-struct cplb_entry {
-        unsigned long data, addr;
-};
-
-struct mem_region {
-        unsigned long start, end;
-        unsigned long dcplb_data;
-        unsigned long icplb_data;
-};
-
-extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_mask_dcplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
-extern int nr_cplb_flush;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask;
-
-extern void flush_switched_cplbs(void);
-extern void set_mask_dcplbs(unsigned long *);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index 9e8b4035fcec..ad566ff9ad16 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -30,7 +30,6 @@
 #ifndef _CPLB_H
 #define _CPLB_H
 
-#include <asm/blackfin.h>
 #include <mach/anomaly.h>
 
 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
@@ -55,13 +54,24 @@
 #endif
 
 #define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
+
+#ifdef CONFIG_SMP
+#define L2_ATTR           (INITIAL_T | I_CPLB | D_CPLB)
+#define L2_IMEMORY         (CPLB_COMMON | CPLB_LOCK)
+#define L2_DMEMORY         (CPLB_COMMON | CPLB_LOCK)
+
+#else
 #ifdef CONFIG_BFIN_L2_CACHEABLE
 #define L2_IMEMORY        (SDRAM_IGENERIC)
 #define L2_DMEMORY        (SDRAM_DGENERIC)
 #else
 #define L2_IMEMORY        (CPLB_COMMON)
 #define L2_DMEMORY        (CPLB_COMMON)
-#endif
+#endif /* CONFIG_BFIN_L2_CACHEABLE */
+
+#define L2_ATTR           (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
+#endif /* CONFIG_SMP */
+
 #define SDRAM_DNON_CHBL  (CPLB_COMMON)
 #define SDRAM_EBIU       (CPLB_COMMON)
 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
@@ -71,14 +81,7 @@
 #define SIZE_1M 0x00100000      /* 1M */
 #define SIZE_4M 0x00400000      /* 4M */
 
-#ifdef CONFIG_MPU
 #define MAX_CPLBS 16
-#else
-#define MAX_CPLBS (16 * 2)
-#endif
-
-#define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
-                                 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
 
 #define CPLB_ENABLE_ICACHE_P    0
 #define CPLB_ENABLE_DCACHE_P    1
@@ -113,4 +116,8 @@
 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
 
+#define FAULT_RW        (1 << 16)
+#define FAULT_USERSUPV  (1 << 17)
+#define FAULT_CPLBBITS  0x0000ffff
+
 #endif                          /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
index f845b41147ba..05b14a631d0c 100644
--- a/arch/blackfin/include/asm/cplbinit.h
+++ b/arch/blackfin/include/asm/cplbinit.h
@@ -32,61 +32,56 @@
 
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
+#include <linux/threads.h>
 
-#ifdef CONFIG_MPU
-
-#include <asm/cplb-mpu.h>
-
+#ifdef CONFIG_CPLB_SWITCH_TAB_L1
+# define PDT_ATTR __attribute__((l1_data))
 #else
+# define PDT_ATTR
+#endif
 
-#define INITIAL_T 0x1
-#define SWITCH_T  0x2
-#define I_CPLB    0x4
-#define D_CPLB    0x8
-
-#define IN_KERNEL 1
-
-enum
-{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
-
-struct cplb_desc {
-        u32 start; /* start address */
-        u32 end; /* end address */
-        u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
-        u16 attr;/* attributes */
-        u16 i_conf;/* I-CPLB DATA */
-        u16 d_conf;/* D-CPLB DATA */
-        u16 valid;/* valid */
-        const s8 name[30];/* name */
+struct cplb_entry {
+        unsigned long data, addr;
 };
 
-struct cplb_tab {
-  u_long *tab;
-        u16 pos;
-        u16 size;
+struct cplb_boundary {
+        unsigned long eaddr; /* End of this region.  */
+        unsigned long data; /* CPLB data value.  */
 };
 
-extern u_long icplb_table[];
-extern u_long dcplb_table[];
+extern struct cplb_boundary dcplb_bounds[];
+extern struct cplb_boundary icplb_bounds[];
+extern int dcplb_nr_bounds, icplb_nr_bounds;
 
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
+extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
+extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
+extern int first_switched_icplb;
+extern int first_switched_dcplb;
 
-extern u_long ipdt_table[];
-extern u_long dpdt_table[];
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[];
-extern u_long dpdt_swapcount_table[];
-#endif
+extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
+extern int nr_dcplb_prot[], nr_cplb_flush[];
+
+#ifdef CONFIG_MPU
+
+extern int first_mask_dcplb;
+
+extern int page_mask_order;
+extern int page_mask_nelts;
+
+extern unsigned long *current_rwx_mask[NR_CPUS];
+
+extern void flush_switched_cplbs(unsigned int);
+extern void set_mask_dcplbs(unsigned long *, unsigned int);
+
+extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
 
 #endif /* CONFIG_MPU */
 
-extern void generate_cplb_tables(void);
+extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
+extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
 
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
+extern void generate_cplb_tables_all(void);
+extern void generate_cplb_tables_cpu(unsigned int cpu);
+#endif
 #endif
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
new file mode 100644
index 000000000000..c2594ef877f6
--- /dev/null
+++ b/arch/blackfin/include/asm/cpu.h
@@ -0,0 +1,41 @@
+/*
+ * File:         arch/blackfin/include/asm/cpu.h.
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_BLACKFIN_CPU_H
+#define __ASM_BLACKFIN_CPU_H
+
+#include <linux/percpu.h>
+
+struct task_struct;
+
+struct blackfin_cpudata {
+        struct cpu cpu;
+        struct task_struct *idle;
+        unsigned int imemctl;
+        unsigned int dmemctl;
+        unsigned long loops_per_jiffy;
+        unsigned long dcache_invld_count;
+};
+
+DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
+
+#endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index 6509733bb0f6..e4f7b8043f02 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -1,44 +1,17 @@
 /*
- * File:         include/asm-blackfin/simple_bf533_dma.h
- * Based on:     none - original work
- * Author:       LG Soft India
- *               Copyright (C) 2004-2005 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  This file contains the major Data structures and constants
- *               used for DMA Implementation in BF533
- * Modified:
+ * dma.h - Blackfin DMA defines/structures/etc...
  *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _BLACKFIN_DMA_H_
 #define _BLACKFIN_DMA_H_
 
-#include <asm/io.h>
-#include <linux/slab.h>
-#include <asm/irq.h>
-#include <asm/signal.h>
-
-#include <linux/kernel.h>
-#include <mach/dma.h>
-#include <linux/mm.h>
 #include <linux/interrupt.h>
+#include <mach/dma.h>
 #include <asm/blackfin.h>
+#include <asm/page.h>
 
 #define MAX_DMA_ADDRESS PAGE_OFFSET
 
@@ -79,7 +52,7 @@ enum dma_chan_status {
 #define DMA_SYNC_RESTART        1
 
 struct dmasg {
-        unsigned long next_desc_addr;
+        void *next_desc_addr;
         unsigned long start_addr;
         unsigned short cfg;
         unsigned short x_count;
@@ -89,7 +62,7 @@ struct dmasg {
 } __attribute__((packed));
 
 struct dma_register {
-        unsigned long next_desc_ptr;    /* DMA Next Descriptor Pointer register */
+        void *next_desc_ptr;    /* DMA Next Descriptor Pointer register */
         unsigned long start_addr;       /* DMA Start address  register */
 
         unsigned short cfg;     /* DMA Configuration register */
@@ -109,7 +82,7 @@ struct dma_register {
         short y_modify; /* DMA y_modify register */
         unsigned short dummy5;
 
-        unsigned long curr_desc_ptr;    /* DMA Current Descriptor Pointer
+        void *curr_desc_ptr;    /* DMA Current Descriptor Pointer
                                            register */
         unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
                                                    register */
@@ -131,19 +104,15 @@ struct dma_register {
 
 };
 
-typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
-
+struct mutex;
 struct dma_channel {
         struct mutex dmalock;
-        char *device_id;
+        const char *device_id;
         enum dma_chan_status chan_status;
-        struct dma_register *regs;
+        volatile struct dma_register *regs;
         struct dmasg *sg;               /* large mode descriptor */
-        unsigned int ctrl_num;  /* controller number */
-        dma_interrupt_t irq_callback;
+        unsigned int irq;
         void *data;
-        unsigned int dma_enable_flag;
-        unsigned int loopback_flag;
 #ifdef CONFIG_PM
         unsigned short saved_peripheral_map;
 #endif
@@ -157,49 +126,132 @@ void blackfin_dma_resume(void);
 /*******************************************************************************
 *       DMA API's
 *******************************************************************************/
-/* functions to set register mode */
-void set_dma_start_addr(unsigned int channel, unsigned long addr);
-void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_x_count(unsigned int channel, unsigned short x_count);
-void set_dma_x_modify(unsigned int channel, short x_modify);
-void set_dma_y_count(unsigned int channel, unsigned short y_count);
-void set_dma_y_modify(unsigned int channel, short y_modify);
-void set_dma_config(unsigned int channel, unsigned short config);
-unsigned short set_bfin_dma_config(char direction, char flow_mode,
-                                   char intr_mode, char dma_mode, char width,
-                                   char syncmode);
-void set_dma_curr_addr(unsigned int channel, unsigned long addr);
-
-/* get curr status for polling */
-unsigned short get_dma_curr_irqstat(unsigned int channel);
-unsigned short get_dma_curr_xcount(unsigned int channel);
-unsigned short get_dma_curr_ycount(unsigned int channel);
-unsigned long get_dma_next_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_addr(unsigned int channel);
-
-/* set large DMA mode descriptor */
-void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
-
-/* check if current channel is in use */
-int dma_channel_active(unsigned int channel);
-
-/* common functions must be called in any mode */
+extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
+extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
+extern int channel2irq(unsigned int channel);
+
+static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
+{
+        dma_ch[channel].regs->start_addr = addr;
+}
+static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
+{
+        dma_ch[channel].regs->next_desc_ptr = addr;
+}
+static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
+{
+        dma_ch[channel].regs->curr_desc_ptr = addr;
+}
+static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
+{
+        dma_ch[channel].regs->x_count = x_count;
+}
+static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
+{
+        dma_ch[channel].regs->y_count = y_count;
+}
+static inline void set_dma_x_modify(unsigned int channel, short x_modify)
+{
+        dma_ch[channel].regs->x_modify = x_modify;
+}
+static inline void set_dma_y_modify(unsigned int channel, short y_modify)
+{
+        dma_ch[channel].regs->y_modify = y_modify;
+}
+static inline void set_dma_config(unsigned int channel, unsigned short config)
+{
+        dma_ch[channel].regs->cfg = config;
+}
+static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
+{
+        dma_ch[channel].regs->curr_addr_ptr = addr;
+}
+
+static inline unsigned short
+set_bfin_dma_config(char direction, char flow_mode,
+                    char intr_mode, char dma_mode, char width, char syncmode)
+{
+        return (direction << 1) | (width << 2) | (dma_mode << 4) |
+                (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
+}
+
+static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
+{
+        return dma_ch[channel].regs->irq_status;
+}
+static inline unsigned short get_dma_curr_xcount(unsigned int channel)
+{
+        return dma_ch[channel].regs->curr_x_count;
+}
+static inline unsigned short get_dma_curr_ycount(unsigned int channel)
+{
+        return dma_ch[channel].regs->curr_y_count;
+}
+static inline void *get_dma_next_desc_ptr(unsigned int channel)
+{
+        return dma_ch[channel].regs->next_desc_ptr;
+}
+static inline void *get_dma_curr_desc_ptr(unsigned int channel)
+{
+        return dma_ch[channel].regs->curr_desc_ptr;
+}
+static inline unsigned short get_dma_config(unsigned int channel)
+{
+        return dma_ch[channel].regs->cfg;
+}
+static inline unsigned long get_dma_curr_addr(unsigned int channel)
+{
+        return dma_ch[channel].regs->curr_addr_ptr;
+}
+
+static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
+{
+        dma_ch[channel].regs->cfg =
+                (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
+                ((ndsize & 0xf) << 8);
+        dma_ch[channel].regs->next_desc_ptr = sg;
+}
+
+static inline int dma_channel_active(unsigned int channel)
+{
+        if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE)
+                return 0;
+        else
+                return 1;
+}
+
+static inline void disable_dma(unsigned int channel)
+{
+        dma_ch[channel].regs->cfg &= ~DMAEN;
+        SSYNC();
+        dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
+}
+static inline void enable_dma(unsigned int channel)
+{
+        dma_ch[channel].regs->curr_x_count = 0;
+        dma_ch[channel].regs->curr_y_count = 0;
+        dma_ch[channel].regs->cfg |= DMAEN;
+        dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
+}
 void free_dma(unsigned int channel);
-int dma_channel_active(unsigned int channel); /* check if a channel is in use */
-void disable_dma(unsigned int channel);
-void enable_dma(unsigned int channel);
-int request_dma(unsigned int channel, char *device_id);
-int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
-                     void *data);
-void dma_disable_irq(unsigned int channel);
-void dma_enable_irq(unsigned int channel);
-void clear_dma_irqstat(unsigned int channel);
+int request_dma(unsigned int channel, const char *device_id);
+int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
+
+static inline void dma_disable_irq(unsigned int channel)
+{
+        disable_irq(dma_ch[channel].irq);
+}
+static inline void dma_enable_irq(unsigned int channel)
+{
+        enable_irq(dma_ch[channel].irq);
+}
+static inline void clear_dma_irqstat(unsigned int channel)
+{
+        dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
+}
+
 void *dma_memcpy(void *dest, const void *src, size_t count);
 void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
+void blackfin_dma_early_init(void);
 
 #endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
index c4f721e0d00d..b30a2968e274 100644
--- a/arch/blackfin/include/asm/entry.h
+++ b/arch/blackfin/include/asm/entry.h
@@ -27,6 +27,14 @@
 #define SAVE_ALL_SYS            save_context_no_interrupts
 /* This is used for all normal interrupts.  It saves a minimum of registers
    to the stack, loads the IRQ number, and jumps to common code.  */
+#ifdef CONFIG_IPIPE
+# define LOAD_IPIPE_IPEND \
+        P0.l = lo(IPEND); \
+        P0.h = hi(IPEND); \
+        R1 = [P0];
+#else
+# define LOAD_IPIPE_IPEND
+#endif
 #define INTERRUPT_ENTRY(N)                                              \
     [--sp] = SYSCFG;                                                    \
                                                                         \
@@ -34,6 +42,7 @@
     [--sp] = R0;        /*orig_r0*/                                     \
     [--sp] = (R7:0,P5:0);                                               \
     R0 = (N);                                                           \
+    LOAD_IPIPE_IPEND                                                    \
     jump __common_int_entry;
 
 /* For timer interrupts, we need to save IPEND, since the user_mode
@@ -53,9 +62,11 @@
 /* This one pushes RETI without using CLI.  Interrupts are enabled.  */
 #define SAVE_CONTEXT_SYSCALL    save_context_syscall
 #define SAVE_CONTEXT            save_context_with_interrupts
+#define SAVE_CONTEXT_CPLB       save_context_cplb
 
 #define RESTORE_ALL_SYS         restore_context_no_interrupts
 #define RESTORE_CONTEXT         restore_context_with_interrupts
+#define RESTORE_CONTEXT_CPLB    restore_context_cplb
 
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index ad33ac271fd9..9477d82fcad2 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -84,11 +84,14 @@
 #ifndef __ARCH_BLACKFIN_GPIO_H__
 #define __ARCH_BLACKFIN_GPIO_H__
 
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x)  (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
+#define gpio_bank(x)    ((x) >> 4)
+#define gpio_bit(x)     (1<<((x) & 0xF))
+#define gpio_sub_n(x)   ((x) & 0xF)
 
-#define GPIO_BANKSIZE 16
+#define GPIO_BANKSIZE   16
+#define GPIO_BANK_NUM   DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
+
+#include <mach/gpio.h>
 
 #define GPIO_0  0
 #define GPIO_1  1
@@ -139,151 +142,9 @@
 #define GPIO_46 46
 #define GPIO_47 47
 
-
 #define PERIPHERAL_USAGE 1
 #define GPIO_USAGE 0
 
-#ifdef BF533_FAMILY
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-
-#endif
-
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PG0        16
-#define GPIO_PG1        17
-#define GPIO_PG2        18
-#define GPIO_PG3        19
-#define GPIO_PG4        20
-#define GPIO_PG5        21
-#define GPIO_PG6        22
-#define GPIO_PG7        23
-#define GPIO_PG8        24
-#define GPIO_PG9        25
-#define GPIO_PG10       26
-#define GPIO_PG11       27
-#define GPIO_PG12       28
-#define GPIO_PG13       29
-#define GPIO_PG14       30
-#define GPIO_PG15       31
-#define GPIO_PH0        32
-#define GPIO_PH1        33
-#define GPIO_PH2        34
-#define GPIO_PH3        35
-#define GPIO_PH4        36
-#define GPIO_PH5        37
-#define GPIO_PH6        38
-#define GPIO_PH7        39
-#define GPIO_PH8        40
-#define GPIO_PH9        41
-#define GPIO_PH10       42
-#define GPIO_PH11       43
-#define GPIO_PH12       44
-#define GPIO_PH13       45
-#define GPIO_PH14       46
-#define GPIO_PH15       47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif
-
-#ifdef BF548_FAMILY
-#include <mach/gpio.h>
-#endif
-
-#ifdef BF561_FAMILY
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PF16       16
-#define GPIO_PF17       17
-#define GPIO_PF18       18
-#define GPIO_PF19       19
-#define GPIO_PF20       20
-#define GPIO_PF21       21
-#define GPIO_PF22       22
-#define GPIO_PF23       23
-#define GPIO_PF24       24
-#define GPIO_PF25       25
-#define GPIO_PF26       26
-#define GPIO_PF27       27
-#define GPIO_PF28       28
-#define GPIO_PF29       29
-#define GPIO_PF30       30
-#define GPIO_PF31       31
-#define GPIO_PF32       32
-#define GPIO_PF33       33
-#define GPIO_PF34       34
-#define GPIO_PF35       35
-#define GPIO_PF36       36
-#define GPIO_PF37       37
-#define GPIO_PF38       38
-#define GPIO_PF39       39
-#define GPIO_PF40       40
-#define GPIO_PF41       41
-#define GPIO_PF42       42
-#define GPIO_PF43       43
-#define GPIO_PF44       44
-#define GPIO_PF45       45
-#define GPIO_PF46       46
-#define GPIO_PF47       47
-
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
-#endif
-
 #ifndef __ASSEMBLY__
 
 /***********************************************************
@@ -425,20 +286,77 @@ struct gpio_port_s {
 * MODIFICATION HISTORY :
 **************************************************************/
 
-int gpio_request(unsigned, const char *);
-void gpio_free(unsigned);
-
-void gpio_set_value(unsigned gpio, int arg);
-int gpio_get_value(unsigned gpio);
+int bfin_gpio_request(unsigned gpio, const char *label);
+void bfin_gpio_free(unsigned gpio);
+int bfin_gpio_irq_request(unsigned gpio, const char *label);
+void bfin_gpio_irq_free(unsigned gpio);
+int bfin_gpio_direction_input(unsigned gpio);
+int bfin_gpio_direction_output(unsigned gpio, int value);
+int bfin_gpio_get_value(unsigned gpio);
+void bfin_gpio_set_value(unsigned gpio, int value);
 
 #ifndef BF548_FAMILY
-#define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
+#define bfin_gpio_set_value(gpio, value)    set_gpio_data(gpio, value)
 #endif
 
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
+#ifdef CONFIG_GPIOLIB
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+        if (gpio < MAX_BLACKFIN_GPIOS)
+                return bfin_gpio_get_value(gpio);
+        else
+                return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+        if (gpio < MAX_BLACKFIN_GPIOS)
+                bfin_gpio_set_value(gpio, value);
+        else
+                __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+#else /* !CONFIG_GPIOLIB */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return bfin_gpio_request(gpio, label);
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        return bfin_gpio_free(gpio);
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return bfin_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return bfin_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return bfin_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        return bfin_gpio_set_value(gpio, value);
+}
 
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
+#endif  /* !CONFIG_GPIOLIB */
 #include <asm/irq.h>
 
 static inline int gpio_to_irq(unsigned gpio)
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
index b6b19f1b9dab..717181a1749b 100644
--- a/arch/blackfin/include/asm/hardirq.h
+++ b/arch/blackfin/include/asm/hardirq.h
@@ -42,4 +42,6 @@ typedef struct {
 
 #define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
 
+extern void ack_bad_irq(unsigned int irq);
+
 #endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 7dc77a21fdf3..63b2d8c78570 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -94,12 +94,12 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define outw_p(x,addr) outw(x,addr)
 #define outl_p(x,addr) outl(x,addr)
 
-#define ioread8_rep(a,d,c)      insb(a,d,c)
-#define ioread16_rep(a,d,c)     insw(a,d,c)
-#define ioread32_rep(a,d,c)     insl(a,d,c)
-#define iowrite8_rep(a,s,c)     outsb(a,s,c)
-#define iowrite16_rep(a,s,c)    outsw(a,s,c)
-#define iowrite32_rep(a,s,c)    outsl(a,s,c)
+#define ioread8_rep(a,d,c)      readsb(a,d,c)
+#define ioread16_rep(a,d,c)     readsw(a,d,c)
+#define ioread32_rep(a,d,c)     readsl(a,d,c)
+#define iowrite8_rep(a,s,c)     writesb(a,s,c)
+#define iowrite16_rep(a,s,c)    writesw(a,s,c)
+#define iowrite32_rep(a,s,c)    writesl(a,s,c)
 
 #define ioread8(X)                      readb(X)
 #define ioread16(X)                     readw(X)
@@ -108,6 +108,8 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define iowrite16(val,X)                writew(val,X)
 #define iowrite32(val,X)                writel(val,X)
 
+#define mmiowb() wmb()
+
 #define IO_SPACE_LIMIT 0xffffffff
 
 /* Values for nocacheflag and cmode */
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
new file mode 100644
index 000000000000..76f53d8b9a0d
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -0,0 +1,278 @@
+/*   -*- linux-c -*-
+ *   include/asm-blackfin/ipipe.h
+ *
+ *   Copyright (C) 2002-2007 Philippe Gerum.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ *   USA; either version 2 of the License, or (at your option) any later
+ *   version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_BLACKFIN_IPIPE_H
+#define __ASM_BLACKFIN_IPIPE_H
+
+#ifdef CONFIG_IPIPE
+
+#include <linux/cpumask.h>
+#include <linux/list.h>
+#include <linux/threads.h>
+#include <linux/irq.h>
+#include <linux/ipipe_percpu.h>
+#include <asm/ptrace.h>
+#include <asm/irq.h>
+#include <asm/bitops.h>
+#include <asm/atomic.h>
+#include <asm/traps.h>
+
+#define IPIPE_ARCH_STRING     "1.8-00"
+#define IPIPE_MAJOR_NUMBER    1
+#define IPIPE_MINOR_NUMBER    8
+#define IPIPE_PATCH_NUMBER    0
+
+#ifdef CONFIG_SMP
+#error "I-pipe/blackfin: SMP not implemented"
+#else /* !CONFIG_SMP */
+#define ipipe_processor_id()    0
+#endif  /* CONFIG_SMP */
+
+#define prepare_arch_switch(next)               \
+do {                                            \
+        ipipe_schedule_notify(current, next);   \
+        local_irq_disable_hw();                 \
+} while (0)
+
+#define task_hijacked(p)                                                \
+        ({                                                              \
+                int __x__ = ipipe_current_domain != ipipe_root_domain;  \
+                /* We would need to clear the SYNC flag for the root domain */ \
+                /* over the current processor in SMP mode. */           \
+                local_irq_enable_hw(); __x__;                           \
+        })
+
+struct ipipe_domain;
+
+struct ipipe_sysinfo {
+
+        int ncpus;              /* Number of CPUs on board */
+        u64 cpufreq;            /* CPU frequency (in Hz) */
+
+        /* Arch-dependent block */
+
+        struct {
+                unsigned tmirq; /* Timer tick IRQ */
+                u64 tmfreq;     /* Timer frequency */
+        } archdep;
+};
+
+#define ipipe_read_tsc(t)                                       \
+        ({                                                      \
+        unsigned long __cy2;                                    \
+        __asm__ __volatile__ ("1: %0 = CYCLES2\n"               \
+                                "%1 = CYCLES\n"                 \
+                                "%2 = CYCLES2\n"                \
+                                "CC = %2 == %0\n"               \
+                                "if ! CC jump 1b\n"             \
+                                : "=r" (((unsigned long *)&t)[1]),      \
+                                  "=r" (((unsigned long *)&t)[0]),      \
+                                  "=r" (__cy2)                          \
+                                : /*no input*/ : "CC");                 \
+        t;                                                              \
+        })
+
+#define ipipe_cpu_freq()        __ipipe_core_clock
+#define ipipe_tsc2ns(_t)        (((unsigned long)(_t)) * __ipipe_freq_scale)
+#define ipipe_tsc2us(_t)        (ipipe_tsc2ns(_t) / 1000 + 1)
+
+/* Private interface -- Internal use only */
+
+#define __ipipe_check_platform()        do { } while (0)
+
+#define __ipipe_init_platform()         do { } while (0)
+
+extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
+
+extern unsigned long __ipipe_irq_lvmask;
+
+extern struct ipipe_domain ipipe_root;
+
+/* enable/disable_irqdesc _must_ be used in pairs. */
+
+void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
+                            unsigned irq);
+
+void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
+                             unsigned irq);
+
+#define __ipipe_enable_irq(irq)         (irq_desc[irq].chip->unmask(irq))
+
+#define __ipipe_disable_irq(irq)        (irq_desc[irq].chip->mask(irq))
+
+#define __ipipe_lock_root()                                     \
+        set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
+
+#define __ipipe_unlock_root()                                   \
+        clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)
+
+void __ipipe_enable_pipeline(void);
+
+#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
+
+#define __ipipe_sync_pipeline(syncmask)                                 \
+        do {                                                            \
+                struct ipipe_domain *ipd = ipipe_current_domain;        \
+                if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
+                        __ipipe_sync_stage(syncmask);                   \
+        } while (0)
+
+void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
+
+int __ipipe_get_irq_priority(unsigned irq);
+
+int __ipipe_get_irqthread_priority(unsigned irq);
+
+void __ipipe_stall_root_raw(void);
+
+void __ipipe_unstall_root_raw(void);
+
+void __ipipe_serial_debug(const char *fmt, ...);
+
+DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
+
+extern unsigned long __ipipe_core_clock;
+
+extern unsigned long __ipipe_freq_scale;
+
+extern unsigned long __ipipe_irq_tail_hook;
+
+static inline unsigned long __ipipe_ffnz(unsigned long ul)
+{
+        return ffs(ul) - 1;
+}
+
+#define __ipipe_run_irqtail()  /* Must be a macro */                    \
+        do {                                                            \
+                asmlinkage void __ipipe_call_irqtail(void);             \
+                unsigned long __pending;                                \
+                CSYNC();                                        \
+                __pending = bfin_read_IPEND();                          \
+                if (__pending & 0x8000) {                               \
+                        __pending &= ~0x8010;                           \
+                        if (__pending && (__pending & (__pending - 1)) == 0) \
+                                __ipipe_call_irqtail();                 \
+                }                                                       \
+        } while (0)
+
+#define __ipipe_run_isr(ipd, irq)                                       \
+        do {                                                            \
+                if (ipd == ipipe_root_domain) {                         \
+                        /*                                              \
+                         * Note: the I-pipe implements a threaded interrupt model on \
+                         * this arch for Linux external IRQs. The interrupt handler we \
+                         * call here only wakes up the associated IRQ thread. \
+                         */                                             \
+                        if (ipipe_virtual_irq_p(irq)) {                 \
+                                /* No irqtail here; virtual interrupts have no effect \
+                                   on IPEND so there is no need for processing \
+                                   deferral. */                         \
+                                local_irq_enable_nohead(ipd);           \
+                                ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
+                                local_irq_disable_nohead(ipd);          \
+                        } else                                          \
+                                /*                                      \
+                                 * No need to run the irqtail here either; \
+                                 * we can't be preempted by hw IRQs, so \
+                                 * non-Linux IRQs cannot stack over the short \
+                                 * thread wakeup code. Which in turn means \
+                                 * that no irqtail condition could be pending \
+                                 * for domains above Linux in the pipeline. \
+                                 */                                     \
+                                ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
+                } else {                                                \
+                        __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
+                        local_irq_enable_nohead(ipd);                   \
+                        ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
+                        /* Attempt to exit the outer interrupt level before \
+                         * starting the deferred IRQ processing. */     \
+                        local_irq_disable_nohead(ipd);                  \
+                        __ipipe_run_irqtail();                          \
+                        __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
+                }                                                       \
+        } while (0)
+
+#define __ipipe_syscall_watched_p(p, sc)        \
+        (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
+
+void ipipe_init_irq_threads(void);
+
+int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
+
+#define IS_SYSIRQ(irq)          ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS)
+#define IS_GPIOIRQ(irq)         ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS)
+
+#define IRQ_SYSTMR              IRQ_TIMER0
+#define IRQ_PRIOTMR             CONFIG_IRQ_TIMER0
+
+#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533)
+#define PRIO_GPIODEMUX(irq)     CONFIG_PFA
+#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
+#define PRIO_GPIODEMUX(irq)     CONFIG_IRQ_PROG_INTA
+#elif defined(CONFIG_BF52x)
+#define PRIO_GPIODEMUX(irq)     ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
+                                 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
+                                 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
+                                 -1)
+#elif defined(CONFIG_BF561)
+#define PRIO_GPIODEMUX(irq)     ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
+                                 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
+                                 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
+                                 -1)
+#define bfin_write_TIMER_DISABLE(val)   bfin_write_TMRS8_DISABLE(val)
+#define bfin_write_TIMER_ENABLE(val)    bfin_write_TMRS8_ENABLE(val)
+#define bfin_write_TIMER_STATUS(val)    bfin_write_TMRS8_STATUS(val)
+#define bfin_read_TIMER_STATUS()        bfin_read_TMRS8_STATUS()
+#elif defined(CONFIG_BF54x)
+#define PRIO_GPIODEMUX(irq)     ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
+                                 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
+                                 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
+                                 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
+                                 -1)
+#define bfin_write_TIMER_DISABLE(val)   bfin_write_TIMER_DISABLE0(val)
+#define bfin_write_TIMER_ENABLE(val)    bfin_write_TIMER_ENABLE0(val)
+#define bfin_write_TIMER_STATUS(val)    bfin_write_TIMER_STATUS0(val)
+#define bfin_read_TIMER_STATUS(val)     bfin_read_TIMER_STATUS0(val)
+#else
+# error "no PRIO_GPIODEMUX() for this part"
+#endif
+
+#define __ipipe_root_tick_p(regs)       ((regs->ipend & 0x10) != 0)
+
+#else /* !CONFIG_IPIPE */
+
+#define task_hijacked(p)                0
+#define ipipe_trap_notify(t, r)         0
+
+#define __ipipe_stall_root_raw()        do { } while (0)
+#define __ipipe_unstall_root_raw()      do { } while (0)
+
+#define ipipe_init_irq_threads()                do { } while (0)
+#define ipipe_start_irq_thread(irq, desc)       0
+
+#define IRQ_SYSTMR              IRQ_CORETMR
+#define IRQ_PRIOTMR             IRQ_CORETMR
+
+#define __ipipe_root_tick_p(regs)       1
+
+#endif /* !CONFIG_IPIPE */
+
+#endif  /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
new file mode 100644
index 000000000000..cb1025aeabcf
--- /dev/null
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -0,0 +1,80 @@
+/*   -*- linux-c -*-
+ *   include/asm-blackfin/_baseipipe.h
+ *
+ *   Copyright (C) 2007 Philippe Gerum.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ *   USA; either version 2 of the License, or (at your option) any later
+ *   version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
+#define __ASM_BLACKFIN_IPIPE_BASE_H
+
+#ifdef CONFIG_IPIPE
+
+#define IPIPE_NR_XIRQS          NR_IRQS
+#define IPIPE_IRQ_ISHIFT        5       /* 2^5 for 32bits arch. */
+
+/* Blackfin-specific, global domain flags */
+#define IPIPE_ROOTLOCK_FLAG     1       /* Lock pipeline for root */
+
+ /* Blackfin traps -- i.e. exception vector numbers */
+#define IPIPE_NR_FAULTS         52 /* We leave a gap after VEC_ILL_RES. */
+/* Pseudo-vectors used for kernel events */
+#define IPIPE_FIRST_EVENT       IPIPE_NR_FAULTS
+#define IPIPE_EVENT_SYSCALL     (IPIPE_FIRST_EVENT)
+#define IPIPE_EVENT_SCHEDULE    (IPIPE_FIRST_EVENT + 1)
+#define IPIPE_EVENT_SIGWAKE     (IPIPE_FIRST_EVENT + 2)
+#define IPIPE_EVENT_SETSCHED    (IPIPE_FIRST_EVENT + 3)
+#define IPIPE_EVENT_INIT        (IPIPE_FIRST_EVENT + 4)
+#define IPIPE_EVENT_EXIT        (IPIPE_FIRST_EVENT + 5)
+#define IPIPE_EVENT_CLEANUP     (IPIPE_FIRST_EVENT + 6)
+#define IPIPE_LAST_EVENT        IPIPE_EVENT_CLEANUP
+#define IPIPE_NR_EVENTS         (IPIPE_LAST_EVENT + 1)
+
+#define IPIPE_TIMER_IRQ         IRQ_CORETMR
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bitops.h>
+
+extern int test_bit(int nr, const void *addr);
+
+
+extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
+
+static inline void __ipipe_stall_root(void)
+{
+        volatile unsigned long *p = &__ipipe_root_status;
+        set_bit(0, p);
+}
+
+static inline unsigned long __ipipe_test_and_stall_root(void)
+{
+        volatile unsigned long *p = &__ipipe_root_status;
+        return test_and_set_bit(0, p);
+}
+
+static inline unsigned long __ipipe_test_root(void)
+{
+        const unsigned long *p = &__ipipe_root_status;
+        return test_bit(0, p);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* CONFIG_IPIPE */
+
+#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 89f59e18af93..3d977909ce7d 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -17,56 +17,272 @@
 #ifndef _BFIN_IRQ_H_
 #define _BFIN_IRQ_H_
 
+/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
 #include <mach/irq.h>
-#include <asm/ptrace.h>
-
-/*******************************************************************************
- *****   INTRODUCTION ***********
- *   On the Blackfin, the interrupt structure allows remmapping of the hardware
- *   levels.
- * - I'm going to assume that the H/W level is going to stay at the default
- *   settings. If someone wants to go through and abstart this out, feel free
- *   to mod the interrupt numbering scheme.
- * - I'm abstracting the interrupts so that uClinux does not know anything
- *   about the H/W levels. If you want to change the H/W AND keep the abstracted
- *   levels that uClinux sees, you should be able to do most of it here.
- * - I've left the "abstract" numbering sparce in case someone wants to pull the
- *   interrupts apart (just the TX/RX for the various devices)
- *******************************************************************************/
+#include <asm/pda.h>
+#include <asm/processor.h>
 
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
+#ifdef CONFIG_SMP
+/* Forward decl needed due to cdef inter dependencies */
+static inline uint32_t __pure bfin_dspid(void);
+# define blackfin_core_id() (bfin_dspid() & 0xff)
+# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
+#else
+extern unsigned long bfin_irq_flags;
+#endif
 
-/*
- * Machine specific interrupt sources.
- *
- * Adding an interrupt service routine for a source with this bit
- * set indicates a special machine specific interrupt source.
- * The machine specific files define these sources.
- *
- * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
- * introduce unnecessary overhead.
- *
- * All interrupt handling is actually machine specific so it is better
- * to use function pointers, as used by the Sparc port, and select the
- * interrupt handling functions when initializing the kernel. This way
- * we save some unnecessary overhead at run-time.
- *                                                      01/11/97 - Jes
- */
+#ifdef CONFIG_IPIPE
+
+#include <linux/ipipe_trace.h>
+
+void __ipipe_unstall_root(void);
+
+void __ipipe_restore_root(unsigned long flags);
+
+#ifdef CONFIG_DEBUG_HWERR
+# define __all_masked_irq_flags 0x3f
+# define __save_and_cli_hw(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                "sti %1;" \
+                : "=&d"(x) \
+                : "d" (0x3F) \
+        )
+#else
+# define __all_masked_irq_flags 0x1f
+# define __save_and_cli_hw(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                : "=&d"(x) \
+        )
+#endif
+
+#define irqs_enabled_from_flags_hw(x)   ((x) != __all_masked_irq_flags)
+#define raw_irqs_disabled_flags(flags)  (!irqs_enabled_from_flags_hw(flags))
+#define local_test_iflag_hw(x)          irqs_enabled_from_flags_hw(x)
 
-extern void ack_bad_irq(unsigned int irq);
+#define local_save_flags(x)                                             \
+        do {                                                            \
+                (x) = __ipipe_test_root() ? \
+                        __all_masked_irq_flags : bfin_irq_flags; \
+        } while (0)
 
-static __inline__ int irq_canonicalize(int irq)
+#define local_irq_save(x)                               \
+        do {                                            \
+                (x) = __ipipe_test_and_stall_root();    \
+        } while (0)
+
+#define local_irq_restore(x)    __ipipe_restore_root(x)
+#define local_irq_disable()     __ipipe_stall_root()
+#define local_irq_enable()      __ipipe_unstall_root()
+#define irqs_disabled()         __ipipe_test_root()
+
+#define local_save_flags_hw(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                "sti %0;" \
+                : "=d"(x) \
+        )
+
+#define irqs_disabled_hw()                              \
+        ({                                              \
+                unsigned long flags;                    \
+                local_save_flags_hw(flags);             \
+                !irqs_enabled_from_flags_hw(flags);     \
+        })
+
+static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
 {
-        return irq;
+        /* Merge virtual and real interrupt mask bits into a single
+           32bit word. */
+        return (real & ~(1 << 31)) | ((virt != 0) << 31);
+}
+
+static inline int raw_demangle_irq_bits(unsigned long *x)
+{
+        int virt = (*x & (1 << 31)) != 0;
+        *x &= ~(1L << 31);
+        return virt;
 }
 
-/* count of spurious interrupts */
-/* extern volatile unsigned int num_spurious; */
+#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
+
+#define local_irq_disable_hw()                                          \
+        do {                                                            \
+                int _tmp_dummy;                                         \
+                if (!irqs_disabled_hw())                                \
+                        ipipe_trace_begin(0x80000000);                  \
+                __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : );        \
+        } while (0)
+
+#define local_irq_enable_hw()                                           \
+        do {                                                            \
+                if (irqs_disabled_hw())                                 \
+                        ipipe_trace_end(0x80000000);                    \
+                __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags));       \
+        } while (0)
+
+#define local_irq_save_hw(x)                            \
+        do {                                            \
+                __save_and_cli_hw(x);                   \
+                if (local_test_iflag_hw(x))             \
+                        ipipe_trace_begin(0x80000001);  \
+        } while (0)
+
+#define local_irq_restore_hw(x)                         \
+        do {                                            \
+                if (local_test_iflag_hw(x)) {           \
+                        ipipe_trace_end(0x80000001);    \
+                        local_irq_enable_hw_notrace();  \
+                }                                       \
+        } while (0)
+
+#define local_irq_disable_hw_notrace()                                  \
+        do {                                                            \
+                int _tmp_dummy;                                         \
+                __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : );        \
+        } while (0)
+
+#define local_irq_enable_hw_notrace() \
+        __asm__ __volatile__( \
+                "sti %0;" \
+                : \
+                : "d"(bfin_irq_flags) \
+        )
 
-#ifndef NO_IRQ
-#define NO_IRQ ((unsigned int)(-1))
+#define local_irq_save_hw_notrace(x) __save_and_cli_hw(x)
+
+#define local_irq_restore_hw_notrace(x)                 \
+        do {                                            \
+                if (local_test_iflag_hw(x))             \
+                        local_irq_enable_hw_notrace();  \
+        } while (0)
+
+#else /* CONFIG_IPIPE_TRACE_IRQSOFF */
+
+#define local_irq_enable_hw() \
+        __asm__ __volatile__( \
+                "sti %0;" \
+                : \
+                : "d"(bfin_irq_flags) \
+        )
+
+#define local_irq_disable_hw()                  \
+        do {                                    \
+                int _tmp_dummy;                 \
+                __asm__ __volatile__ (          \
+                        "cli %0;"               \
+                        : "=d" (_tmp_dummy));   \
+        } while (0)
+
+#define local_irq_restore_hw(x) \
+        do { \
+                if (irqs_enabled_from_flags_hw(x)) \
+                        local_irq_enable_hw(); \
+        } while (0)
+
+#define local_irq_save_hw(x)            __save_and_cli_hw(x)
+
+#define local_irq_disable_hw_notrace()  local_irq_disable_hw()
+#define local_irq_enable_hw_notrace()   local_irq_enable_hw()
+#define local_irq_save_hw_notrace(x)    local_irq_save_hw(x)
+#define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x)
+
+#endif  /* CONFIG_IPIPE_TRACE_IRQSOFF */
+
+#else /* !CONFIG_IPIPE */
+
+/*
+ * Interrupt configuring macros.
+ */
+#define local_irq_disable() \
+        do { \
+                int __tmp_dummy; \
+                __asm__ __volatile__( \
+                        "cli %0;" \
+                        : "=d" (__tmp_dummy) \
+                ); \
+        } while (0)
+
+#define local_irq_enable() \
+        __asm__ __volatile__( \
+                "sti %0;" \
+                : \
+                : "d" (bfin_irq_flags) \
+        )
+
+#ifdef CONFIG_DEBUG_HWERR
+# define __save_and_cli(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                "sti %1;" \
+                : "=&d" (x) \
+                : "d" (0x3F) \
+        )
+#else
+# define __save_and_cli(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                : "=&d" (x) \
+        )
 #endif
 
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
+#define local_save_flags(x) \
+        __asm__ __volatile__( \
+                "cli %0;" \
+                "sti %0;" \
+                : "=d" (x) \
+        )
+
+#ifdef CONFIG_DEBUG_HWERR
+#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
+#else
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+#endif
+
+#define local_irq_restore(x) \
+        do { \
+                if (irqs_enabled_from_flags(x)) \
+                        local_irq_enable(); \
+        } while (0)
+
+/* For spinlocks etc */
+#define local_irq_save(x) __save_and_cli(x)
+
+#define irqs_disabled()                         \
+({                                              \
+        unsigned long flags;                    \
+        local_save_flags(flags);                \
+        !irqs_enabled_from_flags(flags);        \
+})
+
+#define local_irq_save_hw(x)            local_irq_save(x)
+#define local_irq_restore_hw(x)         local_irq_restore(x)
+#define local_irq_enable_hw()           local_irq_enable()
+#define local_irq_disable_hw()          local_irq_disable()
+#define irqs_disabled_hw()              irqs_disabled()
+
+#endif /* !CONFIG_IPIPE */
+
+#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
+# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
+#else
+# define NOP_PAD_ANOMALY_05000244
+#endif
+
+#define idle_with_irq_disabled() \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000244 \
+                ".align 8;" \
+                "sti %0;" \
+                "idle;" \
+                : \
+                : "d" (bfin_irq_flags) \
+        )
+
+static inline int irq_canonicalize(int irq)
+{
+        return irq;
+}
 
 #endif                          /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
index c13ded777828..79dbefaa5bef 100644
--- a/arch/blackfin/include/asm/l1layout.h
+++ b/arch/blackfin/include/asm/l1layout.h
@@ -8,6 +8,7 @@
 
 #include <asm/blackfin.h>
 
+#ifndef CONFIG_SMP
 #ifndef __ASSEMBLY__
 
 /* Data that is "mapped" into the process VM at the start of the L1 scratch
@@ -24,8 +25,10 @@ struct l1_scratch_task_info
 };
 
 /* A pointer to the structure in memory.  */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
+#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\
+                                                get_l1_scratch_start())
 
 #endif
+#endif
 
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index cbe03f4a5698..255a9316ad36 100644
--- a/arch/blackfin/mach-bf527/include/mach/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -1,35 +1,20 @@
 /*
- * File:         include/asm-blackfin/mach-bf527/mem_init.h
- * Based on:
- * Author:
+ * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
  *
- * Created:
- * Description:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Licensed under the GPL-2 or later.
  */
 
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
+#if defined(EBIU_SDGCTL)
+#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
+    defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
+    defined(CONFIG_MEM_GENERIC_BOARD) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75) || \
+    defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
+    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
 #if (CONFIG_SCLK_HZ > 119402985)
 #define SDRAM_tRP       TRP_2
 #define SDRAM_tRP_num   2
@@ -104,53 +89,114 @@
 #endif
 #endif
 
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
+#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC8M32B2B5_7)
   /*SDRAM INFORMATION: */
 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 #define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_MT48LC32M8A2_75)
+#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
+    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
+    defined(CONFIG_MEM_GENERIC_BOARD) || \
+    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
   /*SDRAM INFORMATION: */
 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
+
+#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL        (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
+#else
+#define mem_SDRRC       CONFIG_MEM_SDRRC
+#define mem_SDGCTL      CONFIG_MEM_SDGCTL
+#endif
 #endif
 
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
+
+#if defined(EBIU_DDRCTL0)
+#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
+#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
+#define DDR_CLK_HZ(x)   (1000*1000*1000/x)
+
+#if defined(CONFIG_MEM_MT46V32M16_6T)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_MAX_tCK     13
+
+#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
+#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
+#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
+#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
+
+#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR        DDR_TWTR(1)
+#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
+#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 #endif
 
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
+#if defined(CONFIG_MEM_MT46V32M16_5B)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_MAX_tCK     13
+
+#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
+#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
+#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
+#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
+
+#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR        DDR_TWTR(2)
+#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
+#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 #endif
 
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+#if defined(CONFIG_MEM_GENERIC_BOARD)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_MAX_tCK     13
 
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
+#define DDR_tRCD        DDR_TRCD(3)
+#define DDR_tWTR        DDR_TWTR(2)
+#define DDR_tWR         DDR_TWR(2)
+#define DDR_tMRD        DDR_TMRD(2)
+#define DDR_tRP         DDR_TRP(3)
+#define DDR_tRAS        DDR_TRAS(7)
+#define DDR_tRC         DDR_TRC(10)
+#define DDR_tRFC        DDR_TRFC(12)
+#define DDR_tREFI       DDR_TREFI(1288)
+#endif
+
+#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
+# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
+#elif(CONFIG_SCLK_HZ <= 133333333)
+# define        DDR_CL          CL_2
+#else
+# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
+#endif
+
+#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
+#define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
+#define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
+                        | DDR_tMRD | DDR_tWR | DDR_tRCD)
+#define mem_DDRCTL2     DDR_CL
+#else
+#define mem_DDRCTL0     CONFIG_MEM_DDRCTL0
+#define mem_DDRCTL1     CONFIG_MEM_DDRCTL1
+#define mem_DDRCTL2     CONFIG_MEM_DDRCTL2
+#endif
+#endif
 
 #if defined CONFIG_CLKIN_HALF
 #define CLKIN_HALF       1
@@ -165,6 +211,13 @@
 #endif
 
 /***************************************Currently Not Being Used *********************************/
+
+#if defined(CONFIG_FLASH_SPEED_BWAT) && \
+defined(CONFIG_FLASH_SPEED_BRAT) && \
+defined(CONFIG_FLASH_SPEED_BHT) && \
+defined(CONFIG_FLASH_SPEED_BST) && \
+defined(CONFIG_FLASH_SPEED_BTT)
+
 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
@@ -308,3 +361,4 @@
 #define flash_EBIU_AMBCTL0  \
         (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
          flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
+#endif
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
index 88d04a707708..e92b31051bb7 100644
--- a/arch/blackfin/include/asm/mem_map.h
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -9,4 +9,79 @@
 
 #include <mach/mem_map.h>
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SMP
+static inline ulong get_l1_scratch_start_cpu(int cpu)
+{
+        return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
+}
+static inline ulong get_l1_code_start_cpu(int cpu)
+{
+        return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;
+}
+static inline ulong get_l1_data_a_start_cpu(int cpu)
+{
+        return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
+}
+static inline ulong get_l1_data_b_start_cpu(int cpu)
+{
+        return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
+}
+
+static inline ulong get_l1_scratch_start(void)
+{
+        return get_l1_scratch_start_cpu(blackfin_core_id());
+}
+static inline ulong get_l1_code_start(void)
+{
+        return get_l1_code_start_cpu(blackfin_core_id());
+}
+static inline ulong get_l1_data_a_start(void)
+{
+        return get_l1_data_a_start_cpu(blackfin_core_id());
+}
+static inline ulong get_l1_data_b_start(void)
+{
+        return get_l1_data_b_start_cpu(blackfin_core_id());
+}
+
+#else /* !CONFIG_SMP */
+
+static inline ulong get_l1_scratch_start_cpu(int cpu)
+{
+        return L1_SCRATCH_START;
+}
+static inline ulong get_l1_code_start_cpu(int cpu)
+{
+        return L1_CODE_START;
+}
+static inline ulong get_l1_data_a_start_cpu(int cpu)
+{
+        return L1_DATA_A_START;
+}
+static inline ulong get_l1_data_b_start_cpu(int cpu)
+{
+        return L1_DATA_B_START;
+}
+static inline ulong get_l1_scratch_start(void)
+{
+        return get_l1_scratch_start_cpu(0);
+}
+static inline ulong get_l1_code_start(void)
+{
+        return  get_l1_code_start_cpu(0);
+}
+static inline ulong get_l1_data_a_start(void)
+{
+        return get_l1_data_a_start_cpu(0);
+}
+static inline ulong get_l1_data_b_start(void)
+{
+        return get_l1_data_b_start_cpu(0);
+}
+
+#endif /* CONFIG_SMP */
+#endif /* __ASSEMBLY__ */
+
 #endif                          /* _MEM_MAP_H_ */
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 35593dda2a4d..944e29faae48 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -37,6 +37,10 @@
 #include <asm/pgalloc.h>
 #include <asm/cplbinit.h>
 
+/* Note: L1 stacks are CPU-private things, so we bluntly disable this
+   feature in SMP mode, and use the per-CPU scratch SRAM bank only to
+   store the PDA instead. */
+
 extern void *current_l1_stack_save;
 extern int nr_l1stack_tasks;
 extern void *l1_stack_base;
@@ -88,12 +92,15 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
 static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
                              struct task_struct *tsk)
 {
+#ifdef CONFIG_MPU
+        unsigned int cpu = smp_processor_id();
+#endif
         if (prev_mm == next_mm)
                 return;
 #ifdef CONFIG_MPU
-        if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
-                flush_switched_cplbs();
-                set_mask_dcplbs(next_mm->context.page_rwx_mask);
+        if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
+                flush_switched_cplbs(cpu);
+                set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
         }
 #endif
 
@@ -138,9 +145,10 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr,
 
 static inline void update_protections(struct mm_struct *mm)
 {
-        if (mm->context.page_rwx_mask == current_rwx_mask) {
-                flush_switched_cplbs();
-                set_mask_dcplbs(mm->context.page_rwx_mask);
+        unsigned int cpu = smp_processor_id();
+        if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
+                flush_switched_cplbs(cpu);
+                set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
         }
 }
 #endif
@@ -165,6 +173,9 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 static inline void destroy_context(struct mm_struct *mm)
 {
         struct sram_list_struct *tmp;
+#ifdef CONFIG_MPU
+        unsigned int cpu = smp_processor_id();
+#endif
 
 #ifdef CONFIG_APP_STACK_L1
         if (current_l1_stack_save == mm->context.l1_stack_save)
@@ -179,8 +190,8 @@ static inline void destroy_context(struct mm_struct *mm)
                 kfree(tmp);
         }
 #ifdef CONFIG_MPU
-        if (current_rwx_mask == mm->context.page_rwx_mask)
-                current_rwx_mask = NULL;
+        if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
+                current_rwx_mask[cpu] = NULL;
         free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
 #endif
 }
diff --git a/arch/blackfin/include/asm/mutex-dec.h b/arch/blackfin/include/asm/mutex-dec.h
new file mode 100644
index 000000000000..0134151656af
--- /dev/null
+++ b/arch/blackfin/include/asm/mutex-dec.h
@@ -0,0 +1,112 @@
+/*
+ * include/asm-generic/mutex-dec.h
+ *
+ * Generic implementation of the mutex fastpath, based on atomic
+ * decrement/increment.
+ */
+#ifndef _ASM_GENERIC_MUTEX_DEC_H
+#define _ASM_GENERIC_MUTEX_DEC_H
+
+/**
+ *  __mutex_fastpath_lock - try to take the lock by moving the count
+ *                          from 1 to a 0 value
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 1
+ *
+ * Change the count from 1 to a value lower than 1, and call <fail_fn> if
+ * it wasn't 1 originally. This function MUST leave the value lower than
+ * 1 even when the "1" assertion wasn't true.
+ */
+static inline void
+__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+{
+        if (unlikely(atomic_dec_return(count) < 0))
+                fail_fn(count);
+        else
+                smp_mb();
+}
+
+/**
+ *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
+ *                                 from 1 to a 0 value
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 1
+ *
+ * Change the count from 1 to a value lower than 1, and call <fail_fn> if
+ * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
+ * or anything the slow path function returns.
+ */
+static inline int
+__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *))
+{
+        if (unlikely(atomic_dec_return(count) < 0))
+                return fail_fn(count);
+        else {
+                smp_mb();
+                return 0;
+        }
+}
+
+/**
+ *  __mutex_fastpath_unlock - try to promote the count from 0 to 1
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: function to call if the original value was not 0
+ *
+ * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
+ * In the failure case, this function is allowed to either set the value to
+ * 1, or to set it to a value lower than 1.
+ *
+ * If the implementation sets it to a value of lower than 1, then the
+ * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
+ * to return 0 otherwise.
+ */
+static inline void
+__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+{
+        smp_mb();
+        if (unlikely(atomic_inc_return(count) <= 0))
+                fail_fn(count);
+}
+
+#define __mutex_slowpath_needs_to_unlock()              1
+
+/**
+ * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
+ *
+ *  @count: pointer of type atomic_t
+ *  @fail_fn: fallback function
+ *
+ * Change the count from 1 to a value lower than 1, and return 0 (failure)
+ * if it wasn't 1 originally, or return 1 (success) otherwise. This function
+ * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
+ * Additionally, if the value was < 0 originally, this function must not leave
+ * it to 0 on failure.
+ *
+ * If the architecture has no effective trylock variant, it should call the
+ * <fail_fn> spinlock-based trylock variant unconditionally.
+ */
+static inline int
+__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        /*
+         * We have two variants here. The cmpxchg based one is the best one
+         * because it never induce a false contention state.  It is included
+         * here because architectures using the inc/dec algorithms over the
+         * xchg ones are much more likely to support cmpxchg natively.
+         *
+         * If not we fall back to the spinlock based variant - that is
+         * just as efficient (and simpler) as a 'destructive' probing of
+         * the mutex state would be.
+         */
+#ifdef __HAVE_ARCH_CMPXCHG
+        if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
+                smp_mb();
+                return 1;
+        }
+        return 0;
+#else
+        return fail_fn(count);
+#endif
+}
+
+#endif
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
index 458c1f7fbc18..5d399256bf06 100644
--- a/arch/blackfin/include/asm/mutex.h
+++ b/arch/blackfin/include/asm/mutex.h
@@ -6,4 +6,67 @@
  * implementation. (see asm-generic/mutex-xchg.h for details)
  */
 
+#ifndef _ASM_MUTEX_H
+#define _ASM_MUTEX_H
+
+#ifndef CONFIG_SMP
 #include <asm-generic/mutex-dec.h>
+#else
+
+static inline void
+__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
+{
+        if (unlikely(atomic_dec_return(count) < 0))
+                fail_fn(count);
+        else
+                smp_mb();
+}
+
+static inline int
+__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        if (unlikely(atomic_dec_return(count) < 0))
+                return fail_fn(count);
+        else {
+                smp_mb();
+                return 0;
+        }
+}
+
+static inline void
+__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
+{
+        smp_mb();
+        if (unlikely(atomic_inc_return(count) <= 0))
+                fail_fn(count);
+}
+
+#define __mutex_slowpath_needs_to_unlock()              1
+
+static inline int
+__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
+{
+        /*
+         * We have two variants here. The cmpxchg based one is the best one
+         * because it never induce a false contention state.  It is included
+         * here because architectures using the inc/dec algorithms over the
+         * xchg ones are much more likely to support cmpxchg natively.
+         *
+         * If not we fall back to the spinlock based variant - that is
+         * just as efficient (and simpler) as a 'destructive' probing of
+         * the mutex state would be.
+         */
+#ifdef __HAVE_ARCH_CMPXCHG
+        if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
+                smp_mb();
+                return 1;
+        }
+        return 0;
+#else
+        return fail_fn(count);
+#endif
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
new file mode 100644
index 000000000000..bd8d4a7efeb2
--- /dev/null
+++ b/arch/blackfin/include/asm/pda.h
@@ -0,0 +1,70 @@
+/*
+ * File:         arch/blackfin/include/asm/pda.h
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _ASM_BLACKFIN_PDA_H
+#define _ASM_BLACKFIN_PDA_H
+
+#include <mach/anomaly.h>
+
+#ifndef __ASSEMBLY__
+
+struct blackfin_pda {                   /* Per-processor Data Area */
+        struct blackfin_pda *next;
+
+        unsigned long syscfg;
+#ifdef CONFIG_SMP
+        unsigned long imask;            /* Current IMASK value */
+#endif
+
+        unsigned long *ipdt;            /* Start of switchable I-CPLB table */
+        unsigned long *ipdt_swapcount;  /* Number of swaps in ipdt */
+        unsigned long *dpdt;            /* Start of switchable D-CPLB table */
+        unsigned long *dpdt_swapcount;  /* Number of swaps in dpdt */
+
+        /*
+         * Single instructions can have multiple faults, which
+         * need to be handled by traps.c, in irq5. We store
+         * the exception cause to ensure we don't miss a
+         * double fault condition
+         */
+        unsigned long ex_iptr;
+        unsigned long ex_optr;
+        unsigned long ex_buf[4];
+        unsigned long ex_imask;         /* Saved imask from exception */
+        unsigned long *ex_stack;        /* Exception stack space */
+
+#ifdef ANOMALY_05000261
+        unsigned long last_cplb_fault_retx;
+#endif
+        unsigned long dcplb_fault_addr;
+        unsigned long icplb_fault_addr;
+        unsigned long retx;
+        unsigned long seqstat;
+};
+
+extern struct blackfin_pda cpu_pda[];
+
+void reserve_pda(void);
+
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_BLACKFIN_PDA_H */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
index 78dd61f6b39f..797c0c165069 100644
--- a/arch/blackfin/include/asm/percpu.h
+++ b/arch/blackfin/include/asm/percpu.h
@@ -3,4 +3,14 @@
 
 #include <asm-generic/percpu.h>
 
-#endif                          /* __ARCH_BLACKFIN_PERCPU__ */
+#ifdef CONFIG_MODULES
+#define PERCPU_MODULE_RESERVE 8192
+#else
+#define PERCPU_MODULE_RESERVE 0
+#endif
+
+#define PERCPU_ENOUGH_ROOM \
+        (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \
+         PERCPU_MODULE_RESERVE)
+
+#endif  /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
index f11684e4ade7..783c8f7f8f8c 100644
--- a/arch/blackfin/include/asm/pgtable.h
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -29,6 +29,7 @@ typedef pte_t *pte_addr_t;
 #define PAGE_COPY               __pgprot(0)     /* these mean nothing to NO_MM */
 #define PAGE_READONLY           __pgprot(0)     /* these mean nothing to NO_MM */
 #define PAGE_KERNEL             __pgprot(0)     /* these mean nothing to NO_MM */
+#define pgprot_noncached(prot)  (prot)
 
 extern void paging_init(void);
 
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index e3e9b41fa8db..0eece23b41c7 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -24,6 +24,14 @@ static inline void wrusp(unsigned long usp)
         __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
 }
 
+static inline unsigned long __get_SP(void)
+{
+        unsigned long sp;
+
+        __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp));
+        return sp;
+}
+
 /*
  * User space process size: 1st byte beyond user address space.
  * Fairly meaningless on nommu.  Parts of user programs can be scattered
@@ -57,6 +65,7 @@ struct thread_struct {
  * pass the data segment into user programs if it exists,
  * it can't hurt anything as far as I can tell
  */
+#ifndef CONFIG_SMP
 #define start_thread(_regs, _pc, _usp)                                  \
 do {                                                                    \
         set_fs(USER_DS);                                                \
@@ -70,6 +79,16 @@ do {									\
                 sizeof(*L1_SCRATCH_TASK_INFO));                         \
         wrusp(_usp);                                                    \
 } while(0)
+#else
+#define start_thread(_regs, _pc, _usp)                                  \
+do {                                                                    \
+        set_fs(USER_DS);                                                \
+        (_regs)->pc = (_pc);                                            \
+        if (current->mm)                                                \
+                (_regs)->p5 = current->mm->start_data;                  \
+        wrusp(_usp);                                                    \
+} while (0)
+#endif
 
 /* Forward declaration, a strange C thing */
 struct task_struct;
@@ -106,7 +125,8 @@ unsigned long get_wchan(struct task_struct *p);
         eip; })
 #define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
 
-#define cpu_relax()     barrier()
+#define cpu_relax()     smp_mb()
+
 
 /* Get the Silicon Revision of the chip */
 static inline uint32_t __pure bfin_revid(void)
@@ -137,7 +157,11 @@ static inline uint32_t __pure bfin_revid(void)
 static inline uint16_t __pure bfin_cpuid(void)
 {
         return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
+}
 
+static inline uint32_t __pure bfin_dspid(void)
+{
+        return bfin_read_DSPID();
 }
 
 static inline uint32_t __pure bfin_compiled_revid(void)
@@ -154,6 +178,8 @@ static inline uint32_t __pure bfin_compiled_revid(void)
         return 4;
 #elif defined(CONFIG_BF_REV_0_5)
         return 5;
+#elif defined(CONFIG_BF_REV_0_6)
+        return 6;
 #elif defined(CONFIG_BF_REV_ANY)
         return 0xffff;
 #else
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
index 6d448b5f5985..4856d62b7467 100644
--- a/arch/blackfin/include/asm/reboot.h
+++ b/arch/blackfin/include/asm/reboot.h
@@ -1,7 +1,7 @@
 /*
- * include/asm-blackfin/reboot.h - shutdown/reboot header
+ * reboot.h - shutdown/reboot header
  *
- * Copyright 2004-2007 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h
new file mode 100644
index 000000000000..4a724b378971
--- /dev/null
+++ b/arch/blackfin/include/asm/rwlock.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_BLACKFIN_RWLOCK_H
+#define _ASM_BLACKFIN_RWLOCK_H
+
+#define RW_LOCK_BIAS    0x01000000
+
+#endif
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
index 994dd869558c..3a47606c858b 100644
--- a/arch/blackfin/include/asm/serial.h
+++ b/arch/blackfin/include/asm/serial.h
@@ -3,3 +3,4 @@
  */
 
 #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
+#define BASE_BAUD (1843200 / 16)
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
new file mode 100644
index 000000000000..118deeeae7c0
--- /dev/null
+++ b/arch/blackfin/include/asm/smp.h
@@ -0,0 +1,44 @@
+/*
+ * File:         arch/blackfin/include/asm/smp.h
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_BLACKFIN_SMP_H
+#define __ASM_BLACKFIN_SMP_H
+
+#include <linux/kernel.h>
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/cache.h>
+#include <asm/blackfin.h>
+#include <mach/smp.h>
+
+#define raw_smp_processor_id()  blackfin_core_id()
+
+extern char coreb_trampoline_start, coreb_trampoline_end;
+
+struct corelock_slot {
+        int lock;
+};
+
+void smp_icache_flush_range_others(unsigned long start,
+                                   unsigned long end);
+
+#endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 64e908a50646..0249ac319476 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -1,6 +1,89 @@
 #ifndef __BFIN_SPINLOCK_H
 #define __BFIN_SPINLOCK_H
 
-#error blackfin architecture does not support SMP spin lock yet
+#include <asm/atomic.h>
 
-#endif
+asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
+asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
+asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_read_lock_asm(volatile int *ptr);
+asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_write_lock_asm(volatile int *ptr);
+asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
+
+static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+{
+        return __raw_spin_is_locked_asm(&lock->lock);
+}
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        __raw_spin_lock_asm(&lock->lock);
+}
+
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        return __raw_spin_trylock_asm(&lock->lock);
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        __raw_spin_unlock_asm(&lock->lock);
+}
+
+static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+{
+        while (__raw_spin_is_locked(lock))
+                cpu_relax();
+}
+
+static inline int __raw_read_can_lock(raw_rwlock_t *rw)
+{
+        return __raw_uncached_fetch_asm(&rw->lock) > 0;
+}
+
+static inline int __raw_write_can_lock(raw_rwlock_t *rw)
+{
+        return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS;
+}
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        __raw_read_lock_asm(&rw->lock);
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        return __raw_read_trylock_asm(&rw->lock);
+}
+
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        __raw_read_unlock_asm(&rw->lock);
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        __raw_write_lock_asm(&rw->lock);
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        return __raw_write_trylock_asm(&rw->lock);
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        __raw_write_unlock_asm(&rw->lock);
+}
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /*  !__BFIN_SPINLOCK_H */
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..b1e3c4c7b382
--- /dev/null
+++ b/arch/blackfin/include/asm/spinlock_types.h
@@ -0,0 +1,22 @@
+#ifndef __ASM_SPINLOCK_TYPES_H
+#define __ASM_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+#include <asm/rwlock.h>
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+
+#endif
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 8f1627d8bf09..a4c8254bec55 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -37,114 +37,98 @@
 #include <linux/linkage.h>
 #include <linux/compiler.h>
 #include <mach/anomaly.h>
+#include <asm/pda.h>
+#include <asm/processor.h>
+#include <asm/irq.h>
 
 /*
- * Interrupt configuring macros.
+ * Force strict CPU ordering.
  */
+#define nop()  __asm__ __volatile__ ("nop;\n\t" : : )
+#define mb()   __asm__ __volatile__ (""   : : : "memory")
+#define rmb()  __asm__ __volatile__ (""   : : : "memory")
+#define wmb()  __asm__ __volatile__ (""   : : : "memory")
+#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
+#define read_barrier_depends()          do { } while(0)
 
-extern unsigned long irq_flags;
-
-#define local_irq_enable() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#define local_irq_disable() \
-        do { \
-                int __tmp_dummy; \
-                __asm__ __volatile__( \
-                        "cli %0;" \
-                        : "=d" (__tmp_dummy) \
-                ); \
-        } while (0)
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000244 \
-                ".align 8;" \
-                "sti %0;" \
-                "idle;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#ifdef CONFIG_DEBUG_HWERR
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %1;" \
-                : "=&d" (x) \
-                : "d" (0x3F) \
-        )
-#else
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                : "=&d" (x) \
-        )
-#endif
-
-#define local_save_flags(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %0;" \
-                : "=d" (x) \
-        )
+#ifdef CONFIG_SMP
+asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+
+#ifdef __ARCH_SYNC_CORE_DCACHE
+# define smp_mb()       do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
+# define smp_rmb()      do { barrier(); smp_check_barrier(); } while (0)
+# define smp_wmb()      do { barrier(); smp_mark_barrier(); } while (0)
+#define smp_read_barrier_depends()      do { barrier(); smp_check_barrier(); } while (0)
 
-#ifdef CONFIG_DEBUG_HWERR
-#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
 #else
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+# define smp_mb()       barrier()
+# define smp_rmb()      barrier()
+# define smp_wmb()      barrier()
+#define smp_read_barrier_depends()      barrier()
 #endif
 
-#define local_irq_restore(x) \
-        do { \
-                if (irqs_enabled_from_flags(x)) \
-                        local_irq_enable(); \
-        } while (0)
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                   int size)
+{
+        unsigned long tmp;
 
-/* For spinlocks etc */
-#define local_irq_save(x) __save_and_cli(x)
+        switch (size) {
+        case 1:
+                tmp = __raw_xchg_1_asm(ptr, x);
+                break;
+        case 2:
+                tmp = __raw_xchg_2_asm(ptr, x);
+                break;
+        case 4:
+                tmp = __raw_xchg_4_asm(ptr, x);
+                break;
+        }
 
-#define irqs_disabled()                         \
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !irqs_enabled_from_flags(flags);        \
-})
+        return tmp;
+}
 
 /*
- * Force strict CPU ordering.
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
  */
-#define nop()  asm volatile ("nop;\n\t"::)
-#define mb()   asm volatile (""   : : :"memory")
-#define rmb()  asm volatile (""   : : :"memory")
-#define wmb()  asm volatile (""   : : :"memory")
-#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        unsigned long tmp;
 
-#define read_barrier_depends()          do { } while(0)
+        switch (size) {
+        case 1:
+                tmp = __raw_cmpxchg_1_asm(ptr, new, old);
+                break;
+        case 2:
+                tmp = __raw_cmpxchg_2_asm(ptr, new, old);
+                break;
+        case 4:
+                tmp = __raw_cmpxchg_4_asm(ptr, new, old);
+                break;
+        }
+
+        return tmp;
+}
+#define cmpxchg(ptr, o, n) \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
+                (unsigned long)(n), sizeof(*(ptr))))
+
+#else /* !CONFIG_SMP */
 
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
 #define smp_mb()        barrier()
 #define smp_rmb()       barrier()
 #define smp_wmb()       barrier()
 #define smp_read_barrier_depends()      do { } while(0)
-#endif
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
 struct __xchg_dummy {
         unsigned long a[100];
@@ -157,7 +141,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
         unsigned long tmp = 0;
         unsigned long flags = 0;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         switch (size) {
         case 1:
@@ -179,7 +163,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
                          : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
                 break;
         }
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
         return tmp;
 }
 
@@ -194,9 +178,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
                         (unsigned long)(n), sizeof(*(ptr))))
 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 
-#ifndef CONFIG_SMP
 #include <asm-generic/cmpxchg.h>
-#endif
+
+#endif /* !CONFIG_SMP */
+
+#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
+#define tas(ptr) ((void)xchg((ptr), 1))
 
 #define prepare_to_switch()     do { } while(0)
 
@@ -205,10 +192,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
  * ptr isn't the current task, in which case it does nothing.
  */
 
-#include <asm/blackfin.h>
+#include <asm/l1layout.h>
+#include <asm/mem_map.h>
 
 asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
 
+#ifndef CONFIG_SMP
 #define switch_to(prev,next,last) \
 do {    \
         memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
@@ -217,5 +206,11 @@ do {    \
                 sizeof *L1_SCRATCH_TASK_INFO); \
         (last) = resume (prev, next);   \
 } while (0)
+#else
+#define switch_to(prev, next, last) \
+do {    \
+        (last) = resume(prev, next);   \
+} while (0)
+#endif
 
-#endif                          /* _BLACKFIN_SYSTEM_H */
+#endif  /* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index 642769329d12..e721ce55956c 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -44,6 +44,7 @@
  */
 #define THREAD_SIZE_ORDER       1
 #define THREAD_SIZE             8192    /* 2 pages */
+#define STACK_WARN              (THREAD_SIZE/8)
 
 #ifndef __ASSEMBLY__
 
@@ -62,7 +63,9 @@ struct thread_info {
         int preempt_count;      /* 0 => preemptable, <0 => BUG */
         mm_segment_t addr_limit;        /* address limit */
         struct restart_block restart_block;
+#ifndef CONFIG_SMP
         struct l1_scratch_task_info l1_task_info;
+#endif
 };
 
 /*
@@ -90,7 +93,7 @@ __attribute_const__
 static inline struct thread_info *current_thread_info(void)
 {
         struct thread_info *ti;
-      __asm__("%0 = sp;": "=&d"(ti):
+      __asm__("%0 = sp;" : "=da"(ti) :
         );
         return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
 }
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index d928b8099056..3248033531e6 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -149,54 +149,42 @@ static inline int bad_user_access_length(void)
                  : /* no outputs */                     \
                  :"d" (x),"a" (__ptr(p)) : "memory")
 
-#define get_user(x,p)                                                   \
-        ({                                                              \
-                int _err = 0;                                           \
-                typeof(*(p)) *_p = (p);                                 \
-                if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) {       \
-                        _err = -EFAULT;                                 \
-                }                                                       \
-                else {                                                  \
-                switch (sizeof(*(_p))) {                                \
-                case 1:                                                 \
-                        __get_user_asm(x, _p, B,(Z));                   \
-                        break;                                          \
-                case 2:                                                 \
-                        __get_user_asm(x, _p, W,(Z));                   \
-                        break;                                          \
-                case 4:                                                 \
-                        __get_user_asm(x, _p,  , );                     \
-                        break;                                          \
-                case 8: {                                               \
-                        unsigned long _xl, _xh;                         \
-                        __get_user_asm(_xl, ((unsigned long *)_p)+0,  , ); \
-                        __get_user_asm(_xh, ((unsigned long *)_p)+1,  , ); \
-                        ((unsigned long *)&x)[0] = _xl;                 \
-                        ((unsigned long *)&x)[1] = _xh;                 \
-                } break;                                                \
-                default:                                                \
-                        x = 0;                                          \
-                        printk(KERN_INFO "get_user_bad: %s:%d %s\n",    \
-                               __FILE__, __LINE__, __func__);   \
-                        _err = __get_user_bad();                        \
-                        break;                                          \
-                }                                                       \
-                }                                                       \
-                _err;                                                   \
-        })
+#define get_user(x, ptr)                                        \
+({                                                              \
+        int _err = 0;                                           \
+        unsigned long _val = 0;                                 \
+        const typeof(*(ptr)) __user *_p = (ptr);                \
+        const size_t ptr_size = sizeof(*(_p));                  \
+        if (likely(access_ok(VERIFY_READ, _p, ptr_size))) {     \
+                BUILD_BUG_ON(ptr_size >= 8);                    \
+                switch (ptr_size) {                             \
+                case 1:                                         \
+                        __get_user_asm(_val, _p, B,(Z));        \
+                        break;                                  \
+                case 2:                                         \
+                        __get_user_asm(_val, _p, W,(Z));        \
+                        break;                                  \
+                case 4:                                         \
+                        __get_user_asm(_val, _p,  , );          \
+                        break;                                  \
+                }                                               \
+        } else                                                  \
+                _err = -EFAULT;                                 \
+        x = (typeof(*(ptr)))_val;                               \
+        _err;                                                   \
+})
 
 #define __get_user(x,p) get_user(x,p)
 
 #define __get_user_bad() (bad_user_access_length(), (-EFAULT))
 
-#define __get_user_asm(x,p,bhw,option)                          \
-        {                                                       \
-                unsigned long _tmp;                             \
-                __asm__ ("%0 =" #bhw "[%1]"#option";\n\t"       \
-                         : "=d" (_tmp)                          \
-                         : "a" (__ptr(p)));                     \
-                (x) = (__typeof__(*(p))) _tmp;                  \
-        }
+#define __get_user_asm(x, ptr, bhw, option)     \
+({                                              \
+        __asm__ __volatile__ (                  \
+                "%0 =" #bhw "[%1]" #option ";"  \
+                : "=d" (x)                      \
+                : "a" (__ptr(ptr)));            \
+})
 
 #define __copy_from_user(to, from, n) copy_from_user(to, from, n)
 #define __copy_to_user(to, from, n) copy_to_user(to, from, n)
@@ -209,8 +197,8 @@ static inline int bad_user_access_length(void)
 #define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
                                                    return retval; })
 
-static inline long copy_from_user(void *to,
-                                  const void __user * from, unsigned long n)
+static inline unsigned long __must_check
+copy_from_user(void *to, const void __user *from, unsigned long n)
 {
         if (access_ok(VERIFY_READ, from, n))
                 memcpy(to, from, n);
@@ -219,8 +207,8 @@ static inline long copy_from_user(void *to,
         return 0;
 }
 
-static inline long copy_to_user(void *to,
-                                const void __user * from, unsigned long n)
+static inline unsigned long __must_check
+copy_to_user(void *to, const void __user *from, unsigned long n)
 {
         if (access_ok(VERIFY_WRITE, to, n))
                 memcpy(to, from, n);
@@ -233,8 +221,8 @@ static inline long copy_to_user(void *to,
  * Copy a null terminated string from userspace.
  */
 
-static inline long strncpy_from_user(char *dst,
-                                     const char *src, long count)
+static inline long __must_check
+strncpy_from_user(char *dst, const char *src, long count)
 {
         char *tmp;
         if (!access_ok(VERIFY_READ, src, 1))
@@ -260,7 +248,8 @@ static inline long strnlen_user(const char *src, long n)
  * Zero Userspace
  */
 
-static inline unsigned long __clear_user(void *to, unsigned long n)
+static inline unsigned long __must_check
+__clear_user(void *to, unsigned long n)
 {
         memset(to, 0, n);
         return 0;
diff --git a/arch/blackfin/include/asm/xor.h b/arch/blackfin/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/blackfin/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 606adc78aa85..38a233374f07 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds
 obj-y := \
         entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
         sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
-        fixed_code.o reboot.o bfin_gpio.o
+        fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o
 
 ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
     obj-y += time-ts.o
@@ -15,8 +15,11 @@ else
     obj-y += time.o
 endif
 
+obj-$(CONFIG_IPIPE)                  += ipipe.o
+obj-$(CONFIG_IPIPE_TRACE_MCOUNT)     += mcount.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
+obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
 obj-$(CONFIG_MODULES)                += module.o
-obj-$(CONFIG_BFIN_DMA_5XX)           += bfin_dma_5xx.o
 obj-$(CONFIG_KGDB)                   += kgdb.o
+obj-$(CONFIG_KGDB_TESTCASE)          += kgdb_test.o
 obj-$(CONFIG_EARLY_PRINTK)           += early_printk.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index 9bb85dd5ccb3..b5df9459d6d5 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -56,6 +56,9 @@ int main(void)
         /* offsets into the thread struct */
         DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
         DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
+        DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat));
+        DEFINE(PT_SR, offsetof(struct thread_struct, seqstat));
+        DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
         DEFINE(THREAD_PC, offsetof(struct thread_struct, pc));
         DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
 
@@ -128,5 +131,31 @@ int main(void)
         DEFINE(SIGSEGV, SIGSEGV);
         DEFINE(SIGTRAP, SIGTRAP);
 
+        /* PDA management (in L1 scratchpad) */
+        DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg));
+#ifdef CONFIG_SMP
+        DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask));
+#endif
+        DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt));
+        DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount));
+        DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt));
+        DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount));
+        DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr));
+        DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr));
+        DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf));
+        DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask));
+        DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack));
+#ifdef ANOMALY_05000261
+        DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx));
+#endif
+        DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr));
+        DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr));
+        DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx));
+        DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat));
+#ifdef CONFIG_SMP
+        /* Inter-core lock (in L2 SRAM) */
+        DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
+#endif
+
         return 0;
 }
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 339293d677cc..07e02c0d1c07 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -1,63 +1,27 @@
 /*
- * File:         arch/blackfin/kernel/bfin_dma_5xx.c
- * Based on:
- * Author:
+ * bfin_dma_5xx.c - Blackfin DMA implementation
  *
- * Created:
- * Description:  This file contains the simple DMA Implementation for Blackfin
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/param.h>
+#include <linux/proc_fs.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
 
 #include <asm/blackfin.h>
-#include <asm/dma.h>
 #include <asm/cacheflush.h>
+#include <asm/dma.h>
+#include <asm/uaccess.h>
 
-/* Remove unused code not exported by symbol or internally called */
-#define REMOVE_DEAD_CODE
-
-/**************************************************************************
- * Global Variables
-***************************************************************************/
-
-static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
-
-/*------------------------------------------------------------------------------
- *       Set the Buffer Clear bit in the Configuration register of specific DMA
- *       channel. This will stop the descriptor based DMA operation.
- *-----------------------------------------------------------------------------*/
-static void clear_dma_buffer(unsigned int channel)
-{
-        dma_ch[channel].regs->cfg |= RESTART;
-        SSYNC();
-        dma_ch[channel].regs->cfg &= ~RESTART;
-        SSYNC();
-}
+struct dma_channel dma_ch[MAX_DMA_CHANNELS];
+EXPORT_SYMBOL(dma_ch);
 
 static int __init blackfin_dma_init(void)
 {
@@ -65,32 +29,67 @@ static int __init blackfin_dma_init(void)
 
         printk(KERN_INFO "Blackfin DMA Controller\n");
 
-        for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
+        for (i = 0; i < MAX_DMA_CHANNELS; i++) {
                 dma_ch[i].chan_status = DMA_CHANNEL_FREE;
                 dma_ch[i].regs = dma_io_base_addr[i];
                 mutex_init(&(dma_ch[i].dmalock));
         }
         /* Mark MEMDMA Channel 0 as requested since we're using it internally */
-        dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
-        dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
+        request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
+        request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
 
 #if defined(CONFIG_DEB_DMA_URGENT)
         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
                          | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
 #endif
+
         return 0;
 }
-
 arch_initcall(blackfin_dma_init);
 
-/*------------------------------------------------------------------------------
- *      Request the specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-int request_dma(unsigned int channel, char *device_id)
+#ifdef CONFIG_PROC_FS
+static int proc_dma_show(struct seq_file *m, void *v)
 {
+        int i;
+
+        for (i = 0; i < MAX_DMA_CHANNELS; ++i)
+                if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
+                        seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
+
+        return 0;
+}
 
+static int proc_dma_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, proc_dma_show, NULL);
+}
+
+static const struct file_operations proc_dma_operations = {
+        .open           = proc_dma_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init proc_dma_init(void)
+{
+        return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL;
+}
+late_initcall(proc_dma_init);
+#endif
+
+/**
+ *      request_dma - request a DMA channel
+ *
+ * Request the specific DMA channel from the system if it's available.
+ */
+int request_dma(unsigned int channel, const char *device_id)
+{
         pr_debug("request_dma() : BEGIN \n");
 
+        if (device_id == NULL)
+                printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
+
 #if defined(CONFIG_BF561) && ANOMALY_05000182
         if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
                 if (get_cclk() > 500000000) {
@@ -129,60 +128,63 @@ int request_dma(unsigned int channel, char *device_id)
 #endif
 
         dma_ch[channel].device_id = device_id;
-        dma_ch[channel].irq_callback = NULL;
+        dma_ch[channel].irq = 0;
 
         /* This is to be enabled by putting a restriction -
          * you have to request DMA, before doing any operations on
          * descriptor/channel
          */
         pr_debug("request_dma() : END  \n");
-        return channel;
+        return 0;
 }
 EXPORT_SYMBOL(request_dma);
 
-int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
+int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
 {
-        int ret_irq = 0;
-
         BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
+               && channel < MAX_DMA_CHANNELS));
 
         if (callback != NULL) {
-                int ret_val;
-                ret_irq = channel2irq(channel);
+                int ret;
+                unsigned int irq = channel2irq(channel);
 
-                dma_ch[channel].data = data;
+                ret = request_irq(irq, callback, IRQF_DISABLED,
+                        dma_ch[channel].device_id, data);
+                if (ret)
+                        return ret;
 
-                ret_val =
-                    request_irq(ret_irq, (void *)callback, IRQF_DISABLED,
-                                dma_ch[channel].device_id, data);
-                if (ret_val) {
-                        printk(KERN_NOTICE
-                               "Request irq in DMA engine failed.\n");
-                        return -EPERM;
-                }
-                dma_ch[channel].irq_callback = callback;
+                dma_ch[channel].irq = irq;
+                dma_ch[channel].data = data;
         }
         return 0;
 }
 EXPORT_SYMBOL(set_dma_callback);
 
-void free_dma(unsigned int channel)
+/**
+ *      clear_dma_buffer - clear DMA fifos for specified channel
+ *
+ * Set the Buffer Clear bit in the Configuration register of specific DMA
+ * channel. This will stop the descriptor based DMA operation.
+ */
+static void clear_dma_buffer(unsigned int channel)
 {
-        int ret_irq;
+        dma_ch[channel].regs->cfg |= RESTART;
+        SSYNC();
+        dma_ch[channel].regs->cfg &= ~RESTART;
+}
 
+void free_dma(unsigned int channel)
+{
         pr_debug("freedma() : BEGIN \n");
         BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
+               && channel < MAX_DMA_CHANNELS));
 
         /* Halt the DMA */
         disable_dma(channel);
         clear_dma_buffer(channel);
 
-        if (dma_ch[channel].irq_callback != NULL) {
-                ret_irq = channel2irq(channel);
-                free_irq(ret_irq, dma_ch[channel].data);
-        }
+        if (dma_ch[channel].irq)
+                free_irq(dma_ch[channel].irq, dma_ch[channel].data);
 
         /* Clear the DMA Variable in the Channel */
         mutex_lock(&(dma_ch[channel].dmalock));
@@ -193,294 +195,15 @@ void free_dma(unsigned int channel)
 }
 EXPORT_SYMBOL(free_dma);
 
-void dma_enable_irq(unsigned int channel)
-{
-        int ret_irq;
-
-        pr_debug("dma_enable_irq() : BEGIN \n");
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        ret_irq = channel2irq(channel);
-        enable_irq(ret_irq);
-}
-EXPORT_SYMBOL(dma_enable_irq);
-
-void dma_disable_irq(unsigned int channel)
-{
-        int ret_irq;
-
-        pr_debug("dma_disable_irq() : BEGIN \n");
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        ret_irq = channel2irq(channel);
-        disable_irq(ret_irq);
-}
-EXPORT_SYMBOL(dma_disable_irq);
-
-int dma_channel_active(unsigned int channel)
-{
-        if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
-                return 0;
-        } else {
-                return 1;
-        }
-}
-EXPORT_SYMBOL(dma_channel_active);
-
-/*------------------------------------------------------------------------------
-*       stop the specific DMA channel.
-*-----------------------------------------------------------------------------*/
-void disable_dma(unsigned int channel)
-{
-        pr_debug("stop_dma() : BEGIN \n");
-
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->cfg &= ~DMAEN;    /* Clean the enable bit */
-        SSYNC();
-        dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
-        /* Needs to be enabled Later */
-        pr_debug("stop_dma() : END \n");
-        return;
-}
-EXPORT_SYMBOL(disable_dma);
-
-void enable_dma(unsigned int channel)
-{
-        pr_debug("enable_dma() : BEGIN \n");
-
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
-        dma_ch[channel].regs->curr_x_count = 0;
-        dma_ch[channel].regs->curr_y_count = 0;
-
-        dma_ch[channel].regs->cfg |= DMAEN;     /* Set the enable bit */
-        SSYNC();
-        pr_debug("enable_dma() : END \n");
-        return;
-}
-EXPORT_SYMBOL(enable_dma);
-
-/*------------------------------------------------------------------------------
-*               Set the Start Address register for the specific DMA channel
-*               This function can be used for register based DMA,
-*               to setup the start address
-*               addr:           Starting address of the DMA Data to be transferred.
-*-----------------------------------------------------------------------------*/
-void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
-        pr_debug("set_dma_start_addr() : BEGIN \n");
-
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->start_addr = addr;
-        SSYNC();
-        pr_debug("set_dma_start_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_start_addr);
-
-void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
-{
-        pr_debug("set_dma_next_desc_addr() : BEGIN \n");
-
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->next_desc_ptr = addr;
-        SSYNC();
-        pr_debug("set_dma_next_desc_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_next_desc_addr);
-
-void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
-{
-        pr_debug("set_dma_curr_desc_addr() : BEGIN \n");
-
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->curr_desc_ptr = addr;
-        SSYNC();
-        pr_debug("set_dma_curr_desc_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_curr_desc_addr);
-
-void set_dma_x_count(unsigned int channel, unsigned short x_count)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->x_count = x_count;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_x_count);
-
-void set_dma_y_count(unsigned int channel, unsigned short y_count)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->y_count = y_count;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_y_count);
-
-void set_dma_x_modify(unsigned int channel, short x_modify)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->x_modify = x_modify;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_x_modify);
-
-void set_dma_y_modify(unsigned int channel, short y_modify)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->y_modify = y_modify;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_y_modify);
-
-void set_dma_config(unsigned int channel, unsigned short config)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->cfg = config;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_config);
-
-unsigned short
-set_bfin_dma_config(char direction, char flow_mode,
-                    char intr_mode, char dma_mode, char width, char syncmode)
-{
-        unsigned short config;
-
-        config =
-            ((direction << 1) | (width << 2) | (dma_mode << 4) |
-             (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5));
-        return config;
-}
-EXPORT_SYMBOL(set_bfin_dma_config);
-
-void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
-
-        dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
-
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_sg);
-
-void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        dma_ch[channel].regs->curr_addr_ptr = addr;
-        SSYNC();
-}
-EXPORT_SYMBOL(set_dma_curr_addr);
-
-/*------------------------------------------------------------------------------
- *      Get the DMA status of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_irqstat(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->irq_status;
-}
-EXPORT_SYMBOL(get_dma_curr_irqstat);
-
-/*------------------------------------------------------------------------------
- *      Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
- *-----------------------------------------------------------------------------*/
-void clear_dma_irqstat(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-        dma_ch[channel].regs->irq_status |= 3;
-}
-EXPORT_SYMBOL(clear_dma_irqstat);
-
-/*------------------------------------------------------------------------------
- *      Get current DMA xcount of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_xcount(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->curr_x_count;
-}
-EXPORT_SYMBOL(get_dma_curr_xcount);
-
-/*------------------------------------------------------------------------------
- *      Get current DMA ycount of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_ycount(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-               && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->curr_y_count;
-}
-EXPORT_SYMBOL(get_dma_curr_ycount);
-
-unsigned long get_dma_next_desc_ptr(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-              && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->next_desc_ptr;
-}
-EXPORT_SYMBOL(get_dma_next_desc_ptr);
-
-unsigned long get_dma_curr_desc_ptr(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-              && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->curr_desc_ptr;
-}
-EXPORT_SYMBOL(get_dma_curr_desc_ptr);
-
-unsigned long get_dma_curr_addr(unsigned int channel)
-{
-        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
-              && channel < MAX_BLACKFIN_DMA_CHANNEL));
-
-        return dma_ch[channel].regs->curr_addr_ptr;
-}
-EXPORT_SYMBOL(get_dma_curr_addr);
-
 #ifdef CONFIG_PM
+# ifndef MAX_DMA_SUSPEND_CHANNELS
+#  define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
+# endif
 int blackfin_dma_suspend(void)
 {
         int i;
 
-#ifdef CONFIG_BF561     /* IMDMA channels doesn't have a PERIPHERAL_MAP */
-        for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) {
-#else
-        for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
-#endif
+        for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) {
                 if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
                         printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
                         return -EBUSY;
@@ -495,388 +218,201 @@ int blackfin_dma_suspend(void)
 void blackfin_dma_resume(void)
 {
         int i;
-
-#ifdef CONFIG_BF561     /* IMDMA channels doesn't have a PERIPHERAL_MAP */
-        for (i = 0; i <= CH_MEM_STREAM3_SRC; i++)
-#else
-        for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++)
-#endif
+        for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i)
                 dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
 }
 #endif
 
-static void *__dma_memcpy(void *dest, const void *src, size_t size)
+/**
+ *      blackfin_dma_early_init - minimal DMA init
+ *
+ * Setup a few DMA registers so we can safely do DMA transfers early on in
+ * the kernel booting process.  Really this just means using dma_memcpy().
+ */
+void __init blackfin_dma_early_init(void)
 {
-        int direction;  /* 1 - address decrease, 0 - address increase */
-        int flag_align; /* 1 - address aligned,  0 - address unaligned */
-        int flag_2D;    /* 1 - 2D DMA needed,    0 - 1D DMA needed */
-        unsigned long flags;
-
-        if (size <= 0)
-                return NULL;
-
-        local_irq_save(flags);
-
-        if ((unsigned long)src < memory_end)
-                blackfin_dcache_flush_range((unsigned int)src,
-                                            (unsigned int)(src + size));
-
-        if ((unsigned long)dest < memory_end)
-                blackfin_dcache_invalidate_range((unsigned int)dest,
-                                                 (unsigned int)(dest + size));
-
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        if ((unsigned long)src < (unsigned long)dest)
-                direction = 1;
-        else
-                direction = 0;
-
-        if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0)
-            && ((size % 2) == 0))
-                flag_align = 1;
-        else
-                flag_align = 0;
-
-        if (size > 0x10000)     /* size > 64K */
-                flag_2D = 1;
-        else
-                flag_2D = 0;
-
-        /* Setup destination and source start address */
-        if (direction) {
-                if (flag_align) {
-                        bfin_write_MDMA_D0_START_ADDR(dest + size - 2);
-                        bfin_write_MDMA_S0_START_ADDR(src + size - 2);
-                } else {
-                        bfin_write_MDMA_D0_START_ADDR(dest + size - 1);
-                        bfin_write_MDMA_S0_START_ADDR(src + size - 1);
-                }
-        } else {
-                bfin_write_MDMA_D0_START_ADDR(dest);
-                bfin_write_MDMA_S0_START_ADDR(src);
-        }
-
-        /* Setup destination and source xcount */
-        if (flag_2D) {
-                if (flag_align) {
-                        bfin_write_MDMA_D0_X_COUNT(1024 / 2);
-                        bfin_write_MDMA_S0_X_COUNT(1024 / 2);
-                } else {
-                        bfin_write_MDMA_D0_X_COUNT(1024);
-                        bfin_write_MDMA_S0_X_COUNT(1024);
-                }
-                bfin_write_MDMA_D0_Y_COUNT(size >> 10);
-                bfin_write_MDMA_S0_Y_COUNT(size >> 10);
-        } else {
-                if (flag_align) {
-                        bfin_write_MDMA_D0_X_COUNT(size / 2);
-                        bfin_write_MDMA_S0_X_COUNT(size / 2);
-                } else {
-                        bfin_write_MDMA_D0_X_COUNT(size);
-                        bfin_write_MDMA_S0_X_COUNT(size);
-                }
-        }
-
-        /* Setup destination and source xmodify and ymodify */
-        if (direction) {
-                if (flag_align) {
-                        bfin_write_MDMA_D0_X_MODIFY(-2);
-                        bfin_write_MDMA_S0_X_MODIFY(-2);
-                        if (flag_2D) {
-                                bfin_write_MDMA_D0_Y_MODIFY(-2);
-                                bfin_write_MDMA_S0_Y_MODIFY(-2);
-                        }
-                } else {
-                        bfin_write_MDMA_D0_X_MODIFY(-1);
-                        bfin_write_MDMA_S0_X_MODIFY(-1);
-                        if (flag_2D) {
-                                bfin_write_MDMA_D0_Y_MODIFY(-1);
-                                bfin_write_MDMA_S0_Y_MODIFY(-1);
-                        }
-                }
-        } else {
-                if (flag_align) {
-                        bfin_write_MDMA_D0_X_MODIFY(2);
-                        bfin_write_MDMA_S0_X_MODIFY(2);
-                        if (flag_2D) {
-                                bfin_write_MDMA_D0_Y_MODIFY(2);
-                                bfin_write_MDMA_S0_Y_MODIFY(2);
-                        }
-                } else {
-                        bfin_write_MDMA_D0_X_MODIFY(1);
-                        bfin_write_MDMA_S0_X_MODIFY(1);
-                        if (flag_2D) {
-                                bfin_write_MDMA_D0_Y_MODIFY(1);
-                                bfin_write_MDMA_S0_Y_MODIFY(1);
-                        }
-                }
-        }
-
-        /* Enable source DMA */
-        if (flag_2D) {
-                if (flag_align) {
-                        bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
-                        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
-                } else {
-                        bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
-                        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
-                }
-        } else {
-                if (flag_align) {
-                        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
-                        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
-                } else {
-                        bfin_write_MDMA_S0_CONFIG(DMAEN);
-                        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
-                }
-        }
-
-        SSYNC();
-
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
-                ;
-
-        bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() |
-                                      (DMA_DONE | DMA_ERR));
-
         bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-
-        local_irq_restore(flags);
-
-        return dest;
 }
 
-void *dma_memcpy(void *dest, const void *src, size_t size)
-{
-        size_t bulk;
-        size_t rest;
-        void * addr;
-
-        bulk = (size >> 16) << 16;
-        rest = size - bulk;
-        if (bulk)
-                __dma_memcpy(dest, src, bulk);
-        addr = __dma_memcpy(dest+bulk, src+bulk, rest);
-        return addr;
-}
-EXPORT_SYMBOL(dma_memcpy);
-
-void *safe_dma_memcpy(void *dest, const void *src, size_t size)
-{
-        void *addr;
-        addr = dma_memcpy(dest, src, size);
-        return addr;
-}
-EXPORT_SYMBOL(safe_dma_memcpy);
-
-void dma_outsb(unsigned long addr, const void *buf, unsigned short len)
+/**
+ *      __dma_memcpy - program the MDMA registers
+ *
+ * Actually program MDMA0 and wait for the transfer to finish.  Disable IRQs
+ * while programming registers so that everything is fully configured.  Wait
+ * for DMA to finish with IRQs enabled.  If interrupted, the initial DMA_DONE
+ * check will make sure we don't clobber any existing transfer.
+ */
+static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
 {
+        static DEFINE_SPINLOCK(mdma_lock);
         unsigned long flags;
 
-        local_irq_save(flags);
-
-        blackfin_dcache_flush_range((unsigned int)buf,
-                         (unsigned int)(buf) + len);
+        spin_lock_irqsave(&mdma_lock, flags);
+
+        if (bfin_read_MDMA_S0_CONFIG())
+                while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+                        continue;
+
+        if (conf & DMA2D) {
+                /* For larger bit sizes, we've already divided down cnt so it
+                 * is no longer a multiple of 64k.  So we have to break down
+                 * the limit here so it is a multiple of the incoming size.
+                 * There is no limitation here in terms of total size other
+                 * than the hardware though as the bits lost in the shift are
+                 * made up by MODIFY (== we can hit the whole address space).
+                 * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
+                 */
+                u32 shift = abs(dmod) >> 1;
+                size_t ycnt = cnt >> (16 - shift);
+                cnt = 1 << (16 - shift);
+                bfin_write_MDMA_D0_Y_COUNT(ycnt);
+                bfin_write_MDMA_S0_Y_COUNT(ycnt);
+                bfin_write_MDMA_D0_Y_MODIFY(dmod);
+                bfin_write_MDMA_S0_Y_MODIFY(smod);
+        }
 
-        bfin_write_MDMA_D0_START_ADDR(addr);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(0);
+        bfin_write_MDMA_D0_START_ADDR(daddr);
+        bfin_write_MDMA_D0_X_COUNT(cnt);
+        bfin_write_MDMA_D0_X_MODIFY(dmod);
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
-        bfin_write_MDMA_S0_START_ADDR(buf);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(1);
+        bfin_write_MDMA_S0_START_ADDR(saddr);
+        bfin_write_MDMA_S0_X_COUNT(cnt);
+        bfin_write_MDMA_S0_X_MODIFY(smod);
         bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
+        bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
+        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
+
+        spin_unlock_irqrestore(&mdma_lock, flags);
 
         SSYNC();
 
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
+        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+                if (bfin_read_MDMA_S0_CONFIG())
+                        continue;
+                else
+                        return;
 
         bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
 
         bfin_write_MDMA_S0_CONFIG(0);
         bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
-
 }
-EXPORT_SYMBOL(dma_outsb);
-
 
-void dma_insb(unsigned long addr, void *buf, unsigned short len)
+/**
+ *      _dma_memcpy - translate C memcpy settings into MDMA settings
+ *
+ * Handle all the high level steps before we touch the MDMA registers.  So
+ * handle direction, tweaking of sizes, and formatting of addresses.
+ */
+static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
 {
-        unsigned long flags;
-
-        blackfin_dcache_invalidate_range((unsigned int)buf,
-                         (unsigned int)(buf) + len);
-
-        local_irq_save(flags);
-        bfin_write_MDMA_D0_START_ADDR(buf);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(1);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_START_ADDR(addr);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(0);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        u32 conf, shift;
+        s16 mod;
+        unsigned long dst = (unsigned long)pdst;
+        unsigned long src = (unsigned long)psrc;
 
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
+        if (size == 0)
+                return NULL;
 
-        SSYNC();
+        if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
+                conf = WDSIZE_32;
+                shift = 2;
+        } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
+                conf = WDSIZE_16;
+                shift = 1;
+        } else {
+                conf = WDSIZE_8;
+                shift = 0;
+        }
 
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
+        /* If the two memory regions have a chance of overlapping, make
+         * sure the memcpy still works as expected.  Do this by having the
+         * copy run backwards instead.
+         */
+        mod = 1 << shift;
+        if (src < dst) {
+                mod *= -1;
+                dst += size + mod;
+                src += size + mod;
+        }
+        size >>= shift;
 
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        if (size > 0x10000)
+                conf |= DMA2D;
 
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
+        __dma_memcpy(dst, mod, src, mod, size, conf);
 
+        return pdst;
 }
-EXPORT_SYMBOL(dma_insb);
 
-void dma_outsw(unsigned long addr, const void  *buf, unsigned short len)
+/**
+ *      dma_memcpy - DMA memcpy under mutex lock
+ *
+ * Do not check arguments before starting the DMA memcpy.  Break the transfer
+ * up into two pieces.  The first transfer is in multiples of 64k and the
+ * second transfer is the piece smaller than 64k.
+ */
+void *dma_memcpy(void *pdst, const void *psrc, size_t size)
 {
-        unsigned long flags;
-
-        local_irq_save(flags);
+        unsigned long dst = (unsigned long)pdst;
+        unsigned long src = (unsigned long)psrc;
+        size_t bulk, rest;
 
-        blackfin_dcache_flush_range((unsigned int)buf,
-                         (unsigned int)(buf) + len * sizeof(short));
+        if (bfin_addr_dcachable(src))
+                blackfin_dcache_flush_range(src, src + size);
 
-        bfin_write_MDMA_D0_START_ADDR(addr);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(0);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_START_ADDR(buf);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(2);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
-
-        SSYNC();
-
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
-
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
+        if (bfin_addr_dcachable(dst))
+                blackfin_dcache_invalidate_range(dst, dst + size);
 
+        bulk = size & ~0xffff;
+        rest = size - bulk;
+        if (bulk)
+                _dma_memcpy(pdst, psrc, bulk);
+        _dma_memcpy(pdst + bulk, psrc + bulk, rest);
+        return pdst;
 }
-EXPORT_SYMBOL(dma_outsw);
+EXPORT_SYMBOL(dma_memcpy);
 
-void dma_insw(unsigned long addr, void *buf, unsigned short len)
+/**
+ *      safe_dma_memcpy - DMA memcpy w/argument checking
+ *
+ * Verify arguments are safe before heading to dma_memcpy().
+ */
+void *safe_dma_memcpy(void *dst, const void *src, size_t size)
 {
-        unsigned long flags;
-
-        blackfin_dcache_invalidate_range((unsigned int)buf,
-                         (unsigned int)(buf) + len * sizeof(short));
-
-        local_irq_save(flags);
-
-        bfin_write_MDMA_D0_START_ADDR(buf);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(2);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_START_ADDR(addr);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(0);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
-
-        SSYNC();
-
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
-
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
-
+        if (!access_ok(VERIFY_WRITE, dst, size))
+                return NULL;
+        if (!access_ok(VERIFY_READ, src, size))
+                return NULL;
+        return dma_memcpy(dst, src, size);
 }
-EXPORT_SYMBOL(dma_insw);
+EXPORT_SYMBOL(safe_dma_memcpy);
 
-void dma_outsl(unsigned long addr, const void *buf, unsigned short len)
+static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
+                     u16 size, u16 dma_size)
 {
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        blackfin_dcache_flush_range((unsigned int)buf,
-                         (unsigned int)(buf) + len * sizeof(long));
-
-        bfin_write_MDMA_D0_START_ADDR(addr);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(0);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_START_ADDR(buf);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(4);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
-
-        SSYNC();
-
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
-
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
-
+        blackfin_dcache_flush_range(buf, buf + len * size);
+        __dma_memcpy(addr, 0, buf, size, len, dma_size);
 }
-EXPORT_SYMBOL(dma_outsl);
 
-void dma_insl(unsigned long addr, void *buf, unsigned short len)
+static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
+                    u16 size, u16 dma_size)
 {
-        unsigned long flags;
-
-        blackfin_dcache_invalidate_range((unsigned int)buf,
-                         (unsigned int)(buf) + len * sizeof(long));
-
-        local_irq_save(flags);
-
-        bfin_write_MDMA_D0_START_ADDR(buf);
-        bfin_write_MDMA_D0_X_COUNT(len);
-        bfin_write_MDMA_D0_X_MODIFY(4);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_START_ADDR(addr);
-        bfin_write_MDMA_S0_X_COUNT(len);
-        bfin_write_MDMA_S0_X_MODIFY(0);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
-
-        SSYNC();
-
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
-
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-        bfin_write_MDMA_S0_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
-        local_irq_restore(flags);
-
+        blackfin_dcache_invalidate_range(buf, buf + len * size);
+        __dma_memcpy(buf, size, addr, 0, len, dma_size);
 }
-EXPORT_SYMBOL(dma_insl);
+
+#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
+void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
+{ \
+        _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
+} \
+EXPORT_SYMBOL(dma_##io##s##bwl)
+MAKE_DMA_IO(out, b, 1,  8, const);
+MAKE_DMA_IO(in,  b, 1,  8, );
+MAKE_DMA_IO(out, w, 2, 16, const);
+MAKE_DMA_IO(in,  w, 2, 16, );
+MAKE_DMA_IO(out, l, 4, 32, const);
+MAKE_DMA_IO(in,  l, 4, 32, );
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 5c0800adb4dd..4c14331978f6 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -119,28 +119,28 @@ enum {
 #define AWA_DUMMY_READ(...)  do { } while (0)
 #endif
 
-#ifdef BF533_FAMILY
-static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
+static struct gpio_port_t *gpio_bankb[] = {
         (struct gpio_port_t *) FIO_FLAG_D,
 };
 #endif
 
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
+static struct gpio_port_t *gpio_bankb[] = {
         (struct gpio_port_t *) PORTFIO,
         (struct gpio_port_t *) PORTGIO,
         (struct gpio_port_t *) PORTHIO,
 };
 
-static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+static unsigned short *port_fer[] = {
         (unsigned short *) PORTF_FER,
         (unsigned short *) PORTG_FER,
         (unsigned short *) PORTH_FER,
 };
 #endif
 
-#ifdef BF527_FAMILY
-static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
+static unsigned short *port_mux[] = {
         (unsigned short *) PORTF_MUX,
         (unsigned short *) PORTG_MUX,
         (unsigned short *) PORTH_MUX,
@@ -155,7 +155,7 @@ u8 pmux_offset[][16] =
 #endif
 
 #ifdef BF561_FAMILY
-static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+static struct gpio_port_t *gpio_bankb[] = {
         (struct gpio_port_t *) FIO0_FLAG_D,
         (struct gpio_port_t *) FIO1_FLAG_D,
         (struct gpio_port_t *) FIO2_FLAG_D,
@@ -163,7 +163,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
 #endif
 
 #ifdef BF548_FAMILY
-static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+static struct gpio_port_t *gpio_array[] = {
         (struct gpio_port_t *)PORTA_FER,
         (struct gpio_port_t *)PORTB_FER,
         (struct gpio_port_t *)PORTC_FER,
@@ -177,8 +177,9 @@ static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
 };
 #endif
 
-static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
 static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
+static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
 
 #define RESOURCE_LABEL_SIZE     16
 
@@ -188,48 +189,46 @@ static struct str_ident {
 
 #if defined(CONFIG_PM)
 #if defined(CONFIG_BF54x)
-static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
 #else
-static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static unsigned short wakeup_map[GPIO_BANK_NUM];
 static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
-static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
+static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
 
 #ifdef BF533_FAMILY
-static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
+static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB};
 #endif
 
 #ifdef BF537_FAMILY
-static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
+static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
+#endif
+
+#ifdef BF538_FAMILY
+static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB};
 #endif
 
-#ifdef BF527_FAMILY
-static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
+#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
+static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
 #endif
 
 #ifdef BF561_FAMILY
-static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
+static unsigned int sic_iwr_irqs[] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
 #endif
 #endif
 #endif /* CONFIG_PM */
 
-#if defined(BF548_FAMILY)
 inline int check_gpio(unsigned gpio)
 {
+#if defined(BF548_FAMILY)
         if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
             || gpio == GPIO_PH14 || gpio == GPIO_PH15
-            || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
-            || gpio >= MAX_BLACKFIN_GPIOS)
+            || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
                 return -EINVAL;
-        return 0;
-}
-#else
-inline int check_gpio(unsigned gpio)
-{
+#endif
         if (gpio >= MAX_BLACKFIN_GPIOS)
                 return -EINVAL;
         return 0;
 }
-#endif
 
 static void gpio_error(unsigned gpio)
 {
@@ -258,35 +257,30 @@ static int cmp_label(unsigned short ident, const char *label)
         }
 
         if (label)
-                return strncmp(str_ident[ident].name,
-                                 label, strlen(label));
+                return strcmp(str_ident[ident].name, label);
         else
                 return -EINVAL;
 }
 
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
 static void port_setup(unsigned gpio, unsigned short usage)
 {
-        if (!check_gpio(gpio)) {
-                if (usage == GPIO_USAGE)
-                        *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-                else
-                        *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
-                SSYNC();
-        }
-}
+        if (check_gpio(gpio))
+                return;
+
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
+        if (usage == GPIO_USAGE)
+                *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+        else
+                *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
+        SSYNC();
 #elif defined(BF548_FAMILY)
-static void port_setup(unsigned gpio, unsigned short usage)
-{
         if (usage == GPIO_USAGE)
                 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
         else
                 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
         SSYNC();
-}
-#else
-# define port_setup(...)  do { } while (0)
 #endif
+}
 
 #ifdef BF537_FAMILY
 static struct {
@@ -379,7 +373,7 @@ inline u16 get_portmux(unsigned short portno)
 
         return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
 }
-#elif defined(BF527_FAMILY)
+#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
 inline void portmux_setup(unsigned short portno, unsigned short function)
 {
         u16 pmux, ident = P_IDENT(portno);
@@ -428,13 +422,13 @@ arch_initcall(bfin_gpio_init);
 void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
 { \
         unsigned long flags; \
-        local_irq_save(flags); \
+        local_irq_save_hw(flags); \
         if (arg) \
                 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
         else \
                 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
         AWA_DUMMY_READ(name); \
-        local_irq_restore(flags); \
+        local_irq_restore_hw(flags); \
 } \
 EXPORT_SYMBOL(set_gpio_ ## name);
 
@@ -450,13 +444,13 @@ SET_GPIO(both)
 void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
 { \
         unsigned long flags; \
-        local_irq_save(flags); \
+        local_irq_save_hw(flags); \
         if (arg) \
                 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
         else \
                 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
         AWA_DUMMY_READ(name); \
-        local_irq_restore(flags); \
+        local_irq_restore_hw(flags); \
 } \
 EXPORT_SYMBOL(set_gpio_ ## name);
 #else
@@ -479,10 +473,10 @@ SET_GPIO_SC(data)
 void set_gpio_toggle(unsigned gpio)
 {
         unsigned long flags;
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
         AWA_DUMMY_READ(toggle);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 #else
 void set_gpio_toggle(unsigned gpio)
@@ -500,10 +494,10 @@ EXPORT_SYMBOL(set_gpio_toggle);
 void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
 { \
         unsigned long flags; \
-        local_irq_save(flags); \
+        local_irq_save_hw(flags); \
         gpio_bankb[gpio_bank(gpio)]->name = arg; \
         AWA_DUMMY_READ(name); \
-        local_irq_restore(flags); \
+        local_irq_restore_hw(flags); \
 } \
 EXPORT_SYMBOL(set_gpiop_ ## name);
 #else
@@ -531,10 +525,10 @@ unsigned short get_gpio_ ## name(unsigned gpio) \
 { \
         unsigned long flags; \
         unsigned short ret; \
-        local_irq_save(flags); \
+        local_irq_save_hw(flags); \
         ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
         AWA_DUMMY_READ(name); \
-        local_irq_restore(flags); \
+        local_irq_restore_hw(flags); \
         return ret; \
 } \
 EXPORT_SYMBOL(get_gpio_ ## name);
@@ -564,10 +558,10 @@ unsigned short get_gpiop_ ## name(unsigned gpio) \
 { \
         unsigned long flags; \
         unsigned short ret; \
-        local_irq_save(flags); \
+        local_irq_save_hw(flags); \
         ret = (gpio_bankb[gpio_bank(gpio)]->name); \
         AWA_DUMMY_READ(name); \
-        local_irq_restore(flags); \
+        local_irq_restore_hw(flags); \
         return ret; \
 } \
 EXPORT_SYMBOL(get_gpiop_ ## name);
@@ -617,10 +611,10 @@ int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
         if ((check_gpio(gpio) < 0) || !type)
                 return -EINVAL;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
         wakeup_flags_map[gpio] = type;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
@@ -633,11 +627,11 @@ void gpio_pm_wakeup_free(unsigned gpio)
         if (check_gpio(gpio) < 0)
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(gpio_pm_wakeup_free);
 
@@ -679,7 +673,7 @@ u32 bfin_pm_standby_setup(void)
                 gpio_bankb[bank]->maskb = 0;
 
                 if (mask) {
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
                         gpio_bank_saved[bank].fer   = *port_fer[bank];
 #endif
                         gpio_bank_saved[bank].inen  = gpio_bankb[bank]->inen;
@@ -724,7 +718,7 @@ void bfin_pm_standby_restore(void)
                 bank = gpio_bank(i);
 
                 if (mask) {
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
                         *port_fer[bank]         = gpio_bank_saved[bank].fer;
 #endif
                         gpio_bankb[bank]->inen  = gpio_bank_saved[bank].inen;
@@ -750,9 +744,9 @@ void bfin_gpio_pm_hibernate_suspend(void)
         for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                 bank = gpio_bank(i);
 
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
                         gpio_bank_saved[bank].fer   = *port_fer[bank];
-#ifdef BF527_FAMILY
+#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
                         gpio_bank_saved[bank].mux   = *port_mux[bank];
 #else
                         if (bank == 0)
@@ -778,8 +772,8 @@ void bfin_gpio_pm_hibernate_restore(void)
         for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                         bank = gpio_bank(i);
 
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-#ifdef BF527_FAMILY
+#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
+#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
                         *port_mux[bank] = gpio_bank_saved[bank].mux;
 #else
                         if (bank == 0)
@@ -873,7 +867,6 @@ EXPORT_SYMBOL(get_gpio_dir);
 * MODIFICATION HISTORY :
 **************************************************************/
 
-#ifdef BF548_FAMILY
 int peripheral_request(unsigned short per, const char *label)
 {
         unsigned long flags;
@@ -889,31 +882,35 @@ int peripheral_request(unsigned short per, const char *label)
         if (!(per & P_DEFINED))
                 return -ENODEV;
 
-        if (check_gpio(ident) < 0)
-                return -EINVAL;
+        local_irq_save_hw(flags);
 
-        local_irq_save(flags);
-
-        if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
+        /* If a pin can be muxed as either GPIO or peripheral, make
+         * sure it is not already a GPIO pin when we request it.
+         */
+        if (unlikely(!check_gpio(ident) &&
+            reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
                 dump_stack();
                 printk(KERN_ERR
-                    "%s: Peripheral %d is already reserved as GPIO by %s !\n",
+                       "%s: Peripheral %d is already reserved as GPIO by %s !\n",
                        __func__, ident, get_label(ident));
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 return -EBUSY;
         }
 
         if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
 
-                u16 funct = get_portmux(ident);
-
                 /*
                  * Pin functions like AMC address strobes my
                  * be requested and used by several drivers
                  */
 
-                if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
+#ifdef BF548_FAMILY
+                u16 funct = get_portmux(ident);
 
+                if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
+#else
+                if (!(per & P_MAYSHARE)) {
+#endif
                         /*
                          * Allow that the identical pin function can
                          * be requested from the same driver twice
@@ -926,7 +923,7 @@ int peripheral_request(unsigned short per, const char *label)
                         printk(KERN_ERR
                                "%s: Peripheral %d function %d is already reserved by %s !\n",
                                __func__, ident, P_FUNCT2MUX(per), get_label(ident));
-                        local_irq_restore(flags);
+                        local_irq_restore_hw(flags);
                         return -EBUSY;
                 }
         }
@@ -934,89 +931,19 @@ int peripheral_request(unsigned short per, const char *label)
  anyway:
         reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
 
+#ifdef BF548_FAMILY
         portmux_setup(ident, P_FUNCT2MUX(per));
-        port_setup(ident, PERIPHERAL_USAGE);
-
-        local_irq_restore(flags);
-        set_label(ident, label);
-
-        return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
 #else
-
-int peripheral_request(unsigned short per, const char *label)
-{
-        unsigned long flags;
-        unsigned short ident = P_IDENT(per);
-
-        /*
-         * Don't cares are pins with only one dedicated function
-         */
-
-        if (per & P_DONTCARE)
-                return 0;
-
-        if (!(per & P_DEFINED))
-                return -ENODEV;
-
-        local_irq_save(flags);
-
-        if (!check_gpio(ident)) {
-
-                if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
-                        dump_stack();
-                        printk(KERN_ERR
-                               "%s: Peripheral %d is already reserved as GPIO by %s !\n",
-                               __func__, ident, get_label(ident));
-                        local_irq_restore(flags);
-                        return -EBUSY;
-                }
-
-        }
-
-        if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
-
-                /*
-                 * Pin functions like AMC address strobes my
-                 * be requested and used by several drivers
-                 */
-
-                if (!(per & P_MAYSHARE)) {
-
-                        /*
-                         * Allow that the identical pin function can
-                         * be requested from the same driver twice
-                         */
-
-                        if (cmp_label(ident, label) == 0)
-                                goto anyway;
-
-                        dump_stack();
-                        printk(KERN_ERR
-                               "%s: Peripheral %d function %d is already"
-                               " reserved by %s !\n",
-                               __func__, ident, P_FUNCT2MUX(per),
-                                get_label(ident));
-                        local_irq_restore(flags);
-                        return -EBUSY;
-                }
-
-        }
-
- anyway:
         portmux_setup(per, P_FUNCT2MUX(per));
-
+#endif
         port_setup(ident, PERIPHERAL_USAGE);
 
-        reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
         set_label(ident, label);
 
         return 0;
 }
 EXPORT_SYMBOL(peripheral_request);
-#endif
 
 int peripheral_request_list(const unsigned short per[], const char *label)
 {
@@ -1053,10 +980,10 @@ void peripheral_free(unsigned short per)
         if (check_gpio(ident) < 0)
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 return;
         }
 
@@ -1067,7 +994,7 @@ void peripheral_free(unsigned short per)
 
         set_label(ident, "free");
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 EXPORT_SYMBOL(peripheral_free);
 
@@ -1094,14 +1021,14 @@ EXPORT_SYMBOL(peripheral_free_list);
 * MODIFICATION HISTORY :
 **************************************************************/
 
-int gpio_request(unsigned gpio, const char *label)
+int bfin_gpio_request(unsigned gpio, const char *label)
 {
         unsigned long flags;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         /*
          * Allow that the identical GPIO can
@@ -1110,15 +1037,15 @@ int gpio_request(unsigned gpio, const char *label)
          */
 
         if (cmp_label(gpio, label) == 0) {
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 return 0;
         }
 
         if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
                 dump_stack();
                 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
-                         gpio, get_label(gpio));
-                local_irq_restore(flags);
+                       gpio, get_label(gpio));
+                local_irq_restore_hw(flags);
                 return -EBUSY;
         }
         if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
@@ -1126,34 +1053,37 @@ int gpio_request(unsigned gpio, const char *label)
                 printk(KERN_ERR
                        "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
                        gpio, get_label(gpio));
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 return -EBUSY;
         }
+        if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))
+                printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
+                       " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
 
         reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+        set_label(gpio, label);
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         port_setup(gpio, GPIO_USAGE);
-        set_label(gpio, label);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_request);
+EXPORT_SYMBOL(bfin_gpio_request);
 
-void gpio_free(unsigned gpio)
+void bfin_gpio_free(unsigned gpio)
 {
         unsigned long flags;
 
         if (check_gpio(gpio) < 0)
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
                 dump_stack();
                 gpio_error(gpio);
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 return;
         }
 
@@ -1161,13 +1091,76 @@ void gpio_free(unsigned gpio)
 
         set_label(gpio, "free");
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
+}
+EXPORT_SYMBOL(bfin_gpio_free);
+
+int bfin_gpio_irq_request(unsigned gpio, const char *label)
+{
+        unsigned long flags;
+
+        if (check_gpio(gpio) < 0)
+                return -EINVAL;
+
+        local_irq_save_hw(flags);
+
+        if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                dump_stack();
+                printk(KERN_ERR
+                       "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n",
+                       gpio);
+                local_irq_restore_hw(flags);
+                return -EBUSY;
+        }
+        if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                dump_stack();
+                printk(KERN_ERR
+                       "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
+                       gpio, get_label(gpio));
+                local_irq_restore_hw(flags);
+                return -EBUSY;
+        }
+        if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
+                printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
+                       "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
+                       gpio, get_label(gpio));
+
+        reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
+        set_label(gpio, label);
+
+        local_irq_restore_hw(flags);
+
+        port_setup(gpio, GPIO_USAGE);
+
+        return 0;
+}
+
+void bfin_gpio_irq_free(unsigned gpio)
+{
+        unsigned long flags;
+
+        if (check_gpio(gpio) < 0)
+                return;
+
+        local_irq_save_hw(flags);
+
+        if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
+                dump_stack();
+                gpio_error(gpio);
+                local_irq_restore_hw(flags);
+                return;
+        }
+
+        reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+
+        set_label(gpio, "free");
+
+        local_irq_restore_hw(flags);
 }
-EXPORT_SYMBOL(gpio_free);
 
 
 #ifdef BF548_FAMILY
-int gpio_direction_input(unsigned gpio)
+int bfin_gpio_direction_input(unsigned gpio)
 {
         unsigned long flags;
 
@@ -1176,16 +1169,16 @@ int gpio_direction_input(unsigned gpio)
                 return -EINVAL;
         }
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
         gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_input);
+EXPORT_SYMBOL(bfin_gpio_direction_input);
 
-int gpio_direction_output(unsigned gpio, int value)
+int bfin_gpio_direction_output(unsigned gpio, int value)
 {
         unsigned long flags;
 
@@ -1194,30 +1187,30 @@ int gpio_direction_output(unsigned gpio, int value)
                 return -EINVAL;
         }
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
         gpio_set_value(gpio, value);
         gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_output);
+EXPORT_SYMBOL(bfin_gpio_direction_output);
 
-void gpio_set_value(unsigned gpio, int arg)
+void bfin_gpio_set_value(unsigned gpio, int arg)
 {
         if (arg)
                 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
         else
                 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
 }
-EXPORT_SYMBOL(gpio_set_value);
+EXPORT_SYMBOL(bfin_gpio_set_value);
 
-int gpio_get_value(unsigned gpio)
+int bfin_gpio_get_value(unsigned gpio)
 {
         return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
 }
-EXPORT_SYMBOL(gpio_get_value);
+EXPORT_SYMBOL(bfin_gpio_get_value);
 
 void bfin_gpio_irq_prepare(unsigned gpio)
 {
@@ -1225,34 +1218,34 @@ void bfin_gpio_irq_prepare(unsigned gpio)
 
         port_setup(gpio, GPIO_USAGE);
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
         gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 #else
 
-int gpio_get_value(unsigned gpio)
+int bfin_gpio_get_value(unsigned gpio)
 {
         unsigned long flags;
         int ret;
 
         if (unlikely(get_gpio_edge(gpio))) {
-                local_irq_save(flags);
+                local_irq_save_hw(flags);
                 set_gpio_edge(gpio, 0);
                 ret = get_gpio_data(gpio);
                 set_gpio_edge(gpio, 1);
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
 
                 return ret;
         } else
                 return get_gpio_data(gpio);
 }
-EXPORT_SYMBOL(gpio_get_value);
+EXPORT_SYMBOL(bfin_gpio_get_value);
 
 
-int gpio_direction_input(unsigned gpio)
+int bfin_gpio_direction_input(unsigned gpio)
 {
         unsigned long flags;
 
@@ -1261,17 +1254,17 @@ int gpio_direction_input(unsigned gpio)
                 return -EINVAL;
         }
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
         gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
         AWA_DUMMY_READ(inen);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_input);
+EXPORT_SYMBOL(bfin_gpio_direction_input);
 
-int gpio_direction_output(unsigned gpio, int value)
+int bfin_gpio_direction_output(unsigned gpio, int value)
 {
         unsigned long flags;
 
@@ -1280,7 +1273,7 @@ int gpio_direction_output(unsigned gpio, int value)
                 return -EINVAL;
         }
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
 
         if (value)
@@ -1290,11 +1283,11 @@ int gpio_direction_output(unsigned gpio, int value)
 
         gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
         AWA_DUMMY_READ(dir);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_output);
+EXPORT_SYMBOL(bfin_gpio_direction_output);
 
 /* If we are booting from SPI and our board lacks a strong enough pull up,
  * the core can reset and execute the bootrom faster than the resistor can
@@ -1327,14 +1320,17 @@ void bfin_gpio_irq_prepare(unsigned gpio)
 static int gpio_proc_read(char *buf, char **start, off_t offset,
                           int len, int *unused_i, void *unused_v)
 {
-        int c, outlen = 0;
+        int c, irq, gpio, outlen = 0;
 
         for (c = 0; c < MAX_RESOURCES; c++) {
-                if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
-                        len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
-                                 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
+                irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
+                gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
+                if (!check_gpio(c) && (gpio || irq))
+                        len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
+                                 get_label(c), (gpio && irq) ? " *" : "",
+                                 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
                 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
-                        len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
+                        len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
                 else
                         continue;
                 buf += len;
@@ -1354,3 +1350,57 @@ static __init int gpio_register_proc(void)
 }
 __initcall(gpio_register_proc);
 #endif
+
+#ifdef CONFIG_GPIOLIB
+int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_gpio_direction_input(gpio);
+}
+
+int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
+{
+        return bfin_gpio_direction_output(gpio, level);
+}
+
+int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_gpio_get_value(gpio);
+}
+
+void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+#ifdef BF548_FAMILY
+        return bfin_gpio_set_value(gpio, value);
+#else
+        return set_gpio_data(gpio, value);
+#endif
+}
+
+int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_gpio_request(gpio, chip->label);
+}
+
+void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
+{
+        return bfin_gpio_free(gpio);
+}
+
+static struct gpio_chip bfin_chip = {
+        .label                  = "Blackfin-GPIOlib",
+        .direction_input        = bfin_gpiolib_direction_input,
+        .get                    = bfin_gpiolib_get_value,
+        .direction_output       = bfin_gpiolib_direction_output,
+        .set                    = bfin_gpiolib_set_value,
+        .request                = bfin_gpiolib_gpio_request,
+        .free                   = bfin_gpiolib_gpio_free,
+        .base                   = 0,
+        .ngpio                  = MAX_BLACKFIN_GPIOS,
+};
+
+static int __init bfin_gpiolib_setup(void)
+{
+        return gpiochip_add(&bfin_chip);
+}
+arch_initcall(bfin_gpiolib_setup);
+#endif
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 4367330909b2..01f917d58b59 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -1,52 +1,25 @@
 /*
- * File:         arch/blackfin/kernel/bfin_ksyms.c
- * Based on:     none - original work
- * Author:
+ * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols
  *
- * Created:
- * Description:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/module.h>
-#include <linux/irq.h>
 #include <linux/uaccess.h>
 
-#include <asm/checksum.h>
 #include <asm/cacheflush.h>
 
-/* platform dependent support */
-
-EXPORT_SYMBOL(__ioremap);
-
-EXPORT_SYMBOL(ip_fast_csum);
-
-EXPORT_SYMBOL(kernel_thread);
-
-EXPORT_SYMBOL(is_in_rom);
+/* Allow people to have their own Blackfin exception handler in a module */
 EXPORT_SYMBOL(bfin_return_from_exception);
 
-/* Networking helper routines. */
-EXPORT_SYMBOL(csum_partial_copy);
+/* All the Blackfin cache functions: mach-common/cache.S */
+EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
+EXPORT_SYMBOL(blackfin_icache_dcache_flush_range);
+EXPORT_SYMBOL(blackfin_icache_flush_range);
+EXPORT_SYMBOL(blackfin_dcache_flush_range);
+EXPORT_SYMBOL(blackfin_dflush_page);
 
 /* The following are special because they're not called
  * explicitly (the C compiler generates them).  Fortunately,
@@ -74,8 +47,6 @@ extern void __modsi3(void);
 extern void __muldi3(void);
 extern void __udivsi3(void);
 extern void __umodsi3(void);
-
-/* gcc lib functions */
 EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__ashrdi3);
 EXPORT_SYMBOL(__umulsi3_highpart);
@@ -87,6 +58,7 @@ EXPORT_SYMBOL(__muldi3);
 EXPORT_SYMBOL(__udivsi3);
 EXPORT_SYMBOL(__umodsi3);
 
+/* Input/output symbols: lib/{in,out}s.S */
 EXPORT_SYMBOL(outsb);
 EXPORT_SYMBOL(insb);
 EXPORT_SYMBOL(outsw);
@@ -96,20 +68,39 @@ EXPORT_SYMBOL(insw_8);
 EXPORT_SYMBOL(outsl);
 EXPORT_SYMBOL(insl);
 EXPORT_SYMBOL(insl_16);
-EXPORT_SYMBOL(irq_flags);
-EXPORT_SYMBOL(iounmap);
-EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
-EXPORT_SYMBOL(blackfin_icache_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_icache_flush_range);
-EXPORT_SYMBOL(blackfin_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_dflush_page);
 
-EXPORT_SYMBOL(csum_partial);
-EXPORT_SYMBOL(__init_begin);
-EXPORT_SYMBOL(__init_end);
-EXPORT_SYMBOL(_ebss_l1);
-EXPORT_SYMBOL(_stext_l1);
-EXPORT_SYMBOL(_etext_l1);
-EXPORT_SYMBOL(_sdata_l1);
-EXPORT_SYMBOL(_ebss_b_l1);
-EXPORT_SYMBOL(_sdata_b_l1);
+#ifdef CONFIG_SMP
+EXPORT_SYMBOL(__raw_atomic_update_asm);
+EXPORT_SYMBOL(__raw_atomic_clear_asm);
+EXPORT_SYMBOL(__raw_atomic_set_asm);
+EXPORT_SYMBOL(__raw_atomic_xor_asm);
+EXPORT_SYMBOL(__raw_atomic_test_asm);
+EXPORT_SYMBOL(__raw_xchg_1_asm);
+EXPORT_SYMBOL(__raw_xchg_2_asm);
+EXPORT_SYMBOL(__raw_xchg_4_asm);
+EXPORT_SYMBOL(__raw_cmpxchg_1_asm);
+EXPORT_SYMBOL(__raw_cmpxchg_2_asm);
+EXPORT_SYMBOL(__raw_cmpxchg_4_asm);
+EXPORT_SYMBOL(__raw_spin_is_locked_asm);
+EXPORT_SYMBOL(__raw_spin_lock_asm);
+EXPORT_SYMBOL(__raw_spin_trylock_asm);
+EXPORT_SYMBOL(__raw_spin_unlock_asm);
+EXPORT_SYMBOL(__raw_read_lock_asm);
+EXPORT_SYMBOL(__raw_read_trylock_asm);
+EXPORT_SYMBOL(__raw_read_unlock_asm);
+EXPORT_SYMBOL(__raw_write_lock_asm);
+EXPORT_SYMBOL(__raw_write_trylock_asm);
+EXPORT_SYMBOL(__raw_write_unlock_asm);
+EXPORT_SYMBOL(__raw_bit_set_asm);
+EXPORT_SYMBOL(__raw_bit_clear_asm);
+EXPORT_SYMBOL(__raw_bit_toggle_asm);
+EXPORT_SYMBOL(__raw_bit_test_asm);
+EXPORT_SYMBOL(__raw_bit_test_set_asm);
+EXPORT_SYMBOL(__raw_bit_test_clear_asm);
+EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
+EXPORT_SYMBOL(__raw_uncached_fetch_asm);
+#ifdef __ARCH_SYNC_CORE_DCACHE
+EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
+EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
+#endif
+#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
index 286b69357f97..7d70d3bf3212 100644
--- a/arch/blackfin/kernel/cplb-mpu/Makefile
+++ b/arch/blackfin/kernel/cplb-mpu/Makefile
@@ -4,5 +4,7 @@
 
 obj-y := cplbinit.o cacheinit.o cplbmgr.o
 
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
-
+CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
+                    -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
+                    -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
+                    -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
index a8b712a24c59..c6ff947f9d37 100644
--- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
@@ -25,7 +25,7 @@
 #include <asm/cplbinit.h>
 
 #if defined(CONFIG_BFIN_ICACHE)
-void __init bfin_icache_init(void)
+void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
 {
         unsigned long ctrl;
         int i;
@@ -43,7 +43,7 @@ void __init bfin_icache_init(void)
 #endif
 
 #if defined(CONFIG_BFIN_DCACHE)
-void __init bfin_dcache_init(void)
+void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
 {
         unsigned long ctrl;
         int i;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
deleted file mode 100644
index 822beefa3a4b..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * File:         arch/blackfin/mach-common/cplbinfo.c
- * Based on:
- * Author:       Sonic Zhang <sonic.zhang@analog.com>
- *
- * Created:      Jan. 2005
- * Description:  Display CPLB status
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/uaccess.h>
-
-#include <asm/current.h>
-#include <asm/system.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" };
-
-static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched)
-{
-        int i;
-        buf += sprintf(buf, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
-        for (i = 0; i < MAX_CPLBS; i++) {
-                unsigned long data = tbl[i].data;
-                unsigned long addr = tbl[i].addr;
-                if (!(data & CPLB_VALID))
-                        continue;
-
-                buf +=
-                    sprintf(buf,
-                            "%d\t0x%08lx\t%06lx\t%s\t%c\t%c\t%c\t%c\n",
-                            i, addr, data,
-                            page_size_string_table[(data & 0x30000) >> 16],
-                            (data & CPLB_USER_RD) ? 'Y' : 'N',
-                            (data & CPLB_USER_WR) ? 'Y' : 'N',
-                            (data & CPLB_SUPV_WR) ? 'Y' : 'N',
-                            i < switched ? 'N' : 'Y');
-        }
-        buf += sprintf(buf, "\n");
-
-        return buf;
-}
-
-int cplbinfo_proc_output(char *buf)
-{
-        char *p;
-
-        p = buf;
-
-        p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
-
-        if (bfin_read_IMEM_CONTROL() & ENICPLB) {
-                p += sprintf(p, "Instruction CPLB entry:\n");
-                p = cplb_print_entry(p, icplb_tbl, first_switched_icplb);
-        } else
-                p += sprintf(p, "Instruction CPLB is disabled.\n\n");
-
-        if (1 || bfin_read_DMEM_CONTROL() & ENDCPLB) {
-                p += sprintf(p, "Data CPLB entry:\n");
-                p = cplb_print_entry(p, dcplb_tbl, first_switched_dcplb);
-        } else
-                p += sprintf(p, "Data CPLB is disabled.\n");
-
-        p += sprintf(p, "ICPLB miss: %d\nICPLB supervisor miss: %d\n",
-                     nr_icplb_miss, nr_icplb_supv_miss);
-        p += sprintf(p, "DCPLB miss: %d\nDCPLB protection fault:%d\n",
-                     nr_dcplb_miss, nr_dcplb_prot);
-        p += sprintf(p, "CPLB flushes: %d\n",
-                     nr_cplb_flush);
-
-        return p - buf;
-}
-
-static int cplbinfo_read_proc(char *page, char **start, off_t off,
-                              int count, int *eof, void *data)
-{
-        int len;
-
-        len = cplbinfo_proc_output(page);
-        if (len <= off + count)
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
-}
-
-static int __init cplbinfo_init(void)
-{
-        struct proc_dir_entry *entry;
-
-        entry = create_proc_entry("cplbinfo", 0, NULL);
-        if (!entry)
-                return -ENOMEM;
-
-        entry->read_proc = cplbinfo_read_proc;
-        entry->data = NULL;
-
-        return 0;
-}
-
-static void __exit cplbinfo_exit(void)
-{
-        remove_proc_entry("cplbinfo", NULL);
-}
-
-module_init(cplbinfo_init);
-module_exit(cplbinfo_exit);
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index 55af729f8495..bdb958486e76 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -25,18 +25,19 @@
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
 #include <asm/cplbinit.h>
+#include <asm/mem_map.h>
 
 #if ANOMALY_05000263
 # error the MPU will not function safely while Anomaly 05000263 applies
 #endif
 
-struct cplb_entry icplb_tbl[MAX_CPLBS];
-struct cplb_entry dcplb_tbl[MAX_CPLBS];
+struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
+struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
 
 int first_switched_icplb, first_switched_dcplb;
 int first_mask_dcplb;
 
-void __init generate_cplb_tables(void)
+void __init generate_cplb_tables_cpu(unsigned int cpu)
 {
         int i_d, i_i;
         unsigned long addr;
@@ -55,15 +56,16 @@ void __init generate_cplb_tables(void)
         d_cache |= CPLB_L1_AOW | CPLB_WT;
 #endif
 #endif
+
         i_d = i_i = 0;
 
         /* Set up the zero page.  */
-        dcplb_tbl[i_d].addr = 0;
-        dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
+        dcplb_tbl[cpu][i_d].addr = 0;
+        dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
 
 #if 0
-        icplb_tbl[i_i].addr = 0;
-        icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
+        icplb_tbl[cpu][i_i].addr = 0;
+        icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
 #endif
 
         /* Cover kernel memory with 4M pages.  */
@@ -72,28 +74,28 @@ void __init generate_cplb_tables(void)
         i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
 
         for (; addr < memory_start; addr += 4 * 1024 * 1024) {
-                dcplb_tbl[i_d].addr = addr;
-                dcplb_tbl[i_d++].data = d_data;
-                icplb_tbl[i_i].addr = addr;
-                icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
+                dcplb_tbl[cpu][i_d].addr = addr;
+                dcplb_tbl[cpu][i_d++].data = d_data;
+                icplb_tbl[cpu][i_i].addr = addr;
+                icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
         }
 
         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
-        dcplb_tbl[i_d].addr = L1_DATA_A_START;
-        dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+        dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
+        dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
 #endif
 #if L1_CODE_LENGTH > 0
-        icplb_tbl[i_i].addr = L1_CODE_START;
-        icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
+        icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
+        icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
 #endif
 
         /* Cover L2 memory */
 #if L2_LENGTH > 0
-        dcplb_tbl[i_d].addr = L2_START;
-        dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
-        icplb_tbl[i_i].addr = L2_START;
-        icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
+        dcplb_tbl[cpu][i_d].addr = L2_START;
+        dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
+        icplb_tbl[cpu][i_i].addr = L2_START;
+        icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
 #endif
 
         first_mask_dcplb = i_d;
@@ -101,7 +103,11 @@ void __init generate_cplb_tables(void)
         first_switched_icplb = i_i;
 
         while (i_d < MAX_CPLBS)
-                dcplb_tbl[i_d++].data = 0;
+                dcplb_tbl[cpu][i_d++].data = 0;
         while (i_i < MAX_CPLBS)
-                icplb_tbl[i_i++].data = 0;
+                icplb_tbl[cpu][i_i++].data = 0;
+}
+
+void generate_cplb_tables_all(void)
+{
 }
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index baa52e261f0d..87463ce87f5a 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -25,15 +25,21 @@
 #include <asm/cplbinit.h>
 #include <asm/mmu_context.h>
 
-#define FAULT_RW        (1 << 16)
-#define FAULT_USERSUPV  (1 << 17)
+/*
+ * WARNING
+ *
+ * This file is compiled with certain -ffixed-reg options.  We have to
+ * make sure not to call any functions here that could clobber these
+ * registers.
+ */
 
 int page_mask_nelts;
 int page_mask_order;
-unsigned long *current_rwx_mask;
+unsigned long *current_rwx_mask[NR_CPUS];
 
-int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
-int nr_cplb_flush;
+int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
+int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
+int nr_cplb_flush[NR_CPUS];
 
 static inline void disable_dcplb(void)
 {
@@ -98,42 +104,42 @@ static inline int write_permitted(int status, unsigned long data)
 }
 
 /* Counters to implement round-robin replacement.  */
-static int icplb_rr_index, dcplb_rr_index;
+static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
 
 /*
  * Find an ICPLB entry to be evicted and return its index.
  */
-static int evict_one_icplb(void)
+static int evict_one_icplb(unsigned int cpu)
 {
         int i;
         for (i = first_switched_icplb; i < MAX_CPLBS; i++)
-                if ((icplb_tbl[i].data & CPLB_VALID) == 0)
+                if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
                         return i;
-        i = first_switched_icplb + icplb_rr_index;
+        i = first_switched_icplb + icplb_rr_index[cpu];
         if (i >= MAX_CPLBS) {
                 i -= MAX_CPLBS - first_switched_icplb;
-                icplb_rr_index -= MAX_CPLBS - first_switched_icplb;
+                icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
         }
-        icplb_rr_index++;
+        icplb_rr_index[cpu]++;
         return i;
 }
 
-static int evict_one_dcplb(void)
+static int evict_one_dcplb(unsigned int cpu)
 {
         int i;
         for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
-                if ((dcplb_tbl[i].data & CPLB_VALID) == 0)
+                if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
                         return i;
-        i = first_switched_dcplb + dcplb_rr_index;
+        i = first_switched_dcplb + dcplb_rr_index[cpu];
         if (i >= MAX_CPLBS) {
                 i -= MAX_CPLBS - first_switched_dcplb;
-                dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb;
+                dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
         }
-        dcplb_rr_index++;
+        dcplb_rr_index[cpu]++;
         return i;
 }
 
-static noinline int dcplb_miss(void)
+static noinline int dcplb_miss(unsigned int cpu)
 {
         unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
         int status = bfin_read_DCPLB_STATUS();
@@ -141,7 +147,7 @@ static noinline int dcplb_miss(void)
         int idx;
         unsigned long d_data;
 
-        nr_dcplb_miss++;
+        nr_dcplb_miss[cpu]++;
 
         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 #ifdef CONFIG_BFIN_DCACHE
@@ -168,25 +174,25 @@ static noinline int dcplb_miss(void)
         } else if (addr >= _ramend) {
             d_data |= CPLB_USER_RD | CPLB_USER_WR;
         } else {
-                mask = current_rwx_mask;
+                mask = current_rwx_mask[cpu];
                 if (mask) {
                         int page = addr >> PAGE_SHIFT;
-                        int offs = page >> 5;
+                        int idx = page >> 5;
                         int bit = 1 << (page & 31);
 
-                        if (mask[offs] & bit)
+                        if (mask[idx] & bit)
                                 d_data |= CPLB_USER_RD;
 
                         mask += page_mask_nelts;
-                        if (mask[offs] & bit)
+                        if (mask[idx] & bit)
                                 d_data |= CPLB_USER_WR;
                 }
         }
-        idx = evict_one_dcplb();
+        idx = evict_one_dcplb(cpu);
 
         addr &= PAGE_MASK;
-        dcplb_tbl[idx].addr = addr;
-        dcplb_tbl[idx].data = d_data;
+        dcplb_tbl[cpu][idx].addr = addr;
+        dcplb_tbl[cpu][idx].data = d_data;
 
         disable_dcplb();
         bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
@@ -196,21 +202,21 @@ static noinline int dcplb_miss(void)
         return 0;
 }
 
-static noinline int icplb_miss(void)
+static noinline int icplb_miss(unsigned int cpu)
 {
         unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
         int status = bfin_read_ICPLB_STATUS();
         int idx;
         unsigned long i_data;
 
-        nr_icplb_miss++;
+        nr_icplb_miss[cpu]++;
 
         /* If inside the uncached DMA region, fault.  */
         if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
                 return CPLB_PROT_VIOL;
 
         if (status & FAULT_USERSUPV)
-                nr_icplb_supv_miss++;
+                nr_icplb_supv_miss[cpu]++;
 
         /*
          * First, try to find a CPLB that matches this address.  If we
@@ -218,8 +224,8 @@ static noinline int icplb_miss(void)
          * that the instruction crosses a page boundary.
          */
         for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
-                if (icplb_tbl[idx].data & CPLB_VALID) {
-                        unsigned long this_addr = icplb_tbl[idx].addr;
+                if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
+                        unsigned long this_addr = icplb_tbl[cpu][idx].addr;
                         if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
                                 addr += PAGE_SIZE;
                                 break;
@@ -257,23 +263,23 @@ static noinline int icplb_miss(void)
                  * Otherwise, check the x bitmap of the current process.
                  */
                 if (!(status & FAULT_USERSUPV)) {
-                        unsigned long *mask = current_rwx_mask;
+                        unsigned long *mask = current_rwx_mask[cpu];
 
                         if (mask) {
                                 int page = addr >> PAGE_SHIFT;
-                                int offs = page >> 5;
+                                int idx = page >> 5;
                                 int bit = 1 << (page & 31);
 
                                 mask += 2 * page_mask_nelts;
-                                if (mask[offs] & bit)
+                                if (mask[idx] & bit)
                                         i_data |= CPLB_USER_RD;
                         }
                 }
         }
-        idx = evict_one_icplb();
+        idx = evict_one_icplb(cpu);
         addr &= PAGE_MASK;
-        icplb_tbl[idx].addr = addr;
-        icplb_tbl[idx].data = i_data;
+        icplb_tbl[cpu][idx].addr = addr;
+        icplb_tbl[cpu][idx].data = i_data;
 
         disable_icplb();
         bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
@@ -283,19 +289,19 @@ static noinline int icplb_miss(void)
         return 0;
 }
 
-static noinline int dcplb_protection_fault(void)
+static noinline int dcplb_protection_fault(unsigned int cpu)
 {
         int status = bfin_read_DCPLB_STATUS();
 
-        nr_dcplb_prot++;
+        nr_dcplb_prot[cpu]++;
 
         if (status & FAULT_RW) {
                 int idx = faulting_cplb_index(status);
-                unsigned long data = dcplb_tbl[idx].data;
+                unsigned long data = dcplb_tbl[cpu][idx].data;
                 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
                     write_permitted(status, data)) {
                         data |= CPLB_DIRTY;
-                        dcplb_tbl[idx].data = data;
+                        dcplb_tbl[cpu][idx].data = data;
                         bfin_write32(DCPLB_DATA0 + idx * 4, data);
                         return 0;
                 }
@@ -306,44 +312,45 @@ static noinline int dcplb_protection_fault(void)
 int cplb_hdr(int seqstat, struct pt_regs *regs)
 {
         int cause = seqstat & 0x3f;
+        unsigned int cpu = smp_processor_id();
         switch (cause) {
         case 0x23:
-                return dcplb_protection_fault();
+                return dcplb_protection_fault(cpu);
         case 0x2C:
-                return icplb_miss();
+                return icplb_miss(cpu);
         case 0x26:
-                return dcplb_miss();
+                return dcplb_miss(cpu);
         default:
                 return 1;
         }
 }
 
-void flush_switched_cplbs(void)
+void flush_switched_cplbs(unsigned int cpu)
 {
         int i;
         unsigned long flags;
 
-        nr_cplb_flush++;
+        nr_cplb_flush[cpu]++;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         disable_icplb();
         for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
-                icplb_tbl[i].data = 0;
+                icplb_tbl[cpu][i].data = 0;
                 bfin_write32(ICPLB_DATA0 + i * 4, 0);
         }
         enable_icplb();
 
         disable_dcplb();
         for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
-                dcplb_tbl[i].data = 0;
+                dcplb_tbl[cpu][i].data = 0;
                 bfin_write32(DCPLB_DATA0 + i * 4, 0);
         }
         enable_dcplb();
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
 }
 
-void set_mask_dcplbs(unsigned long *masks)
+void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
 {
         int i;
         unsigned long addr = (unsigned long)masks;
@@ -351,12 +358,12 @@ void set_mask_dcplbs(unsigned long *masks)
         unsigned long flags;
 
         if (!masks) {
-                current_rwx_mask = masks;
+                current_rwx_mask[cpu] = masks;
                 return;
         }
 
-        local_irq_save(flags);
-        current_rwx_mask = masks;
+        local_irq_save_hw(flags);
+        current_rwx_mask[cpu] = masks;
 
         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 #ifdef CONFIG_BFIN_DCACHE
@@ -368,12 +375,12 @@ void set_mask_dcplbs(unsigned long *masks)
 
         disable_dcplb();
         for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
-                dcplb_tbl[i].addr = addr;
-                dcplb_tbl[i].data = d_data;
+                dcplb_tbl[cpu][i].addr = addr;
+                dcplb_tbl[cpu][i].data = d_data;
                 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
                 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
                 addr += PAGE_SIZE;
         }
         enable_dcplb();
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
index d36ea9b5382e..7d70d3bf3212 100644
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ b/arch/blackfin/kernel/cplb-nompu/Makefile
@@ -2,7 +2,9 @@
 # arch/blackfin/kernel/cplb-nompu/Makefile
 #
 
-obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o
-
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
+obj-y := cplbinit.o cacheinit.o cplbmgr.o
 
+CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
+                    -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
+                    -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
+                    -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
index bd0831592c2c..c6ff947f9d37 100644
--- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
@@ -25,19 +25,15 @@
 #include <asm/cplbinit.h>
 
 #if defined(CONFIG_BFIN_ICACHE)
-void __init bfin_icache_init(void)
+void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
 {
-        unsigned long *table = icplb_table;
         unsigned long ctrl;
         int i;
 
+        SSYNC();
         for (i = 0; i < MAX_CPLBS; i++) {
-                unsigned long addr = *table++;
-                unsigned long data = *table++;
-                if (addr == (unsigned long)-1)
-                        break;
-                bfin_write32(ICPLB_ADDR0 + i * 4, addr);
-                bfin_write32(ICPLB_DATA0 + i * 4, data);
+                bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
+                bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
         }
         ctrl = bfin_read_IMEM_CONTROL();
         ctrl |= IMC | ENICPLB;
@@ -47,20 +43,17 @@ void __init bfin_icache_init(void)
 #endif
 
 #if defined(CONFIG_BFIN_DCACHE)
-void __init bfin_dcache_init(void)
+void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
 {
-        unsigned long *table = dcplb_table;
         unsigned long ctrl;
         int i;
 
+        SSYNC();
         for (i = 0; i < MAX_CPLBS; i++) {
-                unsigned long addr = *table++;
-                unsigned long data = *table++;
-                if (addr == (unsigned long)-1)
-                        break;
-                bfin_write32(DCPLB_ADDR0 + i * 4, addr);
-                bfin_write32(DCPLB_DATA0 + i * 4, data);
+                bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
+                bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
         }
+
         ctrl = bfin_read_DMEM_CONTROL();
         ctrl |= DMEM_CNTR;
         bfin_write_DMEM_CONTROL(ctrl);
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
deleted file mode 100644
index ecbabc0a1fed..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * File:         arch/blackfin/mach-common/cplbhdlr.S
- * Based on:
- * Author:       LG Soft India
- *
- * Created:      ?
- * Description:  CPLB exception handler
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <asm/cplb.h>
-#include <asm/entry.h>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.type _cplb_mgr, STT_FUNC;
-.type _panic_cplb_error, STT_FUNC;
-
-.align 2
-
-ENTRY(__cplb_hdr)
-        R2 = SEQSTAT;
-
-        /* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */
-        R2 <<= 26;
-        R2 >>= 26;
-
-        R1 = 0x23; /* Data access CPLB protection violation */
-        CC = R2 == R1;
-        IF !CC JUMP .Lnot_data_write;
-        R0 = 2;         /* is a write to data space*/
-        JUMP .Lis_icplb_miss;
-
-.Lnot_data_write:
-        R1 = 0x2C; /* CPLB miss on an instruction fetch */
-        CC = R2 == R1;
-        R0 = 0;         /* is_data_miss == False*/
-        IF CC JUMP .Lis_icplb_miss;
-
-        R1 = 0x26;
-        CC = R2 == R1;
-        IF !CC JUMP .Lunknown;
-
-        R0 = 1;         /* is_data_miss == True*/
-
-.Lis_icplb_miss:
-
-#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
-        R1 = CPLB_ENABLE_ICACHE;
-# endif
-# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
-        R1 = CPLB_ENABLE_DCACHE;
-# endif
-# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
-        R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
-# endif
-#else
-        R1 = 0;
-#endif
-
-        [--SP] = RETS;
-        CALL _cplb_mgr;
-        RETS = [SP++];
-        CC = R0 == 0;
-        IF !CC JUMP .Lnot_replaced;
-        RTS;
-
-/*
- * Diagnostic exception handlers
- */
-.Lunknown:
-        R0 = CPLB_UNKNOWN_ERR;
-        JUMP .Lcplb_error;
-
-.Lnot_replaced:
-        CC = R0 == CPLB_NO_UNLOCKED;
-        IF !CC JUMP .Lnext_check;
-        R0 = CPLB_NO_UNLOCKED;
-        JUMP .Lcplb_error;
-
-.Lnext_check:
-        CC = R0 == CPLB_NO_ADDR_MATCH;
-        IF !CC JUMP .Lnext_check2;
-        R0 = CPLB_NO_ADDR_MATCH;
-        JUMP .Lcplb_error;
-
-.Lnext_check2:
-        CC = R0 == CPLB_PROT_VIOL;
-        IF !CC JUMP .Lstrange_return_from_cplb_mgr;
-        R0 = CPLB_PROT_VIOL;
-        JUMP .Lcplb_error;
-
-.Lstrange_return_from_cplb_mgr:
-        IDLE;
-        CSYNC;
-        JUMP .Lstrange_return_from_cplb_mgr;
-
-.Lcplb_error:
-        R1 = sp;
-        SP += -12;
-        call _panic_cplb_error;
-        SP += 12;
-        JUMP.L _handle_bad_cplb;
-
-ENDPROC(__cplb_hdr)
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
deleted file mode 100644
index 1e74f0b97996..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * File:         arch/blackfin/mach-common/cplbinfo.c
- * Based on:
- * Author:       Sonic Zhang <sonic.zhang@analog.com>
- *
- * Created:      Jan. 2005
- * Description:  Display CPLB status
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/uaccess.h>
-
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-#define CPLB_I 1
-#define CPLB_D 2
-
-#define SYNC_SYS    SSYNC()
-#define SYNC_CORE   CSYNC()
-
-#define CPLB_BIT_PAGESIZE 0x30000
-
-static int page_size_table[4] = {
-        0x00000400,             /* 1K */
-        0x00001000,             /* 4K */
-        0x00100000,             /* 1M */
-        0x00400000              /* 4M */
-};
-
-static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" };
-
-static int cplb_find_entry(unsigned long *cplb_addr,
-                           unsigned long *cplb_data, unsigned long addr,
-                           unsigned long data)
-{
-        int ii;
-
-        for (ii = 0; ii < 16; ii++)
-                if (addr >= cplb_addr[ii] && addr < cplb_addr[ii] +
-                    page_size_table[(cplb_data[ii] & CPLB_BIT_PAGESIZE) >> 16]
-                        && (cplb_data[ii] == data))
-                        return ii;
-
-        return -1;
-}
-
-static char *cplb_print_entry(char *buf, int type)
-{
-        unsigned long *p_addr = dpdt_table;
-        unsigned long *p_data = dpdt_table + 1;
-        unsigned long *p_icount = dpdt_swapcount_table;
-        unsigned long *p_ocount = dpdt_swapcount_table + 1;
-        unsigned long *cplb_addr = (unsigned long *)DCPLB_ADDR0;
-        unsigned long *cplb_data = (unsigned long *)DCPLB_DATA0;
-        int entry = 0, used_cplb = 0;
-
-        if (type == CPLB_I) {
-                buf += sprintf(buf, "Instruction CPLB entry:\n");
-                p_addr = ipdt_table;
-                p_data = ipdt_table + 1;
-                p_icount = ipdt_swapcount_table;
-                p_ocount = ipdt_swapcount_table + 1;
-                cplb_addr = (unsigned long *)ICPLB_ADDR0;
-                cplb_data = (unsigned long *)ICPLB_DATA0;
-        } else
-                buf += sprintf(buf, "Data CPLB entry:\n");
-
-        buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\tiCount\toCount\n");
-
-        while (*p_addr != 0xffffffff) {
-                entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
-                if (entry >= 0)
-                        used_cplb |= 1 << entry;
-
-                buf +=
-                    sprintf(buf,
-                            "0x%08lx\t0x%05lx\t%s\t%c\t%c\t%2d\t%ld\t%ld\n",
-                            *p_addr, *p_data,
-                            page_size_string_table[(*p_data & 0x30000) >> 16],
-                            (*p_data & CPLB_VALID) ? 'Y' : 'N',
-                            (*p_data & CPLB_LOCK) ? 'Y' : 'N', entry, *p_icount,
-                            *p_ocount);
-
-                p_addr += 2;
-                p_data += 2;
-                p_icount += 2;
-                p_ocount += 2;
-        }
-
-        if (used_cplb != 0xffff) {
-                buf += sprintf(buf, "Unused/mismatched CPLBs:\n");
-
-                for (entry = 0; entry < 16; entry++)
-                        if (0 == ((1 << entry) & used_cplb)) {
-                                int flags = cplb_data[entry];
-                                buf +=
-                                    sprintf(buf,
-                                            "%2d: 0x%08lx\t0x%05x\t%s\t%c\t%c\n",
-                                            entry, cplb_addr[entry], flags,
-                                            page_size_string_table[(flags &
-                                                                    0x30000) >>
-                                                                   16],
-                                            (flags & CPLB_VALID) ? 'Y' : 'N',
-                                            (flags & CPLB_LOCK) ? 'Y' : 'N');
-                        }
-        }
-
-        buf += sprintf(buf, "\n");
-
-        return buf;
-}
-
-static int cplbinfo_proc_output(char *buf)
-{
-        char *p;
-
-        p = buf;
-
-        p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
-
-        if (bfin_read_IMEM_CONTROL() & ENICPLB)
-                p = cplb_print_entry(p, CPLB_I);
-        else
-                p += sprintf(p, "Instruction CPLB is disabled.\n\n");
-
-        if (bfin_read_DMEM_CONTROL() & ENDCPLB)
-                p = cplb_print_entry(p, CPLB_D);
-        else
-                p += sprintf(p, "Data CPLB is disabled.\n");
-
-        return p - buf;
-}
-
-static int cplbinfo_read_proc(char *page, char **start, off_t off,
-                              int count, int *eof, void *data)
-{
-        int len;
-
-        len = cplbinfo_proc_output(page);
-        if (len <= off + count)
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
-}
-
-static int __init cplbinfo_init(void)
-{
-        struct proc_dir_entry *entry;
-
-        entry = create_proc_entry("cplbinfo", 0, NULL);
-        if (!entry)
-                return -ENOMEM;
-
-        entry->read_proc = cplbinfo_read_proc;
-        entry->data = NULL;
-
-        return 0;
-}
-
-static void __exit cplbinfo_exit(void)
-{
-        remove_proc_entry("cplbinfo", NULL);
-}
-
-module_init(cplbinfo_init);
-module_exit(cplbinfo_exit);
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 2debc900e246..0e28f7595733 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -20,445 +20,152 @@
  * to the Free Software Foundation, Inc.,
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+
 #include <linux/module.h>
 
 #include <asm/blackfin.h>
 #include <asm/cacheflush.h>
 #include <asm/cplb.h>
 #include <asm/cplbinit.h>
+#include <asm/mem_map.h>
 
-#define CPLB_MEM CONFIG_MAX_MEM_SIZE
-
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* possibly 1 for L2 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
-                                 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
-
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* possibly 1 for L2 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
-
-
-u_long icplb_table[MAX_CPLBS + 1];
-u_long dcplb_table[MAX_CPLBS + 1];
-
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-# define PDT_ATTR __attribute__((l1_data))
-#else
-# define PDT_ATTR
-#endif
-
-u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
-u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
+struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
+struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
 
-#ifdef CONFIG_CPLB_INFO
-u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
-u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
-#endif
+int first_switched_icplb PDT_ATTR;
+int first_switched_dcplb PDT_ATTR;
 
-struct s_cplb {
-        struct cplb_tab init_i;
-        struct cplb_tab init_d;
-        struct cplb_tab switch_i;
-        struct cplb_tab switch_d;
-};
+struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
+struct cplb_boundary icplb_bounds[7] PDT_ATTR;
 
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-static struct cplb_desc cplb_data[] = {
-        {
-                .start = 0,
-                .end = SIZE_1K,
-                .psize = SIZE_1K,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = SDRAM_OOPS,
-                .d_conf = SDRAM_OOPS,
-#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "Zero Pointer Guard Page",
-        },
-        {
-                .start = L1_CODE_START,
-                .end = L1_CODE_START + L1_CODE_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB,
-                .i_conf = L1_IMEMORY,
-                .d_conf = 0,
-                .valid = 1,
-                .name = "L1 I-Memory",
-        },
-        {
-                .start = L1_DATA_A_START,
-                .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
-                .psize = SIZE_4M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf = 0,
-                .d_conf = L1_DMEMORY,
-#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
-                .valid = 1,
-#else
-                .valid = 0,
-#endif
-                .name = "L1 D-Memory",
-        },
-        {
-                .start = 0,
-                .end = 0,  /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = SDRAM_IGENERIC,
-                .d_conf = SDRAM_DGENERIC,
-                .valid = 1,
-                .name = "Kernel Memory",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .i_conf = SDRAM_IGENERIC,
-                .d_conf = SDRAM_DNON_CHBL,
-                .valid = 1,
-                .name = "uClinux MTD Memory",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0,   /* dynamic */
-                .psize = SIZE_1M,
-                .attr = INITIAL_T | SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_DNON_CHBL,
-                .valid = 1,
-                .name = "Uncached DMA Zone",
-        },
-        {
-                .start = 0, /* dynamic */
-                .end = 0, /* dynamic */
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .i_conf = 0, /* dynamic */
-                .d_conf = 0, /* dynamic */
-                .valid = 1,
-                .name = "Reserved Memory",
-        },
-        {
-                .start = ASYNC_BANK0_BASE,
-                .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
-                .psize = 0,
-                .attr = SWITCH_T | D_CPLB,
-                .d_conf = SDRAM_EBIU,
-                .valid = 1,
-                .name = "Asynchronous Memory Banks",
-        },
-        {
-                .start = L2_START,
-                .end = L2_START + L2_LENGTH,
-                .psize = SIZE_1M,
-                .attr = SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = L2_IMEMORY,
-                .d_conf = L2_DMEMORY,
-                .valid = (L2_LENGTH > 0),
-                .name = "L2 Memory",
-        },
-        {
-                .start = BOOT_ROM_START,
-                .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
-                .psize = SIZE_1M,
-                .attr = SWITCH_T | I_CPLB | D_CPLB,
-                .i_conf = SDRAM_IGENERIC,
-                .d_conf = SDRAM_DGENERIC,
-                .valid = 1,
-                .name = "On-Chip BootROM",
-        },
-};
+int icplb_nr_bounds PDT_ATTR;
+int dcplb_nr_bounds PDT_ATTR;
 
-static u16 __init lock_kernel_check(u32 start, u32 end)
+void __init generate_cplb_tables_cpu(unsigned int cpu)
 {
-        if (start >= (u32)_end || end <= (u32)_stext)
-                return 0;
+        int i_d, i_i;
+        unsigned long addr;
 
-        /* This cplb block overlapped with kernel area. */
-        return IN_KERNEL;
-}
+        struct cplb_entry *d_tbl = dcplb_tbl[cpu];
+        struct cplb_entry *i_tbl = icplb_tbl[cpu];
 
-static unsigned short __init
-fill_cplbtab(struct cplb_tab *table,
-             unsigned long start, unsigned long end,
-             unsigned long block_size, unsigned long cplb_data)
-{
-        int i;
+        printk(KERN_INFO "NOMPU: setting up cplb tables\n");
 
-        switch (block_size) {
-        case SIZE_4M:
-                i = 3;
-                break;
-        case SIZE_1M:
-                i = 2;
-                break;
-        case SIZE_4K:
-                i = 1;
-                break;
-        case SIZE_1K:
-        default:
-                i = 0;
-                break;
-        }
-
-        cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
-
-        while ((start < end) && (table->pos < table->size)) {
+        i_d = i_i = 0;
 
-                table->tab[table->pos++] = start;
+        /* Set up the zero page.  */
+        d_tbl[i_d].addr = 0;
+        d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
 
-                if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
-                        table->tab[table->pos++] =
-                            cplb_data | CPLB_LOCK | CPLB_DIRTY;
-                else
-                        table->tab[table->pos++] = cplb_data;
+        /* Cover kernel memory with 4M pages.  */
+        addr = 0;
 
-                start += block_size;
+        for (; addr < memory_start; addr += 4 * 1024 * 1024) {
+                d_tbl[i_d].addr = addr;
+                d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
+                i_tbl[i_i].addr = addr;
+                i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
         }
-        return 0;
-}
 
-static unsigned short __init
-close_cplbtab(struct cplb_tab *table)
-{
-
-        while (table->pos < table->size) {
-
-                table->tab[table->pos++] = 0;
-                table->tab[table->pos++] = 0; /* !CPLB_VALID */
+        /* Cover L1 memory.  One 4M area for code and data each is enough.  */
+        if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
+                d_tbl[i_d].addr = L1_DATA_A_START;
+                d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
         }
-        return 0;
-}
+        i_tbl[i_i].addr = L1_CODE_START;
+        i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
 
-/* helper function */
-static void __init
-__fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
-{
-        if (cplb_data[i].psize) {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                cplb_data[i].end,
-                                cplb_data[i].psize,
-                                cplb_data[i].i_conf);
-        } else {
-#if defined(CONFIG_BFIN_ICACHE)
-                if (ANOMALY_05000263 && i == SDRAM_KERN) {
-                        fill_cplbtab(t,
-                                        cplb_data[i].start,
-                                        cplb_data[i].end,
-                                        SIZE_4M,
-                                        cplb_data[i].i_conf);
-                } else
-#endif
-                {
-                        fill_cplbtab(t,
-                                        cplb_data[i].start,
-                                        a_start,
-                                        SIZE_1M,
-                                        cplb_data[i].i_conf);
-                        fill_cplbtab(t,
-                                        a_start,
-                                        a_end,
-                                        SIZE_4M,
-                                        cplb_data[i].i_conf);
-                        fill_cplbtab(t, a_end,
-                                        cplb_data[i].end,
-                                        SIZE_1M,
-                                        cplb_data[i].i_conf);
-                }
-        }
-}
+        first_switched_dcplb = i_d;
+        first_switched_icplb = i_i;
 
-static void __init
-__fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
-{
-        if (cplb_data[i].psize) {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                cplb_data[i].end,
-                                cplb_data[i].psize,
-                                cplb_data[i].d_conf);
-        } else {
-                fill_cplbtab(t,
-                                cplb_data[i].start,
-                                a_start, SIZE_1M,
-                                cplb_data[i].d_conf);
-                fill_cplbtab(t, a_start,
-                                a_end, SIZE_4M,
-                                cplb_data[i].d_conf);
-                fill_cplbtab(t, a_end,
-                                cplb_data[i].end,
-                                SIZE_1M,
-                                cplb_data[i].d_conf);
-        }
+        BUG_ON(first_switched_dcplb > MAX_CPLBS);
+        BUG_ON(first_switched_icplb > MAX_CPLBS);
+
+        while (i_d < MAX_CPLBS)
+                d_tbl[i_d++].data = 0;
+        while (i_i < MAX_CPLBS)
+                i_tbl[i_i++].data = 0;
 }
 
-void __init generate_cplb_tables(void)
+void __init generate_cplb_tables_all(void)
 {
+        int i_d, i_i;
 
-        u16 i, j, process;
-        u32 a_start, a_end, as, ae, as_1m;
-
-        struct cplb_tab *t_i = NULL;
-        struct cplb_tab *t_d = NULL;
-        struct s_cplb cplb;
-
-        printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
-
-        cplb.init_i.size = MAX_CPLBS;
-        cplb.init_d.size = MAX_CPLBS;
-        cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
-        cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
-
-        cplb.init_i.pos = 0;
-        cplb.init_d.pos = 0;
-        cplb.switch_i.pos = 0;
-        cplb.switch_d.pos = 0;
-
-        cplb.init_i.tab = icplb_table;
-        cplb.init_d.tab = dcplb_table;
-        cplb.switch_i.tab = ipdt_table;
-        cplb.switch_d.tab = dpdt_table;
-
-        cplb_data[SDRAM_KERN].end = memory_end;
-
+        i_d = 0;
+        /* Normal RAM, including MTD FS.  */
 #ifdef CONFIG_MTD_UCLINUX
-        cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
-        cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
-        cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
-# if defined(CONFIG_ROMFS_FS)
-        cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
-
-        /*
-         * The ROMFS_FS size is often not multiple of 1MB.
-         * This can cause multiple CPLB sets covering the same memory area.
-         * This will then cause multiple CPLB hit exceptions.
-         * Workaround: We ensure a contiguous memory area by extending the kernel
-         * memory section over the mtd section.
-         * For ROMFS_FS memory must be covered with ICPLBs anyways.
-         * So there is no difference between kernel and mtd memory setup.
-         */
-
-        cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
-        cplb_data[SDRAM_RAM_MTD].valid = 0;
-
-# endif
+        dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size;
 #else
-        cplb_data[SDRAM_RAM_MTD].valid = 0;
+        dcplb_bounds[i_d].eaddr = memory_end;
 #endif
+        dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
+        /* DMA uncached region.  */
+        if (DMA_UNCACHED_REGION) {
+                dcplb_bounds[i_d].eaddr = _ramend;
+                dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
+        }
+        if (_ramend != physical_mem_end) {
+                /* Reserved memory.  */
+                dcplb_bounds[i_d].eaddr = physical_mem_end;
+                dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
+                                            SDRAM_DGENERIC : SDRAM_DNON_CHBL);
+        }
+        /* Addressing hole up to the async bank.  */
+        dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
+        dcplb_bounds[i_d++].data = 0;
+        /* ASYNC banks.  */
+        dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
+        dcplb_bounds[i_d++].data = SDRAM_EBIU;
+        /* Addressing hole up to BootROM.  */
+        dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
+        dcplb_bounds[i_d++].data = 0;
+        /* BootROM -- largest one should be less than 1 meg.  */
+        dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
+        if (L2_LENGTH) {
+                /* Addressing hole up to L2 SRAM.  */
+                dcplb_bounds[i_d].eaddr = L2_START;
+                dcplb_bounds[i_d++].data = 0;
+                /* L2 SRAM.  */
+                dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
+                dcplb_bounds[i_d++].data = L2_DMEMORY;
+        }
+        dcplb_nr_bounds = i_d;
+        BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
 
-        cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
-        cplb_data[SDRAM_DMAZ].end = _ramend;
-
-        cplb_data[RES_MEM].start = _ramend;
-        cplb_data[RES_MEM].end = physical_mem_end;
-
-        if (reserved_mem_dcache_on)
-                cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
-        else
-                cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
-
-        if (reserved_mem_icache_on)
-                cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
-        else
-                cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
-
-        for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
-                if (!cplb_data[i].valid)
-                        continue;
-
-                as_1m = cplb_data[i].start % SIZE_1M;
-
-                /* We need to make sure all sections are properly 1M aligned
-                 * However between Kernel Memory and the Kernel mtd section, depending on the
-                 * rootfs size, there can be overlapping memory areas.
-                 */
-
-                if (as_1m && i != L1I_MEM && i != L1D_MEM) {
+        i_i = 0;
+        /* Normal RAM, including MTD FS.  */
 #ifdef CONFIG_MTD_UCLINUX
-                        if (i == SDRAM_RAM_MTD) {
-                                if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
-                                        cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
-                                else
-                                        cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
-                        } else
+        icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
+#else
+        icplb_bounds[i_i].eaddr = memory_end;
 #endif
-                                printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
-                                       cplb_data[i].name, cplb_data[i].start);
-                }
-
-                as = cplb_data[i].start % SIZE_4M;
-                ae = cplb_data[i].end % SIZE_4M;
-
-                if (as)
-                        a_start = cplb_data[i].start + (SIZE_4M - (as));
-                else
-                        a_start = cplb_data[i].start;
-
-                a_end = cplb_data[i].end - ae;
-
-                for (j = INITIAL_T; j <= SWITCH_T; j++) {
-
-                        switch (j) {
-                        case INITIAL_T:
-                                if (cplb_data[i].attr & INITIAL_T) {
-                                        t_i = &cplb.init_i;
-                                        t_d = &cplb.init_d;
-                                        process = 1;
-                                } else
-                                        process = 0;
-                                break;
-                        case SWITCH_T:
-                                if (cplb_data[i].attr & SWITCH_T) {
-                                        t_i = &cplb.switch_i;
-                                        t_d = &cplb.switch_d;
-                                        process = 1;
-                                } else
-                                        process = 0;
-                                break;
-                        default:
-                                        process = 0;
-                                break;
-                        }
-
-                        if (!process)
-                                continue;
-                        if (cplb_data[i].attr & I_CPLB)
-                                __fill_code_cplbtab(t_i, i, a_start, a_end);
-
-                        if (cplb_data[i].attr & D_CPLB)
-                                __fill_data_cplbtab(t_d, i, a_start, a_end);
-                }
+        icplb_bounds[i_i++].data = SDRAM_IGENERIC;
+        /* DMA uncached region.  */
+        if (DMA_UNCACHED_REGION) {
+                icplb_bounds[i_i].eaddr = _ramend;
+                icplb_bounds[i_i++].data = 0;
         }
-
-/* close tables */
-
-        close_cplbtab(&cplb.init_i);
-        close_cplbtab(&cplb.init_d);
-
-        cplb.init_i.tab[cplb.init_i.pos] = -1;
-        cplb.init_d.tab[cplb.init_d.pos] = -1;
-        cplb.switch_i.tab[cplb.switch_i.pos] = -1;
-        cplb.switch_d.tab[cplb.switch_d.pos] = -1;
-
+        if (_ramend != physical_mem_end) {
+                /* Reserved memory.  */
+                icplb_bounds[i_i].eaddr = physical_mem_end;
+                icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
+                                            SDRAM_IGENERIC : SDRAM_INON_CHBL);
+        }
+        /* Addressing hole up to BootROM.  */
+        icplb_bounds[i_i].eaddr = BOOT_ROM_START;
+        icplb_bounds[i_i++].data = 0;
+        /* BootROM -- largest one should be less than 1 meg.  */
+        icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        icplb_bounds[i_i++].data = SDRAM_IGENERIC;
+        if (L2_LENGTH) {
+                /* Addressing hole up to L2 SRAM, including the async bank.  */
+                icplb_bounds[i_i].eaddr = L2_START;
+                icplb_bounds[i_i++].data = 0;
+                /* L2 SRAM.  */
+                icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
+                icplb_bounds[i_i++].data = L2_IMEMORY;
+        }
+        icplb_nr_bounds = i_i;
+        BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
 }
-
-#endif
-
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
deleted file mode 100644
index f5cf3accef37..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
+++ /dev/null
@@ -1,646 +0,0 @@
-/*
- * File:         arch/blackfin/mach-common/cplbmgtr.S
- * Based on:
- * Author:       LG Soft India
- *
- * Created:      ?
- * Description:  CPLB replacement routine for CPLB mismatch
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
- * is_data_miss==2 => Mark as Dirty, write to the clean data page
- * is_data_miss==1 => Replace a data CPLB.
- * is_data_miss==0 => Replace an instruction CPLB.
- *
- * Returns:
- * CPLB_RELOADED        => Successfully updated CPLB table.
- * CPLB_NO_UNLOCKED     => All CPLBs are locked, so cannot be evicted.
- *                         This indicates that the CPLBs in the configuration
- *                         tablei are badly configured, as this should never
- *                         occur.
- * CPLB_NO_ADDR_MATCH   => The address being accessed, that triggered the
- *                         exception, is not covered by any of the CPLBs in
- *                         the configuration table. The application is
- *                         presumably misbehaving.
- * CPLB_PROT_VIOL       => The address being accessed, that triggered the
- *                         exception, was not a first-write to a clean Write
- *                         Back Data page, and so presumably is a genuine
- *                         violation of the page's protection attributes.
- *                         The application is misbehaving.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-ENTRY(_cplb_mgr)
-
-        [--SP]=( R7:4,P5:3 );
-
-        CC = R0 == 2;
-        IF CC JUMP .Ldcplb_write;
-
-        CC = R0 == 0;
-        IF !CC JUMP .Ldcplb_miss_compare;
-
-        /* ICPLB Miss Exception. We need to choose one of the
-        * currently-installed CPLBs, and replace it with one
-        * from the configuration table.
-        */
-
-        /* A multi-word instruction can cross a page boundary. This means the
-         * first part of the instruction can be in a valid page, but the
-         * second part is not, and hence generates the instruction miss.
-         * However, the fault address is for the start of the instruction,
-         * not the part that's in the bad page. Therefore, we have to check
-         * whether the fault address applies to a page that is already present
-         * in the table.
-         */
-
-        P4.L = LO(ICPLB_FAULT_ADDR);
-        P4.H = HI(ICPLB_FAULT_ADDR);
-
-        P1 = 16;
-        P5.L = _page_size_table;
-        P5.H = _page_size_table;
-
-        P0.L = LO(ICPLB_DATA0);
-        P0.H = HI(ICPLB_DATA0);
-        R4 = [P4];              /* Get faulting address*/
-        R6 = 64;                /* Advance past the fault address, which*/
-        R6 = R6 + R4;           /* we'll use if we find a match*/
-        R3 = ((16 << 8) | 2);   /* Extract mask, two bits at posn 16 */
-
-        R5 = 0;
-.Lisearch:
-
-        R1 = [P0-0x100];        /* Address for this CPLB */
-
-        R0 = [P0++];            /* Info for this CPLB*/
-        CC = BITTST(R0,0);      /* Is the CPLB valid?*/
-        IF !CC JUMP .Lnomatch;  /* Skip it, if not.*/
-        CC = R4 < R1(IU);       /* If fault address less than page start*/
-        IF CC JUMP .Lnomatch;   /* then skip this one.*/
-        R2 = EXTRACT(R0,R3.L) (Z);      /* Get page size*/
-        P1 = R2;
-        P1 = P5 + (P1<<2);      /* index into page-size table*/
-        R2 = [P1];              /* Get the page size*/
-        R1 = R1 + R2;           /* and add to page start, to get page end*/
-        CC = R4 < R1(IU);       /* and see whether fault addr is in page.*/
-        IF !CC R4 = R6;         /* If so, advance the address and finish loop.*/
-        IF !CC JUMP .Lisearch_done;
-.Lnomatch:
-        /* Go around again*/
-        R5 += 1;
-        CC = BITTST(R5, 4);     /* i.e CC = R5 >= 16*/
-        IF !CC JUMP .Lisearch;
-
-.Lisearch_done:
-        I0 = R4;                /* Fault address we'll search for*/
-
-        /* set up pointers */
-        P0.L = LO(ICPLB_DATA0);
-        P0.H = HI(ICPLB_DATA0);
-
-        /* The replacement procedure for ICPLBs */
-
-        P4.L = LO(IMEM_CONTROL);
-        P4.H = HI(IMEM_CONTROL);
-
-        /* Turn off CPLBs while we work, necessary according to HRM before
-         * modifying CPLB descriptors
-         */
-        R5 = [P4];              /* Control Register*/
-        BITCLR(R5,ENICPLB_P);
-        CLI R1;
-        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-        .align 8;
-        [P4] = R5;
-        SSYNC;
-        STI R1;
-
-        R1 = -1;                /* end point comparison */
-        R3 = 16;                /* counter */
-
-        /* Search through CPLBs for first non-locked entry */
-        /* Overwrite it by moving everyone else up by 1 */
-.Licheck_lock:
-        R0 = [P0++];
-        R3 = R3 + R1;
-        CC = R3 == R1;
-        IF CC JUMP .Lall_locked;
-        CC = BITTST(R0, 0);             /* an invalid entry is good */
-        IF !CC JUMP .Lifound_victim;
-        CC = BITTST(R0,1);              /* but a locked entry isn't */
-        IF CC JUMP .Licheck_lock;
-
-.Lifound_victim:
-#ifdef CONFIG_CPLB_INFO
-        R7 = [P0 - 0x104];
-        P2.L = _ipdt_table;
-        P2.H = _ipdt_table;
-        P3.L = _ipdt_swapcount_table;
-        P3.H = _ipdt_swapcount_table;
-        P3 += -4;
-.Licount:
-        R2 = [P2];      /* address from config table */
-        P2 += 8;
-        P3 += 8;
-        CC = R2==-1;
-        IF CC JUMP .Licount_done;
-        CC = R7==R2;
-        IF !CC JUMP .Licount;
-        R7 = [P3];
-        R7 += 1;
-        [P3] = R7;
-        CSYNC;
-.Licount_done:
-#endif
-        LC0=R3;
-        LSETUP(.Lis_move,.Lie_move) LC0;
-.Lis_move:
-        R0 = [P0];
-        [P0 - 4] = R0;
-        R0 = [P0 - 0x100];
-        [P0-0x104] = R0;
-.Lie_move:
-        P0+=4;
-
-        /* Clear ICPLB_DATA15, in case we don't find a replacement
-         * otherwise, we would have a duplicate entry, and will crash
-         */
-        R0 = 0;
-        [P0 - 4] = R0;
-
-        /* We've made space in the ICPLB table, so that ICPLB15
-         * is now free to be overwritten. Next, we have to determine
-         * which CPLB we need to install, from the configuration
-         * table. This is a matter of getting the start-of-page
-         * addresses and page-lengths from the config table, and
-         * determining whether the fault address falls within that
-         * range.
-         */
-
-        P2.L = _ipdt_table;
-        P2.H = _ipdt_table;
-#ifdef  CONFIG_CPLB_INFO
-        P3.L = _ipdt_swapcount_table;
-        P3.H = _ipdt_swapcount_table;
-        P3 += -8;
-#endif
-        P0.L = _page_size_table;
-        P0.H = _page_size_table;
-
-        /* Retrieve our fault address (which may have been advanced
-         * because the faulting instruction crossed a page boundary).
-         */
-
-        R0 = I0;
-
-        /* An extraction pattern, to get the page-size bits from
-         * the CPLB data entry. Bits 16-17, so two bits at posn 16.
-         */
-
-        R1 = ((16<<8)|2);
-.Linext:        R4 = [P2++];    /* address from config table */
-        R2 = [P2++];    /* data from config table */
-#ifdef  CONFIG_CPLB_INFO
-        P3 += 8;
-#endif
-
-        CC = R4 == -1;  /* End of config table*/
-        IF CC JUMP .Lno_page_in_table;
-
-        /* See if failed address > start address */
-        CC = R4 <= R0(IU);
-        IF !CC JUMP .Linext;
-
-        /* extract page size (17:16)*/
-        R3 = EXTRACT(R2, R1.L) (Z);
-
-        /* add page size to addr to get range */
-
-        P5 = R3;
-        P5 = P0 + (P5 << 2);    /* scaled, for int access*/
-        R3 = [P5];
-        R3 = R3 + R4;
-
-        /* See if failed address < (start address + page size) */
-        CC = R0 < R3(IU);
-        IF !CC JUMP .Linext;
-
-        /* We've found a CPLB in the config table that covers
-         * the faulting address, so install this CPLB into the
-         * last entry of the table.
-         */
-
-        P1.L = LO(ICPLB_DATA15);                /* ICPLB_DATA15 */
-        P1.H = HI(ICPLB_DATA15);
-        [P1] = R2;
-        [P1-0x100] = R4;
-#ifdef  CONFIG_CPLB_INFO
-        R3 = [P3];
-        R3 += 1;
-        [P3] = R3;
-#endif
-
-        /* P4 points to IMEM_CONTROL, and R5 contains its old
-         * value, after we disabled ICPLBS. Re-enable them.
-         */
-
-        BITSET(R5,ENICPLB_P);
-        CLI R2;
-        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-        .align 8;
-        [P4] = R5;
-        SSYNC;
-        STI R2;
-
-        ( R7:4,P5:3 ) = [SP++];
-        R0 = CPLB_RELOADED;
-        RTS;
-
-/* FAILED CASES*/
-.Lno_page_in_table:
-        R0 = CPLB_NO_ADDR_MATCH;
-        JUMP .Lfail_ret;
-
-.Lall_locked:
-        R0 = CPLB_NO_UNLOCKED;
-        JUMP .Lfail_ret;
-
-.Lprot_violation:
-        R0 = CPLB_PROT_VIOL;
-
-.Lfail_ret:
-        /* Make sure we turn protection/cache back on, even in the failing case */
-        BITSET(R5,ENICPLB_P);
-        CLI R2;
-        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-        .align 8;
-        [P4] = R5;
-        SSYNC;
-        STI R2;
-
-        ( R7:4,P5:3 ) = [SP++];
-        RTS;
-
-.Ldcplb_write:
-
-        /* if a DCPLB is marked as write-back (CPLB_WT==0), and
-         * it is clean (CPLB_DIRTY==0), then a write to the
-         * CPLB's page triggers a protection violation. We have to
-         * mark the CPLB as dirty, to indicate that there are
-         * pending writes associated with the CPLB.
-         */
-
-        P4.L = LO(DCPLB_STATUS);
-        P4.H = HI(DCPLB_STATUS);
-        P3.L = LO(DCPLB_DATA0);
-        P3.H = HI(DCPLB_DATA0);
-        R5 = [P4];
-
-        /* A protection violation can be caused by more than just writes
-         * to a clean WB page, so we have to ensure that:
-         * - It's a write
-         * - to a clean WB page
-         * - and is allowed in the mode the access occurred.
-         */
-
-        CC = BITTST(R5, 16);    /* ensure it was a write*/
-        IF !CC JUMP .Lprot_violation;
-
-        /* to check the rest, we have to retrieve the DCPLB.*/
-
-        /* The low half of DCPLB_STATUS is a bit mask*/
-
-        R2 = R5.L (Z);  /* indicating which CPLB triggered the event.*/
-        R3 = 30;        /* so we can use this to determine the offset*/
-        R2.L = SIGNBITS R2;
-        R2 = R2.L (Z);  /* into the DCPLB table.*/
-        R3 = R3 - R2;
-        P4 = R3;
-        P3 = P3 + (P4<<2);
-        R3 = [P3];      /* Retrieve the CPLB*/
-
-        /* Now we can check whether it's a clean WB page*/
-
-        CC = BITTST(R3, 14);    /* 0==WB, 1==WT*/
-        IF CC JUMP .Lprot_violation;
-        CC = BITTST(R3, 7);     /* 0 == clean, 1 == dirty*/
-        IF CC JUMP .Lprot_violation;
-
-        /* Check whether the write is allowed in the mode that was active.*/
-
-        R2 = 1<<3;              /* checking write in user mode*/
-        CC = BITTST(R5, 17);    /* 0==was user, 1==was super*/
-        R5 = CC;
-        R2 <<= R5;              /* if was super, check write in super mode*/
-        R2 = R3 & R2;
-        CC = R2 == 0;
-        IF CC JUMP .Lprot_violation;
-
-        /* It's a genuine write-to-clean-page.*/
-
-        BITSET(R3, 7);          /* mark as dirty*/
-        [P3] = R3;              /* and write back.*/
-        NOP;
-        CSYNC;
-        ( R7:4,P5:3 ) = [SP++];
-        R0 = CPLB_RELOADED;
-        RTS;
-
-.Ldcplb_miss_compare:
-
-        /* Data CPLB Miss event. We need to choose a CPLB to
-         * evict, and then locate a new CPLB to install from the
-         * config table, that covers the faulting address.
-         */
-
-        P1.L = LO(DCPLB_DATA15);
-        P1.H = HI(DCPLB_DATA15);
-
-        P4.L = LO(DCPLB_FAULT_ADDR);
-        P4.H = HI(DCPLB_FAULT_ADDR);
-        R4 = [P4];
-        I0 = R4;
-
-        /* The replacement procedure for DCPLBs*/
-
-        R6 = R1;        /* Save for later*/
-
-        /* Turn off CPLBs while we work.*/
-        P4.L = LO(DMEM_CONTROL);
-        P4.H = HI(DMEM_CONTROL);
-        R5 = [P4];
-        BITCLR(R5,ENDCPLB_P);
-        CLI R0;
-        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
-        .align 8;
-        [P4] = R5;
-        SSYNC;
-        STI R0;
-
-        /* Start looking for a CPLB to evict. Our order of preference
-         * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
-         * are no good.
-         */
-
-        I1.L = LO(DCPLB_DATA0);
-        I1.H = HI(DCPLB_DATA0);
-        P1 = 2;
-        P2 = 16;
-        I2.L = _dcplb_preference;
-        I2.H = _dcplb_preference;
-        LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1;
-.Lsdsearch1:
-        R0 = [I2++];            /* Get the bits we're interested in*/
-        P0 = I1;                /* Go back to start of table*/
-        LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2;
-.Lsdsearch2:
-        R1 = [P0++];            /* Fetch each installed CPLB in turn*/
-        R2 = R1 & R0;           /* and test for interesting bits.*/
-        CC = R2 == 0;           /* If none are set, it'll do.*/
-        IF !CC JUMP .Lskip_stack_check;
-
-        R2 = [P0 - 0x104];      /* R2 - PageStart */
-        P3.L = _page_size_table; /* retrieve end address */
-        P3.H = _page_size_table; /* retrieve end address */
-        R3 = 0x1002;            /* 16th - position, 2 bits -length */
-#if ANOMALY_05000209
-        nop;                    /* Anomaly 05000209 */
-#endif
-        R7 = EXTRACT(R1,R3.l);
-        R7 = R7 << 2;           /* Page size index offset */
-        P5 = R7;
-        P3 = P3 + P5;
-        R7 = [P3];              /* page size in bytes */
-
-        R7 = R2 + R7;           /* R7 - PageEnd */
-        R4 = SP;                /* Test SP is in range */
-
-        CC = R7 < R4;           /* if PageEnd < SP */
-        IF CC JUMP .Ldfound_victim;
-        R3 = 0x284;             /* stack length from start of trap till
-                                 * the point.
-                                 * 20 stack locations for future modifications
-                                 */
-        R4 = R4 + R3;
-        CC = R4 < R2;           /* if SP + stacklen < PageStart */
-        IF CC JUMP .Ldfound_victim;
-.Lskip_stack_check:
-
-.Ledsearch2: NOP;
-.Ledsearch1: NOP;
-
-        /* If we got here, we didn't find a DCPLB we considered
-         * replacable, which means all of them were locked.
-         */
-
-        JUMP .Lall_locked;
-.Ldfound_victim:
-
-#ifdef CONFIG_CPLB_INFO
-        R7 = [P0 - 0x104];
-        P2.L = _dpdt_table;
-        P2.H = _dpdt_table;
-        P3.L = _dpdt_swapcount_table;
-        P3.H = _dpdt_swapcount_table;
-        P3 += -4;
-.Ldicount:
-        R2 = [P2];
-        P2 += 8;
-        P3 += 8;
-        CC = R2==-1;
-        IF CC JUMP .Ldicount_done;
-        CC = R7==R2;
-        IF !CC JUMP .Ldicount;
-        R7 = [P3];
-        R7 += 1;
-        [P3] = R7;
-.Ldicount_done:
-#endif
-
-        /* Clean down the hardware loops*/
-        R2 = 0;
-        LC1 = R2;
-        LC0 = R2;
-
-        /* There's a suitable victim in [P0-4] (because we've
-         * advanced already).
-         */
-
-.LDdoverwrite:
-
-        /* [P0-4] is a suitable victim CPLB, so we want to
-         * overwrite it by moving all the following CPLBs
-         * one space closer to the start.
-         */
-
-        R1.L = LO(DCPLB_DATA16);                /* DCPLB_DATA15 + 4 */
-        R1.H = HI(DCPLB_DATA16);
-        R0 = P0;
-
-        /* If the victim happens to be in DCPLB15,
-         * we don't need to move anything.
-         */
-
-        CC = R1 == R0;
-        IF CC JUMP .Lde_moved;
-        R1 = R1 - R0;
-        R1 >>= 2;
-        P1 = R1;
-        LSETUP(.Lds_move, .Lde_move) LC0=P1;
-.Lds_move:
-        R0 = [P0++];    /* move data */
-        [P0 - 8] = R0;
-        R0 = [P0-0x104] /* move address */
-.Lde_move:
-         [P0-0x108] = R0;
-
-.Lde_moved:
-        NOP;
-
-        /* Clear DCPLB_DATA15, in case we don't find a replacement
-         * otherwise, we would have a duplicate entry, and will crash
-         */
-        R0 = 0;
-        [P0 - 0x4] = R0;
-
-        /* We've now made space in DCPLB15 for the new CPLB to be
-         * installed. The next stage is to locate a CPLB in the
-         * config table that covers the faulting address.
-         */
-
-        R0 = I0;                /* Our faulting address */
-
-        P2.L = _dpdt_table;
-        P2.H = _dpdt_table;
-#ifdef  CONFIG_CPLB_INFO
-        P3.L = _dpdt_swapcount_table;
-        P3.H = _dpdt_swapcount_table;
-        P3 += -8;
-#endif
-
-        P1.L = _page_size_table;
-        P1.H = _page_size_table;
-
-        /* An extraction pattern, to retrieve bits 17:16.*/
-
-        R1 = (16<<8)|2;
-.Ldnext:        R4 = [P2++];    /* address */
-        R2 = [P2++];    /* data */
-#ifdef  CONFIG_CPLB_INFO
-        P3 += 8;
-#endif
-
-        CC = R4 == -1;
-        IF CC JUMP .Lno_page_in_table;
-
-        /* See if failed address > start address */
-        CC = R4 <= R0(IU);
-        IF !CC JUMP .Ldnext;
-
-        /* extract page size (17:16)*/
-        R3 = EXTRACT(R2, R1.L) (Z);
-
-        /* add page size to addr to get range */
-
-        P5 = R3;
-        P5 = P1 + (P5 << 2);
-        R3 = [P5];
-        R3 = R3 + R4;
-
-        /* See if failed address < (start address + page size) */
-        CC = R0 < R3(IU);
-        IF !CC JUMP .Ldnext;
-
-        /* We've found the CPLB that should be installed, so
-         * write it into CPLB15, masking off any caching bits
-         * if necessary.
-         */
-
-        P1.L = LO(DCPLB_DATA15);
-        P1.H = HI(DCPLB_DATA15);
-
-        /* If the DCPLB has cache bits set, but caching hasn't
-         * been enabled, then we want to mask off the cache-in-L1
-         * bit before installing. Moreover, if caching is off, we
-         * also want to ensure that the DCPLB has WT mode set, rather
-         * than WB, since WB pages still trigger first-write exceptions
-         * even when not caching is off, and the page isn't marked as
-         * cachable. Finally, we could mark the page as clean, not dirty,
-         * but we choose to leave that decision to the user; if the user
-         * chooses to have a CPLB pre-defined as dirty, then they always
-         * pay the cost of flushing during eviction, but don't pay the
-         * cost of first-write exceptions to mark the page as dirty.
-         */
-
-#ifdef CONFIG_BFIN_WT
-        BITSET(R6, 14);         /* Set WT*/
-#endif
-
-        [P1] = R2;
-        [P1-0x100] = R4;
-#ifdef  CONFIG_CPLB_INFO
-        R3 = [P3];
-        R3 += 1;
-        [P3] = R3;
-#endif
-
-        /* We've installed the CPLB, so re-enable CPLBs. P4
-         * points to DMEM_CONTROL, and R5 is the value we
-         * last wrote to it, when we were disabling CPLBs.
-         */
-
-        BITSET(R5,ENDCPLB_P);
-        CLI R2;
-        .align 8;
-        [P4] = R5;
-        SSYNC;
-        STI R2;
-
-        ( R7:4,P5:3 ) = [SP++];
-        R0 = CPLB_RELOADED;
-        RTS;
-ENDPROC(_cplb_mgr)
-
-.data
-.align 4;
-_page_size_table:
-.byte4  0x00000400;     /* 1K */
-.byte4  0x00001000;     /* 4K */
-.byte4  0x00100000;     /* 1M */
-.byte4  0x00400000;     /* 4M */
-
-.align 4;
-_dcplb_preference:
-.byte4  0x00000001;     /* valid bit */
-.byte4  0x00000002;     /* lock bit */
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
new file mode 100644
index 000000000000..376249ab2694
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -0,0 +1,283 @@
+/*
+ * File:         arch/blackfin/kernel/cplb-nompu-c/cplbmgr.c
+ * Based on:     arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+ * Author:       Michael McTernan <mmcternan@airvana.com>
+ *
+ * Created:      01Nov2008
+ * Description:  CPLB miss handler.
+ *
+ * Modified:
+ *               Copyright 2008 Airvana Inc.
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <asm/blackfin.h>
+#include <asm/cplbinit.h>
+#include <asm/cplb.h>
+#include <asm/mmu_context.h>
+
+/*
+ * WARNING
+ *
+ * This file is compiled with certain -ffixed-reg options.  We have to
+ * make sure not to call any functions here that could clobber these
+ * registers.
+ */
+
+int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
+int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
+int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
+
+#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
+#define MGR_ATTR __attribute__((l1_text))
+#else
+#define MGR_ATTR
+#endif
+
+/*
+ * We're in an exception handler.  The normal cli nop nop workaround
+ * isn't going to do very much, as the only thing that can interrupt
+ * us is an NMI, and the cli isn't going to stop that.
+ */
+#define NOWA_SSYNC __asm__ __volatile__ ("ssync;")
+
+/* Anomaly handlers provide SSYNCs, so avoid extra if anomaly is present */
+#if ANOMALY_05000125
+
+#define bfin_write_DMEM_CONTROL_SSYNC(v)    bfin_write_DMEM_CONTROL(v)
+#define bfin_write_IMEM_CONTROL_SSYNC(v)    bfin_write_IMEM_CONTROL(v)
+
+#else
+
+#define bfin_write_DMEM_CONTROL_SSYNC(v) \
+    do { NOWA_SSYNC; bfin_write_DMEM_CONTROL(v); NOWA_SSYNC; } while (0)
+#define bfin_write_IMEM_CONTROL_SSYNC(v) \
+    do { NOWA_SSYNC; bfin_write_IMEM_CONTROL(v); NOWA_SSYNC; } while (0)
+
+#endif
+
+static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
+                                    unsigned long addr)
+{
+        unsigned long ctrl = bfin_read_DMEM_CONTROL();
+        bfin_write_DMEM_CONTROL_SSYNC(ctrl & ~ENDCPLB);
+        bfin_write32(DCPLB_DATA0 + idx * 4, data);
+        bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
+        bfin_write_DMEM_CONTROL_SSYNC(ctrl);
+
+#ifdef CONFIG_CPLB_INFO
+        dcplb_tbl[cpu][idx].addr = addr;
+        dcplb_tbl[cpu][idx].data = data;
+#endif
+}
+
+static inline void write_icplb_data(int cpu, int idx, unsigned long data,
+                                    unsigned long addr)
+{
+        unsigned long ctrl = bfin_read_IMEM_CONTROL();
+
+        bfin_write_IMEM_CONTROL_SSYNC(ctrl & ~ENICPLB);
+        bfin_write32(ICPLB_DATA0 + idx * 4, data);
+        bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
+        bfin_write_IMEM_CONTROL_SSYNC(ctrl);
+
+#ifdef CONFIG_CPLB_INFO
+        icplb_tbl[cpu][idx].addr = addr;
+        icplb_tbl[cpu][idx].data = data;
+#endif
+}
+
+/*
+ * Given the contents of the status register, return the index of the
+ * CPLB that caused the fault.
+ */
+static inline int faulting_cplb_index(int status)
+{
+        int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
+        return 30 - signbits;
+}
+
+/*
+ * Given the contents of the status register and the DCPLB_DATA contents,
+ * return true if a write access should be permitted.
+ */
+static inline int write_permitted(int status, unsigned long data)
+{
+        if (status & FAULT_USERSUPV)
+                return !!(data & CPLB_SUPV_WR);
+        else
+                return !!(data & CPLB_USER_WR);
+}
+
+/* Counters to implement round-robin replacement.  */
+static int icplb_rr_index[NR_CPUS] PDT_ATTR;
+static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
+
+/*
+ * Find an ICPLB entry to be evicted and return its index.
+ */
+static int evict_one_icplb(int cpu)
+{
+        int i = first_switched_icplb + icplb_rr_index[cpu];
+        if (i >= MAX_CPLBS) {
+                i -= MAX_CPLBS - first_switched_icplb;
+                icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
+        }
+        icplb_rr_index[cpu]++;
+        return i;
+}
+
+static int evict_one_dcplb(int cpu)
+{
+        int i = first_switched_dcplb + dcplb_rr_index[cpu];
+        if (i >= MAX_CPLBS) {
+                i -= MAX_CPLBS - first_switched_dcplb;
+                dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
+        }
+        dcplb_rr_index[cpu]++;
+        return i;
+}
+
+MGR_ATTR static int icplb_miss(int cpu)
+{
+        unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
+        int status = bfin_read_ICPLB_STATUS();
+        int idx;
+        unsigned long i_data, base, addr1, eaddr;
+
+        nr_icplb_miss[cpu]++;
+        if (unlikely(status & FAULT_USERSUPV))
+                nr_icplb_supv_miss[cpu]++;
+
+        base = 0;
+        for (idx = 0; idx < icplb_nr_bounds; idx++) {
+                eaddr = icplb_bounds[idx].eaddr;
+                if (addr < eaddr)
+                        break;
+                base = eaddr;
+        }
+        if (unlikely(idx == icplb_nr_bounds))
+                return CPLB_NO_ADDR_MATCH;
+
+        i_data = icplb_bounds[idx].data;
+        if (unlikely(i_data == 0))
+                return CPLB_NO_ADDR_MATCH;
+
+        addr1 = addr & ~(SIZE_4M - 1);
+        addr &= ~(SIZE_1M - 1);
+        i_data |= PAGE_SIZE_1MB;
+        if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
+                /*
+                 * This works because
+                 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
+                 */
+                i_data |= PAGE_SIZE_4MB;
+                addr = addr1;
+        }
+
+        /* Pick entry to evict */
+        idx = evict_one_icplb(cpu);
+
+        write_icplb_data(cpu, idx, i_data, addr);
+
+        return CPLB_RELOADED;
+}
+
+MGR_ATTR static int dcplb_miss(int cpu)
+{
+        unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
+        int status = bfin_read_DCPLB_STATUS();
+        int idx;
+        unsigned long d_data, base, addr1, eaddr;
+
+        nr_dcplb_miss[cpu]++;
+        if (unlikely(status & FAULT_USERSUPV))
+                nr_dcplb_supv_miss[cpu]++;
+
+        base = 0;
+        for (idx = 0; idx < dcplb_nr_bounds; idx++) {
+                eaddr = dcplb_bounds[idx].eaddr;
+                if (addr < eaddr)
+                        break;
+                base = eaddr;
+        }
+        if (unlikely(idx == dcplb_nr_bounds))
+                return CPLB_NO_ADDR_MATCH;
+
+        d_data = dcplb_bounds[idx].data;
+        if (unlikely(d_data == 0))
+                return CPLB_NO_ADDR_MATCH;
+
+        addr1 = addr & ~(SIZE_4M - 1);
+        addr &= ~(SIZE_1M - 1);
+        d_data |= PAGE_SIZE_1MB;
+        if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
+                /*
+                 * This works because
+                 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
+                 */
+                d_data |= PAGE_SIZE_4MB;
+                addr = addr1;
+        }
+
+        /* Pick entry to evict */
+        idx = evict_one_dcplb(cpu);
+
+        write_dcplb_data(cpu, idx, d_data, addr);
+
+        return CPLB_RELOADED;
+}
+
+MGR_ATTR static noinline int dcplb_protection_fault(int cpu)
+{
+        int status = bfin_read_DCPLB_STATUS();
+
+        nr_dcplb_prot[cpu]++;
+
+        if (likely(status & FAULT_RW)) {
+                int idx = faulting_cplb_index(status);
+                unsigned long regaddr = DCPLB_DATA0 + idx * 4;
+                unsigned long data = bfin_read32(regaddr);
+
+                /* Check if fault is to dirty a clean page */
+                if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
+                    write_permitted(status, data)) {
+
+                        dcplb_tbl[cpu][idx].data = data;
+                        bfin_write32(regaddr, data);
+                        return CPLB_RELOADED;
+                }
+        }
+
+        return CPLB_PROT_VIOL;
+}
+
+MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
+{
+        int cause = seqstat & 0x3f;
+        unsigned int cpu = smp_processor_id();
+        switch (cause) {
+        case 0x2C:
+                return icplb_miss(cpu);
+        case 0x26:
+                return dcplb_miss(cpu);
+        default:
+                if (unlikely(cause == 0x23))
+                        return dcplb_protection_fault(cpu);
+
+                return CPLB_UNKNOWN_ERR;
+        }
+}
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
new file mode 100644
index 000000000000..64d78300dd08
--- /dev/null
+++ b/arch/blackfin/kernel/cplbinfo.c
@@ -0,0 +1,177 @@
+/*
+ * arch/blackfin/kernel/cplbinfo.c - display CPLB status
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+
+#include <asm/cplbinit.h>
+#include <asm/blackfin.h>
+
+static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" };
+#define page(flags)    (((flags) & 0x30000) >> 16)
+#define strpage(flags) page_strtbl[page(flags)]
+
+struct cplbinfo_data {
+        loff_t pos;
+        char cplb_type;
+        u32 mem_control;
+        struct cplb_entry *tbl;
+        int switched;
+};
+
+static void cplbinfo_print_header(struct seq_file *m)
+{
+        seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
+}
+
+static int cplbinfo_nomore(struct cplbinfo_data *cdata)
+{
+        return cdata->pos >= MAX_CPLBS;
+}
+
+static int cplbinfo_show(struct seq_file *m, void *p)
+{
+        struct cplbinfo_data *cdata;
+        unsigned long data, addr;
+        loff_t pos;
+
+        cdata = p;
+        pos = cdata->pos;
+        addr = cdata->tbl[pos].addr;
+        data = cdata->tbl[pos].data;
+
+        seq_printf(m,
+                "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n",
+                (int)pos, addr, data, strpage(data),
+                (data & CPLB_USER_RD) ? 'Y' : 'N',
+                (data & CPLB_USER_WR) ? 'Y' : 'N',
+                (data & CPLB_SUPV_WR) ? 'Y' : 'N',
+                pos < cdata->switched ? 'N' : 'Y');
+
+        return 0;
+}
+
+static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu)
+{
+        if (cdata->cplb_type == 'I') {
+                cdata->mem_control = bfin_read_IMEM_CONTROL();
+                cdata->tbl = icplb_tbl[cpu];
+                cdata->switched = first_switched_icplb;
+        } else {
+                cdata->mem_control = bfin_read_DMEM_CONTROL();
+                cdata->tbl = dcplb_tbl[cpu];
+                cdata->switched = first_switched_dcplb;
+        }
+}
+
+static void *cplbinfo_start(struct seq_file *m, loff_t *pos)
+{
+        struct cplbinfo_data *cdata = m->private;
+
+        if (!*pos) {
+                seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type,
+                        (cdata->mem_control & ENDCPLB ? "en" : "dis"),
+                        cdata->mem_control);
+                cplbinfo_print_header(m);
+        } else if (cplbinfo_nomore(cdata))
+                return NULL;
+
+        get_cpu();
+        return cdata;
+}
+
+static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos)
+{
+        struct cplbinfo_data *cdata = p;
+        cdata->pos = ++(*pos);
+        if (cplbinfo_nomore(cdata))
+                return NULL;
+        else
+                return cdata;
+}
+
+static void cplbinfo_stop(struct seq_file *m, void *p)
+{
+        put_cpu();
+}
+
+static const struct seq_operations cplbinfo_sops = {
+        .start = cplbinfo_start,
+        .next  = cplbinfo_next,
+        .stop  = cplbinfo_stop,
+        .show  = cplbinfo_show,
+};
+
+static int cplbinfo_open(struct inode *inode, struct file *file)
+{
+        char buf[256], *path, *p;
+        unsigned int cpu;
+        char *s_cpu, *s_cplb;
+        int ret;
+        struct seq_file *m;
+        struct cplbinfo_data *cdata;
+
+        path = d_path(&file->f_path, buf, sizeof(buf));
+        if (IS_ERR(path))
+                return PTR_ERR(path);
+        s_cpu = strstr(path, "/cpu");
+        s_cplb = strrchr(path, '/');
+        if (!s_cpu || !s_cplb)
+                return -EINVAL;
+
+        cpu = simple_strtoul(s_cpu + 4, &p, 10);
+        if (!cpu_online(cpu))
+                return -ENODEV;
+
+        ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata));
+        if (ret)
+                return ret;
+        m = file->private_data;
+        cdata = m->private;
+
+        cdata->pos = 0;
+        cdata->cplb_type = toupper(s_cplb[1]);
+        cplbinfo_seq_init(cdata, cpu);
+
+        return 0;
+}
+
+static const struct file_operations cplbinfo_fops = {
+        .open    = cplbinfo_open,
+        .read    = seq_read,
+        .llseek  = seq_lseek,
+        .release = seq_release_private,
+};
+
+static int __init cplbinfo_init(void)
+{
+        struct proc_dir_entry *cplb_dir, *cpu_dir;
+        char buf[10];
+        unsigned int cpu;
+
+        cplb_dir = proc_mkdir("cplbinfo", NULL);
+        if (!cplb_dir)
+                return -ENOMEM;
+
+        for_each_possible_cpu(cpu) {
+                sprintf(buf, "cpu%i", cpu);
+                cpu_dir = proc_mkdir(buf, cplb_dir);
+                if (!cpu_dir)
+                        return -ENOMEM;
+
+                proc_create("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops);
+                proc_create("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops);
+        }
+
+        return 0;
+}
+late_initcall(cplbinfo_init);
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 1f4e3d2e0901..c8ad051742e2 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -105,10 +105,10 @@ static struct console * __init earlyserial_init(char *buf)
                 cflag |= CS5;
                 break;
         case 6:
-                cflag |= CS5;
+                cflag |= CS6;
                 break;
         case 7:
-                cflag |= CS5;
+                cflag |= CS7;
                 break;
         default:
                 cflag |= CS8;
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
index faea88ebb2ef..a9cfba9946b5 100644
--- a/arch/blackfin/kernel/entry.S
+++ b/arch/blackfin/kernel/entry.S
@@ -30,6 +30,7 @@
 #include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/errno.h>
+#include <asm/blackfin.h>
 #include <asm/asm-offsets.h>
 
 #include <asm/context.S>
@@ -41,6 +42,10 @@
 #endif
 
 ENTRY(_ret_from_fork)
+#ifdef CONFIG_IPIPE
+        [--sp] = reti;          /* IRQs on. */
+        SP += 4;
+#endif /* CONFIG_IPIPE */
         SP += -12;
         call _schedule_tail;
         SP += 12;
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
index 4b03ba025488..0d2d9e0968c8 100644
--- a/arch/blackfin/kernel/fixed_code.S
+++ b/arch/blackfin/kernel/fixed_code.S
@@ -8,10 +8,12 @@
  * BF561 SMP).
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <linux/unistd.h>
 #include <asm/entry.h>
 
-.text
+__INIT
+
 ENTRY(_fixed_code_start)
 
 .align 16
@@ -144,3 +146,5 @@ ENTRY(_safe_user_instruction)
 ENDPROC(_safe_user_instruction)
 
 ENTRY(_fixed_code_end)
+
+__FINIT
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
new file mode 100644
index 000000000000..339be5a3ae6a
--- /dev/null
+++ b/arch/blackfin/kernel/ipipe.c
@@ -0,0 +1,428 @@
+/* -*- linux-c -*-
+ * linux/arch/blackfin/kernel/ipipe.c
+ *
+ * Copyright (C) 2005-2007 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Architecture-dependent I-pipe support for the Blackfin.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+#include <linux/bitops.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/kthread.h>
+#include <asm/unistd.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+
+static int create_irq_threads;
+
+DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
+
+static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
+
+static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
+
+asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
+
+static void __ipipe_no_irqtail(void);
+
+unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
+EXPORT_SYMBOL(__ipipe_irq_tail_hook);
+
+unsigned long __ipipe_core_clock;
+EXPORT_SYMBOL(__ipipe_core_clock);
+
+unsigned long __ipipe_freq_scale;
+EXPORT_SYMBOL(__ipipe_freq_scale);
+
+atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
+
+unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags;
+EXPORT_SYMBOL(__ipipe_irq_lvmask);
+
+static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
+{
+        desc->ipipe_ack(irq, desc);
+}
+
+/*
+ * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
+ * interrupts are off, and secondary CPUs are still lost in space.
+ */
+void __ipipe_enable_pipeline(void)
+{
+        unsigned irq;
+
+        __ipipe_core_clock = get_cclk(); /* Fetch this once. */
+        __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
+
+        for (irq = 0; irq < NR_IRQS; ++irq)
+                ipipe_virtualize_irq(ipipe_root_domain,
+                                     irq,
+                                     (ipipe_irq_handler_t)&asm_do_IRQ,
+                                     NULL,
+                                     &__ipipe_ack_irq,
+                                     IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
+}
+
+/*
+ * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
+ * interrupt protection log is maintained here for each domain. Hw
+ * interrupts are masked on entry.
+ */
+void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
+{
+        struct ipipe_domain *this_domain, *next_domain;
+        struct list_head *head, *pos;
+        int m_ack, s = -1;
+
+        /*
+         * Software-triggered IRQs do not need any ack.  The contents
+         * of the register frame should only be used when processing
+         * the timer interrupt, but not for handling any other
+         * interrupt.
+         */
+        m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
+
+        this_domain = ipipe_current_domain;
+
+        if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
+                head = &this_domain->p_link;
+        else {
+                head = __ipipe_pipeline.next;
+                next_domain = list_entry(head, struct ipipe_domain, p_link);
+                if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
+                        if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
+                                next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
+                        if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
+                                s = __test_and_set_bit(IPIPE_STALL_FLAG,
+                                                       &ipipe_root_cpudom_var(status));
+                        __ipipe_dispatch_wired(next_domain, irq);
+                                goto finalize;
+                        return;
+                }
+        }
+
+        /* Ack the interrupt. */
+
+        pos = head;
+
+        while (pos != &__ipipe_pipeline) {
+                next_domain = list_entry(pos, struct ipipe_domain, p_link);
+                /*
+                 * For each domain handling the incoming IRQ, mark it
+                 * as pending in its log.
+                 */
+                if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
+                        /*
+                         * Domains that handle this IRQ are polled for
+                         * acknowledging it by decreasing priority
+                         * order. The interrupt must be made pending
+                         * _first_ in the domain's status flags before
+                         * the PIC is unlocked.
+                         */
+                        __ipipe_set_irq_pending(next_domain, irq);
+
+                        if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
+                                next_domain->irqs[irq].acknowledge(irq, irq_desc + irq);
+                                m_ack = 1;
+                        }
+                }
+
+                /*
+                 * If the domain does not want the IRQ to be passed
+                 * down the interrupt pipe, exit the loop now.
+                 */
+                if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
+                        break;
+
+                pos = next_domain->p_link.next;
+        }
+
+        /*
+         * Now walk the pipeline, yielding control to the highest
+         * priority domain that has pending interrupt(s) or
+         * immediately to the current domain if the interrupt has been
+         * marked as 'sticky'. This search does not go beyond the
+         * current domain in the pipeline. We also enforce the
+         * additional root stage lock (blackfin-specific). */
+
+        if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags))
+                s = __test_and_set_bit(IPIPE_STALL_FLAG,
+                                       &ipipe_root_cpudom_var(status));
+finalize:
+
+        __ipipe_walk_pipeline(head);
+
+        if (!s)
+                __clear_bit(IPIPE_STALL_FLAG,
+                            &ipipe_root_cpudom_var(status));
+}
+
+int __ipipe_check_root(void)
+{
+        return ipipe_root_domain_p;
+}
+
+void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        int prio = desc->ic_prio;
+
+        desc->depth = 0;
+        if (ipd != &ipipe_root &&
+            atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
+                __set_bit(prio, &__ipipe_irq_lvmask);
+}
+EXPORT_SYMBOL(__ipipe_enable_irqdesc);
+
+void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        int prio = desc->ic_prio;
+
+        if (ipd != &ipipe_root &&
+            atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
+                __clear_bit(prio, &__ipipe_irq_lvmask);
+}
+EXPORT_SYMBOL(__ipipe_disable_irqdesc);
+
+void __ipipe_stall_root_raw(void)
+{
+        /*
+         * This code is called by the ins{bwl} routines (see
+         * arch/blackfin/lib/ins.S), which are heavily used by the
+         * network stack. It masks all interrupts but those handled by
+         * non-root domains, so that we keep decent network transfer
+         * rates for Linux without inducing pathological jitter for
+         * the real-time domain.
+         */
+        __asm__ __volatile__ ("sti %0;" : : "d"(__ipipe_irq_lvmask));
+
+        __set_bit(IPIPE_STALL_FLAG,
+                  &ipipe_root_cpudom_var(status));
+}
+
+void __ipipe_unstall_root_raw(void)
+{
+        __clear_bit(IPIPE_STALL_FLAG,
+                    &ipipe_root_cpudom_var(status));
+
+        __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags));
+}
+
+int __ipipe_syscall_root(struct pt_regs *regs)
+{
+        unsigned long flags;
+
+        /* We need to run the IRQ tail hook whenever we don't
+         * propagate a syscall to higher domains, because we know that
+         * important operations might be pending there (e.g. Xenomai
+         * deferred rescheduling). */
+
+        if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) {
+                void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
+                hook();
+                return 0;
+        }
+
+        /*
+         * This routine either returns:
+         * 0 -- if the syscall is to be passed to Linux;
+         * 1 -- if the syscall should not be passed to Linux, and no
+         * tail work should be performed;
+         * -1 -- if the syscall should not be passed to Linux but the
+         * tail work has to be performed (for handling signals etc).
+         */
+
+        if (__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) &&
+            __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs) > 0) {
+                if (ipipe_root_domain_p && !in_atomic()) {
+                        /*
+                         * Sync pending VIRQs before _TIF_NEED_RESCHED
+                         * is tested.
+                         */
+                        local_irq_save_hw(flags);
+                        if ((ipipe_root_cpudom_var(irqpend_himask) & IPIPE_IRQMASK_VIRT) != 0)
+                                __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
+                        local_irq_restore_hw(flags);
+                        return -1;
+                }
+                return 1;
+        }
+
+        return 0;
+}
+
+unsigned long ipipe_critical_enter(void (*syncfn) (void))
+{
+        unsigned long flags;
+
+        local_irq_save_hw(flags);
+
+        return flags;
+}
+
+void ipipe_critical_exit(unsigned long flags)
+{
+        local_irq_restore_hw(flags);
+}
+
+static void __ipipe_no_irqtail(void)
+{
+}
+
+int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
+{
+        info->ncpus = num_online_cpus();
+        info->cpufreq = ipipe_cpu_freq();
+        info->archdep.tmirq = IPIPE_TIMER_IRQ;
+        info->archdep.tmfreq = info->cpufreq;
+
+        return 0;
+}
+
+/*
+ * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
+ * just like if it has been actually received from a hw source. Also
+ * works for virtual interrupts.
+ */
+int ipipe_trigger_irq(unsigned irq)
+{
+        unsigned long flags;
+
+        if (irq >= IPIPE_NR_IRQS ||
+            (ipipe_virtual_irq_p(irq)
+             && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
+                return -EINVAL;
+
+        local_irq_save_hw(flags);
+
+        __ipipe_handle_irq(irq, NULL);
+
+        local_irq_restore_hw(flags);
+
+        return 1;
+}
+
+/* Move Linux IRQ to threads. */
+
+static int do_irqd(void *__desc)
+{
+        struct irq_desc *desc = __desc;
+        unsigned irq = desc - irq_desc;
+        int thrprio = desc->thr_prio;
+        int thrmask = 1 << thrprio;
+        int cpu = smp_processor_id();
+        cpumask_t cpumask;
+
+        sigfillset(&current->blocked);
+        current->flags |= PF_NOFREEZE;
+        cpumask = cpumask_of_cpu(cpu);
+        set_cpus_allowed(current, cpumask);
+        ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
+
+        while (!kthread_should_stop()) {
+                local_irq_disable();
+                if (!(desc->status & IRQ_SCHEDULED)) {
+                        set_current_state(TASK_INTERRUPTIBLE);
+resched:
+                        local_irq_enable();
+                        schedule();
+                        local_irq_disable();
+                }
+                __set_current_state(TASK_RUNNING);
+                /*
+                 * If higher priority interrupt servers are ready to
+                 * run, reschedule immediately. We need this for the
+                 * GPIO demux IRQ handler to unmask the interrupt line
+                 * _last_, after all GPIO IRQs have run.
+                 */
+                if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
+                        goto resched;
+                if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
+                        per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
+                desc->status &= ~IRQ_SCHEDULED;
+                desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
+                local_irq_enable();
+        }
+        __set_current_state(TASK_RUNNING);
+        return 0;
+}
+
+static void kick_irqd(unsigned irq, void *cookie)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        int thrprio = desc->thr_prio;
+        int thrmask = 1 << thrprio;
+        int cpu = smp_processor_id();
+
+        if (!(desc->status & IRQ_SCHEDULED)) {
+                desc->status |= IRQ_SCHEDULED;
+                per_cpu(pending_irqthread_mask, cpu) |= thrmask;
+                ++per_cpu(pending_irq_count[thrprio], cpu);
+                wake_up_process(desc->thread);
+        }
+}
+
+int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc)
+{
+        if (desc->thread || !create_irq_threads)
+                return 0;
+
+        desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
+        if (desc->thread == NULL) {
+                printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
+                return -ENOMEM;
+        }
+
+        wake_up_process(desc->thread);
+
+        desc->thr_handler = ipipe_root_domain->irqs[irq].handler;
+        ipipe_root_domain->irqs[irq].handler = &kick_irqd;
+
+        return 0;
+}
+
+void __init ipipe_init_irq_threads(void)
+{
+        unsigned irq;
+        struct irq_desc *desc;
+
+        create_irq_threads = 1;
+
+        for (irq = 0; irq < NR_IRQS; irq++) {
+                desc = irq_desc + irq;
+                if (desc->action != NULL ||
+                        (desc->status & IRQ_NOREQUEST) != 0)
+                        ipipe_start_irq_thread(irq, desc);
+        }
+}
+
+EXPORT_SYMBOL(show_stack);
+
+#ifdef CONFIG_IPIPE_TRACE_MCOUNT
+void notrace _mcount(void);
+EXPORT_SYMBOL(_mcount);
+#endif /* CONFIG_IPIPE_TRACE_MCOUNT */
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 07402f57c9de..ab8209cbbad0 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -36,7 +36,7 @@
 #include <linux/irq.h>
 #include <asm/trace.h>
 
-static unsigned long irq_err_count;
+static atomic_t irq_err_count;
 static spinlock_t irq_controller_lock;
 
 /*
@@ -48,10 +48,9 @@ void dummy_mask_unmask_irq(unsigned int irq)
 
 void ack_bad_irq(unsigned int irq)
 {
-        irq_err_count += 1;
+        atomic_inc(&irq_err_count);
         printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
 }
-EXPORT_SYMBOL(ack_bad_irq);
 
 static struct irq_chip bad_chip = {
         .ack = dummy_mask_unmask_irq,
@@ -72,7 +71,7 @@ static struct irq_desc bad_irq_desc = {
 
 int show_interrupts(struct seq_file *p, void *v)
 {
-        int i = *(loff_t *) v;
+        int i = *(loff_t *) v, j;
         struct irqaction *action;
         unsigned long flags;
 
@@ -80,19 +79,20 @@ int show_interrupts(struct seq_file *p, void *v)
                 spin_lock_irqsave(&irq_desc[i].lock, flags);
                 action = irq_desc[i].action;
                 if (!action)
-                        goto unlock;
-
-                seq_printf(p, "%3d: %10u ", i, kstat_irqs(i));
+                        goto skip;
+                seq_printf(p, "%3d: ", i);
+                for_each_online_cpu(j)
+                        seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
+                seq_printf(p, " %8s", irq_desc[i].chip->name);
                 seq_printf(p, "  %s", action->name);
                 for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
+                        seq_printf(p, "  %s", action->name);
 
                 seq_putc(p, '\n');
- unlock:
+ skip:
                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
-                seq_printf(p, "Err: %10lu\n", irq_err_count);
-        }
+        } else if (i == NR_IRQS)
+                seq_printf(p, "Err: %10u\n",  atomic_read(&irq_err_count));
         return 0;
 }
 
@@ -101,7 +101,6 @@ int show_interrupts(struct seq_file *p, void *v)
  * come via this function.  Instead, they should provide their
  * own 'handler'
  */
-
 #ifdef CONFIG_DO_IRQ_L1
 __attribute__((l1_text))
 #endif
@@ -109,8 +108,9 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs;
         struct irq_desc *desc = irq_desc + irq;
+#ifndef CONFIG_IPIPE
         unsigned short pending, other_ints;
-
+#endif
         old_regs = set_irq_regs(regs);
 
         /*
@@ -121,9 +121,24 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
                 desc = &bad_irq_desc;
 
         irq_enter();
-
+#ifdef CONFIG_DEBUG_STACKOVERFLOW
+        /* Debugging check for stack overflow: is there less than STACK_WARN free? */
+        {
+                long sp;
+
+                sp = __get_SP() & (THREAD_SIZE-1);
+
+                if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
+                        dump_stack();
+                        printk(KERN_EMERG "%s: possible stack overflow while handling irq %i "
+                                        " only %ld bytes free\n",
+                                __func__, irq, sp - sizeof(struct thread_info));
+                }
+        }
+#endif
         generic_handle_irq(irq);
 
+#ifndef CONFIG_IPIPE    /* Useless and bugous over the I-pipe: IRQs are threaded. */
         /* If we're the only interrupt running (ignoring IRQ15 which is for
            syscalls), lower our priority to IRQ14 so that softirqs run at
            that level.  If there's another, lower-level interrupt, irq_exit
@@ -133,6 +148,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
         other_ints = pending & (pending - 1);
         if (other_ints == 0)
                 lower_to_irq14();
+#endif /* !CONFIG_IPIPE */
         irq_exit();
 
         set_irq_regs(old_regs);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index b795a207742c..b163f6d3330d 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -34,9 +34,14 @@ int gdb_bfin_vector = -1;
 #error change the definition of slavecpulocks
 #endif
 
-#ifdef CONFIG_BFIN_WDT
-# error "Please unselect blackfin watchdog driver before build KGDB."
-#endif
+#define IN_MEM(addr, size, l1_addr, l1_size) \
+({ \
+        unsigned long __addr = (unsigned long)(addr); \
+        (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
+})
+#define ASYNC_BANK_SIZE \
+        (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
+         ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
 
 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 {
@@ -105,7 +110,7 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
  * Extracts ebp, esp and eip values understandable by gdb from the values
  * saved by switch_to.
  * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
- * prior to entering switch_to is 8 greater then the value that is saved.
+ * prior to entering switch_to is 8 greater than the value that is saved.
  * If switch_to changes, change following code appropriately.
  */
 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
@@ -219,6 +224,7 @@ int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
                 if (bfin_type == breakinfo[breakno].type
                         && !breakinfo[breakno].occupied) {
                         breakinfo[breakno].occupied = 1;
+                        breakinfo[breakno].skip = 0;
                         breakinfo[breakno].enabled = 1;
                         breakinfo[breakno].addr = addr;
                         breakinfo[breakno].dataacc = dataacc;
@@ -363,12 +369,12 @@ void kgdb_passive_cpu_callback(void *info)
 
 void kgdb_roundup_cpus(unsigned long flags)
 {
-        smp_call_function(kgdb_passive_cpu_callback, NULL, 0, 0);
+        smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
 }
 
 void kgdb_roundup_cpu(int cpu, unsigned long flags)
 {
-        smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0, 0);
+        smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
 }
 #endif
 
@@ -385,10 +391,8 @@ int kgdb_arch_handle_exception(int vector, int signo,
                                struct pt_regs *regs)
 {
         long addr;
-        long breakno;
         char *ptr;
         int newPC;
-        int wp_status;
         int i;
 
         switch (remcom_in_buffer[0]) {
@@ -426,17 +430,6 @@ int kgdb_arch_handle_exception(int vector, int signo,
                         kgdb_single_step = i + 1;
                 }
 
-                if (vector == VEC_WATCH) {
-                        wp_status = bfin_read_WPSTAT();
-                        for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) {
-                                if (wp_status & (1 << breakno)) {
-                                        breakinfo->skip = 1;
-                                        break;
-                                }
-                        }
-                        bfin_write_WPSTAT(0);
-                }
-
                 bfin_correct_hw_break();
 
                 return 0;
@@ -478,57 +471,32 @@ static int validate_memory_access_address(unsigned long addr, int size)
                 return 0;
         if (addr >= SYSMMR_BASE)
                 return 0;
-        if (addr >= ASYNC_BANK0_BASE
-           && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
+        if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
                 return 0;
         if (cpu == 0) {
-                if (addr >= L1_SCRATCH_START
-                   && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
+                if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
                         return 0;
-#if L1_CODE_LENGTH != 0
-                if (addr >= L1_CODE_START
-                   && (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
+                if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH))
                         return 0;
-#endif
-#if L1_DATA_A_LENGTH != 0
-                if (addr >= L1_DATA_A_START
-                   && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
+                if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
                         return 0;
-#endif
-#if L1_DATA_B_LENGTH != 0
-                if (addr >= L1_DATA_B_START
-                   && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
+                if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
                         return 0;
-#endif
 #ifdef CONFIG_SMP
         } else if (cpu == 1) {
-                if (addr >= COREB_L1_SCRATCH_START
-                   && (addr + size <= COREB_L1_SCRATCH_START
-                   + L1_SCRATCH_LENGTH))
+                if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
                         return 0;
-# if L1_CODE_LENGTH != 0
-                if (addr >= COREB_L1_CODE_START
-                   && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
+                if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
                         return 0;
-# endif
-# if L1_DATA_A_LENGTH != 0
-                if (addr >= COREB_L1_DATA_A_START
-                   && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
+                if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
                         return 0;
-# endif
-# if L1_DATA_B_LENGTH != 0
-                if (addr >= COREB_L1_DATA_B_START
-                   && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
+                if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
                         return 0;
-# endif
 #endif
         }
 
-#if L2_LENGTH != 0
-        if (addr >= L2_START
-           && addr + size <= L2_START + L2_LENGTH)
+        if (IN_MEM(addr, size, L2_START, L2_LENGTH))
                 return 0;
-#endif
 
         return EFAULT;
 }
@@ -582,12 +550,9 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
                 default:
                         err = EFAULT;
                 }
-        } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
-                (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
+        } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 #ifdef CONFIG_SMP
-                || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
-                (unsigned int)(mem + count) <=
-                COREB_L1_CODE_START + L1_CODE_LENGTH
+                || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 #endif
                 ) {
                 /* access L1 instruction SRAM*/
@@ -658,12 +623,9 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
                 default:
                         return EFAULT;
                 }
-        } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
-                (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH
+        } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 #ifdef CONFIG_SMP
-                || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
-                (unsigned int)(mem + count) <=
-                COREB_L1_CODE_START + L1_CODE_LENGTH
+                || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 #endif
                 ) {
                 /* access L1 instruction SRAM */
@@ -723,12 +685,9 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
                 default:
                         return EFAULT;
                 }
-        } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
-                (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
+        } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
 #ifdef CONFIG_SMP
-                || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
-                (unsigned int)(mem + count) <=
-                COREB_L1_CODE_START + L1_CODE_LENGTH
+                || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
 #endif
                 ) {
                 /* access L1 instruction SRAM */
@@ -745,24 +704,16 @@ int kgdb_validate_break_address(unsigned long addr)
 
         if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
                 return 0;
-        if (addr >= ASYNC_BANK0_BASE
-           && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
+        if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
                 return 0;
-#if L1_CODE_LENGTH != 0
-        if (cpu == 0 && addr >= L1_CODE_START
-           && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
+        if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
                 return 0;
-# ifdef CONFIG_SMP
-        else if (cpu == 1 && addr >= COREB_L1_CODE_START
-           && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
+#ifdef CONFIG_SMP
+        else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
                 return 0;
-# endif
 #endif
-#if L2_LENGTH != 0
-        if (addr >= L2_START
-           && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
+        if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
                 return 0;
-#endif
 
         return EFAULT;
 }
@@ -772,13 +723,9 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
         int err;
         int cpu = raw_smp_processor_id();
 
-        if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START
-                && (unsigned int)(addr + BREAK_INSTR_SIZE)
-                < L1_CODE_START + L1_CODE_LENGTH)
+        if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
 #ifdef CONFIG_SMP
-                || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START
-                && (unsigned int)(addr + BREAK_INSTR_SIZE)
-                < COREB_L1_CODE_START + L1_CODE_LENGTH)
+                || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
 #endif
                 ) {
                 /* access L1 instruction SRAM */
@@ -804,9 +751,7 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
 
 int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
 {
-        if ((unsigned int)addr >= L1_CODE_START &&
-                (unsigned int)(addr + BREAK_INSTR_SIZE) <
-                        L1_CODE_START + L1_CODE_LENGTH) {
+        if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) {
                 /* access L1 instruction SRAM */
                 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
                         return -EFAULT;
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
new file mode 100644
index 000000000000..3dba9c17304a
--- /dev/null
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -0,0 +1,123 @@
+/*
+ * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests
+ *
+ * Copyright 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+
+#include <asm/current.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+
+#include <asm/blackfin.h>
+
+static char cmdline[256];
+static unsigned long len;
+
+static int num1 __attribute__((l1_data));
+
+void kgdb_l1_test(void) __attribute__((l1_text));
+
+void kgdb_l1_test(void)
+{
+        printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
+        printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test);
+        num1 = num1 + 10 ;
+        printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
+        return ;
+}
+#if L2_LENGTH
+
+static int num2 __attribute__((l2));
+void kgdb_l2_test(void) __attribute__((l2));
+
+void kgdb_l2_test(void)
+{
+        printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
+        printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test);
+        num2 = num2 + 20 ;
+        printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
+        return ;
+}
+
+#endif
+
+
+int kgdb_test(char *name, int len, int count, int z)
+{
+        printk(KERN_DEBUG "kgdb name(%d): %s, %d, %d\n", len, name, count, z);
+        count = z;
+        return count;
+}
+
+static int test_proc_output(char *buf)
+{
+        kgdb_test("hello world!", 12, 0x55, 0x10);
+        kgdb_l1_test();
+        #if L2_LENGTH
+        kgdb_l2_test();
+        #endif
+
+        return 0;
+}
+
+static int test_read_proc(char *page, char **start, off_t off,
+                                 int count, int *eof, void *data)
+{
+        int len;
+
+        len = test_proc_output(page);
+        if (len <= off+count)
+                *eof = 1;
+        *start = page + off;
+        len -= off;
+        if (len > count)
+                len = count;
+        if (len < 0)
+                len = 0;
+        return len;
+}
+
+static int test_write_proc(struct file *file, const char *buffer,
+                                 unsigned long count, void *data)
+{
+        if (count >= 256)
+                len = 255;
+        else
+                len = count;
+
+        memcpy(cmdline, buffer, count);
+        cmdline[len] = 0;
+
+        return len;
+}
+
+static int __init kgdbtest_init(void)
+{
+        struct proc_dir_entry *entry;
+
+        entry = create_proc_entry("kgdbtest", 0, NULL);
+        if (entry == NULL)
+                return -ENOMEM;
+
+        entry->read_proc = test_read_proc;
+        entry->write_proc = test_write_proc;
+        entry->data = NULL;
+
+        return 0;
+}
+
+static void __exit kgdbtest_exit(void)
+{
+        remove_proc_entry("kgdbtest", NULL);
+}
+
+module_init(kgdbtest_init);
+module_exit(kgdbtest_exit);
+MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S
new file mode 100644
index 000000000000..edcfb3865f46
--- /dev/null
+++ b/arch/blackfin/kernel/mcount.S
@@ -0,0 +1,70 @@
+/*
+ * linux/arch/blackfin/mcount.S
+ *
+ * Copyright (C) 2006 Analog Devices Inc.
+ *
+ * 2007/04/12 Save index, length, modify and base registers. --rpm
+ */
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+
+.text
+
+.align 4        /* just in case */
+
+ENTRY(__mcount)
+        [--sp] = i0;
+        [--sp] = i1;
+        [--sp] = i2;
+        [--sp] = i3;
+        [--sp] = l0;
+        [--sp] = l1;
+        [--sp] = l2;
+        [--sp] = l3;
+        [--sp] = m0;
+        [--sp] = m1;
+        [--sp] = m2;
+        [--sp] = m3;
+        [--sp] = b0;
+        [--sp] = b1;
+        [--sp] = b2;
+        [--sp] = b3;
+        [--sp] = ( r7:0, p5:0 );
+        [--sp] = ASTAT;
+
+        p1.L = _ipipe_trace_enable;
+        p1.H = _ipipe_trace_enable;
+        r7 = [p1];
+        CC = r7 == 0;
+        if CC jump out;
+        link 0x10;
+        r0 = 0x0;
+        [sp + 0xc] = r0; /* v */
+        r0 = 0x0;       /* type: IPIPE_TRACE_FN */
+        r1 = rets;
+        p0 = [fp];      /* p0: Prior FP */
+        r2 = [p0 + 4];  /* r2: Prior RETS */
+        call ___ipipe_trace;
+        unlink;
+out:
+        ASTAT = [sp++];
+        ( r7:0, p5:0 ) = [sp++];
+        b3 = [sp++];
+        b2 = [sp++];
+        b1 = [sp++];
+        b0 = [sp++];
+        m3 = [sp++];
+        m2 = [sp++];
+        m1 = [sp++];
+        m0 = [sp++];
+        l3 = [sp++];
+        l2 = [sp++];
+        l1 = [sp++];
+        l0 = [sp++];
+        i3 = [sp++];
+        i2 = [sp++];
+        i1 = [sp++];
+        i0 = [sp++];
+        rts;
+ENDPROC(__mcount)
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
index e1bebc80a5bf..1bd7f2d018a8 100644
--- a/arch/blackfin/kernel/module.c
+++ b/arch/blackfin/kernel/module.c
@@ -37,111 +37,6 @@
 #include <asm/dma.h>
 #include <asm/cacheflush.h>
 
-/*
- * handle arithmetic relocations.
- * See binutils/bfd/elf32-bfin.c for more details
- */
-#define RELOC_STACK_SIZE 100
-static uint32_t reloc_stack[RELOC_STACK_SIZE];
-static unsigned int reloc_stack_tos;
-
-#define is_reloc_stack_empty() ((reloc_stack_tos > 0)?0:1)
-
-static void reloc_stack_push(uint32_t value)
-{
-        reloc_stack[reloc_stack_tos++] = value;
-}
-
-static uint32_t reloc_stack_pop(void)
-{
-        return reloc_stack[--reloc_stack_tos];
-}
-
-static uint32_t reloc_stack_operate(unsigned int oper, struct module *mod)
-{
-        uint32_t value;
-
-        switch (oper) {
-        case R_add:
-                value = reloc_stack[reloc_stack_tos - 2] +
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_sub:
-                value = reloc_stack[reloc_stack_tos - 2] -
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_mult:
-                value = reloc_stack[reloc_stack_tos - 2] *
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_div:
-                value = reloc_stack[reloc_stack_tos - 2] /
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_mod:
-                value = reloc_stack[reloc_stack_tos - 2] %
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_lshift:
-                value = reloc_stack[reloc_stack_tos - 2] <<
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_rshift:
-                value = reloc_stack[reloc_stack_tos - 2] >>
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_and:
-                value = reloc_stack[reloc_stack_tos - 2] &
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_or:
-                value = reloc_stack[reloc_stack_tos - 2] |
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_xor:
-                value = reloc_stack[reloc_stack_tos - 2] ^
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_land:
-                value = reloc_stack[reloc_stack_tos - 2] &&
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_lor:
-                value = reloc_stack[reloc_stack_tos - 2] ||
-                        reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 2;
-                break;
-        case R_neg:
-                value = -reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos--;
-                break;
-        case R_comp:
-                value = ~reloc_stack[reloc_stack_tos - 1];
-                reloc_stack_tos -= 1;
-                break;
-        default:
-                printk(KERN_WARNING "module %s: unhandled reloction\n",
-                                mod->name);
-                return 0;
-        }
-
-        /* now push the new value back on stack */
-        reloc_stack_push(value);
-
-        return value;
-}
-
 void *module_alloc(unsigned long size)
 {
         if (size == 0)
@@ -334,16 +229,18 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
                    undefined symbols have been resolved. */
                 sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
                     + ELF32_R_SYM(rel[i].r_info);
-                if (is_reloc_stack_empty()) {
-                        value = sym->st_value;
-                } else {
-                        value = reloc_stack_pop();
-                }
+                value = sym->st_value;
                 value += rel[i].r_addend;
                 pr_debug("location is %x, value is %x type is %d \n",
                          (unsigned int) location32, value,
                          ELF32_R_TYPE(rel[i].r_info));
-
+#ifdef CONFIG_SMP
+                if ((unsigned long)location16 >= COREB_L1_DATA_A_START) {
+                        printk(KERN_ERR "module %s: cannot relocate in L1: %u (SMP kernel)",
+                                       mod->name, ELF32_R_TYPE(rel[i].r_info));
+                        return -ENOEXEC;
+                }
+#endif
                 switch (ELF32_R_TYPE(rel[i].r_info)) {
 
                 case R_pcrel24:
@@ -355,6 +252,12 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
                         location32 = (uint32_t *) location16;
                         value -= (uint32_t) location32;
                         value >>= 1;
+                        if ((value & 0xFF000000) != 0 &&
+                            (value & 0xFF000000) != 0xFF000000) {
+                                printk(KERN_ERR "module %s: relocation overflow\n",
+                                       mod->name);
+                                return -ENOEXEC;
+                        }
                         pr_debug("value is %x, before %x-%x after %x-%x\n", value,
                                *location16, *(location16 + 1),
                                (*location16 & 0xff00) | (value >> 16 & 0x00ff),
@@ -399,28 +302,6 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
                         pr_debug("before %x after %x\n", *location32, value);
                         *location32 = value;
                         break;
-                case R_push:
-                        reloc_stack_push(value);
-                        break;
-                case R_const:
-                        reloc_stack_push(rel[i].r_addend);
-                        break;
-                case R_add:
-                case R_sub:
-                case R_mult:
-                case R_div:
-                case R_mod:
-                case R_lshift:
-                case R_rshift:
-                case R_and:
-                case R_or:
-                case R_xor:
-                case R_land:
-                case R_lor:
-                case R_neg:
-                case R_comp:
-                        reloc_stack_operate(ELF32_R_TYPE(rel[i].r_info), mod);
-                        break;
                 default:
                         printk(KERN_ERR "module %s: Unknown relocation: %u\n",
                                mod->name, ELF32_R_TYPE(rel[i].r_info));
@@ -436,6 +317,7 @@ module_finalize(const Elf_Ehdr * hdr,
 {
         unsigned int i, strindex = 0, symindex = 0;
         char *secstrings;
+        long err = 0;
 
         secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
 
@@ -460,8 +342,10 @@ module_finalize(const Elf_Ehdr * hdr,
                     (strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) ||
                     ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
                         (hdr->e_flags & (EF_BFIN_CODE_IN_L1|EF_BFIN_CODE_IN_L2))))) {
-                        apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
+                        err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
                                            symindex, i, mod);
+                        if (err < 0)
+                                return -ENOEXEC;
                 }
         }
         return 0;
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 0c3ea118b657..33e2e8993f7f 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -39,6 +39,7 @@
 
 #include <asm/blackfin.h>
 #include <asm/fixed_code.h>
+#include <asm/mem_map.h>
 
 asmlinkage void ret_from_fork(void);
 
@@ -81,11 +82,14 @@ void cpu_idle(void)__attribute__((l1_text));
  */
 static void default_idle(void)
 {
-        local_irq_disable();
+#ifdef CONFIG_IPIPE
+        ipipe_suspend_domain();
+#endif
+        local_irq_disable_hw();
         if (!need_resched())
                 idle_with_irq_disabled();
 
-        local_irq_enable();
+        local_irq_enable_hw();
 }
 
 /*
@@ -154,6 +158,7 @@ pid_t kernel_thread(int (*fn) (void *), void *arg, unsigned long flags)
         return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL,
                        NULL);
 }
+EXPORT_SYMBOL(kernel_thread);
 
 void flush_thread(void)
 {
@@ -170,6 +175,13 @@ asmlinkage int bfin_clone(struct pt_regs *regs)
         unsigned long clone_flags;
         unsigned long newsp;
 
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        if (current->rt.nr_cpus_allowed == num_possible_cpus()) {
+                current->cpus_allowed = cpumask_of_cpu(smp_processor_id());
+                current->rt.nr_cpus_allowed = 1;
+        }
+#endif
+
         /* syscall2 puts clone_flags in r0 and usp in r1 */
         clone_flags = regs->r0;
         newsp = regs->r1;
@@ -337,22 +349,22 @@ int _access_ok(unsigned long addr, unsigned long size)
         if (addr >= (unsigned long)__init_begin &&
             addr + size <= (unsigned long)__init_end)
                 return 1;
-        if (addr >= L1_SCRATCH_START
-            && addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH)
+        if (addr >= get_l1_scratch_start()
+            && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH)
                 return 1;
 #if L1_CODE_LENGTH != 0
-        if (addr >= L1_CODE_START + (_etext_l1 - _stext_l1)
-            && addr + size <= L1_CODE_START + L1_CODE_LENGTH)
+        if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1)
+            && addr + size <= get_l1_code_start() + L1_CODE_LENGTH)
                 return 1;
 #endif
 #if L1_DATA_A_LENGTH != 0
-        if (addr >= L1_DATA_A_START + (_ebss_l1 - _sdata_l1)
-            && addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH)
+        if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1)
+            && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH)
                 return 1;
 #endif
 #if L1_DATA_B_LENGTH != 0
-        if (addr >= L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1)
-            && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH)
+        if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1)
+            && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH)
                 return 1;
 #endif
 #if L2_LENGTH != 0
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 140bf00e9974..d2d388536630 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -45,6 +45,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/dma.h>
 #include <asm/fixed_code.h>
+#include <asm/mem_map.h>
 
 #define TEXT_OFFSET 0
 /*
@@ -80,10 +81,12 @@ static inline struct pt_regs *get_user_regs(struct task_struct *task)
 /*
  * Get all user integer registers.
  */
-static inline int ptrace_getregs(struct task_struct *tsk, void __user * uregs)
+static inline int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
 {
-        struct pt_regs *regs = get_user_regs(tsk);
-        return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
+        struct pt_regs regs;
+        memcpy(&regs, get_user_regs(tsk), sizeof(regs));
+        regs.usp = tsk->thread.usp;
+        return copy_to_user(uregs, &regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
 }
 
 /* Mapping from PT_xxx to the stack offset at which the register is
@@ -220,8 +223,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                 break;
                         pr_debug("ptrace: user address is valid\n");
 
-                        if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
-                            && addr + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) {
+                        if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start()
+                            && addr + sizeof(tmp) <= get_l1_code_start() + L1_CODE_LENGTH) {
                                 safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp));
                                 copied = sizeof(tmp);
 
@@ -300,8 +303,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                 break;
                         pr_debug("ptrace: user address is valid\n");
 
-                        if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
-                            && addr + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) {
+                        if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start()
+                            && addr + sizeof(data) <= get_l1_code_start() + L1_CODE_LENGTH) {
                                 safe_dma_memcpy ((void *)(addr), &data, sizeof(data));
                                 copied = sizeof(data);
 
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index ae97ca407b0d..eeee8cb43360 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -21,7 +21,7 @@
  * the core reset.
  */
 __attribute__((l1_text))
-static void bfin_reset(void)
+static void _bfin_reset(void)
 {
         /* Wait for completion of "system" events such as cache line
          * line fills so that we avoid infinite stalls later on as
@@ -66,6 +66,18 @@ static void bfin_reset(void)
         }
 }
 
+static void bfin_reset(void)
+{
+        if (ANOMALY_05000353 || ANOMALY_05000386)
+                _bfin_reset();
+        else
+                /* the bootrom checks to see how it was reset and will
+                 * automatically perform a software reset for us when
+                 * it starts executing boot
+                 */
+                asm("raise 1;");
+}
+
 __attribute__((weak))
 void native_machine_restart(char *cmd)
 {
@@ -75,14 +87,10 @@ void machine_restart(char *cmd)
 {
         native_machine_restart(cmd);
         local_irq_disable();
-        if (ANOMALY_05000353 || ANOMALY_05000386)
-                bfin_reset();
+        if (smp_processor_id())
+                smp_call_function((void *)bfin_reset, 0, 1);
         else
-                /* the bootrom checks to see how it was reset and will
-                 * automatically perform a software reset for us when
-                 * it starts executing boot
-                 */
-                asm("raise 1;");
+                bfin_reset();
 }
 
 __attribute__((weak))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 71a9a8c53cea..b2a811347b65 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -13,6 +13,7 @@
 #include <linux/bootmem.h>
 #include <linux/seq_file.h>
 #include <linux/cpu.h>
+#include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/tty.h>
 #include <linux/pfn.h>
@@ -26,11 +27,10 @@
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
 #include <asm/div64.h>
+#include <asm/cpu.h>
 #include <asm/fixed_code.h>
 #include <asm/early_printk.h>
 
-static DEFINE_PER_CPU(struct cpu, cpu_devices);
-
 u16 _bfin_swrst;
 EXPORT_SYMBOL(_bfin_swrst);
 
@@ -79,27 +79,68 @@ static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
 
-void __init bfin_cache_init(void)
-{
+DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
+
+static int early_init_clkin_hz(char *buf);
+
 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-        generate_cplb_tables();
+void __init generate_cplb_tables(void)
+{
+        unsigned int cpu;
+
+        generate_cplb_tables_all();
+        /* Generate per-CPU I&D CPLB tables */
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
+                generate_cplb_tables_cpu(cpu);
+}
 #endif
 
+void __cpuinit bfin_setup_caches(unsigned int cpu)
+{
 #ifdef CONFIG_BFIN_ICACHE
-        bfin_icache_init();
-        printk(KERN_INFO "Instruction Cache Enabled\n");
+        bfin_icache_init(icplb_tbl[cpu]);
 #endif
 
 #ifdef CONFIG_BFIN_DCACHE
-        bfin_dcache_init();
-        printk(KERN_INFO "Data Cache Enabled"
+        bfin_dcache_init(dcplb_tbl[cpu]);
+#endif
+
+        /*
+         * In cache coherence emulation mode, we need to have the
+         * D-cache enabled before running any atomic operation which
+         * might invove cache invalidation (i.e. spinlock, rwlock).
+         * So printk's are deferred until then.
+         */
+#ifdef CONFIG_BFIN_ICACHE
+        printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
+#endif
+#ifdef CONFIG_BFIN_DCACHE
+        printk(KERN_INFO "Data Cache Enabled for CPU%u"
 # if defined CONFIG_BFIN_WB
                 " (write-back)"
 # elif defined CONFIG_BFIN_WT
                 " (write-through)"
 # endif
-                "\n");
+                "\n", cpu);
+#endif
+}
+
+void __cpuinit bfin_setup_cpudata(unsigned int cpu)
+{
+        struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
+
+        cpudata->idle = current;
+        cpudata->loops_per_jiffy = loops_per_jiffy;
+        cpudata->imemctl = bfin_read_IMEM_CONTROL();
+        cpudata->dmemctl = bfin_read_DMEM_CONTROL();
+}
+
+void __init bfin_cache_init(void)
+{
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
+        generate_cplb_tables();
 #endif
+        bfin_setup_caches(0);
 }
 
 void __init bfin_relocate_l1_mem(void)
@@ -109,6 +150,8 @@ void __init bfin_relocate_l1_mem(void)
         unsigned long l1_data_b_length;
         unsigned long l2_length;
 
+        blackfin_dma_early_init();
+
         l1_code_length = _etext_l1 - _stext_l1;
         if (l1_code_length > L1_CODE_LENGTH)
                 panic("L1 Instruction SRAM Overflow\n");
@@ -230,7 +273,7 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
         /* record all known change-points (starting and ending addresses),
            omitting those that are for empty memory regions */
         chgidx = 0;
-        for (i = 0; i < old_nr; i++)    {
+        for (i = 0; i < old_nr; i++) {
                 if (map[i].size != 0) {
                         change_point[chgidx]->addr = map[i].addr;
                         change_point[chgidx++]->pentry = &map[i];
@@ -238,13 +281,13 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
                         change_point[chgidx++]->pentry = &map[i];
                 }
         }
-        chg_nr = chgidx;        /* true number of change-points */
+        chg_nr = chgidx;        /* true number of change-points */
 
         /* sort change-point list by memory addresses (low -> high) */
         still_changing = 1;
-        while (still_changing)  {
+        while (still_changing) {
                 still_changing = 0;
-                for (i = 1; i < chg_nr; i++)  {
+                for (i = 1; i < chg_nr; i++) {
                         /* if <current_addr> > <last_addr>, swap */
                         /* or, if current=<start_addr> & last=<end_addr>, swap */
                         if ((change_point[i]->addr < change_point[i-1]->addr) ||
@@ -261,10 +304,10 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
         }
 
         /* create a new memmap, removing overlaps */
-        overlap_entries = 0;     /* number of entries in the overlap table */
-        new_entry = 0;   /* index for creating new memmap entries */
-        last_type = 0;           /* start with undefined memory type */
-        last_addr = 0;           /* start with 0 as last starting address */
+        overlap_entries = 0;    /* number of entries in the overlap table */
+        new_entry = 0;          /* index for creating new memmap entries */
+        last_type = 0;          /* start with undefined memory type */
+        last_addr = 0;          /* start with 0 as last starting address */
         /* loop through change-points, determining affect on the new memmap */
         for (chgidx = 0; chgidx < chg_nr; chgidx++) {
                 /* keep track of all overlapping memmap entries */
@@ -286,14 +329,14 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
                         if (overlap_list[i]->type > current_type)
                                 current_type = overlap_list[i]->type;
                 /* continue building up new memmap based on this information */
-                if (current_type != last_type)  {
+                if (current_type != last_type) {
                         if (last_type != 0) {
                                 new_map[new_entry].size =
                                         change_point[chgidx]->addr - last_addr;
                                 /* move forward only if the new size was non-zero */
                                 if (new_map[new_entry].size != 0)
                                         if (++new_entry >= BFIN_MEMMAP_MAX)
-                                                break;  /* no more space left for new entries */
+                                                break;  /* no more space left for new entries */
                         }
                         if (current_type != 0) {
                                 new_map[new_entry].addr = change_point[chgidx]->addr;
@@ -303,9 +346,9 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
                         last_type = current_type;
                 }
         }
-        new_nr = new_entry;   /* retain count for new entries */
+        new_nr = new_entry;     /* retain count for new entries */
 
-        /* copy new  mapping into original location */
+        /* copy new mapping into original location */
         memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
         *pnr_map = new_nr;
 
@@ -361,7 +404,6 @@ static __init int parse_memmap(char *arg)
  *  - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
  *       @ from <start> to <start>+<mem>, type RAM
  *       $ from <start> to <start>+<mem>, type RESERVED
- *
  */
 static __init void parse_cmdline_early(char *cmdline_p)
 {
@@ -383,14 +425,15 @@ static __init void parse_cmdline_early(char *cmdline_p)
                                         if (*to != ' ') {
                                                 if (*to == '$'
                                                     || *(to + 1) == '$')
-                                                        reserved_mem_dcache_on =
-                                                            1;
+                                                        reserved_mem_dcache_on = 1;
                                                 if (*to == '#'
                                                     || *(to + 1) == '#')
-                                                        reserved_mem_icache_on =
-                                                            1;
+                                                        reserved_mem_icache_on = 1;
                                         }
                                 }
+                        } else if (!memcmp(to, "clkin_hz=", 9)) {
+                                to += 9;
+                                early_init_clkin_hz(to);
                         } else if (!memcmp(to, "earlyprintk=", 12)) {
                                 to += 12;
                                 setup_early_printk(to);
@@ -417,9 +460,8 @@ static __init void parse_cmdline_early(char *cmdline_p)
  *      [_ramend - DMA_UNCACHED_REGION,
  *              _ramend]:                       uncached DMA region
  *  [_ramend, physical_mem_end]:        memory not managed by kernel
- *
  */
-static __init void  memory_setup(void)
+static __init void memory_setup(void)
 {
 #ifdef CONFIG_MTD_UCLINUX
         unsigned long mtd_phys = 0;
@@ -436,7 +478,7 @@ static __init void  memory_setup(void)
         memory_end = _ramend - DMA_UNCACHED_REGION;
 
 #ifdef CONFIG_MPU
-        /* Round up to multiple of 4MB.  */
+        /* Round up to multiple of 4MB */
         memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
 #else
         memory_start = PAGE_ALIGN(_ramstart);
@@ -616,7 +658,7 @@ static __init void setup_bootmem_allocator(void)
         end_pfn = memory_end >> PAGE_SHIFT;
 
         /*
-         * give all the memory to the bootmap allocator,  tell it to put the
+         * give all the memory to the bootmap allocator, tell it to put the
          * boot mem_map at the start of memory.
          */
         bootmap_size = init_bootmem_node(NODE_DATA(0),
@@ -791,7 +833,11 @@ void __init setup_arch(char **cmdline_p)
         bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
 #endif
 
+#ifdef CONFIG_SMP
+        if (_bfin_swrst & SWRST_DBL_FAULT_A) {
+#else
         if (_bfin_swrst & RESET_DOUBLE) {
+#endif
                 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
                 /* We assume the crashing kernel, and the current symbol table match */
@@ -823,9 +869,12 @@ void __init setup_arch(char **cmdline_p)
                         if (bfin_compiled_revid() == -1)
                                 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
                                        bfin_revid());
-                        else if (bfin_compiled_revid() != 0xffff)
+                        else if (bfin_compiled_revid() != 0xffff) {
                                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
                                        bfin_compiled_revid(), bfin_revid());
+                                if (bfin_compiled_revid() > bfin_revid())
+                                        panic("Error: you are missing anomaly workarounds for this rev\n");
+                        }
                 }
                 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
                         printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
@@ -835,7 +884,7 @@ void __init setup_arch(char **cmdline_p)
         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
 
         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
-               cclk / 1000000,  sclk / 1000000);
+               cclk / 1000000, sclk / 1000000);
 
         if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
                 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
@@ -867,18 +916,21 @@ void __init setup_arch(char **cmdline_p)
         BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
                 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
 
+#ifdef CONFIG_SMP
+        platform_init_cpus();
+#endif
         init_exception_vectors();
-        bfin_cache_init();
+        bfin_cache_init();      /* Initialize caches for the boot CPU */
 }
 
 static int __init topology_init(void)
 {
-        int cpu;
+        unsigned int cpu;
+        /* Record CPU-private information for the boot processor. */
+        bfin_setup_cpudata(0);
 
         for_each_possible_cpu(cpu) {
-                struct cpu *c = &per_cpu(cpu_devices, cpu);
-
-                register_cpu(c, cpu);
+                register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
         }
 
         return 0;
@@ -886,36 +938,54 @@ static int __init topology_init(void)
 
 subsys_initcall(topology_init);
 
+/* Get the input clock frequency */
+static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
+static u_long get_clkin_hz(void)
+{
+        return cached_clkin_hz;
+}
+static int __init early_init_clkin_hz(char *buf)
+{
+        cached_clkin_hz = simple_strtoul(buf, NULL, 0);
+#ifdef BFIN_KERNEL_CLOCK
+        if (cached_clkin_hz != CONFIG_CLKIN_HZ)
+                panic("cannot change clkin_hz when reprogramming clocks");
+#endif
+        return 1;
+}
+early_param("clkin_hz=", early_init_clkin_hz);
+
 /* Get the voltage input multiplier */
-static u_long cached_vco_pll_ctl, cached_vco;
 static u_long get_vco(void)
 {
-        u_long msel;
+        static u_long cached_vco;
+        u_long msel, pll_ctl;
 
-        u_long pll_ctl = bfin_read_PLL_CTL();
-        if (pll_ctl == cached_vco_pll_ctl)
+        /* The assumption here is that VCO never changes at runtime.
+         * If, someday, we support that, then we'll have to change this.
+         */
+        if (cached_vco)
                 return cached_vco;
-        else
-                cached_vco_pll_ctl = pll_ctl;
 
+        pll_ctl = bfin_read_PLL_CTL();
         msel = (pll_ctl >> 9) & 0x3F;
         if (0 == msel)
                 msel = 64;
 
-        cached_vco = CONFIG_CLKIN_HZ;
+        cached_vco = get_clkin_hz();
         cached_vco >>= (1 & pll_ctl);   /* DF bit */
         cached_vco *= msel;
         return cached_vco;
 }
 
 /* Get the Core clock */
-static u_long cached_cclk_pll_div, cached_cclk;
 u_long get_cclk(void)
 {
+        static u_long cached_cclk_pll_div, cached_cclk;
         u_long csel, ssel;
 
         if (bfin_read_PLL_STAT() & 0x1)
-                return CONFIG_CLKIN_HZ;
+                return get_clkin_hz();
 
         ssel = bfin_read_PLL_DIV();
         if (ssel == cached_cclk_pll_div)
@@ -934,21 +1004,21 @@ u_long get_cclk(void)
 EXPORT_SYMBOL(get_cclk);
 
 /* Get the System clock */
-static u_long cached_sclk_pll_div, cached_sclk;
 u_long get_sclk(void)
 {
+        static u_long cached_sclk;
         u_long ssel;
 
-        if (bfin_read_PLL_STAT() & 0x1)
-                return CONFIG_CLKIN_HZ;
-
-        ssel = bfin_read_PLL_DIV();
-        if (ssel == cached_sclk_pll_div)
+        /* The assumption here is that SCLK never changes at runtime.
+         * If, someday, we support that, then we'll have to change this.
+         */
+        if (cached_sclk)
                 return cached_sclk;
-        else
-                cached_sclk_pll_div = ssel;
 
-        ssel &= 0xf;
+        if (bfin_read_PLL_STAT() & 0x1)
+                return get_clkin_hz();
+
+        ssel = bfin_read_PLL_DIV() & 0xf;
         if (0 == ssel) {
                 printk(KERN_WARNING "Invalid System Clock\n");
                 ssel = 1;
@@ -982,17 +1052,18 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 {
         char *cpu, *mmu, *fpu, *vendor, *cache;
         uint32_t revid;
-
-        u_long cclk = 0, sclk = 0;
+        int cpu_num = *(unsigned int *)v;
+        u_long sclk, cclk;
         u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
+        struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
 
         cpu = CPU;
         mmu = "none";
         fpu = "none";
         revid = bfin_revid();
 
-        cclk = get_cclk();
         sclk = get_sclk();
+        cclk = get_cclk();
 
         switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
         case 0xca:
@@ -1003,10 +1074,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 break;
         }
 
-        seq_printf(m, "processor\t: %d\n"
-                "vendor_id\t: %s\n",
-                *(unsigned int *)v,
-                vendor);
+        seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
 
         if (CPUID == bfin_cpuid())
                 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
@@ -1029,12 +1097,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 sclk/1000000, sclk%1000000);
         seq_printf(m, "bogomips\t: %lu.%02lu\n"
                 "Calibration\t: %lu loops\n",
-                (loops_per_jiffy * HZ) / 500000,
-                ((loops_per_jiffy * HZ) / 5000) % 100,
-                (loops_per_jiffy * HZ));
+                (cpudata->loops_per_jiffy * HZ) / 500000,
+                ((cpudata->loops_per_jiffy * HZ) / 5000) % 100,
+                (cpudata->loops_per_jiffy * HZ));
 
         /* Check Cache configutation */
-        switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
+        switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
         case ACACHE_BSRAM:
                 cache = "dbank-A/B\t: cache/sram";
                 dcache_size = 16;
@@ -1058,10 +1126,10 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         }
 
         /* Is it turned on? */
-        if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
+        if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
                 dcache_size = 0;
 
-        if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) != (IMC | ENICPLB))
+        if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
                 icache_size = 0;
 
         seq_printf(m, "cache size\t: %d KB(L1 icache) "
@@ -1086,8 +1154,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                    "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
                    dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
                    BFIN_DLINES);
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
+#endif
 #ifdef CONFIG_BFIN_ICACHE_LOCK
-        switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) {
+        switch ((cpudata->imemctl >> 3) & WAYALL_L) {
         case WAY0_L:
                 seq_printf(m, "Way0 Locked-Down\n");
                 break;
@@ -1137,6 +1208,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 seq_printf(m, "No Ways are locked\n");
         }
 #endif
+
+        if (cpu_num != num_possible_cpus() - 1)
+                return 0;
+
+        if (L2_LENGTH)
+                seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
         seq_printf(m, "board name\t: %s\n", bfin_board_name);
         seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
                  physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
@@ -1144,6 +1221,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 ((int)memory_end - (int)_stext) >> 10,
                 _stext,
                 (void *)memory_end);
+        seq_printf(m, "\n");
 
         return 0;
 }
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index eb2352320454..172b4c588467 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -1,32 +1,11 @@
 /*
- * File:         arch/blackfin/kernel/time.c
- * Based on:     none - original work
- * Author:
+ * arch/blackfin/kernel/time.c
  *
- * Created:
- * Description:  This file contains the bfin-specific time handling details.
- *               Most of the stuff is located in the machine specific files.
- *               FIXME: (This file is subject for removal)
+ * This file contains the Blackfin-specific time handling details.
+ * Most of the stuff is located in the machine specific files.
  *
- * Modified:
- *               Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/module.h>
@@ -34,23 +13,43 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
 
 #include <asm/blackfin.h>
 #include <asm/time.h>
+#include <asm/gptimers.h>
 
 /* This is an NTP setting */
 #define TICK_SIZE (tick_nsec / 1000)
 
-static void time_sched_init(irq_handler_t timer_routine);
-static unsigned long gettimeoffset(void);
-
 static struct irqaction bfin_timer_irq = {
-        .name = "BFIN Timer Tick",
+        .name = "Blackfin Timer Tick",
+#ifdef CONFIG_IRQ_PER_CPU
+        .flags = IRQF_DISABLED | IRQF_PERCPU,
+#else
         .flags = IRQF_DISABLED
+#endif
 };
 
-static void
-time_sched_init(irq_handler_t timer_routine)
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
+void __init setup_system_timer0(void)
+{
+        /* Power down the core timer, just to play safe. */
+        bfin_write_TCNTL(0);
+
+        disable_gptimers(TIMER0bit);
+        set_gptimer_status(0, TIMER_STATUS_TRUN0);
+        while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
+                udelay(10);
+
+        set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
+        set_gptimer_period(TIMER0_id, get_sclk() / HZ);
+        set_gptimer_pwidth(TIMER0_id, 1);
+        SSYNC();
+        enable_gptimers(TIMER0bit);
+}
+#else
+void __init setup_core_timer(void)
 {
         u32 tcount;
 
@@ -58,10 +57,8 @@ time_sched_init(irq_handler_t timer_routine)
         bfin_write_TCNTL(1);
         CSYNC();
 
-        /*
-         * the TSCALE prescaler counter.
-         */
-        bfin_write_TSCALE((TIME_SCALE - 1));
+        /* the TSCALE prescaler counter */
+        bfin_write_TSCALE(TIME_SCALE - 1);
 
         tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
         bfin_write_TPERIOD(tcount);
@@ -71,35 +68,52 @@ time_sched_init(irq_handler_t timer_routine)
         CSYNC();
 
         bfin_write_TCNTL(7);
+}
+#endif
 
-        bfin_timer_irq.handler = (irq_handler_t)timer_routine;
-        /* call setup_irq instead of request_irq because request_irq calls
-         * kmalloc which has not been initialized yet
-         */
+static void __init
+time_sched_init(irqreturn_t(*timer_routine) (int, void *))
+{
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
+        setup_system_timer0();
+        bfin_timer_irq.handler = timer_routine;
+        setup_irq(IRQ_TIMER0, &bfin_timer_irq);
+#else
+        setup_core_timer();
+        bfin_timer_irq.handler = timer_routine;
         setup_irq(IRQ_CORETMR, &bfin_timer_irq);
+#endif
 }
 
 /*
  * Should return useconds since last timer tick
  */
+#ifndef CONFIG_GENERIC_TIME
 static unsigned long gettimeoffset(void)
 {
         unsigned long offset;
         unsigned long clocks_per_jiffy;
 
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
+        clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
+        offset = bfin_read_TIMER0_COUNTER() / \
+                (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
+
+        if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2))
+                offset += (USEC_PER_SEC / HZ);
+#else
         clocks_per_jiffy = bfin_read_TPERIOD();
-        offset =
-            (clocks_per_jiffy -
-             bfin_read_TCOUNT()) / (((clocks_per_jiffy + 1) * HZ) /
-                                    USEC_PER_SEC);
+        offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \
+                (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
 
         /* Check if we just wrapped the counters and maybe missed a tick */
         if ((bfin_read_ILAT() & (1 << IRQ_CORETMR))
-            && (offset < (100000 / HZ / 2)))
+                && (offset < (100000 / HZ / 2)))
                 offset += (USEC_PER_SEC / HZ);
-
+#endif
         return offset;
 }
+#endif
 
 static inline int set_rtc_mmss(unsigned long nowtime)
 {
@@ -111,43 +125,49 @@ static inline int set_rtc_mmss(unsigned long nowtime)
  * as well as call the "do_timer()" routine every clocktick
  */
 #ifdef CONFIG_CORE_TIMER_IRQ_L1
-irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text));
+__attribute__((l1_text))
 #endif
-
 irqreturn_t timer_interrupt(int irq, void *dummy)
 {
         /* last time the cmos clock got updated */
         static long last_rtc_update;
 
         write_seqlock(&xtime_lock);
-
-        do_timer(1);
-
-        profile_tick(CPU_PROFILING);
-
-        /*
-         * If we have an externally synchronized Linux clock, then update
-         * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
-         * called as close as possible to 500 ms before the new second starts.
-         */
-
-        if (ntp_synced() &&
-            xtime.tv_sec > last_rtc_update + 660 &&
-            (xtime.tv_nsec / NSEC_PER_USEC) >=
-            500000 - ((unsigned)TICK_SIZE) / 2
-            && (xtime.tv_nsec / NSEC_PER_USEC) <=
-            500000 + ((unsigned)TICK_SIZE) / 2) {
-                if (set_rtc_mmss(xtime.tv_sec) == 0)
-                        last_rtc_update = xtime.tv_sec;
-                else
-                        /* Do it again in 60s. */
-                        last_rtc_update = xtime.tv_sec - 600;
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
+/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */
+        if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
+#endif
+                do_timer(1);
+
+                /*
+                 * If we have an externally synchronized Linux clock, then update
+                 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
+                 * called as close as possible to 500 ms before the new second starts.
+                 */
+                if (ntp_synced() &&
+                    xtime.tv_sec > last_rtc_update + 660 &&
+                    (xtime.tv_nsec / NSEC_PER_USEC) >=
+                    500000 - ((unsigned)TICK_SIZE) / 2
+                    && (xtime.tv_nsec / NSEC_PER_USEC) <=
+                    500000 + ((unsigned)TICK_SIZE) / 2) {
+                        if (set_rtc_mmss(xtime.tv_sec) == 0)
+                                last_rtc_update = xtime.tv_sec;
+                        else
+                                /* Do it again in 60s. */
+                                last_rtc_update = xtime.tv_sec - 600;
+                }
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
+                set_gptimer_status(0, TIMER_STATUS_TIMIL0);
         }
+#endif
         write_sequnlock(&xtime_lock);
 
-#ifndef CONFIG_SMP
+#ifdef CONFIG_IPIPE
+        update_root_process_times(get_irq_regs());
+#else
         update_process_times(user_mode(get_irq_regs()));
 #endif
+        profile_tick(CPU_PROFILING);
 
         return IRQ_HANDLED;
 }
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index bef025b07443..17d8e4172896 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -75,16 +75,6 @@ void __init trap_init(void)
         CSYNC();
 }
 
-/*
- * Used to save the RETX, SEQSTAT, I/D CPLB FAULT ADDR
- * values across the transition from exception to IRQ5.
- * We put these in L1, so they are going to be in a valid
- * location during exception context
- */
-__attribute__((l1_data))
-unsigned long saved_retx, saved_seqstat,
-        saved_icplb_fault_addr, saved_dcplb_fault_addr;
-
 static void decode_address(char *buf, unsigned long address)
 {
 #ifdef CONFIG_DEBUG_VERBOSE
@@ -211,18 +201,18 @@ asmlinkage void double_fault_c(struct pt_regs *fp)
         printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
         if (((long)fp->seqstat &  SEQSTAT_EXCAUSE) == VEC_UNCOV) {
+                unsigned int cpu = smp_processor_id();
                 char buf[150];
-                decode_address(buf, saved_retx);
+                decode_address(buf, cpu_pda[cpu].retx);
                 printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
-                        (int)saved_seqstat & SEQSTAT_EXCAUSE, buf);
-                decode_address(buf, saved_dcplb_fault_addr);
+                        (unsigned int)cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE, buf);
+                decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %s\n", buf);
-                decode_address(buf, saved_icplb_fault_addr);
+                decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %s\n", buf);
 
                 decode_address(buf, fp->retx);
-                printk(KERN_NOTICE "The instruction at %s caused a double exception\n",
-                        buf);
+                printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
         } else
 #endif
         {
@@ -240,6 +230,9 @@ asmlinkage void trap_c(struct pt_regs *fp)
 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
         int j;
 #endif
+#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
+        unsigned int cpu = smp_processor_id();
+#endif
         int sig = 0;
         siginfo_t info;
         unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
@@ -417,7 +410,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
                 info.si_code = ILL_CPLB_MULHIT;
                 sig = SIGSEGV;
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
-                if (saved_dcplb_fault_addr < FIXED_CODE_START)
+                if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
                         verbose_printk(KERN_NOTICE "NULL pointer access\n");
                 else
 #endif
@@ -471,7 +464,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
                 info.si_code = ILL_CPLB_MULHIT;
                 sig = SIGSEGV;
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
-                if (saved_icplb_fault_addr < FIXED_CODE_START)
+                if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
                         verbose_printk(KERN_NOTICE "Jump to NULL address\n");
                 else
 #endif
@@ -584,10 +577,15 @@ asmlinkage void trap_c(struct pt_regs *fp)
                 }
         }
 
-        info.si_signo = sig;
-        info.si_errno = 0;
-        info.si_addr = (void __user *)fp->pc;
-        force_sig_info(sig, &info, current);
+#ifdef CONFIG_IPIPE
+        if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
+#endif
+        {
+                info.si_signo = sig;
+                info.si_errno = 0;
+                info.si_addr = (void __user *)fp->pc;
+                force_sig_info(sig, &info, current);
+        }
 
         trace_buffer_restore(j);
         return;
@@ -656,13 +654,13 @@ static bool get_instruction(unsigned short *val, unsigned short *address)
         return false;
 }
 
-/* 
+/*
  * decode the instruction if we are printing out the trace, as it
  * makes things easier to follow, without running it through objdump
  * These are the normal instructions which cause change of flow, which
  * would be at the source of the trace buffer
  */
-#ifdef CONFIG_DEBUG_VERBOSE
+#if defined(CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
 static void decode_instruction(unsigned short *address)
 {
         unsigned short opcode;
@@ -846,7 +844,7 @@ void show_stack(struct task_struct *task, unsigned long *stack)
         }
         if (fp) {
                 frame = fp;
-                printk(" FP: (0x%p)\n", fp);
+                printk(KERN_NOTICE " FP: (0x%p)\n", fp);
         } else
                 frame = 0;
 
@@ -960,6 +958,7 @@ void dump_bfin_process(struct pt_regs *fp)
                 else
                         verbose_printk(KERN_NOTICE "COMM= invalid\n");
 
+                printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu);
                 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
                         verbose_printk(KERN_NOTICE  "TEXT = 0x%p-0x%p        DATA = 0x%p-0x%p\n"
                                 KERN_NOTICE " BSS = 0x%p-0x%p  USER-STACK = 0x%p\n"
@@ -1053,6 +1052,7 @@ void show_regs(struct pt_regs *fp)
         struct irqaction *action;
         unsigned int i;
         unsigned long flags;
+        unsigned int cpu = smp_processor_id();
 
         verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
         verbose_printk(KERN_NOTICE " SEQSTAT: %08lx  IPEND: %04lx  SYSCFG: %04lx\n",
@@ -1112,9 +1112,9 @@ unlock:
 
         if (((long)fp->seqstat &  SEQSTAT_EXCAUSE) &&
             (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
-                decode_address(buf, saved_dcplb_fault_addr);
+                decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
                 verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
-                decode_address(buf, saved_icplb_fault_addr);
+                decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
                 verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
         }
 
@@ -1153,20 +1153,21 @@ unlock:
 asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text));
 #endif
 
-asmlinkage int sys_bfin_spinlock(int *spinlock)
+static DEFINE_SPINLOCK(bfin_spinlock_lock);
+
+asmlinkage int sys_bfin_spinlock(int *p)
 {
-        int ret = 0;
-        int tmp = 0;
+        int ret, tmp = 0;
 
-        local_irq_disable();
-        ret = get_user(tmp, spinlock);
-        if (ret == 0) {
-                if (tmp)
+        spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
+        ret = get_user(tmp, p);
+        if (likely(ret == 0)) {
+                if (unlikely(tmp))
                         ret = 1;
-                tmp = 1;
-                put_user(tmp, spinlock);
+                else
+                        put_user(1, p);
         }
-        local_irq_enable();
+        spin_unlock(&bfin_spinlock_lock);
         return ret;
 }
 
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 7d12c6692a65..4b4341da0585 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -68,6 +68,8 @@ SECTIONS
                 __etext = .;
         }
 
+        NOTES
+
         /* Just in case the first read only is a 32-bit access */
         RO_DATA(4)
 
@@ -109,7 +111,6 @@ SECTIONS
 #endif
 
                 DATA_DATA
-                *(.data.*)
                 CONSTRUCTORS
 
                 /* make sure the init_task is aligned to the
@@ -161,12 +162,14 @@ SECTIONS
                 *(.con_initcall.init)
                 ___con_initcall_end = .;
         }
+        PERCPU(4)
         SECURITY_INIT
         .init.ramfs :
         {
                 . = ALIGN(4);
                 ___initramfs_start = .;
                 *(.init.ramfs)
+                . = ALIGN(4);
                 ___initramfs_end = .;
         }
 
@@ -212,7 +215,7 @@ SECTIONS
                 __ebss_b_l1 = .;
         }
 
-        __l2_lma_start = .;
+        __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
 
         .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1))
         {
@@ -240,7 +243,7 @@ SECTIONS
         /* Force trailing alignment of our init section so that when we
          * free our init memory, we don't leave behind a partial page.
          */
-        . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
+        . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2);
         . = ALIGN(PAGE_SIZE);
         ___init_end = .;
 
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c
index 5c87505165d3..762a7f02970a 100644
--- a/arch/blackfin/lib/checksum.c
+++ b/arch/blackfin/lib/checksum.c
@@ -29,6 +29,7 @@
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/module.h>
 #include <net/checksum.h>
 #include <asm/checksum.h>
 
@@ -76,6 +77,7 @@ __sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl)
 {
         return (__force __sum16)~do_csum(iph, ihl * 4);
 }
+EXPORT_SYMBOL(ip_fast_csum);
 
 /*
  * computes the checksum of a memory block at buff, length len,
@@ -104,6 +106,7 @@ __wsum csum_partial(const void *buff, int len, __wsum sum)
 
         return sum;
 }
+EXPORT_SYMBOL(csum_partial);
 
 /*
  * this routine is used for miscellaneous IP-like checksums, mainly
@@ -137,3 +140,4 @@ __wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
         memcpy(dst, src, len);
         return csum_partial(dst, len, sum);
 }
+EXPORT_SYMBOL(csum_partial_copy);
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index d60554dce87b..1863a6ba507c 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -1,31 +1,9 @@
 /*
- * File:         arch/blackfin/lib/ins.S
- * Based on:
- * Author:       Bas Vermeulen <bas@buyways.nl>
+ * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
  *
- * Created:      Tue Mar 22 15:27:24 CEST 2005
- * Description:  Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
- *
- * Modified:
- *               Copyright 2004-2008 Analog Devices Inc.
- *               Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/linkage.h>
@@ -33,6 +11,46 @@
 
 .align 2
 
+#ifdef CONFIG_IPIPE
+# define DO_CLI \
+        [--sp] = rets; \
+        [--sp] = (P5:0); \
+        sp += -12; \
+        call ___ipipe_stall_root_raw; \
+        sp += 12; \
+        (P5:0) = [sp++];
+# define CLI_INNER_NOP
+#else
+# define DO_CLI cli R3;
+# define CLI_INNER_NOP nop; nop; nop;
+#endif
+
+#ifdef CONFIG_IPIPE
+# define DO_STI \
+        sp += -12; \
+        call ___ipipe_unstall_root_raw; \
+        sp += 12; \
+2:      rets = [sp++];
+#else
+# define DO_STI 2: sti R3;
+#endif
+
+#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
+# define CLI_OUTER DO_CLI;
+# define STI_OUTER DO_STI;
+# define CLI_INNER 1:
+# if ANOMALY_05000416
+#  define STI_INNER nop; 2: nop;
+# else
+#  define STI_INNER 2:
+# endif
+#else
+# define CLI_OUTER
+# define STI_OUTER
+# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
+# define STI_INNER DO_STI;
+#endif
+
 /*
  * Reads on the Blackfin are speculative. In Blackfin terms, this means they
  * can be interrupted at any time (even after they have been issued on to the
@@ -53,170 +71,48 @@
  * buffers in/out of FIFOs.
  */
 
-ENTRY(_insl)
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-        P0 = R0;        /* P0 = port */
-        cli R3;
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s:  R0 = [P0];
-                [P1++] = R0;
-                NOP;
-.Llong_loop_e:  NOP;
-        sti R3;
-        RTS;
-#else
-        P0 = R0;        /* P0 = port */
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s:
-        CLI R3;
-        NOP; NOP; NOP;
-        R0 = [P0];
-        [P1++] = R0;
-.Llong_loop_e:
-        STI R3;
+#define COMMON_INS(func, ops) \
+ENTRY(_ins##func) \
+        P0 = R0;        /* P0 = port */ \
+        CLI_OUTER;      /* 3 instructions before first read access */ \
+        P1 = R1;        /* P1 = address */ \
+        P2 = R2;        /* P2 = count */ \
+        SSYNC; \
+ \
+        LSETUP(1f, 2f) LC0 = P2; \
+        CLI_INNER; \
+        ops; \
+        STI_INNER; \
+ \
+        STI_OUTER; \
+        RTS; \
+ENDPROC(_ins##func)
 
-        RTS;
-#endif
-ENDPROC(_insl)
-
-ENTRY(_insw)
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-        P0 = R0;        /* P0 = port */
-        cli R3;
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s:  R0 = W[P0];
-                W[P1++] = R0;
-                NOP;
-.Lword_loop_e:  NOP;
-        sti R3;
-        RTS;
-#else
-        P0 = R0;        /* P0 = port */
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s:
-        CLI R3;
-        NOP; NOP; NOP;
-        R0 = W[P0];
-        W[P1++] = R0;
-.Lword_loop_e:
-        STI R3;
-        RTS;
-
-#endif
-ENDPROC(_insw)
-
-ENTRY(_insw_8)
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-        P0 = R0;        /* P0 = port */
-        cli R3;
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s:  R0 = W[P0];
-                B[P1++] = R0;
-                R0 = R0 >> 8;
-                B[P1++] = R0;
-                NOP;
-.Lword8_loop_e: NOP;
-        sti R3;
-        RTS;
-#else
-        P0 = R0;        /* P0 = port */
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s:
-        CLI R3;
-        NOP; NOP; NOP;
-        R0 = W[P0];
-        B[P1++] = R0;
-        R0 = R0 >> 8;
-        B[P1++] = R0;
-        NOP;
-.Lword8_loop_e:
-        STI R3;
+COMMON_INS(l, \
+        R0 = [P0]; \
+        [P1++] = R0; \
+)
 
-        RTS;
-#endif
-ENDPROC(_insw_8)
+COMMON_INS(w, \
+        R0 = W[P0]; \
+        W[P1++] = R0; \
+)
 
-ENTRY(_insb)
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-        P0 = R0;        /* P0 = port */
-        cli R3;
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s:  R0 = B[P0];
-                B[P1++] = R0;
-                NOP;
-.Lbyte_loop_e:  NOP;
-        sti R3;
-        RTS;
-#else
-        P0 = R0;        /* P0 = port */
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s:
-        CLI R3;
-        NOP; NOP; NOP;
-        R0 = B[P0];
-        B[P1++] = R0;
-.Lbyte_loop_e:
-        STI R3;
+COMMON_INS(w_8, \
+        R0 = W[P0]; \
+        B[P1++] = R0; \
+        R0 = R0 >> 8; \
+        B[P1++] = R0; \
+)
 
-        RTS;
-#endif
-ENDPROC(_insb)
+COMMON_INS(b, \
+        R0 = B[P0]; \
+        B[P1++] = R0; \
+)
 
-ENTRY(_insl_16)
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-        P0 = R0;        /* P0 = port */
-        cli R3;
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
-.Llong16_loop_s:  R0 = [P0];
-                  W[P1++] = R0;
-                  R0 = R0 >> 16;
-                  W[P1++] = R0;
-                  NOP;
-.Llong16_loop_e:  NOP;
-        sti R3;
-        RTS;
-#else
-        P0 = R0;        /* P0 = port */
-        P1 = R1;        /* P1 = address */
-        P2 = R2;        /* P2 = count */
-        SSYNC;
-        LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
-.Llong16_loop_s:
-        CLI R3;
-        NOP; NOP; NOP;
-        R0 = [P0];
-        W[P1++] = R0;
-        R0 = R0 >> 16;
-        W[P1++] = R0;
-.Llong16_loop_e:
-        STI R3;
-        RTS;
-#endif
-ENDPROC(_insl_16)
+COMMON_INS(l_16, \
+        R0 = [P0]; \
+        W[P1++] = R0; \
+        R0 = R0 >> 16; \
+        W[P1++] = R0; \
+)
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
new file mode 100644
index 000000000000..abde120ee230
--- /dev/null
+++ b/arch/blackfin/lib/muldi3.S
@@ -0,0 +1,68 @@
+.align 2
+.global ___muldi3;
+.type ___muldi3, STT_FUNC;
+
+#ifdef CONFIG_ARITHMETIC_OPS_L1
+.section .l1.text
+#else
+.text
+#endif
+
+/*
+           R1:R0 * R3:R2
+         = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
+[X]      = (R1.h * R3.h) * 2^96
+[X]        + (R1.h * R3.l + R1.l * R3.h) * 2^80
+[X]        + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
+[T1]       + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
+[T2]       + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
+[T3]       + (R0.l * R2.h + R2.l * R0.h) * 2^16
+[T4]       + (R0.l * R2.l)
+
+        We can discard the first three lines marked "X" since we produce
+        only a 64 bit result.  So, we need ten 16-bit multiplies.
+
+        Individual mul-acc results:
+[E1]     =  R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
+[E2]     =  R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
+[E3]     =  R0.l * R2.h + R2.l * R0.h
+[E4]     =  R0.l * R2.l
+
+        We also need to add high parts from lower-level results to higher ones:
+        E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
+
+        One interesting property is that all parts of the result that depend
+        on the sign of the multiplication are discarded.  Those would be the
+        multiplications involving R1.h and R3.h, but only the top 16 bit of
+        the 32 bit result depend on the sign, and since R1.h and R3.h only
+        occur in E1, the top half of these results is cut off.
+        So, we can just use FU mode for all of the 16-bit multiplies, and
+        ignore questions of when to use mixed mode.  */
+
+___muldi3:
+        /* [SP] technically is part of the caller's frame, but we can
+           use it as scratch space.  */
+        A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12];      /* E1 */
+        A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4;         /* E1 */
+        A0 += A1;                                                       /* E1 */
+        R4 = A0.w;
+        A0 = R0.l * R3.l (FU);                                          /* E2 */
+        A0 += R2.l * R1.l (FU);                                         /* E2 */
+
+        A1 = R2.L * R0.L (FU);                                          /* E4 */
+        R3 = A1.w;
+        A1 = A1 >> 16;                                                  /* E3c */
+        A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU);                      /* E2, E3c */
+        A1 += R0.L * R2.H (FU);                                         /* E3c */
+        R0 = A1.w;
+        A1 = A1 >> 16;                                                  /* E2c */
+        A0 += A1;                                                       /* E2c */
+        R1 = A0.w;
+
+        /* low(result) = low(E3c):low(E4) */
+        R0 = PACK (R0.l, R3.l);
+        /* high(result) = E2c + (E1 << 16) */
+        R1.h = R1.h + R4.l (NS) || R4 = [SP];
+        RTS;
+
+.size ___muldi3, .-___muldi3
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c
deleted file mode 100644
index 303d0c6a6dba..000000000000
--- a/arch/blackfin/lib/muldi3.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * File:         arch/blackfin/lib/muldi3.c
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef SI_TYPE_SIZE
-#define SI_TYPE_SIZE 32
-#endif
-#define __ll_b (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((usitype) (t) % __ll_b)
-#define __ll_highpart(t) ((usitype) (t) / __ll_b)
-#define BITS_PER_UNIT 8
-
-#if !defined(umul_ppmm)
-#define umul_ppmm(w1, w0, u, v)                                         \
-  do {                                                                  \
-    usitype __x0, __x1, __x2, __x3;                                     \
-    usitype __ul, __vl, __uh, __vh;                                     \
-                                                                        \
-    __ul = __ll_lowpart (u);                                            \
-    __uh = __ll_highpart (u);                                           \
-    __vl = __ll_lowpart (v);                                            \
-    __vh = __ll_highpart (v);                                           \
-                                                                        \
-    __x0 = (usitype) __ul * __vl;                                       \
-    __x1 = (usitype) __ul * __vh;                                       \
-    __x2 = (usitype) __uh * __vl;                                       \
-    __x3 = (usitype) __uh * __vh;                                       \
-                                                                        \
-    __x1 += __ll_highpart (__x0);/* this can't give carry */            \
-    __x1 += __x2;               /* but this indeed can */               \
-    if (__x1 < __x2)            /* did we get it? */                    \
-      __x3 += __ll_b;           /* yes, add it in the proper pos. */    \
-                                                                        \
-    (w1) = __x3 + __ll_highpart (__x1);                                 \
-    (w0) = __ll_lowpart (__x1) * __ll_b + __ll_lowpart (__x0);          \
-  } while (0)
-#endif
-
-#if !defined(__umulsidi3)
-#define __umulsidi3(u, v)                                               \
-  ({diunion __w;                                                        \
-       umul_ppmm (__w.s.high, __w.s.low, u, v);                         \
-           __w.ll; })
-#endif
-
-typedef unsigned int usitype __attribute__ ((mode(SI)));
-typedef int sitype __attribute__ ((mode(SI)));
-typedef int ditype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-
-struct distruct {
-        sitype low, high;
-};
-typedef union {
-        struct distruct s;
-        ditype ll;
-} diunion;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-ditype __muldi3(ditype u, ditype v)__attribute__((l1_text));
-#endif
-
-ditype __muldi3(ditype u, ditype v)
-{
-        diunion w;
-        diunion uu, vv;
-
-        uu.ll = u, vv.ll = v;
-        w.ll = __umulsidi3(uu.s.low, vv.s.low);
-        w.s.high += ((usitype) uu.s.low * (usitype) vv.s.high
-                     + (usitype) uu.s.high * (usitype) vv.s.low);
-
-        return w.ll;
-}
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
new file mode 100644
index 000000000000..f397ede006bf
--- /dev/null
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -0,0 +1,233 @@
+if (BF51x)
+
+source "arch/blackfin/mach-bf518/boards/Kconfig"
+
+menu "BF518 Specific Configuration"
+
+comment "Alternative Multiplexing Scheme"
+
+choice
+        prompt "SPORT0"
+        default BF518_SPORT0_PORTG
+        help
+          Select PORT used for SPORT0. See Hardware Reference Manual
+
+config BF518_SPORT0_PORTF
+        bool "PORT F"
+        help
+          PORT F
+
+config BF518_SPORT0_PORTG
+        bool "PORT G"
+        help
+          PORT G
+endchoice
+
+choice
+        prompt "SPORT0 TSCLK Location"
+        depends on BF518_SPORT0_PORTG
+        default BF518_SPORT0_TSCLK_PG10
+        help
+          Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
+
+config BF518_SPORT0_TSCLK_PG10
+        bool "PORT PG10"
+        help
+          PORT PG10
+
+config BF518_SPORT0_TSCLK_PG14
+        bool "PORT PG14"
+        help
+          PORT PG14
+endchoice
+
+choice
+        prompt "UART1"
+        default BF518_UART1_PORTF
+        help
+          Select PORT used for UART1. See Hardware Reference Manual
+
+config BF518_UART1_PORTF
+        bool "PORT F"
+        help
+          PORT F
+
+config BF518_UART1_PORTG
+        bool "PORT G"
+        help
+          PORT G
+endchoice
+
+comment "Interrupt Priority Assignment"
+menu "Priority"
+
+config IRQ_PLL_WAKEUP
+        int "IRQ_PLL_WAKEUP"
+        default 7
+config IRQ_DMA0_ERROR
+        int "IRQ_DMA0_ERROR"
+        default 7
+config IRQ_DMAR0_BLK
+        int "IRQ_DMAR0_BLK"
+        default 7
+config IRQ_DMAR1_BLK
+        int "IRQ_DMAR1_BLK"
+        default 7
+config IRQ_DMAR0_OVR
+        int "IRQ_DMAR0_OVR"
+        default 7
+config IRQ_DMAR1_OVR
+        int "IRQ_DMAR1_OVR"
+        default 7
+config IRQ_PPI_ERROR
+        int "IRQ_PPI_ERROR"
+        default 7
+config IRQ_MAC_ERROR
+        int "IRQ_MAC_ERROR"
+        default 7
+config IRQ_SPORT0_ERROR
+        int "IRQ_SPORT0_ERROR"
+        default 7
+config IRQ_SPORT1_ERROR
+        int "IRQ_SPORT1_ERROR"
+        default 7
+config IRQ_PTP_ERROR
+        int "IRQ_PTP_ERROR"
+        default 7
+config IRQ_UART0_ERROR
+        int "IRQ_UART0_ERROR"
+        default 7
+config IRQ_UART1_ERROR
+        int "IRQ_UART1_ERROR"
+        default 7
+config IRQ_RTC
+        int "IRQ_RTC"
+        default 8
+config IRQ_PPI
+        int "IRQ_PPI"
+        default 8
+config IRQ_SPORT0_RX
+        int "IRQ_SPORT0_RX"
+        default 9
+config IRQ_SPORT0_TX
+        int "IRQ_SPORT0_TX"
+        default 9
+config IRQ_SPORT1_RX
+        int "IRQ_SPORT1_RX"
+        default 9
+config IRQ_SPORT1_TX
+        int "IRQ_SPORT1_TX"
+        default 9
+config IRQ_TWI
+        int "IRQ_TWI"
+        default 10
+config IRQ_SPI0
+        int "IRQ_SPI"
+        default 10
+config IRQ_UART0_RX
+        int "IRQ_UART0_RX"
+        default 10
+config IRQ_UART0_TX
+        int "IRQ_UART0_TX"
+        default 10
+config IRQ_UART1_RX
+        int "IRQ_UART1_RX"
+        default 10
+config IRQ_UART1_TX
+        int "IRQ_UART1_TX"
+        default 10
+config IRQ_OPTSEC
+        int "IRQ_OPTSEC"
+        default 11
+config IRQ_CNT
+        int "IRQ_CNT"
+        default 11
+config IRQ_MAC_RX
+        int "IRQ_MAC_RX"
+        default 11
+config IRQ_PORTH_INTA
+        int "IRQ_PORTH_INTA"
+        default 11
+config IRQ_MAC_TX
+        int "IRQ_MAC_TX/NFC"
+        default 11
+config IRQ_PORTH_INTB
+        int "IRQ_PORTH_INTB"
+        default 11
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 8
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
+        default 12
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
+        default 12
+config IRQ_TIMER3
+        int "IRQ_TIMER3"
+        default 12
+config IRQ_TIMER4
+        int "IRQ_TIMER4"
+        default 12
+config IRQ_TIMER5
+        int "IRQ_TIMER5"
+        default 12
+config IRQ_TIMER6
+        int "IRQ_TIMER6"
+        default 12
+config IRQ_TIMER7
+        int "IRQ_TIMER7"
+        default 12
+config IRQ_PORTG_INTA
+        int "IRQ_PORTG_INTA"
+        default 12
+config IRQ_PORTG_INTB
+        int "IRQ_PORTG_INTB"
+        default 12
+config IRQ_MEM_DMA0
+        int "IRQ_MEM_DMA0"
+        default 13
+config IRQ_MEM_DMA1
+        int "IRQ_MEM_DMA1"
+        default 13
+config IRQ_WATCH
+        int "IRQ_WATCH"
+        default 13
+config IRQ_PORTF_INTA
+        int "IRQ_PORTF_INTA"
+        default 13
+config IRQ_PORTF_INTB
+        int "IRQ_PORTF_INTB"
+        default 13
+config IRQ_SPI0_ERROR
+        int "IRQ_SPI0_ERROR"
+        default 7
+config IRQ_SPI1_ERROR
+        int "IRQ_SPI1_ERROR"
+        default 7
+config IRQ_RSI_INT0
+        int "IRQ_RSI_INT0"
+        default 7
+config IRQ_RSI_INT1
+        int "IRQ_RSI_INT1"
+        default 7
+config IRQ_PWM_TRIP
+        int "IRQ_PWM_TRIP"
+        default 10
+config IRQ_PWM_SYNC
+        int "IRQ_PWM_SYNC"
+        default 10
+config IRQ_PTP_STAT
+        int "IRQ_PTP_STAT"
+        default 10
+
+        help
+          Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
+          This applies to all the above.  It is not recommended to assign the
+          highest priority number 7 to UART or any other device.
+
+endmenu
+
+endmenu
+
+endif
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile
new file mode 100644
index 000000000000..168a193f9f9a
--- /dev/null
+++ b/arch/blackfin/mach-bf518/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf518/Makefile
+#
+
+obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig
new file mode 100644
index 000000000000..96163514ed22
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/Kconfig
@@ -0,0 +1,12 @@
+choice
+        prompt "System type"
+        default BFIN518F_EZBRD
+        help
+          Select your board!
+
+config BFIN518F_EZBRD
+        bool "BF518F-EZBRD"
+        help
+          BF518-EZBRD board support.
+
+endchoice
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile
new file mode 100644
index 000000000000..172e859c3a7f
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf518/boards/Makefile
+#
+
+obj-$(CONFIG_BFIN518F_EZBRD)            += ezbrd.o
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
new file mode 100644
index 000000000000..15f1351c8645
--- /dev/null
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -0,0 +1,669 @@
+/*
+ * File:         arch/blackfin/mach-bf518/boards/ezbrd.c
+ * Based on:     arch/blackfin/mach-bf527/boards/ezbrd.c
+ * Author:       Bryan Wu <cooloney@kernel.org>
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2005 National ICT Australia (NICTA)
+ *               Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/dma.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
+#include <asm/portmux.h>
+#include <asm/dpmc.h>
+#include <asm/bfin_sdh.h>
+#include <linux/spi/ad7877.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "ADI BF518F-EZBRD";
+
+/*
+ *  Driver needs to know address, irq and flag pin.
+ */
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition ezbrd_partitions[] = {
+        {
+                .name       = "bootloader(nor)",
+                .size       = 0x40000,
+                .offset     = 0,
+        }, {
+                .name       = "linux kernel(nor)",
+                .size       = 0x1C0000,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "file system(nor)",
+                .size       = MTDPART_SIZ_FULL,
+                .offset     = MTDPART_OFS_APPEND,
+        }
+};
+
+static struct physmap_flash_data ezbrd_flash_data = {
+        .width      = 2,
+        .parts      = ezbrd_partitions,
+        .nr_parts   = ARRAY_SIZE(ezbrd_partitions),
+};
+
+static struct resource ezbrd_flash_resource = {
+        .start = 0x20000000,
+        .end   = 0x203fffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ezbrd_flash_device = {
+        .name          = "physmap-flash",
+        .id            = 0,
+        .dev = {
+                .platform_data = &ezbrd_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &ezbrd_flash_resource,
+};
+#endif
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static struct platform_device bfin_mac_device = {
+        .name = "bfin_mac",
+};
+#endif
+
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+static struct mtd_partition bfin_spi_flash_partitions[] = {
+        {
+                .name = "bootloader(spi)",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = MTD_CAP_ROM
+        }, {
+                .name = "linux kernel(spi)",
+                .size = MTDPART_SIZ_FULL,
+                .offset = MTDPART_OFS_APPEND,
+        }
+};
+
+static struct flash_platform_data bfin_spi_flash_data = {
+        .name = "m25p80",
+        .parts = bfin_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
+        .type = "m25p16",
+};
+
+/* SPI flash chip (m25p64) */
+static struct bfin5xx_spi_chip spi_flash_chip_info = {
+        .enable_dma = 0,         /* use dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_SPI_ADC_BF533) \
+        || defined(CONFIG_SPI_ADC_BF533_MODULE)
+/* SPI ADC chip */
+static struct bfin5xx_spi_chip spi_adc_chip_info = {
+        .enable_dma = 1,         /* use dma transfer with this chip*/
+        .bits_per_word = 16,
+};
+#endif
+
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+static struct bfin5xx_spi_chip spi_mmc_chip_info = {
+        .enable_dma = 1,
+        .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_PBX)
+static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
+        .ctl_reg        = 0x4, /* send zero */
+        .enable_dma     = 0,
+        .bits_per_word  = 8,
+        .cs_change_per_word = 1,
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+
+static const struct ad7877_platform_data bfin_ad7877_ts_info = {
+        .model                  = 7877,
+        .vref_delay_usecs       = 50,   /* internal, no capacitor */
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .pressure_max           = 1000,
+        .pressure_min           = 0,
+        .stopacq_polarity       = 1,
+        .first_conversion_delay = 3,
+        .acquisition_time       = 1,
+        .averaging              = 1,
+        .pen_down_acc_interval  = 1,
+};
+#endif
+
+#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+         && defined(CONFIG_SND_SOC_WM8731_SPI)
+static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 8,
+};
+#endif
+
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+        {
+                /* the modalias must be the same as spi device driver name */
+                .modalias = "m25p80", /* Name of spi_driver for this device */
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0, /* Framework bus number */
+                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
+                .platform_data = &bfin_spi_flash_data,
+                .controller_data = &spi_flash_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+
+#if defined(CONFIG_SPI_ADC_BF533) \
+        || defined(CONFIG_SPI_ADC_BF533_MODULE)
+        {
+                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
+                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0, /* Framework bus number */
+                .chip_select = 1, /* Framework chip select. */
+                .platform_data = NULL, /* No spi_driver specific config */
+                .controller_data = &spi_adc_chip_info,
+        },
+#endif
+
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+        {
+                .modalias = "spi_mmc_dummy",
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = NULL,
+                .controller_data = &spi_mmc_chip_info,
+                .mode = SPI_MODE_3,
+        },
+        {
+                .modalias = "spi_mmc",
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
+                .platform_data = NULL,
+                .controller_data = &spi_mmc_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_PBX)
+        {
+                .modalias = "fxs-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 8 - CONFIG_J11_JUMPER,
+                .controller_data = &spi_si3xxx_chip_info,
+                .mode = SPI_MODE_3,
+        },
+        {
+                .modalias = "fxo-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 8 - CONFIG_J19_JUMPER,
+                .controller_data = &spi_si3xxx_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+        {
+                .modalias               = "ad7877",
+                .platform_data          = &bfin_ad7877_ts_info,
+                .irq                    = IRQ_PF8,
+                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num        = 0,
+                .chip_select  = 2,
+                .controller_data = &spi_ad7877_chip_info,
+        },
+#endif
+#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+         && defined(CONFIG_SND_SOC_WM8731_SPI)
+        {
+                .modalias       = "wm8731",
+                .max_speed_hz   = 3125000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num        = 0,
+                .chip_select    = 5,
+                .controller_data = &spi_wm8731_chip_info,
+                .mode = SPI_MODE_0,
+        },
+#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = &spidev_chip_info,
+        },
+#endif
+#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+        {
+                .modalias = "bfin-lq035q1-spi",
+                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = &lq035q1_spi_chip_info,
+                .mode = SPI_CPHA | SPI_CPOL,
+        },
+#endif
+};
+
+/* SPI controller data */
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+/* SPI (0) */
+static struct bfin5xx_spi_master bfin_spi0_info = {
+        .num_chipselect = 5,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI0,
+                .end   = CH_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_spi0_device = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
+        .dev = {
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
+        },
+};
+
+/* SPI (1) */
+static struct bfin5xx_spi_master bfin_spi1_info = {
+        .num_chipselect = 5,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
+};
+
+static struct resource bfin_spi1_resource[] = {
+        [0] = {
+                .start = SPI1_REGBASE,
+                .end   = SPI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI1,
+                .end   = CH_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_spi1_device = {
+        .name = "bfin-spi",
+        .id = 1, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi1_resource),
+        .resource = bfin_spi1_resource,
+        .dev = {
+                .platform_data = &bfin_spi1_info, /* Passed to driver */
+        },
+};
+#endif  /* spi master and devices */
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+static struct resource bfin_uart_resources[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+};
+
+static struct platform_device bfin_uart_device = {
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart_resources),
+        .resource = bfin_uart_resources,
+};
+#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir1_device = {
+        .name = "bfin_sir",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
+};
+#endif
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI,
+                .end   = IRQ_TWI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c_bfin_twi_device = {
+        .name = "i2c-bfin-twi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
+};
+#endif
+
+#ifdef CONFIG_I2C_BOARDINFO
+static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
+#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
+        {
+                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
+        },
+#endif
+#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
+        {
+                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
+                .irq = IRQ_PF8,
+        },
+#endif
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+static struct platform_device bfin_sport0_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 0,
+};
+
+static struct platform_device bfin_sport1_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 1,
+};
+#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+        {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
+        {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+        .buttons        = bfin_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+        .name      = "gpio-keys",
+        .dev = {
+                .platform_data = &bfin_gpio_keys_data,
+        },
+};
+#endif
+
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+
+static struct bfin_sd_host bfin_sdh_data = {
+        .dma_chan = CH_RSI,
+        .irq_int0 = IRQ_RSI_INT0,
+        .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
+};
+
+static struct platform_device bf51x_sdh_device = {
+        .name = "bfin-sdh",
+        .id = 0,
+        .dev = {
+                .platform_data = &bfin_sdh_data,
+        },
+};
+#endif
+
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
+static const unsigned int cclk_vlev_datasheet[] =
+{
+        VRPAIR(VLEV_100, 400000000),
+        VRPAIR(VLEV_105, 426000000),
+        VRPAIR(VLEV_110, 500000000),
+        VRPAIR(VLEV_115, 533000000),
+        VRPAIR(VLEV_120, 600000000),
+};
+
+static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
+        .tuple_tab = cclk_vlev_datasheet,
+        .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
+        .vr_settling_time = 25 /* us */,
+};
+
+static struct platform_device bfin_dpmc = {
+        .name = "bfin dpmc",
+        .dev = {
+                .platform_data = &bfin_dmpc_vreg_data,
+        },
+};
+
+static struct platform_device *stamp_devices[] __initdata = {
+
+        &bfin_dpmc,
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+        &bfin_mac_device,
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &bfin_spi0_device,
+        &bfin_spi1_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+        &bfin_uart_device,
+#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+        &bfin_sport0_uart_device,
+        &bfin_sport1_uart_device,
+#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+        &bfin_device_gpiokeys,
+#endif
+
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+        &bf51x_sdh_device,
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &ezbrd_flash_device,
+#endif
+
+        &bfin_gpios_device,
+};
+
+static int __init ezbrd_init(void)
+{
+        printk(KERN_INFO "%s(): registering device resources\n", __func__);
+
+#ifdef CONFIG_I2C_BOARDINFO
+        i2c_register_board_info(0, bfin_i2c_board_info,
+                                ARRAY_SIZE(bfin_i2c_board_info));
+#endif
+
+        platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
+        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        return 0;
+}
+
+arch_initcall(ezbrd_init);
+
+void native_machine_restart(char *cmd)
+{
+        /* workaround reboot hang when booting from SPI */
+        if ((bfin_read_SYSCR() & 0x7) == 0x3)
+                bfin_gpio_reset_spi0_ssel1();
+}
+
+void bfin_get_ether_addr(char *addr)
+{
+        /* the MAC is stored in OTP memory page 0xDF */
+        u32 ret;
+        u64 otp_mac;
+        u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
+
+        ret = otp_read(0xDF, 0x00, &otp_mac);
+        if (!(ret & 0x1)) {
+                char *otp_mac_p = (char *)&otp_mac;
+                for (ret = 0; ret < 6; ++ret)
+                        addr[ret] = otp_mac_p[5 - ret];
+        }
+}
+EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
new file mode 100644
index 000000000000..698e88ca5104
--- /dev/null
+++ b/arch/blackfin/mach-bf518/dma.c
@@ -0,0 +1,118 @@
+/*
+ * File:         arch/blackfin/mach-bf518/dma.c
+ * Based on:
+ * Author:       Bryan Wu <cooloney@kernel.org>
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA11_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+};
+EXPORT_SYMBOL(dma_io_base_addr);
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_PPI:
+                ret_irq = IRQ_PPI;
+                break;
+
+        case CH_EMAC_RX:
+                ret_irq = IRQ_MAC_RX;
+                break;
+
+        case CH_EMAC_TX:
+                ret_irq = IRQ_MAC_TX;
+                break;
+
+        case CH_UART1_RX:
+                ret_irq = IRQ_UART1_RX;
+                break;
+
+        case CH_UART1_TX:
+                ret_irq = IRQ_UART1_TX;
+                break;
+
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+
+        case CH_SPI0:
+                ret_irq = IRQ_SPI0;
+                break;
+
+        case CH_UART0_RX:
+                ret_irq = IRQ_UART0_RX;
+                break;
+
+        case CH_UART0_TX:
+                ret_irq = IRQ_UART0_TX;
+                break;
+
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MEM_DMA0;
+                break;
+
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MEM_DMA1;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
new file mode 100644
index 000000000000..e5b4bef0edae
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -0,0 +1,79 @@
+/*
+ * File: include/asm-blackfin/mach-bf518/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file shoule be up to date with:
+ *  - ????
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (1)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (1)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 (1)
+/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
+#define ANOMALY_05000438 (1)
+/* Preboot Cannot be Used to Program the PLL_DIV Register */
+#define ANOMALY_05000439 (1)
+/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
+#define ANOMALY_05000440 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* Incorrect L1 Instruction Bank B Memory Map Location */
+#define ANOMALY_05000444 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (0)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+
+#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
new file mode 100644
index 000000000000..78da1a07ee73
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bf518.h
@@ -0,0 +1,132 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/bf518.h
+ * Based on:    include/asm-blackfin/mach-bf527/bf527.h
+ * Author:      Michael Hennerich (michael.hennerich@analog.com)
+ *
+ * Created:
+ * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF518
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF518_H__
+#define __MACH_BF518_H__
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR            0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************/
+
+#define BFIN_DSUBBANKS  4
+#define BFIN_DWAYS              2
+#define BFIN_DLINES             64
+#define BFIN_ISUBBANKS  4
+#define BFIN_IWAYS              4
+#define BFIN_ILINES             32
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+#ifdef CONFIG_C_CDPRIO
+#define V_CDPRIO 0x100
+#else
+#define V_CDPRIO 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
+
+#ifdef CONFIG_BF518
+#define CPU "BF518"
+#define CPUID 0x27e8
+#endif
+#ifdef CONFIG_BF516
+#define CPU "BF516"
+#define CPUID 0x27e8
+#endif
+#ifdef CONFIG_BF514
+#define CPU "BF514"
+#define CPUID 0x27e8
+#endif
+#ifdef CONFIG_BF512
+#define CPU "BF512"
+#define CPUID 0x27e8
+#endif
+
+#ifndef CPU
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
+#endif
+
+#endif                          /* __MACH_BF518_H__  */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..b50a63b975a2
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,169 @@
+/*
+ * file:        include/asm-blackfin/mach-bf518/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
+#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
+#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
+#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
+#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
+#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
+#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
+
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
+#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
+#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
+#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
+# define CONFIG_SERIAL_BFIN_CTSRTS
+
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_CTS_PIN
+#  define CONFIG_UART1_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_RTS_PIN
+#  define CONFIG_UART1_RTS_PIN -1
+# endif
+#endif
+
+#define BFIN_UART_TX_FIFO_SIZE  2
+
+/*
+ * The pin configuration is different from schematic
+ */
+struct bfin_serial_port {
+        struct uart_port port;
+        unsigned int old_status;
+        unsigned int lsr;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int tx_done;
+        int tx_count;
+        struct circ_buf rx_dma_buf;
+        struct timer_list rx_dma_timer;
+        int rx_dma_nrows;
+        unsigned int tx_dma_channel;
+        unsigned int rx_dma_channel;
+        struct work_struct tx_dma_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        struct timer_list cts_timer;
+        int cts_pin;
+        int rts_pin;
+#endif
+};
+
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
+{
+        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
+        uart->lsr |= (lsr & (BI|FE|PE|OE));
+        return lsr | uart->lsr;
+}
+
+static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
+{
+        uart->lsr = 0;
+        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
+}
+
+struct bfin_serial_res {
+        unsigned long uart_base_addr;
+        int uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int uart_tx_dma_channel;
+        unsigned int uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int uart_cts_pin;
+        int uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+         0xFFC00400,
+         IRQ_UART0_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+         CH_UART0_TX,
+         CH_UART0_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+         CONFIG_UART0_CTS_PIN,
+         CONFIG_UART0_RTS_PIN,
+#endif
+         },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+         0xFFC02000,
+         IRQ_UART1_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+         CH_UART1_TX,
+         CH_UART1_RX,
+#endif
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+         CONFIG_UART1_CTS_PIN,
+         CONFIG_UART1_RTS_PIN,
+#endif
+         },
+#endif
+};
+
+#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
new file mode 100644
index 000000000000..d1a2b9ca6227
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -0,0 +1,105 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF518_FAMILY
+
+#include "bf518.h"
+#include "mem_map.h"
+#include "defBF512.h"
+#include "anomaly.h"
+
+#if defined(CONFIG_BF518)
+#include "defBF518.h"
+#endif
+
+#if defined(CONFIG_BF516)
+#include "defBF516.h"
+#endif
+
+#if defined(CONFIG_BF514)
+#include "defBF514.h"
+#endif
+
+#if defined(CONFIG_BF512)
+#include "defBF512.h"
+#endif
+
+#if !defined(__ASSEMBLY__)
+#include "cdefBF512.h"
+
+#if defined(CONFIG_BF518)
+#include "cdefBF518.h"
+#endif
+
+#if defined(CONFIG_BF516)
+#include "cdefBF516.h"
+#endif
+
+#if defined(CONFIG_BF514)
+#include "cdefBF514.h"
+#endif
+#endif
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+
+#define BFIN_UART_NR_PORTS      2
+
+#define OFFSET_THR              0x00    /* Transmit Holding register            */
+#define OFFSET_RBR              0x00    /* Receive Buffer register              */
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24    /* Global Control Register              */
+
+/* DPMC*/
+#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
+#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
+#define STOPCK_OFF STOPCK
+
+/* PLL_DIV Masks                                                                                                        */
+#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
+#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
+#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
+#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
+
+#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
new file mode 100644
index 000000000000..820c13c4daaa
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -0,0 +1,46 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/cdefbf512.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF512_H
+#define _CDEF_BF512_H
+
+/* include all Core registers and bit definitions */
+#include "defBF512.h"
+
+/* include core specific register pointer definitions */
+#include <asm/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "cdefBF51x_base.h"
+
+#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
new file mode 100644
index 000000000000..9521e178fb28
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -0,0 +1,48 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/cdefbf514.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF514_H
+#define _CDEF_BF514_H
+
+/* include all Core registers and bit definitions */
+#include "defBF514.h"
+
+/* include core specific register pointer definitions */
+#include <asm/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "cdefBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
+
+#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
new file mode 100644
index 000000000000..4e26ccfcef97
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -0,0 +1,213 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/cdefbf516.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF516_H
+#define _CDEF_BF516_H
+
+/* include all Core registers and bit definitions */
+#include "defBF516.h"
+
+/* include core specific register pointer definitions */
+#include <asm/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "cdefBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
+
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
+#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
+#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
+#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
+#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
+#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
+#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
+#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
+#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
+#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
+#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
+#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
+#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
+#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
+
+#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
+#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
+#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
+#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
+#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
+#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
+#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
+#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
+
+#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
+#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
+#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
+#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
+#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
+
+#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
+#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
+#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
+#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
+#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
+#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
+#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
+#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
+#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
+#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
+#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
+#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
+#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
+#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
+#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
+#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
+#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
+#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
+#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
+#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
+#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
+#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
+#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
+#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
+
+#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
+#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
+#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
+#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
+#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
+#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
+#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
+#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
+#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
+#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
+#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
+#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
+#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
+#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
+#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
+#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
+#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
+#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
+#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
+#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
+#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
+#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
+#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
+
+#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
new file mode 100644
index 000000000000..bafb370cfb3c
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -0,0 +1,282 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/cdefbf518.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF518_H
+#define _CDEF_BF518_H
+
+/* include all Core registers and bit definitions */
+#include "defBF518.h"
+
+/* include core specific register pointer definitions */
+#include <asm/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
+
+/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "cdefBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
+
+
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
+#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
+#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
+#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
+#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
+#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
+#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
+#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
+#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
+#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
+#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
+#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
+#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
+#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
+
+#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
+#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
+#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
+#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
+#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
+#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
+#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
+#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
+
+#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
+#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
+#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
+#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
+#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
+
+#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
+#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
+#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
+#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
+#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
+#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
+#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
+#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
+#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
+#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
+#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
+#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
+#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
+#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
+#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
+#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
+#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
+#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
+#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
+#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
+#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
+#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
+#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
+#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
+
+#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
+#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
+#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
+#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
+#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
+#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
+#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
+#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
+#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
+#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
+#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
+#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
+#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
+#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
+#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
+#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
+#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
+#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
+#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
+#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
+#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
+#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
+#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
+
+/* Removable Storage Interface Registers */
+
+#define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)
+#define bfin_write_RSI_PWR_CTL(val)    bfin_write16(RSI_PWR_CONTROL, val)
+#define bfin_read_RSI_CLK_CTL()        bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CTL(val)    bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CTL()       bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CTL(val)   bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUS_CLR()     bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CTL()      bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CTL(val)  bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_E_STATUS()       bfin_read16(RSI_ESTAT)
+#define bfin_write_RSI_E_STATUS(val)   bfin_write16(RSI_ESTAT, val)
+#define bfin_read_RSI_E_MASK()         bfin_read16(RSI_EMASK)
+#define bfin_write_RSI_E_MASK(val)     bfin_write16(RSI_EMASK, val)
+#define bfin_read_RSI_CFG()            bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CFG(val)        bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
+#define bfin_read_RSI_PID4()           bfin_read16(RSI_PID4)
+#define bfin_write_RSI_PID4(val)       bfin_write16(RSI_PID4, val)
+#define bfin_read_RSI_PID5()           bfin_read16(RSI_PID5)
+#define bfin_write_RSI_PID5(val)       bfin_write16(RSI_PID5, val)
+#define bfin_read_RSI_PID6()           bfin_read16(RSI_PID6)
+#define bfin_write_RSI_PID6(val)       bfin_write16(RSI_PID6, val)
+#define bfin_read_RSI_PID7()           bfin_read16(RSI_PID7)
+#define bfin_write_RSI_PID7(val)       bfin_write16(RSI_PID7, val)
+
+
+#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
new file mode 100644
index 000000000000..ee3d4733369c
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -0,0 +1,1208 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/cdefBF51x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF52X_H
+#define _CDEF_BF52X_H
+
+#include <asm/blackfin.h>
+
+#include "defBF51x_base.h"
+
+/* Include core specific register pointer definitions                                                           */
+#include <asm/cdef_LPBlackfin.h>
+
+/* ==== begin from cdefBF534.h ==== */
+
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
+
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
+#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX32)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX32, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX32)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX32, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX16)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX16, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX16)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX16, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX32)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX32, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX32)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX32, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX16)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX16, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX16)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX16, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
+#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
+#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* OTP/FUSE Registers */
+
+#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
+#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
+#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
+#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
+#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
+#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
+#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
+
+/* NFC Registers */
+
+#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
+#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
+#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
+#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
+#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
+#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
+#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
+#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
+#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
+#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
+#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
+#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
+#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
+#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
+#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
+#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
+
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
new file mode 100644
index 000000000000..a96ca90154dd
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -0,0 +1,42 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/defBF512.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF512_H
+#define _DEF_BF512_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "defBF51x_base.h"
+
+#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
new file mode 100644
index 000000000000..543f2913b3f5
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -0,0 +1,113 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/defBF514.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF514_H
+#define _DEF_BF514_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "defBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+
+/* Removable Storage Interface Registers */
+
+#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
+#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
+#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
+#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
+#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
+#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
+#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
+#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
+#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
+#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
+#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
+#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
+#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
+#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
+#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
+#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
+#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
+#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
+#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
+#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
+#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
+#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
+#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
+#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
+#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
+#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
+#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
+
+#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
new file mode 100644
index 000000000000..149a269306c5
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -0,0 +1,490 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/defBF516.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF516_H
+#define _DEF_BF516_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "defBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
+#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
+#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
+#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
+#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
+#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
+#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
+#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
+#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
+#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
+#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
+#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
+#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
+#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
+#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
+#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
+
+#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
+#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
+#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
+#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
+#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
+#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
+#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
+#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
+
+#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
+#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
+#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
+#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
+#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
+
+#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
+#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
+#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
+#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
+#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
+#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
+#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
+#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
+#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
+#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
+#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
+#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
+#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
+#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
+#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
+#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
+#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
+#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
+#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
+#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
+#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
+#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
+#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
+#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
+#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
+#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
+#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
+#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
+#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
+#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
+#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
+#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
+#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
+#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
+#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
+#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
+#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
+#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
+#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
+#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
+#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
+#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
+#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
+#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
+#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
+#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
+#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
+#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
+#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
+#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
+#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
+#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
+#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
+#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
+#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
+#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
+#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
+#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
+#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
+#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
+#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
+#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
+#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
+#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
+#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
+#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
+#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
+#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
+#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
+#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
+#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
+#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
+#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
+#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
+#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
+#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE                 0x00000001     /* Receiver Enable                                    */
+#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
+#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
+#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
+#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
+#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
+#define IFE                0x00000100     /* Inverse Filtering Enable                           */
+#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
+#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
+#define PSF                0x00000800     /* Pass Short Frames Enable                           */
+#define RAF                0x00001000     /* Receive-All Mode                                   */
+#define TE                 0x00010000     /* Transmitter Enable                                 */
+#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
+#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
+#define DC                 0x00080000     /* Deferral Check                                     */
+#define BOLMT              0x00300000     /* Back-Off Limit                                     */
+#define BOLMT_10           0x00000000     /*            10-bit range                            */
+#define BOLMT_8            0x00100000     /*            8-bit range                             */
+#define BOLMT_4            0x00200000     /*            4-bit range                             */
+#define BOLMT_1            0x00300000     /*            1-bit range                             */
+#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
+#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
+#define RMII               0x01000000     /* RMII/MII* Mode                                     */
+#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
+#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
+#define LB                 0x08000000     /* Internal Loopback Enable                           */
+#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
+#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
+#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
+#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
+#define REGAD              0x000007C0     /* STA Register Address                               */
+#define PHYAD              0x0000F800     /* PHY Device Address                                 */
+
+#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA            0x0000FFFF     /* Station Management Data                            */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
+#define FLCE               0x00000002     /* Flow Control Enable                                */
+#define PCF                0x00000004     /* Pass Control Frames                                */
+#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
+#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
+#define MPKE               0x00000002    /* Magic Packet Enable                                 */
+#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
+#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
+#define MPKS               0x00000020    /* Magic Packet Received Status                        */
+#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
+#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
+#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
+#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
+#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
+#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
+#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
+#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
+#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
+#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
+#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
+#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
+#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
+#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
+#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
+#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
+#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
+#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
+#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
+#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
+#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
+#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
+#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
+#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
+#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
+#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
+#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
+#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
+#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
+#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
+#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
+#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
+#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
+#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
+#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
+#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
+#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
+#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
+#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
+#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
+#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
+#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
+#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
+#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
+#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
+
+#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
+#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
+#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
+#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
+#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
+#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
+#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
+#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
+#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
+#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
+#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
+#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
+#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
+#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
+#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC              0x00000001    /* Reset All Counters                                     */
+#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
+#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
+#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
+#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
+#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
+#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
+#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
+#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
+#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
+#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
+#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
+#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
+#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
+#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
+#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
+#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
+#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
+#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
+#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
+#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
+#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
+#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
+#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
+#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
+#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
+#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
+
+#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
+#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
+#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
+#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
+#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
+#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
+#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
+#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
+#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
+#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
+#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
+#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
+#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
+#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
+#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
+#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
+#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
+#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
+#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
+#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
+#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
+#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
+#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+
+/* Removable Storage Interface Registers */
+
+#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
+#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
+#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
+#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
+#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
+#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
+#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
+#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
+#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
+#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
+#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
+#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
+#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
+#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
+#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
+#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
+#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
+#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
+#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
+#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
+#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
+#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
+#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
+#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
+#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
+#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
+#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
+
+#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
new file mode 100644
index 000000000000..6e982abf4ede
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -0,0 +1,651 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/defBF518.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF518_H
+#define _DEF_BF518_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
+
+/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
+#include "defBF51x_base.h"
+
+/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
+#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
+#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
+#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
+#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
+#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
+#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
+#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
+#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
+#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
+#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
+#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
+#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
+#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
+#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
+#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
+
+#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
+#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
+#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
+#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
+#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
+#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
+#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
+#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
+
+#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
+#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
+#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
+#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
+#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
+
+#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
+#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
+#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
+#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
+#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
+#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
+#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
+#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
+#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
+#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
+#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
+#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
+#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
+#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
+#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
+#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
+#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
+#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
+#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
+#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
+#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
+#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
+#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
+#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
+#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
+#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
+#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
+#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
+#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
+#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
+#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
+#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
+#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
+#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
+#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
+#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
+#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
+#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
+#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
+#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
+#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
+#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
+#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
+#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
+#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
+#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
+#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
+#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
+#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
+#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
+#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
+#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
+#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
+#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
+#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
+#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
+#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
+#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
+#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
+#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
+#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
+#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
+#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
+#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
+#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
+#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
+#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
+#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
+#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
+#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
+#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
+#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
+#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
+#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
+#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
+#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE                 0x00000001     /* Receiver Enable                                    */
+#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
+#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
+#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
+#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
+#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
+#define IFE                0x00000100     /* Inverse Filtering Enable                           */
+#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
+#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
+#define PSF                0x00000800     /* Pass Short Frames Enable                           */
+#define RAF                0x00001000     /* Receive-All Mode                                   */
+#define TE                 0x00010000     /* Transmitter Enable                                 */
+#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
+#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
+#define DC                 0x00080000     /* Deferral Check                                     */
+#define BOLMT              0x00300000     /* Back-Off Limit                                     */
+#define BOLMT_10           0x00000000     /*            10-bit range                            */
+#define BOLMT_8            0x00100000     /*            8-bit range                             */
+#define BOLMT_4            0x00200000     /*            4-bit range                             */
+#define BOLMT_1            0x00300000     /*            1-bit range                             */
+#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
+#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
+#define RMII               0x01000000     /* RMII/MII* Mode                                     */
+#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
+#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
+#define LB                 0x08000000     /* Internal Loopback Enable                           */
+#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
+#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
+#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
+#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
+#define REGAD              0x000007C0     /* STA Register Address                               */
+#define PHYAD              0x0000F800     /* PHY Device Address                                 */
+
+#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA            0x0000FFFF     /* Station Management Data                            */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
+#define FLCE               0x00000002     /* Flow Control Enable                                */
+#define PCF                0x00000004     /* Pass Control Frames                                */
+#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
+#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
+#define MPKE               0x00000002    /* Magic Packet Enable                                 */
+#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
+#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
+#define MPKS               0x00000020    /* Magic Packet Received Status                        */
+#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
+#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
+#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
+#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
+#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
+#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
+#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
+#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
+#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
+#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
+#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
+#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
+#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
+#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
+#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
+#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
+#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
+#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
+#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
+#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
+#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
+#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
+#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
+#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
+#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
+#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
+#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
+#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
+#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
+#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
+#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
+#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
+#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
+#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
+#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
+#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
+#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
+#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
+#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
+#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
+#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
+#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
+#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
+#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
+#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
+
+#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
+#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
+#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
+#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
+#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
+#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
+#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
+#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
+#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
+#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
+#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
+#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
+#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
+#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
+#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC              0x00000001    /* Reset All Counters                                     */
+#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
+#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
+#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
+#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
+#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
+#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
+#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
+#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
+#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
+#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
+#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
+#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
+#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
+#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
+#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
+#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
+#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
+#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
+#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
+#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
+#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
+#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
+#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
+#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
+#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
+#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
+
+#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
+#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
+#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
+#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
+#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
+#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
+#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
+#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
+#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
+#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
+#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
+#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
+#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
+#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
+#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
+#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
+#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
+#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
+#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
+#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
+#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
+#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
+#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+
+/* Removable Storage Interface Registers */
+
+#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
+#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
+#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
+#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
+#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
+#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
+#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
+#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
+#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
+#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
+#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
+#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
+#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
+#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
+#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
+#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
+#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
+#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
+#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
+#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
+#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
+#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
+#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
+#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
+#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
+#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
+#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
+#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
+
+/* PTP TSYNC Registers */
+
+#define EMAC_PTP_CTL                   0xFFC030A0 /* PTP Block Control */
+#define EMAC_PTP_IE                    0xFFC030A4 /* PTP Block Interrupt Enable */
+#define EMAC_PTP_ISTAT                 0xFFC030A8 /* PTP Block Interrupt Status */
+#define EMAC_PTP_FOFF                  0xFFC030AC /* PTP Filter offset Register */
+#define EMAC_PTP_FV1                   0xFFC030B0 /* PTP Filter Value Register 1 */
+#define EMAC_PTP_FV2                   0xFFC030B4 /* PTP Filter Value Register 2 */
+#define EMAC_PTP_FV3                   0xFFC030B8 /* PTP Filter Value Register 3 */
+#define EMAC_PTP_ADDEND                0xFFC030BC /* PTP Addend for Frequency Compensation */
+#define EMAC_PTP_ACCR                  0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
+#define EMAC_PTP_OFFSET                0xFFC030C4 /* PTP Time Offset Register */
+#define EMAC_PTP_TIMELO                0xFFC030C8 /* PTP Precision Clock Time Low */
+#define EMAC_PTP_TIMEHI                0xFFC030CC /* PTP Precision Clock Time High */
+#define EMAC_PTP_RXSNAPLO              0xFFC030D0 /* PTP Receive Snapshot Register Low */
+#define EMAC_PTP_RXSNAPHI              0xFFC030D4 /* PTP Receive Snapshot Register High */
+#define EMAC_PTP_TXSNAPLO              0xFFC030D8 /* PTP Transmit Snapshot Register Low */
+#define EMAC_PTP_TXSNAPHI              0xFFC030DC /* PTP Transmit Snapshot Register High */
+#define EMAC_PTP_ALARMLO               0xFFC030E0 /* PTP Alarm time Low */
+#define EMAC_PTP_ALARMHI               0xFFC030E4 /* PTP Alarm time High */
+#define EMAC_PTP_ID_OFF                0xFFC030E8 /* PTP Capture ID offset register */
+#define EMAC_PTP_ID_SNAP               0xFFC030EC /* PTP Capture ID register */
+#define EMAC_PTP_PPS_STARTLO           0xFFC030F0 /* PPS Start Time Low */
+#define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
+#define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for SDH_COMMAND */
+
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define                     CMD_E  0x400      /* Command Enable */
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define                    PWR_ON  0x3        /* Power On */
+#if 0
+#define                       TBD  0x3c       /* TBD */
+#endif
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                   ROD_CTL  0x80       /* Rod Control */
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
+#define               DAT_TIME_OUT  0x8        /* Data Time Out */
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                   DAT_END  0x100      /* Data End */
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+
+/* Bit masks for SDH_MASK0 */
+
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+
+/* Bit masks for SDH_E_MASK */
+
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+
+/* Bit masks for SDH_CFG */
+
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define                       RWR  0x1        /* Read Wait Request */
+
+#endif /* _DEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
new file mode 100644
index 000000000000..1bec8d1c2a73
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -0,0 +1,1940 @@
+/*
+ * File:         include/asm-blackfin/mach-bf518/defBF51x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF51X_H
+#define _DEF_BF51X_H
+
+
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
+/* ************************************************************** */
+
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register                           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID                          0xFFC00014      /* Device ID Register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                                */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                                */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register                      */
+
+#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                              */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                              */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                              */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                              */
+#define SIC_ISR0                        0xFFC00120      /* Interrupt Status Register                                    */
+#define SIC_IWR0                        0xFFC00124      /* Interrupt Wakeup Register                                    */
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+/* SPI0 Controller                      (0xFFC00500 - 0xFFC005FF)                                                       */
+#define SPI0_REGBASE                    0xFFC00500
+#define SPI0_CTL                        0xFFC00500      /* SPI Control Register                                         */
+#define SPI0_FLG                        0xFFC00504      /* SPI Flag register                                            */
+#define SPI0_STAT                       0xFFC00508      /* SPI Status register                                          */
+#define SPI0_TDBR                       0xFFC0050C      /* SPI Transmit Data Buffer Register                            */
+#define SPI0_RDBR                       0xFFC00510      /* SPI Receive Data Buffer Register                             */
+#define SPI0_BAUD                       0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI0_SHADOW                     0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+/* SPI1 Controller                      (0xFFC03400 - 0xFFC034FF)                                                       */
+#define SPI1_REGBASE                    0xFFC03400
+#define SPI1_CTL                        0xFFC03400      /* SPI Control Register                                         */
+#define SPI1_FLG                        0xFFC03404      /* SPI Flag register                                            */
+#define SPI1_STAT                       0xFFC03408      /* SPI Status register                                          */
+#define SPI1_TDBR                       0xFFC0340C      /* SPI Transmit Data Buffer Register                            */
+#define SPI1_RDBR                       0xFFC03410      /* SPI Receive Data Buffer Register                             */
+#define SPI1_BAUD                       0xFFC03414      /* SPI Baud rate Register                                       */
+#define SPI1_SHADOW                     0xFFC03418      /* SPI_RDBR Shadow Register                                     */
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
+#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
+#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
+#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
+#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
+#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+/*
+** ********************* PLL AND RESET MASKS ****************************************/
+/* PLL_CTL Masks                                                                                                                                        */
+#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
+#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
+#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
+#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
+#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
+#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
+#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
+
+/* PLL_DIV Masks                                                                                                                */
+#define SSEL                    0x000F  /* System Select                                                */
+#define CSEL                    0x0030  /* Core Select                                                  */
+#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
+#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
+#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
+#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
+/* PLL_DIV Macros                                                                                                               */
+#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
+
+/* VR_CTL Masks */
+#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
+#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
+#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
+#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
+#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
+#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
+#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
+#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
+#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
+#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate                     */
+#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
+#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
+#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
+#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
+
+/* PLL_STAT Masks                                                                                                                                       */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+
+#if 0
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+#endif
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+ #define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+
+/* ***************  REAL TIME CLOCK MASKS  **************************/
+/* RTC_STAT and RTC_ALARM Masks                                                                         */
+#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
+#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
+#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
+#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
+
+/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
+#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
+#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
+#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
+#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
+#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
+#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
+#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
+#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
+#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
+#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
+
+/* RTC_FAST / RTC_PREN Mask                                                                                             */
+#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
+
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* UARTx_LCR Masks                                                                                              */
+#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
+#define STB                     0x04                            /* Stop Bits                    */
+#define PEN                     0x08                            /* Parity Enable                */
+#define EPS                     0x10                            /* Even Parity Select   */
+#define STP                     0x20                            /* Stick Parity                 */
+#define SB                      0x40                            /* Set Break                    */
+#define DLAB            0x80                            /* Divisor Latch Access */
+
+/* UARTx_MCR Mask                                                                               */
+#define LOOP_ENA        0x10    /* Loopback Mode Enable */
+#define LOOP_ENA_P      0x04
+
+/* UARTx_LSR Masks                                                                              */
+#define DR                      0x01    /* Data Ready                           */
+#define OE                      0x02    /* Overrun Error                        */
+#define PE                      0x04    /* Parity Error                         */
+#define FE                      0x08    /* Framing Error                        */
+#define BI                      0x10    /* Break Interrupt                      */
+#define THRE            0x20    /* THR Empty                            */
+#define TEMT            0x40    /* TSR and UART_THR Empty       */
+
+/* UARTx_IER Masks                                                                                                                      */
+#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
+#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
+#define ELSI            0x04            /* Enable RX Status Interrupt                           */
+
+/* UARTx_IIR Masks                                                                                                              */
+#define NINT            0x01            /* Pending Interrupt                                    */
+#define IIR_TX_READY    0x02            /* UART_THR empty                               */
+#define IIR_RX_READY    0x04            /* Receive data ready                           */
+#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */
+#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
+
+/* UARTx_GCTL Masks                                                                                                     */
+#define UCEN            0x01            /* Enable UARTx Clocks                          */
+#define IREN            0x02            /* Enable IrDA Mode                                     */
+#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
+#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
+#define FPE                     0x10            /* Force Parity Error On Transmit       */
+#define FFE                     0x20            /* Force Framing Error On Transmit      */
+
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
+/* SPI_CTL Masks                                                                                                                                        */
+#define TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
+#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
+#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
+#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
+#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
+#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
+#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
+#define PSSE            0x0010          /* Slave-Select Input Enable                                            */
+#define EMISO           0x0020          /* Enable MISO As Output                                                        */
+#define SIZE            0x0100          /* Size of Words (16/8* Bits)                                           */
+#define LSBF            0x0200          /* LSB First                                                                            */
+#define CPHA            0x0400          /* Clock Phase                                                                          */
+#define CPOL            0x0800          /* Clock Polarity                                                                       */
+#define MSTR            0x1000          /* Master/Slave*                                                                        */
+#define WOM                     0x2000          /* Write Open Drain Master                                                      */
+#define SPE                     0x4000          /* SPI Enable                                                                           */
+
+/* SPI_FLG Masks                                                                                                                                        */
+#define FLS1            0x0002          /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
+#define FLS2            0x0004          /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
+#define FLS3            0x0008          /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
+#define FLS4            0x0010          /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
+#define FLS5            0x0020          /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
+#define FLS6            0x0040          /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
+#define FLS7            0x0080          /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
+#define FLG1            0xFDFF          /* Activates SPI_FLOUT1                                                         */
+#define FLG2            0xFBFF          /* Activates SPI_FLOUT2                                                         */
+#define FLG3            0xF7FF          /* Activates SPI_FLOUT3                                                         */
+#define FLG4            0xEFFF          /* Activates SPI_FLOUT4                                                         */
+#define FLG5            0xDFFF          /* Activates SPI_FLOUT5                                                         */
+#define FLG6            0xBFFF          /* Activates SPI_FLOUT6                                                         */
+#define FLG7            0x7FFF          /* Activates SPI_FLOUT7                                                         */
+
+/* SPI_STAT Masks                                                                                                                                                               */
+#define SPIF            0x0001          /* SPI Finished (Single-Word Transfer Complete)                                 */
+#define MODF            0x0002          /* Mode Fault Error (Another Device Tried To Become Master)             */
+#define TXE                     0x0004          /* Transmission Error (Data Sent With No New Data In TDBR)              */
+#define TXS                     0x0008          /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
+#define RBSY            0x0010          /* Receive Error (Data Received With RDBR Full)                                 */
+#define RXS                     0x0020          /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
+#define TXCOL           0x0040          /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
+
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+
+/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
+/* Port F Masks                                                                                                                 */
+#define PF0             0x0001
+#define PF1             0x0002
+#define PF2             0x0004
+#define PF3             0x0008
+#define PF4             0x0010
+#define PF5             0x0020
+#define PF6             0x0040
+#define PF7             0x0080
+#define PF8             0x0100
+#define PF9             0x0200
+#define PF10    0x0400
+#define PF11    0x0800
+#define PF12    0x1000
+#define PF13    0x2000
+#define PF14    0x4000
+#define PF15    0x8000
+
+/* Port G Masks                                                                                                                 */
+#define PG0             0x0001
+#define PG1             0x0002
+#define PG2             0x0004
+#define PG3             0x0008
+#define PG4             0x0010
+#define PG5             0x0020
+#define PG6             0x0040
+#define PG7             0x0080
+#define PG8             0x0100
+#define PG9             0x0200
+#define PG10    0x0400
+#define PG11    0x0800
+#define PG12    0x1000
+#define PG13    0x2000
+#define PG14    0x4000
+#define PG15    0x8000
+
+/* Port H Masks                                                                                                                 */
+#define PH0             0x0001
+#define PH1             0x0002
+#define PH2             0x0004
+#define PH3             0x0008
+#define PH4             0x0010
+#define PH5             0x0020
+#define PH6             0x0040
+#define PH7             0x0080
+
+
+/* *******************  SERIAL PORT MASKS  **************************************/
+/* SPORTx_TCR1 Masks                                                                                                                    */
+#define TSPEN           0x0001          /* Transmit Enable                                                              */
+#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
+#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
+#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
+#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
+#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
+#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
+#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
+#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
+#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
+
+/* SPORTx_TCR2 Masks and Macro                                                                                                  */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
+#define TXSE            0x0100          /* TX Secondary Enable                                                  */
+#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
+#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
+
+/* SPORTx_RCR1 Masks                                                                                                                    */
+#define RSPEN           0x0001          /* Receive Enable                                                               */
+#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
+#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
+#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
+#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
+#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
+#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
+#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
+#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
+
+/* SPORTx_RCR2 Masks                                                                                                                    */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
+#define RXSE            0x0100          /* RX Secondary Enable                                                  */
+#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
+#define RRFST           0x0400          /* Right-First Data Order                                               */
+
+/* SPORTx_STAT Masks                                                                                                                    */
+#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
+#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
+#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
+#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
+#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
+#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
+#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
+
+/* SPORTx_MCMC1 Macros                                                                                                                  */
+#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
+#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
+
+/* SPORTx_MCMC2 Masks                                                                                                                   */
+#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
+#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
+#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
+#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
+#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
+#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
+#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
+#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
+#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
+#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
+#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
+#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
+#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
+#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
+#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
+#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
+#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
+#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
+#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
+#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
+#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
+#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
+
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
+#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
+#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
+#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
+#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
+#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
+#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
+#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
+#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
+#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
+#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
+#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
+#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
+#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
+#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
+#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
+#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
+#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
+#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
+#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
+#define NDSIZE                  0x0900  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
+#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
+#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
+#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
+#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
+
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTRL Masks                                                                                                                 */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTRL Masks                                                                                                        */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* Motor Control PWM Registers */
+
+#define                         PWM_CTRL  0xffc03700   /* PWM Control Register */
+#define                         PWM_STAT  0xffc03704   /* PWM Status Register */
+#define                           PWM_TM  0xffc03708   /* PWM Period Register */
+#define                           PWM_DT  0xffc0370c   /* PWM Dead Time Register */
+#define                         PWM_GATE  0xffc03710   /* PWM Chopping Control */
+#define                          PWM_CHA  0xffc03714   /* PWM Channel A Duty Control */
+#define                          PWM_CHB  0xffc03718   /* PWM Channel B Duty Control */
+#define                          PWM_CHC  0xffc0371c   /* PWM Channel C Duty Control */
+#define                          PWM_SEG  0xffc03720   /* PWM Crossover and Output Enable */
+#define                       PWM_SYNCWT  0xffc03724   /* PWM Sync Pluse Width Control */
+#define                         PWM_CHAL  0xffc03728   /* PWM Channel AL Duty Control (SR mode only) */
+#define                         PWM_CHBL  0xffc0372c   /* PWM Channel BL Duty Control (SR mode only) */
+#define                         PWM_CHCL  0xffc03730   /* PWM Channel CL Duty Control (SR mode only) */
+#define                          PWM_LSI  0xffc03734   /* PWM Low Side Invert (SR mode only) */
+#define                        PWM_STAT2  0xffc03738   /* PWM Status Register 2 */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
+#define                  HOST_CNTR_nHOST_EN  0x0
+#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
+#define                 HOST_CNTR_nHOST_END  0x0
+#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
+#define                HOST_CNTR_nDATA_SIZE  0x0
+#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
+#define                 HOST_CNTR_nHOST_RST  0x0
+#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
+#define                 HOST_CNTR_nHRDY_OVR  0x0
+#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
+#define                 HOST_CNTR_nINT_MODE  0x0
+#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
+#define                   HOST_CNTR_ nBT_EN  0x0
+#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
+#define                      HOST_CNTR_nEHW  0x0
+#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
+#define                      HOST_CNTR_nEHR  0x0
+#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
+#define                      HOST_CNTR_nBDR  0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define                     HOST_STAT_READY  0x1        /* DMA Ready */
+#define                    HOST_STAT_nREADY  0x0
+#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
+#define                 HOST_STAT_nFIFOFULL  0x0
+#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
+#define                HOST_STAT_nFIFOEMPTY  0x0
+#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
+#define                 HOST_STAT_nCOMPLETE  0x0
+#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
+#define                     HOST_STAT_nHSHK  0x0
+#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
+#define                  HOST_STAT_nTIMEOUT  0x0
+#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
+#define                     HOST_STAT_nHIRQ  0x0
+#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               HOST_STAT_nALLOW_CNFG  0x0
+#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
+#define                  HOST_STAT_nDMA_DIR  0x0
+#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
+#define                      HOST_STAT_nBTE  0x0
+#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              HOST_STAT_nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for CNT_CONFIG */
+
+#define                      CNTE  0x1        /* Counter Enable */
+#define                     nCNTE  0x0
+#define                      DEBE  0x2        /* Debounce Enable */
+#define                     nDEBE  0x0
+#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
+#define                   nCDGINV  0x0
+#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
+#define                   nCUDINV  0x0
+#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
+#define                   nCZMINV  0x0
+#define                   CNTMODE  0x700      /* Counter Operating Mode */
+#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
+#define                     nZMZC  0x0
+#define                   BNDMODE  0x3000     /* Boundary register Mode */
+#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
+#define                   nINPDIS  0x0
+
+/* Bit masks for CNT_IMASK */
+
+#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
+#define                     nICIE  0x0
+#define                      UCIE  0x2        /* Up count Interrupt Enable */
+#define                     nUCIE  0x0
+#define                      DCIE  0x4        /* Down count Interrupt Enable */
+#define                     nDCIE  0x0
+#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
+#define                   nMINCIE  0x0
+#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
+#define                   nMAXCIE  0x0
+#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
+#define                  nCOV31IE  0x0
+#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
+#define                  nCOV15IE  0x0
+#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
+#define                  nCZEROIE  0x0
+#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
+#define                    nCZMIE  0x0
+#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
+#define                   nCZMEIE  0x0
+#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
+#define                   nCZMZIE  0x0
+
+/* Bit masks for CNT_STATUS */
+
+#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
+#define                     nICII  0x0
+#define                      UCII  0x2        /* Up count Interrupt Identifier */
+#define                     nUCII  0x0
+#define                      DCII  0x4        /* Down count Interrupt Identifier */
+#define                     nDCII  0x0
+#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
+#define                   nMINCII  0x0
+#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
+#define                   nMAXCII  0x0
+#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
+#define                  nCOV31II  0x0
+#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
+#define                  nCOV15II  0x0
+#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
+#define                  nCZEROII  0x0
+#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
+#define                    nCZMII  0x0
+#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
+#define                   nCZMEII  0x0
+#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
+#define                   nCZMZII  0x0
+
+/* Bit masks for CNT_COMMAND */
+
+#define                    W1LCNT  0xf        /* Load Counter Register */
+#define                    W1LMIN  0xf0       /* Load Min Register */
+#define                    W1LMAX  0xf00      /* Load Max Register */
+#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
+#define                 nW1ZMONCE  0x0
+
+/* Bit masks for CNT_DEBOUNCE */
+
+#define                 DPRESCALE  0xf        /* Load Counter Register */
+
+/* CNT_COMMAND bit field options */
+
+#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
+#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
+#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
+
+#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
+#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
+#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
+
+#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
+#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
+#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
+
+/* CNT_CONFIG bit field options */
+
+#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
+#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
+#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
+#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
+#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
+
+#define BNDMODE_COMP     0x0000  /* boundary compare mode */
+#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
+#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
+#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
+
+/* Bit masks for OTP_CONTROL */
+
+#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
+#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
+#define                     nFIEN  0x0
+#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
+#define                 nFTESTDEC  0x0
+#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
+#define                  nFWRTEST  0x0
+#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
+#define                    nFRDEN  0x0
+#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
+#define                    nFWREN  0x0
+
+/* Bit masks for OTP_BEN */
+
+#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
+
+/* Bit masks for OTP_STATUS */
+
+#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
+#define                    nFCOMP  0x0
+#define                    FERROR  0x2        /* OTP/Fuse Access Error */
+#define                   nFERROR  0x0
+#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
+#define                 nMMRGLOAD  0x0
+#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
+#define                 nMMRGLOCK  0x0
+#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
+#define                   nFPGMEN  0x0
+
+/* Bit masks for OTP_TIMING */
+
+#define                   USECDIV  0xff       /* Micro Second Divider */
+#define                   READACC  0x7f00     /* Read Access Time */
+#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
+#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
+#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
+#define                   PGMTIME  0xff000000 /* Program Time */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0
+#define                   SECSTAT  0xe0       /* Secure Status */
+
+
+
+#endif /* _DEF_BF51X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h
new file mode 100644
index 000000000000..bbd33c1706e2
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/dma.h
@@ -0,0 +1,33 @@
+/* mach/dma.h - arch-specific DMA defines
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define MAX_DMA_CHANNELS 16
+
+#define CH_PPI                  0       /* PPI receive/transmit */
+#define CH_EMAC_RX              1       /* Ethernet MAC receive */
+#define CH_EMAC_TX              2       /* Ethernet MAC transmit */
+#define CH_SPORT0_RX            3       /* SPORT0 receive */
+#define CH_SPORT0_TX            4       /* SPORT0 transmit */
+#define CH_RSI                  4       /* RSI */
+#define CH_SPORT1_RX            5       /* SPORT1 receive */
+#define CH_SPI1                 5       /* SPI1 transmit/receive */
+#define CH_SPORT1_TX            6       /* SPORT1 transmit */
+#define CH_SPI0                 7       /* SPI0 transmit/receive */
+#define CH_UART0_RX             8       /* UART0 receive */
+#define CH_UART0_TX             9       /* UART0 transmit */
+#define CH_UART1_RX             10      /* UART1 receive */
+#define CH_UART1_TX             11      /* UART1 transmit */
+
+#define CH_MEM_STREAM0_SRC      12      /* RX */
+#define CH_MEM_STREAM0_DEST     13      /* TX */
+#define CH_MEM_STREAM1_SRC      14      /* RX */
+#define CH_MEM_STREAM1_DEST     15      /* TX */
+
+#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
new file mode 100644
index 000000000000..9757683c3948
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -0,0 +1,60 @@
+/*
+ * File: arch/blackfin/mach-bf518/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 40
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PG0        16
+#define GPIO_PG1        17
+#define GPIO_PG2        18
+#define GPIO_PG3        19
+#define GPIO_PG4        20
+#define GPIO_PG5        21
+#define GPIO_PG6        22
+#define GPIO_PG7        23
+#define GPIO_PG8        24
+#define GPIO_PG9        25
+#define GPIO_PG10       26
+#define GPIO_PG11       27
+#define GPIO_PG12       28
+#define GPIO_PG13       29
+#define GPIO_PG14       30
+#define GPIO_PG15       31
+#define GPIO_PH0        32
+#define GPIO_PH1        33
+#define GPIO_PH2        34
+#define GPIO_PH3        35
+#define GPIO_PH4        36
+#define GPIO_PH5        37
+#define GPIO_PH6        38
+#define GPIO_PH7        39
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
new file mode 100644
index 000000000000..3ff0f093313d
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -0,0 +1,260 @@
+/*
+ * file:        include/asm-blackfin/mach-bf518/irq.h
+ * based on:    include/asm-blackfin/mach-bf527/irq.h
+ * author:      Michael Hennerich (michael.hennerich@analog.com)
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _BF518_IRQ_H_
+#define _BF518_IRQ_H_
+
+/*
+ * Interrupt source definitions
+        Event Source    Core Event Name
+        Core        Emulation               **
+        Events         (highest priority)  EMU         0
+        Reset                   RST         1
+        NMI                     NMI         2
+        Exception               EVX         3
+        Reserved                --          4
+        Hardware Error          IVHW        5
+        Core Timer              IVTMR       6 *
+
+        .....
+
+         Software Interrupt 1    IVG14       31
+         Software Interrupt 2    --
+         (lowest priority)  IVG15       32 *
+*/
+
+#define NR_PERI_INTS    (2 * 32)
+
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU                 0       /* Emulation */
+#define IRQ_RST                 1       /* reset */
+#define IRQ_NMI                 2       /* Non Maskable */
+#define IRQ_EVX                 3       /* Exception */
+#define IRQ_UNUSED              4       /* - unused interrupt */
+#define IRQ_HWERR               5       /* Hardware Error */
+#define IRQ_CORETMR             6       /* Core timer */
+
+#define BFIN_IRQ(x)             ((x) + 7)
+
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
+#define IRQ_DMAR0_BLK           BFIN_IRQ(2)     /* DMAR0 Block Interrupt */
+#define IRQ_DMAR1_BLK           BFIN_IRQ(3)     /* DMAR1 Block Interrupt */
+#define IRQ_DMAR0_OVR           BFIN_IRQ(4)     /* DMAR0 Overflow Error */
+#define IRQ_DMAR1_OVR           BFIN_IRQ(5)     /* DMAR1 Overflow Error */
+#define IRQ_PPI_ERROR           BFIN_IRQ(6)     /* PPI Error */
+#define IRQ_MAC_ERROR           BFIN_IRQ(7)     /* MAC Status */
+#define IRQ_SPORT0_ERROR        BFIN_IRQ(8)     /* SPORT0 Status */
+#define IRQ_SPORT1_ERROR        BFIN_IRQ(9)     /* SPORT1 Status */
+#define IRQ_PTP_ERROR           BFIN_IRQ(10)    /* PTP Error Interrupt */
+#define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
+#define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
+#define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
+#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
+#define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
+#define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
+#define IRQ_RSI                 BFIN_IRQ(17)    /* DMA 4 Channel (RSI) */
+#define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX/SPI) */
+#define IRQ_SPI1                BFIN_IRQ(18)    /* DMA 5 Channel (SPI1) */
+#define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
+#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
+#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
+#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
+#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
+#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
+#define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX) */
+#define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
+#define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(33)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(34)    /* Timer 2 */
+#define IRQ_TIMER3              BFIN_IRQ(35)    /* Timer 3 */
+#define IRQ_TIMER4              BFIN_IRQ(36)    /* Timer 4 */
+#define IRQ_TIMER5              BFIN_IRQ(37)    /* Timer 5 */
+#define IRQ_TIMER6              BFIN_IRQ(38)    /* Timer 6 */
+#define IRQ_TIMER7              BFIN_IRQ(39)    /* Timer 7 */
+#define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
+#define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
+#define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
+#define IRQ_MEM_DMA1            BFIN_IRQ(43)    /* MDMA Stream 1 */
+#define IRQ_WATCH               BFIN_IRQ(44)    /* Software Watchdog Timer */
+#define IRQ_PORTF_INTA          BFIN_IRQ(45)    /* Port F Interrupt A */
+#define IRQ_PORTF_INTB          BFIN_IRQ(46)    /* Port F Interrupt B */
+#define IRQ_SPI0_ERROR          BFIN_IRQ(47)    /* SPI0 Status */
+#define IRQ_SPI1_ERROR          BFIN_IRQ(48)    /* SPI1 Error */
+#define IRQ_RSI_INT0            BFIN_IRQ(51)    /* RSI Interrupt0 */
+#define IRQ_RSI_INT1            BFIN_IRQ(52)    /* RSI Interrupt1 */
+#define IRQ_PWM_TRIP            BFIN_IRQ(53)    /* PWM Trip Interrupt */
+#define IRQ_PWM_SYNC            BFIN_IRQ(54)    /* PWM Sync Interrupt */
+#define IRQ_PTP_STAT            BFIN_IRQ(55)    /* PTP Stat Interrupt */
+
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+
+#define IRQ_PF0         71
+#define IRQ_PF1         72
+#define IRQ_PF2         73
+#define IRQ_PF3         74
+#define IRQ_PF4         75
+#define IRQ_PF5         76
+#define IRQ_PF6         77
+#define IRQ_PF7         78
+#define IRQ_PF8         79
+#define IRQ_PF9         80
+#define IRQ_PF10        81
+#define IRQ_PF11        82
+#define IRQ_PF12        83
+#define IRQ_PF13        84
+#define IRQ_PF14        85
+#define IRQ_PF15        86
+
+#define IRQ_PG0         87
+#define IRQ_PG1         88
+#define IRQ_PG2         89
+#define IRQ_PG3         90
+#define IRQ_PG4         91
+#define IRQ_PG5         92
+#define IRQ_PG6         93
+#define IRQ_PG7         94
+#define IRQ_PG8         95
+#define IRQ_PG9         96
+#define IRQ_PG10        97
+#define IRQ_PG11        98
+#define IRQ_PG12        99
+#define IRQ_PG13        100
+#define IRQ_PG14        101
+#define IRQ_PG15        102
+
+#define IRQ_PH0         103
+#define IRQ_PH1         104
+#define IRQ_PH2         105
+#define IRQ_PH3         106
+#define IRQ_PH4         107
+#define IRQ_PH5         108
+#define IRQ_PH6         109
+#define IRQ_PH7         110
+#define IRQ_PH8         111
+#define IRQ_PH9         112
+#define IRQ_PH10        113
+#define IRQ_PH11        114
+#define IRQ_PH12        115
+#define IRQ_PH13        116
+#define IRQ_PH14        117
+#define IRQ_PH15        118
+
+#define GPIO_IRQ_BASE   IRQ_PF0
+
+#define NR_IRQS     (IRQ_PH15 + 1)
+
+#define IVG7            7
+#define IVG8            8
+#define IVG9            9
+#define IVG10           10
+#define IVG11           11
+#define IVG12           12
+#define IVG13           13
+#define IVG14           14
+#define IVG15           15
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS      0
+#define IRQ_DMA0_ERROR_POS      4
+#define IRQ_DMAR0_BLK_POS       8
+#define IRQ_DMAR1_BLK_POS       12
+#define IRQ_DMAR0_OVR_POS       16
+#define IRQ_DMAR1_OVR_POS       20
+#define IRQ_PPI_ERROR_POS       24
+#define IRQ_MAC_ERROR_POS       28
+
+/* IAR1 BIT FIELDS */
+#define IRQ_SPORT0_ERROR_POS    0
+#define IRQ_SPORT1_ERROR_POS    4
+#define IRQ_PTP_ERROR_POS       8
+#define IRQ_UART0_ERROR_POS     16
+#define IRQ_UART1_ERROR_POS     20
+#define IRQ_RTC_POS             24
+#define IRQ_PPI_POS             28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_SPORT0_RX_POS       0
+#define IRQ_SPORT0_TX_POS       4
+#define IRQ_RSI_POS             4
+#define IRQ_SPORT1_RX_POS       8
+#define IRQ_SPI1_POS            8
+#define IRQ_SPORT1_TX_POS       12
+#define IRQ_TWI_POS             16
+#define IRQ_SPI0_POS            20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_UART1_RX_POS        0
+#define IRQ_UART1_TX_POS        4
+#define IRQ_OPTSEC_POS          8
+#define IRQ_CNT_POS             12
+#define IRQ_MAC_RX_POS          16
+#define IRQ_PORTH_INTA_POS      20
+#define IRQ_MAC_TX_POS          24
+#define IRQ_PORTH_INTB_POS      28
+
+/* IAR4 BIT FIELDS */
+#define IRQ_TIMER0_POS          0
+#define IRQ_TIMER1_POS          4
+#define IRQ_TIMER2_POS          8
+#define IRQ_TIMER3_POS          12
+#define IRQ_TIMER4_POS          16
+#define IRQ_TIMER5_POS          20
+#define IRQ_TIMER6_POS          24
+#define IRQ_TIMER7_POS          28
+
+/* IAR5 BIT FIELDS */
+#define IRQ_PORTG_INTA_POS      0
+#define IRQ_PORTG_INTB_POS      4
+#define IRQ_MEM_DMA0_POS        8
+#define IRQ_MEM_DMA1_POS        12
+#define IRQ_WATCH_POS           16
+#define IRQ_PORTF_INTA_POS      20
+#define IRQ_PORTF_INTB_POS      24
+#define IRQ_SPI0_ERROR_POS      28
+
+/* IAR6 BIT FIELDS */
+#define IRQ_SPI1_ERROR_POS      0
+#define IRQ_RSI_INT0_POS        12
+#define IRQ_RSI_INT1_POS        16
+#define IRQ_PWM_TRIP_POS        20
+#define IRQ_PWM_SYNC_POS        24
+#define IRQ_PTP_STAT_POS        28
+
+#endif                          /* _BF518_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
new file mode 100644
index 000000000000..62bcc781bfaa
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h
@@ -0,0 +1,108 @@
+/*
+ * file:         include/asm-blackfin/mach-bf518/mem_map.h
+ * based on:    include/asm-blackfin/mach-bf527/mem_map.h
+ * author:      Bryan Wu <cooloney@kernel.org>
+ *
+ * created:
+ * description:
+ *      Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
+ * rev:
+ *
+ * modified:
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _MEM_MAP_518_H_
+#define _MEM_MAP_518_H_
+
+#define COREMMR_BASE           0xFFE00000       /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000       /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x20300000      /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK2_BASE        0x20200000      /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK1_BASE        0x20100000      /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK0_BASE        0x20000000      /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
+
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x8000
+
+/* Level 1 Memory */
+
+/* Memory Map for ADSP-BF518/6/4/2 processors */
+
+#ifdef CONFIG_BFIN_ICACHE
+#define BFIN_ICACHESIZE         (16 * 1024)
+#else
+#define BFIN_ICACHESIZE         (0)
+#endif
+
+#define L1_CODE_START           0xFFA00000
+#define L1_DATA_A_START         0xFF800000
+#define L1_DATA_B_START         0xFF900000
+
+#define L1_CODE_LENGTH          0xC000
+
+#ifdef CONFIG_BFIN_DCACHE
+
+#ifdef CONFIG_BFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH        (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH        0x8000
+#define BFIN_DCACHESIZE         (16 * 1024)
+#define BFIN_DSUPBANKS          1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH        (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH        (0x8000 - 0x4000)
+#define BFIN_DCACHESIZE         (32 * 1024)
+#define BFIN_DSUPBANKS          2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH        0x8000
+#define L1_DATA_B_LENGTH        0x8000
+#define BFIN_DCACHESIZE         0
+#define BFIN_DSUPBANKS          0
+#endif                          /*CONFIG_BFIN_DCACHE */
+
+/* Level 2 Memory - none */
+
+#define L2_START        0
+#define L2_LENGTH       0
+
+/* Scratch Pad Memory */
+
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
+#endif                          /* _MEM_MAP_518_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
new file mode 100644
index 000000000000..ac16d54734d4
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -0,0 +1,188 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
+
+/* EMAC MII/RMII Port Mux */
+#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
+#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
+#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
+#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
+#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
+#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
+#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
+
+#define P_MII0_MDC      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_MII0_MDIO     (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
+#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
+#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
+#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
+#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
+#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
+#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+
+#define P_MII0 {\
+        P_MII0_ETxD0, \
+        P_MII0_ETxD1, \
+        P_MII0_ETxD2, \
+        P_MII0_ETxD3, \
+        P_MII0_ETxEN, \
+        P_MII0_TxCLK, \
+        P_MII0_PHYINT, \
+        P_MII0_COL, \
+        P_MII0_ERxD0, \
+        P_MII0_ERxD1, \
+        P_MII0_ERxD2, \
+        P_MII0_ERxD3, \
+        P_MII0_ERxDV, \
+        P_MII0_ERxCLK, \
+        P_MII0_ERxER, \
+        P_MII0_CRS, \
+        P_MII0_MDC, \
+        P_MII0_MDIO, 0}
+
+#define P_RMII0 {\
+        P_MII0_ETxD0, \
+        P_MII0_ETxD1, \
+        P_MII0_ETxEN, \
+        P_MII0_ERxD0, \
+        P_MII0_ERxD1, \
+        P_MII0_ERxER, \
+        P_MII0_TxCLK, \
+        P_MII0_PHYINT, \
+        P_MII0_CRS, \
+        P_MII0_MDC, \
+        P_MII0_MDIO, 0}
+
+/* PPI Port Mux */
+#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+
+#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
+#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
+#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
+#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
+
+#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
+#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
+#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_SPI1_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
+#define P_SPI1_SSEL5    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
+
+/* SPORT Port Mux */
+#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+
+#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
+#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
+#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
+#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
+#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
+#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
+#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
+#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
+
+/* UART Port Mux */
+#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+
+#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
+#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
+
+/* Timer */
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
+#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
+#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
+#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
+#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
+#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
+
+/* DMA */
+#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
+
+/* TWI */
+#define P_TWI0_SCL      (P_DONTCARE)
+#define P_TWI0_SDA      (P_DONTCARE)
+
+/* PWM */
+#define P_PWM0_AH               (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_PWM0_AL               (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_PWM0_BH               (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_PWM0_BL               (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_PWM0_CH               (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_PWM0_CL               (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_PWM0_SYNC             (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+
+#define P_PWM1_AH               (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_PWM1_AL               (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_PWM1_BH               (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_PWM1_BL               (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_PWM1_CH               (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_PWM1_CL               (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_PWM1_SYNC             (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+
+#define P_PWM_TRIPB             (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
+
+/* RSI */
+#define P_RSI_DATA0             (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
+#define P_RSI_DATA1             (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_RSI_DATA2             (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_DATA3             (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+#define P_RSI_DATA4             (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
+#define P_RSI_DATA5             (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
+#define P_RSI_DATA6             (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
+#define P_RSI_DATA7             (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
+#define P_RSI_CMD               (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_RSI_CLK               (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+
+/* PTP */
+#define P_PTP_PPS               (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
+#define P_PTP_CLKOUT            (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
+
+#define P_HWAIT         (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
+
+#endif                          /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
new file mode 100644
index 000000000000..3151fd5501ca
--- /dev/null
+++ b/arch/blackfin/mach-bf518/ints-priority.c
@@ -0,0 +1,99 @@
+/*
+ * File:         arch/blackfin/mach-bf518/ints-priority.c
+ * Based on:     arch/blackfin/mach-bf527/ints-priority.c
+ * Author:       Bryan Wu <cooloney@kernel.org>
+ *
+ * Created:
+ * Description:  Set up the interrupt priorities
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+void __init program_IAR(void)
+{
+        /* Program the IAR0 Register with the configured priority */
+        bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
+                        ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
+                        ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
+                        ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
+                        ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
+                        ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
+                        ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
+                        ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
+
+
+        bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
+                        ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
+                        ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
+                        ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
+                        ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
+                        ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
+
+        bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
+                        ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
+                        ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
+                        ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
+                        ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
+                        ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
+                        ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
+                        ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
+
+        bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
+                        ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
+                        ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
+                        ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
+                        ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
+                        ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
+                        ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
+                        ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
+
+        bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                        ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
+                        ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                        ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+                        ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
+                        ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+                        ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+                        ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
+
+        bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
+                        ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
+                        ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
+                        ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
+                        ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
+                        ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
+                        ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
+                        ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
+
+        bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
+                        ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
+                        ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
+                        ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
+                        ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
+                        ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
+
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 3cde4beeb214..8438ec6d6679 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -168,29 +168,29 @@ config IRQ_MAC_TX
 config IRQ_PORTH_INTB
         int "IRQ_PORTH_INTB"
         default 11
-config IRQ_TMR0
-        int "IRQ_TMR0"
-        default 12
-config IRQ_TMR1
-        int "IRQ_TMR1"
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 8
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
         default 12
-config IRQ_TMR2
-        int "IRQ_TMR2"
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
         default 12
-config IRQ_TMR3
-        int "IRQ_TMR3"
+config IRQ_TIMER3
+        int "IRQ_TIMER3"
         default 12
-config IRQ_TMR4
-        int "IRQ_TMR4"
+config IRQ_TIMER4
+        int "IRQ_TIMER4"
         default 12
-config IRQ_TMR5
-        int "IRQ_TMR5"
+config IRQ_TIMER5
+        int "IRQ_TIMER5"
         default 12
-config IRQ_TMR6
-        int "IRQ_TMR6"
+config IRQ_TIMER6
+        int "IRQ_TIMER6"
         default 12
-config IRQ_TMR7
-        int "IRQ_TMR7"
+config IRQ_TIMER7
+        int "IRQ_TIMER7"
         default 12
 config IRQ_PORTG_INTA
         int "IRQ_PORTG_INTA"
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
index 4eddb580319c..4a6cdafab8ce 100644
--- a/arch/blackfin/mach-bf527/Makefile
+++ b/arch/blackfin/mach-bf527/Makefile
@@ -2,6 +2,4 @@
 # arch/blackfin/mach-bf527/Makefile
 #
 
-extra-y := head.o
-
 obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 9ea440bbb13d..a2c3578f4b6c 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -61,51 +61,40 @@ const char bfin_board_name[] = "Bluetechnix CM-BF527";
  *  Driver needs to know address, irq and flag pin.
  */
 
-#define ISP1761_BASE       0x203C0000
-#define ISP1761_IRQ        IRQ_PF7
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
         [0] = {
-                .name   = "isp1761-regs",
-                .start  = ISP1761_BASE + 0x00000000,
-                .end    = ISP1761_BASE + 0x000fffff,
+                .start  = 0x203C0000,
+                .end    = 0x203C0000 + 0x000fffff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = ISP1761_IRQ,
-                .end    = ISP1761_IRQ,
+                .start  = IRQ_PF7,
+                .end    = IRQ_PF7,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
@@ -132,8 +121,8 @@ static struct musb_hdrc_config musb_config = {
         .dyn_fifo       = 0,
         .soft_con       = 1,
         .dma            = 1,
-        .num_eps        = 7,
-        .dma_channels   = 7,
+        .num_eps        = 8,
+        .dma_channels   = 8,
         .gpio_vrsel     = GPIO_PF11,
 };
 
@@ -728,30 +717,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -885,6 +903,10 @@ static struct platform_device *stamp_devices[] __initdata = {
         &isp1362_hcd_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
         &musb_device,
 #endif
@@ -918,7 +940,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 36c87b6fbdec..0314bd3355eb 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -51,7 +51,7 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "BF526-EZBRD";
+const char bfin_board_name[] = "ADI BF526-EZBRD";
 
 /*
  *  Driver needs to know address, irq and flag pin.
@@ -81,8 +81,8 @@ static struct musb_hdrc_config musb_config = {
         .dyn_fifo       = 0,
         .soft_con       = 1,
         .dma            = 1,
-        .num_eps        = 7,
-        .dma_channels   = 7,
+        .num_eps        = 8,
+        .dma_channels   = 8,
         .gpio_vrsel     = GPIO_PG13,
 };
 
@@ -288,6 +288,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
+#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#include <linux/spi/ad7879.h>
+static const struct ad7879_platform_data bfin_ad7879_ts_info = {
+        .model                  = 7879, /* Model = AD7879 */
+        .x_plate_ohms           = 620,  /* 620 Ohm from the touch datasheet */
+        .pressure_max           = 10000,
+        .pressure_min           = 0,
+        .first_conversion_delay = 3,    /* wait 512us before do a first conversion */
+        .acquisition_time       = 1,    /* 4us acquisition time per sample */
+        .median                 = 2,    /* do 8 measurements */
+        .averaging              = 1,    /* take the average of 4 middle samples */
+        .pen_down_acc_interval  = 255,  /* 9.4 ms */
+        .gpio_output            = 1,    /* configure AUX/VBAT/GPIO as GPIO output */
+        .gpio_default           = 1,    /* During initialization set GPIO = HIGH */
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+#endif
+
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
          && defined(CONFIG_SND_SOC_WM8731_SPI)
 static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
@@ -386,6 +410,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .controller_data = &spi_ad7877_chip_info,
         },
 #endif
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+        {
+                .modalias = "ad7879",
+                .platform_data = &bfin_ad7879_ts_info,
+                .irq = IRQ_PG0,
+                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 5,
+                .controller_data = &spi_ad7879_chip_info,
+                .mode = SPI_CPHA | SPI_CPOL,
+        },
+#endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
          && defined(CONFIG_SND_SOC_WM8731_SPI)
         {
@@ -478,30 +514,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -671,7 +736,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 8ee2b744e234..9454fb7b18c3 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -54,57 +54,46 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADDS-BF527-EZKIT";
+const char bfin_board_name[] = "ADI BF527-EZKIT";
 
 /*
  *  Driver needs to know address, irq and flag pin.
  */
 
-#define ISP1761_BASE       0x203C0000
-#define ISP1761_IRQ        IRQ_PF7
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
         [0] = {
-                .name   = "isp1761-regs",
-                .start  = ISP1761_BASE + 0x00000000,
-                .end    = ISP1761_BASE + 0x000fffff,
+                .start  = 0x203C0000,
+                .end    = 0x203C0000 + 0x000fffff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = ISP1761_IRQ,
-                .end    = ISP1761_IRQ,
+                .start  = IRQ_PF7,
+                .end    = IRQ_PF7,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
@@ -131,8 +120,8 @@ static struct musb_hdrc_config musb_config = {
         .dyn_fifo       = 0,
         .soft_con       = 1,
         .dma            = 1,
-        .num_eps        = 7,
-        .dma_channels   = 7,
+        .num_eps        = 8,
+        .dma_channels   = 8,
         .gpio_vrsel     = GPIO_PG13,
 };
 
@@ -515,13 +504,6 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
-static struct bfin5xx_spi_chip spi_mmc_chip_info = {
-        .enable_dma = 1,
-        .bits_per_word = 8,
-};
-#endif
-
 #if defined(CONFIG_PBX)
 static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
         .ctl_reg        = 0x4, /* send zero */
@@ -552,6 +534,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
+#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#include <linux/spi/ad7879.h>
+static const struct ad7879_platform_data bfin_ad7879_ts_info = {
+        .model                  = 7879, /* Model = AD7879 */
+        .x_plate_ohms           = 620,  /* 620 Ohm from the touch datasheet */
+        .pressure_max           = 10000,
+        .pressure_min           = 0,
+        .first_conversion_delay = 3,    /* wait 512us before do a first conversion */
+        .acquisition_time       = 1,    /* 4us acquisition time per sample */
+        .median                 = 2,    /* do 8 measurements */
+        .averaging              = 1,    /* take the average of 4 middle samples */
+        .pen_down_acc_interval  = 255,  /* 9.4 ms */
+        .gpio_output            = 1,    /* configure AUX/VBAT/GPIO as GPIO output */
+        .gpio_default           = 1,    /* During initialization set GPIO = HIGH */
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+#endif
+
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
          && defined(CONFIG_SND_SOC_WM8731_SPI)
 static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
@@ -613,26 +619,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .controller_data = &ad9960_spi_chip_info,
         },
 #endif
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
-        {
-                .modalias = "spi_mmc_dummy",
-                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
-                .mode = SPI_MODE_3,
-        },
-        {
-                .modalias = "spi_mmc",
-                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,
-                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
-                .mode = SPI_MODE_3,
-        },
-#endif
 #if defined(CONFIG_PBX)
         {
                 .modalias = "fxs-spi",
@@ -662,6 +648,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .controller_data = &spi_ad7877_chip_info,
         },
 #endif
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+        {
+                .modalias = "ad7879",
+                .platform_data = &bfin_ad7879_ts_info,
+                .irq = IRQ_PF8,
+                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 3,
+                .controller_data = &spi_ad7879_chip_info,
+                .mode = SPI_CPHA | SPI_CPOL,
+        },
+#endif
 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
          && defined(CONFIG_SND_SOC_WM8731_SPI)
         {
@@ -756,30 +754,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -944,6 +971,10 @@ static struct platform_device *stamp_devices[] __initdata = {
         &isp1362_hcd_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
         &musb_device,
 #endif
@@ -985,7 +1016,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
index dfd080cda787..231877578243 100644
--- a/arch/blackfin/mach-bf527/dma.c
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -31,7 +31,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
deleted file mode 100644
index 0eb1da85db73..000000000000
--- a/arch/blackfin/mach-bf527/head.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf527/head.S
- * Based on:     arch/blackfin/mach-bf533/head.S
- * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
- *
- * Created:      1998
- * Description:  Startup code for Blackfin BF537
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#include <asm/clocks.h>
-#include <mach/mem_init.h>
-#endif
-
-.section .l1.text
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-ENTRY(_start_dma_code)
-
-        /* Enable PHY CLK buffer output */
-        p0.h = hi(VR_CTL);
-        p0.l = lo(VR_CTL);
-        r0.l = w[p0];
-        bitset(r0, 14);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.h = hi(SIC_IWR0);
-        p0.l = lo(SIC_IWR0);
-        r0.l = 0x1;
-        r0.h = 0x0;
-        [p0] = r0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        p0.h = hi(PLL_LOCKCNT);
-        p0.l = lo(PLL_LOCKCNT);
-        r0 = 0x300(Z);
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-#ifdef ANOMALY_05000265
-        BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
-#endif
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-
-.Lcheck_again:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again;
-
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
-        p0.h = hi(EBIU_SDSTAT);
-        p0.l = lo(EBIU_SDSTAT);
-        r2.l = w[p0];
-        cc = bittst(r2,3);
-        if !cc jump .Lskip;
-        NOP;
-        BITSET (R0, 23);
-.Lskip:
-        [P2] = R0;
-        SSYNC;
-
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
-        R1 = [p2];
-        R1 = R1 | R0;
-        [P2] = R1;
-        SSYNC;
-
-        RTS;
-ENDPROC(_start_dma_code)
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 62373e61c585..035e8d835058 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -28,7 +28,7 @@
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
+#define ANOMALY_05000119 (1)    /* note: brokenness is noted in documentation, not anomaly sheet */
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@@ -37,8 +37,6 @@
 #define ANOMALY_05000265 (1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (ANOMALY_BF527)
 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
 #define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
@@ -153,6 +151,10 @@
 #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
 #define ANOMALY_05000432 (ANOMALY_BF526)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -168,7 +170,9 @@
 #define ANOMALY_05000285 (0)
 #define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
index 144f08d3f8ea..3832aab11e9a 100644
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ b/arch/blackfin/mach-bf527/include/mach/bf527.h
@@ -110,7 +110,7 @@
 
 #ifdef CONFIG_BF527
 #define CPU "BF527"
-#define CPUID 0x27e4
+#define CPUID 0x27e0
 #endif
 #ifdef CONFIG_BF526
 #define CPU "BF526"
@@ -118,7 +118,7 @@
 #endif
 #ifdef CONFIG_BF525
 #define CPU "BF525"
-#define CPUID 0x27e4
+#define CPUID 0x27e0
 #endif
 #ifdef CONFIG_BF524
 #define CPU "BF524"
@@ -126,7 +126,7 @@
 #endif
 #ifdef CONFIG_BF523
 #define CPU "BF523"
-#define CPUID 0x27e4
+#define CPUID 0x27e0
 #endif
 #ifdef CONFIG_BF522
 #define CPU "BF522"
@@ -134,7 +134,7 @@
 #endif
 
 #ifndef CPU
-#error Unknown CPU type - This kernel doesn't seem to be configured properly
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 #endif
 
 #endif                          /* __MACH_BF527_H__  */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 9a814b9a12b9..1fe76d8e0403 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -31,7 +31,6 @@
 #ifndef _CDEF_BF52X_H
 #define _CDEF_BF52X_H
 
-#include <asm/system.h>
 #include <asm/blackfin.h>
 
 #include "defBF52x_base.h"
@@ -43,57 +42,9 @@
 
 /* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
 #define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
 #define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
 #define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
@@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
 #endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
index 49dd693223e8..eb287da101a2 100644
--- a/arch/blackfin/mach-bf527/include/mach/dma.h
+++ b/arch/blackfin/mach-bf527/include/mach/dma.h
@@ -1,38 +1,14 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/dma.h
- * based on:    include/asm-blackfin/mach-bf537/dma.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
+/* mach/dma.h - arch-specific DMA defines
  *
- * created:
- * description:
- *      system DMA map
- * rev:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_DMA_H_
 #define _MACH_DMA_H_
 
-#define MAX_BLACKFIN_DMA_CHANNEL 16
+#define MAX_DMA_CHANNELS 16
 
 #define CH_PPI                  0       /* PPI receive/transmit or NFC */
 #define CH_EMAC_RX              1       /* Ethernet MAC receive or HOSTDP */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
new file mode 100644
index 000000000000..06b6eebf0d49
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -0,0 +1,68 @@
+/*
+ * File: arch/blackfin/mach-bf527/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PG0        16
+#define GPIO_PG1        17
+#define GPIO_PG2        18
+#define GPIO_PG3        19
+#define GPIO_PG4        20
+#define GPIO_PG5        21
+#define GPIO_PG6        22
+#define GPIO_PG7        23
+#define GPIO_PG8        24
+#define GPIO_PG9        25
+#define GPIO_PG10       26
+#define GPIO_PG11       27
+#define GPIO_PG12       28
+#define GPIO_PG13       29
+#define GPIO_PG14       30
+#define GPIO_PG15       31
+#define GPIO_PH0        32
+#define GPIO_PH1        33
+#define GPIO_PH2        34
+#define GPIO_PH3        35
+#define GPIO_PH4        36
+#define GPIO_PH5        37
+#define GPIO_PH6        38
+#define GPIO_PH7        39
+#define GPIO_PH8        40
+#define GPIO_PH9        41
+#define GPIO_PH10       42
+#define GPIO_PH11       43
+#define GPIO_PH12       44
+#define GPIO_PH13       45
+#define GPIO_PH14       46
+#define GPIO_PH15       47
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 4e2b3f2020e5..8ea660d8151f 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -96,14 +96,14 @@
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
 #define IRQ_NFC                 BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
-#define IRQ_TMR0                BFIN_IRQ(32)    /* Timer 0 */
-#define IRQ_TMR1                BFIN_IRQ(33)    /* Timer 1 */
-#define IRQ_TMR2                BFIN_IRQ(34)    /* Timer 2 */
-#define IRQ_TMR3                BFIN_IRQ(35)    /* Timer 3 */
-#define IRQ_TMR4                BFIN_IRQ(36)    /* Timer 4 */
-#define IRQ_TMR5                BFIN_IRQ(37)    /* Timer 5 */
-#define IRQ_TMR6                BFIN_IRQ(38)    /* Timer 6 */
-#define IRQ_TMR7                BFIN_IRQ(39)    /* Timer 7 */
+#define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(33)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(34)    /* Timer 2 */
+#define IRQ_TIMER3              BFIN_IRQ(35)    /* Timer 3 */
+#define IRQ_TIMER4              BFIN_IRQ(36)    /* Timer 4 */
+#define IRQ_TIMER5              BFIN_IRQ(37)    /* Timer 5 */
+#define IRQ_TIMER6              BFIN_IRQ(38)    /* Timer 6 */
+#define IRQ_TIMER7              BFIN_IRQ(39)    /* Timer 7 */
 #define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
 #define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
 #define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
@@ -227,14 +227,14 @@
 #define IRQ_PORTH_INTB_POS      28
 
 /* IAR4 BIT FIELDS */
-#define IRQ_TMR0_POS            0
-#define IRQ_TMR1_POS            4
-#define IRQ_TMR2_POS            8
-#define IRQ_TMR3_POS            12
-#define IRQ_TMR4_POS            16
-#define IRQ_TMR5_POS            20
-#define IRQ_TMR6_POS            24
-#define IRQ_TMR7_POS            28
+#define IRQ_TIMER0_POS          0
+#define IRQ_TIMER1_POS          4
+#define IRQ_TIMER2_POS          8
+#define IRQ_TIMER3_POS          12
+#define IRQ_TIMER4_POS          16
+#define IRQ_TIMER5_POS          20
+#define IRQ_TIMER6_POS          24
+#define IRQ_TIMER7_POS          28
 
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
index ef46dc991cd4..019e0017ad81 100644
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h
@@ -99,4 +99,10 @@
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
 
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
 #endif                          /* _MEM_MAP_527_H_ */
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
index 8a2367403d2b..f8c8acd73e30 100644
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ b/arch/blackfin/mach-bf527/ints-priority.c
@@ -69,14 +69,14 @@ void __init program_IAR(void)
                         ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
                         ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
 
-        bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
-                        ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
-                        ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
-                        ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
-                        ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
-                        ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
-                        ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
-                        ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
+        bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                        ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
+                        ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                        ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+                        ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
+                        ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+                        ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+                        ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
 
         bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
                         ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
index 76beb75f12da..14427de7d77f 100644
--- a/arch/blackfin/mach-bf533/Kconfig
+++ b/arch/blackfin/mach-bf533/Kconfig
@@ -59,7 +59,7 @@ config DMA7_UARTTX
         default 10
 config TIMER0
         int "TIMER0"
-        default 11
+        default 8
 config TIMER1
         int "TIMER1"
         default 11
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
index aa9f2647ee0c..874840f76028 100644
--- a/arch/blackfin/mach-bf533/Makefile
+++ b/arch/blackfin/mach-bf533/Makefile
@@ -2,6 +2,4 @@
 # arch/blackfin/mach-bf533/Makefile
 #
 
-extra-y := head.o
-
 obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 72ac3ac8ef76..0c66bf44cfab 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -313,23 +313,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 
@@ -431,7 +441,9 @@ static struct platform_device *h8606_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index d064ded87719..6ee607c259ac 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -212,23 +212,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 static struct platform_device bfin_sport0_uart_device = {
@@ -353,7 +363,9 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 575843f6d9ef..e7061c7e8c42 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -219,6 +219,19 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 static struct resource bfin_uart_resources[] = {
         {
@@ -237,23 +250,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 static struct platform_device bfin_sport0_uart_device = {
@@ -342,7 +365,9 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -365,6 +390,8 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
         &bfin_spi0_device,
 #endif
+
+        &bfin_gpios_device,
 };
 
 static int __init cm_bf533_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index cc2e7eeb1d5a..08cd0969de47 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -46,7 +46,7 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADDS-BF533-EZKIT";
+const char bfin_board_name[] = "ADI BF533-EZKIT";
 
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 static struct platform_device rtc_device = {
@@ -236,23 +236,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/input.h>
@@ -363,7 +373,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
index 82b1f6a60e3f..986eeec53b1f 100644
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ b/arch/blackfin/mach-bf533/boards/generic_board.c
@@ -72,6 +72,35 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#endif
+
 static struct platform_device *generic_board_devices[] __initdata = {
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
         &rtc_device,
@@ -80,6 +109,12 @@ static struct platform_device *generic_board_devices[] __initdata = {
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
         &smc91x_device,
 #endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#endif
 };
 
 static int __init generic_board_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 5864892de314..e30b1b7d1442 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -197,23 +197,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 static struct resource isp1362_hcd_resources[] = {
@@ -272,7 +282,9 @@ static struct platform_device *ip0x_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 050ffca53530..07f9ad1e189c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -49,7 +49,7 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADDS-BF533-STAMP";
+const char bfin_board_name[] = "ADI BF533-STAMP";
 
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 static struct platform_device rtc_device = {
@@ -118,7 +118,7 @@ static struct mtd_partition stamp_partitions[] = {
                 .offset = 0,
         }, {
                 .name   = "linux kernel(nor)",
-                .size   = 0xE0000,
+                .size   = 0x180000,
                 .offset = MTDPART_OFS_APPEND,
         }, {
                 .name   = "file system(nor)",
@@ -169,7 +169,7 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .mask_flags = MTD_CAP_ROM
         }, {
                 .name = "linux kernel(spi)",
-                .size = 0xe0000,
+                .size = 0x180000,
                 .offset = MTDPART_OFS_APPEND,
         }, {
                 .name = "file system(spi)",
@@ -216,13 +216,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
-static struct bfin5xx_spi_chip spi_mmc_chip_info = {
-        .enable_dma = 1,
-        .bits_per_word = 8,
-};
-#endif
-
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 static struct bfin5xx_spi_chip spidev_chip_info = {
         .enable_dma = 0,
@@ -265,27 +258,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
-        {
-                .modalias = "spi_mmc_dummy",
-                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
-                .mode = SPI_MODE_3,
-        },
-        {
-                .modalias = "spi_mmc",
-                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,
-                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
-                .mode = SPI_MODE_3,
-        },
-#endif
-
 #if defined(CONFIG_PBX)
         {
                 .modalias = "fxs-spi",
@@ -373,23 +345,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 static struct platform_device bfin_sport0_uart_device = {
@@ -537,7 +519,9 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
index 28655c1cb7dc..0a6eb8f24d98 100644
--- a/arch/blackfin/mach-bf533/dma.c
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -31,7 +31,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
deleted file mode 100644
index 9fc95aaca439..000000000000
--- a/arch/blackfin/mach-bf533/head.S
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf533/head.S
- * Based on:
- * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
- *
- * Created:      1998
- * Description:  bf533 startup file
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#include <asm/clocks.h>
-#include <mach/mem_init.h>
-#endif
-
-.section .l1.text
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-ENTRY(_start_dma_code)
-        p0.h = hi(SIC_IWR);
-        p0.l = lo(SIC_IWR);
-        r0.l = 0x1;
-        r0.h = 0x0;
-        [p0] = r0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        p0.h = hi(PLL_LOCKCNT);
-        p0.l = lo(PLL_LOCKCNT);
-        r0 = 0x300(Z);
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-#ifdef ANOMALY_05000265
-        BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
-#endif
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-
-.Lcheck_again:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again;
-
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
-        p0.h = hi(EBIU_SDSTAT);
-        p0.l = lo(EBIU_SDSTAT);
-        r2.l = w[p0];
-        cc = bittst(r2,3);
-        if !cc jump .Lskip;
-        NOP;
-        BITSET (R0, 23);
-.Lskip:
-        [P2] = R0;
-        SSYNC;
-
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
-        R1 = [p2];
-        R1 = R1 | R0;
-        [P2] = R1;
-        SSYNC;
-
-        RTS;
-ENDPROC(_start_dma_code)
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index f544fc56959a..0d3a03429fb9 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -194,6 +194,12 @@
 #define ANOMALY_05000403 (1)
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* These anomalies have been "phased" out of analog.com anomaly sheets and are
  * here to show running on older silicon just isn't feasible.
@@ -273,5 +279,8 @@
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
index dfc8c1ad2d7a..cf4427cd3f72 100644
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ b/arch/blackfin/mach-bf533/include/mach/bf533.h
@@ -145,7 +145,7 @@
 #endif
 #ifdef CONFIG_BF532
 #define CPU "BF532"
-#define CPUID 0x275A
+#define CPUID 0x27a5
 #endif
 #ifdef CONFIG_BF531
 #define CPU "BF531"
@@ -153,7 +153,7 @@
 #endif
 
 #ifndef CPU
-#error Unknown CPU type - This kernel doesn't seem to be configured properly
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 #endif
 
 #endif                          /* __MACH_BF533_H__  */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index d80971b4e3aa..045184f81a29 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -44,6 +44,13 @@
 
 #define BFIN_UART_NR_PORTS      1
 
+#define CH_UART_RX CH_UART0_RX
+#define CH_UART_TX CH_UART0_TX
+
+#define IRQ_UART_ERROR IRQ_UART0_ERROR
+#define IRQ_UART_RX    IRQ_UART0_RX
+#define IRQ_UART_TX    IRQ_UART0_TX
+
 #define OFFSET_THR              0x00    /* Transmit Holding register            */
 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 3d8978a52c17..bbc3c8386d48 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -39,31 +39,8 @@
 /*include core specific register pointer definitions*/
 #include <asm/cdef_LPBlackfin.h>
 
-#include <asm/system.h>
-
 /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -72,27 +49,6 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
 
 /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
 #define bfin_read_SWRST()                    bfin_read16(SWRST)
@@ -178,50 +134,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
 
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
-{\
-        unsigned long flags;\
-        local_irq_save(flags);\
-        bfin_write16(FIO_FLAG_ ## name,val);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
-{\
-        unsigned long flags;\
-        unsigned short ret;\
-        local_irq_save(flags);\
-        ret = bfin_read16(FIO_FLAG_ ## name);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-        return ret;\
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#endif
-
-
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
@@ -764,4 +676,93 @@ BFIN_READ_FIO_FLAG(T)
 #define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+#if ANOMALY_05000311
+#define BFIN_WRITE_FIO_FLAG(name) \
+static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
+{ \
+        unsigned long flags; \
+        local_irq_save_hw(flags); \
+        bfin_write16(FIO_FLAG_##name, val); \
+        bfin_read_CHIPID(); \
+        local_irq_restore_hw(flags); \
+}
+BFIN_WRITE_FIO_FLAG(D)
+BFIN_WRITE_FIO_FLAG(C)
+BFIN_WRITE_FIO_FLAG(S)
+BFIN_WRITE_FIO_FLAG(T)
+
+#define BFIN_READ_FIO_FLAG(name) \
+static inline u16 bfin_read_FIO_FLAG_##name(void) \
+{ \
+        unsigned long flags; \
+        u16 ret; \
+        local_irq_save_hw(flags); \
+        ret = bfin_read16(FIO_FLAG_##name); \
+        bfin_read_CHIPID(); \
+        local_irq_restore_hw(flags); \
+        return ret; \
+}
+BFIN_READ_FIO_FLAG(D)
+BFIN_READ_FIO_FLAG(C)
+BFIN_READ_FIO_FLAG(S)
+BFIN_READ_FIO_FLAG(T)
+
+#else
+#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
+#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
+#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
+#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
+#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
+#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
+#endif
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        local_irq_restore_hw(flags);
+}
+
 #endif                          /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
index bd9d5e94307d..fb34934c5ba8 100644
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ b/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -1,42 +1,14 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
-/*
- * File:         include/asm-blackfin/mach-bf533/dma.h
- * Based on:
- * Author:
+/* mach/dma.h - arch-specific DMA defines
  *
- * Created:
- * Description:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_DMA_H_
 #define _MACH_DMA_H_
 
-#define MAX_BLACKFIN_DMA_CHANNEL 12
+#define MAX_DMA_CHANNELS 12
 
 #define CH_PPI          0
 #define CH_SPORT0_RX    1
@@ -44,8 +16,8 @@
 #define CH_SPORT1_RX    3
 #define CH_SPORT1_TX    4
 #define CH_SPI          5
-#define CH_UART_RX      6
-#define CH_UART_TX      7
+#define CH_UART0_RX     6
+#define CH_UART0_TX     7
 #define CH_MEM_STREAM0_DEST     8        /* TX */
 #define CH_MEM_STREAM0_SRC      9        /* RX */
 #define CH_MEM_STREAM1_DEST     10       /* TX */
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
new file mode 100644
index 000000000000..e45c17077aff
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * File: arch/blackfin/mach-bf533/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 16
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+
+#define PORT_F GPIO_PF0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 5aa38e5da6b7..db1e346cd1aa 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -90,19 +90,19 @@ Core        Emulation               **
 #define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
 #define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
 #define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
-#define IRQ_UART_ERROR          13      /*UART Error Interrupt */
+#define IRQ_UART0_ERROR         13      /*UART Error Interrupt */
 #define IRQ_RTC                 14      /*RTC Interrupt */
 #define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
 #define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
 #define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
 #define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
 #define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
-#define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
-#define IRQ_TMR0                23      /*Timer 0 */
-#define IRQ_TMR1                24      /*Timer 1 */
-#define IRQ_TMR2                25      /*Timer 2 */
+#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define IRQ_UART0_RX            21      /*DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_TX            22      /*DMA7 Interrupt (UART TX) */
+#define IRQ_TIMER0              23      /*Timer 0 */
+#define IRQ_TIMER1              24      /*Timer 1 */
+#define IRQ_TIMER2              25      /*Timer 2 */
 #define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
 #define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
 #define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_init.h b/arch/blackfin/mach-bf533/include/mach/mem_init.h
deleted file mode 100644
index ed2034bf10ec..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/mem_init.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
-     CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
index 581fc6eea789..fc33b7cb9937 100644
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h
@@ -168,4 +168,10 @@
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
 
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index 8255374c04aa..bbc08fd4f122 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -64,29 +64,29 @@ config IRQ_MAC_RX
 config IRQ_MAC_TX
         int "IRQ_MAC_TX"
         default 11
-config IRQ_TMR0
-        int "IRQ_TMR0"
-        default 12
-config IRQ_TMR1
-        int "IRQ_TMR1"
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 8
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
         default 12
-config IRQ_TMR2
-        int "IRQ_TMR2"
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
         default 12
-config IRQ_TMR3
-        int "IRQ_TMR3"
+config IRQ_TIMER3
+        int "IRQ_TIMER3"
         default 12
-config IRQ_TMR4
-        int "IRQ_TMR4"
+config IRQ_TIMER4
+        int "IRQ_TIMER4"
         default 12
-config IRQ_TMR5
-        int "IRQ_TMR5"
+config IRQ_TIMER5
+        int "IRQ_TIMER5"
         default 12
-config IRQ_TMR6
-        int "IRQ_TMR6"
+config IRQ_TIMER6
+        int "IRQ_TIMER6"
         default 12
-config IRQ_TMR7
-        int "IRQ_TMR7"
+config IRQ_TIMER7
+        int "IRQ_TIMER7"
         default 12
 config IRQ_PROG_INTA
         int "IRQ_PROG_INTA"
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
index 68e5478e95a9..56994b675f9c 100644
--- a/arch/blackfin/mach-bf537/Makefile
+++ b/arch/blackfin/mach-bf537/Makefile
@@ -2,6 +2,4 @@
 # arch/blackfin/mach-bf537/Makefile
 #
 
-extra-y := head.o
-
 obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index dde14720b0ea..6ac8e4d5bd38 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -308,6 +308,19 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
 
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
 #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
 static struct mtd_partition cm_partitions[] = {
         {
@@ -379,30 +392,57 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
-
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -525,7 +565,12 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
@@ -564,6 +609,8 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
         &cm_flash_device,
 #endif
+
+        &bfin_gpios_device,
 };
 
 static int __init cm_bf537_init(void)
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index 78a13d5bfd55..dd6e6bfb98ea 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -50,57 +50,46 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "GENERIC Board";
+const char bfin_board_name[] = "UNKNOWN BOARD";
 
 /*
  *  Driver needs to know address, irq and flag pin.
  */
 
-#define ISP1761_BASE       0x203C0000
-#define ISP1761_IRQ        IRQ_PF7
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
         [0] = {
-                .name   = "isp1761-regs",
-                .start  = ISP1761_BASE + 0x00000000,
-                .end    = ISP1761_BASE + 0x000fffff,
+                .start  = 0x203C0000,
+                .end    = 0x203C0000 + 0x000fffff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = ISP1761_IRQ,
-                .end    = ISP1761_IRQ,
+                .start  = IRQ_PF7,
+                .end    = IRQ_PF7,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
@@ -559,30 +548,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -651,6 +669,10 @@ static struct platform_device *stamp_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
         &bfin_spi0_device,
 #endif
@@ -668,7 +690,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 48c4cd2d1be6..bb795341cb17 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -226,30 +226,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -311,7 +340,12 @@ static struct platform_device *minotaur_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index f9174c11cbd4..89de94f4545d 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -49,7 +49,7 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "PNAV-1.0";
+const char bfin_board_name[] = "ADI PNAV-1.0";
 
 /*
  *  Driver needs to know address, irq and flag pin.
@@ -453,30 +453,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 static struct platform_device *stamp_devices[] __initdata = {
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
@@ -520,7 +549,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 };
 
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 8d394393201f..d812e2514a2f 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -46,6 +46,7 @@
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/usb/sl811.h>
+#include <linux/spi/mmc_spi.h>
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/reboot.h>
@@ -55,57 +56,46 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADDS-BF537-STAMP";
+const char bfin_board_name[] = "ADI BF537-STAMP";
 
 /*
  *  Driver needs to know address, irq and flag pin.
  */
 
-#define ISP1761_BASE       0x203C0000
-#define ISP1761_IRQ        IRQ_PF7
-
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
         [0] = {
-                .name   = "isp1761-regs",
-                .start  = ISP1761_BASE + 0x00000000,
-                .end    = ISP1761_BASE + 0x000fffff,
+                .start  = 0x203C0000,
+                .end    = 0x203C0000 + 0x000fffff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = ISP1761_IRQ,
-                .end    = ISP1761_IRQ,
-                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_PF7,
+                .end    = IRQ_PF7,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
@@ -443,11 +433,11 @@ static struct mtd_partition stamp_partitions[] = {
                 .offset     = 0,
         }, {
                 .name       = "linux kernel(nor)",
-                .size       = 0xE0000,
+                .size       = 0x180000,
                 .offset     = MTDPART_OFS_APPEND,
         }, {
                 .name       = "file system(nor)",
-                .size       = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
+                .size       = 0x400000 - 0x40000 - 0x180000 - 0x10000,
                 .offset     = MTDPART_OFS_APPEND,
         }, {
                 .name       = "MAC Address(nor)",
@@ -490,7 +480,7 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
                 .mask_flags = MTD_CAP_ROM
         }, {
                 .name = "linux kernel(spi)",
-                .size = 0xe0000,
+                .size = 0x180000,
                 .offset = MTDPART_OFS_APPEND,
         }, {
                 .name = "file system(spi)",
@@ -503,7 +493,7 @@ static struct flash_platform_data bfin_spi_flash_data = {
         .name = "m25p80",
         .parts = bfin_spi_flash_partitions,
         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
-        .type = "m25p64",
+        /* .type = "m25p64", */
 };
 
 /* SPI flash chip (m25p64) */
@@ -537,9 +527,29 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
-static struct bfin5xx_spi_chip spi_mmc_chip_info = {
-        .enable_dma = 1,
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
+
+static int bfin_mmc_spi_init(struct device *dev,
+        irqreturn_t (*detect_int)(int, void *), void *data)
+{
+        return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
+                IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
+}
+
+static void bfin_mmc_spi_exit(struct device *dev, void *data)
+{
+        free_irq(MMC_SPI_CARD_DETECT_INT, data);
+}
+
+static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
+        .init = bfin_mmc_spi_init,
+        .exit = bfin_mmc_spi_exit,
+        .detect_delay = 100, /* msecs */
+};
+
+static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
+        .enable_dma = 0,
         .bits_per_word = 8,
 };
 #endif
@@ -613,6 +623,14 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
 };
 #endif
 
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
+        .enable_dma     = 1,
+        .bits_per_word  = 8,
+        .cs_gpio = GPIO_PF10,
+};
+#endif
+
 #if defined(CONFIG_MTD_DATAFLASH) \
         || defined(CONFIG_MTD_DATAFLASH_MODULE)
 
@@ -624,7 +642,7 @@ static struct mtd_partition bfin_spi_dataflash_partitions[] = {
                 .mask_flags = MTD_CAP_ROM
         }, {
                 .name = "linux kernel(spi)",
-                .size = 0xe0000,
+                .size = 0x180000,
                 .offset = MTDPART_OFS_APPEND,
         }, {
                 .name = "file system(spi)",
@@ -703,23 +721,14 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .controller_data = &ad9960_spi_chip_info,
         },
 #endif
-#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
         {
-                .modalias = "spi_mmc_dummy",
+                .modalias = "mmc_spi",
                 .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
-                .mode = SPI_MODE_3,
-        },
-        {
-                .modalias = "spi_mmc",
-                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 0,
-                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
-                .platform_data = NULL,
-                .controller_data = &spi_mmc_chip_info,
+                .chip_select = 4,
+                .platform_data = &bfin_mmc_spi_pdata,
+                .controller_data = &mmc_spi_chip_info,
                 .mode = SPI_MODE_3,
         },
 #endif
@@ -783,6 +792,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .mode = SPI_CPHA | SPI_CPOL,
         },
 #endif
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+        {
+                .modalias = "enc28j60",
+                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
+                .irq = IRQ_PF6,
+                .bus_num = 0,
+                .chip_select = 0,       /* GPIO controlled SSEL */
+                .controller_data = &enc28j60_spi_chip_info,
+                .mode = SPI_MODE_0,
+        },
+#endif
 };
 
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -885,30 +905,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -932,6 +981,93 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
 
+#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
+#include <linux/input.h>
+#include <linux/i2c/adp5588_keys.h>
+static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
+        [0]      = KEY_GRAVE,
+        [1]      = KEY_1,
+        [2]      = KEY_2,
+        [3]      = KEY_3,
+        [4]      = KEY_4,
+        [5]      = KEY_5,
+        [6]      = KEY_6,
+        [7]      = KEY_7,
+        [8]      = KEY_8,
+        [9]      = KEY_9,
+        [10]     = KEY_0,
+        [11]     = KEY_MINUS,
+        [12]     = KEY_EQUAL,
+        [13]     = KEY_BACKSLASH,
+        [15]     = KEY_KP0,
+        [16]     = KEY_Q,
+        [17]     = KEY_W,
+        [18]     = KEY_E,
+        [19]     = KEY_R,
+        [20]     = KEY_T,
+        [21]     = KEY_Y,
+        [22]     = KEY_U,
+        [23]     = KEY_I,
+        [24]     = KEY_O,
+        [25]     = KEY_P,
+        [26]     = KEY_LEFTBRACE,
+        [27]     = KEY_RIGHTBRACE,
+        [29]     = KEY_KP1,
+        [30]     = KEY_KP2,
+        [31]     = KEY_KP3,
+        [32]     = KEY_A,
+        [33]     = KEY_S,
+        [34]     = KEY_D,
+        [35]     = KEY_F,
+        [36]     = KEY_G,
+        [37]     = KEY_H,
+        [38]     = KEY_J,
+        [39]     = KEY_K,
+        [40]     = KEY_L,
+        [41]     = KEY_SEMICOLON,
+        [42]     = KEY_APOSTROPHE,
+        [43]     = KEY_BACKSLASH,
+        [45]     = KEY_KP4,
+        [46]     = KEY_KP5,
+        [47]     = KEY_KP6,
+        [48]     = KEY_102ND,
+        [49]     = KEY_Z,
+        [50]     = KEY_X,
+        [51]     = KEY_C,
+        [52]     = KEY_V,
+        [53]     = KEY_B,
+        [54]     = KEY_N,
+        [55]     = KEY_M,
+        [56]     = KEY_COMMA,
+        [57]     = KEY_DOT,
+        [58]     = KEY_SLASH,
+        [60]     = KEY_KPDOT,
+        [61]     = KEY_KP7,
+        [62]     = KEY_KP8,
+        [63]     = KEY_KP9,
+        [64]     = KEY_SPACE,
+        [65]     = KEY_BACKSPACE,
+        [66]     = KEY_TAB,
+        [67]     = KEY_KPENTER,
+        [68]     = KEY_ENTER,
+        [69]     = KEY_ESC,
+        [70]     = KEY_DELETE,
+        [74]     = KEY_KPMINUS,
+        [76]     = KEY_UP,
+        [77]     = KEY_DOWN,
+        [78]     = KEY_RIGHT,
+        [79]     = KEY_LEFT,
+};
+
+static struct adp5588_kpad_platform_data adp5588_kpad_data = {
+        .rows           = 8,
+        .cols           = 10,
+        .keymap         = adp5588_keymap,
+        .keymapsize     = ARRAY_SIZE(adp5588_keymap),
+        .repeat         = 0,
+};
+#endif
+
 #ifdef CONFIG_I2C_BOARDINFO
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
@@ -958,6 +1094,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                 .platform_data = (void *)&bfin_ad7879_ts_info,
         },
 #endif
+#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
+        {
+                I2C_BOARD_INFO("adp5588-keys", 0x34),
+                .irq = IRQ_PG0,
+                .platform_data = (void *)&adp5588_kpad_data,
+        },
+#endif
 };
 #endif
 
@@ -1057,6 +1200,10 @@ static struct platform_device *stamp_devices[] __initdata = {
         &isp1362_hcd_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
         &smc91x_device,
 #endif
@@ -1098,7 +1245,12 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index d5ff705a5129..2f4b066153c5 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -308,6 +308,19 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
 
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
 #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
 static struct mtd_partition cm_partitions[] = {
         {
@@ -379,30 +392,59 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir1_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
@@ -525,7 +567,12 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
@@ -564,6 +611,8 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
         &cm_flash_device,
 #endif
+
+        &bfin_gpios_device,
 };
 
 static int __init cm_bf537_init(void)
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 4edb363ff99c..81185051de91 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -31,7 +31,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
deleted file mode 100644
index f5c94bf80e3b..000000000000
--- a/arch/blackfin/mach-bf537/head.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf537/head.S
- * Based on:     arch/blackfin/mach-bf533/head.S
- * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
- *
- * Created:      1998
- * Description:  Startup code for Blackfin BF537
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#include <asm/clocks.h>
-#include <mach/mem_init.h>
-#endif
-
-.section .l1.text
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-ENTRY(_start_dma_code)
-
-        /* Enable PHY CLK buffer output */
-        p0.h = hi(VR_CTL);
-        p0.l = lo(VR_CTL);
-        r0.l = w[p0];
-        bitset(r0, 14);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.h = hi(SIC_IWR);
-        p0.l = lo(SIC_IWR);
-        r0.l = 0x1;
-        r0.h = 0x0;
-        [p0] = r0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        p0.h = hi(PLL_LOCKCNT);
-        p0.l = lo(PLL_LOCKCNT);
-        r0 = 0x300(Z);
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-#ifdef ANOMALY_05000265
-        BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
-#endif
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-
-.Lcheck_again:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again;
-
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
-        p0.h = hi(EBIU_SDSTAT);
-        p0.l = lo(EBIU_SDSTAT);
-        r2.l = w[p0];
-        cc = bittst(r2,3);
-        if !cc jump .Lskip;
-        NOP;
-        BITSET (R0, 23);
-.Lskip:
-        [P2] = R0;
-        SSYNC;
-
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
-        R1 = [p2];
-        R1 = R1 | R0;
-        [P2] = R1;
-        SSYNC;
-
-        RTS;
-ENDPROC(_start_dma_code)
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index c68992494f9e..9cb39121d1cb 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -148,6 +148,14 @@
 #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -161,5 +169,8 @@
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
index 24d5c9d42323..f194a848ae8e 100644
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -133,7 +133,7 @@
 #endif
 
 #ifndef CPU
-#error Unknown CPU type - This kernel doesn't seem to be configured properly
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 #endif
 
 #endif                          /* __MACH_BF537_H__  */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index cffc786b2a2b..7d6069c886f1 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -82,7 +82,7 @@
 #define STATUS_P1       0x02
 #define STATUS_P0       0x01
 
-/* DMA Channnel */
+/* DMA Channel */
 #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
 #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
 #define CH_UART_RX CH_UART0_RX
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index 88d491cd9f36..5f8b5f845be6 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -40,55 +40,11 @@
 /* Include core specific register pointer definitions                                                           */
 #include <asm/cdef_LPBlackfin.h>
 
-#include <asm/system.h>
-
 /* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -1816,4 +1772,51 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR, iwr);
+        local_irq_restore_hw(flags);
+}
+
 #endif                          /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
index 7a964040870a..5ae83b1183a1 100644
--- a/arch/blackfin/mach-bf537/include/mach/dma.h
+++ b/arch/blackfin/mach-bf537/include/mach/dma.h
@@ -1,38 +1,14 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/dma.h
- * based on:
- * author:
+/* mach/dma.h - arch-specific DMA defines
  *
- * created:
- * description:
- *      system mmr register map
- * rev:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_DMA_H_
 #define _MACH_DMA_H_
 
-#define MAX_BLACKFIN_DMA_CHANNEL 16
+#define MAX_DMA_CHANNELS 16
 
 #define CH_PPI                      0
 #define CH_EMAC_RX                  1
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
new file mode 100644
index 000000000000..d77a31e45a30
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -0,0 +1,68 @@
+/*
+ * File: arch/blackfin/mach-bf537/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PG0        16
+#define GPIO_PG1        17
+#define GPIO_PG2        18
+#define GPIO_PG3        19
+#define GPIO_PG4        20
+#define GPIO_PG5        21
+#define GPIO_PG6        22
+#define GPIO_PG7        23
+#define GPIO_PG8        24
+#define GPIO_PG9        25
+#define GPIO_PG10       26
+#define GPIO_PG11       27
+#define GPIO_PG12       28
+#define GPIO_PG13       29
+#define GPIO_PG14       30
+#define GPIO_PG15       31
+#define GPIO_PH0        32
+#define GPIO_PH1        33
+#define GPIO_PH2        34
+#define GPIO_PH3        35
+#define GPIO_PH4        36
+#define GPIO_PH5        37
+#define GPIO_PH6        38
+#define GPIO_PH7        39
+#define GPIO_PH8        40
+#define GPIO_PH9        41
+#define GPIO_PH10       42
+#define GPIO_PH11       43
+#define GPIO_PH12       44
+#define GPIO_PH13       45
+#define GPIO_PH14       46
+#define GPIO_PH15       47
+
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2e68a8a1e730..b2a71d5d4e5f 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -82,14 +82,14 @@
 #define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
 #define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
 #define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TMR0            26  /*Timer 0 */
-#define IRQ_TMR1            27  /*Timer 1 */
-#define IRQ_TMR2            28  /*Timer 2 */
-#define IRQ_TMR3            29  /*Timer 3 */
-#define IRQ_TMR4            30  /*Timer 4 */
-#define IRQ_TMR5            31  /*Timer 5 */
-#define IRQ_TMR6            32  /*Timer 6 */
-#define IRQ_TMR7            33  /*Timer 7 */
+#define IRQ_TIMER0            26        /*Timer 0 */
+#define IRQ_TIMER1            27        /*Timer 1 */
+#define IRQ_TIMER2            28        /*Timer 2 */
+#define IRQ_TIMER3            29        /*Timer 3 */
+#define IRQ_TIMER4            30        /*Timer 4 */
+#define IRQ_TIMER5            31        /*Timer 5 */
+#define IRQ_TIMER6            32        /*Timer 6 */
+#define IRQ_TIMER7            33        /*Timer 7 */
 #define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
 #define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
 #define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
@@ -195,16 +195,16 @@
 #define IRQ_CAN_TX_POS      0
 #define IRQ_MAC_RX_POS      4
 #define IRQ_MAC_TX_POS      8
-#define IRQ_TMR0_POS        12
-#define IRQ_TMR1_POS        16
-#define IRQ_TMR2_POS        20
-#define IRQ_TMR3_POS        24
-#define IRQ_TMR4_POS        28
+#define IRQ_TIMER0_POS        12
+#define IRQ_TIMER1_POS        16
+#define IRQ_TIMER2_POS        20
+#define IRQ_TIMER3_POS        24
+#define IRQ_TIMER4_POS        28
 
 /* IAR3 BIT FIELDS*/
-#define IRQ_TMR5_POS        0
-#define IRQ_TMR6_POS        4
-#define IRQ_TMR7_POS        8
+#define IRQ_TIMER5_POS        0
+#define IRQ_TIMER6_POS        4
+#define IRQ_TIMER7_POS        8
 #define IRQ_PROG_INTA_POS   12
 #define IRQ_PORTG_INTB_POS   16
 #define IRQ_MEM_DMA0_POS    20
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_init.h b/arch/blackfin/mach-bf537/include/mach/mem_init.h
deleted file mode 100644
index f67698f670ca..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/mem_init.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
index 5078b669431f..f9010c4b4bf3 100644
--- a/arch/blackfin/mach-bf537/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h
@@ -176,4 +176,10 @@
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
 
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
 #endif                          /* _MEM_MAP_537_H_ */
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index b1300b3f1812..51c48087e03b 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -55,15 +55,15 @@ void __init program_IAR(void)
         bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
                             ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
                             ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
-                            ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
-                            ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
-                            ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
-                            ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
-                            ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS));
+                            ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                            ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
+                            ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                            ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+                            ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
 
-        bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
-                            ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
-                            ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) |
+        bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+                            ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+                            ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
                             ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
                             ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
                             ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
new file mode 100644
index 000000000000..f068c3523cdc
--- /dev/null
+++ b/arch/blackfin/mach-bf538/Kconfig
@@ -0,0 +1,164 @@
+if (BF538 || BF539)
+
+source "arch/blackfin/mach-bf538/boards/Kconfig"
+
+menu "BF538 Specific Configuration"
+
+comment "Interrupt Priority Assignment"
+menu "Priority"
+
+config IRQ_PLL_WAKEUP
+        int "IRQ_PLL_WAKEUP"
+        default 7
+config IRQ_DMA0_ERROR
+        int "IRQ_DMA0_ERROR"
+        default 7
+config IRQ_PPI_ERROR
+        int "IRQ_PPI_ERROR"
+        default 7
+config IRQ_SPORT0_ERROR
+        int "IRQ_SPORT0_ERROR"
+        default 7
+config IRQ_SPORT1_ERROR
+        int "IRQ_SPORT1_ERROR"
+        default 7
+config IRQ_SPI0_ERROR
+        int "IRQ_SPI0_ERROR"
+        default 7
+config IRQ_UART0_ERROR
+        int "IRQ_UART0_ERROR"
+        default 7
+config IRQ_RTC
+        int "IRQ_RTC"
+        default 8
+config IRQ_PPI
+        int "IRQ_PPI"
+        default 8
+config IRQ_SPORT0_RX
+        int "IRQ_SPORT0_RX"
+        default 9
+config IRQ_SPORT0_TX
+        int "IRQ_SPORT0_TX"
+        default 9
+config IRQ_SPORT1_RX
+        int "IRQ_SPORT1_RX"
+        default 9
+config IRQ_SPORT1_TX
+        int "IRQ_SPORT1_TX"
+        default 9
+config IRQ_SPI0
+        int "IRQ_SPI0"
+        default 10
+config IRQ_UART0_RX
+        int "IRQ_UART0_RX"
+        default 10
+config IRQ_UART0_TX
+        int "IRQ_UART0_TX"
+        default 10
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 8
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
+        default 11
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
+        default 11
+config IRQ_PORTF_INTA
+        int "IRQ_PORTF_INTA"
+        default 12
+config IRQ_PORTF_INTB
+        int "IRQ_PORTF_INTB"
+        default 12
+config IRQ_MEM0_DMA0
+        int "IRQ_MEM0_DMA0"
+        default 13
+config IRQ_MEM0_DMA1
+        int "IRQ_MEM0_DMA1"
+        default 13
+config IRQ_WATCH
+        int "IRQ_WATCH"
+        default 13
+config IRQ_DMA1_ERROR
+        int "IRQ_DMA1_ERROR"
+        default 7
+config IRQ_SPORT2_ERROR
+        int "IRQ_SPORT2_ERROR"
+        default 7
+config IRQ_SPORT3_ERROR
+        int "IRQ_SPORT3_ERROR"
+        default 7
+config IRQ_SPI1_ERROR
+        int "IRQ_SPI1_ERROR"
+        default 7
+config IRQ_SPI2_ERROR
+        int "IRQ_SPI2_ERROR"
+        default 7
+config IRQ_UART1_ERROR
+        int "IRQ_UART1_ERROR"
+        default 7
+config IRQ_UART2_ERROR
+        int "IRQ_UART2_ERROR"
+        default 7
+config IRQ_CAN_ERROR
+        int "IRQ_CAN_ERROR"
+        default 7
+config IRQ_SPORT2_RX
+        int "IRQ_SPORT2_RX"
+        default 9
+config IRQ_SPORT2_TX
+        int "IRQ_SPORT2_TX"
+        default 9
+config IRQ_SPORT3_RX
+        int "IRQ_SPORT3_RX"
+        default 9
+config IRQ_SPORT3_TX
+        int "IRQ_SPORT3_TX"
+        default 9
+config IRQ_SPI1
+        int "IRQ_SPI1"
+        default 10
+config IRQ_SPI2
+        int "IRQ_SPI2"
+        default 10
+config IRQ_UART1_RX
+        int "IRQ_UART1_RX"
+        default 10
+config IRQ_UART1_TX
+        int "IRQ_UART1_TX"
+        default 10
+config IRQ_UART2_RX
+        int "IRQ_UART2_RX"
+        default 10
+config IRQ_UART2_TX
+        int "IRQ_UART2_TX"
+        default 10
+config IRQ_TWI0
+        int "IRQ_TWI0"
+        default 11
+config IRQ_TWI1
+        int "IRQ_TWI1"
+        default 11
+config IRQ_CAN_RX
+        int "IRQ_CAN_RX"
+        default 11
+config IRQ_CAN_TX
+        int "IRQ_CAN_TX"
+        default 11
+config IRQ_MEM1_DMA0
+        int "IRQ_MEM1_DMA0"
+        default 13
+config IRQ_MEM1_DMA1
+        int "IRQ_MEM1_DMA1"
+        default 13
+
+        help
+          Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
+          This applies to all the above.  It is not recommended to assign the
+          highest priority number 7 to UART or any other device.
+
+endmenu
+
+endmenu
+
+endif
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
new file mode 100644
index 000000000000..8cd2719684db
--- /dev/null
+++ b/arch/blackfin/mach-bf538/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf538/Makefile
+#
+
+obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig
new file mode 100644
index 000000000000..215249ba58bb
--- /dev/null
+++ b/arch/blackfin/mach-bf538/boards/Kconfig
@@ -0,0 +1,12 @@
+choice
+        prompt "System type"
+        default BFIN538_EZKIT
+        help
+          Select your board!
+
+config BFIN538_EZKIT
+        bool "BF538-EZKIT"
+        help
+          BF538-EZKIT-LITE board support.
+
+endchoice
diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile
new file mode 100644
index 000000000000..6143b320d585
--- /dev/null
+++ b/arch/blackfin/mach-bf538/boards/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf538/boards/Makefile
+#
+
+obj-$(CONFIG_BFIN538_EZKIT)            += ezkit.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
new file mode 100644
index 000000000000..e37cb9378884
--- /dev/null
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -0,0 +1,606 @@
+/*
+ * File:         arch/blackfin/mach-bf538/boards/ezkit.c
+ * Based on:     arch/blackfin/mach-bf537/boards/ezkit.c
+ * Author:       Aidan Williams <aidan@nicta.com.au>
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2005 National ICT Australia (NICTA)
+ *               Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/dma.h>
+#include <asm/gpio.h>
+#include <asm/nand.h>
+#include <asm/portmux.h>
+#include <asm/dpmc.h>
+#include <linux/input.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "ADI BF538-EZKIT";
+
+/*
+ *  Driver needs to know address, irq and flag pin.
+ */
+
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+static struct resource bfin_uart_resources[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+        {
+                .start = 0xFFC02100,
+                .end = 0xFFC021FF,
+                .flags = IORESOURCE_MEM,
+        },
+#endif
+};
+
+static struct platform_device bfin_uart_device = {
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart_resources),
+        .resource = bfin_uart_resources,
+};
+#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir1_device = {
+        .name = "bfin_sir",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
+};
+#endif
+#ifdef CONFIG_BFIN_SIR2
+static struct resource bfin_sir2_resources[] = {
+        {
+                .start = 0xFFC02100,
+                .end = 0xFFC021FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART2_RX,
+                .end = IRQ_UART2_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART2_RX,
+                .end = CH_UART2_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir2_device = {
+        .name = "bfin_sir",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(bfin_sir2_resources),
+        .resource = bfin_sir2_resources,
+};
+#endif
+#endif
+
+/*
+ *  USB-LAN EzExtender board
+ *  Driver needs to know address, irq and flag pin.
+ */
+#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+static struct resource smc91x_resources[] = {
+        {
+                .name = "smc91x-regs",
+                .start = 0x20310300,
+                .end = 0x20310300 + 16,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IRQ_PF0,
+                .end = IRQ_PF0,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+};
+static struct platform_device smc91x_device = {
+        .name = "smc91x",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(smc91x_resources),
+        .resource = smc91x_resources,
+};
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+/* all SPI peripherals info goes here */
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+/* SPI flash chip (m25p16) */
+static struct mtd_partition bfin_spi_flash_partitions[] = {
+        {
+                .name = "bootloader(spi)",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = MTD_CAP_ROM
+        }, {
+                .name = "linux kernel(spi)",
+                .size = 0x1c0000,
+                .offset = 0x40000
+        }
+};
+
+static struct flash_platform_data bfin_spi_flash_data = {
+        .name = "m25p80",
+        .parts = bfin_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
+        .type = "m25p16",
+};
+
+static struct bfin5xx_spi_chip spi_flash_chip_info = {
+        .enable_dma = 0,         /* use dma transfer with this chip*/
+        .bits_per_word = 8,
+        .cs_change_per_word = 0,
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#include <linux/spi/ad7879.h>
+static const struct ad7879_platform_data bfin_ad7879_ts_info = {
+        .model                  = 7879, /* Model = AD7879 */
+        .x_plate_ohms           = 620,  /* 620 Ohm from the touch datasheet */
+        .pressure_max           = 10000,
+        .pressure_min           = 0,
+        .first_conversion_delay = 3,    /* wait 512us before do a first conversion */
+        .acquisition_time       = 1,    /* 4us acquisition time per sample */
+        .median                 = 2,    /* do 8 measurements */
+        .averaging              = 1,    /* take the average of 4 middle samples */
+        .pen_down_acc_interval  = 255,  /* 9.4 ms */
+        .gpio_output            = 1,    /* configure AUX/VBAT/GPIO as GPIO output */
+        .gpio_default           = 1,    /* During initialization set GPIO = HIGH */
+};
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+#endif
+
+#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#include <asm/bfin-lq035q1.h>
+
+static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
+        .mode =         LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
+        .use_bl =       0,      /* let something else control the LCD Blacklight */
+        .gpio_bl =      GPIO_PF7,
+};
+
+static struct resource bfin_lq035q1_resources[] = {
+        {
+                .start = IRQ_PPI_ERROR,
+                .end = IRQ_PPI_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device bfin_lq035q1_device = {
+        .name           = "bfin-lq035q1",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(bfin_lq035q1_resources),
+        .resource       = bfin_lq035q1_resources,
+        .dev            = {
+                .platform_data = &bfin_lq035q1_data,
+        },
+};
+#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
+        .enable_dma     = 0,
+        .bits_per_word  = 8,
+};
+#endif
+
+static struct spi_board_info bf538_spi_board_info[] __initdata = {
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+        {
+                /* the modalias must be the same as spi device driver name */
+                .modalias = "m25p80", /* Name of spi_driver for this device */
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0, /* Framework bus number */
+                .chip_select = 1, /* SPI_SSEL1*/
+                .platform_data = &bfin_spi_flash_data,
+                .controller_data = &spi_flash_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+        {
+                .modalias = "ad7879",
+                .platform_data = &bfin_ad7879_ts_info,
+                .irq = IRQ_PF3,
+                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = &spi_ad7879_chip_info,
+                .mode = SPI_CPHA | SPI_CPOL,
+        },
+#endif
+#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+        {
+                .modalias = "bfin-lq035q1-spi",
+                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 2,
+                .controller_data = &lq035q1_spi_chip_info,
+                .mode = SPI_CPHA | SPI_CPOL,
+        },
+#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = &spidev_chip_info,
+        },
+#endif
+};
+
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI0,
+                .end   = CH_SPI0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+/* SPI (1) */
+static struct resource bfin_spi1_resource[] = {
+        [0] = {
+                .start = SPI1_REGBASE,
+                .end   = SPI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI1,
+                .end   = CH_SPI1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+/* SPI (2) */
+static struct resource bfin_spi2_resource[] = {
+        [0] = {
+                .start = SPI2_REGBASE,
+                .end   = SPI2_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI2,
+                .end   = CH_SPI2,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+/* SPI controller data */
+static struct bfin5xx_spi_master bf538_spi_master_info0 = {
+        .num_chipselect = 8,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+
+static struct platform_device bf538_spi_master0 = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
+        .dev = {
+                .platform_data = &bf538_spi_master_info0, /* Passed to driver */
+                },
+};
+
+static struct bfin5xx_spi_master bf538_spi_master_info1 = {
+        .num_chipselect = 8,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
+};
+
+static struct platform_device bf538_spi_master1 = {
+        .name = "bfin-spi",
+        .id = 1, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi1_resource),
+        .resource = bfin_spi1_resource,
+        .dev = {
+                .platform_data = &bf538_spi_master_info1, /* Passed to driver */
+                },
+};
+
+static struct bfin5xx_spi_master bf538_spi_master_info2 = {
+        .num_chipselect = 8,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+        .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
+};
+
+static struct platform_device bf538_spi_master2 = {
+        .name = "bfin-spi",
+        .id = 2, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi2_resource),
+        .resource = bfin_spi2_resource,
+        .dev = {
+                .platform_data = &bf538_spi_master_info2, /* Passed to driver */
+                },
+};
+
+#endif  /* spi master and devices */
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI0,
+                .end   = IRQ_TWI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c_bfin_twi0_device = {
+        .name = "i2c-bfin-twi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
+};
+
+#if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
+static struct resource bfin_twi1_resource[] = {
+        [0] = {
+                .start = TWI1_REGBASE,
+                .end   = TWI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI1,
+                .end   = IRQ_TWI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c_bfin_twi1_device = {
+        .name = "i2c-bfin-twi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
+        .resource = bfin_twi1_resource,
+};
+#endif
+#endif
+
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+        {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+        .buttons        = bfin_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+        .name      = "gpio-keys",
+        .dev = {
+                .platform_data = &bfin_gpio_keys_data,
+        },
+};
+#endif
+
+static const unsigned int cclk_vlev_datasheet[] =
+{
+/*
+ * Internal VLEV BF538SBBC1533
+ ****temporarily using these values until data sheet is updated
+ */
+        VRPAIR(VLEV_100, 150000000),
+        VRPAIR(VLEV_100, 250000000),
+        VRPAIR(VLEV_110, 276000000),
+        VRPAIR(VLEV_115, 301000000),
+        VRPAIR(VLEV_120, 525000000),
+        VRPAIR(VLEV_125, 550000000),
+        VRPAIR(VLEV_130, 600000000),
+};
+
+static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
+        .tuple_tab = cclk_vlev_datasheet,
+        .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
+        .vr_settling_time = 25 /* us */,
+};
+
+static struct platform_device bfin_dpmc = {
+        .name = "bfin dpmc",
+        .dev = {
+                .platform_data = &bfin_dmpc_vreg_data,
+        },
+};
+
+static struct platform_device *cm_bf538_devices[] __initdata = {
+
+        &bfin_dpmc,
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+        &bfin_uart_device,
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &bf538_spi_master0,
+        &bf538_spi_master1,
+        &bf538_spi_master2,
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi0_device,
+        &i2c_bfin_twi1_device,
+#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
+#ifdef CONFIG_BFIN_SIR2
+        &bfin_sir2_device,
+#endif
+#endif
+
+#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+        &smc91x_device,
+#endif
+
+#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+        &bfin_lq035q1_device,
+#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+        &bfin_device_gpiokeys,
+#endif
+
+        &bfin_gpios_device,
+};
+
+static int __init ezkit_init(void)
+{
+        printk(KERN_INFO "%s(): registering device resources\n", __func__);
+        platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        spi_register_board_info(bf538_spi_board_info,
+                        ARRAY_SIZE(bf538_spi_board_info));
+#endif
+
+        return 0;
+}
+
+arch_initcall(ezkit_init);
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
new file mode 100644
index 000000000000..d6837fbf94ea
--- /dev/null
+++ b/arch/blackfin/mach-bf538/dma.c
@@ -0,0 +1,161 @@
+/*
+ * File:         arch/blackfin/mach-bf538/dma.c
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  This file contains the simple DMA Implementation for Blackfin
+ *
+ * Modified:
+ *               Copyright 2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA11_NEXT_DESC_PTR,
+        (struct dma_register *) DMA12_NEXT_DESC_PTR,
+        (struct dma_register *) DMA13_NEXT_DESC_PTR,
+        (struct dma_register *) DMA14_NEXT_DESC_PTR,
+        (struct dma_register *) DMA15_NEXT_DESC_PTR,
+        (struct dma_register *) DMA16_NEXT_DESC_PTR,
+        (struct dma_register *) DMA17_NEXT_DESC_PTR,
+        (struct dma_register *) DMA18_NEXT_DESC_PTR,
+        (struct dma_register *) DMA19_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
+};
+EXPORT_SYMBOL(dma_io_base_addr);
+
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+
+        switch (channel) {
+        case CH_PPI:
+                ret_irq = IRQ_PPI;
+                break;
+
+        case CH_UART0_RX:
+                ret_irq = IRQ_UART0_RX;
+                break;
+
+        case CH_UART0_TX:
+                ret_irq = IRQ_UART0_TX;
+                break;
+
+        case CH_UART1_RX:
+                ret_irq = IRQ_UART1_RX;
+                break;
+
+        case CH_UART1_TX:
+                ret_irq = IRQ_UART1_TX;
+                break;
+
+        case CH_UART2_RX:
+                ret_irq = IRQ_UART2_RX;
+                break;
+
+        case CH_UART2_TX:
+                ret_irq = IRQ_UART2_TX;
+                break;
+
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+
+        case CH_SPORT2_RX:
+                ret_irq = IRQ_SPORT2_RX;
+                break;
+
+        case CH_SPORT2_TX:
+                ret_irq = IRQ_SPORT2_TX;
+                break;
+
+        case CH_SPORT3_RX:
+                ret_irq = IRQ_SPORT3_RX;
+                break;
+
+        case CH_SPORT3_TX:
+                ret_irq = IRQ_SPORT3_TX;
+                break;
+
+        case CH_SPI0:
+                ret_irq = IRQ_SPI0;
+                break;
+
+        case CH_SPI1:
+                ret_irq = IRQ_SPI1;
+                break;
+
+        case CH_SPI2:
+                ret_irq = IRQ_SPI2;
+                break;
+
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MEM0_DMA0;
+                break;
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MEM0_DMA1;
+                break;
+        case CH_MEM_STREAM2_SRC:
+        case CH_MEM_STREAM2_DEST:
+                ret_irq = IRQ_MEM1_DMA0;
+                break;
+        case CH_MEM_STREAM3_SRC:
+        case CH_MEM_STREAM3_DEST:
+                ret_irq = IRQ_MEM1_DMA1;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
new file mode 100644
index 000000000000..e130b4f8a05d
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -0,0 +1,132 @@
+/*
+ * File: include/asm-blackfin/mach-bf538/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ *  - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+#if __SILICON_REVISION__ < 4
+# error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3
+#endif
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (1)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (1)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (1)
+/* SPI Slave Boot Mode Modifies Registers from Reset Value */
+#define ANOMALY_05000229 (1)
+/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
+#define ANOMALY_05000233 (1)
+/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (1)
+/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM Memory May Be Lost */
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
+/* False Hardware Error Exception when ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
+/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
+/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
+#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
+/* Hibernate Leakage Current Is Higher Than Specified */
+#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
+/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000294 (1)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
+/* PPI Is Level-Sensitive on First Transfer */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
+/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
+/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
+#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
+/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
+#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
+/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */
+#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Specific GPIO Pins May Change State when Entering Hibernate */
+#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h
new file mode 100644
index 000000000000..9c8abb307908
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bf538.h
@@ -0,0 +1,124 @@
+/*
+ * File:         include/asm-blackfin/mach-bf538/bf538.h
+ * Based on:    include/asm-blackfin/mach-bf537/bf537.h
+ * Author:      Michael Hennerich (michael.hennerich@analog.com)
+ *
+ * Created:
+ * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF538_H__
+#define __MACH_BF538_H__
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR    0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************/
+
+#define BFIN_DSUBBANKS  4
+#define BFIN_DWAYS              2
+#define BFIN_DLINES             64
+#define BFIN_ISUBBANKS  4
+#define BFIN_IWAYS              4
+#define BFIN_ILINES             32
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+#ifdef CONFIG_C_CDPRIO
+#define V_CDPRIO 0x100
+#else
+#define V_CDPRIO 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
+
+#ifdef CONFIG_BF538
+#define CPU "BF538"
+#define CPUID 0x27C4
+#endif
+#ifdef CONFIG_BF539
+#define CPU "BF539"
+#define CPUID 0x27C4    /* FXIME:? */
+#endif
+
+#ifndef CPU
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
+#endif
+
+#endif                          /* __MACH_BF538_H__  */
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..40503b6b89a3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,183 @@
+/*
+ * file:         include/asm-blackfin/mach-bf538/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      blackfin serial driver header files
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
+#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
+#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
+#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
+#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
+#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
+#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
+
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
+#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
+#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
+#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
+# define CONFIG_SERIAL_BFIN_CTSRTS
+
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_CTS_PIN
+#  define CONFIG_UART1_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_RTS_PIN
+#  define CONFIG_UART1_RTS_PIN -1
+# endif
+#endif
+
+#define BFIN_UART_TX_FIFO_SIZE  2
+
+/*
+ * The pin configuration is different from schematic
+ */
+struct bfin_serial_port {
+        struct uart_port        port;
+        unsigned int            old_status;
+        unsigned int lsr;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int                     tx_done;
+        int                     tx_count;
+        struct circ_buf         rx_dma_buf;
+        struct timer_list       rx_dma_timer;
+        int                     rx_dma_nrows;
+        unsigned int            tx_dma_channel;
+        unsigned int            rx_dma_channel;
+        struct work_struct      tx_dma_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        struct timer_list       cts_timer;
+        int             cts_pin;
+        int             rts_pin;
+#endif
+};
+
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
+{
+        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
+        uart->lsr |= (lsr & (BI|FE|PE|OE));
+        return lsr | uart->lsr;
+}
+
+static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
+{
+        uart->lsr = 0;
+        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
+}
+
+struct bfin_serial_res {
+        unsigned long   uart_base_addr;
+        int             uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int    uart_tx_dma_channel;
+        unsigned int    uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int     uart_cts_pin;
+        int     uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+        0xFFC00400,
+        IRQ_UART0_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART0_TX,
+        CH_UART0_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        CONFIG_UART0_CTS_PIN,
+        CONFIG_UART0_RTS_PIN,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+        0xFFC02000,
+        IRQ_UART1_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART1_TX,
+        CH_UART1_RX,
+#endif
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+        CONFIG_UART1_CTS_PIN,
+        CONFIG_UART1_RTS_PIN,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART2
+        {
+        0xFFC02100,
+        IRQ_UART2_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART2_TX,
+        CH_UART2_RX,
+#endif
+#ifdef CONFIG_BFIN_UART2_CTSRTS
+        CONFIG_UART2_CTS_PIN,
+        CONFIG_UART2_RTS_PIN,
+#endif
+        },
+#endif
+};
+
+#define DRIVER_NAME "bfin-uart"
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
new file mode 100644
index 000000000000..ea25371a922b
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -0,0 +1,101 @@
+/*
+ * File:         include/asm-blackfin/mach-bf538/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF538_FAMILY
+
+#include "bf538.h"
+#include "mem_map.h"
+#include "defBF539.h"
+#include "anomaly.h"
+
+
+#if !defined(__ASSEMBLY__)
+#include "cdefBF538.h"
+
+#if defined(CONFIG_BF539)
+#include "cdefBF539.h"
+#endif
+#endif
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+
+#define BFIN_UART_NR_PORTS      3
+
+#define OFFSET_THR              0x00    /* Transmit Holding register            */
+#define OFFSET_RBR              0x00    /* Receive Buffer register              */
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24    /* Global Control Register              */
+
+
+#define bfin_write_MDMA_D0_IRQ_STATUS   bfin_write_MDMA0_D0_IRQ_STATUS
+#define bfin_write_MDMA_D0_START_ADDR   bfin_write_MDMA0_D0_START_ADDR
+#define bfin_write_MDMA_S0_START_ADDR   bfin_write_MDMA0_S0_START_ADDR
+#define bfin_write_MDMA_D0_X_COUNT      bfin_write_MDMA0_D0_X_COUNT
+#define bfin_write_MDMA_S0_X_COUNT      bfin_write_MDMA0_S0_X_COUNT
+#define bfin_write_MDMA_D0_Y_COUNT      bfin_write_MDMA0_D0_Y_COUNT
+#define bfin_write_MDMA_S0_Y_COUNT      bfin_write_MDMA0_S0_Y_COUNT
+#define bfin_write_MDMA_D0_X_MODIFY     bfin_write_MDMA0_D0_X_MODIFY
+#define bfin_write_MDMA_S0_X_MODIFY     bfin_write_MDMA0_S0_X_MODIFY
+#define bfin_write_MDMA_D0_Y_MODIFY     bfin_write_MDMA0_D0_Y_MODIFY
+#define bfin_write_MDMA_S0_Y_MODIFY     bfin_write_MDMA0_S0_Y_MODIFY
+#define bfin_write_MDMA_S0_CONFIG       bfin_write_MDMA0_S0_CONFIG
+#define bfin_write_MDMA_D0_CONFIG       bfin_write_MDMA0_D0_CONFIG
+#define bfin_read_MDMA_S0_CONFIG        bfin_read_MDMA0_S0_CONFIG
+#define bfin_read_MDMA_D0_IRQ_STATUS    bfin_read_MDMA0_D0_IRQ_STATUS
+#define bfin_write_MDMA_S0_IRQ_STATUS   bfin_write_MDMA0_S0_IRQ_STATUS
+
+
+/* DPMC*/
+#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
+#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
+#define STOPCK_OFF STOPCK
+
+/* PLL_DIV Masks                                                                                                        */
+#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
+#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
+#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
+#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
new file mode 100644
index 000000000000..241725bc6988
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -0,0 +1,2108 @@
+/*
+ * File:         include/asm-blackfin/mach-bf538/cdefBF538.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF538_H
+#define _CDEF_BF538_H
+
+#include <asm/blackfin.h>
+
+/*include all Core registers and bit definitions*/
+#include "defBF539.h"
+
+/*include core specific register pointer definitions*/
+#include <asm/cdef_LPBlackfin.h>
+
+#define bfin_writePTR(addr, val) bfin_write32(addr, val)
+
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define bfin_read_SIC_RVECT()          bfin_readPTR(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)      bfin_writePTR(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IMASK(x)         bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
+#define bfin_write_SIC_IMASK(x, val)   bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_ISR(x)           bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
+#define bfin_write_SIC_ISR(x, val)     bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define bfin_read_SIC_IWR(x)           bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
+#define bfin_write_SIC_IWR(x, val)     bfin_write32((SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define bfin_read_UART2_IER()          bfin_read16(UART2_IER)
+#define bfin_write_UART2_IER(val)      bfin_write16(UART2_IER, val)
+#define bfin_read_UART2_IIR()          bfin_read16(UART2_IIR)
+#define bfin_write_UART2_IIR(val)      bfin_write16(UART2_IIR, val)
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define bfin_read_SPORT2_TX()          bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define bfin_read_SPORT3_TX()          bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
+#define bfin_read_PORTCIO_FER()        bfin_read16(PORTCIO_FER)
+#define bfin_write_PORTCIO_FER(val)    bfin_write16(PORTCIO_FER, val)
+#define bfin_read_PORTCIO()            bfin_read16(PORTCIO)
+#define bfin_write_PORTCIO(val)        bfin_write16(PORTCIO, val)
+#define bfin_read_PORTCIO_CLEAR()      bfin_read16(PORTCIO_CLEAR)
+#define bfin_write_PORTCIO_CLEAR(val)  bfin_write16(PORTCIO_CLEAR, val)
+#define bfin_read_PORTCIO_SET()        bfin_read16(PORTCIO_SET)
+#define bfin_write_PORTCIO_SET(val)    bfin_write16(PORTCIO_SET, val)
+#define bfin_read_PORTCIO_TOGGLE()     bfin_read16(PORTCIO_TOGGLE)
+#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
+#define bfin_read_PORTCIO_DIR()        bfin_read16(PORTCIO_DIR)
+#define bfin_write_PORTCIO_DIR(val)    bfin_write16(PORTCIO_DIR, val)
+#define bfin_read_PORTCIO_INEN()       bfin_read16(PORTCIO_INEN)
+#define bfin_write_PORTCIO_INEN(val)   bfin_write16(PORTCIO_INEN, val)
+#define bfin_read_PORTDIO_FER()        bfin_read16(PORTDIO_FER)
+#define bfin_write_PORTDIO_FER(val)    bfin_write16(PORTDIO_FER, val)
+#define bfin_read_PORTDIO()            bfin_read16(PORTDIO)
+#define bfin_write_PORTDIO(val)        bfin_write16(PORTDIO, val)
+#define bfin_read_PORTDIO_CLEAR()      bfin_read16(PORTDIO_CLEAR)
+#define bfin_write_PORTDIO_CLEAR(val)  bfin_write16(PORTDIO_CLEAR, val)
+#define bfin_read_PORTDIO_SET()        bfin_read16(PORTDIO_SET)
+#define bfin_write_PORTDIO_SET(val)    bfin_write16(PORTDIO_SET, val)
+#define bfin_read_PORTDIO_TOGGLE()     bfin_read16(PORTDIO_TOGGLE)
+#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
+#define bfin_read_PORTDIO_DIR()        bfin_read16(PORTDIO_DIR)
+#define bfin_write_PORTDIO_DIR(val)    bfin_write16(PORTDIO_DIR, val)
+#define bfin_read_PORTDIO_INEN()       bfin_read16(PORTDIO_INEN)
+#define bfin_write_PORTDIO_INEN(val)   bfin_write16(PORTDIO_INEN, val)
+#define bfin_read_PORTEIO_FER()        bfin_read16(PORTEIO_FER)
+#define bfin_write_PORTEIO_FER(val)    bfin_write16(PORTEIO_FER, val)
+#define bfin_read_PORTEIO()            bfin_read16(PORTEIO)
+#define bfin_write_PORTEIO(val)        bfin_write16(PORTEIO, val)
+#define bfin_read_PORTEIO_CLEAR()      bfin_read16(PORTEIO_CLEAR)
+#define bfin_write_PORTEIO_CLEAR(val)  bfin_write16(PORTEIO_CLEAR, val)
+#define bfin_read_PORTEIO_SET()        bfin_read16(PORTEIO_SET)
+#define bfin_write_PORTEIO_SET(val)    bfin_write16(PORTEIO_SET, val)
+#define bfin_read_PORTEIO_TOGGLE()     bfin_read16(PORTEIO_TOGGLE)
+#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
+#define bfin_read_PORTEIO_DIR()        bfin_read16(PORTEIO_DIR)
+#define bfin_write_PORTEIO_DIR(val)    bfin_write16(PORTEIO_DIR, val)
+#define bfin_read_PORTEIO_INEN()       bfin_read16(PORTEIO_INEN)
+#define bfin_write_PORTEIO_INEN(val)   bfin_write16(PORTEIO_INEN, val)
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+#define bfin_read_DMA0_TC_PER()        bfin_read16(DMA0_TC_PER)
+#define bfin_write_DMA0_TC_PER(val)    bfin_write16(DMA0_TC_PER, val)
+#define bfin_read_DMA0_TC_CNT()        bfin_read16(DMA0_TC_CNT)
+#define bfin_write_DMA0_TC_CNT(val)    bfin_write16(DMA0_TC_CNT, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
+#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
+#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
+#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
+#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
+#define bfin_read_MDMA0_D0_CONFIG()    bfin_read16(MDMA0_D0_CONFIG)
+#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
+#define bfin_read_MDMA0_D0_X_COUNT()   bfin_read16(MDMA0_D0_X_COUNT)
+#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
+#define bfin_read_MDMA0_D0_X_MODIFY()  bfin_read16(MDMA0_D0_X_MODIFY)
+#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
+#define bfin_read_MDMA0_D0_Y_COUNT()   bfin_read16(MDMA0_D0_Y_COUNT)
+#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
+#define bfin_read_MDMA0_D0_Y_MODIFY()  bfin_read16(MDMA0_D0_Y_MODIFY)
+#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
+#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
+#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
+#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
+#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
+#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
+#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
+#define bfin_read_MDMA0_S0_CONFIG()    bfin_read16(MDMA0_S0_CONFIG)
+#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
+#define bfin_read_MDMA0_S0_X_COUNT()   bfin_read16(MDMA0_S0_X_COUNT)
+#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
+#define bfin_read_MDMA0_S0_X_MODIFY()  bfin_read16(MDMA0_S0_X_MODIFY)
+#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
+#define bfin_read_MDMA0_S0_Y_COUNT()   bfin_read16(MDMA0_S0_Y_COUNT)
+#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
+#define bfin_read_MDMA0_S0_Y_MODIFY()  bfin_read16(MDMA0_S0_Y_MODIFY)
+#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
+#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
+#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
+#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
+#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
+#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
+#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
+#define bfin_read_MDMA0_D1_CONFIG()    bfin_read16(MDMA0_D1_CONFIG)
+#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
+#define bfin_read_MDMA0_D1_X_COUNT()   bfin_read16(MDMA0_D1_X_COUNT)
+#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
+#define bfin_read_MDMA0_D1_X_MODIFY()  bfin_read16(MDMA0_D1_X_MODIFY)
+#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
+#define bfin_read_MDMA0_D1_Y_COUNT()   bfin_read16(MDMA0_D1_Y_COUNT)
+#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
+#define bfin_read_MDMA0_D1_Y_MODIFY()  bfin_read16(MDMA0_D1_Y_MODIFY)
+#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
+#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
+#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
+#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
+#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
+#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
+#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
+#define bfin_read_MDMA0_S1_CONFIG()    bfin_read16(MDMA0_S1_CONFIG)
+#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
+#define bfin_read_MDMA0_S1_X_COUNT()   bfin_read16(MDMA0_S1_X_COUNT)
+#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
+#define bfin_read_MDMA0_S1_X_MODIFY()  bfin_read16(MDMA0_S1_X_MODIFY)
+#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
+#define bfin_read_MDMA0_S1_Y_COUNT()   bfin_read16(MDMA0_S1_Y_COUNT)
+#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
+#define bfin_read_MDMA0_S1_Y_MODIFY()  bfin_read16(MDMA0_S1_Y_MODIFY)
+#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
+#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
+#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
+#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
+#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
+#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
+#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
+#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
+#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
+#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
+#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
+#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
+#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
+#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
+#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
+#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
+#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
+#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
+#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
+#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
+#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
+#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
+#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
+#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
+#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
+#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
+#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
+#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
+#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
+#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
+#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
+#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
+#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
+#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
+#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
+#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
+#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
+#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
+#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
+#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
+#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
+#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
+#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
+#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
+#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
+#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
+#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
+#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
+#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
+#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
+#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
+#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
+#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
+#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
+#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
+#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
+#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
+#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
+#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
+#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
+#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
+#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
+#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
+#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
+#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
+#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
+#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
+#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
+#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
+#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
+#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define bfin_read_TWI0_SLAVE_CTRL()    bfin_read16(TWI0_SLAVE_CTRL)
+#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL()    bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
+#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
+#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
+#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
+#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
+#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
+#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
+#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
+#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
+#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
+#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
+#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
+#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
+#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
+#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
+#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
+#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
+#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
+#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
+#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
+#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
+#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
+#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
+#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
+#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
+#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
+#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
+#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
+#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
+#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
+#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
+#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
+#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
+#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
+#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
+#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
+#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
+#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
+#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
+#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
+#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
+#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
+#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
+#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
+#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
+#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
+#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
+#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
+#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
+#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
+#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
+#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
+#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
+#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
+#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
+#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
+#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
+#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
+#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
+#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
+#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
+#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
+#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
+#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
+#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
+#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
+#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
+#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
+#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
+#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
+#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
+#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
+#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
+#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
+#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
+#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
+#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
+#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
+#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
+#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
+#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
+#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
+#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
+#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
+#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
+#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
+#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
+#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
+#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
+#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
+#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
+#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
+#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
+#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
+#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
+#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
+#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
+#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
+#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
+#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
+#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
+#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
+#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
+#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
+#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
+#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
+#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
+#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
+#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
+#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
+#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
+#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
+#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
+#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
+#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
+#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
+#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
+#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
+#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
+#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
+#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
+#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
+#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
+#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
+#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
+#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
+#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
+#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
+#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
+#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
+#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
+#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
+#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
+#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
+#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
+#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
+#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
+#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
+#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
+#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
+#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
+#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
+#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
+#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
+#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
+#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
+#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
+#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
+#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
+#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
+#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
+#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
+#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
+#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
+#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
+#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
+#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
+#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
+#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
+#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
+#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
+#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
+#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
+#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
+#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
+#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
+#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
+#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
+#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
+#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
+#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
+#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
+#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
+#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
+#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
+#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
+#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
+#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
+#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
+#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
+#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
+#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
+#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
+#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
+#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
+#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
+#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
+#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
+#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
+#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
+#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
+#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
+#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
+#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
+#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
+#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
+#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
+#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
+#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
+#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
+#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
+#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
+#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
+#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
+#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
+#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
+#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
+#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
+#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
+#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
+#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
+#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
+#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
+#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
+#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
+#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
+#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
+#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
+#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
+#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
+#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
+#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
+#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
+#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
+#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
+#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
+#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
+#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
+#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
+#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
+#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
+#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
+#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
+#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
+#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
+#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
+#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
+#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
+#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
+#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
+#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
+#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
+#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
+#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
+#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
+#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
+#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
+#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
+#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
+#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
+#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
+#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
+#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
+#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
+#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
+#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
+#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
+#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
+#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
+#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
+#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
+#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
+#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
+#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
+#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
+#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
+#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
+#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
+#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
+#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
+#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
+#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
+#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
+#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
+#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
+#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
+#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
+#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
+#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
+#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
+#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
+#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
+#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
+#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
+#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
+#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
+#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
+#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
+#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
+#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
+#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
+#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
+#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
+#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
+#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
+#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
+#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
+#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
+#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
+#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
+#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
+#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
+#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
+#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
+#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
+#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
+#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
+#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
+#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
+#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
+#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
+#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
+#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
+#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
+#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
+#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
+#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
+#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
+#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
+#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
+#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
+#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
+#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
+#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
+#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
+#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
+#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
+#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
+#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
+#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
+#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
+#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
+#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
+#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
+#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
+#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
+#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
+#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
+#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
+#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
+#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
+#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
+#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
+#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
+#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
+#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
+#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
+#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
+#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
+#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
+#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
+#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
+#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
+#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
+#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
+#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
+#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
+#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
+#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
+#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
+#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
+#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
+#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
+#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
+#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
+#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
+#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
+#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
+#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
+#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
+#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
+#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
+#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
+#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
+#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
+#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
+#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
+#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
+#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
+#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
+#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
+#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
+#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
+#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
+#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
+#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
+#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
+#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
+#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
+#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
+#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
+#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
+#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
+#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
+#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
+#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
+#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
+#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
+#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
+#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
+#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
+#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
+#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
+#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
+#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
+#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
+#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
+#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
+#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
+#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
+#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
+#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
+#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
+#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
+#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
+#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
+#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
+#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
+#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
+#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
+#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
+#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
+#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
+#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
+#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
+#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
+#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
+#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
+#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
+#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
+#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
+#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
+#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
+#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
+#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
+#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
+#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
+#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
+#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
+#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
+#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
+#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
+#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
+#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
+#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
+#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
+#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
+#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
+#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
+#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
+#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
+#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
+#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
+#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
+#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
+#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
+#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
+#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
+#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
+#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
+#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
+#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
+#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
+#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
+#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
+#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
+#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
+#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
+#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
+#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
+#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
+#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
+#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
+#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
+#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
+#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
+#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
+#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
+#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
+#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
+#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
+#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
+#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
+#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
+#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
+#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
+#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
+#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
+#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
+#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
+#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
+#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
+#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
+#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
+#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
+#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
+#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
+#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
+#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
+#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
+#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
+#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
+#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
+#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
+#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
+#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
+#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
+#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
+#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
+#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
+#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
+#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
+#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
+#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
+#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
+#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
+#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
+#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
+#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
+#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
+#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
+#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
+#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
+#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
+#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
+#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
+#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
+#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
+#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
+#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
+#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
+#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
+#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
+#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
+#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
+#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
+#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
+#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
+#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
+#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
+#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
+#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
+#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
+#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
+#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
+#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
+#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
+#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
+#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
+#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
+#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
+#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
+#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
+#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
+#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
+#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
+#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
+#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
+#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
+#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
+#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
+#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
+#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
+#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
+#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
+#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
+#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
+#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
+#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
+#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
+#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
+#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
+#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
+#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
+#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
+#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
+#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
+#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
+#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
+#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
+#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
+#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
+#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
+#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
+#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
+#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
+#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
+#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
+#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
+#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
+#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
+#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
+#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
+#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
+#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
+#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
+#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
+#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
+#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
+#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
+#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
+#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
+#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
+#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
+#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
+#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
+#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
+#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
+#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
+#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
+#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
+#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
+#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
+#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
+#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
+#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
+#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
+#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
+#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
+#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
+#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
+#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
+#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
+#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
+#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
+#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
+#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
+#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
+#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
+#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
+#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
+#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
+#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
+#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
+#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
+#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
+#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
+#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
+#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
+#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
+#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
+#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
+#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
+#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
+#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
+#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
+#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
+#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
+#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
+#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
+#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
+#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
+#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
+#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
+#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
+#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
+#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
+#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
+#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
+#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
+#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
+#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
+#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
+#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
+#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
+#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
+#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
+#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
+#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
+#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
+#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
+#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
+#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
+#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
+#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
+#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
+#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
+#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
+#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
+#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
+#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
+#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
+#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
+#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
+#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
+#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
+#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
+#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
+#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
+#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
+#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
+#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
+#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
+#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
+#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
+#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
+#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
+#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
+#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
+#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
+#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
+#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
+#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
+#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
+#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
+#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
+#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
+#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
+#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
+#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
+#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
+#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
+#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
+#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
+#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
+#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
+#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
+#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
+#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
+#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
+#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
+#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
+#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
+#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
+#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
+#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
+#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
+#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
+#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
+#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
+
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
new file mode 100644
index 000000000000..198c4bbc8e5d
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
@@ -0,0 +1,240 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef _CDEF_BF539_H
+#define _CDEF_BF539_H
+
+/* Include MMRs Common to BF538                                                                 */
+#include "cdefBF538.h"
+
+
+#define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
+#define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
+#define bfin_read_MXVR_PLL_CTL_0()     bfin_read32(MXVR_PLL_CTL_0)
+#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
+#define bfin_read_MXVR_STATE_0()       bfin_read32(MXVR_STATE_0)
+#define bfin_write_MXVR_STATE_0(val)   bfin_write32(MXVR_STATE_0, val)
+#define bfin_read_MXVR_STATE_1()       bfin_read32(MXVR_STATE_1)
+#define bfin_write_MXVR_STATE_1(val)   bfin_write32(MXVR_STATE_1, val)
+#define bfin_read_MXVR_INT_STAT_0()    bfin_read32(MXVR_INT_STAT_0)
+#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
+#define bfin_read_MXVR_INT_STAT_1()    bfin_read32(MXVR_INT_STAT_1)
+#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
+#define bfin_read_MXVR_INT_EN_0()      bfin_read32(MXVR_INT_EN_0)
+#define bfin_write_MXVR_INT_EN_0(val)  bfin_write32(MXVR_INT_EN_0, val)
+#define bfin_read_MXVR_INT_EN_1()      bfin_read32(MXVR_INT_EN_1)
+#define bfin_write_MXVR_INT_EN_1(val)  bfin_write32(MXVR_INT_EN_1, val)
+#define bfin_read_MXVR_POSITION()      bfin_read16(MXVR_POSITION)
+#define bfin_write_MXVR_POSITION(val)  bfin_write16(MXVR_POSITION, val)
+#define bfin_read_MXVR_MAX_POSITION()  bfin_read16(MXVR_MAX_POSITION)
+#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
+#define bfin_read_MXVR_DELAY()         bfin_read16(MXVR_DELAY)
+#define bfin_write_MXVR_DELAY(val)     bfin_write16(MXVR_DELAY, val)
+#define bfin_read_MXVR_MAX_DELAY()     bfin_read16(MXVR_MAX_DELAY)
+#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
+#define bfin_read_MXVR_LADDR()         bfin_read32(MXVR_LADDR)
+#define bfin_write_MXVR_LADDR(val)     bfin_write32(MXVR_LADDR, val)
+#define bfin_read_MXVR_GADDR()         bfin_read16(MXVR_GADDR)
+#define bfin_write_MXVR_GADDR(val)     bfin_write16(MXVR_GADDR, val)
+#define bfin_read_MXVR_AADDR()         bfin_read32(MXVR_AADDR)
+#define bfin_write_MXVR_AADDR(val)     bfin_write32(MXVR_AADDR, val)
+#define bfin_read_MXVR_ALLOC_0()       bfin_read32(MXVR_ALLOC_0)
+#define bfin_write_MXVR_ALLOC_0(val)   bfin_write32(MXVR_ALLOC_0, val)
+#define bfin_read_MXVR_ALLOC_1()       bfin_read32(MXVR_ALLOC_1)
+#define bfin_write_MXVR_ALLOC_1(val)   bfin_write32(MXVR_ALLOC_1, val)
+#define bfin_read_MXVR_ALLOC_2()       bfin_read32(MXVR_ALLOC_2)
+#define bfin_write_MXVR_ALLOC_2(val)   bfin_write32(MXVR_ALLOC_2, val)
+#define bfin_read_MXVR_ALLOC_3()       bfin_read32(MXVR_ALLOC_3)
+#define bfin_write_MXVR_ALLOC_3(val)   bfin_write32(MXVR_ALLOC_3, val)
+#define bfin_read_MXVR_ALLOC_4()       bfin_read32(MXVR_ALLOC_4)
+#define bfin_write_MXVR_ALLOC_4(val)   bfin_write32(MXVR_ALLOC_4, val)
+#define bfin_read_MXVR_ALLOC_5()       bfin_read32(MXVR_ALLOC_5)
+#define bfin_write_MXVR_ALLOC_5(val)   bfin_write32(MXVR_ALLOC_5, val)
+#define bfin_read_MXVR_ALLOC_6()       bfin_read32(MXVR_ALLOC_6)
+#define bfin_write_MXVR_ALLOC_6(val)   bfin_write32(MXVR_ALLOC_6, val)
+#define bfin_read_MXVR_ALLOC_7()       bfin_read32(MXVR_ALLOC_7)
+#define bfin_write_MXVR_ALLOC_7(val)   bfin_write32(MXVR_ALLOC_7, val)
+#define bfin_read_MXVR_ALLOC_8()       bfin_read32(MXVR_ALLOC_8)
+#define bfin_write_MXVR_ALLOC_8(val)   bfin_write32(MXVR_ALLOC_8, val)
+#define bfin_read_MXVR_ALLOC_9()       bfin_read32(MXVR_ALLOC_9)
+#define bfin_write_MXVR_ALLOC_9(val)   bfin_write32(MXVR_ALLOC_9, val)
+#define bfin_read_MXVR_ALLOC_10()      bfin_read32(MXVR_ALLOC_10)
+#define bfin_write_MXVR_ALLOC_10(val)  bfin_write32(MXVR_ALLOC_10, val)
+#define bfin_read_MXVR_ALLOC_11()      bfin_read32(MXVR_ALLOC_11)
+#define bfin_write_MXVR_ALLOC_11(val)  bfin_write32(MXVR_ALLOC_11, val)
+#define bfin_read_MXVR_ALLOC_12()      bfin_read32(MXVR_ALLOC_12)
+#define bfin_write_MXVR_ALLOC_12(val)  bfin_write32(MXVR_ALLOC_12, val)
+#define bfin_read_MXVR_ALLOC_13()      bfin_read32(MXVR_ALLOC_13)
+#define bfin_write_MXVR_ALLOC_13(val)  bfin_write32(MXVR_ALLOC_13, val)
+#define bfin_read_MXVR_ALLOC_14()      bfin_read32(MXVR_ALLOC_14)
+#define bfin_write_MXVR_ALLOC_14(val)  bfin_write32(MXVR_ALLOC_14, val)
+#define bfin_read_MXVR_SYNC_LCHAN_0()  bfin_read32(MXVR_SYNC_LCHAN_0)
+#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
+#define bfin_read_MXVR_SYNC_LCHAN_1()  bfin_read32(MXVR_SYNC_LCHAN_1)
+#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
+#define bfin_read_MXVR_SYNC_LCHAN_2()  bfin_read32(MXVR_SYNC_LCHAN_2)
+#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
+#define bfin_read_MXVR_SYNC_LCHAN_3()  bfin_read32(MXVR_SYNC_LCHAN_3)
+#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
+#define bfin_read_MXVR_SYNC_LCHAN_4()  bfin_read32(MXVR_SYNC_LCHAN_4)
+#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
+#define bfin_read_MXVR_SYNC_LCHAN_5()  bfin_read32(MXVR_SYNC_LCHAN_5)
+#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
+#define bfin_read_MXVR_SYNC_LCHAN_6()  bfin_read32(MXVR_SYNC_LCHAN_6)
+#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
+#define bfin_read_MXVR_SYNC_LCHAN_7()  bfin_read32(MXVR_SYNC_LCHAN_7)
+#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
+#define bfin_read_MXVR_DMA0_CONFIG()   bfin_read32(MXVR_DMA0_CONFIG)
+#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
+#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
+#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
+#define bfin_read_MXVR_DMA0_COUNT()    bfin_read16(MXVR_DMA0_COUNT)
+#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
+#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
+#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
+#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA1_CONFIG()   bfin_read32(MXVR_DMA1_CONFIG)
+#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
+#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
+#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
+#define bfin_read_MXVR_DMA1_COUNT()    bfin_read16(MXVR_DMA1_COUNT)
+#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
+#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
+#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
+#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA2_CONFIG()   bfin_read32(MXVR_DMA2_CONFIG)
+#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
+#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
+#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
+#define bfin_read_MXVR_DMA2_COUNT()    bfin_read16(MXVR_DMA2_COUNT)
+#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
+#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
+#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
+#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA3_CONFIG()   bfin_read32(MXVR_DMA3_CONFIG)
+#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
+#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
+#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
+#define bfin_read_MXVR_DMA3_COUNT()    bfin_read16(MXVR_DMA3_COUNT)
+#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
+#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
+#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
+#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA4_CONFIG()   bfin_read32(MXVR_DMA4_CONFIG)
+#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
+#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
+#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
+#define bfin_read_MXVR_DMA4_COUNT()    bfin_read16(MXVR_DMA4_COUNT)
+#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
+#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
+#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
+#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA5_CONFIG()   bfin_read32(MXVR_DMA5_CONFIG)
+#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
+#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
+#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
+#define bfin_read_MXVR_DMA5_COUNT()    bfin_read16(MXVR_DMA5_COUNT)
+#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
+#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
+#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
+#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA6_CONFIG()   bfin_read32(MXVR_DMA6_CONFIG)
+#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
+#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
+#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
+#define bfin_read_MXVR_DMA6_COUNT()    bfin_read16(MXVR_DMA6_COUNT)
+#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
+#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
+#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
+#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
+#define bfin_read_MXVR_DMA7_CONFIG()   bfin_read32(MXVR_DMA7_CONFIG)
+#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
+#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
+#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
+#define bfin_read_MXVR_DMA7_COUNT()    bfin_read16(MXVR_DMA7_COUNT)
+#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
+#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
+#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
+#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
+#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
+#define bfin_read_MXVR_AP_CTL()        bfin_read16(MXVR_AP_CTL)
+#define bfin_write_MXVR_AP_CTL(val)    bfin_write16(MXVR_AP_CTL, val)
+#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
+#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
+#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
+#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
+#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
+#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
+#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
+#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
+#define bfin_read_MXVR_CM_CTL()        bfin_read32(MXVR_CM_CTL)
+#define bfin_write_MXVR_CM_CTL(val)    bfin_write32(MXVR_CM_CTL, val)
+#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
+#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
+#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
+#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
+#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
+#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
+#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
+#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
+#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
+#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
+#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
+#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
+#define bfin_read_MXVR_PAT_DATA_0()    bfin_read32(MXVR_PAT_DATA_0)
+#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
+#define bfin_read_MXVR_PAT_EN_0()      bfin_read32(MXVR_PAT_EN_0)
+#define bfin_write_MXVR_PAT_EN_0(val)  bfin_write32(MXVR_PAT_EN_0, val)
+#define bfin_read_MXVR_PAT_DATA_1()    bfin_read32(MXVR_PAT_DATA_1)
+#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
+#define bfin_read_MXVR_PAT_EN_1()      bfin_read32(MXVR_PAT_EN_1)
+#define bfin_write_MXVR_PAT_EN_1(val)  bfin_write32(MXVR_PAT_EN_1, val)
+#define bfin_read_MXVR_FRAME_CNT_0()   bfin_read16(MXVR_FRAME_CNT_0)
+#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
+#define bfin_read_MXVR_FRAME_CNT_1()   bfin_read16(MXVR_FRAME_CNT_1)
+#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
+#define bfin_read_MXVR_ROUTING_0()     bfin_read32(MXVR_ROUTING_0)
+#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
+#define bfin_read_MXVR_ROUTING_1()     bfin_read32(MXVR_ROUTING_1)
+#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
+#define bfin_read_MXVR_ROUTING_2()     bfin_read32(MXVR_ROUTING_2)
+#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
+#define bfin_read_MXVR_ROUTING_3()     bfin_read32(MXVR_ROUTING_3)
+#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
+#define bfin_read_MXVR_ROUTING_4()     bfin_read32(MXVR_ROUTING_4)
+#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
+#define bfin_read_MXVR_ROUTING_5()     bfin_read32(MXVR_ROUTING_5)
+#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
+#define bfin_read_MXVR_ROUTING_6()     bfin_read32(MXVR_ROUTING_6)
+#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
+#define bfin_read_MXVR_ROUTING_7()     bfin_read32(MXVR_ROUTING_7)
+#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
+#define bfin_read_MXVR_ROUTING_8()     bfin_read32(MXVR_ROUTING_8)
+#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
+#define bfin_read_MXVR_ROUTING_9()     bfin_read32(MXVR_ROUTING_9)
+#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
+#define bfin_read_MXVR_ROUTING_10()    bfin_read32(MXVR_ROUTING_10)
+#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
+#define bfin_read_MXVR_ROUTING_11()    bfin_read32(MXVR_ROUTING_11)
+#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
+#define bfin_read_MXVR_ROUTING_12()    bfin_read32(MXVR_ROUTING_12)
+#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
+#define bfin_read_MXVR_ROUTING_13()    bfin_read32(MXVR_ROUTING_13)
+#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
+#define bfin_read_MXVR_ROUTING_14()    bfin_read32(MXVR_ROUTING_14)
+#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
+#define bfin_read_MXVR_PLL_CTL_1()     bfin_read32(MXVR_PLL_CTL_1)
+#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
+#define bfin_read_MXVR_BLOCK_CNT()     bfin_read16(MXVR_BLOCK_CNT)
+#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
+
+#endif /* _CDEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
new file mode 100644
index 000000000000..6adbfcc65a35
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -0,0 +1,4243 @@
+/************************************************************************
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ ************************************************************************/
+/*
+ * File:         include/asm-blackfin/mach-bf538/defBF539.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */
+
+#ifndef _DEF_BF539_H
+#define _DEF_BF539_H
+
+/* include all Core registers and bit definitions */
+#include <asm/def_LPBlackfin.h>
+
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
+#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
+#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock     Count register (16-bit) */
+#define CHIPID                  0xFFC00014      /* Chip ID Register */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
+#define SYSCR                   0xFFC00104  /* System Configuration registe */
+#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register */
+#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3 */
+#define SIC_ISR0                        0xFFC00120  /* Interrupt Status Register */
+#define SIC_IWR0                        0xFFC00124  /* Interrupt Wakeup Register */
+#define SIC_IMASK1                      0xFFC00128      /* Interrupt Mask Register 1 */
+#define SIC_ISR1                        0xFFC0012C      /* Interrupt Status Register 1 */
+#define SIC_IWR1                        0xFFC00130      /* Interrupt Wakeup Register 1 */
+#define SIC_IAR4                        0xFFC00134      /* Interrupt Assignment Register 4 */
+#define SIC_IAR5                        0xFFC00138      /* Interrupt Assignment Register 5 */
+#define SIC_IAR6                        0xFFC0013C      /* Interrupt Assignment Register 6 */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
+#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
+#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT        0xFFC00300  /* RTC Status Register */
+#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
+#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
+#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
+#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
+#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
+#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR             0xFFC00400  /* Transmit Holding register */
+#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
+#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
+#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
+#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
+#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
+#define UART0_LCR             0xFFC0040C  /* Line Control Register */
+#define UART0_MCR                        0xFFC00410  /* Modem Control Register */
+#define UART0_LSR             0xFFC00414  /* Line Status Register */
+#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
+#define UART0_GCTL                   0xFFC00424  /* Global Control Register */
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
+
+#define SPI0_CTL                        0xFFC00500  /* SPI0 Control Register */
+#define SPI0_FLG                        0xFFC00504  /* SPI0 Flag register */
+#define SPI0_STAT                       0xFFC00508  /* SPI0 Status register */
+#define SPI0_TDBR                       0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                       0xFFC00510  /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                       0xFFC00514  /* SPI0 Baud rate Register */
+#define SPI0_SHADOW                     0xFFC00518  /* SPI0_RDBR Shadow Register */
+#define SPI0_REGBASE                    SPI0_CTL
+
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
+#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
+#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
+#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
+#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
+
+#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
+#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
+#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
+#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
+
+#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
+#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
+#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
+
+
+/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
+#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
+#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
+#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
+#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
+#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
+#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
+#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
+#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+/* Asynchronous Memory Controller  */
+#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller */
+#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
+
+
+
+/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+
+#define DMAC0_TC_PER                    0xFFC00B0C      /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TC_CNT                    0xFFC00B10      /* DMA Controller 0 Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA0_TCPER                      DMAC0_TC_PER
+#define DMA0_TCCNT                      DMAC0_TC_CNT
+
+
+/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)                                                    */
+
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
+
+#define MDMA0_D0_NEXT_DESC_PTR  0xFFC00E00      /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA0_D0_START_ADDR             0xFFC00E04      /* MemDMA0 Stream 0 Destination Start Address Register */
+#define MDMA0_D0_CONFIG                 0xFFC00E08      /* MemDMA0 Stream 0 Destination Configuration Register */
+#define MDMA0_D0_X_COUNT                0xFFC00E10      /* MemDMA0 Stream 0 Destination X Count Register */
+#define MDMA0_D0_X_MODIFY               0xFFC00E14      /* MemDMA0 Stream 0 Destination X Modify Register */
+#define MDMA0_D0_Y_COUNT                0xFFC00E18      /* MemDMA0 Stream 0 Destination Y Count Register */
+#define MDMA0_D0_Y_MODIFY               0xFFC00E1C      /* MemDMA0 Stream 0 Destination Y Modify Register */
+#define MDMA0_D0_CURR_DESC_PTR  0xFFC00E20      /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA0_D0_CURR_ADDR              0xFFC00E24      /* MemDMA0 Stream 0 Destination Current Address Register */
+#define MDMA0_D0_IRQ_STATUS             0xFFC00E28      /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
+#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C      /* MemDMA0 Stream 0 Destination Peripheral Map Register */
+#define MDMA0_D0_CURR_X_COUNT   0xFFC00E30      /* MemDMA0 Stream 0 Destination Current X Count Register */
+#define MDMA0_D0_CURR_Y_COUNT   0xFFC00E38      /* MemDMA0 Stream 0 Destination Current Y Count Register */
+
+#define MDMA0_S0_NEXT_DESC_PTR  0xFFC00E40      /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA0_S0_START_ADDR             0xFFC00E44      /* MemDMA0 Stream 0 Source Start Address Register */
+#define MDMA0_S0_CONFIG                 0xFFC00E48      /* MemDMA0 Stream 0 Source Configuration Register */
+#define MDMA0_S0_X_COUNT                0xFFC00E50      /* MemDMA0 Stream 0 Source X Count Register */
+#define MDMA0_S0_X_MODIFY               0xFFC00E54      /* MemDMA0 Stream 0 Source X Modify Register */
+#define MDMA0_S0_Y_COUNT                0xFFC00E58      /* MemDMA0 Stream 0 Source Y Count Register */
+#define MDMA0_S0_Y_MODIFY               0xFFC00E5C      /* MemDMA0 Stream 0 Source Y Modify Register */
+#define MDMA0_S0_CURR_DESC_PTR  0xFFC00E60      /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA0_S0_CURR_ADDR              0xFFC00E64      /* MemDMA0 Stream 0 Source Current Address Register */
+#define MDMA0_S0_IRQ_STATUS             0xFFC00E68      /* MemDMA0 Stream 0 Source Interrupt/Status Register */
+#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C      /* MemDMA0 Stream 0 Source Peripheral Map Register */
+#define MDMA0_S0_CURR_X_COUNT   0xFFC00E70      /* MemDMA0 Stream 0 Source Current X Count Register */
+#define MDMA0_S0_CURR_Y_COUNT   0xFFC00E78      /* MemDMA0 Stream 0 Source Current Y Count Register */
+
+#define MDMA0_D1_NEXT_DESC_PTR  0xFFC00E80      /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA0_D1_START_ADDR             0xFFC00E84      /* MemDMA0 Stream 1 Destination Start Address Register */
+#define MDMA0_D1_CONFIG                 0xFFC00E88      /* MemDMA0 Stream 1 Destination Configuration Register */
+#define MDMA0_D1_X_COUNT                0xFFC00E90      /* MemDMA0 Stream 1 Destination X Count Register */
+#define MDMA0_D1_X_MODIFY               0xFFC00E94      /* MemDMA0 Stream 1 Destination X Modify Register */
+#define MDMA0_D1_Y_COUNT                0xFFC00E98      /* MemDMA0 Stream 1 Destination Y Count Register */
+#define MDMA0_D1_Y_MODIFY               0xFFC00E9C      /* MemDMA0 Stream 1 Destination Y Modify Register */
+#define MDMA0_D1_CURR_DESC_PTR  0xFFC00EA0      /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA0_D1_CURR_ADDR              0xFFC00EA4      /* MemDMA0 Stream 1 Destination Current Address Register */
+#define MDMA0_D1_IRQ_STATUS             0xFFC00EA8      /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
+#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC      /* MemDMA0 Stream 1 Destination Peripheral Map Register */
+#define MDMA0_D1_CURR_X_COUNT   0xFFC00EB0      /* MemDMA0 Stream 1 Destination Current X Count Register */
+#define MDMA0_D1_CURR_Y_COUNT   0xFFC00EB8      /* MemDMA0 Stream 1 Destination Current Y Count Register */
+
+#define MDMA0_S1_NEXT_DESC_PTR  0xFFC00EC0      /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA0_S1_START_ADDR             0xFFC00EC4      /* MemDMA0 Stream 1 Source Start Address Register */
+#define MDMA0_S1_CONFIG                 0xFFC00EC8      /* MemDMA0 Stream 1 Source Configuration Register */
+#define MDMA0_S1_X_COUNT                0xFFC00ED0      /* MemDMA0 Stream 1 Source X Count Register */
+#define MDMA0_S1_X_MODIFY               0xFFC00ED4      /* MemDMA0 Stream 1 Source X Modify Register */
+#define MDMA0_S1_Y_COUNT                0xFFC00ED8      /* MemDMA0 Stream 1 Source Y Count Register */
+#define MDMA0_S1_Y_MODIFY               0xFFC00EDC      /* MemDMA0 Stream 1 Source Y Modify Register */
+#define MDMA0_S1_CURR_DESC_PTR  0xFFC00EE0      /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA0_S1_CURR_ADDR              0xFFC00EE4      /* MemDMA0 Stream 1 Source Current Address Register */
+#define MDMA0_S1_IRQ_STATUS             0xFFC00EE8      /* MemDMA0 Stream 1 Source Interrupt/Status Register */
+#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC      /* MemDMA0 Stream 1 Source Peripheral Map Register */
+#define MDMA0_S1_CURR_X_COUNT   0xFFC00EF0      /* MemDMA0 Stream 1 Source Current X Count Register */
+#define MDMA0_S1_CURR_Y_COUNT   0xFFC00EF8      /* MemDMA0 Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF)                        */
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
+#define TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTRL         0xFFC01408      /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
+#define TWI0_MASTER_CTRL        0xFFC01414      /* Master Mode Control Register */
+#define TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
+#define TWI0_FIFO_CTRL          0xFFC01428      /* FIFO Control Register */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register */
+
+#define TWI0_REGBASE            TWI0_CLKDIV
+
+/* the following are for backwards compatibility */
+#define TWI0_PRESCALE    TWI0_CONTROL
+#define TWI0_INT_SRC     TWI0_INT_STAT
+#define TWI0_INT_ENABLE  TWI0_INT_MASK
+
+
+/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
+
+/* GPIO Port C Register Names */
+#define GPIO_C_CNFG                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
+#define GPIO_C_D                        0xFFC01510      /* GPIO Pin Port C Data Register */
+#define GPIO_C_C                        0xFFC01520      /* Clear GPIO Pin Port C Register */
+#define GPIO_C_S                        0xFFC01530      /* Set GPIO Pin Port C Register */
+#define GPIO_C_T                        0xFFC01540      /* Toggle GPIO Pin Port C Register */
+#define GPIO_C_DIR                      0xFFC01550      /* GPIO Pin Port C Direction Register */
+#define GPIO_C_INEN                     0xFFC01560      /* GPIO Pin Port C Input Enable Register */
+
+/* GPIO Port D Register Names */
+#define GPIO_D_CNFG                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
+#define GPIO_D_D                        0xFFC01514      /* GPIO Pin Port D Data Register */
+#define GPIO_D_C                        0xFFC01524      /* Clear GPIO Pin Port D Register */
+#define GPIO_D_S                        0xFFC01534      /* Set GPIO Pin Port D Register */
+#define GPIO_D_T                        0xFFC01544      /* Toggle GPIO Pin Port D Register */
+#define GPIO_D_DIR                      0xFFC01554      /* GPIO Pin Port D Direction Register */
+#define GPIO_D_INEN                     0xFFC01564      /* GPIO Pin Port D Input Enable Register */
+
+/* GPIO Port E Register Names */
+#define GPIO_E_CNFG                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
+#define GPIO_E_D                        0xFFC01518      /* GPIO Pin Port E Data Register */
+#define GPIO_E_C                        0xFFC01528      /* Clear GPIO Pin Port E Register */
+#define GPIO_E_S                        0xFFC01538      /* Set GPIO Pin Port E Register */
+#define GPIO_E_T                        0xFFC01548      /* Toggle GPIO Pin Port E Register */
+#define GPIO_E_DIR                      0xFFC01558      /* GPIO Pin Port E Direction Register */
+#define GPIO_E_INEN                     0xFFC01568      /* GPIO Pin Port E Input Enable Register */
+
+/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
+
+#define DMAC1_TC_PER                    0xFFC01B0C      /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TC_CNT                    0xFFC01B10      /* DMA Controller 1 Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA1_TCPER                      DMAC1_TC_PER
+#define DMA1_TCCNT                      DMAC1_TC_CNT
+
+
+/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)                                                    */
+#define DMA8_NEXT_DESC_PTR              0xFFC01C00      /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                 0xFFC01C04      /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                             0xFFC01C08      /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                    0xFFC01C10      /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                   0xFFC01C14      /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                    0xFFC01C18      /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                   0xFFC01C1C      /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR              0xFFC01C20      /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                  0xFFC01C24      /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                 0xFFC01C28      /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP             0xFFC01C2C      /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT               0xFFC01C30      /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT               0xFFC01C38      /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC01C40      /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                 0xFFC01C44      /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                             0xFFC01C48      /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                    0xFFC01C50      /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                   0xFFC01C54      /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                    0xFFC01C58      /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                   0xFFC01C5C      /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR              0xFFC01C60      /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                  0xFFC01C64      /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                 0xFFC01C68      /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP             0xFFC01C6C      /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT               0xFFC01C70      /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT               0xFFC01C78      /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC01C80      /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR                0xFFC01C84      /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                    0xFFC01C88      /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                   0xFFC01C90      /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                  0xFFC01C94      /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                   0xFFC01C98      /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                  0xFFC01C9C      /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR             0xFFC01CA0      /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                 0xFFC01CA4      /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS                0xFFC01CA8      /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP    0xFFC01CAC      /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT              0xFFC01CB0      /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT              0xFFC01CB8      /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC01CC0      /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR                0xFFC01CC4      /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                    0xFFC01CC8      /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                   0xFFC01CD0      /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                  0xFFC01CD4      /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                   0xFFC01CD8      /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                  0xFFC01CDC      /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR             0xFFC01CE0      /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                 0xFFC01CE4      /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS                0xFFC01CE8      /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP    0xFFC01CEC      /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT              0xFFC01CF0      /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT              0xFFC01CF8      /* DMA Channel 11 Current Y Count Register */
+
+#define DMA12_NEXT_DESC_PTR             0xFFC01D00      /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR                0xFFC01D04      /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                    0xFFC01D08      /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                   0xFFC01D10      /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                  0xFFC01D14      /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                   0xFFC01D18      /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                  0xFFC01D1C      /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR             0xFFC01D20      /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                 0xFFC01D24      /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS                0xFFC01D28      /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP    0xFFC01D2C      /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT              0xFFC01D30      /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT              0xFFC01D38      /* DMA Channel 12 Current Y Count Register */
+
+#define DMA13_NEXT_DESC_PTR             0xFFC01D40      /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR                0xFFC01D44      /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                    0xFFC01D48      /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                   0xFFC01D50      /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                  0xFFC01D54      /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                   0xFFC01D58      /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                  0xFFC01D5C      /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR             0xFFC01D60      /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                 0xFFC01D64      /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS                0xFFC01D68      /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP    0xFFC01D6C      /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT              0xFFC01D70      /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT              0xFFC01D78      /* DMA Channel 13 Current Y Count Register */
+
+#define DMA14_NEXT_DESC_PTR             0xFFC01D80      /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR                0xFFC01D84      /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                    0xFFC01D88      /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                   0xFFC01D90      /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                  0xFFC01D94      /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                   0xFFC01D98      /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                  0xFFC01D9C      /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR             0xFFC01DA0      /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                 0xFFC01DA4      /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS                0xFFC01DA8      /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP    0xFFC01DAC      /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT              0xFFC01DB0      /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT              0xFFC01DB8      /* DMA Channel 14 Current Y Count Register */
+
+#define DMA15_NEXT_DESC_PTR             0xFFC01DC0      /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR                0xFFC01DC4      /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                    0xFFC01DC8      /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                   0xFFC01DD0      /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                  0xFFC01DD4      /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                   0xFFC01DD8      /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                  0xFFC01DDC      /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR             0xFFC01DE0      /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                 0xFFC01DE4      /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS                0xFFC01DE8      /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP    0xFFC01DEC      /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT              0xFFC01DF0      /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT              0xFFC01DF8      /* DMA Channel 15 Current Y Count Register */
+
+#define DMA16_NEXT_DESC_PTR             0xFFC01E00      /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR                0xFFC01E04      /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                    0xFFC01E08      /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                   0xFFC01E10      /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                  0xFFC01E14      /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                   0xFFC01E18      /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                  0xFFC01E1C      /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR             0xFFC01E20      /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                 0xFFC01E24      /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS                0xFFC01E28      /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP    0xFFC01E2C      /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT              0xFFC01E30      /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT              0xFFC01E38      /* DMA Channel 16 Current Y Count Register */
+
+#define DMA17_NEXT_DESC_PTR             0xFFC01E40      /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR                0xFFC01E44      /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                    0xFFC01E48      /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                   0xFFC01E50      /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                  0xFFC01E54      /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                   0xFFC01E58      /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                  0xFFC01E5C      /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR             0xFFC01E60      /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                 0xFFC01E64      /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS                0xFFC01E68      /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP    0xFFC01E6C      /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT              0xFFC01E70      /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT              0xFFC01E78      /* DMA Channel 17 Current Y Count Register */
+
+#define DMA18_NEXT_DESC_PTR             0xFFC01E80      /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR                0xFFC01E84      /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                    0xFFC01E88      /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                   0xFFC01E90      /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                  0xFFC01E94      /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                   0xFFC01E98      /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                  0xFFC01E9C      /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR             0xFFC01EA0      /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                 0xFFC01EA4      /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS                0xFFC01EA8      /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP    0xFFC01EAC      /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT              0xFFC01EB0      /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT              0xFFC01EB8      /* DMA Channel 18 Current Y Count Register */
+
+#define DMA19_NEXT_DESC_PTR             0xFFC01EC0      /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR                0xFFC01EC4      /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                    0xFFC01EC8      /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                   0xFFC01ED0      /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                  0xFFC01ED4      /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                   0xFFC01ED8      /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                  0xFFC01EDC      /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR             0xFFC01EE0      /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                 0xFFC01EE4      /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS                0xFFC01EE8      /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP    0xFFC01EEC      /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT              0xFFC01EF0      /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT              0xFFC01EF8      /* DMA Channel 19 Current Y Count Register */
+
+#define MDMA1_D0_NEXT_DESC_PTR  0xFFC01F00      /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA1_D0_START_ADDR             0xFFC01F04      /* MemDMA1 Stream 0 Destination Start Address Register */
+#define MDMA1_D0_CONFIG                 0xFFC01F08      /* MemDMA1 Stream 0 Destination Configuration Register */
+#define MDMA1_D0_X_COUNT                0xFFC01F10      /* MemDMA1 Stream 0 Destination X Count Register */
+#define MDMA1_D0_X_MODIFY               0xFFC01F14      /* MemDMA1 Stream 0 Destination X Modify Register */
+#define MDMA1_D0_Y_COUNT                0xFFC01F18      /* MemDMA1 Stream 0 Destination Y Count Register */
+#define MDMA1_D0_Y_MODIFY               0xFFC01F1C      /* MemDMA1 Stream 0 Destination Y Modify Register */
+#define MDMA1_D0_CURR_DESC_PTR  0xFFC01F20      /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA1_D0_CURR_ADDR              0xFFC01F24      /* MemDMA1 Stream 0 Destination Current Address Register */
+#define MDMA1_D0_IRQ_STATUS             0xFFC01F28      /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /* MemDMA1 Stream 0 Destination Peripheral Map Register */
+#define MDMA1_D0_CURR_X_COUNT   0xFFC01F30      /* MemDMA1 Stream 0 Destination Current X Count Register */
+#define MDMA1_D0_CURR_Y_COUNT   0xFFC01F38      /* MemDMA1 Stream 0 Destination Current Y Count Register */
+
+#define MDMA1_S0_NEXT_DESC_PTR  0xFFC01F40      /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA1_S0_START_ADDR             0xFFC01F44      /* MemDMA1 Stream 0 Source Start Address Register */
+#define MDMA1_S0_CONFIG                 0xFFC01F48      /* MemDMA1 Stream 0 Source Configuration Register */
+#define MDMA1_S0_X_COUNT                0xFFC01F50      /* MemDMA1 Stream 0 Source X Count Register */
+#define MDMA1_S0_X_MODIFY               0xFFC01F54      /* MemDMA1 Stream 0 Source X Modify Register */
+#define MDMA1_S0_Y_COUNT                0xFFC01F58      /* MemDMA1 Stream 0 Source Y Count Register */
+#define MDMA1_S0_Y_MODIFY               0xFFC01F5C      /* MemDMA1 Stream 0 Source Y Modify Register */
+#define MDMA1_S0_CURR_DESC_PTR  0xFFC01F60      /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA1_S0_CURR_ADDR              0xFFC01F64      /* MemDMA1 Stream 0 Source Current Address Register */
+#define MDMA1_S0_IRQ_STATUS             0xFFC01F68      /* MemDMA1 Stream 0 Source Interrupt/Status Register */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /* MemDMA1 Stream 0 Source Peripheral Map Register */
+#define MDMA1_S0_CURR_X_COUNT   0xFFC01F70      /* MemDMA1 Stream 0 Source Current X Count Register */
+#define MDMA1_S0_CURR_Y_COUNT   0xFFC01F78      /* MemDMA1 Stream 0 Source Current Y Count Register */
+
+#define MDMA1_D1_NEXT_DESC_PTR  0xFFC01F80      /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA1_D1_START_ADDR             0xFFC01F84      /* MemDMA1 Stream 1 Destination Start Address Register */
+#define MDMA1_D1_CONFIG                 0xFFC01F88      /* MemDMA1 Stream 1 Destination Configuration Register */
+#define MDMA1_D1_X_COUNT                0xFFC01F90      /* MemDMA1 Stream 1 Destination X Count Register */
+#define MDMA1_D1_X_MODIFY               0xFFC01F94      /* MemDMA1 Stream 1 Destination X Modify Register */
+#define MDMA1_D1_Y_COUNT                0xFFC01F98      /* MemDMA1 Stream 1 Destination Y Count Register */
+#define MDMA1_D1_Y_MODIFY               0xFFC01F9C      /* MemDMA1 Stream 1 Destination Y Modify Register */
+#define MDMA1_D1_CURR_DESC_PTR  0xFFC01FA0      /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA1_D1_CURR_ADDR              0xFFC01FA4      /* MemDMA1 Stream 1 Destination Current Address Register */
+#define MDMA1_D1_IRQ_STATUS             0xFFC01FA8      /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /* MemDMA1 Stream 1 Destination Peripheral Map Register */
+#define MDMA1_D1_CURR_X_COUNT   0xFFC01FB0      /* MemDMA1 Stream 1 Destination Current X Count Register */
+#define MDMA1_D1_CURR_Y_COUNT   0xFFC01FB8      /* MemDMA1 Stream 1 Destination Current Y Count Register */
+
+#define MDMA1_S1_NEXT_DESC_PTR  0xFFC01FC0      /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA1_S1_START_ADDR             0xFFC01FC4      /* MemDMA1 Stream 1 Source Start Address Register */
+#define MDMA1_S1_CONFIG                 0xFFC01FC8      /* MemDMA1 Stream 1 Source Configuration Register */
+#define MDMA1_S1_X_COUNT                0xFFC01FD0      /* MemDMA1 Stream 1 Source X Count Register */
+#define MDMA1_S1_X_MODIFY               0xFFC01FD4      /* MemDMA1 Stream 1 Source X Modify Register */
+#define MDMA1_S1_Y_COUNT                0xFFC01FD8      /* MemDMA1 Stream 1 Source Y Count Register */
+#define MDMA1_S1_Y_MODIFY               0xFFC01FDC      /* MemDMA1 Stream 1 Source Y Modify Register */
+#define MDMA1_S1_CURR_DESC_PTR  0xFFC01FE0      /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA1_S1_CURR_ADDR              0xFFC01FE4      /* MemDMA1 Stream 1 Source Current Address Register */
+#define MDMA1_S1_IRQ_STATUS             0xFFC01FE8      /* MemDMA1 Stream 1 Source Interrupt/Status Register */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /* MemDMA1 Stream 1 Source Peripheral Map Register */
+#define MDMA1_S1_CURR_X_COUNT   0xFFC01FF0      /* MemDMA1 Stream 1 Source Current X Count Register */
+#define MDMA1_S1_CURR_Y_COUNT   0xFFC01FF8      /* MemDMA1 Stream 1 Source Current Y Count Register */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)        */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte) */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte) */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register */
+
+
+/* UART2 Controller             (0xFFC02100 - 0xFFC021FF)        */
+#define UART2_THR                       0xFFC02100      /* Transmit Holding register */
+#define UART2_RBR                       0xFFC02100      /* Receive Buffer register */
+#define UART2_DLL                       0xFFC02100      /* Divisor Latch (Low-Byte) */
+#define UART2_IER                       0xFFC02104      /* Interrupt Enable Register */
+#define UART2_DLH                       0xFFC02104      /* Divisor Latch (High-Byte) */
+#define UART2_IIR                       0xFFC02108      /* Interrupt Identification Register */
+#define UART2_LCR                       0xFFC0210C      /* Line Control Register */
+#define UART2_MCR                       0xFFC02110      /* Modem Control Register */
+#define UART2_LSR                       0xFFC02114      /* Line Status Register */
+#define UART2_SCR                       0xFFC0211C      /* SCR Scratch Register */
+#define UART2_GCTL                      0xFFC02124      /* Global Control Register */
+
+
+/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF)                        */
+#define TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
+#define TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTRL         0xFFC02208      /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
+#define TWI1_MASTER_CTRL        0xFFC02214      /* Master Mode Control Register */
+#define TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
+#define TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTRL          0xFFC02228      /* FIFO Control Register */
+#define TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
+#define TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8          0xFFC02288      /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16         0xFFC0228C      /* FIFO Receive Data Double Byte Register */
+#define TWI1_REGBASE            TWI1_CLKDIV
+
+
+/* the following are for backwards compatibility */
+#define TWI1_PRESCALE     TWI1_CONTROL
+#define TWI1_INT_SRC      TWI1_INT_STAT
+#define TWI1_INT_ENABLE   TWI1_INT_MASK
+
+
+/* SPI1 Controller              (0xFFC02300 - 0xFFC023FF)        */
+#define SPI1_CTL                        0xFFC02300  /* SPI1 Control Register */
+#define SPI1_FLG                        0xFFC02304  /* SPI1 Flag register */
+#define SPI1_STAT                       0xFFC02308  /* SPI1 Status register */
+#define SPI1_TDBR                       0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                       0xFFC02310  /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                       0xFFC02314  /* SPI1 Baud rate Register */
+#define SPI1_SHADOW                     0xFFC02318  /* SPI1_RDBR Shadow Register */
+#define SPI1_REGBASE                    SPI1_CTL
+
+/* SPI2 Controller              (0xFFC02400 - 0xFFC024FF)        */
+#define SPI2_CTL                        0xFFC02400  /* SPI2 Control Register */
+#define SPI2_FLG                        0xFFC02404  /* SPI2 Flag register */
+#define SPI2_STAT                       0xFFC02408  /* SPI2 Status register */
+#define SPI2_TDBR                       0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                       0xFFC02410  /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                       0xFFC02414  /* SPI2 Baud rate Register */
+#define SPI2_SHADOW                     0xFFC02418  /* SPI2_RDBR Shadow Register */
+#define SPI2_REGBASE                    SPI2_CTL
+
+/* SPORT2 Controller            (0xFFC02500 - 0xFFC025FF)                        */
+#define SPORT2_TCR1                     0xFFC02500      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                     0xFFC02504      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV          0xFFC02508      /* SPORT2 Transmit Clock Divider */
+#define SPORT2_TFSDIV           0xFFC0250C      /* SPORT2 Transmit Frame Sync Divider */
+#define SPORT2_TX                       0xFFC02510      /* SPORT2 TX Data Register */
+#define SPORT2_RX                       0xFFC02518      /* SPORT2 RX Data Register */
+#define SPORT2_RCR1                     0xFFC02520      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_RCR2                     0xFFC02524      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_RCLKDIV          0xFFC02528      /* SPORT2 Receive Clock Divider */
+#define SPORT2_RFSDIV           0xFFC0252C      /* SPORT2 Receive Frame Sync Divider */
+#define SPORT2_STAT                     0xFFC02530      /* SPORT2 Status Register */
+#define SPORT2_CHNL                     0xFFC02534      /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1            0xFFC02538      /* SPORT2 Multi-Channel Configuration Register 1 */
+#define SPORT2_MCMC2            0xFFC0253C      /* SPORT2 Multi-Channel Configuration Register 2 */
+#define SPORT2_MTCS0            0xFFC02540      /* SPORT2 Multi-Channel Transmit Select Register 0 */
+#define SPORT2_MTCS1            0xFFC02544      /* SPORT2 Multi-Channel Transmit Select Register 1 */
+#define SPORT2_MTCS2            0xFFC02548      /* SPORT2 Multi-Channel Transmit Select Register 2 */
+#define SPORT2_MTCS3            0xFFC0254C      /* SPORT2 Multi-Channel Transmit Select Register 3 */
+#define SPORT2_MRCS0            0xFFC02550      /* SPORT2 Multi-Channel Receive Select Register 0 */
+#define SPORT2_MRCS1            0xFFC02554      /* SPORT2 Multi-Channel Receive Select Register 1 */
+#define SPORT2_MRCS2            0xFFC02558      /* SPORT2 Multi-Channel Receive Select Register 2 */
+#define SPORT2_MRCS3            0xFFC0255C      /* SPORT2 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT3 Controller            (0xFFC02600 - 0xFFC026FF)                        */
+#define SPORT3_TCR1                     0xFFC02600      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                     0xFFC02604      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV          0xFFC02608      /* SPORT3 Transmit Clock Divider */
+#define SPORT3_TFSDIV           0xFFC0260C      /* SPORT3 Transmit Frame Sync Divider */
+#define SPORT3_TX                       0xFFC02610      /* SPORT3 TX Data Register */
+#define SPORT3_RX                       0xFFC02618      /* SPORT3 RX Data Register */
+#define SPORT3_RCR1                     0xFFC02620      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_RCR2                     0xFFC02624      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_RCLKDIV          0xFFC02628      /* SPORT3 Receive Clock Divider */
+#define SPORT3_RFSDIV           0xFFC0262C      /* SPORT3 Receive Frame Sync Divider */
+#define SPORT3_STAT                     0xFFC02630      /* SPORT3 Status Register */
+#define SPORT3_CHNL                     0xFFC02634      /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1            0xFFC02638      /* SPORT3 Multi-Channel Configuration Register 1 */
+#define SPORT3_MCMC2            0xFFC0263C      /* SPORT3 Multi-Channel Configuration Register 2 */
+#define SPORT3_MTCS0            0xFFC02640      /* SPORT3 Multi-Channel Transmit Select Register 0 */
+#define SPORT3_MTCS1            0xFFC02644      /* SPORT3 Multi-Channel Transmit Select Register 1 */
+#define SPORT3_MTCS2            0xFFC02648      /* SPORT3 Multi-Channel Transmit Select Register 2 */
+#define SPORT3_MTCS3            0xFFC0264C      /* SPORT3 Multi-Channel Transmit Select Register 3 */
+#define SPORT3_MRCS0            0xFFC02650      /* SPORT3 Multi-Channel Receive Select Register 0 */
+#define SPORT3_MRCS1            0xFFC02654      /* SPORT3 Multi-Channel Receive Select Register 1 */
+#define SPORT3_MRCS2            0xFFC02658      /* SPORT3 Multi-Channel Receive Select Register 2 */
+#define SPORT3_MRCS3            0xFFC0265C      /* SPORT3 Multi-Channel Receive Select Register 3 */
+
+
+/* Media Transceiver (MXVR)   (0xFFC02700 - 0xFFC028FF) */
+
+#define MXVR_CONFIG           0xFFC02700  /* MXVR Configuration Register */
+#define MXVR_PLL_CTL_0        0xFFC02704  /* MXVR Phase Lock Loop Control Register 0 */
+
+#define MXVR_STATE_0          0xFFC02708  /* MXVR State Register 0 */
+#define MXVR_STATE_1          0xFFC0270C  /* MXVR State Register 1 */
+
+#define MXVR_INT_STAT_0       0xFFC02710  /* MXVR Interrupt Status Register 0 */
+#define MXVR_INT_STAT_1       0xFFC02714  /* MXVR Interrupt Status Register 1 */
+
+#define MXVR_INT_EN_0         0xFFC02718  /* MXVR Interrupt Enable Register 0 */
+#define MXVR_INT_EN_1         0xFFC0271C  /* MXVR Interrupt Enable Register 1 */
+
+#define MXVR_POSITION         0xFFC02720  /* MXVR Node Position Register */
+#define MXVR_MAX_POSITION     0xFFC02724  /* MXVR Maximum Node Position Register */
+
+#define MXVR_DELAY            0xFFC02728  /* MXVR Node Frame Delay Register */
+#define MXVR_MAX_DELAY        0xFFC0272C  /* MXVR Maximum Node Frame Delay Register */
+
+#define MXVR_LADDR            0xFFC02730  /* MXVR Logical Address Register */
+#define MXVR_GADDR            0xFFC02734  /* MXVR Group Address Register */
+#define MXVR_AADDR            0xFFC02738  /* MXVR Alternate Address Register */
+
+#define MXVR_ALLOC_0          0xFFC0273C  /* MXVR Allocation Table Register 0 */
+#define MXVR_ALLOC_1          0xFFC02740  /* MXVR Allocation Table Register 1 */
+#define MXVR_ALLOC_2          0xFFC02744  /* MXVR Allocation Table Register 2 */
+#define MXVR_ALLOC_3          0xFFC02748  /* MXVR Allocation Table Register 3 */
+#define MXVR_ALLOC_4          0xFFC0274C  /* MXVR Allocation Table Register 4 */
+#define MXVR_ALLOC_5          0xFFC02750  /* MXVR Allocation Table Register 5 */
+#define MXVR_ALLOC_6          0xFFC02754  /* MXVR Allocation Table Register 6 */
+#define MXVR_ALLOC_7          0xFFC02758  /* MXVR Allocation Table Register 7 */
+#define MXVR_ALLOC_8          0xFFC0275C  /* MXVR Allocation Table Register 8 */
+#define MXVR_ALLOC_9          0xFFC02760  /* MXVR Allocation Table Register 9 */
+#define MXVR_ALLOC_10         0xFFC02764  /* MXVR Allocation Table Register 10 */
+#define MXVR_ALLOC_11         0xFFC02768  /* MXVR Allocation Table Register 11 */
+#define MXVR_ALLOC_12         0xFFC0276C  /* MXVR Allocation Table Register 12 */
+#define MXVR_ALLOC_13         0xFFC02770  /* MXVR Allocation Table Register 13 */
+#define MXVR_ALLOC_14         0xFFC02774  /* MXVR Allocation Table Register 14 */
+
+#define MXVR_SYNC_LCHAN_0     0xFFC02778  /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define MXVR_SYNC_LCHAN_1     0xFFC0277C  /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define MXVR_SYNC_LCHAN_2     0xFFC02780  /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define MXVR_SYNC_LCHAN_3     0xFFC02784  /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define MXVR_SYNC_LCHAN_4     0xFFC02788  /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define MXVR_SYNC_LCHAN_5     0xFFC0278C  /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define MXVR_SYNC_LCHAN_6     0xFFC02790  /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define MXVR_SYNC_LCHAN_7     0xFFC02794  /* MXVR Sync Data Logical Channel Assign Register 7 */
+
+#define MXVR_DMA0_CONFIG      0xFFC02798  /* MXVR Sync Data DMA0 Config Register */
+#define MXVR_DMA0_START_ADDR  0xFFC0279C  /* MXVR Sync Data DMA0 Start Address Register */
+#define MXVR_DMA0_COUNT       0xFFC027A0  /* MXVR Sync Data DMA0 Loop Count Register */
+#define MXVR_DMA0_CURR_ADDR   0xFFC027A4  /* MXVR Sync Data DMA0 Current Address Register */
+#define MXVR_DMA0_CURR_COUNT  0xFFC027A8  /* MXVR Sync Data DMA0 Current Loop Count Register */
+
+#define MXVR_DMA1_CONFIG      0xFFC027AC  /* MXVR Sync Data DMA1 Config Register */
+#define MXVR_DMA1_START_ADDR  0xFFC027B0  /* MXVR Sync Data DMA1 Start Address Register */
+#define MXVR_DMA1_COUNT       0xFFC027B4  /* MXVR Sync Data DMA1 Loop Count Register */
+#define MXVR_DMA1_CURR_ADDR   0xFFC027B8  /* MXVR Sync Data DMA1 Current Address Register */
+#define MXVR_DMA1_CURR_COUNT  0xFFC027BC  /* MXVR Sync Data DMA1 Current Loop Count Register */
+
+#define MXVR_DMA2_CONFIG      0xFFC027C0  /* MXVR Sync Data DMA2 Config Register */
+#define MXVR_DMA2_START_ADDR  0xFFC027C4  /* MXVR Sync Data DMA2 Start Address Register */
+#define MXVR_DMA2_COUNT       0xFFC027C8  /* MXVR Sync Data DMA2 Loop Count Register */
+#define MXVR_DMA2_CURR_ADDR   0xFFC027CC  /* MXVR Sync Data DMA2 Current Address Register */
+#define MXVR_DMA2_CURR_COUNT  0xFFC027D0  /* MXVR Sync Data DMA2 Current Loop Count Register */
+
+#define MXVR_DMA3_CONFIG      0xFFC027D4  /* MXVR Sync Data DMA3 Config Register */
+#define MXVR_DMA3_START_ADDR  0xFFC027D8  /* MXVR Sync Data DMA3 Start Address Register */
+#define MXVR_DMA3_COUNT       0xFFC027DC  /* MXVR Sync Data DMA3 Loop Count Register */
+#define MXVR_DMA3_CURR_ADDR   0xFFC027E0  /* MXVR Sync Data DMA3 Current Address Register */
+#define MXVR_DMA3_CURR_COUNT  0xFFC027E4  /* MXVR Sync Data DMA3 Current Loop Count Register */
+
+#define MXVR_DMA4_CONFIG      0xFFC027E8  /* MXVR Sync Data DMA4 Config Register */
+#define MXVR_DMA4_START_ADDR  0xFFC027EC  /* MXVR Sync Data DMA4 Start Address Register */
+#define MXVR_DMA4_COUNT       0xFFC027F0  /* MXVR Sync Data DMA4 Loop Count Register */
+#define MXVR_DMA4_CURR_ADDR   0xFFC027F4  /* MXVR Sync Data DMA4 Current Address Register */
+#define MXVR_DMA4_CURR_COUNT  0xFFC027F8  /* MXVR Sync Data DMA4 Current Loop Count Register */
+
+#define MXVR_DMA5_CONFIG      0xFFC027FC  /* MXVR Sync Data DMA5 Config Register */
+#define MXVR_DMA5_START_ADDR  0xFFC02800  /* MXVR Sync Data DMA5 Start Address Register */
+#define MXVR_DMA5_COUNT       0xFFC02804  /* MXVR Sync Data DMA5 Loop Count Register */
+#define MXVR_DMA5_CURR_ADDR   0xFFC02808  /* MXVR Sync Data DMA5 Current Address Register */
+#define MXVR_DMA5_CURR_COUNT  0xFFC0280C  /* MXVR Sync Data DMA5 Current Loop Count Register */
+
+#define MXVR_DMA6_CONFIG      0xFFC02810  /* MXVR Sync Data DMA6 Config Register */
+#define MXVR_DMA6_START_ADDR  0xFFC02814  /* MXVR Sync Data DMA6 Start Address Register */
+#define MXVR_DMA6_COUNT       0xFFC02818  /* MXVR Sync Data DMA6 Loop Count Register */
+#define MXVR_DMA6_CURR_ADDR   0xFFC0281C  /* MXVR Sync Data DMA6 Current Address Register */
+#define MXVR_DMA6_CURR_COUNT  0xFFC02820  /* MXVR Sync Data DMA6 Current Loop Count Register */
+
+#define MXVR_DMA7_CONFIG      0xFFC02824  /* MXVR Sync Data DMA7 Config Register */
+#define MXVR_DMA7_START_ADDR  0xFFC02828  /* MXVR Sync Data DMA7 Start Address Register */
+#define MXVR_DMA7_COUNT       0xFFC0282C  /* MXVR Sync Data DMA7 Loop Count Register */
+#define MXVR_DMA7_CURR_ADDR   0xFFC02830  /* MXVR Sync Data DMA7 Current Address Register */
+#define MXVR_DMA7_CURR_COUNT  0xFFC02834  /* MXVR Sync Data DMA7 Current Loop Count Register */
+
+#define MXVR_AP_CTL           0xFFC02838  /* MXVR Async Packet Control Register */
+#define MXVR_APRB_START_ADDR  0xFFC0283C  /* MXVR Async Packet RX Buffer Start Addr Register */
+#define MXVR_APRB_CURR_ADDR   0xFFC02840  /* MXVR Async Packet RX Buffer Current Addr Register */
+#define MXVR_APTB_START_ADDR  0xFFC02844  /* MXVR Async Packet TX Buffer Start Addr Register */
+#define MXVR_APTB_CURR_ADDR   0xFFC02848  /* MXVR Async Packet TX Buffer Current Addr Register */
+
+#define MXVR_CM_CTL           0xFFC0284C  /* MXVR Control Message Control Register */
+#define MXVR_CMRB_START_ADDR  0xFFC02850  /* MXVR Control Message RX Buffer Start Addr Register */
+#define MXVR_CMRB_CURR_ADDR   0xFFC02854  /* MXVR Control Message RX Buffer Current Address */
+#define MXVR_CMTB_START_ADDR  0xFFC02858  /* MXVR Control Message TX Buffer Start Addr Register */
+#define MXVR_CMTB_CURR_ADDR   0xFFC0285C  /* MXVR Control Message TX Buffer Current Address */
+
+#define MXVR_RRDB_START_ADDR  0xFFC02860  /* MXVR Remote Read Buffer Start Addr Register */
+#define MXVR_RRDB_CURR_ADDR   0xFFC02864  /* MXVR Remote Read Buffer Current Addr Register */
+
+#define MXVR_PAT_DATA_0       0xFFC02868  /* MXVR Pattern Data Register 0 */
+#define MXVR_PAT_EN_0         0xFFC0286C  /* MXVR Pattern Enable Register 0 */
+#define MXVR_PAT_DATA_1       0xFFC02870  /* MXVR Pattern Data Register 1 */
+#define MXVR_PAT_EN_1         0xFFC02874  /* MXVR Pattern Enable Register 1 */
+
+#define MXVR_FRAME_CNT_0      0xFFC02878  /* MXVR Frame Counter 0 */
+#define MXVR_FRAME_CNT_1      0xFFC0287C  /* MXVR Frame Counter 1 */
+
+#define MXVR_ROUTING_0        0xFFC02880  /* MXVR Routing Table Register 0 */
+#define MXVR_ROUTING_1        0xFFC02884  /* MXVR Routing Table Register 1 */
+#define MXVR_ROUTING_2        0xFFC02888  /* MXVR Routing Table Register 2 */
+#define MXVR_ROUTING_3        0xFFC0288C  /* MXVR Routing Table Register 3 */
+#define MXVR_ROUTING_4        0xFFC02890  /* MXVR Routing Table Register 4 */
+#define MXVR_ROUTING_5        0xFFC02894  /* MXVR Routing Table Register 5 */
+#define MXVR_ROUTING_6        0xFFC02898  /* MXVR Routing Table Register 6 */
+#define MXVR_ROUTING_7        0xFFC0289C  /* MXVR Routing Table Register 7 */
+#define MXVR_ROUTING_8        0xFFC028A0  /* MXVR Routing Table Register 8 */
+#define MXVR_ROUTING_9        0xFFC028A4  /* MXVR Routing Table Register 9 */
+#define MXVR_ROUTING_10       0xFFC028A8  /* MXVR Routing Table Register 10 */
+#define MXVR_ROUTING_11       0xFFC028AC  /* MXVR Routing Table Register 11 */
+#define MXVR_ROUTING_12       0xFFC028B0  /* MXVR Routing Table Register 12 */
+#define MXVR_ROUTING_13       0xFFC028B4  /* MXVR Routing Table Register 13 */
+#define MXVR_ROUTING_14       0xFFC028B8  /* MXVR Routing Table Register 14 */
+
+#define MXVR_PLL_CTL_1        0xFFC028BC  /* MXVR Phase Lock Loop Control Register 1 */
+#define MXVR_BLOCK_CNT        0xFFC028C0  /* MXVR Block Counter */
+#define MXVR_PLL_CTL_2        0xFFC028C4  /* MXVR Phase Lock Loop Control Register 2 */
+
+
+/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                */
+/* For Mailboxes 0-15                                                                                    */
+#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1  */
+#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1 */
+#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1 */
+#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1 */
+#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1 */
+#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1 */
+#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1 */
+#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmission reg 1 */
+
+/* For Mailboxes 16-31                                                                                   */
+#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2  */
+#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2 */
+#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2 */
+#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2 */
+#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2 */
+#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2 */
+#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2 */
+#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmission reg 2 */
+
+#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0 */
+#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1 */
+
+#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                */
+/* the following is for backwards compatibility */
+#define CAN_CNF          CAN_DEBUG
+
+#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register */
+#define CAN_CEC                         0xFFC02A90      /* Error Counter Register */
+#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register */
+#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register */
+#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register */
+#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register */
+#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register */
+#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature */
+#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level */
+#define CAN_ESR                         0xFFC02AB4      /* Error Status Register */
+#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter     */
+#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Reload/Capture Register */
+#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks                                      */
+#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x)                     (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x)                     (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers                                                                     */
+#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits and Macros */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+/* PLL_CTL Masks */
+#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2          0x0001  /* Pass CLKIN/2 to PLL */
+#define DF                                      0x0001   /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
+
+#define STOPCK                          0x0008  /* Core Clock Off                */
+#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
+#define IN_DELAY                        0x0014  /* EBIU Input Delay Select */
+#define OUT_DELAY                       0x00C0  /* EBIU Output Delay Select */
+#define BYPASS                          0x0100  /* Bypass the PLL */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
+
+/* PLL_CTL Macros                                */
+#ifdef _MISRA_RULES
+#define SET_MSEL(x)             (((x)&0x3Fu) << 0x9)    /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#define SET_OUT_DELAY(x)        (((x)&0x03u) << 0x6)
+#define SET_IN_DELAY(x)         ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
+#else
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+#define SET_OUT_DELAY(x)        (((x)&0x03) << 0x6)
+#define SET_IN_DELAY(x)         ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
+#endif /* _MISRA_RULES */
+
+/* PLL_DIV Masks */
+#define SSEL                            0x000F  /* System Select */
+#define CSEL                            0x0030  /* Core Select */
+#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1 */
+#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2 */
+#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4 */
+#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8 */
+
+#define SCLK_DIV(x)                     (x)             /* SCLK = VCO / x */
+
+/* PLL_DIV Macros                                                        */
+#ifdef _MISRA_RULES
+#define SET_SSEL(x)                     ((x)&0xFu)      /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#else
+#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#endif /* _MISRA_RULES */
+
+/* PLL_STAT Masks                                                                                */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached */
+
+/* VR_CTL Masks                                                                          */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation */
+#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz */
+
+#define GAIN                    0x000C  /* Voltage Level Gain */
+#define GAIN_5                  0x0000  /*              GAIN = 5 */
+#define GAIN_10                 0x0004  /*              GAIN = 10 */
+#define GAIN_20                 0x0008  /*              GAIN = 20 */
+#define GAIN_50                 0x000C  /*              GAIN = 50 */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_100                0x0090  /*      VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105                0x00A0  /*      VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110                0x00B0  /*      VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115                0x00C0  /*      VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120                0x00D0  /*      VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_125                0x00E0  /*      VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_130                0x00F0  /*      VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
+#define MXVRWE                  0x0400  /* Enable MXVR Wakeup From Hibernate */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
+/* SWRST Mask */
+#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
+#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks                                                                                                   */
+#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
+#define PLL_WAKEUP_IRQ          0x00000001      /* PLL Wakeup Interrupt Request */
+#define DMAC0_ERR_IRQ           0x00000002      /* DMA Controller 0 Error Interrupt Request */
+#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
+#define SPORT0_ERR_IRQ          0x00000008      /* SPORT0 Error Interrupt Request */
+#define SPORT1_ERR_IRQ          0x00000010      /* SPORT1 Error Interrupt Request */
+#define SPI0_ERR_IRQ            0x00000020      /* SPI0 Error Interrupt Request */
+#define UART0_ERR_IRQ           0x00000040      /* UART0 Error Interrupt Request */
+#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
+#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
+#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
+#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
+#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
+#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
+#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
+#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
+#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
+#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
+#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
+#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
+#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
+#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
+#define MDMA0_0_IRQ             0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
+#define MDMA0_1_IRQ             0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
+#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
+#define DMAC1_ERR_IRQ           0x01000000      /* DMA Controller 1 Error Interrupt Request */
+#define SPORT2_ERR_IRQ          0x02000000      /* SPORT2 Error Interrupt Request */
+#define SPORT3_ERR_IRQ          0x04000000      /* SPORT3 Error Interrupt Request */
+#define MXVR_SD_IRQ             0x08000000      /* MXVR Synchronous Data Interrupt Request */
+#define SPI1_ERR_IRQ            0x10000000      /* SPI1 Error Interrupt Request */
+#define SPI2_ERR_IRQ            0x20000000      /* SPI2 Error Interrupt Request */
+#define UART1_ERR_IRQ           0x40000000      /* UART1 Error Interrupt Request */
+#define UART2_ERR_IRQ           0x80000000      /* UART2 Error Interrupt Request */
+
+/* the following are for backwards compatibility */
+#define DMA0_ERR_IRQ            DMAC0_ERR_IRQ
+#define DMA1_ERR_IRQ            DMAC1_ERR_IRQ
+
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1   */
+#define CAN_ERR_IRQ                     0x00000001      /* CAN Error Interrupt Request */
+#define DMA8_IRQ                        0x00000002      /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
+#define DMA9_IRQ                        0x00000004      /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
+#define DMA10_IRQ                       0x00000008      /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
+#define DMA11_IRQ                       0x00000010      /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
+#define DMA12_IRQ                       0x00000020      /* DMA Channel 12 Interrupt Request */
+#define DMA13_IRQ                       0x00000040      /* DMA Channel 13 Interrupt Request */
+#define DMA14_IRQ                       0x00000080      /* DMA Channel 14 (SPI1) Interrupt Request */
+#define DMA15_IRQ                       0x00000100      /* DMA Channel 15 (SPI2) Interrupt Request */
+#define DMA16_IRQ                       0x00000200      /* DMA Channel 16 (UART1 RX) Interrupt Request */
+#define DMA17_IRQ                       0x00000400      /* DMA Channel 17 (UART1 TX) Interrupt Request */
+#define DMA18_IRQ                       0x00000800      /* DMA Channel 18 (UART2 RX) Interrupt Request */
+#define DMA19_IRQ                       0x00001000      /* DMA Channel 19 (UART2 TX) Interrupt Request */
+#define TWI0_IRQ                        0x00002000      /* TWI0 Interrupt Request */
+#define TWI1_IRQ                        0x00004000      /* TWI1 Interrupt Request */
+#define CAN_RX_IRQ                      0x00008000      /* CAN Receive Interrupt Request */
+#define CAN_TX_IRQ                      0x00010000      /* CAN Transmit Interrupt Request */
+#define MDMA1_0_IRQ                     0x00020000      /* MemDMA1 Stream 0 Interrupt Request */
+#define MDMA1_1_IRQ                     0x00040000      /* MemDMA1 Stream 1 Interrupt Request */
+#define MXVR_STAT_IRQ                   0x00080000      /* MXVR Status Interrupt Request */
+#define MXVR_CM_IRQ                     0x00100000      /* MXVR Control Message Interrupt Request */
+#define MXVR_AP_IRQ                     0x00200000      /* MXVR Asynchronous Packet Interrupt */
+
+/* the following are for backwards compatibility */
+#define MDMA0_IRQ               MDMA1_0_IRQ
+#define MDMA1_IRQ               MDMA1_1_IRQ
+
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
+/* SIC_IMASKx Masks                                                                                      */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt */
+#else
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+/* SIC_IWRx Masks                                                                                        */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x */
+#else
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+/* Watchdog Timer WDOG_CTL Register Masks */
+#ifdef _MISRA_RULES
+#define WDEV(x)                 (((x)<<1) & 0x0006u)    /* event generated on roll over */
+#else
+#define WDEV(x)                 (((x)<<1) & 0x0006)     /* event generated on roll over */
+#endif /* _MISRA_RULES */
+#define WDEV_RESET              0x0000                          /* generate reset event on roll over */
+#define WDEV_NMI                0x0002                          /* generate NMI event on roll over */
+#define WDEV_GPI                0x0004                          /* generate GP IRQ on roll over */
+#define WDEV_NONE               0x0006                          /* no event on roll over */
+#define WDEN                    0x0FF0                          /* enable watchdog */
+#define WDDIS                   0x0AD0                          /* disable watchdog */
+#define WDRO                    0x8000                          /* watchdog rolled over latch */
+
+/* deprecated WDOG_CTL Register Masks for legacy code */
+#define ICTL WDEV
+#define ENABLE_RESET    WDEV_RESET
+#define WDOG_RESET              WDEV_RESET
+#define ENABLE_NMI              WDEV_NMI
+#define WDOG_NMI                WDEV_NMI
+#define ENABLE_GPI              WDEV_GPI
+#define WDOG_GPI                WDEV_GPI
+#define DISABLE_EVT     WDEV_NONE
+#define WDOG_NONE               WDEV_NONE
+
+#define TMR_EN                  WDEN
+#define WDOG_DISABLE            WDDIS
+#define TRO                     WDRO
+
+#define ICTL_P0                 0x01
+#define ICTL_P1                 0x02
+#define TRO_P                   0x0F
+
+
+/* ***************  REAL TIME CLOCK MASKS  **************************/
+/* RTC_STAT and RTC_ALARM register */
+#define RTSEC           0x0000003F      /* Real-Time Clock Seconds */
+#define RTMIN           0x00000FC0      /* Real-Time Clock Minutes */
+#define RTHR            0x0001F000      /* Real-Time Clock Hours */
+#define RTDAY           0xFFFE0000      /* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define SWIE            0x0001          /* Stopwatch Interrupt Enable */
+#define AIE                     0x0002          /* Alarm Interrupt Enable */
+#define SIE                     0x0004          /* Seconds (1 Hz) Interrupt Enable */
+#define MIE                     0x0008          /* Minutes Interrupt Enable */
+#define HIE                     0x0010          /* Hours Interrupt Enable */
+#define DIE                     0x0020          /* 24 Hours (Days) Interrupt Enable */
+#define DAIE            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WCIE            0x8000          /* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define SWEF            0x0001          /* Stopwatch Event Flag */
+#define AEF                     0x0002          /* Alarm Event Flag */
+#define SEF                     0x0004          /* Seconds (1 Hz) Event Flag */
+#define MEF                     0x0008          /* Minutes Event Flag */
+#define HEF                     0x0010          /* Hours Event Flag */
+#define DEF                     0x0020          /* 24 Hours (Days) Event Flag */
+#define DAEF            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define WPS                     0x4000          /* Write Pending Status (RO) */
+#define WCOM            0x8000          /* Write Complete */
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE      0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
+#define PREN                 0x00000001
+                /* ** Must be set after power-up for proper operation of RTC */
+
+/* Deprecated RTC_STAT and RTC_ALARM Masks                       */
+#define RTC_SEC                 RTSEC   /* Real-Time Clock Seconds */
+#define RTC_MIN                 RTMIN   /* Real-Time Clock Minutes */
+#define RTC_HR                  RTHR    /* Real-Time Clock Hours */
+#define RTC_DAY                 RTDAY   /* Real-Time Clock Days */
+
+/* Deprecated RTC_ICTL/RTC_ISTAT Masks                                                                                   */
+#define STOPWATCH               SWIE            /* Stopwatch Interrupt Enable    */
+#define ALARM                   AIE             /* Alarm Interrupt Enable                */
+#define SECOND                  SIE             /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE                  MIE             /* Minutes Interrupt Enable              */
+#define HOUR                    HIE             /* Hours Interrupt Enable                */
+#define DAY                             DIE             /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM               DAIE            /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_COMPLETE  WCIE            /* Write Complete Interrupt Enable */
+
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+/* UARTx_LCR Register */
+#ifdef _MISRA_RULES
+#define WLS(x)          (((x)-5u) & 0x03u)      /* Word Length Select */
+#else
+#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
+#endif /* _MISRA_RULES */
+#define STB                     0x04                            /* Stop Bits */
+#define PEN                     0x08                            /* Parity Enable */
+#define EPS                     0x10                            /* Even Parity Select */
+#define STP                     0x20                            /* Stick Parity */
+#define SB                      0x40                            /* Set Break */
+#define DLAB            0x80                            /* Divisor Latch Access */
+
+#define DLAB_P          0x07
+#define SB_P            0x06
+#define STP_P           0x05
+#define EPS_P           0x04
+#define PEN_P           0x03
+#define STB_P           0x02
+#define WLS_P1          0x01
+#define WLS_P0          0x00
+
+/* UARTx_MCR Register */
+#define LOOP_ENA        0x10    /* Loopback Mode Enable */
+#define LOOP_ENA_P      0x04
+/* Deprecated UARTx_MCR Mask                     */
+
+/* UARTx_LSR Register */
+#define DR                      0x01    /* Data Ready */
+#define OE                      0x02    /* Overrun Error */
+#define PE                      0x04    /* Parity Error */
+#define FE                      0x08    /* Framing Error */
+#define BI                      0x10    /* Break Interrupt */
+#define THRE            0x20    /* THR Empty */
+#define TEMT            0x40    /* TSR and UART_THR Empty */
+
+#define TEMP_P          0x06
+#define THRE_P          0x05
+#define BI_P            0x04
+#define FE_P            0x03
+#define PE_P            0x02
+#define OE_P            0x01
+#define DR_P            0x00
+
+/* UARTx_IER Register */
+#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt */
+#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI            0x04            /* Enable RX Status Interrupt */
+
+#define ELSI_P          0x02
+#define ETBEI_P         0x01
+#define ERBFI_P         0x00
+
+/* UARTx_IIR Register */
+#define NINT            0x01
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+#define NINT_P          0x00
+
+/* UARTx_GCTL Register */
+#define UCEN            0x01            /* Enable UARTx Clocks */
+#define IREN            0x02            /* Enable IrDA Mode */
+#define TPOLC           0x04            /* IrDA TX Polarity Change */
+#define RPOLC           0x08            /* IrDA RX Polarity Change */
+#define FPE                     0x10            /* Force Parity Error On Transmit */
+#define FFE                     0x20            /* Force Framing Error On Transmit */
+
+#define FFE_P           0x05
+#define FPE_P           0x04
+#define RPOLC_P         0x03
+#define TPOLC_P         0x02
+#define IREN_P          0x01
+#define UCEN_P          0x00
+
+
+/* **********  SERIAL PORT MASKS  ********************** */
+/* SPORTx_TCR1 Masks */
+#define TSPEN           0x0001  /* TX enable  */
+#define ITCLK           0x0002  /* Internal TX Clock Select  */
+#define TDTYPE          0x000C  /* TX Data Formatting Select */
+#define DTYPE_NORM      0x0000          /* Data Format Normal */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law */
+#define TLSBIT          0x0010  /* TX Bit Order */
+#define ITFS            0x0200  /* Internal TX Frame Sync Select  */
+#define TFSR            0x0400  /* TX Frame Sync Required Select  */
+#define DITFS           0x0800  /* Data Independent TX Frame Sync Select  */
+#define LTFS            0x1000  /* Low TX Frame Sync Select  */
+#define LATFS           0x2000  /* Late TX Frame Sync Select  */
+#define TCKFE           0x4000  /* TX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks                                                          */
+#define TULAW           DTYPE_ULAW              /* Compand Using u-Law */
+#define TALAW           DTYPE_ALAW                      /* Compand Using A-Law */
+
+/* SPORTx_TCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x)         ((x)&0x1Fu)     /* SPORT TX Word Length (2 - 31) */
+#else
+#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
+#define TXSE            0x0100  /*TX Secondary Enable */
+#define TSFSE           0x0200  /*TX Stereo Frame Sync Enable */
+#define TRFST           0x0400  /*TX Right-First Data Order  */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN           0x0001  /* RX enable  */
+#define IRCLK           0x0002  /* Internal RX Clock Select  */
+#define RDTYPE          0x000C  /* RX Data Formatting Select */
+#define DTYPE_NORM      0x0000          /* no companding */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law */
+#define RLSBIT          0x0010  /* RX Bit Order */
+#define IRFS            0x0200  /* Internal RX Frame Sync Select  */
+#define RFSR            0x0400  /* RX Frame Sync Required Select  */
+#define LRFS            0x1000  /* Low RX Frame Sync Select  */
+#define LARFS           0x2000  /* Late RX Frame Sync Select  */
+#define RCKFE           0x4000  /* RX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks                                                          */
+#define RULAW           DTYPE_ULAW              /* Compand Using u-Law */
+#define RALAW           DTYPE_ALAW                      /* Compand Using A-Law */
+
+/* SPORTx_RCR2 Masks */
+#ifdef _MISRA_RULES
+#define SLEN(x)         ((x)&0x1Fu)     /* SPORT RX Word Length (2 - 31) */
+#else
+#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31) */
+#endif /* _MISRA_RULES */
+#define RXSE            0x0100  /*RX Secondary Enable */
+#define RSFSE           0x0200  /*RX Stereo Frame Sync Enable */
+#define RRFST           0x0400  /*Right-First Data Order  */
+
+/*SPORTx_STAT Masks */
+#define RXNE            0x0001          /*RX FIFO Not Empty Status */
+#define RUVF            0x0002          /*RX Underflow Status */
+#define ROVF            0x0004          /*RX Overflow Status */
+#define TXF                     0x0008          /*TX FIFO Full Status */
+#define TUVF            0x0010          /*TX Underflow Status */
+#define TOVF            0x0020          /*TX Overflow Status */
+#define TXHRE           0x0040          /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define WOFF                    0x000003FF      /*Multichannel Window Offset Field */
+/* SPORTx_MCMC1 Macros                                                           */
+#ifdef _MISRA_RULES
+#define SET_WOFF(x)             ((x) & 0x3FFu)  /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x)    (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+#else
+#define SET_WOFF(x)             ((x) & 0x3FF)   /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x)    (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1 */
+#endif /* _MISRA_RULES */
+
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM           0x0003  /*Multichannel Clock Recovery Mode */
+#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE         0x0004  /*Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x0008  /*Multichannel DMA Receive Packing */
+#define MCMEN           0x0010  /*Multichannel Frame Mode Enable */
+#define FSDR            0x0080  /*Multichannel Frame Sync to Data Relationship */
+#define MFD                     0xF000  /*Multichannel Frame Delay    */
+#define MFD_0           0x0000          /* Multichannel Frame Delay = 0 */
+#define MFD_1           0x1000          /* Multichannel Frame Delay = 1 */
+#define MFD_2           0x2000          /* Multichannel Frame Delay = 2 */
+#define MFD_3           0x3000          /* Multichannel Frame Delay = 3 */
+#define MFD_4           0x4000          /* Multichannel Frame Delay = 4 */
+#define MFD_5           0x5000          /* Multichannel Frame Delay = 5 */
+#define MFD_6           0x6000          /* Multichannel Frame Delay = 6 */
+#define MFD_7           0x7000          /* Multichannel Frame Delay = 7 */
+#define MFD_8           0x8000          /* Multichannel Frame Delay = 8 */
+#define MFD_9           0x9000          /* Multichannel Frame Delay = 9 */
+#define MFD_10          0xA000          /* Multichannel Frame Delay = 10 */
+#define MFD_11          0xB000          /* Multichannel Frame Delay = 11 */
+#define MFD_12          0xC000          /* Multichannel Frame Delay = 12 */
+#define MFD_13          0xD000          /* Multichannel Frame Delay = 13 */
+#define MFD_14          0xE000          /* Multichannel Frame Delay = 14 */
+#define MFD_15          0xF000          /* Multichannel Frame Delay = 15 */
+
+
+/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
+/*  PPI_CONTROL Masks         */
+#define PORT_EN         0x0001  /* PPI Port Enable  */
+#define PORT_DIR        0x0002  /* PPI Port Direction       */
+#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
+#define PORT_CFG        0x0030  /* PPI Port Configuration */
+#define FLD_SEL         0x0040  /* PPI Active Field Select */
+#define PACK_EN         0x0080  /* PPI Packing Mode */
+/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
+#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
+#define DLENGTH         0x3800  /* PPI Data Length  */
+#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
+#define DLEN_10         0x0800          /* Data Length = 10 Bits */
+#define DLEN_11         0x1000          /* Data Length = 11 Bits */
+#define DLEN_12         0x1800          /* Data Length = 12 Bits */
+#define DLEN_13         0x2000          /* Data Length = 13 Bits */
+#define DLEN_14         0x2800          /* Data Length = 14 Bits */
+#define DLEN_15         0x3000          /* Data Length = 15 Bits */
+#define DLEN_16         0x3800          /* Data Length = 16 Bits */
+#ifdef _MISRA_RULES
+#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#else
+#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
+#define POL                     0xC000  /* PPI Signal Polarities       */
+#define POLC            0x4000          /* PPI Clock Polarity */
+#define POLS            0x8000          /* PPI Frame Sync Polarity */
+
+
+/* PPI_STATUS Masks                                          */
+#define FLD                     0x0400  /* Field Indicator   */
+#define FT_ERR          0x0800  /* Frame Track Error */
+#define OVR                     0x1000  /* FIFO Overflow Error */
+#define UNDR            0x2000  /* FIFO Underrun Error */
+#define ERR_DET         0x4000  /* Error Detected Indicator */
+#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
+
+
+/* **********  DMA CONTROLLER MASKS  ***********************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN           0x0001  /* Channel Enable */
+#define WNR                     0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8        0x0000  /* Word Size 8 bits */
+#define WDSIZE_16       0x0004  /* Word Size 16 bits */
+#define WDSIZE_32       0x0008  /* Word Size 32 bits */
+#define DMA2D           0x0010  /* 2D/1D* Mode */
+#define RESTART         0x0020  /* Restart */
+#define DI_SEL          0x0040  /* Data Interrupt Select */
+#define DI_EN           0x0080  /* Data Interrupt Enable */
+#define NDSIZE          0x0900  /* Next Descriptor Size */
+#define NDSIZE_0        0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1        0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2        0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3        0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4        0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5        0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6        0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7        0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8        0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9        0x0900  /* Next Descriptor Size = 9 */
+
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP            0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
+
+#define DMAEN_P         0x0             /* Channel Enable */
+#define WNR_P           0x1             /* Channel Direction (W/R*) */
+#define DMA2D_P         0x4             /* 2D/1D* Mode */
+#define RESTART_P       0x5             /* Restart */
+#define DI_SEL_P        0x6             /* Data Interrupt Select */
+#define DI_EN_P         0x7             /* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE        0x0001  /* DMA Done Indicator */
+#define DMA_ERR         0x0002  /* DMA Error Indicator */
+#define DFETCH          0x0004  /* Descriptor Fetch Indicator */
+#define DMA_RUN         0x0008  /* DMA Running Indicator */
+
+#define DMA_DONE_P      0x0             /* DMA Done Indicator */
+#define DMA_ERR_P       0x1             /* DMA Error Indicator */
+#define DFETCH_P        0x2             /* Descriptor Fetch Indicator */
+#define DMA_RUN_P       0x3             /* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
+#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
+#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
+#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
+#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
+#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
+#define PMAP                    0xF000  /* DMA Peripheral Map Field */
+
+/* PMAP Encodings For DMA Controller 0 */
+#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI0               0x5000  /* PMAP SPI DMA */
+#define PMAP_UART0RX            0x6000  /* PMAP UART Receive DMA */
+#define PMAP_UART0TX            0x7000  /* PMAP UART Transmit DMA */
+
+/* PMAP Encodings For DMA Controller 1 */
+#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
+#define PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
+#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
+#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
+#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
+#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
+#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
+#define PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
+#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
+#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
+
+
+/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
+/* PWM Timer bit definitions */
+/* TIMER_ENABLE Register */
+#define TIMEN0                  0x0001  /* Enable Timer 0 */
+#define TIMEN1                  0x0002  /* Enable Timer 1 */
+#define TIMEN2                  0x0004  /* Enable Timer 2 */
+
+#define TIMEN0_P                0x00
+#define TIMEN1_P                0x01
+#define TIMEN2_P                0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0                 0x0001  /* Disable Timer 0 */
+#define TIMDIS1                 0x0002  /* Disable Timer 1 */
+#define TIMDIS2                 0x0004  /* Disable Timer 2 */
+
+#define TIMDIS0_P               0x00
+#define TIMDIS1_P               0x01
+#define TIMDIS2_P               0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0                  0x0001  /* Timer 0 Interrupt */
+#define TIMIL1                  0x0002  /* Timer 1 Interrupt */
+#define TIMIL2                  0x0004  /* Timer 2 Interrupt */
+#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow */
+#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow */
+#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow */
+#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status */
+#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status */
+#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status */
+
+#define TIMIL0_P                0x00
+#define TIMIL1_P                0x01
+#define TIMIL2_P                0x02
+#define TOVF_ERR0_P             0x04
+#define TOVF_ERR1_P             0x05
+#define TOVF_ERR2_P             0x06
+#define TRUN0_P                 0x0C
+#define TRUN1_P                 0x0D
+#define TRUN2_P                 0x0E
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0               TOVF_ERR0
+#define TOVL_ERR1               TOVF_ERR1
+#define TOVL_ERR2               TOVF_ERR2
+#define TOVL_ERR0_P             TOVF_ERR0_P
+#define TOVL_ERR1_P     TOVF_ERR1_P
+#define TOVL_ERR2_P     TOVF_ERR2_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT                 0x0001
+#define WDTH_CAP                0x0002
+#define EXT_CLK                 0x0003
+#define PULSE_HI                0x0004
+#define PERIOD_CNT              0x0008
+#define IRQ_ENA                 0x0010
+#define TIN_SEL                 0x0020
+#define OUT_DIS                 0x0040
+#define CLK_SEL                 0x0080
+#define TOGGLE_HI               0x0100
+#define EMU_RUN                 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x)              (((x) & 0x03u) << 14)
+#else
+#define ERR_TYP(x)              (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
+
+#define TMODE_P0                0x00
+#define TMODE_P1                0x01
+#define PULSE_HI_P              0x02
+#define PERIOD_CNT_P    0x03
+#define IRQ_ENA_P               0x04
+#define TIN_SEL_P               0x05
+#define OUT_DIS_P               0x06
+#define CLK_SEL_P               0x07
+#define TOGGLE_HI_P             0x08
+#define EMU_RUN_P               0x09
+#define ERR_TYP_P0              0x0E
+#define ERR_TYP_P1              0x0F
+
+
+/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
+/*  Flag I/O (FIO_) Masks */
+#define PF0                     0x0001
+#define PF1                     0x0002
+#define PF2                     0x0004
+#define PF3                     0x0008
+#define PF4                     0x0010
+#define PF5                     0x0020
+#define PF6                     0x0040
+#define PF7                     0x0080
+#define PF8                     0x0100
+#define PF9                     0x0200
+#define PF10            0x0400
+#define PF11            0x0800
+#define PF12            0x1000
+#define PF13            0x2000
+#define PF14            0x4000
+#define PF15            0x8000
+
+/*  PORT F BIT POSITIONS */
+#define PF0_P           0x0
+#define PF1_P           0x1
+#define PF2_P           0x2
+#define PF3_P           0x3
+#define PF4_P           0x4
+#define PF5_P           0x5
+#define PF6_P           0x6
+#define PF7_P           0x7
+#define PF8_P           0x8
+#define PF9_P           0x9
+#define PF10_P          0xA
+#define PF11_P          0xB
+#define PF12_P          0xC
+#define PF13_P          0xD
+#define PF14_P          0xE
+#define PF15_P          0xF
+
+
+/*******************   GPIO MASKS  *********************/
+/* Port C Masks */
+#define PC0             0x0001
+#define PC1             0x0002
+#define PC4             0x0010
+#define PC5             0x0020
+#define PC6             0x0040
+#define PC7             0x0080
+#define PC8             0x0100
+#define PC9             0x0200
+/* Port C Bit Positions */
+#define PC0_P   0x0
+#define PC1_P   0x1
+#define PC4_P   0x4
+#define PC5_P   0x5
+#define PC6_P   0x6
+#define PC7_P   0x7
+#define PC8_P   0x8
+#define PC9_P   0x9
+
+/* Port D */
+#define PD0             0x0001
+#define PD1             0x0002
+#define PD2             0x0004
+#define PD3             0x0008
+#define PD4             0x0010
+#define PD5             0x0020
+#define PD6             0x0040
+#define PD7             0x0080
+#define PD8             0x0100
+#define PD9             0x0200
+#define PD10    0x0400
+#define PD11    0x0800
+#define PD12    0x1000
+#define PD13    0x2000
+#define PD14    0x4000
+#define PD15    0x8000
+/* Port D Bit Positions */
+#define PD0_P   0x0
+#define PD1_P   0x1
+#define PD2_P   0x2
+#define PD3_P   0x3
+#define PD4_P   0x4
+#define PD5_P   0x5
+#define PD6_P   0x6
+#define PD7_P   0x7
+#define PD8_P   0x8
+#define PD9_P   0x9
+#define PD10_P  0xA
+#define PD11_P  0xB
+#define PD12_P  0xC
+#define PD13_P  0xD
+#define PD14_P  0xE
+#define PD15_P  0xF
+
+/* Port E */
+#define PE0             0x0001
+#define PE1             0x0002
+#define PE2             0x0004
+#define PE3             0x0008
+#define PE4             0x0010
+#define PE5             0x0020
+#define PE6             0x0040
+#define PE7             0x0080
+#define PE8             0x0100
+#define PE9             0x0200
+#define PE10    0x0400
+#define PE11    0x0800
+#define PE12    0x1000
+#define PE13    0x2000
+#define PE14    0x4000
+#define PE15    0x8000
+/* Port E Bit Positions */
+#define PE0_P   0x0
+#define PE1_P   0x1
+#define PE2_P   0x2
+#define PE3_P   0x3
+#define PE4_P   0x4
+#define PE5_P   0x5
+#define PE6_P   0x6
+#define PE7_P   0x7
+#define PE8_P   0x8
+#define PE9_P   0x9
+#define PE10_P  0xA
+#define PE11_P  0xB
+#define PE12_P  0xC
+#define PE13_P  0xD
+#define PE14_P  0xE
+#define PE15_P  0xF
+
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
+/* SPIx_CTL Masks */
+#define TIMOD           0x0003          /* Transfer Initiate Mode */
+#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full */
+#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE            0x0010          /* Slave-Select Input Enable */
+#define EMISO           0x0020          /* Enable MISO As Output */
+#define SIZE            0x0100          /* Size of Words (16/8* Bits) */
+#define LSBF            0x0200          /* LSB First                     */
+#define CPHA            0x0400          /* Clock Phase                   */
+#define CPOL            0x0800          /* Clock Polarity                */
+#define MSTR            0x1000          /* Master/Slave*                 */
+#define WOM                     0x2000          /* Write Open Drain Master */
+#define SPE                     0x4000          /* SPI Enable                    */
+
+/* SPIx_FLG Masks */
+#define FLS1    0x0002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2    0x0004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3    0x0008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4    0x0010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5    0x0020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6    0x0040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7    0x0080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+#define FLG1    0x0200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2    0x0400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3    0x0800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4    0x1000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5    0x2000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6    0x4000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7    0x8000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPIx_FLG Bit Positions */
+#define FLS1_P  0x0001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P  0x0002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P  0x0003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P  0x0004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P  0x0005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P  0x0006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P  0x0007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P  0x0009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2_P  0x000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P  0x000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4_P  0x000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5_P  0x000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6_P  0x000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7_P  0x000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPIx_STAT Masks */
+#define SPIF    0x0001  /* Set (=1) when SPI single-word transfer complete */
+#define MODF    0x0002  /* Set (=1) in a master device when some other device tries to become master */
+#define TXE             0x0004  /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS             0x0008  /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY    0x0010  /* Set (=1) when data is received with RDBR full */
+#define RXS             0x0020  /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
+#define TXCOL   0x0040  /* When set (=1), corrupt data may have been transmitted  */
+
+/* SPIx_FLG Masks                                                                                */
+#define FLG1E   0xFDFF          /* Activates SPI_FLOUT1  */
+#define FLG2E   0xFBFF          /* Activates SPI_FLOUT2  */
+#define FLG3E   0xF7FF          /* Activates SPI_FLOUT3  */
+#define FLG4E   0xEFFF          /* Activates SPI_FLOUT4  */
+#define FLG5E   0xDFFF          /* Activates SPI_FLOUT5  */
+#define FLG6E   0xBFFF          /* Activates SPI_FLOUT6  */
+#define FLG7E   0x7FFF          /* Activates SPI_FLOUT7  */
+
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN          0x0001  /* Enable CLKOUT */
+#define AMBEN_NONE      0x0000  /* All Banks Disabled */
+#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO          0x0100  /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P                0x0000  /* Enable CLKOUT */
+#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+/* EBIU_SDGCTL Masks */
+#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE                             0x00000010 /* Enable SDRAM prefetch */
+#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD                   0x00200000 /*Power-up start delay */
+#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE                   0x02000000 /* Enable external buffering timing */
+#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
+#define EMREN                   0x10000000 /* Extended mode register enable */
+#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE                             0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16                 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32                 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64                 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
+#define EBSZ_256                0x00000008 /* SDRAM External Bank Size = 256MB */
+#define EBSZ_512                0x0000000A /* SDRAM External Bank Size = 512MB */
+#define EBCAW_8                 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9                 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                    0x00000001 /* SDRAM controller is idle */
+#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA                   0x00000004 /* SDRAM power up active  */
+#define SDRS                    0x00000008 /* SDRAM is in reset state */
+#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                  0x00000020 /* Bus granted */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
+/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
+#else
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
+
+/* TWIx_PRESCALE Masks                                                           */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA         0x0080          /* TWI Enable            */
+#define SCCB            0x0200          /* SCCB Compatibility Enable */
+
+/* TWIx_SLAVE_CTRL Masks                                                                 */
+#define SEN                     0x0001          /* Slave Enable          */
+#define SADD_LEN        0x0002          /* Slave Address Length */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
+
+/* TWIx_SLAVE_STAT Masks                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator */
+
+/* TWIx_MASTER_CTRL Masks                                                */
+#define MEN                     0x0001          /* Master Mode Enable */
+#define MADD_LEN        0x0002          /* Master Address Length */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs */
+#define STOP            0x0010          /* Issue Stop Condition */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer */
+#define SDAOVR          0x4000          /* Serial Data Override */
+#define SCLOVR          0x8000          /* Serial Clock Override */
+
+/* TWIx_MASTER_STAT Masks                                                        */
+#define MPROG           0x0001          /* Master Transfer In Progress */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK            0x0004          /* Address Not Acknowledged */
+#define DNAK            0x0008          /* Data Not Acknowledged */
+#define BUFRDERR        0x0010          /* Buffer Read Error */
+#define BUFWRERR        0x0020          /* Buffer Write Error */
+#define SDASEN          0x0040          /* Serial Data Sense */
+#define SCLSEN          0x0080          /* Serial Clock Sense */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator */
+
+/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
+#define SINIT           0x0001          /* Slave Transfer Initiated */
+#define SCOMP           0x0002          /* Slave Transfer Complete */
+#define SERR            0x0004          /* Slave Transfer Error */
+#define SOVF            0x0008          /* Slave Overflow */
+#define MCOMP           0x0010          /* Master Transfer Complete */
+#define MERR            0x0020          /* Master Transfer Error */
+#define XMTSERV         0x0040          /* Transmit FIFO Service */
+#define RCVSERV         0x0080          /* Receive FIFO Service */
+
+/* TWIx_FIFO_CTRL Masks                                  */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
+
+/* TWIx_FIFO_STAT Masks                                                          */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
+
+
+/********************************* MXVR MASKS ****************************************/
+
+/* MXVR_CONFIG Masks */
+
+#define MXVREN    0x00000001lu
+#define MMSM      0x00000002lu
+#define ACTIVE    0x00000004lu
+#define SDELAY    0x00000008lu
+#define NCMRXEN   0x00000010lu
+#define RWRRXEN   0x00000020lu
+#define MTXEN     0x00000040lu
+#define MTXON     0x00000080lu /*legacy*/
+#define MTXONB    0x00000080lu
+#define EPARITY   0x00000100lu
+#define MSB       0x00001E00lu
+#define APRXEN    0x00002000lu
+#define WAKEUP    0x00004000lu
+#define LMECH     0x00008000lu
+
+#ifdef _MISRA_RULES
+#define SET_MSB(x)     (((x)&0xFu) << 0x9)
+#else
+#define SET_MSB(x)     (((x)&0xF) << 0x9)
+#endif /* _MISRA_RULES */
+
+
+/* MXVR_PLL_CTL_0 Masks */
+
+#define MXTALCEN  0x00000001lu
+#define MXTALFEN  0x00000002lu
+#define MPLLMS    0x00000008lu
+#define MXTALMUL  0x00000030lu
+#define MPLLEN    0x00000040lu
+#define MPLLEN0   0x00000040lu /* legacy */
+#define MPLLEN1   0x00000080lu /* legacy */
+#define MMCLKEN   0x00000100lu
+#define MMCLKMUL  0x00001E00lu
+#define MPLLRSTB  0x00002000lu
+#define MPLLRSTB0 0x00002000lu /* legacy */
+#define MPLLRSTB1 0x00004000lu /* legacy */
+#define MBCLKEN   0x00010000lu
+#define MBCLKDIV  0x001E0000lu
+#define MPLLCDR   0x00200000lu
+#define MPLLCDR0  0x00200000lu /* legacy */
+#define MPLLCDR1  0x00400000lu /* legacy */
+#define INVRX     0x00800000lu
+#define MFSEN     0x01000000lu
+#define MFSDIV    0x1E000000lu
+#define MFSSEL    0x60000000lu
+#define MFSSYNC   0x80000000lu
+
+#define MXTALMUL_256FS   0x00000000lu /* legacy */
+#define MXTALMUL_384FS   0x00000010lu /* legacy */
+#define MXTALMUL_512FS   0x00000020lu /* legacy */
+#define MXTALMUL_1024FS  0x00000030lu
+
+#define MMCLKMUL_1024FS  0x00000000lu
+#define MMCLKMUL_512FS   0x00000200lu
+#define MMCLKMUL_256FS   0x00000400lu
+#define MMCLKMUL_128FS   0x00000600lu
+#define MMCLKMUL_64FS    0x00000800lu
+#define MMCLKMUL_32FS    0x00000A00lu
+#define MMCLKMUL_16FS    0x00000C00lu
+#define MMCLKMUL_8FS     0x00000E00lu
+#define MMCLKMUL_4FS     0x00001000lu
+#define MMCLKMUL_2FS     0x00001200lu
+#define MMCLKMUL_1FS     0x00001400lu
+#define MMCLKMUL_1536FS  0x00001A00lu
+#define MMCLKMUL_768FS   0x00001C00lu
+#define MMCLKMUL_384FS   0x00001E00lu
+
+#define MBCLKDIV_DIV2    0x00020000lu
+#define MBCLKDIV_DIV4    0x00040000lu
+#define MBCLKDIV_DIV8    0x00060000lu
+#define MBCLKDIV_DIV16   0x00080000lu
+#define MBCLKDIV_DIV32   0x000A0000lu
+#define MBCLKDIV_DIV64   0x000C0000lu
+#define MBCLKDIV_DIV128  0x000E0000lu
+#define MBCLKDIV_DIV256  0x00100000lu
+#define MBCLKDIV_DIV512  0x00120000lu
+#define MBCLKDIV_DIV1024 0x00140000lu
+
+#define MFSDIV_DIV2      0x02000000lu
+#define MFSDIV_DIV4      0x04000000lu
+#define MFSDIV_DIV8      0x06000000lu
+#define MFSDIV_DIV16     0x08000000lu
+#define MFSDIV_DIV32     0x0A000000lu
+#define MFSDIV_DIV64     0x0C000000lu
+#define MFSDIV_DIV128    0x0E000000lu
+#define MFSDIV_DIV256    0x10000000lu
+#define MFSDIV_DIV512    0x12000000lu
+#define MFSDIV_DIV1024   0x14000000lu
+
+#define MFSSEL_CLOCK     0x00000000lu
+#define MFSSEL_PULSE_HI  0x20000000lu
+#define MFSSEL_PULSE_LO  0x40000000lu
+
+
+/* MXVR_PLL_CTL_1 Masks */
+
+#define MSTO       0x00000001lu
+#define MSTO0      0x00000001lu /* legacy */
+#define MHOGGD     0x00000004lu
+#define MHOGGD0    0x00000004lu /* legacy */
+#define MHOGGD1    0x00000008lu /* legacy */
+#define MSHAPEREN  0x00000010lu
+#define MSHAPEREN0 0x00000010lu /* legacy */
+#define MSHAPEREN1 0x00000020lu /* legacy */
+#define MPLLCNTEN  0x00008000lu
+#define MPLLCNT    0xFFFF0000lu
+
+#ifdef _MISRA_RULES
+#define SET_MPLLCNT(x)     (((x)&0xFFFFu) << 0x10)
+#else
+#define SET_MPLLCNT(x)     (((x)&0xFFFF) << 0x10)
+#endif /* _MISRA_RULES */
+
+
+/* MXVR_PLL_CTL_2 Masks */
+
+#define MSHAPERSEL 0x00000007lu
+#define MCPSEL     0x000000E0lu
+
+/* MXVR_INT_STAT_0 Masks */
+
+#define NI2A  0x00000001lu
+#define NA2I  0x00000002lu
+#define SBU2L 0x00000004lu
+#define SBL2U 0x00000008lu
+#define PRU   0x00000010lu
+#define MPRU  0x00000020lu
+#define DRU   0x00000040lu
+#define MDRU  0x00000080lu
+#define SBU   0x00000100lu
+#define ATU   0x00000200lu
+#define FCZ0  0x00000400lu
+#define FCZ1  0x00000800lu
+#define PERR  0x00001000lu
+#define MH2L  0x00002000lu
+#define ML2H  0x00004000lu
+#define WUP   0x00008000lu
+#define FU2L  0x00010000lu
+#define FL2U  0x00020000lu
+#define BU2L  0x00040000lu
+#define BL2U  0x00080000lu
+#define PCZ   0x00400000lu
+#define FERR  0x00800000lu
+#define CMR   0x01000000lu
+#define CMROF 0x02000000lu
+#define CMTS  0x04000000lu
+#define CMTC  0x08000000lu
+#define RWRC  0x10000000lu
+#define BCZ   0x20000000lu
+#define BMERR 0x40000000lu
+#define DERR  0x80000000lu
+
+
+/* MXVR_INT_EN_0 Masks */
+
+#define NI2AEN  NI2A
+#define NA2IEN  NA2I
+#define SBU2LEN SBU2L
+#define SBL2UEN SBL2U
+#define PRUEN   PRU
+#define MPRUEN  MPRU
+#define DRUEN   DRU
+#define MDRUEN  MDRU
+#define SBUEN   SBU
+#define ATUEN   ATU
+#define FCZ0EN  FCZ0
+#define FCZ1EN  FCZ1
+#define PERREN  PERR
+#define MH2LEN  MH2L
+#define ML2HEN  ML2H
+#define WUPEN   WUP
+#define FU2LEN  FU2L
+#define FL2UEN  FL2U
+#define BU2LEN  BU2L
+#define BL2UEN  BL2U
+#define PCZEN   PCZ
+#define FERREN  FERR
+#define CMREN   CMR
+#define CMROFEN CMROF
+#define CMTSEN  CMTS
+#define CMTCEN  CMTC
+#define RWRCEN  RWRC
+#define BCZEN   BCZ
+#define BMERREN BMERR
+#define DERREN  DERR
+
+
+/* MXVR_INT_STAT_1 Masks */
+
+#define APR   0x00000004lu
+#define APROF 0x00000008lu
+#define APTS  0x00000040lu
+#define APTC  0x00000080lu
+#define APRCE 0x00000400lu
+#define APRPE 0x00000800lu
+
+#define HDONE0 0x00000001lu
+#define DONE0  0x00000002lu
+#define HDONE1 0x00000010lu
+#define DONE1  0x00000020lu
+#define HDONE2 0x00000100lu
+#define DONE2  0x00000200lu
+#define HDONE3 0x00001000lu
+#define DONE3  0x00002000lu
+#define HDONE4 0x00010000lu
+#define DONE4  0x00020000lu
+#define HDONE5 0x00100000lu
+#define DONE5  0x00200000lu
+#define HDONE6 0x01000000lu
+#define DONE6  0x02000000lu
+#define HDONE7 0x10000000lu
+#define DONE7  0x20000000lu
+
+#define DONEX(x) (0x00000002 << (4 * (x)))
+#define HDONEX(x) (0x00000001 << (4 * (x)))
+
+
+/* MXVR_INT_EN_1 Masks */
+
+#define APREN   APR
+#define APROFEN APROF
+#define APTSEN  APTS
+#define APTCEN  APTC
+#define APRCEEN APRCE
+#define APRPEEN APRPE
+
+#define HDONEEN0 HDONE0
+#define DONEEN0  DONE0
+#define HDONEEN1 HDONE1
+#define DONEEN1  DONE1
+#define HDONEEN2 HDONE2
+#define DONEEN2  DONE2
+#define HDONEEN3 HDONE3
+#define DONEEN3  DONE3
+#define HDONEEN4 HDONE4
+#define DONEEN4  DONE4
+#define HDONEEN5 HDONE5
+#define DONEEN5  DONE5
+#define HDONEEN6 HDONE6
+#define DONEEN6  DONE6
+#define HDONEEN7 HDONE7
+#define DONEEN7  DONE7
+
+#define DONEENX(x) (0x00000002 << (4 * (x)))
+#define HDONEENX(x) (0x00000001 << (4 * (x)))
+
+
+/* MXVR_STATE_0 Masks */
+
+#define NACT     0x00000001lu
+#define SBLOCK   0x00000002lu
+#define PFDLOCK  0x00000004lu
+#define PFDLOCK0 0x00000004lu /* legacy */
+#define PDD      0x00000008lu
+#define PDD0     0x00000008lu /* legacy */
+#define PVCO     0x00000010lu
+#define PVCO0    0x00000010lu /* legacy */
+#define PFDLOCK1 0x00000020lu /* legacy */
+#define PDD1     0x00000040lu /* legacy */
+#define PVCO1    0x00000080lu /* legacy */
+#define APBSY    0x00000100lu
+#define APARB    0x00000200lu
+#define APTX     0x00000400lu
+#define APRX     0x00000800lu
+#define CMBSY    0x00001000lu
+#define CMARB    0x00002000lu
+#define CMTX     0x00004000lu
+#define CMRX     0x00008000lu
+#define MRXONB   0x00010000lu
+#define RGSIP    0x00020000lu
+#define DALIP    0x00040000lu
+#define ALIP     0x00080000lu
+#define RRDIP    0x00100000lu
+#define RWRIP    0x00200000lu
+#define FLOCK    0x00400000lu
+#define BLOCK    0x00800000lu
+#define RSB      0x0F000000lu
+#define DERRNUM  0xF0000000lu
+
+
+/* MXVR_STATE_1 Masks */
+
+#define STXNUMB     0x0000000Flu
+#define SRXNUMB     0x000000F0lu
+#define APCONT      0x00000100lu
+#define DMAACTIVEX  0x00FF0000lu
+#define DMAACTIVE0  0x00010000lu
+#define DMAACTIVE1  0x00020000lu
+#define DMAACTIVE2  0x00040000lu
+#define DMAACTIVE3  0x00080000lu
+#define DMAACTIVE4  0x00100000lu
+#define DMAACTIVE5  0x00200000lu
+#define DMAACTIVE6  0x00400000lu
+#define DMAACTIVE7  0x00800000lu
+#define DMAPMENX    0xFF000000lu
+#define DMAPMEN0    0x01000000lu
+#define DMAPMEN1    0x02000000lu
+#define DMAPMEN2    0x04000000lu
+#define DMAPMEN3    0x08000000lu
+#define DMAPMEN4    0x10000000lu
+#define DMAPMEN5    0x20000000lu
+#define DMAPMEN6    0x40000000lu
+#define DMAPMEN7    0x80000000lu
+
+
+/* MXVR_POSITION Masks */
+
+#define PVALID       0x8000
+#define POSITION     0x003F
+
+
+/* MXVR_MAX_POSITION Masks */
+
+#define MPVALID      0x8000
+#define MPOSITION    0x003F
+
+
+/* MXVR_DELAY Masks */
+
+#define DVALID       0x8000
+#define DELAY        0x003F
+
+
+/* MXVR_MAX_DELAY Masks */
+
+#define MDVALID      0x8000
+#define MDELAY       0x003F
+
+
+/* MXVR_LADDR Masks */
+
+#define LVALID       0x80000000lu
+#define LADDR        0x0000FFFFlu
+
+
+/* MXVR_GADDR Masks */
+
+#define GVALID       0x8000
+#define GADDRL       0x00FF
+
+
+/* MXVR_AADDR Masks */
+
+#define AVALID       0x80000000lu
+#define AADDR        0x0000FFFFlu
+
+
+/* MXVR_ALLOC_0 Masks */
+
+#define CIU0         0x00000080lu
+#define CIU1         0x00008000lu
+#define CIU2         0x00800000lu
+#define CIU3         0x80000000lu
+
+#define CL0          0x0000007Flu
+#define CL1          0x00007F00lu
+#define CL2          0x007F0000lu
+#define CL3          0x7F000000lu
+
+
+/* MXVR_ALLOC_1 Masks */
+
+#define CIU4         0x00000080lu
+#define CIU5         0x00008000lu
+#define CIU6         0x00800000lu
+#define CIU7         0x80000000lu
+
+#define CL4          0x0000007Flu
+#define CL5          0x00007F00lu
+#define CL6          0x007F0000lu
+#define CL7          0x7F000000lu
+
+
+/* MXVR_ALLOC_2 Masks */
+
+#define CIU8         0x00000080lu
+#define CIU9         0x00008000lu
+#define CIU10        0x00800000lu
+#define CIU11        0x80000000lu
+
+#define CL8          0x0000007Flu
+#define CL9          0x00007F00lu
+#define CL10         0x007F0000lu
+#define CL11         0x7F000000lu
+
+
+/* MXVR_ALLOC_3 Masks */
+
+#define CIU12        0x00000080lu
+#define CIU13        0x00008000lu
+#define CIU14        0x00800000lu
+#define CIU15        0x80000000lu
+
+#define CL12         0x0000007Flu
+#define CL13         0x00007F00lu
+#define CL14         0x007F0000lu
+#define CL15         0x7F000000lu
+
+
+/* MXVR_ALLOC_4 Masks */
+
+#define CIU16        0x00000080lu
+#define CIU17        0x00008000lu
+#define CIU18        0x00800000lu
+#define CIU19        0x80000000lu
+
+#define CL16         0x0000007Flu
+#define CL17         0x00007F00lu
+#define CL18         0x007F0000lu
+#define CL19         0x7F000000lu
+
+
+/* MXVR_ALLOC_5 Masks */
+
+#define CIU20        0x00000080lu
+#define CIU21        0x00008000lu
+#define CIU22        0x00800000lu
+#define CIU23        0x80000000lu
+
+#define CL20         0x0000007Flu
+#define CL21         0x00007F00lu
+#define CL22         0x007F0000lu
+#define CL23         0x7F000000lu
+
+
+/* MXVR_ALLOC_6 Masks */
+
+#define CIU24        0x00000080lu
+#define CIU25        0x00008000lu
+#define CIU26        0x00800000lu
+#define CIU27        0x80000000lu
+
+#define CL24         0x0000007Flu
+#define CL25         0x00007F00lu
+#define CL26         0x007F0000lu
+#define CL27         0x7F000000lu
+
+
+/* MXVR_ALLOC_7 Masks */
+
+#define CIU28        0x00000080lu
+#define CIU29        0x00008000lu
+#define CIU30        0x00800000lu
+#define CIU31        0x80000000lu
+
+#define CL28         0x0000007Flu
+#define CL29         0x00007F00lu
+#define CL30         0x007F0000lu
+#define CL31         0x7F000000lu
+
+
+/* MXVR_ALLOC_8 Masks */
+
+#define CIU32        0x00000080lu
+#define CIU33        0x00008000lu
+#define CIU34        0x00800000lu
+#define CIU35        0x80000000lu
+
+#define CL32         0x0000007Flu
+#define CL33         0x00007F00lu
+#define CL34         0x007F0000lu
+#define CL35         0x7F000000lu
+
+
+/* MXVR_ALLOC_9 Masks */
+
+#define CIU36        0x00000080lu
+#define CIU37        0x00008000lu
+#define CIU38        0x00800000lu
+#define CIU39        0x80000000lu
+
+#define CL36         0x0000007Flu
+#define CL37         0x00007F00lu
+#define CL38         0x007F0000lu
+#define CL39         0x7F000000lu
+
+
+/* MXVR_ALLOC_10 Masks */
+
+#define CIU40        0x00000080lu
+#define CIU41        0x00008000lu
+#define CIU42        0x00800000lu
+#define CIU43        0x80000000lu
+
+#define CL40         0x0000007Flu
+#define CL41         0x00007F00lu
+#define CL42         0x007F0000lu
+#define CL43         0x7F000000lu
+
+
+/* MXVR_ALLOC_11 Masks */
+
+#define CIU44        0x00000080lu
+#define CIU45        0x00008000lu
+#define CIU46        0x00800000lu
+#define CIU47        0x80000000lu
+
+#define CL44         0x0000007Flu
+#define CL45         0x00007F00lu
+#define CL46         0x007F0000lu
+#define CL47         0x7F000000lu
+
+
+/* MXVR_ALLOC_12 Masks */
+
+#define CIU48        0x00000080lu
+#define CIU49        0x00008000lu
+#define CIU50        0x00800000lu
+#define CIU51        0x80000000lu
+
+#define CL48         0x0000007Flu
+#define CL49         0x00007F00lu
+#define CL50         0x007F0000lu
+#define CL51         0x7F000000lu
+
+
+/* MXVR_ALLOC_13 Masks */
+
+#define CIU52        0x00000080lu
+#define CIU53        0x00008000lu
+#define CIU54        0x00800000lu
+#define CIU55        0x80000000lu
+
+#define CL52         0x0000007Flu
+#define CL53         0x00007F00lu
+#define CL54         0x007F0000lu
+#define CL55         0x7F000000lu
+
+
+/* MXVR_ALLOC_14 Masks */
+
+#define CIU56        0x00000080lu
+#define CIU57        0x00008000lu
+#define CIU58        0x00800000lu
+#define CIU59        0x80000000lu
+
+#define CL56         0x0000007Flu
+#define CL57         0x00007F00lu
+#define CL58         0x007F0000lu
+#define CL59         0x7F000000lu
+
+
+/* MXVR_SYNC_LCHAN_0 Masks */
+
+#define LCHANPC0     0x0000000Flu
+#define LCHANPC1     0x000000F0lu
+#define LCHANPC2     0x00000F00lu
+#define LCHANPC3     0x0000F000lu
+#define LCHANPC4     0x000F0000lu
+#define LCHANPC5     0x00F00000lu
+#define LCHANPC6     0x0F000000lu
+#define LCHANPC7     0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_1 Masks */
+
+#define LCHANPC8     0x0000000Flu
+#define LCHANPC9     0x000000F0lu
+#define LCHANPC10    0x00000F00lu
+#define LCHANPC11    0x0000F000lu
+#define LCHANPC12    0x000F0000lu
+#define LCHANPC13    0x00F00000lu
+#define LCHANPC14    0x0F000000lu
+#define LCHANPC15    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_2 Masks */
+
+#define LCHANPC16    0x0000000Flu
+#define LCHANPC17    0x000000F0lu
+#define LCHANPC18    0x00000F00lu
+#define LCHANPC19    0x0000F000lu
+#define LCHANPC20    0x000F0000lu
+#define LCHANPC21    0x00F00000lu
+#define LCHANPC22    0x0F000000lu
+#define LCHANPC23    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_3 Masks */
+
+#define LCHANPC24    0x0000000Flu
+#define LCHANPC25    0x000000F0lu
+#define LCHANPC26    0x00000F00lu
+#define LCHANPC27    0x0000F000lu
+#define LCHANPC28    0x000F0000lu
+#define LCHANPC29    0x00F00000lu
+#define LCHANPC30    0x0F000000lu
+#define LCHANPC31    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_4 Masks */
+
+#define LCHANPC32    0x0000000Flu
+#define LCHANPC33    0x000000F0lu
+#define LCHANPC34    0x00000F00lu
+#define LCHANPC35    0x0000F000lu
+#define LCHANPC36    0x000F0000lu
+#define LCHANPC37    0x00F00000lu
+#define LCHANPC38    0x0F000000lu
+#define LCHANPC39    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_5 Masks */
+
+#define LCHANPC40    0x0000000Flu
+#define LCHANPC41    0x000000F0lu
+#define LCHANPC42    0x00000F00lu
+#define LCHANPC43    0x0000F000lu
+#define LCHANPC44    0x000F0000lu
+#define LCHANPC45    0x00F00000lu
+#define LCHANPC46    0x0F000000lu
+#define LCHANPC47    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_6 Masks */
+
+#define LCHANPC48    0x0000000Flu
+#define LCHANPC49    0x000000F0lu
+#define LCHANPC50    0x00000F00lu
+#define LCHANPC51    0x0000F000lu
+#define LCHANPC52    0x000F0000lu
+#define LCHANPC53    0x00F00000lu
+#define LCHANPC54    0x0F000000lu
+#define LCHANPC55    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_7 Masks */
+
+#define LCHANPC56    0x0000000Flu
+#define LCHANPC57    0x000000F0lu
+#define LCHANPC58    0x00000F00lu
+#define LCHANPC59    0x0000F000lu
+
+
+/* MXVR_DMAx_CONFIG Masks */
+
+#define MDMAEN      0x00000001lu
+#define DD          0x00000002lu
+#define LCHAN       0x000003C0lu
+#define BITSWAPEN   0x00000400lu
+#define BYSWAPEN    0x00000800lu
+#define MFLOW       0x00007000lu
+#define FIXEDPM     0x00080000lu
+#define STARTPAT    0x00300000lu
+#define STOPPAT     0x00C00000lu
+#define COUNTPOS    0x1C000000lu
+
+#define DD_TX       0x00000000lu
+#define DD_RX       0x00000002lu
+
+#define LCHAN_0     0x00000000lu
+#define LCHAN_1     0x00000040lu
+#define LCHAN_2     0x00000080lu
+#define LCHAN_3     0x000000C0lu
+#define LCHAN_4     0x00000100lu
+#define LCHAN_5     0x00000140lu
+#define LCHAN_6     0x00000180lu
+#define LCHAN_7     0x000001C0lu
+
+#define MFLOW_STOP  0x00000000lu
+#define MFLOW_AUTO  0x00001000lu
+#define MFLOW_PVC   0x00002000lu
+#define MFLOW_PSS   0x00003000lu
+#define MFLOW_PFC   0x00004000lu
+
+#define STARTPAT_0  0x00000000lu
+#define STARTPAT_1  0x00100000lu
+
+#define STOPPAT_0   0x00000000lu
+#define STOPPAT_1   0x00400000lu
+
+#define COUNTPOS_0  0x00000000lu
+#define COUNTPOS_1  0x04000000lu
+#define COUNTPOS_2  0x08000000lu
+#define COUNTPOS_3  0x0C000000lu
+#define COUNTPOS_4  0x10000000lu
+#define COUNTPOS_5  0x14000000lu
+#define COUNTPOS_6  0x18000000lu
+#define COUNTPOS_7  0x1C000000lu
+
+
+/* MXVR_AP_CTL Masks */
+
+#define STARTAP    0x00000001lu
+#define CANCELAP   0x00000002lu
+#define RESETAP    0x00000004lu
+#define APRBE0     0x00004000lu
+#define APRBE1     0x00008000lu
+#define APRBEX     0x0000C000lu
+
+
+/* MXVR_CM_CTL Masks */
+
+#define STARTCM    0x00000001lu
+#define CANCELCM   0x00000002lu
+#define CMRBEX     0xFFFF0000lu
+#define CMRBE0     0x00010000lu
+#define CMRBE1     0x00020000lu
+#define CMRBE2     0x00040000lu
+#define CMRBE3     0x00080000lu
+#define CMRBE4     0x00100000lu
+#define CMRBE5     0x00200000lu
+#define CMRBE6     0x00400000lu
+#define CMRBE7     0x00800000lu
+#define CMRBE8     0x01000000lu
+#define CMRBE9     0x02000000lu
+#define CMRBE10    0x04000000lu
+#define CMRBE11    0x08000000lu
+#define CMRBE12    0x10000000lu
+#define CMRBE13    0x20000000lu
+#define CMRBE14    0x40000000lu
+#define CMRBE15    0x80000000lu
+
+
+/* MXVR_PAT_DATA_x Masks */
+
+#define MATCH_DATA_0 0x000000FFlu
+#define MATCH_DATA_1 0x0000FF00lu
+#define MATCH_DATA_2 0x00FF0000lu
+#define MATCH_DATA_3 0xFF000000lu
+
+
+
+/* MXVR_PAT_EN_x Masks */
+
+#define MATCH_EN_0_0 0x00000001lu
+#define MATCH_EN_0_1 0x00000002lu
+#define MATCH_EN_0_2 0x00000004lu
+#define MATCH_EN_0_3 0x00000008lu
+#define MATCH_EN_0_4 0x00000010lu
+#define MATCH_EN_0_5 0x00000020lu
+#define MATCH_EN_0_6 0x00000040lu
+#define MATCH_EN_0_7 0x00000080lu
+
+#define MATCH_EN_1_0 0x00000100lu
+#define MATCH_EN_1_1 0x00000200lu
+#define MATCH_EN_1_2 0x00000400lu
+#define MATCH_EN_1_3 0x00000800lu
+#define MATCH_EN_1_4 0x00001000lu
+#define MATCH_EN_1_5 0x00002000lu
+#define MATCH_EN_1_6 0x00004000lu
+#define MATCH_EN_1_7 0x00008000lu
+
+#define MATCH_EN_2_0 0x00010000lu
+#define MATCH_EN_2_1 0x00020000lu
+#define MATCH_EN_2_2 0x00040000lu
+#define MATCH_EN_2_3 0x00080000lu
+#define MATCH_EN_2_4 0x00100000lu
+#define MATCH_EN_2_5 0x00200000lu
+#define MATCH_EN_2_6 0x00400000lu
+#define MATCH_EN_2_7 0x00800000lu
+
+#define MATCH_EN_3_0 0x01000000lu
+#define MATCH_EN_3_1 0x02000000lu
+#define MATCH_EN_3_2 0x04000000lu
+#define MATCH_EN_3_3 0x08000000lu
+#define MATCH_EN_3_4 0x10000000lu
+#define MATCH_EN_3_5 0x20000000lu
+#define MATCH_EN_3_6 0x40000000lu
+#define MATCH_EN_3_7 0x80000000lu
+
+
+/* MXVR_ROUTING_0 Masks */
+
+#define MUTE_CH0        0x00000080lu
+#define MUTE_CH1        0x00008000lu
+#define MUTE_CH2        0x00800000lu
+#define MUTE_CH3        0x80000000lu
+
+#define TX_CH0          0x0000007Flu
+#define TX_CH1          0x00007F00lu
+#define TX_CH2          0x007F0000lu
+#define TX_CH3          0x7F000000lu
+
+
+/* MXVR_ROUTING_1 Masks */
+
+#define MUTE_CH4        0x00000080lu
+#define MUTE_CH5        0x00008000lu
+#define MUTE_CH6        0x00800000lu
+#define MUTE_CH7        0x80000000lu
+
+#define TX_CH4          0x0000007Flu
+#define TX_CH5          0x00007F00lu
+#define TX_CH6          0x007F0000lu
+#define TX_CH7          0x7F000000lu
+
+
+/* MXVR_ROUTING_2 Masks */
+
+#define MUTE_CH8        0x00000080lu
+#define MUTE_CH9        0x00008000lu
+#define MUTE_CH10       0x00800000lu
+#define MUTE_CH11       0x80000000lu
+
+#define TX_CH8          0x0000007Flu
+#define TX_CH9          0x00007F00lu
+#define TX_CH10         0x007F0000lu
+#define TX_CH11         0x7F000000lu
+
+/* MXVR_ROUTING_3 Masks */
+
+#define MUTE_CH12       0x00000080lu
+#define MUTE_CH13       0x00008000lu
+#define MUTE_CH14       0x00800000lu
+#define MUTE_CH15       0x80000000lu
+
+#define TX_CH12         0x0000007Flu
+#define TX_CH13         0x00007F00lu
+#define TX_CH14         0x007F0000lu
+#define TX_CH15         0x7F000000lu
+
+
+/* MXVR_ROUTING_4 Masks */
+
+#define MUTE_CH16       0x00000080lu
+#define MUTE_CH17       0x00008000lu
+#define MUTE_CH18       0x00800000lu
+#define MUTE_CH19       0x80000000lu
+
+#define TX_CH16         0x0000007Flu
+#define TX_CH17         0x00007F00lu
+#define TX_CH18         0x007F0000lu
+#define TX_CH19         0x7F000000lu
+
+
+/* MXVR_ROUTING_5 Masks */
+
+#define MUTE_CH20       0x00000080lu
+#define MUTE_CH21       0x00008000lu
+#define MUTE_CH22       0x00800000lu
+#define MUTE_CH23       0x80000000lu
+
+#define TX_CH20         0x0000007Flu
+#define TX_CH21         0x00007F00lu
+#define TX_CH22         0x007F0000lu
+#define TX_CH23         0x7F000000lu
+
+
+/* MXVR_ROUTING_6 Masks */
+
+#define MUTE_CH24       0x00000080lu
+#define MUTE_CH25       0x00008000lu
+#define MUTE_CH26       0x00800000lu
+#define MUTE_CH27       0x80000000lu
+
+#define TX_CH24         0x0000007Flu
+#define TX_CH25         0x00007F00lu
+#define TX_CH26         0x007F0000lu
+#define TX_CH27         0x7F000000lu
+
+
+/* MXVR_ROUTING_7 Masks */
+
+#define MUTE_CH28       0x00000080lu
+#define MUTE_CH29       0x00008000lu
+#define MUTE_CH30       0x00800000lu
+#define MUTE_CH31       0x80000000lu
+
+#define TX_CH28         0x0000007Flu
+#define TX_CH29         0x00007F00lu
+#define TX_CH30         0x007F0000lu
+#define TX_CH31         0x7F000000lu
+
+
+/* MXVR_ROUTING_8 Masks */
+
+#define MUTE_CH32       0x00000080lu
+#define MUTE_CH33       0x00008000lu
+#define MUTE_CH34       0x00800000lu
+#define MUTE_CH35       0x80000000lu
+
+#define TX_CH32         0x0000007Flu
+#define TX_CH33         0x00007F00lu
+#define TX_CH34         0x007F0000lu
+#define TX_CH35         0x7F000000lu
+
+
+/* MXVR_ROUTING_9 Masks */
+
+#define MUTE_CH36       0x00000080lu
+#define MUTE_CH37       0x00008000lu
+#define MUTE_CH38       0x00800000lu
+#define MUTE_CH39       0x80000000lu
+
+#define TX_CH36         0x0000007Flu
+#define TX_CH37         0x00007F00lu
+#define TX_CH38         0x007F0000lu
+#define TX_CH39         0x7F000000lu
+
+
+/* MXVR_ROUTING_10 Masks */
+
+#define MUTE_CH40       0x00000080lu
+#define MUTE_CH41       0x00008000lu
+#define MUTE_CH42       0x00800000lu
+#define MUTE_CH43       0x80000000lu
+
+#define TX_CH40         0x0000007Flu
+#define TX_CH41         0x00007F00lu
+#define TX_CH42         0x007F0000lu
+#define TX_CH43         0x7F000000lu
+
+
+/* MXVR_ROUTING_11 Masks */
+
+#define MUTE_CH44       0x00000080lu
+#define MUTE_CH45       0x00008000lu
+#define MUTE_CH46       0x00800000lu
+#define MUTE_CH47       0x80000000lu
+
+#define TX_CH44         0x0000007Flu
+#define TX_CH45         0x00007F00lu
+#define TX_CH46         0x007F0000lu
+#define TX_CH47         0x7F000000lu
+
+
+/* MXVR_ROUTING_12 Masks */
+
+#define MUTE_CH48       0x00000080lu
+#define MUTE_CH49       0x00008000lu
+#define MUTE_CH50       0x00800000lu
+#define MUTE_CH51       0x80000000lu
+
+#define TX_CH48         0x0000007Flu
+#define TX_CH49         0x00007F00lu
+#define TX_CH50         0x007F0000lu
+#define TX_CH51         0x7F000000lu
+
+
+/* MXVR_ROUTING_13 Masks */
+
+#define MUTE_CH52       0x00000080lu
+#define MUTE_CH53       0x00008000lu
+#define MUTE_CH54       0x00800000lu
+#define MUTE_CH55       0x80000000lu
+
+#define TX_CH52         0x0000007Flu
+#define TX_CH53         0x00007F00lu
+#define TX_CH54         0x007F0000lu
+#define TX_CH55         0x7F000000lu
+
+
+/* MXVR_ROUTING_14 Masks */
+
+#define MUTE_CH56       0x00000080lu
+#define MUTE_CH57       0x00008000lu
+#define MUTE_CH58       0x00800000lu
+#define MUTE_CH59       0x80000000lu
+
+#define TX_CH56         0x0000007Flu
+#define TX_CH57         0x00007F00lu
+#define TX_CH58         0x007F0000lu
+#define TX_CH59         0x7F000000lu
+
+
+/* Control Message Receive Buffer (CMRB) Address Offsets */
+
+#define CMRB_STRIDE       0x00000016lu
+
+#define CMRB_DST_OFFSET   0x00000000lu
+#define CMRB_SRC_OFFSET   0x00000002lu
+#define CMRB_DATA_OFFSET  0x00000005lu
+
+
+/* Control Message Transmit Buffer (CMTB) Address Offsets */
+
+#define CMTB_PRIO_OFFSET    0x00000000lu
+#define CMTB_DST_OFFSET     0x00000002lu
+#define CMTB_SRC_OFFSET     0x00000004lu
+#define CMTB_TYPE_OFFSET    0x00000006lu
+#define CMTB_DATA_OFFSET    0x00000007lu
+
+#define CMTB_ANSWER_OFFSET  0x0000000Alu
+
+#define CMTB_STAT_N_OFFSET  0x00000018lu
+#define CMTB_STAT_A_OFFSET  0x00000016lu
+#define CMTB_STAT_D_OFFSET  0x0000000Elu
+#define CMTB_STAT_R_OFFSET  0x00000014lu
+#define CMTB_STAT_W_OFFSET  0x00000014lu
+#define CMTB_STAT_G_OFFSET  0x00000014lu
+
+
+/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
+
+#define APRB_STRIDE       0x00000400lu
+
+#define APRB_DST_OFFSET   0x00000000lu
+#define APRB_LEN_OFFSET   0x00000002lu
+#define APRB_SRC_OFFSET   0x00000004lu
+#define APRB_DATA_OFFSET  0x00000006lu
+
+
+/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
+
+#define APTB_PRIO_OFFSET  0x00000000lu
+#define APTB_DST_OFFSET   0x00000002lu
+#define APTB_LEN_OFFSET   0x00000004lu
+#define APTB_SRC_OFFSET   0x00000006lu
+#define APTB_DATA_OFFSET  0x00000008lu
+
+
+/* Remote Read Buffer (RRDB) Address Offsets */
+
+#define RRDB_WADDR_OFFSET 0x00000100lu
+#define RRDB_WLEN_OFFSET  0x00000101lu
+
+
+
+/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
+/* CAN_CONTROL Masks                                     */
+#define SRS                     0x0001  /* Software Reset */
+#define DNM                     0x0002  /* Device Net Mode */
+#define ABO                     0x0004  /* Auto-Bus On Enable */
+#define WBA                     0x0010  /* Wake-Up On CAN Bus Activity Enable */
+#define SMR                     0x0020  /* Sleep Mode Request */
+#define CSR                     0x0040  /* CAN Suspend Mode Request */
+#define CCR                     0x0080  /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks                                      */
+#define WT                      0x0001  /* TX Warning Flag */
+#define WR                      0x0002  /* RX Warning Flag */
+#define EP                      0x0004  /* Error Passive Mode */
+#define EBO                     0x0008  /* Error Bus Off Mode */
+#define CSA                     0x0040  /* Suspend Mode Acknowledge */
+#define CCA                     0x0080  /* Configuration Mode Acknowledge */
+#define MBPTR           0x1F00  /* Mailbox Pointer */
+#define TRM                     0x4000  /* Transmit Mode */
+#define REC                     0x8000  /* Receive Mode */
+
+/* CAN_CLOCK Masks               */
+#define BRP                     0x03FF  /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks                              */
+#define TSEG1           0x000F  /* Time Segment 1 */
+#define TSEG2           0x0070  /* Time Segment 2 */
+#define SAM                     0x0080  /* Sampling */
+#define SJW                     0x0300  /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks                               */
+#define DEC                     0x0001  /* Disable CAN Error Counters */
+#define DRI                     0x0002  /* Disable CAN RX Input */
+#define DTO                     0x0004  /* Disable CAN TX Output */
+#define DIL                     0x0008  /* Disable CAN Internal Loop */
+#define MAA                     0x0010  /* Mode Auto-Acknowledge Enable */
+#define MRB                     0x0020  /* Mode Read Back Enable */
+#define CDE                     0x8000  /* CAN Debug Enable */
+
+/* CAN_CEC Masks                         */
+#define RXECNT          0x00FF  /* Receive Error Counter */
+#define TXECNT          0xFF00  /* Transmit Error Counter */
+
+/* CAN_INTR Masks                                */
+#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt */
+#define MBRIF           MBRIRQ  /* legacy */
+#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt */
+#define MBTIF           MBTIRQ  /* legacy */
+#define GIRQ            0x0004  /* Global Interrupt */
+#define SMACK           0x0008  /* Sleep Mode Acknowledge */
+#define CANTX           0x0040  /* CAN TX Bus Value */
+#define CANRX           0x0080  /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks                   */
+#define DFC                     0xFFFF  /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID          0x1FFC  /* Base Identifier       */
+#define IDE                     0x2000  /* Identifier Extension */
+#define RTR                     0x4000  /* Remote Frame Transmission Request */
+#define AME                     0x8000  /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV                     0xFFFF  /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC                     0x000F  /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks                                         */
+#define DFM                     0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID          0x1FFC  /* Base Identifier               */
+#define AMIDE           0x2000  /* Acceptance Mask ID Extension Enable */
+#define FMD                     0x4000  /* Full Mask Data Field Enable */
+#define FDF                     0x8000  /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks                 */
+#define MC0                     0x0001  /* Enable Mailbox 0 */
+#define MC1                     0x0002  /* Enable Mailbox 1 */
+#define MC2                     0x0004  /* Enable Mailbox 2 */
+#define MC3                     0x0008  /* Enable Mailbox 3 */
+#define MC4                     0x0010  /* Enable Mailbox 4 */
+#define MC5                     0x0020  /* Enable Mailbox 5 */
+#define MC6                     0x0040  /* Enable Mailbox 6 */
+#define MC7                     0x0080  /* Enable Mailbox 7 */
+#define MC8                     0x0100  /* Enable Mailbox 8 */
+#define MC9                     0x0200  /* Enable Mailbox 9 */
+#define MC10            0x0400  /* Enable Mailbox 10 */
+#define MC11            0x0800  /* Enable Mailbox 11 */
+#define MC12            0x1000  /* Enable Mailbox 12 */
+#define MC13            0x2000  /* Enable Mailbox 13 */
+#define MC14            0x4000  /* Enable Mailbox 14 */
+#define MC15            0x8000  /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks                 */
+#define MC16            0x0001  /* Enable Mailbox 16 */
+#define MC17            0x0002  /* Enable Mailbox 17 */
+#define MC18            0x0004  /* Enable Mailbox 18 */
+#define MC19            0x0008  /* Enable Mailbox 19 */
+#define MC20            0x0010  /* Enable Mailbox 20 */
+#define MC21            0x0020  /* Enable Mailbox 21 */
+#define MC22            0x0040  /* Enable Mailbox 22 */
+#define MC23            0x0080  /* Enable Mailbox 23 */
+#define MC24            0x0100  /* Enable Mailbox 24 */
+#define MC25            0x0200  /* Enable Mailbox 25 */
+#define MC26            0x0400  /* Enable Mailbox 26 */
+#define MC27            0x0800  /* Enable Mailbox 27 */
+#define MC28            0x1000  /* Enable Mailbox 28 */
+#define MC29            0x2000  /* Enable Mailbox 29 */
+#define MC30            0x4000  /* Enable Mailbox 30 */
+#define MC31            0x8000  /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks                                         */
+#define MD0                     0x0001  /* Enable Mailbox 0 For Receive */
+#define MD1                     0x0002  /* Enable Mailbox 1 For Receive */
+#define MD2                     0x0004  /* Enable Mailbox 2 For Receive */
+#define MD3                     0x0008  /* Enable Mailbox 3 For Receive */
+#define MD4                     0x0010  /* Enable Mailbox 4 For Receive */
+#define MD5                     0x0020  /* Enable Mailbox 5 For Receive */
+#define MD6                     0x0040  /* Enable Mailbox 6 For Receive */
+#define MD7                     0x0080  /* Enable Mailbox 7 For Receive */
+#define MD8                     0x0100  /* Enable Mailbox 8 For Receive */
+#define MD9                     0x0200  /* Enable Mailbox 9 For Receive */
+#define MD10            0x0400  /* Enable Mailbox 10 For Receive */
+#define MD11            0x0800  /* Enable Mailbox 11 For Receive */
+#define MD12            0x1000  /* Enable Mailbox 12 For Receive */
+#define MD13            0x2000  /* Enable Mailbox 13 For Receive */
+#define MD14            0x4000  /* Enable Mailbox 14 For Receive */
+#define MD15            0x8000  /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks                                         */
+#define MD16            0x0001  /* Enable Mailbox 16 For Receive */
+#define MD17            0x0002  /* Enable Mailbox 17 For Receive */
+#define MD18            0x0004  /* Enable Mailbox 18 For Receive */
+#define MD19            0x0008  /* Enable Mailbox 19 For Receive */
+#define MD20            0x0010  /* Enable Mailbox 20 For Receive */
+#define MD21            0x0020  /* Enable Mailbox 21 For Receive */
+#define MD22            0x0040  /* Enable Mailbox 22 For Receive */
+#define MD23            0x0080  /* Enable Mailbox 23 For Receive */
+#define MD24            0x0100  /* Enable Mailbox 24 For Receive */
+#define MD25            0x0200  /* Enable Mailbox 25 For Receive */
+#define MD26            0x0400  /* Enable Mailbox 26 For Receive */
+#define MD27            0x0800  /* Enable Mailbox 27 For Receive */
+#define MD28            0x1000  /* Enable Mailbox 28 For Receive */
+#define MD29            0x2000  /* Enable Mailbox 29 For Receive */
+#define MD30            0x4000  /* Enable Mailbox 30 For Receive */
+#define MD31            0x8000  /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks                                        */
+#define RMP0            0x0001  /* RX Message Pending In Mailbox 0 */
+#define RMP1            0x0002  /* RX Message Pending In Mailbox 1 */
+#define RMP2            0x0004  /* RX Message Pending In Mailbox 2 */
+#define RMP3            0x0008  /* RX Message Pending In Mailbox 3 */
+#define RMP4            0x0010  /* RX Message Pending In Mailbox 4 */
+#define RMP5            0x0020  /* RX Message Pending In Mailbox 5 */
+#define RMP6            0x0040  /* RX Message Pending In Mailbox 6 */
+#define RMP7            0x0080  /* RX Message Pending In Mailbox 7 */
+#define RMP8            0x0100  /* RX Message Pending In Mailbox 8 */
+#define RMP9            0x0200  /* RX Message Pending In Mailbox 9 */
+#define RMP10           0x0400  /* RX Message Pending In Mailbox 10 */
+#define RMP11           0x0800  /* RX Message Pending In Mailbox 11 */
+#define RMP12           0x1000  /* RX Message Pending In Mailbox 12 */
+#define RMP13           0x2000  /* RX Message Pending In Mailbox 13 */
+#define RMP14           0x4000  /* RX Message Pending In Mailbox 14 */
+#define RMP15           0x8000  /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks                                        */
+#define RMP16           0x0001  /* RX Message Pending In Mailbox 16 */
+#define RMP17           0x0002  /* RX Message Pending In Mailbox 17 */
+#define RMP18           0x0004  /* RX Message Pending In Mailbox 18 */
+#define RMP19           0x0008  /* RX Message Pending In Mailbox 19 */
+#define RMP20           0x0010  /* RX Message Pending In Mailbox 20 */
+#define RMP21           0x0020  /* RX Message Pending In Mailbox 21 */
+#define RMP22           0x0040  /* RX Message Pending In Mailbox 22 */
+#define RMP23           0x0080  /* RX Message Pending In Mailbox 23 */
+#define RMP24           0x0100  /* RX Message Pending In Mailbox 24 */
+#define RMP25           0x0200  /* RX Message Pending In Mailbox 25 */
+#define RMP26           0x0400  /* RX Message Pending In Mailbox 26 */
+#define RMP27           0x0800  /* RX Message Pending In Mailbox 27 */
+#define RMP28           0x1000  /* RX Message Pending In Mailbox 28 */
+#define RMP29           0x2000  /* RX Message Pending In Mailbox 29 */
+#define RMP30           0x4000  /* RX Message Pending In Mailbox 30 */
+#define RMP31           0x8000  /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks                                        */
+#define RML0            0x0001  /* RX Message Lost In Mailbox 0 */
+#define RML1            0x0002  /* RX Message Lost In Mailbox 1 */
+#define RML2            0x0004  /* RX Message Lost In Mailbox 2 */
+#define RML3            0x0008  /* RX Message Lost In Mailbox 3 */
+#define RML4            0x0010  /* RX Message Lost In Mailbox 4 */
+#define RML5            0x0020  /* RX Message Lost In Mailbox 5 */
+#define RML6            0x0040  /* RX Message Lost In Mailbox 6 */
+#define RML7            0x0080  /* RX Message Lost In Mailbox 7 */
+#define RML8            0x0100  /* RX Message Lost In Mailbox 8 */
+#define RML9            0x0200  /* RX Message Lost In Mailbox 9 */
+#define RML10           0x0400  /* RX Message Lost In Mailbox 10 */
+#define RML11           0x0800  /* RX Message Lost In Mailbox 11 */
+#define RML12           0x1000  /* RX Message Lost In Mailbox 12 */
+#define RML13           0x2000  /* RX Message Lost In Mailbox 13 */
+#define RML14           0x4000  /* RX Message Lost In Mailbox 14 */
+#define RML15           0x8000  /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks                                        */
+#define RML16           0x0001  /* RX Message Lost In Mailbox 16 */
+#define RML17           0x0002  /* RX Message Lost In Mailbox 17 */
+#define RML18           0x0004  /* RX Message Lost In Mailbox 18 */
+#define RML19           0x0008  /* RX Message Lost In Mailbox 19 */
+#define RML20           0x0010  /* RX Message Lost In Mailbox 20 */
+#define RML21           0x0020  /* RX Message Lost In Mailbox 21 */
+#define RML22           0x0040  /* RX Message Lost In Mailbox 22 */
+#define RML23           0x0080  /* RX Message Lost In Mailbox 23 */
+#define RML24           0x0100  /* RX Message Lost In Mailbox 24 */
+#define RML25           0x0200  /* RX Message Lost In Mailbox 25 */
+#define RML26           0x0400  /* RX Message Lost In Mailbox 26 */
+#define RML27           0x0800  /* RX Message Lost In Mailbox 27 */
+#define RML28           0x1000  /* RX Message Lost In Mailbox 28 */
+#define RML29           0x2000  /* RX Message Lost In Mailbox 29 */
+#define RML30           0x4000  /* RX Message Lost In Mailbox 30 */
+#define RML31           0x8000  /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks                                                                                                       */
+#define OPSS0           0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1           0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2           0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3           0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4           0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5           0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6           0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7           0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8           0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9           0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks                                                                                                       */
+#define OPSS16          0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17          0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18          0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19          0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20          0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21          0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22          0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23          0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24          0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25          0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks                                                        */
+#define TRR0            0x0001  /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1            0x0002  /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2            0x0004  /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3            0x0008  /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4            0x0010  /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5            0x0020  /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6            0x0040  /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7            0x0080  /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8            0x0100  /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9            0x0200  /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10           0x0400  /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11           0x0800  /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12           0x1000  /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13           0x2000  /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14           0x4000  /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15           0x8000  /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks                                                        */
+#define TRR16           0x0001  /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17           0x0002  /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18           0x0004  /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19           0x0008  /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20           0x0010  /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21           0x0020  /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22           0x0040  /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23           0x0080  /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24           0x0100  /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25           0x0200  /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26           0x0400  /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27           0x0800  /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28           0x1000  /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29           0x2000  /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30           0x4000  /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31           0x8000  /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks                                                */
+#define TRS0            0x0001  /* Remote Frame Request For Mailbox 0 */
+#define TRS1            0x0002  /* Remote Frame Request For Mailbox 1 */
+#define TRS2            0x0004  /* Remote Frame Request For Mailbox 2 */
+#define TRS3            0x0008  /* Remote Frame Request For Mailbox 3 */
+#define TRS4            0x0010  /* Remote Frame Request For Mailbox 4 */
+#define TRS5            0x0020  /* Remote Frame Request For Mailbox 5 */
+#define TRS6            0x0040  /* Remote Frame Request For Mailbox 6 */
+#define TRS7            0x0080  /* Remote Frame Request For Mailbox 7 */
+#define TRS8            0x0100  /* Remote Frame Request For Mailbox 8 */
+#define TRS9            0x0200  /* Remote Frame Request For Mailbox 9 */
+#define TRS10           0x0400  /* Remote Frame Request For Mailbox 10 */
+#define TRS11           0x0800  /* Remote Frame Request For Mailbox 11 */
+#define TRS12           0x1000  /* Remote Frame Request For Mailbox 12 */
+#define TRS13           0x2000  /* Remote Frame Request For Mailbox 13 */
+#define TRS14           0x4000  /* Remote Frame Request For Mailbox 14 */
+#define TRS15           0x8000  /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks                                                */
+#define TRS16           0x0001  /* Remote Frame Request For Mailbox 16 */
+#define TRS17           0x0002  /* Remote Frame Request For Mailbox 17 */
+#define TRS18           0x0004  /* Remote Frame Request For Mailbox 18 */
+#define TRS19           0x0008  /* Remote Frame Request For Mailbox 19 */
+#define TRS20           0x0010  /* Remote Frame Request For Mailbox 20 */
+#define TRS21           0x0020  /* Remote Frame Request For Mailbox 21 */
+#define TRS22           0x0040  /* Remote Frame Request For Mailbox 22 */
+#define TRS23           0x0080  /* Remote Frame Request For Mailbox 23 */
+#define TRS24           0x0100  /* Remote Frame Request For Mailbox 24 */
+#define TRS25           0x0200  /* Remote Frame Request For Mailbox 25 */
+#define TRS26           0x0400  /* Remote Frame Request For Mailbox 26 */
+#define TRS27           0x0800  /* Remote Frame Request For Mailbox 27 */
+#define TRS28           0x1000  /* Remote Frame Request For Mailbox 28 */
+#define TRS29           0x2000  /* Remote Frame Request For Mailbox 29 */
+#define TRS30           0x4000  /* Remote Frame Request For Mailbox 30 */
+#define TRS31           0x8000  /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks                                         */
+#define AA0                     0x0001  /* Aborted Message In Mailbox 0 */
+#define AA1                     0x0002  /* Aborted Message In Mailbox 1 */
+#define AA2                     0x0004  /* Aborted Message In Mailbox 2 */
+#define AA3                     0x0008  /* Aborted Message In Mailbox 3 */
+#define AA4                     0x0010  /* Aborted Message In Mailbox 4 */
+#define AA5                     0x0020  /* Aborted Message In Mailbox 5 */
+#define AA6                     0x0040  /* Aborted Message In Mailbox 6 */
+#define AA7                     0x0080  /* Aborted Message In Mailbox 7 */
+#define AA8                     0x0100  /* Aborted Message In Mailbox 8 */
+#define AA9                     0x0200  /* Aborted Message In Mailbox 9 */
+#define AA10            0x0400  /* Aborted Message In Mailbox 10 */
+#define AA11            0x0800  /* Aborted Message In Mailbox 11 */
+#define AA12            0x1000  /* Aborted Message In Mailbox 12 */
+#define AA13            0x2000  /* Aborted Message In Mailbox 13 */
+#define AA14            0x4000  /* Aborted Message In Mailbox 14 */
+#define AA15            0x8000  /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks                                         */
+#define AA16            0x0001  /* Aborted Message In Mailbox 16 */
+#define AA17            0x0002  /* Aborted Message In Mailbox 17 */
+#define AA18            0x0004  /* Aborted Message In Mailbox 18 */
+#define AA19            0x0008  /* Aborted Message In Mailbox 19 */
+#define AA20            0x0010  /* Aborted Message In Mailbox 20 */
+#define AA21            0x0020  /* Aborted Message In Mailbox 21 */
+#define AA22            0x0040  /* Aborted Message In Mailbox 22 */
+#define AA23            0x0080  /* Aborted Message In Mailbox 23 */
+#define AA24            0x0100  /* Aborted Message In Mailbox 24 */
+#define AA25            0x0200  /* Aborted Message In Mailbox 25 */
+#define AA26            0x0400  /* Aborted Message In Mailbox 26 */
+#define AA27            0x0800  /* Aborted Message In Mailbox 27 */
+#define AA28            0x1000  /* Aborted Message In Mailbox 28 */
+#define AA29            0x2000  /* Aborted Message In Mailbox 29 */
+#define AA30            0x4000  /* Aborted Message In Mailbox 30 */
+#define AA31            0x8000  /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks                                                 */
+#define TA0                     0x0001  /* Transmit Successful From Mailbox 0 */
+#define TA1                     0x0002  /* Transmit Successful From Mailbox 1 */
+#define TA2                     0x0004  /* Transmit Successful From Mailbox 2 */
+#define TA3                     0x0008  /* Transmit Successful From Mailbox 3 */
+#define TA4                     0x0010  /* Transmit Successful From Mailbox 4 */
+#define TA5                     0x0020  /* Transmit Successful From Mailbox 5 */
+#define TA6                     0x0040  /* Transmit Successful From Mailbox 6 */
+#define TA7                     0x0080  /* Transmit Successful From Mailbox 7 */
+#define TA8                     0x0100  /* Transmit Successful From Mailbox 8 */
+#define TA9                     0x0200  /* Transmit Successful From Mailbox 9 */
+#define TA10            0x0400  /* Transmit Successful From Mailbox 10 */
+#define TA11            0x0800  /* Transmit Successful From Mailbox 11 */
+#define TA12            0x1000  /* Transmit Successful From Mailbox 12 */
+#define TA13            0x2000  /* Transmit Successful From Mailbox 13 */
+#define TA14            0x4000  /* Transmit Successful From Mailbox 14 */
+#define TA15            0x8000  /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks                                                 */
+#define TA16            0x0001  /* Transmit Successful From Mailbox 16 */
+#define TA17            0x0002  /* Transmit Successful From Mailbox 17 */
+#define TA18            0x0004  /* Transmit Successful From Mailbox 18 */
+#define TA19            0x0008  /* Transmit Successful From Mailbox 19 */
+#define TA20            0x0010  /* Transmit Successful From Mailbox 20 */
+#define TA21            0x0020  /* Transmit Successful From Mailbox 21 */
+#define TA22            0x0040  /* Transmit Successful From Mailbox 22 */
+#define TA23            0x0080  /* Transmit Successful From Mailbox 23 */
+#define TA24            0x0100  /* Transmit Successful From Mailbox 24 */
+#define TA25            0x0200  /* Transmit Successful From Mailbox 25 */
+#define TA26            0x0400  /* Transmit Successful From Mailbox 26 */
+#define TA27            0x0800  /* Transmit Successful From Mailbox 27 */
+#define TA28            0x1000  /* Transmit Successful From Mailbox 28 */
+#define TA29            0x2000  /* Transmit Successful From Mailbox 29 */
+#define TA30            0x4000  /* Transmit Successful From Mailbox 30 */
+#define TA31            0x8000  /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks                                        */
+#define TDPTR           0x001F  /* Mailbox To Temporarily Disable */
+#define TDA                     0x0040  /* Temporary Disable Acknowledge */
+#define TDR                     0x0080  /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks                                                                                        */
+#define RFH0            0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1            0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2            0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3            0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4            0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5            0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6            0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7            0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8            0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9            0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks                                                                                        */
+#define RFH16           0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17           0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18           0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19           0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20           0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21           0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22           0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23           0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24           0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25           0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks                                              */
+#define MBTIF0          0x0001  /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1          0x0002  /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2          0x0004  /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3          0x0008  /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4          0x0010  /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5          0x0020  /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6          0x0040  /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7          0x0080  /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8          0x0100  /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9          0x0200  /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10         0x0400  /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11         0x0800  /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12         0x1000  /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13         0x2000  /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14         0x4000  /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15         0x8000  /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks                                              */
+#define MBTIF16         0x0001  /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17         0x0002  /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18         0x0004  /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19         0x0008  /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20         0x0010  /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21         0x0020  /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22         0x0040  /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23         0x0080  /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24         0x0100  /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25         0x0200  /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26         0x0400  /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27         0x0800  /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28         0x1000  /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29         0x2000  /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30         0x4000  /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31         0x8000  /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks                                              */
+#define MBRIF0          0x0001  /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1          0x0002  /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2          0x0004  /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3          0x0008  /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4          0x0010  /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5          0x0020  /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6          0x0040  /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7          0x0080  /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8          0x0100  /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9          0x0200  /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10         0x0400  /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11         0x0800  /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12         0x1000  /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13         0x2000  /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14         0x4000  /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15         0x8000  /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks                                              */
+#define MBRIF16         0x0001  /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17         0x0002  /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18         0x0004  /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19         0x0008  /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20         0x0010  /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21         0x0020  /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22         0x0040  /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23         0x0080  /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24         0x0100  /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25         0x0200  /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26         0x0400  /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27         0x0800  /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28         0x1000  /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29         0x2000  /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30         0x4000  /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31         0x8000  /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks                                       */
+#define MBIM0           0x0001  /* Enable Interrupt For Mailbox 0 */
+#define MBIM1           0x0002  /* Enable Interrupt For Mailbox 1 */
+#define MBIM2           0x0004  /* Enable Interrupt For Mailbox 2 */
+#define MBIM3           0x0008  /* Enable Interrupt For Mailbox 3 */
+#define MBIM4           0x0010  /* Enable Interrupt For Mailbox 4 */
+#define MBIM5           0x0020  /* Enable Interrupt For Mailbox 5 */
+#define MBIM6           0x0040  /* Enable Interrupt For Mailbox 6 */
+#define MBIM7           0x0080  /* Enable Interrupt For Mailbox 7 */
+#define MBIM8           0x0100  /* Enable Interrupt For Mailbox 8 */
+#define MBIM9           0x0200  /* Enable Interrupt For Mailbox 9 */
+#define MBIM10          0x0400  /* Enable Interrupt For Mailbox 10 */
+#define MBIM11          0x0800  /* Enable Interrupt For Mailbox 11 */
+#define MBIM12          0x1000  /* Enable Interrupt For Mailbox 12 */
+#define MBIM13          0x2000  /* Enable Interrupt For Mailbox 13 */
+#define MBIM14          0x4000  /* Enable Interrupt For Mailbox 14 */
+#define MBIM15          0x8000  /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks                                       */
+#define MBIM16          0x0001  /* Enable Interrupt For Mailbox 16 */
+#define MBIM17          0x0002  /* Enable Interrupt For Mailbox 17 */
+#define MBIM18          0x0004  /* Enable Interrupt For Mailbox 18 */
+#define MBIM19          0x0008  /* Enable Interrupt For Mailbox 19 */
+#define MBIM20          0x0010  /* Enable Interrupt For Mailbox 20 */
+#define MBIM21          0x0020  /* Enable Interrupt For Mailbox 21 */
+#define MBIM22          0x0040  /* Enable Interrupt For Mailbox 22 */
+#define MBIM23          0x0080  /* Enable Interrupt For Mailbox 23 */
+#define MBIM24          0x0100  /* Enable Interrupt For Mailbox 24 */
+#define MBIM25          0x0200  /* Enable Interrupt For Mailbox 25 */
+#define MBIM26          0x0400  /* Enable Interrupt For Mailbox 26 */
+#define MBIM27          0x0800  /* Enable Interrupt For Mailbox 27 */
+#define MBIM28          0x1000  /* Enable Interrupt For Mailbox 28 */
+#define MBIM29          0x2000  /* Enable Interrupt For Mailbox 29 */
+#define MBIM30          0x4000  /* Enable Interrupt For Mailbox 30 */
+#define MBIM31          0x8000  /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks                                                                         */
+#define EWTIM           0x0001  /* Enable TX Error Count Interrupt */
+#define EWRIM           0x0002  /* Enable RX Error Count Interrupt */
+#define EPIM            0x0004  /* Enable Error-Passive Mode Interrupt */
+#define BOIM            0x0008  /* Enable Bus Off Interrupt */
+#define WUIM            0x0010  /* Enable Wake-Up Interrupt */
+#define UIAIM           0x0020  /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM            0x0040  /* Enable Abort Acknowledge Interrupt */
+#define RMLIM           0x0080  /* Enable RX Message Lost Interrupt */
+#define UCEIM           0x0100  /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM           0x0200  /* Enable External Trigger Output Interrupt */
+#define ADIM            0x0400  /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks                                                                 */
+#define EWTIS           0x0001  /* TX Error Count IRQ Status */
+#define EWRIS           0x0002  /* RX Error Count IRQ Status */
+#define EPIS            0x0004  /* Error-Passive Mode IRQ Status */
+#define BOIS            0x0008  /* Bus Off IRQ Status */
+#define WUIS            0x0010  /* Wake-Up IRQ Status */
+#define UIAIS           0x0020  /* Access To Unimplemented Address IRQ Status */
+#define AAIS            0x0040  /* Abort Acknowledge IRQ Status */
+#define RMLIS           0x0080  /* RX Message Lost IRQ Status */
+#define UCEIS           0x0100  /* Universal Counter Overflow IRQ Status */
+#define EXTIS           0x0200  /* External Trigger Output IRQ Status */
+#define ADIS            0x0400  /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks                                                                 */
+#define EWTIF           0x0001  /* TX Error Count IRQ Flag */
+#define EWRIF           0x0002  /* RX Error Count IRQ Flag */
+#define EPIF            0x0004  /* Error-Passive Mode IRQ Flag */
+#define BOIF            0x0008  /* Bus Off IRQ Flag      */
+#define WUIF            0x0010  /* Wake-Up IRQ Flag      */
+#define UIAIF           0x0020  /* Access To Unimplemented Address IRQ Flag */
+#define AAIF            0x0040  /* Abort Acknowledge IRQ Flag */
+#define RMLIF           0x0080  /* RX Message Lost IRQ Flag */
+#define UCEIF           0x0100  /* Universal Counter Overflow IRQ Flag */
+#define EXTIF           0x0200  /* External Trigger Output IRQ Flag */
+#define ADIF            0x0400  /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks                                                               */
+#define UCCNF           0x000F  /* Universal Counter Mode */
+#define UC_STAMP        0x0001  /*              Timestamp Mode */
+#define UC_WDOG         0x0002  /*              Watchdog Mode */
+#define UC_AUTOTX       0x0003  /*              Auto-Transmit Mode */
+#define UC_ERROR        0x0006  /*              CAN Error Frame Count */
+#define UC_OVER         0x0007  /*              CAN Overload Frame Count */
+#define UC_LOST         0x0008  /*              Arbitration Lost During TX Count */
+#define UC_AA           0x0009  /*              TX Abort Count */
+#define UC_TA           0x000A  /*              TX Successful Count */
+#define UC_REJECT       0x000B  /*              RX Message Rejected Count */
+#define UC_RML          0x000C  /*              RX Message Lost Count */
+#define UC_RX           0x000D  /*              Total Successful RX Messages Count */
+#define UC_RMP          0x000E  /*              Successful RX W/Matching ID Count */
+#define UC_ALL          0x000F  /*              Correct Message On CAN Bus Line Count */
+#define UCRC            0x0020  /* Universal Counter Reload/Clear */
+#define UCCT            0x0040  /* Universal Counter CAN Trigger */
+#define UCE                     0x0080  /* Universal Counter Enable */
+
+/* CAN_ESR Masks                         */
+#define ACKE            0x0004  /* Acknowledge Error */
+#define SER                     0x0008  /* Stuff Error */
+#define CRCE            0x0010  /* CRC Error */
+#define SA0                     0x0020  /* Stuck At Dominant Error */
+#define BEF                     0x0040  /* Bit Error Flag */
+#define FER                     0x0080  /* Form Error Flag */
+
+/* CAN_EWR Masks                                         */
+#define EWLREC          0x00FF  /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC          0xFF00  /* TX Error Count Limit (For EWTIS) */
+
+#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h
new file mode 100644
index 000000000000..eb05cacbf4d3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/dma.h
@@ -0,0 +1,41 @@
+/* mach/dma.h - arch-specific DMA defines
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define CH_PPI                  0
+#define CH_SPORT0_RX            1
+#define CH_SPORT0_TX            2
+#define CH_SPORT1_RX            3
+#define CH_SPORT1_TX            4
+#define CH_SPI0                 5
+#define CH_UART0_RX             6
+#define CH_UART0_TX             7
+#define CH_SPORT2_RX            8
+#define CH_SPORT2_TX            9
+#define CH_SPORT3_RX            10
+#define CH_SPORT3_TX            11
+#define CH_SPI1                 14
+#define CH_SPI2                 15
+#define CH_UART1_RX             16
+#define CH_UART1_TX             17
+#define CH_UART2_RX             18
+#define CH_UART2_TX             19
+
+#define CH_MEM_STREAM0_DEST     20
+#define CH_MEM_STREAM0_SRC      21
+#define CH_MEM_STREAM1_DEST     22
+#define CH_MEM_STREAM1_SRC      23
+#define CH_MEM_STREAM2_DEST     24
+#define CH_MEM_STREAM2_SRC      25
+#define CH_MEM_STREAM3_DEST     26
+#define CH_MEM_STREAM3_SRC      27
+
+#define MAX_DMA_CHANNELS 28
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
new file mode 100644
index 000000000000..30f4f723f7cc
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -0,0 +1,79 @@
+/*
+ * File: arch/blackfin/mach-bf538/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+        /* FIXME:
+         * For now only support PORTF GPIOs.
+         * PORT C,D and E are for peripheral usage only
+         */
+#define MAX_BLACKFIN_GPIOS 16
+
+#define GPIO_PF0        0       /* PF */
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PC0        16      /* PC */
+#define GPIO_PC1        17
+#define GPIO_PC4        20
+#define GPIO_PC5        21
+#define GPIO_PC6        22
+#define GPIO_PC7        23
+#define GPIO_PC8        24
+#define GPIO_PC9        25
+#define GPIO_PD0        32      /* PD */
+#define GPIO_PD1        33
+#define GPIO_PD2        34
+#define GPIO_PD3        35
+#define GPIO_PD4        36
+#define GPIO_PD5        37
+#define GPIO_PD6        38
+#define GPIO_PD7        39
+#define GPIO_PD8        40
+#define GPIO_PD9        41
+#define GPIO_PD10       42
+#define GPIO_PD11       43
+#define GPIO_PD12       44
+#define GPIO_PD13       45
+#define GPIO_PE0        48      /* PE */
+#define GPIO_PE1        49
+#define GPIO_PE2        50
+#define GPIO_PE3        51
+#define GPIO_PE4        52
+#define GPIO_PE5        53
+#define GPIO_PE6        54
+#define GPIO_PE7        55
+#define GPIO_PE8        56
+#define GPIO_PE9        57
+#define GPIO_PE10       58
+#define GPIO_PE11       59
+#define GPIO_PE12       60
+#define GPIO_PE13       61
+#define GPIO_PE14       62
+#define GPIO_PE15       63
+
+#define PORT_F GPIO_PF0
+#define PORT_C GPIO_PC0
+#define PORT_D GPIO_PD0
+#define PORT_E GPIO_PE0
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
new file mode 100644
index 000000000000..fdc87fe2c174
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -0,0 +1,211 @@
+/*
+ * file:        include/asm-blackfin/mach-bf538/irq.h
+ * based on:    include/asm-blackfin/mach-bf537/irq.h
+ * author:      Michael Hennerich (michael.hennerich@analog.com)
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _BF538_IRQ_H_
+#define _BF538_IRQ_H_
+
+/*
+ * Interrupt source definitions
+        Event Source    Core Event Name
+        Core        Emulation               **
+        Events         (highest priority)  EMU         0
+        Reset                   RST         1
+        NMI                     NMI         2
+        Exception               EVX         3
+        Reserved                --          4
+        Hardware Error          IVHW        5
+        Core Timer              IVTMR       6 *
+
+        .....
+
+         Software Interrupt 1    IVG14       31
+         Software Interrupt 2    --
+         (lowest priority)  IVG15       32 *
+*/
+
+#define NR_PERI_INTS    (2 * 32)
+
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU                 0       /* Emulation */
+#define IRQ_RST                 1       /* reset */
+#define IRQ_NMI                 2       /* Non Maskable */
+#define IRQ_EVX                 3       /* Exception */
+#define IRQ_UNUSED              4       /* - unused interrupt */
+#define IRQ_HWERR               5       /* Hardware Error */
+#define IRQ_CORETMR             6       /* Core timer */
+
+#define BFIN_IRQ(x)             ((x) + 7)
+
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
+#define IRQ_PPI_ERROR           BFIN_IRQ(2)     /* PPI Error */
+#define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Status */
+#define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Status */
+#define IRQ_SPI0_ERROR          BFIN_IRQ(5)     /* SPI0 Status */
+#define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART0 Status */
+#define IRQ_RTC                 BFIN_IRQ(7)     /* RTC */
+#define IRQ_PPI                 BFIN_IRQ(8)     /* DMA Channel 0 (PPI) */
+#define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* DMA 1 Channel (SPORT0 RX) */
+#define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* DMA 2 Channel (SPORT0 TX) */
+#define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* DMA 3 Channel (SPORT1 RX) */
+#define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* DMA 4 Channel (SPORT1 TX) */
+#define IRQ_SPI0                BFIN_IRQ(13)    /* DMA 5 Channel (SPI0) */
+#define IRQ_UART0_RX            BFIN_IRQ(14)    /* DMA 6 Channel (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(15)    /* DMA 7 Channel (UART0 TX) */
+#define IRQ_TIMER0              BFIN_IRQ(16)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(17)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(18)    /* Timer 2 */
+#define IRQ_PORTF_INTA          BFIN_IRQ(19)    /* Port F Interrupt A */
+#define IRQ_PORTF_INTB          BFIN_IRQ(20)    /* Port F Interrupt B */
+#define IRQ_MEM0_DMA0           BFIN_IRQ(21)    /* MDMA0 Stream 0 */
+#define IRQ_MEM0_DMA1           BFIN_IRQ(22)    /* MDMA0 Stream 1 */
+#define IRQ_WATCH               BFIN_IRQ(23)    /* Software Watchdog Timer */
+#define IRQ_DMA1_ERROR          BFIN_IRQ(24)    /* DMA Error 1 (generic) */
+#define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Status */
+#define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Status */
+#define IRQ_SPI1_ERROR          BFIN_IRQ(28)    /* SPI1 Status */
+#define IRQ_SPI2_ERROR          BFIN_IRQ(29)    /* SPI2 Status */
+#define IRQ_UART1_ERROR         BFIN_IRQ(30)    /* UART1 Status */
+#define IRQ_UART2_ERROR         BFIN_IRQ(31)    /* UART2 Status */
+#define IRQ_CAN_ERROR           BFIN_IRQ(32)    /* CAN Status (Error) Interrupt */
+#define IRQ_SPORT2_RX           BFIN_IRQ(33)    /* DMA 8 Channel (SPORT2 RX) */
+#define IRQ_SPORT2_TX           BFIN_IRQ(34)    /* DMA 9 Channel (SPORT2 TX) */
+#define IRQ_SPORT3_RX           BFIN_IRQ(35)    /* DMA 10 Channel (SPORT3 RX) */
+#define IRQ_SPORT3_TX           BFIN_IRQ(36)    /* DMA 11 Channel (SPORT3 TX) */
+#define IRQ_SPI1                BFIN_IRQ(39)    /* DMA 14 Channel (SPI1) */
+#define IRQ_SPI2                BFIN_IRQ(40)    /* DMA 15 Channel (SPI2) */
+#define IRQ_UART1_RX            BFIN_IRQ(41)    /* DMA 16 Channel (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(42)    /* DMA 17 Channel (UART1 TX) */
+#define IRQ_UART2_RX            BFIN_IRQ(43)    /* DMA 18 Channel (UART2 RX) */
+#define IRQ_UART2_TX            BFIN_IRQ(44)    /* DMA 19 Channel (UART2 TX) */
+#define IRQ_TWI0                BFIN_IRQ(45)    /* TWI0 */
+#define IRQ_TWI1                BFIN_IRQ(46)    /* TWI1 */
+#define IRQ_CAN_RX              BFIN_IRQ(47)    /* CAN Receive Interrupt */
+#define IRQ_CAN_TX              BFIN_IRQ(48)    /* CAN Transmit Interrupt */
+#define IRQ_MEM1_DMA0           BFIN_IRQ(49)    /* MDMA1 Stream 0 */
+#define IRQ_MEM1_DMA1           BFIN_IRQ(50)    /* MDMA1 Stream 1 */
+
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+
+#define IRQ_PF0         71
+#define IRQ_PF1         72
+#define IRQ_PF2         73
+#define IRQ_PF3         74
+#define IRQ_PF4         75
+#define IRQ_PF5         76
+#define IRQ_PF6         77
+#define IRQ_PF7         78
+#define IRQ_PF8         79
+#define IRQ_PF9         80
+#define IRQ_PF10        81
+#define IRQ_PF11        82
+#define IRQ_PF12        83
+#define IRQ_PF13        84
+#define IRQ_PF14        85
+#define IRQ_PF15        86
+
+#define GPIO_IRQ_BASE   IRQ_PF0
+
+#define NR_IRQS     (IRQ_PF15+1)
+
+#define IVG7            7
+#define IVG8            8
+#define IVG9            9
+#define IVG10           10
+#define IVG11           11
+#define IVG12           12
+#define IVG13           13
+#define IVG14           14
+#define IVG15           15
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS      0
+#define IRQ_DMA0_ERROR_POS      4
+#define IRQ_PPI_ERROR_POS       8
+#define IRQ_SPORT0_ERROR_POS    12
+#define IRQ_SPORT1_ERROR_POS    16
+#define IRQ_SPI0_ERROR_POS      20
+#define IRQ_UART0_ERROR_POS     24
+#define IRQ_RTC_POS             28
+
+/* IAR1 BIT FIELDS */
+#define IRQ_PPI_POS             0
+#define IRQ_SPORT0_RX_POS       4
+#define IRQ_SPORT0_TX_POS       8
+#define IRQ_SPORT1_RX_POS       12
+#define IRQ_SPORT1_TX_POS       16
+#define IRQ_SPI0_POS            20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_TIMER0_POS          0
+#define IRQ_TIMER1_POS          4
+#define IRQ_TIMER2_POS          8
+#define IRQ_PORTF_INTA_POS      12
+#define IRQ_PORTF_INTB_POS      16
+#define IRQ_MEM0_DMA0_POS       20
+#define IRQ_MEM0_DMA1_POS       24
+#define IRQ_WATCH_POS           28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_DMA1_ERROR_POS      0
+#define IRQ_SPORT2_ERROR_POS    4
+#define IRQ_SPORT3_ERROR_POS    8
+#define IRQ_SPI1_ERROR_POS      16
+#define IRQ_SPI2_ERROR_POS      20
+#define IRQ_UART1_ERROR_POS     24
+#define IRQ_UART2_ERROR_POS     28
+
+/* IAR4 BIT FIELDS */
+#define IRQ_CAN_ERROR_POS       0
+#define IRQ_SPORT2_RX_POS       4
+#define IRQ_SPORT2_TX_POS       8
+#define IRQ_SPORT3_RX_POS       12
+#define IRQ_SPORT3_TX_POS       16
+#define IRQ_SPI1_POS            28
+
+/* IAR5 BIT FIELDS */
+#define IRQ_SPI2_POS            0
+#define IRQ_UART1_RX_POS        4
+#define IRQ_UART1_TX_POS        8
+#define IRQ_UART2_RX_POS        12
+#define IRQ_UART2_TX_POS        16
+#define IRQ_TWI0_POS            20
+#define IRQ_TWI1_POS            24
+#define IRQ_CAN_RX_POS          28
+
+/* IAR6 BIT FIELDS */
+#define IRQ_CAN_TX_POS          0
+#define IRQ_MEM1_DMA0_POS       4
+#define IRQ_MEM1_DMA1_POS       8
+#endif                          /* _BF538_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h
new file mode 100644
index 000000000000..76811966690e
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/mem_map.h
@@ -0,0 +1,113 @@
+/*
+ * File:         include/asm-blackfin/mach-bf538/mem_map.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MEM_MAP_538_H_
+#define _MEM_MAP_538_H_
+
+#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
+
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+#define BOOT_ROM_LENGTH         0x400
+
+/* Level 1 Memory */
+
+#ifdef CONFIG_BFIN_ICACHE
+#define BFIN_ICACHESIZE (16*1024)
+#else
+#define BFIN_ICACHESIZE (0*1024)
+#endif
+
+/* Memory Map for ADSP-BF538/9 processors */
+
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#ifdef CONFIG_BFIN_ICACHE
+#define L1_CODE_LENGTH      (0x14000 - 0x4000)
+#else
+#define L1_CODE_LENGTH      0x14000
+#endif
+
+#ifdef CONFIG_BFIN_DCACHE
+
+#ifdef CONFIG_BFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BFIN_DCACHESIZE (16*1024)
+#define BFIN_DSUPBANKS  1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BFIN_DCACHESIZE (32*1024)
+#define BFIN_DSUPBANKS  2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BFIN_DCACHESIZE (0*1024)
+#define BFIN_DSUPBANKS  0
+#endif /*CONFIG_BFIN_DCACHE*/
+
+
+/* Level 2 Memory - none */
+
+#define L2_START        0
+#define L2_LENGTH       0
+
+/* Scratch Pad Memory */
+
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
+#endif                          /* _MEM_MAP_538_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
new file mode 100644
index 000000000000..1e031b588b47
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -0,0 +1,106 @@
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
+
+#define P_TMR2          (P_DONTCARE)
+#define P_TMR1          (P_DONTCARE)
+#define P_TMR0          (P_DONTCARE)
+#define P_TMRCLK        (P_DONTCARE)
+#define P_PPI0_CLK      (P_DONTCARE)
+#define P_PPI0_FS1      (P_DONTCARE)
+#define P_PPI0_FS2      (P_DONTCARE)
+
+#define P_TWI0_SCL      (P_DONTCARE)
+#define P_TWI0_SDA      (P_DONTCARE)
+#define P_TWI1_SCL      (P_DONTCARE)
+#define P_TWI1_SDA      (P_DONTCARE)
+
+#define P_SPORT1_TSCLK  (P_DONTCARE)
+#define P_SPORT1_RSCLK  (P_DONTCARE)
+#define P_SPORT0_TSCLK  (P_DONTCARE)
+#define P_SPORT0_RSCLK  (P_DONTCARE)
+#define P_SPORT1_DRSEC  (P_DONTCARE)
+#define P_SPORT1_RFS    (P_DONTCARE)
+#define P_SPORT1_DTPRI  (P_DONTCARE)
+#define P_SPORT1_DTSEC  (P_DONTCARE)
+#define P_SPORT1_TFS    (P_DONTCARE)
+#define P_SPORT1_DRPRI  (P_DONTCARE)
+#define P_SPORT0_DRSEC  (P_DONTCARE)
+#define P_SPORT0_RFS    (P_DONTCARE)
+#define P_SPORT0_DTPRI  (P_DONTCARE)
+#define P_SPORT0_DTSEC  (P_DONTCARE)
+#define P_SPORT0_TFS    (P_DONTCARE)
+#define P_SPORT0_DRPRI  (P_DONTCARE)
+
+#define P_UART0_RX      (P_DONTCARE)
+#define P_UART0_TX      (P_DONTCARE)
+
+#define P_SPI0_MOSI     (P_DONTCARE)
+#define P_SPI0_MISO     (P_DONTCARE)
+#define P_SPI0_SCK      (P_DONTCARE)
+
+#define P_PPI0_D0       (P_DONTCARE)
+#define P_PPI0_D1       (P_DONTCARE)
+#define P_PPI0_D2       (P_DONTCARE)
+#define P_PPI0_D3       (P_DONTCARE)
+
+#define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PC0))
+#define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PC1))
+
+#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PD0))
+#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PD1))
+#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PD2))
+#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PD3))
+#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD4))
+#define P_SPI2_MOSI     (P_DEFINED | P_IDENT(GPIO_PD5))
+#define P_SPI2_MISO     (P_DEFINED | P_IDENT(GPIO_PD6))
+#define P_SPI2_SCK      (P_DEFINED | P_IDENT(GPIO_PD7))
+#define P_SPI2_SS       (P_DEFINED | P_IDENT(GPIO_PD8))
+#define P_SPI2_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD9))
+#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PD10))
+#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PD11))
+#define P_UART2_RX      (P_DEFINED | P_IDENT(GPIO_PD12))
+#define P_UART2_TX      (P_DEFINED | P_IDENT(GPIO_PD13))
+
+#define P_SPORT2_RSCLK  (P_DEFINED | P_IDENT(GPIO_PE0))
+#define P_SPORT2_RFS    (P_DEFINED | P_IDENT(GPIO_PE1))
+#define P_SPORT2_DRPRI  (P_DEFINED | P_IDENT(GPIO_PE2))
+#define P_SPORT2_DRSEC  (P_DEFINED | P_IDENT(GPIO_PE3))
+#define P_SPORT2_TSCLK  (P_DEFINED | P_IDENT(GPIO_PE4))
+#define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PE5))
+#define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PE6))
+#define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PE7))
+#define P_SPORT3_RSCLK  (P_DEFINED | P_IDENT(GPIO_PE8))
+#define P_SPORT3_RFS    (P_DEFINED | P_IDENT(GPIO_PE9))
+#define P_SPORT3_DRPRI  (P_DEFINED | P_IDENT(GPIO_PE10))
+#define P_SPORT3_DRSEC  (P_DEFINED | P_IDENT(GPIO_PE11))
+#define P_SPORT3_TSCLK  (P_DEFINED | P_IDENT(GPIO_PE12))
+#define P_SPORT3_TFS    (P_DEFINED | P_IDENT(GPIO_PE13))
+#define P_SPORT3_DTPRI  (P_DEFINED | P_IDENT(GPIO_PE14))
+#define P_SPORT3_DTSEC  (P_DEFINED | P_IDENT(GPIO_PE15))
+
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF8))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF9))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF10))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF11))
+
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF15))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF14))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF13))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF12))
+#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
+#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
+
+#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
new file mode 100644
index 000000000000..70d17e550e05
--- /dev/null
+++ b/arch/blackfin/mach-bf538/ints-priority.c
@@ -0,0 +1,94 @@
+/*
+ * File:         arch/blackfin/mach-bf538/ints-priority.c
+ * Based on:     arch/blackfin/mach-bf533/ints-priority.c
+ * Author:       Michael Hennerich
+ *
+ * Created:
+ * Description:  Set up the interrupt priorities
+ *
+ * Modified:
+ *               Copyright 2008 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+void __init program_IAR(void)
+{
+
+        /* Program the IAR0 Register with the configured priority */
+        bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
+                        ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
+                        ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
+                        ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
+                        ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
+                        ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
+
+        bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
+                        ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
+                        ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
+                        ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
+                        ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
+                        ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
+                        ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
+                        ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
+
+        bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                        ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
+                        ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                        ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
+                        ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
+                        ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
+                        ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
+                        ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
+
+        bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
+                        ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
+                        ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
+                        ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
+                        ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
+
+        bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
+                        ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
+                        ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
+                        ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
+                        ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
+                        ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
+
+        bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
+                        ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
+                        ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
+                        ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
+                        ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
+                        ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
+                        ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
+                        ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
+
+        bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
+                        ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
+                        ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
+
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 1bfcd8f646ab..dcf657159051 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -250,7 +250,7 @@ config IRQ_OTPSEC
         default 11
 config IRQ_TIMER0
         int "IRQ_TIMER0"
-        default 11
+        default 8
 config IRQ_TIMER1
         int "IRQ_TIMER1"
         default 11
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
index 68e5478e95a9..56994b675f9c 100644
--- a/arch/blackfin/mach-bf548/Makefile
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -2,6 +2,4 @@
 # arch/blackfin/mach-bf537/Makefile
 #
 
-extra-y := head.o
-
 obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 24192aaa9275..f53ad682530b 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -32,6 +32,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/irq.h>
@@ -42,6 +43,7 @@
 #include <asm/gpio.h>
 #include <asm/nand.h>
 #include <asm/portmux.h>
+#include <asm/bfin_sdh.h>
 #include <mach/bf54x_keys.h>
 #include <asm/dpmc.h>
 #include <linux/input.h>
@@ -186,44 +188,107 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir1_device = {
+        .name = "bfin_sir",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR2
+static struct resource bfin_sir2_resources[] = {
         {
                 .start = 0xFFC02100,
                 .end = 0xFFC021FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART2_RX,
+                .end = IRQ_UART2_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART2_RX,
+                .end = CH_UART2_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir2_device = {
+        .name = "bfin_sir",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(bfin_sir2_resources),
+        .resource = bfin_sir2_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR3
+static struct resource bfin_sir3_resources[] = {
         {
                 .start = 0xFFC03100,
                 .end = 0xFFC031FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART3_RX,
+                .end = IRQ_UART3_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART3_RX,
+                .end = CH_UART3_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
-
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir3_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 3,
+        .num_resources = ARRAY_SIZE(bfin_sir3_resources),
+        .resource = bfin_sir3_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 static struct resource smsc911x_resources[] = {
@@ -271,8 +336,8 @@ static struct musb_hdrc_config musb_config = {
         .dyn_fifo       = 0,
         .soft_con       = 1,
         .dma            = 1,
-        .num_eps        = 7,
-        .dma_channels   = 7,
+        .num_eps        = 8,
+        .dma_channels   = 8,
         .gpio_vrsel     = GPIO_PH6,
 };
 
@@ -302,6 +367,19 @@ static struct platform_device musb_device = {
 };
 #endif
 
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
 #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
 static struct resource bfin_atapi_resources[] = {
         {
@@ -372,9 +450,58 @@ static struct platform_device bf5xx_nand_device = {
 #endif
 
 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+static struct bfin_sd_host bfin_sdh_data = {
+        .dma_chan = CH_SDH,
+        .irq_int0 = IRQ_SDH_MASK0,
+        .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
+};
+
 static struct platform_device bf54x_sdh_device = {
         .name = "bfin-sdh",
         .id = 0,
+        .dev = {
+                .platform_data = &bfin_sdh_data,
+        },
+};
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition para_partitions[] = {
+        {
+                .name       = "bootloader(nor)",
+                .size       = 0x40000,
+                .offset     = 0,
+        }, {
+                .name       = "linux kernel(nor)",
+                .size       = 0x400000,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "file system(nor)",
+                .size       = MTDPART_SIZ_FULL,
+                .offset     = MTDPART_OFS_APPEND,
+        }
+};
+
+static struct physmap_flash_data para_flash_data = {
+        .width      = 2,
+        .parts      = para_partitions,
+        .nr_parts   = ARRAY_SIZE(para_partitions),
+};
+
+static struct resource para_flash_resource = {
+        .start = 0x20000000,
+        .end   = 0x207fffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device para_flash_device = {
+        .name          = "physmap-flash",
+        .id            = 0,
+        .dev = {
+                .platform_data = &para_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &para_flash_resource,
 };
 #endif
 
@@ -642,7 +769,18 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
+#ifdef CONFIG_BFIN_SIR2
+        &bfin_sir2_device,
+#endif
+#ifdef CONFIG_BFIN_SIR3
+        &bfin_sir3_device,
+#endif
 #endif
 
 #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -679,7 +817,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
-/*      &i2c_bfin_twi0_device, */
+        &i2c_bfin_twi0_device,
 #if !defined(CONFIG_BF542)
         &i2c_bfin_twi1_device,
 #endif
@@ -688,6 +826,12 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
         &bfin_device_gpiokeys,
 #endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &para_flash_device,
+#endif
+
+        &bfin_gpios_device,
 };
 
 static int __init cm_bf548_init(void)
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 5288187a3ace..309c16014cae 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -45,6 +45,7 @@
 #include <asm/nand.h>
 #include <asm/dpmc.h>
 #include <asm/portmux.h>
+#include <asm/bfin_sdh.h>
 #include <mach/bf54x_keys.h>
 #include <linux/input.h>
 #include <linux/spi/ad7877.h>
@@ -52,16 +53,16 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADSP-BF548-EZKIT";
+const char bfin_board_name[] = "ADI BF548-EZKIT";
 
 /*
  *  Driver needs to know address, irq and flag pin.
  */
 
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
         [0] = {
-                .name   = "isp1761-regs",
                 .start  = 0x2C0C0000,
                 .end    = 0x2C0C0000 + 0xfffff,
                 .flags  = IORESOURCE_MEM,
@@ -73,32 +74,25 @@ static struct resource bfin_isp1761_resources[] = {
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(bfin_isp1761_resources[1].start, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -262,44 +256,107 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
         {
                 .start = 0xFFC02000,
                 .end = 0xFFC020FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir1_device = {
+        .name = "bfin_sir",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR2
+static struct resource bfin_sir2_resources[] = {
         {
                 .start = 0xFFC02100,
                 .end = 0xFFC021FF,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = IRQ_UART2_RX,
+                .end = IRQ_UART2_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART2_RX,
+                .end = CH_UART2_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir2_device = {
+        .name = "bfin_sir",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(bfin_sir2_resources),
+        .resource = bfin_sir2_resources,
+};
 #endif
 #ifdef CONFIG_BFIN_SIR3
+static struct resource bfin_sir3_resources[] = {
         {
                 .start = 0xFFC03100,
                 .end = 0xFFC031FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART3_RX,
+                .end = IRQ_UART3_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART3_RX,
+                .end = CH_UART3_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
-
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir3_device = {
         .name = "bfin_sir",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .id = 3,
+        .num_resources = ARRAY_SIZE(bfin_sir3_resources),
+        .resource = bfin_sir3_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 static struct resource smsc911x_resources[] = {
@@ -347,8 +404,8 @@ static struct musb_hdrc_config musb_config = {
         .dyn_fifo       = 0,
         .soft_con       = 1,
         .dma            = 1,
-        .num_eps        = 7,
-        .dma_channels   = 7,
+        .num_eps        = 8,
+        .dma_channels   = 8,
         .gpio_vrsel     = GPIO_PE7,
 };
 
@@ -448,9 +505,19 @@ static struct platform_device bf5xx_nand_device = {
 #endif
 
 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+
+static struct bfin_sd_host bfin_sdh_data = {
+        .dma_chan = CH_SDH,
+        .irq_int0 = IRQ_SDH_MASK0,
+        .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
+};
+
 static struct platform_device bf54x_sdh_device = {
         .name = "bfin-sdh",
         .id = 0,
+        .dev = {
+                .platform_data = &bfin_sdh_data,
+        },
 };
 #endif
 
@@ -589,7 +656,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 {
         .modalias               = "ad7877",
         .platform_data          = &bfin_ad7877_ts_info,
-        .irq                    = IRQ_PJ11,     /* newer boards (Rev 1.4+) use IRQ_PB4 */
+        .irq                    = IRQ_PB4,      /* old boards (<=Rev 1.3) use IRQ_PJ11 */
         .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
         .bus_num                = 0,
         .chip_select            = 2,
@@ -812,7 +879,18 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
+#ifdef CONFIG_BFIN_SIR2
+        &bfin_sir2_device,
+#endif
+#ifdef CONFIG_BFIN_SIR3
+        &bfin_sir3_device,
+#endif
 #endif
 
 #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
@@ -827,6 +905,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &musb_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
         &bfin_atapi_device,
 #endif
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 74730eb8ae1b..535980652bf6 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -32,7 +32,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
deleted file mode 100644
index 93b361dff27b..000000000000
--- a/arch/blackfin/mach-bf548/head.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf548/head.S
- * Based on:     arch/blackfin/mach-bf537/head.S
- * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
- *
- * Created:      1998
- * Description:  Startup code for Blackfin BF548
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#include <asm/clocks.h>
-#include <mach/mem_init.h>
-#endif
-
-.section .l1.text
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-ENTRY(_start_dma_code)
-
-        /* Enable PHY CLK buffer output */
-        p0.h = hi(VR_CTL);
-        p0.l = lo(VR_CTL);
-        r0.l = w[p0];
-        bitset(r0, 14);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.h = hi(SIC_IWR0);
-        p0.l = lo(SIC_IWR0);
-        r0.l = 0x1;
-        r0.h = 0x0;
-        [p0] = r0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        p0.h = hi(PLL_LOCKCNT);
-        p0.l = lo(PLL_LOCKCNT);
-        r0 = 0x300(Z);
-        w[p0] = r0.l;
-        ssync;
-
-        /* enable self refresh via SRREQ */
-        P2.H = hi(EBIU_RSTCTL);
-        P2.L = lo(EBIU_RSTCTL);
-        R0 = [P2];
-        BITSET (R0, 3);
-        [P2] = R0;
-        SSYNC;
-
-        /* wait for SRACK bit to be set */
-.LSRR_MODE:
-        R0 = [P2];
-        CC = BITTST(R0, 4);
-        if !CC JUMP .LSRR_MODE;
-
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-#ifdef ANOMALY_05000265
-        BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
-#endif
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-
-.Lcheck_again:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again;
-
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-
-        /* disable self refresh by clearing SRREQ */
-        P2.H = hi(EBIU_RSTCTL);
-        P2.L = lo(EBIU_RSTCTL);
-        R0 = [P2];
-        CC = BITTST(R0, 0);
-        if CC jump .Lskipddrrst;
-        BITSET (R0, 0);
-.Lskipddrrst:
-        BITCLR (R0, 3);
-        [P2] = R0;
-        SSYNC;
-
-        p0.l = lo(EBIU_DDRCTL0);
-        p0.h = hi(EBIU_DDRCTL0);
-        r0.l = lo(mem_DDRCTL0);
-        r0.h = hi(mem_DDRCTL0);
-        [p0] = r0;
-        ssync;
-
-        p0.l = lo(EBIU_DDRCTL1);
-        p0.h = hi(EBIU_DDRCTL1);
-        r0.l = lo(mem_DDRCTL1);
-        r0.h = hi(mem_DDRCTL1);
-        [p0] = r0;
-        ssync;
-
-        p0.l = lo(EBIU_DDRCTL2);
-        p0.h = hi(EBIU_DDRCTL2);
-        r0.l = lo(mem_DDRCTL2);
-        r0.h = hi(mem_DDRCTL2);
-        [p0] = r0;
-        ssync;
-
-        RTS;
-ENDPROC(_start_dma_code)
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 816b09278f62..3b5430999f4f 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -157,6 +157,8 @@
 #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
 /* Software System Reset Corrupts PLL_LOCKCNT Register */
 #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
@@ -173,5 +175,8 @@
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
index 49f9b403d458..f0e569984810 100644
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ b/arch/blackfin/mach-bf548/include/mach/bf548.h
@@ -122,7 +122,7 @@
 #endif
 
 #ifndef CPU
-#error Unknown CPU type - This kernel doesn't seem to be configured properly
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 #endif
 
 #endif  /* __MACH_BF48_H__  */
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
deleted file mode 100644
index c41f9cf00268..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER_SET)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_LSR(port)    bfin_read16((port)->membase + OFFSET_LSR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_SET_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_SET), v)
-#define SIR_UART_CLEAR_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LSR(port, v)  bfin_write16(((port)->membase + OFFSET_LSR), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_CLEAR_LSR(port)  bfin_write16(((port)->membase + OFFSET_LSR), -1)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-        CH_UART2_RX,
-        CH_UART2_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-        CH_UART3_RX,
-        CH_UART3_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR2
-        ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR3
-        ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index d6ee74ac0460..0c0e3e2c3c21 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -111,7 +111,7 @@
 
 /* UART 0*/
 
-/* DMA Channnel */
+/* DMA Channel */
 #define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
 #define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
 #define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 57ac8cb9b1f6..6e636c418cb0 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -34,7 +34,6 @@
 #include <asm/blackfin.h>
 
 #include "defBF54x_base.h"
-#include <asm/system.h>
 
 /* ************************************************************** */
 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
@@ -43,63 +42,9 @@
 /* PLL Registers */
 
 #define bfin_read_PLL_CTL()             bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
 #define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
 #define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
@@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
 #define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        iwr2 = bfin_read32(SIC_IWR2);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+        bfin_write32(SIC_IWR2, 0);
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        bfin_write32(SIC_IWR2, iwr2);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SIC_IWR0);
+        iwr1 = bfin_read32(SIC_IWR1);
+        iwr2 = bfin_read32(SIC_IWR2);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+        bfin_write32(SIC_IWR1, 0);
+        bfin_write32(SIC_IWR2, 0);
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SIC_IWR0, iwr0);
+        bfin_write32(SIC_IWR1, iwr1);
+        bfin_write32(SIC_IWR2, iwr2);
+        local_irq_restore_hw(flags);
+}
+
 #endif /* _CDEF_BF54X_H */
 
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
index 36a2ef7e7849..a30d242c7398 100644
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -1,32 +1,8 @@
-/*
- * file:         include/asm-blackfin/mach-bf548/dma.h
- * based on:
- * author:
+/* mach/dma.h - arch-specific DMA defines
  *
- * created:
- * description:
- *      system mmr register map
- * rev:
+ * Copyright 2004-2008 Analog Devices Inc.
  *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_DMA_H_
@@ -71,6 +47,6 @@
 #define CH_MEM_STREAM3_DEST     30
 #define CH_MEM_STREAM3_SRC      31
 
-#define MAX_BLACKFIN_DMA_CHANNEL 32
+#define MAX_DMA_CHANNELS 32
 
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index ad380d1f5872..60299a71e090 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -158,7 +158,7 @@ Events         (highest priority)  EMU         0
 #define IRQ_PINT2               BFIN_IRQ(94)    /* PINT2 Interrupt */
 #define IRQ_PINT3               BFIN_IRQ(95)    /* PINT3 Interrupt */
 
-#define SYS_IRQS                IRQ_PINT3
+#define SYS_IRQS                IRQ_PINT3
 
 #define BFIN_PA_IRQ(x)          ((x) + SYS_IRQS + 1)
 #define IRQ_PA0                 BFIN_PA_IRQ(0)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x)   (1000*1000*1000/x)
-
-#if (CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(1)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRCD        DDR_TRCD(3)
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tWR         DDR_TWR(2)
-#define DDR_tMRD        DDR_TMRD(2)
-#define DDR_tRP         DDR_TRP(3)
-#define DDR_tRAS        DDR_TRAS(7)
-#define DDR_tRC         DDR_TRC(10)
-#define DDR_tRFC        DDR_TRFC(12)
-#define DDR_tREFI       DDR_TREFI(1288)
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define        DDR_CL          CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-
-#define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
-                        | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2     DDR_CL
-
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
index a2228428dc06..70b9c1194024 100644
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -108,4 +108,10 @@
 #define L1_SCRATCH_START        0xFFB00000
 #define L1_SCRATCH_LENGTH       0x1000
 
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+
 #endif/* _MEM_MAP_548_H_ */
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
index 3f4895450bea..638ec38ca470 100644
--- a/arch/blackfin/mach-bf561/Kconfig
+++ b/arch/blackfin/mach-bf561/Kconfig
@@ -4,9 +4,9 @@ source "arch/blackfin/mach-bf561/boards/Kconfig"
 
 menu "BF561 Specific Configuration"
 
-comment "Core B Support"
+if (!SMP)
 
-menu "Core B Support"
+comment "Core B Support"
 
 config BF561_COREB
         bool "Enable Core B support"
@@ -25,7 +25,7 @@ config BF561_COREB_RESET
           0 is set, and will reset PC to 0xff600000 when
           COREB_SRAM_INIT is cleared.
 
-endmenu
+endif
 
 comment "Interrupt Priority Assignment"
 
@@ -138,7 +138,7 @@ config IRQ_DMA2_11
         default 9
 config IRQ_TIMER0
         int "TIMER 0  Interrupt"
-        default 10
+        default 8
 config IRQ_TIMER1
         int "TIMER 1  Interrupt"
         default 10
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index f39235a55783..59e18afe28c6 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -2,8 +2,7 @@
 # arch/blackfin/mach-bf561/Makefile
 #
 
-extra-y := head.o
-
 obj-y := ints-priority.o dma.o
 
 obj-$(CONFIG_BF561_COREB) += coreb.o
+obj-$(CONFIG_SMP)  += smp.o secondary.o atomic.o
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
new file mode 100644
index 000000000000..9439bc6bd01f
--- /dev/null
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -0,0 +1,919 @@
+/*
+ * File:         arch/blackfin/mach-bf561/atomic.S
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/cache.h>
+#include <asm/asm-offsets.h>
+#include <asm/rwlock.h>
+#include <asm/cplb.h>
+
+.text
+
+.macro coreslot_loadaddr reg:req
+        \reg\().l = _corelock;
+        \reg\().h = _corelock;
+.endm
+
+/*
+ * r0 = address of atomic data to flush and invalidate (32bit).
+ *
+ * Clear interrupts and return the old mask.
+ * We assume that no atomic data can span cachelines.
+ *
+ * Clobbers: r2:0, p0
+ */
+ENTRY(_get_core_lock)
+        r1 = -L1_CACHE_BYTES;
+        r1 = r0 & r1;
+        cli r0;
+        coreslot_loadaddr p0;
+.Lretry_corelock:
+        testset (p0);
+        if cc jump .Ldone_corelock;
+        SSYNC(r2);
+        jump .Lretry_corelock
+.Ldone_corelock:
+        p0 = r1;
+        CSYNC(r2);
+        flushinv[p0];
+        SSYNC(r2);
+        rts;
+ENDPROC(_get_core_lock)
+
+/*
+ * r0 = address of atomic data in uncacheable memory region (32bit).
+ *
+ * Clear interrupts and return the old mask.
+ *
+ * Clobbers: r0, p0
+ */
+ENTRY(_get_core_lock_noflush)
+        cli r0;
+        coreslot_loadaddr p0;
+.Lretry_corelock_noflush:
+        testset (p0);
+        if cc jump .Ldone_corelock_noflush;
+        SSYNC(r2);
+        jump .Lretry_corelock_noflush
+.Ldone_corelock_noflush:
+        rts;
+ENDPROC(_get_core_lock_noflush)
+
+/*
+ * r0 = interrupt mask to restore.
+ * r1 = address of atomic data to flush and invalidate (32bit).
+ *
+ * Interrupts are masked on entry (see _get_core_lock).
+ * Clobbers: r2:0, p0
+ */
+ENTRY(_put_core_lock)
+        /* Write-through cache assumed, so no flush needed here. */
+        coreslot_loadaddr p0;
+        r1 = 0;
+        [p0] = r1;
+        SSYNC(r2);
+        sti r0;
+        rts;
+ENDPROC(_put_core_lock)
+
+#ifdef __ARCH_SYNC_CORE_DCACHE
+
+ENTRY(___raw_smp_mark_barrier_asm)
+        [--sp] = rets;
+        [--sp] = ( r7:5 );
+        [--sp] = r0;
+        [--sp] = p1;
+        [--sp] = p0;
+        call _get_core_lock_noflush;
+
+        /*
+         * Calculate current core mask
+         */
+        GET_CPUID(p1, r7);
+        r6 = 1;
+        r6 <<= r7;
+
+        /*
+         * Set bit of other cores in barrier mask. Don't change current core bit.
+         */
+        p1.l = _barrier_mask;
+        p1.h = _barrier_mask;
+        r7 = [p1];
+        r5 = r7 & r6;
+        r7 = ~r6;
+        cc = r5 == 0;
+        if cc jump 1f;
+        r7 = r7 | r6;
+1:
+        [p1] = r7;
+        SSYNC(r2);
+
+        call _put_core_lock;
+        p0 = [sp++];
+        p1 = [sp++];
+        r0 = [sp++];
+        ( r7:5 ) = [sp++];
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_smp_mark_barrier_asm)
+
+ENTRY(___raw_smp_check_barrier_asm)
+        [--sp] = rets;
+        [--sp] = ( r7:5 );
+        [--sp] = r0;
+        [--sp] = p1;
+        [--sp] = p0;
+        call _get_core_lock_noflush;
+
+        /*
+         * Calculate current core mask
+         */
+        GET_CPUID(p1, r7);
+        r6 = 1;
+        r6 <<= r7;
+
+        /*
+         * Clear current core bit in barrier mask if it is set.
+         */
+        p1.l = _barrier_mask;
+        p1.h = _barrier_mask;
+        r7 = [p1];
+        r5 = r7 & r6;
+        cc = r5 == 0;
+        if cc jump 1f;
+        r6 = ~r6;
+        r7 = r7 & r6;
+        [p1] = r7;
+        SSYNC(r2);
+
+        call _put_core_lock;
+
+        /*
+         * Invalidate the entire D-cache of current core.
+         */
+        sp += -12;
+        call _resync_core_dcache
+        sp += 12;
+        jump 2f;
+1:
+        call _put_core_lock;
+2:
+        p0 = [sp++];
+        p1 = [sp++];
+        r0 = [sp++];
+        ( r7:5 ) = [sp++];
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_smp_check_barrier_asm)
+
+/*
+ * r0 = irqflags
+ * r1 = address of atomic data
+ *
+ * Clobbers: r2:0, p1:0
+ */
+_start_lock_coherent:
+
+        [--sp] = rets;
+        [--sp] = ( r7:6 );
+        r7 = r0;
+        p1 = r1;
+
+        /*
+         * Determine whether the atomic data was previously
+         * owned by another CPU (=r6).
+         */
+        GET_CPUID(p0, r2);
+        r1 = 1;
+        r1 <<= r2;
+        r2 = ~r1;
+
+        r1 = [p1];
+        r1 >>= 28;   /* CPU fingerprints are stored in the high nibble. */
+        r6 = r1 & r2;
+        r1 = [p1];
+        r1 <<= 4;
+        r1 >>= 4;
+        [p1] = r1;
+
+        /*
+         * Release the core lock now, but keep IRQs disabled while we are
+         * performing the remaining housekeeping chores for the current CPU.
+         */
+        coreslot_loadaddr p0;
+        r1 = 0;
+        [p0] = r1;
+
+        /*
+         * If another CPU has owned the same atomic section before us,
+         * then our D-cached copy of the shared data protected by the
+         * current spin/write_lock may be obsolete.
+         */
+        cc = r6 == 0;
+        if cc jump .Lcache_synced
+
+        /*
+         * Invalidate the entire D-cache of the current core.
+         */
+        sp += -12;
+        call _resync_core_dcache
+        sp += 12;
+
+.Lcache_synced:
+        SSYNC(r2);
+        sti r7;
+        ( r7:6 ) = [sp++];
+        rets = [sp++];
+        rts
+
+/*
+ * r0 = irqflags
+ * r1 = address of atomic data
+ *
+ * Clobbers: r2:0, p1:0
+ */
+_end_lock_coherent:
+
+        p1 = r1;
+        GET_CPUID(p0, r2);
+        r2 += 28;
+        r1 = 1;
+        r1 <<= r2;
+        r2 = [p1];
+        r2 = r1 | r2;
+        [p1] = r2;
+        r1 = p1;
+        jump _put_core_lock;
+
+#endif /* __ARCH_SYNC_CORE_DCACHE */
+
+/*
+ * r0 = &spinlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_spin_is_locked_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r3 = [p1];
+        cc = bittst( r3, 0 );
+        r3 = cc;
+        r1 = p1;
+        call _put_core_lock;
+        rets = [sp++];
+        r0 = r3;
+        rts;
+ENDPROC(___raw_spin_is_locked_asm)
+
+/*
+ * r0 = &spinlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_spin_lock_asm)
+        p1 = r0;
+        [--sp] = rets;
+.Lretry_spinlock:
+        call _get_core_lock;
+        r1 = p1;
+        r2 = [p1];
+        cc = bittst( r2, 0 );
+        if cc jump .Lbusy_spinlock
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        r3 = p1;
+        bitset ( r2, 0 ); /* Raise the lock bit. */
+        [p1] = r2;
+        call _start_lock_coherent
+#else
+        r2 = 1;
+        [p1] = r2;
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        rts;
+
+.Lbusy_spinlock:
+        /* We don't touch the atomic area if busy, so that flush
+           will behave like nop in _put_core_lock. */
+        call _put_core_lock;
+        SSYNC(r2);
+        r0 = p1;
+        jump .Lretry_spinlock
+ENDPROC(___raw_spin_lock_asm)
+
+/*
+ * r0 = &spinlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_spin_trylock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r1 = p1;
+        r3 = [p1];
+        cc = bittst( r3, 0 );
+        if cc jump .Lfailed_trylock
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        bitset ( r3, 0 ); /* Raise the lock bit. */
+        [p1] = r3;
+        call _start_lock_coherent
+#else
+        r2 = 1;
+        [p1] = r2;
+        call _put_core_lock;
+#endif
+        r0 = 1;
+        rets = [sp++];
+        rts;
+.Lfailed_trylock:
+        call _put_core_lock;
+        r0 = 0;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_spin_trylock_asm)
+
+/*
+ * r0 = &spinlock->lock
+ *
+ * Clobbers: r2:0, p1:0
+ */
+ENTRY(___raw_spin_unlock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r2 = [p1];
+        bitclr ( r2, 0 );
+        [p1] = r2;
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _end_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_spin_unlock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Clobbers: r2:0, p1:0
+ */
+ENTRY(___raw_read_lock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+.Lrdlock_try:
+        r1 = [p1];
+        r1 += -1;
+        [p1] = r1;
+        cc = r1 < 0;
+        if cc jump .Lrdlock_failed
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _start_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        rts;
+
+.Lrdlock_failed:
+        r1 += 1;
+        [p1] = r1;
+.Lrdlock_wait:
+        r1 = p1;
+        call _put_core_lock;
+        SSYNC(r2);
+        r0 = p1;
+        call _get_core_lock;
+        r1 = [p1];
+        cc = r1 < 2;
+        if cc jump .Lrdlock_wait;
+        jump .Lrdlock_try
+ENDPROC(___raw_read_lock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_read_trylock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r1 = [p1];
+        cc = r1 <= 0;
+        if cc jump .Lfailed_tryrdlock;
+        r1 += -1;
+        [p1] = r1;
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _start_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        r0 = 1;
+        rts;
+.Lfailed_tryrdlock:
+        r1 = p1;
+        call _put_core_lock;
+        rets = [sp++];
+        r0 = 0;
+        rts;
+ENDPROC(___raw_read_trylock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Note: Processing controlled by a reader lock should not have
+ * any side-effect on cache issues with the other core, so we
+ * just release the core lock and exit (no _end_lock_coherent).
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_read_unlock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r1 = [p1];
+        r1 += 1;
+        [p1] = r1;
+        r1 = p1;
+        call _put_core_lock;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_read_unlock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_write_lock_asm)
+        p1 = r0;
+        r3.l = lo(RW_LOCK_BIAS);
+        r3.h = hi(RW_LOCK_BIAS);
+        [--sp] = rets;
+        call _get_core_lock;
+.Lwrlock_try:
+        r1 = [p1];
+        r1 = r1 - r3;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        r2 = r1;
+        r2 <<= 4;
+        r2 >>= 4;
+        cc = r2 == 0;
+#else
+        cc = r1 == 0;
+#endif
+        if !cc jump .Lwrlock_wait
+        [p1] = r1;
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _start_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        rts;
+
+.Lwrlock_wait:
+        r1 = p1;
+        call _put_core_lock;
+        SSYNC(r2);
+        r0 = p1;
+        call _get_core_lock;
+        r1 = [p1];
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        r1 <<= 4;
+        r1 >>= 4;
+#endif
+        cc = r1 == r3;
+        if !cc jump .Lwrlock_wait;
+        jump .Lwrlock_try
+ENDPROC(___raw_write_lock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_write_trylock_asm)
+        p1 = r0;
+        [--sp] = rets;
+        call _get_core_lock;
+        r1 = [p1];
+        r2.l = lo(RW_LOCK_BIAS);
+        r2.h = hi(RW_LOCK_BIAS);
+        cc = r1 == r2;
+        if !cc jump .Lfailed_trywrlock;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        r1 >>= 28;
+        r1 <<= 28;
+#else
+        r1 = 0;
+#endif
+        [p1] = r1;
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _start_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        r0 = 1;
+        rts;
+
+.Lfailed_trywrlock:
+        r1 = p1;
+        call _put_core_lock;
+        rets = [sp++];
+        r0 = 0;
+        rts;
+ENDPROC(___raw_write_trylock_asm)
+
+/*
+ * r0 = &rwlock->lock
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_write_unlock_asm)
+        p1 = r0;
+        r3.l = lo(RW_LOCK_BIAS);
+        r3.h = hi(RW_LOCK_BIAS);
+        [--sp] = rets;
+        call _get_core_lock;
+        r1 = [p1];
+        r1 = r1 + r3;
+        [p1] = r1;
+        r1 = p1;
+#ifdef __ARCH_SYNC_CORE_DCACHE
+        call _end_lock_coherent
+#else
+        call _put_core_lock;
+#endif
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_write_unlock_asm)
+
+/*
+ * r0 = ptr
+ * r1 = value
+ *
+ * Add a signed value to a 32bit word and return the new value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_atomic_update_asm)
+        p1 = r0;
+        r3 = r1;
+        [--sp] = rets;
+        call _get_core_lock;
+        r2 = [p1];
+        r3 = r3 + r2;
+        [p1] = r3;
+        r1 = p1;
+        call _put_core_lock;
+        r0 = r3;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_atomic_update_asm)
+
+/*
+ * r0 = ptr
+ * r1 = mask
+ *
+ * Clear the mask bits from a 32bit word and return the old 32bit value
+ * atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_atomic_clear_asm)
+        p1 = r0;
+        r3 = ~r1;
+        [--sp] = rets;
+        call _get_core_lock;
+        r2 = [p1];
+        r3 = r2 & r3;
+        [p1] = r3;
+        r3 = r2;
+        r1 = p1;
+        call _put_core_lock;
+        r0 = r3;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_atomic_clear_asm)
+
+/*
+ * r0 = ptr
+ * r1 = mask
+ *
+ * Set the mask bits into a 32bit word and return the old 32bit value
+ * atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_atomic_set_asm)
+        p1 = r0;
+        r3 = r1;
+        [--sp] = rets;
+        call _get_core_lock;
+        r2 = [p1];
+        r3 = r2 | r3;
+        [p1] = r3;
+        r3 = r2;
+        r1 = p1;
+        call _put_core_lock;
+        r0 = r3;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_atomic_set_asm)
+
+/*
+ * r0 = ptr
+ * r1 = mask
+ *
+ * XOR the mask bits with a 32bit word and return the old 32bit value
+ * atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_atomic_xor_asm)
+        p1 = r0;
+        r3 = r1;
+        [--sp] = rets;
+        call _get_core_lock;
+        r2 = [p1];
+        r3 = r2 ^ r3;
+        [p1] = r3;
+        r3 = r2;
+        r1 = p1;
+        call _put_core_lock;
+        r0 = r3;
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_atomic_xor_asm)
+
+/*
+ * r0 = ptr
+ * r1 = mask
+ *
+ * Perform a logical AND between the mask bits and a 32bit word, and
+ * return the masked value. We need this on this architecture in
+ * order to invalidate the local cache before testing.
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_atomic_test_asm)
+        p1 = r0;
+        r3 = r1;
+        r1 = -L1_CACHE_BYTES;
+        r1 = r0 & r1;
+        p0 = r1;
+        flushinv[p0];
+        SSYNC(r2);
+        r0 = [p1];
+        r0 = r0 & r3;
+        rts;
+ENDPROC(___raw_atomic_test_asm)
+
+/*
+ * r0 = ptr
+ * r1 = value
+ *
+ * Swap *ptr with value and return the old 32bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+#define __do_xchg(src, dst)             \
+        p1 = r0;                        \
+        r3 = r1;                        \
+        [--sp] = rets;                  \
+        call _get_core_lock;            \
+        r2 = src;                       \
+        dst = r3;                       \
+        r3 = r2;                        \
+        r1 = p1;                        \
+        call _put_core_lock;            \
+        r0 = r3;                        \
+        rets = [sp++];                  \
+        rts;
+
+ENTRY(___raw_xchg_1_asm)
+        __do_xchg(b[p1] (z), b[p1])
+ENDPROC(___raw_xchg_1_asm)
+
+ENTRY(___raw_xchg_2_asm)
+        __do_xchg(w[p1] (z), w[p1])
+ENDPROC(___raw_xchg_2_asm)
+
+ENTRY(___raw_xchg_4_asm)
+        __do_xchg([p1], [p1])
+ENDPROC(___raw_xchg_4_asm)
+
+/*
+ * r0 = ptr
+ * r1 = new
+ * r2 = old
+ *
+ * Swap *ptr with new if *ptr == old and return the previous *ptr
+ * value atomically.
+ *
+ * Clobbers: r3:0, p1:0
+ */
+#define __do_cmpxchg(src, dst)          \
+        [--sp] = rets;                  \
+        [--sp] = r4;                    \
+        p1 = r0;                        \
+        r3 = r1;                        \
+        r4 = r2;                        \
+        call _get_core_lock;            \
+        r2 = src;                       \
+        cc = r2 == r4;                  \
+        if !cc jump 1f;                 \
+        dst = r3;                       \
+     1: r3 = r2;                        \
+        r1 = p1;                        \
+        call _put_core_lock;            \
+        r0 = r3;                        \
+        r4 = [sp++];                    \
+        rets = [sp++];                  \
+        rts;
+
+ENTRY(___raw_cmpxchg_1_asm)
+        __do_cmpxchg(b[p1] (z), b[p1])
+ENDPROC(___raw_cmpxchg_1_asm)
+
+ENTRY(___raw_cmpxchg_2_asm)
+        __do_cmpxchg(w[p1] (z), w[p1])
+ENDPROC(___raw_cmpxchg_2_asm)
+
+ENTRY(___raw_cmpxchg_4_asm)
+        __do_cmpxchg([p1], [p1])
+ENDPROC(___raw_cmpxchg_4_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Set a bit in a 32bit word and return the old 32bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_set_asm)
+        r2 = r1;
+        r1 = 1;
+        r1 <<= r2;
+        jump ___raw_atomic_set_asm
+ENDPROC(___raw_bit_set_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Clear a bit in a 32bit word and return the old 32bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_clear_asm)
+        r2 = r1;
+        r1 = 1;
+        r1 <<= r2;
+        jump ___raw_atomic_clear_asm
+ENDPROC(___raw_bit_clear_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Toggle a bit in a 32bit word and return the old 32bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_toggle_asm)
+        r2 = r1;
+        r1 = 1;
+        r1 <<= r2;
+        jump ___raw_atomic_xor_asm
+ENDPROC(___raw_bit_toggle_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Test-and-set a bit in a 32bit word and return the old bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_test_set_asm)
+        [--sp] = rets;
+        [--sp] = r1;
+        call ___raw_bit_set_asm
+        r1 = [sp++];
+        r2 = 1;
+        r2 <<= r1;
+        r0 = r0 & r2;
+        cc = r0 == 0;
+        if cc jump 1f
+        r0 = 1;
+1:
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_bit_test_set_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_test_clear_asm)
+        [--sp] = rets;
+        [--sp] = r1;
+        call ___raw_bit_clear_asm
+        r1 = [sp++];
+        r2 = 1;
+        r2 <<= r1;
+        r0 = r0 & r2;
+        cc = r0 == 0;
+        if cc jump 1f
+        r0 = 1;
+1:
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_bit_test_clear_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Test-and-toggle a bit in a 32bit word,
+ * and return the old bit value atomically.
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_test_toggle_asm)
+        [--sp] = rets;
+        [--sp] = r1;
+        call ___raw_bit_toggle_asm
+        r1 = [sp++];
+        r2 = 1;
+        r2 <<= r1;
+        r0 = r0 & r2;
+        cc = r0 == 0;
+        if cc jump 1f
+        r0 = 1;
+1:
+        rets = [sp++];
+        rts;
+ENDPROC(___raw_bit_test_toggle_asm)
+
+/*
+ * r0 = ptr
+ * r1 = bitnr
+ *
+ * Test a bit in a 32bit word and return its value.
+ * We need this on this architecture in order to invalidate
+ * the local cache before testing.
+ *
+ * Clobbers: r3:0, p1:0
+ */
+ENTRY(___raw_bit_test_asm)
+        r2 = r1;
+        r1 = 1;
+        r1 <<= r2;
+        jump ___raw_atomic_test_asm
+ENDPROC(___raw_bit_test_asm)
+
+/*
+ * r0 = ptr
+ *
+ * Fetch and return an uncached 32bit value.
+ *
+ * Clobbers: r2:0, p1:0
+ */
+ENTRY(___raw_uncached_fetch_asm)
+        p1 = r0;
+        r1 = -L1_CACHE_BYTES;
+        r1 = r0 & r1;
+        p0 = r1;
+        flushinv[p0];
+        SSYNC(r2);
+        r0 = [p1];
+        rts;
+ENDPROC(___raw_uncached_fetch_asm)
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 8f40990eea2f..6880d1ebfe60 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -230,6 +230,19 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
+static struct resource bfin_gpios_resources = {
+        .start = 0,
+        .end   = MAX_BLACKFIN_GPIOS - 1,
+        .flags = IORESOURCE_IRQ,
+};
+
+static struct platform_device bfin_gpios_device = {
+        .name = "simple-gpio",
+        .id = -1,
+        .num_resources = 1,
+        .resource = &bfin_gpios_resources,
+};
+
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 static struct resource isp1362_hcd_resources[] = {
         {
@@ -287,23 +300,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
 #define PATA_INT        IRQ_PF46
@@ -382,7 +405,9 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -400,6 +425,8 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
         &bfin_pata_device,
 #endif
+
+        &bfin_gpios_device,
 };
 
 static int __init cm_bf561_init(void)
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 50b4cdceccfe..0e2178a1aec5 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -43,53 +43,42 @@
 /*
  * Name the Board for the /proc/cpuinfo
  */
-const char bfin_board_name[] = "ADDS-BF561-EZKIT";
-
-#define ISP1761_BASE       0x2C0F0000
-#define ISP1761_IRQ        IRQ_PF10
+const char bfin_board_name[] = "ADI BF561-EZKIT";
 
 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
-static struct resource bfin_isp1761_resources[] = {
-        {
-                .name   = "isp1761-regs",
-                .start  = ISP1761_BASE + 0x00000000,
-                .end    = ISP1761_BASE + 0x000fffff,
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
+        [0] = {
+                .start  = 0x2C0F0000,
+                .end    = 0x203C0000 + 0xfffff,
                 .flags  = IORESOURCE_MEM,
         },
-        {
-                .start  = ISP1761_IRQ,
-                .end    = ISP1761_IRQ,
+        [1] = {
+                .start  = IRQ_PF10,
+                .end    = IRQ_PF10,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device bfin_isp1761_device = {
-        .name           = "isp1761",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
-        .resource       = bfin_isp1761_resources,
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .port1_disable = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
 };
 
-static struct platform_device *bfin_isp1761_devices[] = {
-        &bfin_isp1761_device,
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760-hcd",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
 };
-
-int __init bfin_isp1761_init(void)
-{
-        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
-
-        printk(KERN_INFO "%s(): registering device resources\n", __func__);
-        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
-
-        return platform_add_devices(bfin_isp1761_devices, num_devices);
-}
-
-void __exit bfin_isp1761_exit(void)
-{
-        platform_device_unregister(&bfin_isp1761_device);
-}
-
-arch_initcall(bfin_isp1761_init);
 #endif
 
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -221,23 +210,33 @@ static struct platform_device bfin_uart_device = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-static struct resource bfin_sir_resources[] = {
 #ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
         {
                 .start = 0xFFC00400,
                 .end = 0xFFC004FF,
                 .flags = IORESOURCE_MEM,
         },
-#endif
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
-static struct platform_device bfin_sir_device = {
+static struct platform_device bfin_sir0_device = {
         .name = "bfin_sir",
         .id = 0,
-        .num_resources = ARRAY_SIZE(bfin_sir_resources),
-        .resource = bfin_sir_resources,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
 };
 #endif
+#endif
 
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 static struct mtd_partition ezkit_partitions[] = {
@@ -449,6 +448,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &net2272_bfin_device,
 #endif
 
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
         &bfin_spi0_device,
 #endif
@@ -458,7 +461,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
-        &bfin_sir_device,
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
 #endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
index 2faa0072d614..0ba366a0e696 100644
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -62,10 +62,45 @@ static struct platform_device smc91x_device = {
 };
 #endif
 
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#endif
+
 static struct platform_device *generic_board_devices[] __initdata = {
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
         &smc91x_device,
 #endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#endif
 };
 
 static int __init generic_board_init(void)
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index c9174b39f98d..6f77dbe952f5 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -44,8 +44,42 @@ static struct platform_device smc91x_device = {
         .resource      = smc91x_resources,
 };
 
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#endif
+
 static struct platform_device *tepla_devices[] __initdata = {
         &smc91x_device,
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#endif
 };
 
 static int __init tepla_init(void)
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index 24415eb82698..42b0037afe61 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -31,7 +31,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
+struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
deleted file mode 100644
index 31a777a9e699..000000000000
--- a/arch/blackfin/mach-bf561/head.S
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf561/head.S
- * Based on:     arch/blackfin/mach-bf533/head.S
- * Author:
- *
- * Created:
- * Description:  BF561 startup file
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#include <asm/clocks.h>
-#include <mach/mem_init.h>
-#endif
-
-.section .l1.text
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-ENTRY(_start_dma_code)
-        p0.h = hi(SICA_IWR0);
-        p0.l = lo(SICA_IWR0);
-        r0.l = 0x1;
-        [p0] = r0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        p0.h = hi(PLL_LOCKCNT);
-        p0.l = lo(PLL_LOCKCNT);
-        r0 = 0x300(Z);
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-#ifdef ANOMALY_05000265
-        BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
-#endif
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-
-.Lcheck_again:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again;
-
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-
-        p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
-
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
-        p0.h = hi(EBIU_SDSTAT);
-        p0.l = lo(EBIU_SDSTAT);
-        r2.l = w[p0];
-        cc = bittst(r2,3);
-        if !cc jump .Lskip;
-        NOP;
-        BITSET (R0, 23);
-.Lskip:
-        [P2] = R0;
-        SSYNC;
-
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
-        R1 = [p2];
-        R1 = R1 | R0;
-        [P2] = R1;
-        SSYNC;
-
-        RTS;
-ENDPROC(_start_dma_code)
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22990df04ae1..1a9e17562821 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -7,7 +7,7 @@
  */
 
 /* This file shoule be up to date with:
- *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -264,6 +264,18 @@
 #define ANOMALY_05000371 (1)
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 #define ANOMALY_05000403 (1)
+/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
+#define ANOMALY_05000412 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
+#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
@@ -272,5 +284,7 @@
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000386 (1)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
index 18b1b3a223ab..9968362a2ee4 100644
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ b/arch/blackfin/mach-bf561/include/mach/bf561.h
@@ -215,7 +215,7 @@
 #endif
 
 #ifndef CPU
-#error Unknown CPU type - This kernel doesn't seem to be configured properly
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
 #endif
 
 #endif                          /* __MACH_BF561_H__  */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 0ea8666e6764..f79f6626b7ec 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -66,8 +66,12 @@
 
 #define bfin_read_SIC_IMASK(x)          bfin_read32(SICA_IMASK0 + (x << 2))
 #define bfin_write_SIC_IMASK(x, val)    bfin_write32((SICA_IMASK0 + (x << 2)), val)
+#define bfin_read_SICB_IMASK(x)         bfin_read32(SICB_IMASK0 + (x << 2))
+#define bfin_write_SICB_IMASK(x, val)   bfin_write32((SICB_IMASK0 + (x << 2)), val)
 #define bfin_read_SIC_ISR(x)            bfin_read32(SICA_ISR0 + (x << 2))
 #define bfin_write_SIC_ISR(x, val)      bfin_write32((SICA_ISR0 + (x << 2)), val)
+#define bfin_read_SICB_ISR(x)           bfin_read32(SICB_ISR0 + (x << 2))
+#define bfin_write_SICB_ISR(x, val)     bfin_write32((SICB_ISR0 + (x << 2)), val)
 
 #define BFIN_UART_NR_PORTS      1
 
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index c14d63402e70..95d609f11c97 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -39,65 +39,15 @@
 /*include core specific register pointer definitions*/
 #include <asm/cdef_LPBlackfin.h>
 
-#include <asm/system.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
 
 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SICA_IWR0);
+        iwr1 = bfin_read32(SICA_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+        bfin_write32(SICA_IWR1, 0);
+
+        bfin_write16(PLL_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SICA_IWR0, iwr0);
+        bfin_write32(SICA_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1;
+
+        if (val == bfin_read_VR_CTL())
+                return;
+
+        local_irq_save_hw(flags);
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr0 = bfin_read32(SICA_IWR0);
+        iwr1 = bfin_read32(SICA_IWR1);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+        bfin_write32(SICA_IWR1, 0);
+
+        bfin_write16(VR_CTL, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_write32(SICA_IWR0, iwr0);
+        bfin_write32(SICA_IWR1, iwr1);
+        local_irq_restore_hw(flags);
+}
+
 #endif                          /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 4eca2026bb92..d7c509759659 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -912,6 +912,9 @@
 #define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
 #define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
+/* SICA_SYSCR Masks */
+#define COREB_SRAM_INIT         0x0020
+
 /* SWRST Mask */
 #define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
 #define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
index 8bc46cd89a02..13647c71f1c7 100644
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ b/arch/blackfin/mach-bf561/include/mach/dma.h
@@ -1,13 +1,17 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
+/* mach/dma.h - arch-specific DMA defines
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
 
 #ifndef _MACH_DMA_H_
 #define _MACH_DMA_H_
 
-#define MAX_BLACKFIN_DMA_CHANNEL 36
+#define MAX_DMA_CHANNELS 36
+
+/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
+#define MAX_DMA_SUSPEND_CHANNELS 32
 
 #define CH_PPI0                 0
 #define CH_PPI                  (CH_PPI0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
new file mode 100644
index 000000000000..7882f79e1ade
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -0,0 +1,68 @@
+/*
+ * File: arch/blackfin/mach-bf561/include/mach/gpio.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 48
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PF16       16
+#define GPIO_PF17       17
+#define GPIO_PF18       18
+#define GPIO_PF19       19
+#define GPIO_PF20       20
+#define GPIO_PF21       21
+#define GPIO_PF22       22
+#define GPIO_PF23       23
+#define GPIO_PF24       24
+#define GPIO_PF25       25
+#define GPIO_PF26       26
+#define GPIO_PF27       27
+#define GPIO_PF28       28
+#define GPIO_PF29       29
+#define GPIO_PF30       30
+#define GPIO_PF31       31
+#define GPIO_PF32       32
+#define GPIO_PF33       33
+#define GPIO_PF34       34
+#define GPIO_PF35       35
+#define GPIO_PF36       36
+#define GPIO_PF37       37
+#define GPIO_PF38       38
+#define GPIO_PF39       39
+#define GPIO_PF40       40
+#define GPIO_PF41       41
+#define GPIO_PF42       42
+#define GPIO_PF43       43
+#define GPIO_PF44       44
+#define GPIO_PF45       45
+#define GPIO_PF46       46
+#define GPIO_PF47       47
+
+#define PORT_FIO0 GPIO_0
+#define PORT_FIO1 GPIO_16
+#define PORT_FIO2 GPIO_32
+
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC8M32B2B5_7)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index f1d4c0637bd2..419dffdc96eb 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -85,4 +85,84 @@
 #define L1_SCRATCH_START        COREA_L1_SCRATCH_START
 #define L1_SCRATCH_LENGTH       0x1000
 
+#ifdef __ASSEMBLY__
+
+/*
+ * The following macros both return the address of the PDA for the
+ * current core.
+ *
+ * In its first safe (and hairy) form, the macro neither clobbers any
+ * register aside of the output Preg, nor uses the stack, since it
+ * could be called with an invalid stack pointer, or the current stack
+ * space being uncovered by any CPLB (e.g. early exception handling).
+ *
+ * The constraints on the second form are a bit relaxed, and the code
+ * is allowed to use the specified Dreg for determining the PDA
+ * address to be returned into Preg.
+ */
+#ifdef CONFIG_SMP
+#define GET_PDA_SAFE(preg)              \
+        preg.l = lo(DSPID);             \
+        preg.h = hi(DSPID);             \
+        preg = [preg];                  \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        preg = preg << 2;               \
+        if cc jump 2f;                  \
+        cc = preg == 0x0;               \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;              \
+        if !cc jump 3f;                 \
+1:                                      \
+        /* preg = 0x0; */               \
+        cc = !cc; /* restore cc to 0 */ \
+        jump 4f;                        \
+2:                                      \
+        cc = preg == 0x0;               \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;              \
+        if cc jump 4f;                  \
+        /* preg = 0x1000000; */         \
+        cc = !cc; /* restore cc to 1 */ \
+3:                                      \
+        preg = [preg];                  \
+4:
+
+#define GET_PDA(preg, dreg)             \
+        preg.l = lo(DSPID);             \
+        preg.h = hi(DSPID);             \
+        dreg = [preg];                  \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;              \
+        cc = bittst(dreg, 0);           \
+        if !cc jump 1f;                 \
+        preg = [preg];                  \
+1:                                      \
+
+#define GET_CPUID(preg, dreg)           \
+        preg.l = lo(DSPID);             \
+        preg.h = hi(DSPID);             \
+        dreg = [preg];                  \
+        dreg = ROT dreg BY -1;          \
+        dreg = CC;
+
+#else
+#define GET_PDA_SAFE(preg)              \
+        preg.l = _cpu_pda;              \
+        preg.h = _cpu_pda;
+
+#define GET_PDA(preg, dreg)     GET_PDA_SAFE(preg)
+#endif /* CONFIG_SMP */
+
+#endif /* __ASSEMBLY__ */
+
 #endif                          /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
new file mode 100644
index 000000000000..f9e65ebe81b2
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -0,0 +1,22 @@
+#ifndef _MACH_BF561_SMP
+#define _MACH_BF561_SMP
+
+struct task_struct;
+
+void platform_init_cpus(void);
+
+void platform_prepare_cpus(unsigned int max_cpus);
+
+int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
+
+void platform_secondary_init(unsigned int cpu);
+
+void platform_request_ipi(int (*handler)(int, void *));
+
+void platform_send_ipi(cpumask_t callmap);
+
+void platform_send_ipi_cpu(unsigned int cpu);
+
+void platform_clear_ipi(unsigned int cpu);
+
+#endif /* !_MACH_BF561_SMP */
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
new file mode 100644
index 000000000000..35280f06b7b6
--- /dev/null
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -0,0 +1,215 @@
+/*
+ * File:         arch/blackfin/mach-bf561/secondary.S
+ * Based on:     arch/blackfin/mach-bf561/head.S
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * Description:  BF561 coreB bootstrap file
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/blackfin.h>
+#include <asm/asm-offsets.h>
+
+__INIT
+
+/* Lay the initial stack into the L1 scratch area of Core B */
+#define INITIAL_STACK   (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+
+ENTRY(_coreb_trampoline_start)
+        /* Set the SYSCFG register */
+        R0 = 0x36;
+        SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+        R0 = 0;
+
+        /*Clear Out All the data and pointer  Registers*/
+        R1 = R0;
+        R2 = R0;
+        R3 = R0;
+        R4 = R0;
+        R5 = R0;
+        R6 = R0;
+        R7 = R0;
+
+        P0 = R0;
+        P1 = R0;
+        P2 = R0;
+        P3 = R0;
+        P4 = R0;
+        P5 = R0;
+
+        LC0 = r0;
+        LC1 = r0;
+        L0 = r0;
+        L1 = r0;
+        L2 = r0;
+        L3 = r0;
+
+        /* Clear Out All the DAG Registers*/
+        B0 = r0;
+        B1 = r0;
+        B2 = r0;
+        B3 = r0;
+
+        I0 = r0;
+        I1 = r0;
+        I2 = r0;
+        I3 = r0;
+
+        M0 = r0;
+        M1 = r0;
+        M2 = r0;
+        M3 = r0;
+
+        /* Turn off the icache */
+        p0.l = LO(IMEM_CONTROL);
+        p0.h = HI(IMEM_CONTROL);
+        R1 = [p0];
+        R0 = ~ENICPLB;
+        R0 = R0 & R1;
+
+        /* Anomaly 05000125 */
+#ifdef ANOMALY_05000125
+        CLI R2;
+        SSYNC;
+#endif
+        [p0] = R0;
+        SSYNC;
+#ifdef ANOMALY_05000125
+        STI R2;
+#endif
+
+        /* Turn off the dcache */
+        p0.l = LO(DMEM_CONTROL);
+        p0.h = HI(DMEM_CONTROL);
+        R1 = [p0];
+        R0 = ~ENDCPLB;
+        R0 = R0 & R1;
+
+        /* Anomaly 05000125 */
+#ifdef ANOMALY_05000125
+        CLI R2;
+        SSYNC;
+#endif
+        [p0] = R0;
+        SSYNC;
+#ifdef ANOMALY_05000125
+        STI R2;
+#endif
+
+        /* in case of double faults, save a few things */
+        p0.l = _init_retx_coreb;
+        p0.h = _init_retx_coreb;
+        R0 = RETX;
+        [P0] = R0;
+
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+        /* Only save these if we are storing them,
+         * This happens here, since L1 gets clobbered
+         * below
+         */
+        GET_PDA(p0, r0);
+        r7 = [p0 + PDA_RETX];
+        p1.l = _init_saved_retx_coreb;
+        p1.h = _init_saved_retx_coreb;
+        [p1] = r7;
+
+        r7 = [p0 + PDA_DCPLB];
+        p1.l = _init_saved_dcplb_fault_addr_coreb;
+        p1.h = _init_saved_dcplb_fault_addr_coreb;
+        [p1] = r7;
+
+        r7 = [p0 + PDA_ICPLB];
+        p1.l = _init_saved_icplb_fault_addr_coreb;
+        p1.h = _init_saved_icplb_fault_addr_coreb;
+        [p1] = r7;
+
+        r7 = [p0 + PDA_SEQSTAT];
+        p1.l = _init_saved_seqstat_coreb;
+        p1.h = _init_saved_seqstat_coreb;
+        [p1] = r7;
+#endif
+
+        /* Initialize stack pointer */
+        sp.l = lo(INITIAL_STACK);
+        sp.h = hi(INITIAL_STACK);
+        fp = sp;
+        usp = sp;
+
+        /* This section keeps the processor in supervisor mode
+         * during core B startup.  Branches to the idle task.
+         */
+
+        /* EVT15 = _real_start */
+
+        p0.l = lo(EVT15);
+        p0.h = hi(EVT15);
+        p1.l = _coreb_start;
+        p1.h = _coreb_start;
+        [p0] = p1;
+        csync;
+
+        p0.l = lo(IMASK);
+        p0.h = hi(IMASK);
+        p1.l = IMASK_IVG15;
+        p1.h = 0x0;
+        [p0] = p1;
+        csync;
+
+        raise 15;
+        p0.l = .LWAIT_HERE;
+        p0.h = .LWAIT_HERE;
+        reti = p0;
+#if defined(ANOMALY_05000281)
+        nop; nop; nop;
+#endif
+        rti;
+
+.LWAIT_HERE:
+        jump .LWAIT_HERE;
+ENDPROC(_coreb_trampoline_start)
+ENTRY(_coreb_trampoline_end)
+
+ENTRY(_coreb_start)
+        [--sp] = reti;
+
+        p0.l = lo(WDOGB_CTL);
+        p0.h = hi(WDOGB_CTL);
+        r0 = 0xAD6(z);
+        w[p0] = r0;     /* Clear the watchdog. */
+        ssync;
+
+        /*
+         * switch to IDLE stack.
+         */
+        p0.l = _secondary_stack;
+        p0.h = _secondary_stack;
+        sp = [p0];
+        usp = sp;
+        fp = sp;
+        sp += -12;
+        call _init_pda
+        sp += 12;
+        call _secondary_start_kernel;
+.L_exit:
+        jump.s  .L_exit;
+ENDPROC(_coreb_start)
+
+__FINIT
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
new file mode 100644
index 000000000000..9b27e698c0b2
--- /dev/null
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -0,0 +1,167 @@
+/*
+ * File:         arch/blackfin/mach-bf561/smp.c
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <asm/smp.h>
+#include <asm/dma.h>
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static cpumask_t cpu_callin_map;
+
+/*
+ * platform_init_cpus() - Tell the world about how many cores we
+ * have. This is called while setting up the architecture support
+ * (setup_arch()), so don't be too demanding here with respect to
+ * available kernel services.
+ */
+
+void __init platform_init_cpus(void)
+{
+        cpu_set(0, cpu_possible_map); /* CoreA */
+        cpu_set(1, cpu_possible_map); /* CoreB */
+}
+
+void __init platform_prepare_cpus(unsigned int max_cpus)
+{
+        int len;
+
+        len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
+        BUG_ON(len > L1_CODE_LENGTH);
+
+        dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
+
+        /* Both cores ought to be present on a bf561! */
+        cpu_set(0, cpu_present_map); /* CoreA */
+        cpu_set(1, cpu_present_map); /* CoreB */
+
+        printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
+}
+
+int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
+{
+        return -EINVAL;
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        local_irq_disable();
+
+        /* Clone setup for peripheral interrupt sources from CoreA. */
+        bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
+        bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
+        SSYNC();
+
+        /* Clone setup for IARs from CoreA. */
+        bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
+        bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
+        bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
+        bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
+        bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
+        bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
+        bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
+        bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
+        SSYNC();
+
+        local_irq_enable();
+
+        /* Calibrate loops per jiffy value. */
+        calibrate_delay();
+
+        /* Store CPU-private information to the cpu_data array. */
+        bfin_setup_cpudata(cpu);
+
+        /* We are done with local CPU inits, unblock the boot CPU. */
+        cpu_set(cpu, cpu_callin_map);
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /* CoreB already running?! */
+        BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
+
+        printk(KERN_INFO "Booting Core B.\n");
+
+        spin_lock(&boot_lock);
+
+        /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
+        SSYNC();
+        bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
+        SSYNC();
+
+        timeout = jiffies + 1 * HZ;
+        while (time_before(jiffies, timeout)) {
+                if (cpu_isset(cpu, cpu_callin_map))
+                        break;
+                udelay(100);
+                barrier();
+        }
+
+        spin_unlock(&boot_lock);
+
+        return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS;
+}
+
+void __init platform_request_ipi(irq_handler_t handler)
+{
+        int ret;
+
+        ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
+                          "SMP interrupt", handler);
+        if (ret)
+                panic("Cannot request supplemental interrupt 0 for IPI service\n");
+}
+
+void platform_send_ipi(cpumask_t callmap)
+{
+        unsigned int cpu;
+
+        for_each_cpu_mask(cpu, callmap) {
+                BUG_ON(cpu >= 2);
+                SSYNC();
+                bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+                SSYNC();
+        }
+}
+
+void platform_send_ipi_cpu(unsigned int cpu)
+{
+        BUG_ON(cpu >= 2);
+        SSYNC();
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+        SSYNC();
+}
+
+void platform_clear_ipi(unsigned int cpu)
+{
+        BUG_ON(cpu >= 2);
+        SSYNC();
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index e6ed57c56d4b..1f3228ed713f 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -3,10 +3,12 @@
 #
 
 obj-y := \
-        cache.o entry.o head.o \
+        cache.o cache-c.o entry.o head.o \
         interrupt.o irqpanic.o arch_checks.o ints-priority.o
 
 obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
 obj-$(CONFIG_PM)          += pm.o dpmc_modes.o
 obj-$(CONFIG_CPU_FREQ)    += cpufreq.o
 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
+obj-$(CONFIG_SMP)         += smp.o
+obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
new file mode 100644
index 000000000000..e6ab1f815123
--- /dev/null
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -0,0 +1,24 @@
+/*
+ * Blackfin cache control code (simpler control-style functions)
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/blackfin.h>
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+void blackfin_invalidate_entire_dcache(void)
+{
+        u32 dmem = bfin_read_DMEM_CONTROL();
+        SSYNC();
+        bfin_write_DMEM_CONTROL(dmem & ~0xc);
+        SSYNC();
+        bfin_write_DMEM_CONTROL(dmem);
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index a028e9450419..3c98dacbf289 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -49,13 +49,17 @@
 .ifnb \optflushins
         \optflushins [P0];
 .endif
+#if ANOMALY_05000443
 .ifb \optnopins
 2:
 .endif
         \flushins [P0++];
 .ifnb \optnopins
-2: \optnopins;
+2:      \optnopins;
 .endif
+#else
+2:      \flushins [P0++];
+#endif
 
         RTS;
 .endm
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
new file mode 100644
index 000000000000..5d182abefc7b
--- /dev/null
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -0,0 +1,93 @@
+/*
+ * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/blackfin.h>
+
+#include <asm/dma.h>
+#include <asm/clocks.h>
+#include <asm/mem_init.h>
+
+#define PLL_CTL_VAL \
+        (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
+         (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
+
+__attribute__((l1_text))
+static void do_sync(void)
+{
+        __builtin_bfin_ssync();
+}
+
+__attribute__((l1_text))
+void init_clocks(void)
+{
+        /* Kill any active DMAs as they may trigger external memory accesses
+         * in the middle of reprogramming things, and that'll screw us up.
+         * For example, any automatic DMAs left by U-Boot for splash screens.
+         */
+        size_t i;
+        for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
+                struct dma_register *dma = dma_io_base_addr[i];
+                dma->cfg = 0;
+        }
+
+        do_sync();
+
+#ifdef SIC_IWR0
+        bfin_write_SIC_IWR0(IWR_ENABLE(0));
+# ifdef SIC_IWR1
+        /* BF52x system reset does not properly reset SIC_IWR1 which
+         * will screw up the bootrom as it relies on MDMA0/1 waking it
+         * up from IDLE instructions.  See this report for more info:
+         * http://blackfin.uclinux.org/gf/tracker/4323
+         */
+        if (ANOMALY_05000435)
+                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+        else
+                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
+# endif
+# ifdef SIC_IWR2
+        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
+# endif
+#else
+        bfin_write_SIC_IWR(IWR_ENABLE(0));
+#endif
+        do_sync();
+#ifdef EBIU_SDGCTL
+        bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
+        do_sync();
+#endif
+
+#ifdef CLKBUFOE
+        bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
+        do_sync();
+        __asm__ __volatile__("IDLE;");
+#endif
+        bfin_write_PLL_LOCKCNT(0x300);
+        do_sync();
+        bfin_write16(PLL_CTL, PLL_CTL_VAL);
+        __asm__ __volatile__("IDLE;");
+        bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+#ifdef EBIU_SDGCTL
+        bfin_write_EBIU_SDRRC(mem_SDRRC);
+        bfin_write_EBIU_SDGCTL(mem_SDGCTL);
+#else
+        bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
+        do_sync();
+        bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
+        bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
+        bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
+        bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
+#ifdef CONFIG_MEM_EBIU_DDRQUE
+        bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
+#endif
+#endif
+        do_sync();
+        bfin_read16(0);
+}
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index dda5443b37ed..72e16605ca09 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -104,7 +104,7 @@ static int bfin_target(struct cpufreq_policy *policy,
                  cclk_hz, target_freq, freqs.old);
 
         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
                 plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
                 tscale = dpm_state_table[index].tscale;
                 bfin_write_PLL_DIV(plldiv);
@@ -112,10 +112,10 @@ static int bfin_target(struct cpufreq_policy *policy,
                 bfin_write_TSCALE(tscale);
                 cycles = get_cycles();
                 SSYNC();
-        cycles += 10; /* ~10 cycles we loose after get_cycles() */
+        cycles += 10; /* ~10 cycles we lose after get_cycles() */
         __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
         __bfin_cycles_mod = index;
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
         /* TODO: just test case for cycles clock source, remove later */
         pr_debug("cpufreq: done\n");
         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index ad5431e2cd05..4da50bcd9300 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -247,7 +247,8 @@ ENTRY(_unset_dram_srfs)
 ENDPROC(_unset_dram_srfs)
 
 ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
+        defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
         P0.H = hi(SIC_IWR0);
         P0.L = lo(SIC_IWR0);
         P1.H = hi(SIC_IWR1);
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index bde6dc4e2614..fae774651374 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -36,6 +36,7 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 #include <linux/unistd.h>
+#include <linux/threads.h>
 #include <asm/blackfin.h>
 #include <asm/errno.h>
 #include <asm/fixed_code.h>
@@ -75,11 +76,11 @@ ENTRY(_ex_workaround_261)
          * handle it.
          */
         P4 = R7;        /* Store EXCAUSE */
-        p5.l = _last_cplb_fault_retx;
-        p5.h = _last_cplb_fault_retx;
-        r7 = [p5];
+
+        GET_PDA(p5, r7);
+        r7 = [p5 + PDA_LFRETX];
         r6 = retx;
-        [p5] = r6;
+        [p5 + PDA_LFRETX] = r6;
         cc = r6 == r7;
         if !cc jump _bfin_return_from_exception;
         /* fall through */
@@ -111,24 +112,21 @@ ENTRY(_ex_dcplb_viol)
 ENTRY(_ex_dcplb_miss)
 ENTRY(_ex_icplb_miss)
         (R7:6,P5:4) = [sp++];
-        ASTAT = [sp++];
-        SAVE_ALL_SYS
-#ifdef CONFIG_MPU
+        /* We leave the previously pushed ASTAT on the stack.  */
+        SAVE_CONTEXT_CPLB
+
         /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
          * will change the stack pointer.  */
         R0 = SEQSTAT;
         R1 = SP;
-#endif
+
         DEBUG_HWTRACE_SAVE(p5, r7)
-#ifdef CONFIG_MPU
+
         sp += -12;
         call _cplb_hdr;
         sp += 12;
         CC = R0 == 0;
         IF !CC JUMP _handle_bad_cplb;
-#else
-        call __cplb_hdr;
-#endif
 
 #ifdef CONFIG_DEBUG_DOUBLEFAULT
         /* While we were processing this, did we double fault? */
@@ -142,7 +140,8 @@ ENTRY(_ex_icplb_miss)
 #endif
 
         DEBUG_HWTRACE_RESTORE(p5, r7)
-        RESTORE_ALL_SYS
+        RESTORE_CONTEXT_CPLB
+        ASTAT = [SP++];
         SP = EX_SCRATCH_REG;
         rtx;
 ENDPROC(_ex_icplb_miss)
@@ -297,9 +296,8 @@ ENTRY(_handle_bad_cplb)
          * the stack to get ready so, we can fall through - we
          * need to make a CPLB exception look like a normal exception
          */
-
-        RESTORE_ALL_SYS
-        [--sp] = ASTAT;
+        RESTORE_CONTEXT_CPLB
+        /* ASTAT is still on the stack, where it is needed.  */
         [--sp] = (R7:6,P5:4);
 
 ENTRY(_ex_replaceable)
@@ -324,7 +322,9 @@ ENTRY(_ex_trap_c)
         [p4] = p5;
         csync;
 
+        GET_PDA(p5, r6);
 #ifndef CONFIG_DEBUG_DOUBLEFAULT
+
         /*
          * Save these registers, as they are only valid in exception context
          *  (where we are now - as soon as we defer to IRQ5, they can change)
@@ -335,29 +335,25 @@ ENTRY(_ex_trap_c)
         p4.l = lo(DCPLB_FAULT_ADDR);
         p4.h = hi(DCPLB_FAULT_ADDR);
         r7 = [p4];
-        p5.h = _saved_dcplb_fault_addr;
-        p5.l = _saved_dcplb_fault_addr;
-        [p5] = r7;
+        [p5 + PDA_DCPLB] = r7;
 
-        r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
-        p5.h = _saved_icplb_fault_addr;
-        p5.l = _saved_icplb_fault_addr;
-        [p5] = r7;
+        p4.l = lo(ICPLB_FAULT_ADDR);
+        p4.h = hi(ICPLB_FAULT_ADDR);
+        r6 = [p4];
+        [p5 + PDA_ICPLB] = r6;
 
         r6 = retx;
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
-        [p4] = r6;
+        [p5 + PDA_RETX] = r6;
 #endif
         r6 = SYSCFG;
-        [p4 + 4] = r6;
+        [p5 + PDA_SYSCFG] = r6;
         BITCLR(r6, 0);
         SYSCFG = r6;
 
         /* Disable all interrupts, but make sure level 5 is enabled so
          * we can switch to that level.  Save the old mask.  */
         cli r6;
-        [p4 + 8] = r6;
+        [p5 + PDA_EXIMASK] = r6;
 
         p4.l = lo(SAFE_USER_INSTRUCTION);
         p4.h = hi(SAFE_USER_INSTRUCTION);
@@ -371,9 +367,10 @@ ENTRY(_ex_trap_c)
 ENDPROC(_ex_trap_c)
 
 /* We just realized we got an exception, while we were processing a different
- * exception. This is a unrecoverable event, so crash
+ * exception. This is a unrecoverable event, so crash.
+ * Note: this cannot be ENTRY() as we jump here with "if cc jump" ...
  */
-ENTRY(_double_fault)
+_double_fault:
         /* Turn caches & protection off, to ensure we don't get any more
          * double exceptions
          */
@@ -424,17 +421,16 @@ ENDPROC(_double_fault)
 ENTRY(_exception_to_level5)
         SAVE_ALL_SYS
 
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
-        r6 = [p4];
+        GET_PDA(p4, r7);        /* Fetch current PDA */
+        r6 = [p4 + PDA_RETX];
         [sp + PT_PC] = r6;
 
-        r6 = [p4 + 4];
+        r6 = [p4 + PDA_SYSCFG];
         [sp + PT_SYSCFG] = r6;
 
         /* Restore interrupt mask.  We haven't pushed RETI, so this
          * doesn't enable interrupts until we return from this handler.  */
-        r6 = [p4 + 8];
+        r6 = [p4 + PDA_EXIMASK];
         sti r6;
 
         /* Restore the hardware error vector.  */
@@ -478,8 +474,8 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
          * scratch register (for want of a better option).
          */
         EX_SCRATCH_REG = sp;
-        sp.l = _exception_stack_top;
-        sp.h = _exception_stack_top;
+        GET_PDA_SAFE(sp);
+        sp = [sp + PDA_EXSTACK]
         /* Try to deal with syscalls quickly.  */
         [--sp] = ASTAT;
         [--sp] = (R7:6,P5:4);
@@ -501,27 +497,22 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
          * but they are not very interesting, so don't save them
          */
 
+        GET_PDA(p5, r7);
         p4.l = lo(DCPLB_FAULT_ADDR);
         p4.h = hi(DCPLB_FAULT_ADDR);
         r7 = [p4];
-        p5.h = _saved_dcplb_fault_addr;
-        p5.l = _saved_dcplb_fault_addr;
-        [p5] = r7;
+        [p5 + PDA_DCPLB] = r7;
 
-        r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
-        p5.h = _saved_icplb_fault_addr;
-        p5.l = _saved_icplb_fault_addr;
-        [p5] = r7;
+        p4.l = lo(ICPLB_FAULT_ADDR);
+        p4.h = hi(ICPLB_FAULT_ADDR);
+        r7 = [p4];
+        [p5 + PDA_ICPLB] = r7;
 
-        p4.l = _saved_retx;
-        p4.h = _saved_retx;
         r6 = retx;
-        [p4] = r6;
+        [p5 + PDA_RETX] = r6;
 
         r7 = SEQSTAT;           /* reason code is in bit 5:0 */
-        p4.l = _saved_seqstat;
-        p4.h = _saved_seqstat;
-        [p4] = r7;
+        [p5 + PDA_SEQSTAT] = r7;
 #else
         r7 = SEQSTAT;           /* reason code is in bit 5:0 */
 #endif
@@ -546,11 +537,11 @@ ENTRY(_kernel_execve)
         p0 = sp;
         r3 = SIZEOF_PTREGS / 4;
         r4 = 0(x);
-0:
+.Lclear_regs:
         [p0++] = r4;
         r3 += -1;
         cc = r3 == 0;
-        if !cc jump 0b (bp);
+        if !cc jump .Lclear_regs (bp);
 
         p0 = sp;
         sp += -16;
@@ -558,7 +549,7 @@ ENTRY(_kernel_execve)
         call _do_execve;
         SP += 16;
         cc = r0 == 0;
-        if ! cc jump 1f;
+        if ! cc jump .Lexecve_failed;
         /* Success.  Copy our temporary pt_regs to the top of the kernel
          * stack and do a normal exception return.
          */
@@ -574,12 +565,12 @@ ENTRY(_kernel_execve)
         p0 = fp;
         r4 = [p0--];
         r3 = SIZEOF_PTREGS / 4;
-0:
+.Lcopy_regs:
         r4 = [p0--];
         [p1--] = r4;
         r3 += -1;
         cc = r3 == 0;
-        if ! cc jump 0b (bp);
+        if ! cc jump .Lcopy_regs (bp);
 
         r0 = (KERNEL_STACK_SIZE - SIZEOF_PTREGS) (z);
         p1 = r0;
@@ -591,7 +582,7 @@ ENTRY(_kernel_execve)
 
         RESTORE_CONTEXT;
         rti;
-1:
+.Lexecve_failed:
         unlink;
         rts;
 ENDPROC(_kernel_execve)
@@ -925,9 +916,14 @@ _schedule_and_signal_from_int:
         p1 = rets;
         [sp + PT_RESERVED] = p1;
 
-        p0.l = _irq_flags;
-        p0.h = _irq_flags;
+#ifdef CONFIG_SMP
+        GET_PDA(p0, r0);        /* Fetch current PDA (can't migrate to other CPU here) */
+        r0 = [p0 + PDA_IRQFLAGS];
+#else
+        p0.l = _bfin_irq_flags;
+        p0.h = _bfin_irq_flags;
         r0 = [p0];
+#endif
         sti r0;
 
         r0 = sp;
@@ -1539,14 +1535,18 @@ ENTRY(_sys_call_table)
         .endr
 END(_sys_call_table)
 
-_exception_stack:
-        .rept 1024
-        .long 0;
+#ifdef CONFIG_EXCEPTION_L1_SCRATCH
+/* .section .l1.bss.scratch */
+.set _exception_stack_top, L1_SCRATCH_START + L1_SCRATCH_LENGTH
+#else
+#ifdef CONFIG_SYSCALL_TAB_L1
+.section .l1.bss
+#else
+.bss
+#endif
+ENTRY(_exception_stack)
+        .rept 1024 * NR_CPUS
+        .long 0
         .endr
 _exception_stack_top:
-
-#if ANOMALY_05000261
-/* Used by the assembly entry point to work around an anomaly.  */
-_last_cplb_fault_retx:
-        .long 0;
 #endif
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index f123a62e2451..e1e42c029e15 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -13,6 +13,7 @@
 #include <asm/blackfin.h>
 #include <asm/thread_info.h>
 #include <asm/trace.h>
+#include <asm/asm-offsets.h>
 
 __INIT
 
@@ -111,33 +112,26 @@ ENTRY(__start)
          * This happens here, since L1 gets clobbered
          * below
          */
-        p0.l = _saved_retx;
-        p0.h = _saved_retx;
+        GET_PDA(p0, r0);
+        r7 = [p0 + PDA_RETX];
         p1.l = _init_saved_retx;
         p1.h = _init_saved_retx;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_dcplb_fault_addr;
-        p0.h = _saved_dcplb_fault_addr;
+        r7 = [p0 + PDA_DCPLB];
         p1.l = _init_saved_dcplb_fault_addr;
         p1.h = _init_saved_dcplb_fault_addr;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_icplb_fault_addr;
-        p0.h = _saved_icplb_fault_addr;
+        r7 = [p0 + PDA_ICPLB];
         p1.l = _init_saved_icplb_fault_addr;
         p1.h = _init_saved_icplb_fault_addr;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 
-        p0.l = _saved_seqstat;
-        p0.h = _saved_seqstat;
+        r7 = [p0 + PDA_SEQSTAT];
         p1.l = _init_saved_seqstat;
         p1.h = _init_saved_seqstat;
-        r0 = [p0];
-        [p1] = r0;
+        [p1] = r7;
 #endif
 
         /* Initialize stack pointer */
@@ -153,7 +147,7 @@ ENTRY(__start)
         /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
         call _bfin_relocate_l1_mem;
 #ifdef CONFIG_BFIN_KERNEL_CLOCK
-        call _start_dma_code;
+        call _init_clocks;
 #endif
 
         /* This section keeps the processor in supervisor mode
@@ -170,12 +164,8 @@ ENTRY(__start)
         [p0] = p1;
         csync;
 
-        p0.l = lo(IMASK);
-        p0.h = hi(IMASK);
-        p1.l = IMASK_IVG15;
-        p1.h = 0x0;
-        [p0] = p1;
-        csync;
+        r0 = EVT_IVG15 (z);
+        sti r0;
 
         raise 15;
         p0.l = .LWAIT_HERE;
@@ -195,6 +185,19 @@ ENDPROC(__start)
 # define WDOG_CTL WDOGA_CTL
 #endif
 
+ENTRY(__init_clear_bss)
+        r2 = r2 - r1;
+        cc = r2 == 0;
+        if cc jump .L_bss_done;
+        r2 >>= 2;
+        p1 = r1;
+        p2 = r2;
+        lsetup (1f, 1f) lc0 = p2;
+1:      [p1++] = r0;
+.L_bss_done:
+        rts;
+ENDPROC(__init_clear_bss)
+
 ENTRY(_real_start)
         /* Enable nested interrupts */
         [--sp] = reti;
@@ -206,87 +209,34 @@ ENTRY(_real_start)
         w[p0] = r0;
         ssync;
 
+        r0 = 0 (x);
+        /* Zero out all of the fun bss regions */
 #if L1_DATA_A_LENGTH > 0
         r1.l = __sbss_l1;
         r1.h = __sbss_l1;
         r2.l = __ebss_l1;
         r2.h = __ebss_l1;
-        r0 = 0 (z);
-        r2 = r2 - r1;
-        cc = r2 == 0;
-        if cc jump .L_a_l1_done;
-        r2 >>= 2;
-        p1 = r1;
-        p2 = r2;
-        lsetup (.L_clear_a_l1, .L_clear_a_l1 ) lc0 = p2;
-.L_clear_a_l1:
-        [p1++] = r0;
-.L_a_l1_done:
+        call __init_clear_bss
 #endif
-
 #if L1_DATA_B_LENGTH > 0
         r1.l = __sbss_b_l1;
         r1.h = __sbss_b_l1;
         r2.l = __ebss_b_l1;
         r2.h = __ebss_b_l1;
-        r0 = 0 (z);
-        r2 = r2 - r1;
-        cc = r2 == 0;
-        if cc jump .L_b_l1_done;
-        r2 >>= 2;
-        p1 = r1;
-        p2 = r2;
-        lsetup (.L_clear_b_l1, .L_clear_b_l1 ) lc0 = p2;
-.L_clear_b_l1:
-        [p1++] = r0;
-.L_b_l1_done:
+        call __init_clear_bss
 #endif
-
 #if L2_LENGTH > 0
         r1.l = __sbss_l2;
         r1.h = __sbss_l2;
         r2.l = __ebss_l2;
         r2.h = __ebss_l2;
-        r0 = 0 (z);
-        r2 = r2 - r1;
-        cc = r2 == 0;
-        if cc jump .L_l2_done;
-        r2 >>= 2;
-        p1 = r1;
-        p2 = r2;
-        lsetup (.L_clear_l2, .L_clear_l2 ) lc0 = p2;
-.L_clear_l2:
-        [p1++] = r0;
-.L_l2_done:
+        call __init_clear_bss
 #endif
-
-        /* Zero out the bss region
-         * Note: this will fail if bss is 0 bytes ...
-         */
-        r0 = 0 (z);
         r1.l = ___bss_start;
         r1.h = ___bss_start;
         r2.l = ___bss_stop;
         r2.h = ___bss_stop;
-        r2 = r2 - r1;
-        r2 >>= 2;
-        p1 = r1;
-        p2 = r2;
-        lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
-.L_clear_bss:
-        [p1++] = r0;
-
-        /* In case there is a NULL pointer reference,
-         * zero out region before stext
-         */
-        p1 = r0;
-        r2.l = __stext;
-        r2.h = __stext;
-        r2 >>= 2;
-        p2 = r2;
-        lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
-.L_clear_zero:
-        [p1++] = r0;
+        call __init_clear_bss
 
         /* Pass the u-boot arguments to the global value command line */
         R0 = R7;
@@ -299,6 +249,9 @@ ENTRY(_real_start)
         sp = sp + p1;
         usp = sp;
         fp = sp;
+        sp += -12;
+        call _init_pda
+        sp += 12;
         jump.l _start_kernel;
 ENDPROC(_real_start)
 
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 4a2ec7a9675a..473df0f7fa78 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -129,8 +129,15 @@ __common_int_entry:
 #endif
         r1 =  sp;
         SP += -12;
+#ifdef CONFIG_IPIPE
+        call ___ipipe_grab_irq
+        SP += 12;
+        cc = r0 == 0;
+        if cc jump .Lcommon_restore_context;
+#else /* CONFIG_IPIPE */
         call _do_irq;
         SP += 12;
+#endif /* CONFIG_IPIPE */
         call _return_from_int;
 .Lcommon_restore_context:
         RESTORE_CONTEXT
@@ -152,15 +159,6 @@ ENTRY(_evt_ivhw)
 1:
 #endif
 
-#ifdef CONFIG_HARDWARE_PM
-        r7 = [sp + PT_SEQSTAT];
-        r7 = r7 >>> 0xe;
-        r6 = 0x1F;
-        r7 = r7 & r6;
-        r5 = 0x12;
-        cc = r7 == r5;
-        if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */
-#endif
         # We are going to dump something out, so make sure we print IPEND properly
         p2.l = lo(IPEND);
         p2.h = hi(IPEND);
@@ -192,17 +190,6 @@ ENTRY(_evt_ivhw)
 .Lcommon_restore_all_sys:
         RESTORE_ALL_SYS
         rti;
-
-#ifdef CONFIG_HARDWARE_PM
-.Lcall_do_ovf:
-
-        SP += -12;
-        call _pm_overflow;
-        SP += 12;
-
-        jump .Lcommon_restore_all_sys;
-#endif
-
 ENDPROC(_evt_ivhw)
 
 /* Interrupt routine for evt2 (NMI).
@@ -245,3 +232,56 @@ ENTRY(_evt_system_call)
         call _system_call;
         jump .Lcommon_restore_context;
 ENDPROC(_evt_system_call)
+
+#ifdef CONFIG_IPIPE
+ENTRY(___ipipe_call_irqtail)
+        r0.l = 1f;
+        r0.h = 1f;
+        reti = r0;
+        rti;
+1:
+        [--sp] = rets;
+        [--sp] = ( r7:4, p5:3 );
+        p0.l = ___ipipe_irq_tail_hook;
+        p0.h = ___ipipe_irq_tail_hook;
+        p0 = [p0];
+        sp += -12;
+        call (p0);
+        sp += 12;
+        ( r7:4, p5:3 ) = [sp++];
+        rets = [sp++];
+
+        [--sp] = reti;
+        reti = [sp++];          /* IRQs are off. */
+        r0.h = 3f;
+        r0.l = 3f;
+        p0.l = lo(EVT14);
+        p0.h = hi(EVT14);
+        [p0] = r0;
+        csync;
+        r0 = 0x401f;
+        sti r0;
+        raise 14;
+        [--sp] = reti;          /* IRQs on. */
+2:
+        jump 2b;                /* Likely paranoid. */
+3:
+        sp += 4;                /* Discard saved RETI */
+        r0.h = _evt14_softirq;
+        r0.l = _evt14_softirq;
+        p0.l = lo(EVT14);
+        p0.h = hi(EVT14);
+        [p0] = r0;
+        csync;
+        p0.l = _bfin_irq_flags;
+        p0.h = _bfin_irq_flags;
+        r0 = [p0];
+        sti r0;
+#if 0 /* FIXME: this actually raises scheduling latencies */
+        /* Reenable interrupts */
+        [--sp] = reti;
+        r0 = [sp++];
+#endif
+        rts;
+ENDPROC(___ipipe_call_irqtail)
+#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 34e8a726ffda..1bba6030dce9 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1,9 +1,6 @@
 /*
  * File:         arch/blackfin/mach-common/ints-priority.c
- * Based on:
- * Author:
  *
- * Created:      ?
  * Description:  Set up the interrupt priorities
  *
  * Modified:
@@ -37,6 +34,9 @@
 #include <linux/kernel_stat.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
+#ifdef CONFIG_IPIPE
+#include <linux/ipipe.h>
+#endif
 #ifdef CONFIG_KGDB
 #include <linux/kgdb.h>
 #endif
@@ -45,6 +45,8 @@
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
 
+#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
+
 #ifdef BF537_FAMILY
 # define BF537_GENERIC_ERROR_INT_DEMUX
 #else
@@ -58,13 +60,16 @@
  * -
  */
 
+#ifndef CONFIG_SMP
 /* Initialize this to an actual value to force it into the .data
  * section so that we know it is properly initialized at entry into
  * the kernel but before bss is initialized to zero (which is where
  * it would live otherwise).  The 0x1f magic represents the IRQs we
  * cannot actually mask out in hardware.
  */
-unsigned long irq_flags = 0x1f;
+unsigned long bfin_irq_flags = 0x1f;
+EXPORT_SYMBOL(bfin_irq_flags);
+#endif
 
 /* The number of spurious interrupts */
 atomic_t num_spurious;
@@ -103,12 +108,14 @@ static void __init search_IAR(void)
                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
                         int iar_shift = (irqn & 7) * 4;
                                 if (ivg == (0xf &
-#ifndef CONFIG_BF52x
+#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
+        || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
                              bfin_read32((unsigned long *)SIC_IAR0 +
-                                         (irqn >> 3)) >> iar_shift)) {
+                                         ((irqn % 32) >> 3) + ((irqn / 32) *
+                                         ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
 #else
                              bfin_read32((unsigned long *)SIC_IAR0 +
-                                         ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
+                                         (irqn >> 3)) >> iar_shift)) {
 #endif
                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
@@ -130,25 +137,25 @@ static void bfin_ack_noop(unsigned int irq)
 
 static void bfin_core_mask_irq(unsigned int irq)
 {
-        irq_flags &= ~(1 << irq);
-        if (!irqs_disabled())
-                local_irq_enable();
+        bfin_irq_flags &= ~(1 << irq);
+        if (!irqs_disabled_hw())
+                local_irq_enable_hw();
 }
 
 static void bfin_core_unmask_irq(unsigned int irq)
 {
-        irq_flags |= 1 << irq;
+        bfin_irq_flags |= 1 << irq;
         /*
          * If interrupts are enabled, IMASK must contain the same value
-         * as irq_flags.  Make sure that invariant holds.  If interrupts
+         * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
          * are currently disabled we need not do anything; one of the
          * callers will take care of setting IMASK to the proper value
          * when reenabling interrupts.
-         * local_irq_enable just does "STI irq_flags", so it's exactly
+         * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
          * what we need.
          */
-        if (!irqs_disabled())
-                local_irq_enable();
+        if (!irqs_disabled_hw())
+                local_irq_enable_hw();
         return;
 }
 
@@ -163,8 +170,11 @@ static void bfin_internal_mask_irq(unsigned int irq)
         mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
                              ~(1 << mask_bit));
+#ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
+                             ~(1 << mask_bit));
+#endif
 #endif
-        SSYNC();
 }
 
 static void bfin_internal_unmask_irq(unsigned int irq)
@@ -178,14 +188,17 @@ static void bfin_internal_unmask_irq(unsigned int irq)
         mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
                              (1 << mask_bit));
+#ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
+                             (1 << mask_bit));
+#endif
 #endif
-        SSYNC();
 }
 
 #ifdef CONFIG_PM
 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 {
-        unsigned bank, bit, wakeup = 0;
+        u32 bank, bit, wakeup = 0;
         unsigned long flags;
         bank = SIC_SYSIRQ(irq) / 32;
         bit = SIC_SYSIRQ(irq) % 32;
@@ -225,7 +238,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
         break;
         }
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         if (state) {
                 bfin_sic_iwr[bank] |= (1 << bit);
@@ -236,7 +249,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
                 vr_wakeup  &= ~wakeup;
         }
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 
         return 0;
 }
@@ -262,6 +275,19 @@ static struct irq_chip bfin_internal_irqchip = {
 #endif
 };
 
+static void bfin_handle_irq(unsigned irq)
+{
+#ifdef CONFIG_IPIPE
+        struct pt_regs regs;    /* Contents not used. */
+        ipipe_trace_irq_entry(irq);
+        __ipipe_handle_irq(irq, &regs);
+        ipipe_trace_irq_exit(irq);
+#else /* !CONFIG_IPIPE */
+        struct irq_desc *desc = irq_desc + irq;
+        desc->handle_irq(irq, desc);
+#endif  /* !CONFIG_IPIPE */
+}
+
 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 static int error_int_mask;
 
@@ -292,8 +318,6 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
 {
         int irq = 0;
 
-        SSYNC();
-
 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
                 irq = IRQ_MAC_ERROR;
@@ -317,10 +341,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
                 irq = IRQ_UART1_ERROR;
 
         if (irq) {
-                if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
-                        struct irq_desc *desc = irq_desc + irq;
-                        desc->handle_irq(irq, desc);
-                } else {
+                if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
+                        bfin_handle_irq(irq);
+                else {
 
                         switch (irq) {
                         case IRQ_PPI_ERROR:
@@ -366,62 +389,57 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
 
 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 {
+#ifdef CONFIG_IPIPE
+        _set_irq_handler(irq, handle_edge_irq);
+#else
         struct irq_desc *desc = irq_desc + irq;
         /* May not call generic set_irq_handler() due to spinlock
            recursion. */
         desc->handle_irq = handle;
+#endif
 }
 
-#if !defined(CONFIG_BF54x)
-
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
-static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
-
+static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 extern void bfin_gpio_irq_prepare(unsigned gpio);
 
+#if !defined(CONFIG_BF54x)
+
 static void bfin_gpio_ack_irq(unsigned int irq)
 {
-        u16 gpionr = irq - IRQ_PF0;
-
-        if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
-                set_gpio_data(gpionr, 0);
-                SSYNC();
-        }
+        /* AFAIK ack_irq in case mask_ack is provided
+         * get's only called for edge sense irqs
+         */
+        set_gpio_data(irq_to_gpio(irq), 0);
 }
 
 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 {
-        u16 gpionr = irq - IRQ_PF0;
+        struct irq_desc *desc = irq_desc + irq;
+        u32 gpionr = irq_to_gpio(irq);
 
-        if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
+        if (desc->handle_irq == handle_edge_irq)
                 set_gpio_data(gpionr, 0);
-                SSYNC();
-        }
 
         set_gpio_maska(gpionr, 0);
-        SSYNC();
 }
 
 static void bfin_gpio_mask_irq(unsigned int irq)
 {
-        set_gpio_maska(irq - IRQ_PF0, 0);
-        SSYNC();
+        set_gpio_maska(irq_to_gpio(irq), 0);
 }
 
 static void bfin_gpio_unmask_irq(unsigned int irq)
 {
-        set_gpio_maska(irq - IRQ_PF0, 1);
-        SSYNC();
+        set_gpio_maska(irq_to_gpio(irq), 1);
 }
 
 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 {
-        u16 gpionr = irq - IRQ_PF0;
+        u32 gpionr = irq_to_gpio(irq);
 
-        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
+        if (__test_and_set_bit(gpionr, gpio_enabled))
                 bfin_gpio_irq_prepare(gpionr);
 
-        gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
         bfin_gpio_unmask_irq(irq);
 
         return 0;
@@ -429,29 +447,39 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 
 static void bfin_gpio_irq_shutdown(unsigned int irq)
 {
+        u32 gpionr = irq_to_gpio(irq);
+
         bfin_gpio_mask_irq(irq);
-        gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
+        __clear_bit(gpionr, gpio_enabled);
+        bfin_gpio_irq_free(gpionr);
 }
 
 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 {
-        u16 gpionr = irq - IRQ_PF0;
+        int ret;
+        char buf[16];
+        u32 gpionr = irq_to_gpio(irq);
 
         if (type == IRQ_TYPE_PROBE) {
                 /* only probe unenabled GPIO interrupt lines */
-                if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
+                if (__test_bit(gpionr, gpio_enabled))
                         return 0;
                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
         }
 
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
+
+                snprintf(buf, 16, "gpio-irq%d", irq);
+                ret = bfin_gpio_irq_request(gpionr, buf);
+                if (ret)
+                        return ret;
+
+                if (__test_and_set_bit(gpionr, gpio_enabled))
                         bfin_gpio_irq_prepare(gpionr);
 
-                gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
         } else {
-                gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
+                __clear_bit(gpionr, gpio_enabled);
                 return 0;
         }
 
@@ -472,17 +500,13 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
                 set_gpio_edge(gpionr, 1);
                 set_gpio_inen(gpionr, 1);
-                gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
                 set_gpio_data(gpionr, 0);
 
         } else {
                 set_gpio_edge(gpionr, 0);
-                gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
                 set_gpio_inen(gpionr, 1);
         }
 
-        SSYNC();
-
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
                 bfin_set_irq_handler(irq, handle_edge_irq);
         else
@@ -505,22 +529,6 @@ int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 }
 #endif
 
-static struct irq_chip bfin_gpio_irqchip = {
-        .name = "GPIO",
-        .ack = bfin_gpio_ack_irq,
-        .mask = bfin_gpio_mask_irq,
-        .mask_ack = bfin_gpio_mask_ack_irq,
-        .unmask = bfin_gpio_unmask_irq,
-        .disable = bfin_gpio_mask_irq,
-        .enable = bfin_gpio_unmask_irq,
-        .set_type = bfin_gpio_irq_type,
-        .startup = bfin_gpio_irq_startup,
-        .shutdown = bfin_gpio_irq_shutdown,
-#ifdef CONFIG_PM
-        .set_wake = bfin_gpio_set_wake,
-#endif
-};
-
 static void bfin_demux_gpio_irq(unsigned int inta_irq,
                                 struct irq_desc *desc)
 {
@@ -537,7 +545,11 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
                 irq = IRQ_PH0;
                 break;
 # endif
-#elif defined(CONFIG_BF52x)
+#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+        case IRQ_PORTF_INTA:
+                irq = IRQ_PF0;
+                break;
+#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
         case IRQ_PORTF_INTA:
                 irq = IRQ_PF0;
                 break;
@@ -567,30 +579,22 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
                         irq += i;
 
-                        mask = get_gpiop_data(i) &
-                                (gpio_enabled[gpio_bank(i)] &
-                                get_gpiop_maska(i));
+                        mask = get_gpiop_data(i) & get_gpiop_maska(i);
 
                         while (mask) {
-                                if (mask & 1) {
-                                        desc = irq_desc + irq;
-                                        desc->handle_irq(irq, desc);
-                                }
+                                if (mask & 1)
+                                        bfin_handle_irq(irq);
                                 irq++;
                                 mask >>= 1;
                         }
                 }
         } else {
                         gpio = irq_to_gpio(irq);
-                        mask = get_gpiop_data(gpio) &
-                                (gpio_enabled[gpio_bank(gpio)] &
-                                get_gpiop_maska(gpio));
+                        mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 
                         do {
-                                if (mask & 1) {
-                                        desc = irq_desc + irq;
-                                        desc->handle_irq(irq, desc);
-                                }
+                                if (mask & 1)
+                                        bfin_handle_irq(irq);
                                 irq++;
                                 mask >>= 1;
                         } while (mask);
@@ -612,10 +616,6 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
 static unsigned char irq2pint_lut[NR_PINTS];
 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 
-static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
-
-
 struct pin_int_t {
         unsigned int mask_set;
         unsigned int mask_clear;
@@ -636,12 +636,9 @@ static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
         (struct pin_int_t *)PINT3_MASK_SET,
 };
 
-extern void bfin_gpio_irq_prepare(unsigned gpio);
-
-inline unsigned short get_irq_base(u8 bank, u8 bmap)
+inline unsigned int get_irq_base(u32 bank, u8 bmap)
 {
-
-        u16 irq_base;
+        unsigned int irq_base;
 
         if (bank < 2) {         /*PA-PB */
                 irq_base = IRQ_PA0 + bmap * 16;
@@ -650,7 +647,6 @@ inline unsigned short get_irq_base(u8 bank, u8 bmap)
         }
 
         return irq_base;
-
 }
 
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
@@ -677,20 +673,18 @@ void init_pint_lut(void)
 
                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
-
                 }
-
         }
-
 }
 
 static void bfin_gpio_ack_irq(unsigned int irq)
 {
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        struct irq_desc *desc = irq_desc + irq;
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
-        u8 bank = PINT_2_BANK(pint_val);
+        u32 bank = PINT_2_BANK(pint_val);
 
-        if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
+        if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                 if (pint[bank]->invert_set & pintbit)
                         pint[bank]->invert_clear = pintbit;
                 else
@@ -698,16 +692,16 @@ static void bfin_gpio_ack_irq(unsigned int irq)
         }
         pint[bank]->request = pintbit;
 
-        SSYNC();
 }
 
 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 {
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        struct irq_desc *desc = irq_desc + irq;
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
-        u8 bank = PINT_2_BANK(pint_val);
+        u32 bank = PINT_2_BANK(pint_val);
 
-        if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
+        if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                 if (pint[bank]->invert_set & pintbit)
                         pint[bank]->invert_clear = pintbit;
                 else
@@ -716,32 +710,29 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
 
         pint[bank]->request = pintbit;
         pint[bank]->mask_clear = pintbit;
-        SSYNC();
 }
 
 static void bfin_gpio_mask_irq(unsigned int irq)
 {
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 
         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
-        SSYNC();
 }
 
 static void bfin_gpio_unmask_irq(unsigned int irq)
 {
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
-        u8 bank = PINT_2_BANK(pint_val);
+        u32 bank = PINT_2_BANK(pint_val);
 
         pint[bank]->request = pintbit;
         pint[bank]->mask_set = pintbit;
-        SSYNC();
 }
 
 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 {
-        u16 gpionr = irq_to_gpio(irq);
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 gpionr = irq_to_gpio(irq);
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 
         if (pint_val == IRQ_NOT_AVAIL) {
                 printk(KERN_ERR
@@ -750,10 +741,9 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
                 return -ENODEV;
         }
 
-        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
+        if (__test_and_set_bit(gpionr, gpio_enabled))
                 bfin_gpio_irq_prepare(gpionr);
 
-        gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
         bfin_gpio_unmask_irq(irq);
 
         return 0;
@@ -761,38 +751,45 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 
 static void bfin_gpio_irq_shutdown(unsigned int irq)
 {
-        u16 gpionr = irq_to_gpio(irq);
+        u32 gpionr = irq_to_gpio(irq);
 
         bfin_gpio_mask_irq(irq);
-        gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
+        __clear_bit(gpionr, gpio_enabled);
+        bfin_gpio_irq_free(gpionr);
 }
 
 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 {
-
-        u16 gpionr = irq_to_gpio(irq);
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        int ret;
+        char buf[16];
+        u32 gpionr = irq_to_gpio(irq);
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
-        u8 bank = PINT_2_BANK(pint_val);
+        u32 bank = PINT_2_BANK(pint_val);
 
         if (pint_val == IRQ_NOT_AVAIL)
                 return -ENODEV;
 
         if (type == IRQ_TYPE_PROBE) {
                 /* only probe unenabled GPIO interrupt lines */
-                if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
+                if (__test_bit(gpionr, gpio_enabled))
                         return 0;
                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
         }
 
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
+
+                snprintf(buf, 16, "gpio-irq%d", irq);
+                ret = bfin_gpio_irq_request(gpionr, buf);
+                if (ret)
+                        return ret;
+
+                if (__test_and_set_bit(gpionr, gpio_enabled))
                         bfin_gpio_irq_prepare(gpionr);
 
-                gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
         } else {
-                gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
+                __clear_bit(gpionr, gpio_enabled);
                 return 0;
         }
 
@@ -803,15 +800,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 
         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-
-                gpio_both_edge_triggered[bank] |= pintbit;
-
                 if (gpio_get_value(gpionr))
                         pint[bank]->invert_set = pintbit;
                 else
                         pint[bank]->invert_clear = pintbit;
-        } else {
-                gpio_both_edge_triggered[bank] &= ~pintbit;
         }
 
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
@@ -822,8 +814,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
                 bfin_set_irq_handler(irq, handle_level_irq);
         }
 
-        SSYNC();
-
         return 0;
 }
 
@@ -834,7 +824,7 @@ u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 {
         u32 pint_irq;
-        u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+        u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
         u32 bank = PINT_2_BANK(pint_val);
         u32 pintbit = PINT_BIT(pint_val);
 
@@ -895,26 +885,10 @@ void bfin_pm_restore(void)
 }
 #endif
 
-static struct irq_chip bfin_gpio_irqchip = {
-        .name = "GPIO",
-        .ack = bfin_gpio_ack_irq,
-        .mask = bfin_gpio_mask_irq,
-        .mask_ack = bfin_gpio_mask_ack_irq,
-        .unmask = bfin_gpio_unmask_irq,
-        .disable = bfin_gpio_mask_irq,
-        .enable = bfin_gpio_unmask_irq,
-        .set_type = bfin_gpio_irq_type,
-        .startup = bfin_gpio_irq_startup,
-        .shutdown = bfin_gpio_irq_shutdown,
-#ifdef CONFIG_PM
-        .set_wake = bfin_gpio_set_wake,
-#endif
-};
-
 static void bfin_demux_gpio_irq(unsigned int inta_irq,
                                 struct irq_desc *desc)
 {
-        u8 bank, pint_val;
+        u32 bank, pint_val;
         u32 request, irq;
 
         switch (inta_irq) {
@@ -941,8 +915,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
         while (request) {
                 if (request & 1) {
                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
-                        desc = irq_desc + irq;
-                        desc->handle_irq(irq, desc);
+                        bfin_handle_irq(irq);
                 }
                 pint_val++;
                 request >>= 1;
@@ -951,10 +924,24 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
 }
 #endif
 
-void __init init_exception_vectors(void)
-{
-        SSYNC();
+static struct irq_chip bfin_gpio_irqchip = {
+        .name = "GPIO",
+        .ack = bfin_gpio_ack_irq,
+        .mask = bfin_gpio_mask_irq,
+        .mask_ack = bfin_gpio_mask_ack_irq,
+        .unmask = bfin_gpio_unmask_irq,
+        .disable = bfin_gpio_mask_irq,
+        .enable = bfin_gpio_unmask_irq,
+        .set_type = bfin_gpio_irq_type,
+        .startup = bfin_gpio_irq_startup,
+        .shutdown = bfin_gpio_irq_shutdown,
+#ifdef CONFIG_PM
+        .set_wake = bfin_gpio_set_wake,
+#endif
+};
 
+void __cpuinit init_exception_vectors(void)
+{
         /* cannot program in software:
          * evt0 - emulation (jtag)
          * evt1 - reset
@@ -979,17 +966,23 @@ void __init init_exception_vectors(void)
  * This function should be called during kernel startup to initialize
  * the BFin IRQ handling routines.
  */
+
 int __init init_arch_irq(void)
 {
         int irq;
         unsigned long ilat = 0;
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
+        || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 # ifdef CONFIG_BF54x
         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 # endif
+# ifdef CONFIG_SMP
+        bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
+        bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
+# endif
 #else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
@@ -1029,7 +1022,7 @@ int __init init_arch_irq(void)
                 case IRQ_PINT1:
                 case IRQ_PINT2:
                 case IRQ_PINT3:
-#elif defined(CONFIG_BF52x)
+#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
                 case IRQ_PORTF_INTA:
                 case IRQ_PORTG_INTA:
                 case IRQ_PORTH_INTA:
@@ -1037,18 +1030,41 @@ int __init init_arch_irq(void)
                 case IRQ_PROG0_INTA:
                 case IRQ_PROG1_INTA:
                 case IRQ_PROG2_INTA:
+#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+                case IRQ_PORTF_INTA:
 #endif
+
                         set_irq_chained_handler(irq,
                                                 bfin_demux_gpio_irq);
                         break;
 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
                 case IRQ_GENERIC_ERROR:
-                        set_irq_handler(irq, bfin_demux_error_irq);
-
+                        set_irq_chained_handler(irq, bfin_demux_error_irq);
+                        break;
+#endif
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
+                case IRQ_TIMER0:
+                        set_irq_handler(irq, handle_percpu_irq);
+                        break;
+#endif
+#ifdef CONFIG_SMP
+                case IRQ_SUPPLE_0:
+                case IRQ_SUPPLE_1:
+                        set_irq_handler(irq, handle_percpu_irq);
                         break;
 #endif
                 default:
+#ifdef CONFIG_IPIPE
+        /*
+         * We want internal interrupt sources to be masked, because
+         * ISRs may trigger interrupts recursively (e.g. DMA), but
+         * interrupts are _not_ masked at CPU level. So let's handle
+         * them as level interrupts.
+         */
+                        set_irq_handler(irq, handle_level_irq);
+#else /* !CONFIG_IPIPE */
                         set_irq_handler(irq, handle_simple_irq);
+#endif /* !CONFIG_IPIPE */
                         break;
                 }
         }
@@ -1073,7 +1089,7 @@ int __init init_arch_irq(void)
         CSYNC();
 
         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-        /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
+        /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
          * local_irq_enable()
          */
         program_IAR();
@@ -1081,19 +1097,23 @@ int __init init_arch_irq(void)
         search_IAR();
 
         /* Enable interrupts IVG7-15 */
-        irq_flags = irq_flags | IMASK_IVG15 |
+        bfin_irq_flags |= IMASK_IVG15 |
             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
+        || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-#if defined(CONFIG_BF52x)
-        /* BF52x system reset does not properly reset SIC_IWR1 which
+#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
+        /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
          * will screw up the bootrom as it relies on MDMA0/1 waking it
          * up from IDLE instructions.  See this report for more info:
          * http://blackfin.uclinux.org/gf/tracker/4323
          */
-        bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+        if (ANOMALY_05000435)
+                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+        else
+                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 #else
         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 #endif
@@ -1104,6 +1124,14 @@ int __init init_arch_irq(void)
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
 
+#ifdef CONFIG_IPIPE
+        for (irq = 0; irq < NR_IRQS; irq++) {
+                struct irq_desc *desc = irq_desc + irq;
+                desc->ic_prio = __ipipe_get_irq_priority(irq);
+                desc->thr_prio = __ipipe_get_irqthread_priority(irq);
+        }
+#endif /* CONFIG_IPIPE */
+
         return 0;
 }
 
@@ -1117,11 +1145,20 @@ void do_irq(int vec, struct pt_regs *fp)
         } else {
                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
+        || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
                 unsigned long sic_status[3];
 
-                sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
-                sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+                if (smp_processor_id()) {
+#ifdef CONFIG_SMP
+                        /* This will be optimized out in UP mode. */
+                        sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
+                        sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
+#endif
+                } else {
+                        sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+                        sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+                }
 #ifdef CONFIG_BF54x
                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
 #endif
@@ -1150,3 +1187,161 @@ void do_irq(int vec, struct pt_regs *fp)
         }
         asm_do_IRQ(vec, fp);
 }
+
+#ifdef CONFIG_IPIPE
+
+int __ipipe_get_irq_priority(unsigned irq)
+{
+        int ient, prio;
+
+        if (irq <= IRQ_CORETMR)
+                return irq;
+
+        for (ient = 0; ient < NR_PERI_INTS; ient++) {
+                struct ivgx *ivg = ivg_table + ient;
+                if (ivg->irqno == irq) {
+                        for (prio = 0; prio <= IVG13-IVG7; prio++) {
+                                if (ivg7_13[prio].ifirst <= ivg &&
+                                    ivg7_13[prio].istop > ivg)
+                                        return IVG7 + prio;
+                        }
+                }
+        }
+
+        return IVG15;
+}
+
+int __ipipe_get_irqthread_priority(unsigned irq)
+{
+        int ient, prio;
+        int demux_irq;
+
+        /* The returned priority value is rescaled to [0..IVG13+1]
+         * with 0 being the lowest effective priority level. */
+
+        if (irq <= IRQ_CORETMR)
+                return IVG13 - irq + 1;
+
+        /* GPIO IRQs are given the priority of the demux
+         * interrupt. */
+        if (IS_GPIOIRQ(irq)) {
+#if defined(CONFIG_BF54x)
+                u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
+                demux_irq = (bank == 0 ? IRQ_PINT0 :
+                                bank == 1 ? IRQ_PINT1 :
+                                bank == 2 ? IRQ_PINT2 :
+                                IRQ_PINT3);
+#elif defined(CONFIG_BF561)
+                demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
+                                irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
+                                IRQ_PROG0_INTA);
+#elif defined(CONFIG_BF52x)
+                demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
+                                irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
+                                IRQ_PORTF_INTA);
+#else
+                demux_irq = irq;
+#endif
+                return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
+        }
+
+        /* The GPIO demux interrupt is given a lower priority
+         * than the GPIO IRQs, so that its threaded handler
+         * unmasks the interrupt line after the decoded IRQs
+         * have been processed. */
+        prio = PRIO_GPIODEMUX(irq);
+        /* demux irq? */
+        if (prio != -1)
+                return IVG13 - prio;
+
+        for (ient = 0; ient < NR_PERI_INTS; ient++) {
+                struct ivgx *ivg = ivg_table + ient;
+                if (ivg->irqno == irq) {
+                        for (prio = 0; prio <= IVG13-IVG7; prio++) {
+                                if (ivg7_13[prio].ifirst <= ivg &&
+                                    ivg7_13[prio].istop > ivg)
+                                        return IVG7 - prio;
+                        }
+                }
+        }
+
+        return 0;
+}
+
+/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
+asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
+{
+        struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
+        struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
+        int irq;
+
+        if (likely(vec == EVT_IVTMR_P)) {
+                irq = IRQ_CORETMR;
+                goto handle_irq;
+        }
+
+        SSYNC();
+
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
+        {
+                unsigned long sic_status[3];
+
+                sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+                sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+#ifdef CONFIG_BF54x
+                sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+#endif
+                for (;; ivg++) {
+                        if (ivg >= ivg_stop) {
+                                atomic_inc(&num_spurious);
+                                return 0;
+                        }
+                        if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
+                                break;
+                }
+        }
+#else
+        {
+                unsigned long sic_status;
+
+                sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+
+                for (;; ivg++) {
+                        if (ivg >= ivg_stop) {
+                                atomic_inc(&num_spurious);
+                                return 0;
+                        } else if (sic_status & ivg->isrflag)
+                                break;
+                }
+        }
+#endif
+
+        irq = ivg->irqno;
+
+        if (irq == IRQ_SYSTMR) {
+                bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
+                /* This is basically what we need from the register frame. */
+                __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
+                __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
+                if (!ipipe_root_domain_p)
+                        __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
+                else
+                        __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
+        }
+
+handle_irq:
+
+        ipipe_trace_irq_entry(irq);
+        __ipipe_handle_irq(irq, regs);
+       ipipe_trace_irq_exit(irq);
+
+       if (ipipe_root_domain_p)
+                return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
+
+       return 0;
+}
+
+#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c
index 606ded9ff4e1..05004df0f78b 100644
--- a/arch/blackfin/mach-common/irqpanic.c
+++ b/arch/blackfin/mach-common/irqpanic.c
@@ -33,8 +33,6 @@
 #include <asm/traps.h>
 #include <asm/blackfin.h>
 
-#include "../oprofile/op_blackfin.h"
-
 #ifdef CONFIG_DEBUG_ICACHE_CHECK
 #define L1_ICACHE_START 0xffa10000
 #define L1_ICACHE_END   0xffa13fff
@@ -134,13 +132,3 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs)
 #endif
 
 }
-
-#ifdef CONFIG_HARDWARE_PM
-/*
- * call the handler of Performance overflow
- */
-asmlinkage void pm_overflow(int irq, struct pt_regs *regs)
-{
-        pm_overflow_handler(irq, regs);
-}
-#endif
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 9daf01201e9f..6c5f5f0ea7fe 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -160,7 +160,7 @@ ENDPROC(_cache_grab_lock)
  * R0 - Which way to be locked
  */
 
-ENTRY(_cache_lock)
+ENTRY(_bfin_cache_lock)
 
         [--SP]=( R7:0,P5:0 );
 
@@ -184,7 +184,7 @@ ENTRY(_cache_lock)
 
         ( R7:0,P5:0 ) = [SP++];
         RTS;
-ENDPROC(_cache_lock)
+ENDPROC(_bfin_cache_lock)
 
 /* Invalidate the Entire Instruction cache by
  * disabling IMC bit
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index e28c6af1f415..d3d70fd67c16 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -71,7 +71,7 @@ void bfin_pm_suspend_standby_enter(void)
         gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
 #endif
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         bfin_pm_standby_setup();
 
 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -82,15 +82,19 @@ void bfin_pm_suspend_standby_enter(void)
 
         bfin_pm_standby_restore();
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561) || \
+        defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-#if defined(CONFIG_BF52x)
+#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
         /* BF52x system reset does not properly reset SIC_IWR1 which
          * will screw up the bootrom as it relies on MDMA0/1 waking it
          * up from IDLE instructions.  See this report for more info:
          * http://blackfin.uclinux.org/gf/tracker/4323
          */
-        bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+        if (ANOMALY_05000435)
+                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+        else
+                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 #else
         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
 #endif
@@ -101,7 +105,7 @@ void bfin_pm_suspend_standby_enter(void)
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -245,12 +249,12 @@ int bfin_pm_suspend_mem_enter(void)
         wakeup |= GPWE;
 #endif
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
 
         ret = blackfin_dma_suspend();
 
         if (ret) {
-                local_irq_restore(flags);
+                local_irq_restore_hw(flags);
                 kfree(memptr);
                 return ret;
         }
@@ -271,7 +275,7 @@ int bfin_pm_suspend_mem_enter(void)
         bfin_gpio_pm_hibernate_restore();
         blackfin_dma_resume();
 
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
         kfree(memptr);
 
         return 0;
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
new file mode 100644
index 000000000000..77c992847094
--- /dev/null
+++ b/arch/blackfin/mach-common/smp.c
@@ -0,0 +1,476 @@
+/*
+ * File:         arch/blackfin/kernel/smp.c
+ * Author:       Philippe Gerum <rpm@xenomai.org>
+ * IPI management based on arch/arm/kernel/smp.c.
+ *
+ *               Copyright 2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/cache.h>
+#include <linux/profile.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
+#include <linux/seq_file.h>
+#include <linux/irq.h>
+#include <asm/atomic.h>
+#include <asm/cacheflush.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/cpu.h>
+#include <linux/err.h>
+
+struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
+
+void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
+        *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
+        *init_saved_dcplb_fault_addr_coreb;
+
+cpumask_t cpu_possible_map;
+EXPORT_SYMBOL(cpu_possible_map);
+
+cpumask_t cpu_online_map;
+EXPORT_SYMBOL(cpu_online_map);
+
+#define BFIN_IPI_RESCHEDULE   0
+#define BFIN_IPI_CALL_FUNC    1
+#define BFIN_IPI_CPU_STOP     2
+
+struct blackfin_flush_data {
+        unsigned long start;
+        unsigned long end;
+};
+
+void *secondary_stack;
+
+
+struct smp_call_struct {
+        void (*func)(void *info);
+        void *info;
+        int wait;
+        cpumask_t pending;
+        cpumask_t waitmask;
+};
+
+static struct blackfin_flush_data smp_flush_data;
+
+static DEFINE_SPINLOCK(stop_lock);
+
+struct ipi_message {
+        struct list_head list;
+        unsigned long type;
+        struct smp_call_struct call_struct;
+};
+
+struct ipi_message_queue {
+        struct list_head head;
+        spinlock_t lock;
+        unsigned long count;
+};
+
+static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
+
+static void ipi_cpu_stop(unsigned int cpu)
+{
+        spin_lock(&stop_lock);
+        printk(KERN_CRIT "CPU%u: stopping\n", cpu);
+        dump_stack();
+        spin_unlock(&stop_lock);
+
+        cpu_clear(cpu, cpu_online_map);
+
+        local_irq_disable();
+
+        while (1)
+                SSYNC();
+}
+
+static void ipi_flush_icache(void *info)
+{
+        struct blackfin_flush_data *fdata = info;
+
+        /* Invalidate the memory holding the bounds of the flushed region. */
+        blackfin_dcache_invalidate_range((unsigned long)fdata,
+                                         (unsigned long)fdata + sizeof(*fdata));
+
+        blackfin_icache_flush_range(fdata->start, fdata->end);
+}
+
+static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
+{
+        int wait;
+        void (*func)(void *info);
+        void *info;
+        func = msg->call_struct.func;
+        info = msg->call_struct.info;
+        wait = msg->call_struct.wait;
+        cpu_clear(cpu, msg->call_struct.pending);
+        func(info);
+        if (wait)
+                cpu_clear(cpu, msg->call_struct.waitmask);
+        else
+                kfree(msg);
+}
+
+static irqreturn_t ipi_handler(int irq, void *dev_instance)
+{
+        struct ipi_message *msg, *mg;
+        struct ipi_message_queue *msg_queue;
+        unsigned int cpu = smp_processor_id();
+
+        platform_clear_ipi(cpu);
+
+        msg_queue = &__get_cpu_var(ipi_msg_queue);
+        msg_queue->count++;
+
+        spin_lock(&msg_queue->lock);
+        list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
+                list_del(&msg->list);
+                switch (msg->type) {
+                case BFIN_IPI_RESCHEDULE:
+                        /* That's the easiest one; leave it to
+                         * return_from_int. */
+                        kfree(msg);
+                        break;
+                case BFIN_IPI_CALL_FUNC:
+                        ipi_call_function(cpu, msg);
+                        break;
+                case BFIN_IPI_CPU_STOP:
+                        ipi_cpu_stop(cpu);
+                        kfree(msg);
+                        break;
+                default:
+                        printk(KERN_CRIT "CPU%u: Unknown IPI message \
+                        0x%lx\n", cpu, msg->type);
+                        kfree(msg);
+                        break;
+                }
+        }
+        spin_unlock(&msg_queue->lock);
+        return IRQ_HANDLED;
+}
+
+static void ipi_queue_init(void)
+{
+        unsigned int cpu;
+        struct ipi_message_queue *msg_queue;
+        for_each_possible_cpu(cpu) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                INIT_LIST_HEAD(&msg_queue->head);
+                spin_lock_init(&msg_queue->lock);
+                msg_queue->count = 0;
+        }
+}
+
+int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+        unsigned int cpu;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return 0;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        INIT_LIST_HEAD(&msg->list);
+        msg->call_struct.func = func;
+        msg->call_struct.info = info;
+        msg->call_struct.wait = wait;
+        msg->call_struct.pending = callmap;
+        msg->call_struct.waitmask = callmap;
+        msg->type = BFIN_IPI_CALL_FUNC;
+
+        for_each_cpu_mask(cpu, callmap) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                spin_lock_irqsave(&msg_queue->lock, flags);
+                list_add(&msg->list, &msg_queue->head);
+                spin_unlock_irqrestore(&msg_queue->lock, flags);
+                platform_send_ipi_cpu(cpu);
+        }
+        if (wait) {
+                while (!cpus_empty(msg->call_struct.waitmask))
+                        blackfin_dcache_invalidate_range(
+                                (unsigned long)(&msg->call_struct.waitmask),
+                                (unsigned long)(&msg->call_struct.waitmask));
+                kfree(msg);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(smp_call_function);
+
+int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
+                                int wait)
+{
+        unsigned int cpu = cpuid;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        if (cpu_is_offline(cpu))
+                return 0;
+        cpus_clear(callmap);
+        cpu_set(cpu, callmap);
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        INIT_LIST_HEAD(&msg->list);
+        msg->call_struct.func = func;
+        msg->call_struct.info = info;
+        msg->call_struct.wait = wait;
+        msg->call_struct.pending = callmap;
+        msg->call_struct.waitmask = callmap;
+        msg->type = BFIN_IPI_CALL_FUNC;
+
+        msg_queue = &per_cpu(ipi_msg_queue, cpu);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+        list_add(&msg->list, &msg_queue->head);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
+        platform_send_ipi_cpu(cpu);
+
+        if (wait) {
+                while (!cpus_empty(msg->call_struct.waitmask))
+                        blackfin_dcache_invalidate_range(
+                                (unsigned long)(&msg->call_struct.waitmask),
+                                (unsigned long)(&msg->call_struct.waitmask));
+                kfree(msg);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(smp_call_function_single);
+
+void smp_send_reschedule(int cpu)
+{
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        if (cpu_is_offline(cpu))
+                return;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        memset(msg, 0, sizeof(msg));
+        INIT_LIST_HEAD(&msg->list);
+        msg->type = BFIN_IPI_RESCHEDULE;
+
+        msg_queue = &per_cpu(ipi_msg_queue, cpu);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+        list_add(&msg->list, &msg_queue->head);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
+        platform_send_ipi_cpu(cpu);
+
+        return;
+}
+
+void smp_send_stop(void)
+{
+        unsigned int cpu;
+        cpumask_t callmap;
+        unsigned long flags;
+        struct ipi_message_queue *msg_queue;
+        struct ipi_message *msg;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return;
+
+        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
+        memset(msg, 0, sizeof(msg));
+        INIT_LIST_HEAD(&msg->list);
+        msg->type = BFIN_IPI_CPU_STOP;
+
+        for_each_cpu_mask(cpu, callmap) {
+                msg_queue = &per_cpu(ipi_msg_queue, cpu);
+                spin_lock_irqsave(&msg_queue->lock, flags);
+                list_add(&msg->list, &msg_queue->head);
+                spin_unlock_irqrestore(&msg_queue->lock, flags);
+                platform_send_ipi_cpu(cpu);
+        }
+        return;
+}
+
+int __cpuinit __cpu_up(unsigned int cpu)
+{
+        struct task_struct *idle;
+        int ret;
+
+        idle = fork_idle(cpu);
+        if (IS_ERR(idle)) {
+                printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
+                return PTR_ERR(idle);
+        }
+
+        secondary_stack = task_stack_page(idle) + THREAD_SIZE;
+        smp_wmb();
+
+        ret = platform_boot_secondary(cpu, idle);
+
+        if (ret) {
+                cpu_clear(cpu, cpu_present_map);
+                printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
+                free_task(idle);
+        } else
+                cpu_set(cpu, cpu_online_map);
+
+        secondary_stack = NULL;
+
+        return ret;
+}
+
+static void __cpuinit setup_secondary(unsigned int cpu)
+{
+#if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE))
+        struct irq_desc *timer_desc;
+#endif
+        unsigned long ilat;
+
+        bfin_write_IMASK(0);
+        CSYNC();
+        ilat = bfin_read_ILAT();
+        CSYNC();
+        bfin_write_ILAT(ilat);
+        CSYNC();
+
+        /* Reserve the PDA space for the secondary CPU. */
+        reserve_pda();
+
+        /* Enable interrupt levels IVG7-15. IARs have been already
+         * programmed by the boot CPU.  */
+        bfin_irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+
+#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
+        /* Power down the core timer, just to play safe. */
+        bfin_write_TCNTL(0);
+
+        /* system timer0 has been setup by CoreA. */
+#else
+        timer_desc = irq_desc + IRQ_CORETMR;
+        setup_core_timer();
+        timer_desc->chip->enable(IRQ_CORETMR);
+#endif
+}
+
+void __cpuinit secondary_start_kernel(void)
+{
+        unsigned int cpu = smp_processor_id();
+        struct mm_struct *mm = &init_mm;
+
+        if (_bfin_swrst & SWRST_DBL_FAULT_B) {
+                printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
+#ifdef CONFIG_DEBUG_DOUBLEFAULT
+                printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
+                        (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
+                printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
+                printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
+#endif
+                printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
+                        init_retx_coreb);
+        }
+
+        /*
+         * We want the D-cache to be enabled early, in case the atomic
+         * support code emulates cache coherence (see
+         * __ARCH_SYNC_CORE_DCACHE).
+         */
+        init_exception_vectors();
+
+        bfin_setup_caches(cpu);
+
+        local_irq_disable();
+
+        /* Attach the new idle task to the global mm. */
+        atomic_inc(&mm->mm_users);
+        atomic_inc(&mm->mm_count);
+        current->active_mm = mm;
+        BUG_ON(current->mm);    /* Can't be, but better be safe than sorry. */
+
+        preempt_disable();
+
+        setup_secondary(cpu);
+
+        local_irq_enable();
+
+        platform_secondary_init(cpu);
+
+        cpu_idle();
+}
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        platform_prepare_cpus(max_cpus);
+        ipi_queue_init();
+        platform_request_ipi(&ipi_handler);
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+        unsigned long bogosum = 0;
+        unsigned int cpu;
+
+        for_each_online_cpu(cpu)
+                bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
+
+        printk(KERN_INFO "SMP: Total of %d processors activated "
+               "(%lu.%02lu BogoMIPS).\n",
+               num_online_cpus(),
+               bogosum / (500000/HZ),
+               (bogosum / (5000/HZ)) % 100);
+}
+
+void smp_icache_flush_range_others(unsigned long start, unsigned long end)
+{
+        smp_flush_data.start = start;
+        smp_flush_data.end = end;
+
+        if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
+                printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
+}
+EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
+
+#ifdef __ARCH_SYNC_CORE_DCACHE
+unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
+
+void resync_core_dcache(void)
+{
+        unsigned int cpu = get_cpu();
+        blackfin_invalidate_entire_dcache();
+        ++per_cpu(cpu_data, cpu).dcache_invld_count;
+        put_cpu();
+}
+EXPORT_SYMBOL(resync_core_dcache);
+#endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index bc240abb8745..d0532b72bba5 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -31,7 +31,8 @@
 #include <linux/bootmem.h>
 #include <linux/uaccess.h>
 #include <asm/bfin-global.h>
-#include <asm/l1layout.h>
+#include <asm/pda.h>
+#include <asm/cplbinit.h>
 #include "blackfin_sram.h"
 
 /*
@@ -53,6 +54,11 @@ static unsigned long empty_bad_page;
 
 unsigned long empty_zero_page;
 
+extern unsigned long exception_stack[NR_CPUS][1024];
+
+struct blackfin_pda cpu_pda[NR_CPUS];
+EXPORT_SYMBOL(cpu_pda);
+
 /*
  * paging_init() continues the virtual memory environment setup which
  * was begun by the code in arch/head.S.
@@ -98,6 +104,32 @@ void __init paging_init(void)
         }
 }
 
+asmlinkage void init_pda(void)
+{
+        unsigned int cpu = raw_smp_processor_id();
+
+        /* Initialize the PDA fields holding references to other parts
+           of the memory. The content of such memory is still
+           undefined at the time of the call, we are only setting up
+           valid pointers to it. */
+        memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
+
+        cpu_pda[0].next = &cpu_pda[1];
+        cpu_pda[1].next = &cpu_pda[0];
+
+        cpu_pda[cpu].ex_stack = exception_stack[cpu + 1];
+
+#ifdef CONFIG_SMP
+        cpu_pda[cpu].imask = 0x1f;
+#endif
+}
+
+void __cpuinit reserve_pda(void)
+{
+        printk(KERN_INFO "PDA for CPU%u reserved at %p\n", smp_processor_id(),
+                                        &cpu_pda[smp_processor_id()]);
+}
+
 void __init mem_init(void)
 {
         unsigned int codek = 0, datak = 0, initk = 0;
@@ -141,21 +173,13 @@ void __init mem_init(void)
 
 static int __init sram_init(void)
 {
-        unsigned long tmp;
-
         /* Initialize the blackfin L1 Memory. */
         bfin_sram_init();
 
-        /* Allocate this once; never free it.  We assume this gives us a
-           pointer to the start of L1 scratchpad memory; panic if it
-           doesn't.  */
-        tmp = (unsigned long)l1sram_alloc(sizeof(struct l1_scratch_task_info));
-        if (tmp != (unsigned long)L1_SCRATCH_TASK_INFO) {
-                printk(KERN_EMERG "mem_init(): Did not get the right address from l1sram_alloc: %08lx != %08lx\n",
-                        tmp, (unsigned long)L1_SCRATCH_TASK_INFO);
-                panic("No L1, time to give up\n");
-        }
-
+        /* Reserve the PDA space for the boot CPU right after we
+         * initialized the scratch memory allocator.
+         */
+        reserve_pda();
         return 0;
 }
 pure_initcall(sram_init);
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index cc6f336e7313..834cab7438a8 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -39,10 +39,13 @@
 #include <linux/spinlock.h>
 #include <linux/rtc.h>
 #include <asm/blackfin.h>
+#include <asm/mem_map.h>
 #include "blackfin_sram.h"
 
-static spinlock_t l1sram_lock, l1_data_sram_lock, l1_inst_sram_lock;
-static spinlock_t l2_sram_lock;
+static DEFINE_PER_CPU(spinlock_t, l1sram_lock) ____cacheline_aligned_in_smp;
+static DEFINE_PER_CPU(spinlock_t, l1_data_sram_lock) ____cacheline_aligned_in_smp;
+static DEFINE_PER_CPU(spinlock_t, l1_inst_sram_lock) ____cacheline_aligned_in_smp;
+static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp;
 
 /* the data structure for L1 scratchpad and DATA SRAM */
 struct sram_piece {
@@ -52,18 +55,22 @@ struct sram_piece {
         struct sram_piece *next;
 };
 
-static struct sram_piece free_l1_ssram_head, used_l1_ssram_head;
+static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head);
+static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head);
 
 #if L1_DATA_A_LENGTH != 0
-static struct sram_piece free_l1_data_A_sram_head, used_l1_data_A_sram_head;
+static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head);
+static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head);
 #endif
 
 #if L1_DATA_B_LENGTH != 0
-static struct sram_piece free_l1_data_B_sram_head, used_l1_data_B_sram_head;
+static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head);
+static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head);
 #endif
 
 #if L1_CODE_LENGTH != 0
-static struct sram_piece free_l1_inst_sram_head, used_l1_inst_sram_head;
+static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head);
+static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head);
 #endif
 
 #if L2_LENGTH != 0
@@ -75,102 +82,117 @@ static struct kmem_cache *sram_piece_cache;
 /* L1 Scratchpad SRAM initialization function */
 static void __init l1sram_init(void)
 {
-        free_l1_ssram_head.next =
-                kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
-        if (!free_l1_ssram_head.next) {
-                printk(KERN_INFO "Failed to initialize Scratchpad data SRAM\n");
-                return;
+        unsigned int cpu;
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
+                per_cpu(free_l1_ssram_head, cpu).next =
+                        kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
+                if (!per_cpu(free_l1_ssram_head, cpu).next) {
+                        printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n");
+                        return;
+                }
+
+                per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu);
+                per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH;
+                per_cpu(free_l1_ssram_head, cpu).next->pid = 0;
+                per_cpu(free_l1_ssram_head, cpu).next->next = NULL;
+
+                per_cpu(used_l1_ssram_head, cpu).next = NULL;
+
+                /* mutex initialize */
+                spin_lock_init(&per_cpu(l1sram_lock, cpu));
+                printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
+                        L1_SCRATCH_LENGTH >> 10);
         }
-
-        free_l1_ssram_head.next->paddr = (void *)L1_SCRATCH_START;
-        free_l1_ssram_head.next->size = L1_SCRATCH_LENGTH;
-        free_l1_ssram_head.next->pid = 0;
-        free_l1_ssram_head.next->next = NULL;
-
-        used_l1_ssram_head.next = NULL;
-
-        /* mutex initialize */
-        spin_lock_init(&l1sram_lock);
-
-        printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
-               L1_SCRATCH_LENGTH >> 10);
 }
 
 static void __init l1_data_sram_init(void)
 {
+#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
+        unsigned int cpu;
+#endif
 #if L1_DATA_A_LENGTH != 0
-        free_l1_data_A_sram_head.next =
-                kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
-        if (!free_l1_data_A_sram_head.next) {
-                printk(KERN_INFO "Failed to initialize L1 Data A SRAM\n");
-                return;
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
+                per_cpu(free_l1_data_A_sram_head, cpu).next =
+                        kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
+                if (!per_cpu(free_l1_data_A_sram_head, cpu).next) {
+                        printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n");
+                        return;
+                }
+
+                per_cpu(free_l1_data_A_sram_head, cpu).next->paddr =
+                        (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1);
+                per_cpu(free_l1_data_A_sram_head, cpu).next->size =
+                        L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
+                per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0;
+                per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL;
+
+                per_cpu(used_l1_data_A_sram_head, cpu).next = NULL;
+
+                printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
+                        L1_DATA_A_LENGTH >> 10,
+                        per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10);
         }
-
-        free_l1_data_A_sram_head.next->paddr =
-                (void *)L1_DATA_A_START + (_ebss_l1 - _sdata_l1);
-        free_l1_data_A_sram_head.next->size =
-                L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
-        free_l1_data_A_sram_head.next->pid = 0;
-        free_l1_data_A_sram_head.next->next = NULL;
-
-        used_l1_data_A_sram_head.next = NULL;
-
-        printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
-                L1_DATA_A_LENGTH >> 10,
-                free_l1_data_A_sram_head.next->size >> 10);
 #endif
 #if L1_DATA_B_LENGTH != 0
-        free_l1_data_B_sram_head.next =
-                kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
-        if (!free_l1_data_B_sram_head.next) {
-                printk(KERN_INFO "Failed to initialize L1 Data B SRAM\n");
-                return;
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
+                per_cpu(free_l1_data_B_sram_head, cpu).next =
+                        kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
+                if (!per_cpu(free_l1_data_B_sram_head, cpu).next) {
+                        printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n");
+                        return;
+                }
+
+                per_cpu(free_l1_data_B_sram_head, cpu).next->paddr =
+                        (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1);
+                per_cpu(free_l1_data_B_sram_head, cpu).next->size =
+                        L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
+                per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0;
+                per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL;
+
+                per_cpu(used_l1_data_B_sram_head, cpu).next = NULL;
+
+                printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
+                        L1_DATA_B_LENGTH >> 10,
+                        per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10);
+                /* mutex initialize */
         }
-
-        free_l1_data_B_sram_head.next->paddr =
-                (void *)L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1);
-        free_l1_data_B_sram_head.next->size =
-                L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
-        free_l1_data_B_sram_head.next->pid = 0;
-        free_l1_data_B_sram_head.next->next = NULL;
-
-        used_l1_data_B_sram_head.next = NULL;
-
-        printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
-                L1_DATA_B_LENGTH >> 10,
-                free_l1_data_B_sram_head.next->size >> 10);
 #endif
 
-        /* mutex initialize */
-        spin_lock_init(&l1_data_sram_lock);
+#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
+                spin_lock_init(&per_cpu(l1_data_sram_lock, cpu));
+#endif
 }
 
 static void __init l1_inst_sram_init(void)
 {
 #if L1_CODE_LENGTH != 0
-        free_l1_inst_sram_head.next =
-                kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
-        if (!free_l1_inst_sram_head.next) {
-                printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
-                return;
+        unsigned int cpu;
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
+                per_cpu(free_l1_inst_sram_head, cpu).next =
+                        kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
+                if (!per_cpu(free_l1_inst_sram_head, cpu).next) {
+                        printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
+                        return;
+                }
+
+                per_cpu(free_l1_inst_sram_head, cpu).next->paddr =
+                        (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1);
+                per_cpu(free_l1_inst_sram_head, cpu).next->size =
+                        L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
+                per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0;
+                per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL;
+
+                per_cpu(used_l1_inst_sram_head, cpu).next = NULL;
+
+                printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
+                        L1_CODE_LENGTH >> 10,
+                        per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10);
+
+                /* mutex initialize */
+                spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu));
         }
-
-        free_l1_inst_sram_head.next->paddr =
-                (void *)L1_CODE_START + (_etext_l1 - _stext_l1);
-        free_l1_inst_sram_head.next->size =
-                L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
-        free_l1_inst_sram_head.next->pid = 0;
-        free_l1_inst_sram_head.next->next = NULL;
-
-        used_l1_inst_sram_head.next = NULL;
-
-        printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
-                L1_CODE_LENGTH >> 10,
-                free_l1_inst_sram_head.next->size >> 10);
 #endif
-
-        /* mutex initialize */
-        spin_lock_init(&l1_inst_sram_lock);
 }
 
 static void __init l2_sram_init(void)
@@ -179,7 +201,7 @@ static void __init l2_sram_init(void)
         free_l2_sram_head.next =
                 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
         if (!free_l2_sram_head.next) {
-                printk(KERN_INFO "Failed to initialize L2 SRAM\n");
+                printk(KERN_INFO "Fail to initialize L2 SRAM.\n");
                 return;
         }
 
@@ -200,6 +222,7 @@ static void __init l2_sram_init(void)
         /* mutex initialize */
         spin_lock_init(&l2_sram_lock);
 }
+
 void __init bfin_sram_init(void)
 {
         sram_piece_cache = kmem_cache_create("sram_piece_cache",
@@ -353,20 +376,20 @@ int sram_free(const void *addr)
 {
 
 #if L1_CODE_LENGTH != 0
-        if (addr >= (void *)L1_CODE_START
-                 && addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
+        if (addr >= (void *)get_l1_code_start()
+                 && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH))
                 return l1_inst_sram_free(addr);
         else
 #endif
 #if L1_DATA_A_LENGTH != 0
-        if (addr >= (void *)L1_DATA_A_START
-                 && addr < (void *)(L1_DATA_A_START + L1_DATA_A_LENGTH))
+        if (addr >= (void *)get_l1_data_a_start()
+                 && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH))
                 return l1_data_A_sram_free(addr);
         else
 #endif
 #if L1_DATA_B_LENGTH != 0
-        if (addr >= (void *)L1_DATA_B_START
-                 && addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH))
+        if (addr >= (void *)get_l1_data_b_start()
+                 && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH))
                 return l1_data_B_sram_free(addr);
         else
 #endif
@@ -384,17 +407,20 @@ void *l1_data_A_sram_alloc(size_t size)
 {
         unsigned long flags;
         void *addr = NULL;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_data_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
 
 #if L1_DATA_A_LENGTH != 0
-        addr = _sram_alloc(size, &free_l1_data_A_sram_head,
-                        &used_l1_data_A_sram_head);
+        addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu),
+                        &per_cpu(used_l1_data_A_sram_head, cpu));
 #endif
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_data_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
+        put_cpu();
 
         pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n",
                  (long unsigned int)addr, size);
@@ -407,19 +433,22 @@ int l1_data_A_sram_free(const void *addr)
 {
         unsigned long flags;
         int ret;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_data_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
 
 #if L1_DATA_A_LENGTH != 0
-        ret = _sram_free(addr, &free_l1_data_A_sram_head,
-                        &used_l1_data_A_sram_head);
+        ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu),
+                        &per_cpu(used_l1_data_A_sram_head, cpu));
 #else
         ret = -1;
 #endif
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_data_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
+        put_cpu();
 
         return ret;
 }
@@ -430,15 +459,18 @@ void *l1_data_B_sram_alloc(size_t size)
 #if L1_DATA_B_LENGTH != 0
         unsigned long flags;
         void *addr;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_data_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
 
-        addr = _sram_alloc(size, &free_l1_data_B_sram_head,
-                        &used_l1_data_B_sram_head);
+        addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu),
+                        &per_cpu(used_l1_data_B_sram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_data_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
+        put_cpu();
 
         pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n",
                  (long unsigned int)addr, size);
@@ -455,15 +487,18 @@ int l1_data_B_sram_free(const void *addr)
 #if L1_DATA_B_LENGTH != 0
         unsigned long flags;
         int ret;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_data_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
 
-        ret = _sram_free(addr, &free_l1_data_B_sram_head,
-                        &used_l1_data_B_sram_head);
+        ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu),
+                        &per_cpu(used_l1_data_B_sram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_data_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
+        put_cpu();
 
         return ret;
 #else
@@ -509,15 +544,18 @@ void *l1_inst_sram_alloc(size_t size)
 #if L1_CODE_LENGTH != 0
         unsigned long flags;
         void *addr;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_inst_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
 
-        addr = _sram_alloc(size, &free_l1_inst_sram_head,
-                        &used_l1_inst_sram_head);
+        addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu),
+                        &per_cpu(used_l1_inst_sram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_inst_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
+        put_cpu();
 
         pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n",
                  (long unsigned int)addr, size);
@@ -534,15 +572,18 @@ int l1_inst_sram_free(const void *addr)
 #if L1_CODE_LENGTH != 0
         unsigned long flags;
         int ret;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1_inst_sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
 
-        ret = _sram_free(addr, &free_l1_inst_sram_head,
-                        &used_l1_inst_sram_head);
+        ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu),
+                        &per_cpu(used_l1_inst_sram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1_inst_sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
+        put_cpu();
 
         return ret;
 #else
@@ -556,15 +597,18 @@ void *l1sram_alloc(size_t size)
 {
         unsigned long flags;
         void *addr;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
 
-        addr = _sram_alloc(size, &free_l1_ssram_head,
-                        &used_l1_ssram_head);
+        addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu),
+                        &per_cpu(used_l1_ssram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
+        put_cpu();
 
         return addr;
 }
@@ -574,15 +618,18 @@ void *l1sram_alloc_max(size_t *psize)
 {
         unsigned long flags;
         void *addr;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
 
-        addr = _sram_alloc_max(&free_l1_ssram_head,
-                        &used_l1_ssram_head, psize);
+        addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu),
+                        &per_cpu(used_l1_ssram_head, cpu), psize);
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
+        put_cpu();
 
         return addr;
 }
@@ -592,15 +639,18 @@ int l1sram_free(const void *addr)
 {
         unsigned long flags;
         int ret;
+        unsigned int cpu;
 
+        cpu = get_cpu();
         /* add mutex operation */
-        spin_lock_irqsave(&l1sram_lock, flags);
+        spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
 
-        ret = _sram_free(addr, &free_l1_ssram_head,
-                        &used_l1_ssram_head);
+        ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu),
+                        &per_cpu(used_l1_ssram_head, cpu));
 
         /* add mutex operation */
-        spin_unlock_irqrestore(&l1sram_lock, flags);
+        spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
+        put_cpu();
 
         return ret;
 }
@@ -761,33 +811,36 @@ static int sram_proc_read(char *buf, char **start, off_t offset, int count,
                 int *eof, void *data)
 {
         int len = 0;
+        unsigned int cpu;
 
-        if (_sram_proc_read(buf, &len, count, "Scratchpad",
-                        &free_l1_ssram_head, &used_l1_ssram_head))
-                goto not_done;
+        for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
+                if (_sram_proc_read(buf, &len, count, "Scratchpad",
+                        &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
+                        goto not_done;
 #if L1_DATA_A_LENGTH != 0
-        if (_sram_proc_read(buf, &len, count, "L1 Data A",
-                        &free_l1_data_A_sram_head,
-                        &used_l1_data_A_sram_head))
-                goto not_done;
+                if (_sram_proc_read(buf, &len, count, "L1 Data A",
+                        &per_cpu(free_l1_data_A_sram_head, cpu),
+                        &per_cpu(used_l1_data_A_sram_head, cpu)))
+                        goto not_done;
 #endif
 #if L1_DATA_B_LENGTH != 0
-        if (_sram_proc_read(buf, &len, count, "L1 Data B",
-                        &free_l1_data_B_sram_head,
-                        &used_l1_data_B_sram_head))
-                goto not_done;
+                if (_sram_proc_read(buf, &len, count, "L1 Data B",
+                        &per_cpu(free_l1_data_B_sram_head, cpu),
+                        &per_cpu(used_l1_data_B_sram_head, cpu)))
+                        goto not_done;
 #endif
 #if L1_CODE_LENGTH != 0
-        if (_sram_proc_read(buf, &len, count, "L1 Instruction",
-                        &free_l1_inst_sram_head, &used_l1_inst_sram_head))
-                goto not_done;
+                if (_sram_proc_read(buf, &len, count, "L1 Instruction",
+                        &per_cpu(free_l1_inst_sram_head, cpu),
+                        &per_cpu(used_l1_inst_sram_head, cpu)))
+                        goto not_done;
 #endif
+        }
 #if L2_LENGTH != 0
-        if (_sram_proc_read(buf, &len, count, "L2",
-                        &free_l2_sram_head, &used_l2_sram_head))
+        if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head,
+                &used_l2_sram_head))
                 goto not_done;
 #endif
-
         *eof = 1;
  not_done:
         return len;
diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile
index 634e300d67e2..c70af3a01297 100644
--- a/arch/blackfin/oprofile/Makefile
+++ b/arch/blackfin/oprofile/Makefile
@@ -10,5 +10,4 @@ DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
                 oprofilefs.o oprofile_stats.o \
                 timer_int.o )
 
-oprofile-y := $(DRIVER_OBJS) common.o
-oprofile-$(CONFIG_HARDWARE_PM) += op_model_bf533.o
+oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o
diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c
new file mode 100644
index 000000000000..c3b9713b23f8
--- /dev/null
+++ b/arch/blackfin/oprofile/bfin_oprofile.c
@@ -0,0 +1,18 @@
+/*
+ * bfin_oprofile.c - Blackfin oprofile code
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/oprofile.h>
+#include <linux/init.h>
+
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+        return -1;
+}
+
+void oprofile_arch_exit(void)
+{
+}
diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c
deleted file mode 100644
index 0f6d303a8891..000000000000
--- a/arch/blackfin/oprofile/common.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * File:         arch/blackfin/oprofile/common.c
- * Based on:     arch/alpha/oprofile/common.c
- * Author:       Anton Blanchard <anton@au.ibm.com>
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/mutex.h>
-#include <linux/ptrace.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/blackfin.h>
-
-#include "op_blackfin.h"
-
-#define BFIN_533_ID  0xE5040003
-#define BFIN_537_ID  0xE5040002
-
-static int pfmon_enabled;
-static struct mutex pfmon_lock;
-
-struct op_bfin533_model *model;
-
-struct op_counter_config ctr[OP_MAX_COUNTER];
-
-static int op_bfin_setup(void)
-{
-        int ret;
-
-        /* Pre-compute the values to stuff in the hardware registers.  */
-        spin_lock(&oprofilefs_lock);
-        ret = model->reg_setup(ctr);
-        spin_unlock(&oprofilefs_lock);
-
-        return ret;
-}
-
-static void op_bfin_shutdown(void)
-{
-#if 0
-        /* what is the difference between shutdown and stop? */
-#endif
-}
-
-static int op_bfin_start(void)
-{
-        int ret = -EBUSY;
-
-        printk(KERN_INFO "KSDBG:in %s\n", __func__);
-        mutex_lock(&pfmon_lock);
-        if (!pfmon_enabled) {
-                ret = model->start(ctr);
-                pfmon_enabled = !ret;
-        }
-        mutex_unlock(&pfmon_lock);
-
-        return ret;
-}
-
-static void op_bfin_stop(void)
-{
-        mutex_lock(&pfmon_lock);
-        if (pfmon_enabled) {
-                model->stop();
-                pfmon_enabled = 0;
-        }
-        mutex_unlock(&pfmon_lock);
-}
-
-static int op_bfin_create_files(struct super_block *sb, struct dentry *root)
-{
-        int i;
-
-        for (i = 0; i < model->num_counters; ++i) {
-                struct dentry *dir;
-                char buf[3];
-                printk(KERN_INFO "Oprofile: creating files... \n");
-
-                snprintf(buf, sizeof buf, "%d", i);
-                dir = oprofilefs_mkdir(sb, root, buf);
-
-                oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
-                oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
-                oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
-                /*
-                 * We dont support per counter user/kernel selection, but
-                 * we leave the entries because userspace expects them
-                 */
-                oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
-                oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
-                oprofilefs_create_ulong(sb, dir, "unit_mask",
-                                        &ctr[i].unit_mask);
-        }
-
-        return 0;
-}
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
-#ifdef CONFIG_HARDWARE_PM
-        unsigned int dspid;
-
-        mutex_init(&pfmon_lock);
-
-        dspid = bfin_read_DSPID();
-
-        printk(KERN_INFO "Oprofile got the cpu id is 0x%x. \n", dspid);
-
-        switch (dspid) {
-        case BFIN_533_ID:
-                model = &op_model_bfin533;
-                model->num_counters = 2;
-                break;
-        case BFIN_537_ID:
-                model = &op_model_bfin533;
-                model->num_counters = 2;
-                break;
-        default:
-                return -ENODEV;
-        }
-
-        ops->cpu_type = model->name;
-        ops->create_files = op_bfin_create_files;
-        ops->setup = op_bfin_setup;
-        ops->shutdown = op_bfin_shutdown;
-        ops->start = op_bfin_start;
-        ops->stop = op_bfin_stop;
-
-        printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
-               ops->cpu_type);
-
-        return 0;
-#else
-        return -1;
-#endif
-}
-
-void oprofile_arch_exit(void)
-{
-}
diff --git a/arch/blackfin/oprofile/op_blackfin.h b/arch/blackfin/oprofile/op_blackfin.h
deleted file mode 100644
index 05dd08c9d154..000000000000
--- a/arch/blackfin/oprofile/op_blackfin.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * File:         arch/blackfin/oprofile/op_blackfin.h
- * Based on:
- * Author:       Anton Blanchard <anton@au.ibm.com>
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef OP_BLACKFIN_H
-#define OP_BLACKFIN_H 1
-
-#define OP_MAX_COUNTER 2
-
-#include <asm/blackfin.h>
-
-/* Per-counter configuration as set via oprofilefs.  */
-struct op_counter_config {
-        unsigned long valid;
-        unsigned long enabled;
-        unsigned long event;
-        unsigned long count;
-        unsigned long kernel;
-        unsigned long user;
-        unsigned long unit_mask;
-};
-
-/* System-wide configuration as set via oprofilefs.  */
-struct op_system_config {
-        unsigned long enable_kernel;
-        unsigned long enable_user;
-};
-
-/* Per-arch configuration */
-struct op_bfin533_model {
-        int (*reg_setup) (struct op_counter_config *);
-        int (*start) (struct op_counter_config *);
-        void (*stop) (void);
-        int num_counters;
-        char *name;
-};
-
-extern struct op_bfin533_model op_model_bfin533;
-
-static inline unsigned int ctr_read(void)
-{
-        unsigned int tmp;
-
-        tmp = bfin_read_PFCTL();
-        CSYNC();
-
-        return tmp;
-}
-
-static inline void ctr_write(unsigned int val)
-{
-        bfin_write_PFCTL(val);
-        CSYNC();
-}
-
-static inline void count_read(unsigned int *count)
-{
-        count[0] = bfin_read_PFCNTR0();
-        count[1] = bfin_read_PFCNTR1();
-        CSYNC();
-}
-
-static inline void count_write(unsigned int *count)
-{
-        bfin_write_PFCNTR0(count[0]);
-        bfin_write_PFCNTR1(count[1]);
-        CSYNC();
-}
-
-extern int pm_overflow_handler(int irq, struct pt_regs *regs);
-
-#endif
diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c
deleted file mode 100644
index d1c698bb9ee5..000000000000
--- a/arch/blackfin/oprofile/op_model_bf533.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * File:         arch/blackfin/oprofile/op_model_bf533.c
- * Based on:
- * Author:       Anton Blanchard <anton@au.ibm.com>
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/ptrace.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm/blackfin.h>
-
-#include "op_blackfin.h"
-
-#define PM_ENABLE 0x01;
-#define PM_CTL1_ENABLE  0x18
-#define PM_CTL0_ENABLE  0xC000
-#define COUNT_EDGE_ONLY 0x3000000
-
-static int oprofile_running;
-
-static unsigned curr_pfctl, curr_count[2];
-
-static int bfin533_reg_setup(struct op_counter_config *ctr)
-{
-        unsigned int pfctl = ctr_read();
-        unsigned int count[2];
-
-        /* set Blackfin perf monitor regs with ctr */
-        if (ctr[0].enabled) {
-                pfctl |= (PM_CTL0_ENABLE | ((char)ctr[0].event << 5));
-                count[0] = 0xFFFFFFFF - ctr[0].count;
-                curr_count[0] = count[0];
-        }
-        if (ctr[1].enabled) {
-                pfctl |= (PM_CTL1_ENABLE | ((char)ctr[1].event << 16));
-                count[1] = 0xFFFFFFFF - ctr[1].count;
-                curr_count[1] = count[1];
-        }
-
-        pr_debug("ctr[0].enabled=%d,ctr[1].enabled=%d,ctr[0].event<<5=0x%x,ctr[1].event<<16=0x%x\n", ctr[0].enabled, ctr[1].enabled, ctr[0].event << 5, ctr[1].event << 16);
-        pfctl |= COUNT_EDGE_ONLY;
-        curr_pfctl = pfctl;
-
-        pr_debug("write 0x%x to pfctl\n", pfctl);
-        ctr_write(pfctl);
-        count_write(count);
-
-        return 0;
-}
-
-static int bfin533_start(struct op_counter_config *ctr)
-{
-        unsigned int pfctl = ctr_read();
-
-        pfctl |= PM_ENABLE;
-        curr_pfctl = pfctl;
-
-        ctr_write(pfctl);
-
-        oprofile_running = 1;
-        pr_debug("start oprofile counter \n");
-
-        return 0;
-}
-
-static void bfin533_stop(void)
-{
-        int pfctl;
-
-        pfctl = ctr_read();
-        pfctl &= ~PM_ENABLE;
-        /* freeze counters */
-        ctr_write(pfctl);
-
-        oprofile_running = 0;
-        pr_debug("stop oprofile counter \n");
-}
-
-static int get_kernel(void)
-{
-        int ipend, is_kernel;
-
-        ipend = bfin_read_IPEND();
-
-        /* test bit 15 */
-        is_kernel = ((ipend & 0x8000) != 0);
-
-        return is_kernel;
-}
-
-int pm_overflow_handler(int irq, struct pt_regs *regs)
-{
-        int is_kernel;
-        int i, cpu;
-        unsigned int pc, pfctl;
-        unsigned int count[2];
-
-        pr_debug("get interrupt in %s\n", __func__);
-        if (oprofile_running == 0) {
-                pr_debug("error: entering interrupt when oprofile is stopped.\n\r");
-                return -1;
-        }
-
-        is_kernel = get_kernel();
-        cpu = smp_processor_id();
-        pc = regs->pc;
-        pfctl = ctr_read();
-
-        /* read the two event counter regs */
-        count_read(count);
-
-        /* if the counter overflows, add sample to oprofile buffer */
-        for (i = 0; i < 2; ++i) {
-                if (oprofile_running) {
-                        oprofile_add_sample(regs, i);
-                }
-        }
-
-        /* reset the perfmon counter */
-        ctr_write(curr_pfctl);
-        count_write(curr_count);
-        return 0;
-}
-
-struct op_bfin533_model op_model_bfin533 = {
-        .reg_setup = bfin533_reg_setup,
-        .start = bfin533_start,
-        .stop = bfin533_stop,
-        .num_counters = 2,
-        .name = "blackfin/bf533"
-};
diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c
deleted file mode 100644
index 6c6f8606af4c..000000000000
--- a/arch/blackfin/oprofile/timer_int.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * File:         arch/blackfin/oprofile/timer_int.c
- * Based on:
- * Author:       Michael Kang
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/irq.h>
-#include <linux/oprofile.h>
-#include <linux/ptrace.h>
-
-static void enable_sys_timer0()
-{
-}
-static void disable_sys_timer0()
-{
-}
-
-static irqreturn_t sys_timer0_int_handler(int irq, void *dev_id,
-                                          struct pt_regs *regs)
-{
-        oprofile_add_sample(regs, 0);
-        return IRQ_HANDLED;
-}
-
-static int sys_timer0_start(void)
-{
-        enable_sys_timer0();
-        return request_irq(IVG11, sys_timer0_int_handler, 0, "sys_timer0", NULL);
-}
-
-static void sys_timer0_stop(void)
-{
-        disable_sys_timer();
-}
-
-int __init sys_timer0_init(struct oprofile_operations *ops)
-{
-        extern int nmi_active;
-
-        if (nmi_active <= 0)
-                return -ENODEV;
-
-        ops->start = timer_start;
-        ops->stop = timer_stop;
-        ops->cpu_type = "timer";
-        printk(KERN_INFO "oprofile: using NMI timer interrupt.\n");
-        return 0;
-}
diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c
index da7d2be000ba..372d0ca6efbc 100644
--- a/arch/cris/arch-v32/kernel/signal.c
+++ b/arch/cris/arch-v32/kernel/signal.c
@@ -456,7 +456,7 @@ give_sigsegv:
         return -EFAULT;
 }
 
-/* Invoke a singal handler to, well, handle the signal. */
+/* Invoke a signal handler to, well, handle the signal. */
 static inline int
 handle_signal(int canrestart, unsigned long sig,
               siginfo_t *info, struct k_sigaction *ka,
diff --git a/arch/ia64/kernel/kprobes.c b/arch/ia64/kernel/kprobes.c
index 097b84d54e73..f90be51b1123 100644
--- a/arch/ia64/kernel/kprobes.c
+++ b/arch/ia64/kernel/kprobes.c
@@ -434,7 +434,7 @@ int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs)
         /*
          * It is possible to have multiple instances associated with a given
          * task either because an multiple functions in the call path
-         * have a return probe installed on them, and/or more then one return
+         * have a return probe installed on them, and/or more than one return
          * return probe was registered for a target function.
          *
          * We can handle this because:
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index c825bde17cb3..fb87c08c6b57 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -303,7 +303,7 @@ config M68KFPU_EMU_EXTRAPREC
           correct rounding, the emulator can (often) do the same but this
           extra calculation can cost quite some time, so you can disable
           it here. The emulator will then "only" calculate with a 64 bit
-          mantissa and round slightly incorrect, what is more then enough
+          mantissa and round slightly incorrect, what is more than enough
           for normal usage.
 
 config M68KFPU_EMU_ONLY
diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c
index 6d813de2baf1..184acc90808d 100644
--- a/arch/m68k/kernel/traps.c
+++ b/arch/m68k/kernel/traps.c
@@ -401,7 +401,7 @@ static inline void do_040writebacks(struct frame *fp)
  * called from sigreturn(), must ensure userspace code didn't
  * manipulate exception frame to circumvent protection, then complete
  * pending writebacks
- * we just clear TM2 to turn it into an userspace access
+ * we just clear TM2 to turn it into a userspace access
  */
 asmlinkage void berr_040cleanup(struct frame *fp)
 {
diff --git a/arch/mips/kernel/stacktrace.c b/arch/mips/kernel/stacktrace.c
index 0632e2a849c0..58f5cd76c8c3 100644
--- a/arch/mips/kernel/stacktrace.c
+++ b/arch/mips/kernel/stacktrace.c
@@ -32,7 +32,8 @@ static void save_raw_context_stack(struct stack_trace *trace,
         }
 }
 
-static void save_context_stack(struct stack_trace *trace, struct pt_regs *regs)
+static void save_context_stack(struct stack_trace *trace,
+        struct task_struct *tsk, struct pt_regs *regs)
 {
         unsigned long sp = regs->regs[29];
 #ifdef CONFIG_KALLSYMS
@@ -41,7 +42,7 @@ static void save_context_stack(struct stack_trace *trace, struct pt_regs *regs)
 
         if (raw_show_trace || !__kernel_text_address(pc)) {
                 unsigned long stack_page =
-                        (unsigned long)task_stack_page(current);
+                        (unsigned long)task_stack_page(tsk);
                 if (stack_page && sp >= stack_page &&
                     sp <= stack_page + THREAD_SIZE - 32)
                         save_raw_context_stack(trace, sp);
@@ -54,7 +55,7 @@ static void save_context_stack(struct stack_trace *trace, struct pt_regs *regs)
                         trace->entries[trace->nr_entries++] = pc;
                 if (trace->nr_entries >= trace->max_entries)
                         break;
-                pc = unwind_stack(current, &sp, pc, &ra);
+                pc = unwind_stack(tsk, &sp, pc, &ra);
         } while (pc);
 #else
         save_raw_context_stack(trace, sp);
@@ -66,12 +67,23 @@ static void save_context_stack(struct stack_trace *trace, struct pt_regs *regs)
  */
 void save_stack_trace(struct stack_trace *trace)
 {
+        save_stack_trace_tsk(current, trace);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
         struct pt_regs dummyregs;
         struct pt_regs *regs = &dummyregs;
 
         WARN_ON(trace->nr_entries || !trace->max_entries);
 
-        prepare_frametrace(regs);
-        save_context_stack(trace, regs);
+        if (tsk != current) {
+                regs->regs[29] = tsk->thread.reg29;
+                regs->regs[31] = 0;
+                regs->cp0_epc = tsk->thread.reg31;
+        } else
+                prepare_frametrace(regs);
+        save_context_stack(trace, tsk, regs);
 }
-EXPORT_SYMBOL_GPL(save_stack_trace);
+EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
index 97862f45496d..caf5e9a0acc7 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
@@ -148,7 +148,7 @@ int read_eeprom(char *buffer, int eeprom_size, int size)
         send_byte(W_HEADER);
         recv_ack();
 
-        /* EEPROM with size of more then 2K need two byte addressing */
+        /* EEPROM with size of more than 2K need two byte addressing */
         if (eeprom_size > 2048) {
                 send_byte(0x00);
                 recv_ack();
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index f32829937aad..ab6dda372438 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -208,7 +208,7 @@ image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
 #
 # Theses are default targets to build images which embed device tree blobs.
 # They are only required on boards which do not have FDT support in firmware.
-# Boards with newish u-boot firmare can use the uImage target above
+# Boards with newish u-boot firmware can use the uImage target above
 #
 
 # Board ports in arch/powerpc/platform/40x/Kconfig
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 3b295e8df53f..43cc68bd3192 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -134,7 +134,7 @@
                 };
 
                 USB1: usb@e0000400 {
-                        compatible = "ohci-be";
+                        compatible = "ibm,usb-ohci-440epx", "ohci-be";
                         reg = <0x00000000 0xe0000400 0x00000060>;
                         interrupt-parent = <&UIC0>;
                         interrupts = <0x15 0x8>;
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 989edcdf0297..c9329786073b 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -317,7 +317,7 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
         /*
          * It is possible to have multiple instances associated with a given
          * task either because an multiple functions in the call path
-         * have a return probe installed on them, and/or more then one return
+         * have a return probe installed on them, and/or more than one return
          * return probe was registered for a target function.
          *
          * We can handle this because:
diff --git a/arch/powerpc/oprofile/cell/spu_profiler.c b/arch/powerpc/oprofile/cell/spu_profiler.c
index dd499c3e9da7..83faa958b9d4 100644
--- a/arch/powerpc/oprofile/cell/spu_profiler.c
+++ b/arch/powerpc/oprofile/cell/spu_profiler.c
@@ -49,7 +49,7 @@ void set_spu_profiling_frequency(unsigned int freq_khz, unsigned int cycles_rese
          * of precision.  This is close enough for the purpose at hand.
          *
          * The value of the timeout should be small enough that the hw
-         * trace buffer will not get more then about 1/3 full for the
+         * trace buffer will not get more than about 1/3 full for the
          * maximum user specified (the LFSR value) hw sampling frequency.
          * This is to ensure the trace buffer will never fill even if the
          * kernel thread scheduling varies under a heavy system load.
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 19577aeffd7b..a94a3c3ae932 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -299,7 +299,7 @@ config WARN_STACK
           This option enables the compiler options -mwarn-framesize and
           -mwarn-dynamicstack. If the compiler supports these options it
           will generate warnings for function which either use alloca or
-          create a stack frame bigger then CONFIG_WARN_STACK_SIZE.
+          create a stack frame bigger than CONFIG_WARN_STACK_SIZE.
 
           Say N if you are unsure.
 
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index 9b92856632cf..a01cf0284db2 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -382,7 +382,7 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
         /*
          * It is possible to have multiple instances associated with a given
          * task either because an multiple functions in the call path
-         * have a return probe installed on them, and/or more then one return
+         * have a return probe installed on them, and/or more than one return
          * return probe was registered for a target function.
          *
          * We can handle this because:
diff --git a/arch/sparc/kernel/kprobes.c b/arch/sparc/kernel/kprobes.c
index 201a6e547e4a..3bc6527c95af 100644
--- a/arch/sparc/kernel/kprobes.c
+++ b/arch/sparc/kernel/kprobes.c
@@ -517,7 +517,7 @@ int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs)
         /*
          * It is possible to have multiple instances associated with a given
          * task either because an multiple functions in the call path
-         * have a return probe installed on them, and/or more then one return
+         * have a return probe installed on them, and/or more than one return
          * return probe was registered for a target function.
          *
          * We can handle this because:
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index eead6f8f9218..884d985b8b82 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -695,7 +695,7 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
         /*
          * It is possible to have multiple instances associated with a given
          * task either because multiple functions in the call path have
-         * return probes installed on them, and/or more then one
+         * return probes installed on them, and/or more than one
          * return probe was registered for a target function.
          *
          * We can handle this because:
diff --git a/arch/x86/kernel/mfgpt_32.c b/arch/x86/kernel/mfgpt_32.c
index c12314c9e86f..8815f3c7fec7 100644
--- a/arch/x86/kernel/mfgpt_32.c
+++ b/arch/x86/kernel/mfgpt_32.c
@@ -252,7 +252,7 @@ EXPORT_SYMBOL_GPL(geode_mfgpt_alloc_timer);
 /*
  * The MFPGT timers on the CS5536 provide us with suitable timers to use
  * as clock event sources - not as good as a HPET or APIC, but certainly
- * better then the PIT.  This isn't a general purpose MFGPT driver, but
+ * better than the PIT.  This isn't a general purpose MFGPT driver, but
  * a simplified one designed specifically to act as a clock event source.
  * For full details about the MFGPT, please consult the CS5536 data sheet.
  */
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 015b6b2a26b9..1da55fe4beff 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -33,6 +33,15 @@ KBUILD_CFLAGS += -ffreestanding
 
 KBUILD_CFLAGS += -pipe -mlongcalls
 
+vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
+plfdirs := $(patsubst %,arch/xtensa/platforms/%/,$(platform-y))
+
+ifeq ($(KBUILD_SRC),)
+KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(vardirs) $(plfdirs))
+else
+KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(vardirs) $(plfdirs))
+endif
+
 KBUILD_DEFCONFIG := iss_defconfig
 
 # ramdisk/initrd support
@@ -66,21 +75,6 @@ libs-y		+= arch/xtensa/lib/ $(LIBGCC)
 
 boot            := arch/xtensa/boot
 
-archinc         := include/asm-xtensa
-
-archprepare: $(archinc)/.platform
-
-# Update processor variant and platform symlinks if something which affects
-# them changed.
-
-$(archinc)/.platform: $(wildcard include/config/arch/*.h) include/config/auto.conf
-        @echo '  SYMLINK $(archinc)/variant -> $(archinc)/variant-$(VARIANT)'
-        $(Q)mkdir -p $(archinc)
-        $(Q)ln -fsn $(srctree)/$(archinc)/variant-$(VARIANT) $(archinc)/variant
-        @echo '  SYMLINK $(archinc)/platform -> $(archinc)/platform-$(PLATFORM)'
-        $(Q)ln -fsn $(srctree)/$(archinc)/platform-$(PLATFORM) $(archinc)/platform
-        @touch $@
-
 
 all: zImage
 
@@ -89,10 +83,6 @@ bzImage : zImage
 zImage zImage.initrd: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) $@
 
-CLEAN_FILES     += arch/xtensa/vmlinux.lds                      \
-                   $(archinc)/platform $(archinc)/variant       \
-                   $(archinc)/.platform
-
 define archhelp
   @echo '* zImage      - Compressed kernel image (arch/xtensa/boot/images/zImage.*)'
 endef
diff --git a/arch/xtensa/boot/boot-elf/boot.lds.S b/arch/xtensa/boot/boot-elf/boot.lds.S
index 849dfcafd518..4e53b74dc44b 100644
--- a/arch/xtensa/boot/boot-elf/boot.lds.S
+++ b/arch/xtensa/boot/boot-elf/boot.lds.S
@@ -1,4 +1,4 @@
-#include <asm/variant/core.h>
+#include <variant/core.h>
 OUTPUT_ARCH(xtensa)
 ENTRY(_ResetVector)
 
diff --git a/arch/xtensa/boot/boot-redboot/bootstrap.S b/arch/xtensa/boot/boot-redboot/bootstrap.S
index 84848123e2a8..5582e8cfac8f 100644
--- a/arch/xtensa/boot/boot-redboot/bootstrap.S
+++ b/arch/xtensa/boot/boot-redboot/bootstrap.S
@@ -1,4 +1,4 @@
-#include <asm/variant/core.h>
+#include <variant/core.h>
 #include <asm/regs.h>
 #include <asm/asmmacro.h>
 #include <asm/cacheasm.h>
diff --git a/include/asm-xtensa/Kbuild b/arch/xtensa/include/asm/Kbuild
index c68e1680da01..58c02a454130 100644
--- a/include/asm-xtensa/Kbuild
+++ b/arch/xtensa/include/asm/Kbuild
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+
+unifdef-y += swab.h
diff --git a/include/asm-xtensa/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
index 76915cabad17..755320f6e0bc 100644
--- a/include/asm-xtensa/asmmacro.h
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -11,7 +11,7 @@
 #ifndef _XTENSA_ASMMACRO_H
 #define _XTENSA_ASMMACRO_H
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 /*
  * Some little helpers for loops. Use zero-overhead-loops
diff --git a/include/asm-xtensa/atomic.h b/arch/xtensa/include/asm/atomic.h
index 67ad67bed8c1..67ad67bed8c1 100644
--- a/include/asm-xtensa/atomic.h
+++ b/arch/xtensa/include/asm/atomic.h
diff --git a/include/asm-xtensa/auxvec.h b/arch/xtensa/include/asm/auxvec.h
index 257dec75c5af..257dec75c5af 100644
--- a/include/asm-xtensa/auxvec.h
+++ b/arch/xtensa/include/asm/auxvec.h
diff --git a/include/asm-xtensa/bitops.h b/arch/xtensa/include/asm/bitops.h
index 6c3930397bd3..6c3930397bd3 100644
--- a/include/asm-xtensa/bitops.h
+++ b/arch/xtensa/include/asm/bitops.h
diff --git a/include/asm-xtensa/bootparam.h b/arch/xtensa/include/asm/bootparam.h
index 9983f2c1b7ee..9983f2c1b7ee 100644
--- a/include/asm-xtensa/bootparam.h
+++ b/arch/xtensa/include/asm/bootparam.h
diff --git a/include/asm-xtensa/bug.h b/arch/xtensa/include/asm/bug.h
index 3e52d72712f1..3e52d72712f1 100644
--- a/include/asm-xtensa/bug.h
+++ b/arch/xtensa/include/asm/bug.h
diff --git a/include/asm-xtensa/bugs.h b/arch/xtensa/include/asm/bugs.h
index 69b29d198249..69b29d198249 100644
--- a/include/asm-xtensa/bugs.h
+++ b/arch/xtensa/include/asm/bugs.h
diff --git a/arch/xtensa/include/asm/byteorder.h b/arch/xtensa/include/asm/byteorder.h
new file mode 100644
index 000000000000..329b94591ca4
--- /dev/null
+++ b/arch/xtensa/include/asm/byteorder.h
@@ -0,0 +1,14 @@
+#ifndef _XTENSA_BYTEORDER_H
+#define _XTENSA_BYTEORDER_H
+
+#include <asm/swab.h>
+
+#ifdef __XTENSA_EL__
+#include <linux/byteorder/little_endian.h>
+#elif defined(__XTENSA_EB__)
+#include <linux/byteorder/big_endian.h>
+#else
+# error processor byte order undefined!
+#endif
+
+#endif /* _XTENSA_BYTEORDER_H */
diff --git a/include/asm-xtensa/cache.h b/arch/xtensa/include/asm/cache.h
index 3bba2a540cf0..f04c9891142f 100644
--- a/include/asm-xtensa/cache.h
+++ b/arch/xtensa/include/asm/cache.h
@@ -11,7 +11,7 @@
 #ifndef _XTENSA_CACHE_H
 #define _XTENSA_CACHE_H
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 #define L1_CACHE_SHIFT  XCHAL_DCACHE_LINEWIDTH
 #define L1_CACHE_BYTES  XCHAL_DCACHE_LINESIZE
diff --git a/include/asm-xtensa/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index 2c20a58f94cd..2c20a58f94cd 100644
--- a/include/asm-xtensa/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
diff --git a/include/asm-xtensa/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 94c4c53a099e..94c4c53a099e 100644
--- a/include/asm-xtensa/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
diff --git a/include/asm-xtensa/checksum.h b/arch/xtensa/include/asm/checksum.h
index 23534c60b3a4..f84d3f00774a 100644
--- a/include/asm-xtensa/checksum.h
+++ b/arch/xtensa/include/asm/checksum.h
@@ -12,7 +12,7 @@
 #define _XTENSA_CHECKSUM_H
 
 #include <linux/in6.h>
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 /*
  * computes the checksum of a memory block at buff, length len,
diff --git a/include/asm-xtensa/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h
index 1cbcf9001a41..65a285d8d3fb 100644
--- a/include/asm-xtensa/coprocessor.h
+++ b/arch/xtensa/include/asm/coprocessor.h
@@ -13,11 +13,11 @@
 #define _XTENSA_COPROCESSOR_H
 
 #include <linux/stringify.h>
-#include <asm/variant/tie.h>
+#include <variant/tie.h>
 #include <asm/types.h>
 
 #ifdef __ASSEMBLY__
-# include <asm/variant/tie-asm.h>
+# include <variant/tie-asm.h>
 
 .macro  xchal_sa_start  a b
         .set .Lxchal_pofs_, 0
diff --git a/include/asm-xtensa/cpumask.h b/arch/xtensa/include/asm/cpumask.h
index ebeede397db3..ebeede397db3 100644
--- a/include/asm-xtensa/cpumask.h
+++ b/arch/xtensa/include/asm/cpumask.h
diff --git a/include/asm-xtensa/cputime.h b/arch/xtensa/include/asm/cputime.h
index a7fb864a50ae..a7fb864a50ae 100644
--- a/include/asm-xtensa/cputime.h
+++ b/arch/xtensa/include/asm/cputime.h
diff --git a/include/asm-xtensa/current.h b/arch/xtensa/include/asm/current.h
index 8d1eb5d78649..8d1eb5d78649 100644
--- a/include/asm-xtensa/current.h
+++ b/arch/xtensa/include/asm/current.h
diff --git a/include/asm-xtensa/delay.h b/arch/xtensa/include/asm/delay.h
index e1d8c9e010c1..e1d8c9e010c1 100644
--- a/include/asm-xtensa/delay.h
+++ b/arch/xtensa/include/asm/delay.h
diff --git a/include/asm-xtensa/device.h b/arch/xtensa/include/asm/device.h
index d8f9872b0e2d..d8f9872b0e2d 100644
--- a/include/asm-xtensa/device.h
+++ b/arch/xtensa/include/asm/device.h
diff --git a/include/asm-xtensa/div64.h b/arch/xtensa/include/asm/div64.h
index f35678cb0a9b..f35678cb0a9b 100644
--- a/include/asm-xtensa/div64.h
+++ b/arch/xtensa/include/asm/div64.h
diff --git a/include/asm-xtensa/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping.h
index 51882ae3db4d..51882ae3db4d 100644
--- a/include/asm-xtensa/dma-mapping.h
+++ b/arch/xtensa/include/asm/dma-mapping.h
diff --git a/include/asm-xtensa/dma.h b/arch/xtensa/include/asm/dma.h
index e30f3abf48f0..e30f3abf48f0 100644
--- a/include/asm-xtensa/dma.h
+++ b/arch/xtensa/include/asm/dma.h
diff --git a/include/asm-xtensa/elf.h b/arch/xtensa/include/asm/elf.h
index c3f53e755ca5..c3f53e755ca5 100644
--- a/include/asm-xtensa/elf.h
+++ b/arch/xtensa/include/asm/elf.h
diff --git a/include/asm-xtensa/emergency-restart.h b/arch/xtensa/include/asm/emergency-restart.h
index 108d8c48e42e..108d8c48e42e 100644
--- a/include/asm-xtensa/emergency-restart.h
+++ b/arch/xtensa/include/asm/emergency-restart.h
diff --git a/include/asm-xtensa/errno.h b/arch/xtensa/include/asm/errno.h
index a0f3b96b79b4..a0f3b96b79b4 100644
--- a/include/asm-xtensa/errno.h
+++ b/arch/xtensa/include/asm/errno.h
diff --git a/include/asm-xtensa/fb.h b/arch/xtensa/include/asm/fb.h
index c7df38030992..c7df38030992 100644
--- a/include/asm-xtensa/fb.h
+++ b/arch/xtensa/include/asm/fb.h
diff --git a/include/asm-xtensa/fcntl.h b/arch/xtensa/include/asm/fcntl.h
index 46ab12db5739..46ab12db5739 100644
--- a/include/asm-xtensa/fcntl.h
+++ b/arch/xtensa/include/asm/fcntl.h
diff --git a/include/asm-xtensa/futex.h b/arch/xtensa/include/asm/futex.h
index 0b745828f42b..0b745828f42b 100644
--- a/include/asm-xtensa/futex.h
+++ b/arch/xtensa/include/asm/futex.h
diff --git a/include/asm-xtensa/hardirq.h b/arch/xtensa/include/asm/hardirq.h
index 87cb19d1b10c..87cb19d1b10c 100644
--- a/include/asm-xtensa/hardirq.h
+++ b/arch/xtensa/include/asm/hardirq.h
diff --git a/include/asm-xtensa/highmem.h b/arch/xtensa/include/asm/highmem.h
index 0a046ca5a687..0a046ca5a687 100644
--- a/include/asm-xtensa/highmem.h
+++ b/arch/xtensa/include/asm/highmem.h
diff --git a/include/asm-xtensa/hw_irq.h b/arch/xtensa/include/asm/hw_irq.h
index 3ddbea759b2b..3ddbea759b2b 100644
--- a/include/asm-xtensa/hw_irq.h
+++ b/arch/xtensa/include/asm/hw_irq.h
diff --git a/include/asm-xtensa/io.h b/arch/xtensa/include/asm/io.h
index 07b7299dab20..07b7299dab20 100644
--- a/include/asm-xtensa/io.h
+++ b/arch/xtensa/include/asm/io.h
diff --git a/include/asm-xtensa/ioctl.h b/arch/xtensa/include/asm/ioctl.h
index b279fe06dfe5..b279fe06dfe5 100644
--- a/include/asm-xtensa/ioctl.h
+++ b/arch/xtensa/include/asm/ioctl.h
diff --git a/include/asm-xtensa/ioctls.h b/arch/xtensa/include/asm/ioctls.h
index 0ffa942954b9..0ffa942954b9 100644
--- a/include/asm-xtensa/ioctls.h
+++ b/arch/xtensa/include/asm/ioctls.h
diff --git a/include/asm-xtensa/ipcbuf.h b/arch/xtensa/include/asm/ipcbuf.h
index c33aa6a42145..c33aa6a42145 100644
--- a/include/asm-xtensa/ipcbuf.h
+++ b/arch/xtensa/include/asm/ipcbuf.h
diff --git a/include/asm-xtensa/irq.h b/arch/xtensa/include/asm/irq.h
index fc73b7f11aff..1620d1e0e695 100644
--- a/include/asm-xtensa/irq.h
+++ b/arch/xtensa/include/asm/irq.h
@@ -11,8 +11,8 @@
 #ifndef _XTENSA_IRQ_H
 #define _XTENSA_IRQ_H
 
-#include <asm/platform/hardware.h>
-#include <asm/variant/core.h>
+#include <platform/hardware.h>
+#include <variant/core.h>
 
 #ifndef PLATFORM_NR_IRQS
 # define PLATFORM_NR_IRQS 0
diff --git a/include/asm-xtensa/irq_regs.h b/arch/xtensa/include/asm/irq_regs.h
index 3dd9c0b70270..3dd9c0b70270 100644
--- a/include/asm-xtensa/irq_regs.h
+++ b/arch/xtensa/include/asm/irq_regs.h
diff --git a/include/asm-xtensa/kdebug.h b/arch/xtensa/include/asm/kdebug.h
index 6ece1b037665..6ece1b037665 100644
--- a/include/asm-xtensa/kdebug.h
+++ b/arch/xtensa/include/asm/kdebug.h
diff --git a/include/asm-xtensa/kmap_types.h b/arch/xtensa/include/asm/kmap_types.h
index 9e822d2e3bce..9e822d2e3bce 100644
--- a/include/asm-xtensa/kmap_types.h
+++ b/arch/xtensa/include/asm/kmap_types.h
diff --git a/include/asm-xtensa/linkage.h b/arch/xtensa/include/asm/linkage.h
index bf2128a99d79..bf2128a99d79 100644
--- a/include/asm-xtensa/linkage.h
+++ b/arch/xtensa/include/asm/linkage.h
diff --git a/include/asm-xtensa/local.h b/arch/xtensa/include/asm/local.h
index 48723e550d14..48723e550d14 100644
--- a/include/asm-xtensa/local.h
+++ b/arch/xtensa/include/asm/local.h
diff --git a/include/asm-xtensa/mman.h b/arch/xtensa/include/asm/mman.h
index 9b92620c8a1e..9b92620c8a1e 100644
--- a/include/asm-xtensa/mman.h
+++ b/arch/xtensa/include/asm/mman.h
diff --git a/include/asm-xtensa/mmu.h b/arch/xtensa/include/asm/mmu.h
index 44c5bb04c55c..44c5bb04c55c 100644
--- a/include/asm-xtensa/mmu.h
+++ b/arch/xtensa/include/asm/mmu.h
diff --git a/include/asm-xtensa/mmu_context.h b/arch/xtensa/include/asm/mmu_context.h
index c0fd8e5b4513..c0fd8e5b4513 100644
--- a/include/asm-xtensa/mmu_context.h
+++ b/arch/xtensa/include/asm/mmu_context.h
diff --git a/include/asm-xtensa/module.h b/arch/xtensa/include/asm/module.h
index d9b34bee4d42..d9b34bee4d42 100644
--- a/include/asm-xtensa/module.h
+++ b/arch/xtensa/include/asm/module.h
diff --git a/include/asm-xtensa/msgbuf.h b/arch/xtensa/include/asm/msgbuf.h
index 693c96755280..693c96755280 100644
--- a/include/asm-xtensa/msgbuf.h
+++ b/arch/xtensa/include/asm/msgbuf.h
diff --git a/include/asm-xtensa/mutex.h b/arch/xtensa/include/asm/mutex.h
index 458c1f7fbc18..458c1f7fbc18 100644
--- a/include/asm-xtensa/mutex.h
+++ b/arch/xtensa/include/asm/mutex.h
diff --git a/include/asm-xtensa/page.h b/arch/xtensa/include/asm/page.h
index 11f7dc2dbec7..11f7dc2dbec7 100644
--- a/include/asm-xtensa/page.h
+++ b/arch/xtensa/include/asm/page.h
diff --git a/include/asm-xtensa/param.h b/arch/xtensa/include/asm/param.h
index ba03d5aeab6b..ba03d5aeab6b 100644
--- a/include/asm-xtensa/param.h
+++ b/arch/xtensa/include/asm/param.h
diff --git a/include/asm-xtensa/pci-bridge.h b/arch/xtensa/include/asm/pci-bridge.h
index 00fcbd7c534a..00fcbd7c534a 100644
--- a/include/asm-xtensa/pci-bridge.h
+++ b/arch/xtensa/include/asm/pci-bridge.h
diff --git a/include/asm-xtensa/pci.h b/arch/xtensa/include/asm/pci.h
index 66410acf18b4..66410acf18b4 100644
--- a/include/asm-xtensa/pci.h
+++ b/arch/xtensa/include/asm/pci.h
diff --git a/include/asm-xtensa/percpu.h b/arch/xtensa/include/asm/percpu.h
index 6d2bc2ada9d1..6d2bc2ada9d1 100644
--- a/include/asm-xtensa/percpu.h
+++ b/arch/xtensa/include/asm/percpu.h
diff --git a/include/asm-xtensa/pgalloc.h b/arch/xtensa/include/asm/pgalloc.h
index 4f4a7987eded..4f4a7987eded 100644
--- a/include/asm-xtensa/pgalloc.h
+++ b/arch/xtensa/include/asm/pgalloc.h
diff --git a/include/asm-xtensa/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index 8014d96b21f1..8014d96b21f1 100644
--- a/include/asm-xtensa/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
diff --git a/include/asm-xtensa/platform.h b/arch/xtensa/include/asm/platform.h
index 48135a9718b0..e3d5a48ad495 100644
--- a/include/asm-xtensa/platform.h
+++ b/arch/xtensa/include/asm/platform.h
@@ -1,6 +1,4 @@
 /*
- * include/asm-xtensa/platform.h
- *
  * Platform specific functions
  *
  * This file is subject to the terms and conditions of the GNU General
diff --git a/include/asm-xtensa/poll.h b/arch/xtensa/include/asm/poll.h
index 9d2d5993f068..9d2d5993f068 100644
--- a/include/asm-xtensa/poll.h
+++ b/arch/xtensa/include/asm/poll.h
diff --git a/include/asm-xtensa/posix_types.h b/arch/xtensa/include/asm/posix_types.h
index 43f9dd1126a4..43f9dd1126a4 100644
--- a/include/asm-xtensa/posix_types.h
+++ b/arch/xtensa/include/asm/posix_types.h
diff --git a/include/asm-xtensa/processor.h b/arch/xtensa/include/asm/processor.h
index 4918a4e96d42..07387d3b99f4 100644
--- a/include/asm-xtensa/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -11,7 +11,7 @@
 #ifndef _XTENSA_PROCESSOR_H
 #define _XTENSA_PROCESSOR_H
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 #include <asm/coprocessor.h>
 
 #include <linux/compiler.h>
diff --git a/include/asm-xtensa/ptrace.h b/arch/xtensa/include/asm/ptrace.h
index 089b0db44816..905e1e619654 100644
--- a/include/asm-xtensa/ptrace.h
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -111,7 +111,7 @@ struct pt_regs {
         unsigned long areg[16];         /* 128 (64) */
 };
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 # define task_pt_regs(tsk) ((struct pt_regs*) \
   (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
diff --git a/include/asm-xtensa/regs.h b/arch/xtensa/include/asm/regs.h
index d4baed246928..d4baed246928 100644
--- a/include/asm-xtensa/regs.h
+++ b/arch/xtensa/include/asm/regs.h
diff --git a/include/asm-xtensa/resource.h b/arch/xtensa/include/asm/resource.h
index 17b5ab311771..17b5ab311771 100644
--- a/include/asm-xtensa/resource.h
+++ b/arch/xtensa/include/asm/resource.h
diff --git a/include/asm-xtensa/rmap.h b/arch/xtensa/include/asm/rmap.h
index 649588b7e9ad..649588b7e9ad 100644
--- a/include/asm-xtensa/rmap.h
+++ b/arch/xtensa/include/asm/rmap.h
diff --git a/include/asm-xtensa/rwsem.h b/arch/xtensa/include/asm/rwsem.h
index e39edf5c86f2..e39edf5c86f2 100644
--- a/include/asm-xtensa/rwsem.h
+++ b/arch/xtensa/include/asm/rwsem.h
diff --git a/include/asm-xtensa/scatterlist.h b/arch/xtensa/include/asm/scatterlist.h
index 810080bb0a2b..810080bb0a2b 100644
--- a/include/asm-xtensa/scatterlist.h
+++ b/arch/xtensa/include/asm/scatterlist.h
diff --git a/include/asm-xtensa/sections.h b/arch/xtensa/include/asm/sections.h
index 40b5191b55a2..40b5191b55a2 100644
--- a/include/asm-xtensa/sections.h
+++ b/arch/xtensa/include/asm/sections.h
diff --git a/include/asm-xtensa/segment.h b/arch/xtensa/include/asm/segment.h
index a2eb547a1a75..a2eb547a1a75 100644
--- a/include/asm-xtensa/segment.h
+++ b/arch/xtensa/include/asm/segment.h
diff --git a/include/asm-xtensa/sembuf.h b/arch/xtensa/include/asm/sembuf.h
index c15870493b33..c15870493b33 100644
--- a/include/asm-xtensa/sembuf.h
+++ b/arch/xtensa/include/asm/sembuf.h
diff --git a/include/asm-xtensa/serial.h b/arch/xtensa/include/asm/serial.h
index ec04114fcf0b..a8a2493260f6 100644
--- a/include/asm-xtensa/serial.h
+++ b/arch/xtensa/include/asm/serial.h
@@ -13,6 +13,6 @@
 #ifndef _XTENSA_SERIAL_H
 #define _XTENSA_SERIAL_H
 
-#include <asm/platform/serial.h>
+#include <platform/serial.h>
 
 #endif  /* _XTENSA_SERIAL_H */
diff --git a/include/asm-xtensa/setup.h b/arch/xtensa/include/asm/setup.h
index e3636520d8cc..e3636520d8cc 100644
--- a/include/asm-xtensa/setup.h
+++ b/arch/xtensa/include/asm/setup.h
diff --git a/include/asm-xtensa/shmbuf.h b/arch/xtensa/include/asm/shmbuf.h
index ad4b0121782c..ad4b0121782c 100644
--- a/include/asm-xtensa/shmbuf.h
+++ b/arch/xtensa/include/asm/shmbuf.h
diff --git a/include/asm-xtensa/shmparam.h b/arch/xtensa/include/asm/shmparam.h
index c8cc16c3da9e..c8cc16c3da9e 100644
--- a/include/asm-xtensa/shmparam.h
+++ b/arch/xtensa/include/asm/shmparam.h
diff --git a/include/asm-xtensa/sigcontext.h b/arch/xtensa/include/asm/sigcontext.h
index 03383af8c3b7..03383af8c3b7 100644
--- a/include/asm-xtensa/sigcontext.h
+++ b/arch/xtensa/include/asm/sigcontext.h
diff --git a/include/asm-xtensa/siginfo.h b/arch/xtensa/include/asm/siginfo.h
index 6916248295df..6916248295df 100644
--- a/include/asm-xtensa/siginfo.h
+++ b/arch/xtensa/include/asm/siginfo.h
diff --git a/include/asm-xtensa/signal.h b/arch/xtensa/include/asm/signal.h
index 633ba73bc4d2..633ba73bc4d2 100644
--- a/include/asm-xtensa/signal.h
+++ b/arch/xtensa/include/asm/signal.h
diff --git a/include/asm-xtensa/smp.h b/arch/xtensa/include/asm/smp.h
index 83c569e3bdbd..83c569e3bdbd 100644
--- a/include/asm-xtensa/smp.h
+++ b/arch/xtensa/include/asm/smp.h
diff --git a/include/asm-xtensa/socket.h b/arch/xtensa/include/asm/socket.h
index 6100682b1da2..6100682b1da2 100644
--- a/include/asm-xtensa/socket.h
+++ b/arch/xtensa/include/asm/socket.h
diff --git a/include/asm-xtensa/sockios.h b/arch/xtensa/include/asm/sockios.h
index efe0af379f01..efe0af379f01 100644
--- a/include/asm-xtensa/sockios.h
+++ b/arch/xtensa/include/asm/sockios.h
diff --git a/include/asm-xtensa/spinlock.h b/arch/xtensa/include/asm/spinlock.h
index 8ff23649581b..8ff23649581b 100644
--- a/include/asm-xtensa/spinlock.h
+++ b/arch/xtensa/include/asm/spinlock.h
diff --git a/include/asm-xtensa/stat.h b/arch/xtensa/include/asm/stat.h
index c4992038cee0..c4992038cee0 100644
--- a/include/asm-xtensa/stat.h
+++ b/arch/xtensa/include/asm/stat.h
diff --git a/include/asm-xtensa/statfs.h b/arch/xtensa/include/asm/statfs.h
index 9c3d1a213136..9c3d1a213136 100644
--- a/include/asm-xtensa/statfs.h
+++ b/arch/xtensa/include/asm/statfs.h
diff --git a/include/asm-xtensa/string.h b/arch/xtensa/include/asm/string.h
index 5fb8c27cbef5..5fb8c27cbef5 100644
--- a/include/asm-xtensa/string.h
+++ b/arch/xtensa/include/asm/string.h
diff --git a/include/asm-xtensa/byteorder.h b/arch/xtensa/include/asm/swab.h
index 765edf17a9a4..f50b697eb601 100644
--- a/include/asm-xtensa/byteorder.h
+++ b/arch/xtensa/include/asm/swab.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-xtensa/byteorder.h
+ * include/asm-xtensa/swab.h
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -8,13 +8,15 @@
  * Copyright (C) 2001 - 2005 Tensilica Inc.
  */
 
-#ifndef _XTENSA_BYTEORDER_H
-#define _XTENSA_BYTEORDER_H
+#ifndef _XTENSA_SWAB_H
+#define _XTENSA_SWAB_H
 
 #include <asm/types.h>
 #include <linux/compiler.h>
 
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+#define __SWAB_64_THRU_32__
+
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
     __u32 res;
     /* instruction sequence from Xtensa ISA release 2/2000 */
@@ -28,8 +30,9 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
             );
     return res;
 }
+#define __arch_swab32 __arch_swab32
 
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
     /* Given that 'short' values are signed (i.e., can be negative),
      * we cannot assume that the upper 16-bits of the register are
@@ -62,21 +65,6 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
 
     return res;
 }
+#define __arch_swab16 __arch_swab16
 
-#define __arch__swab32(x) ___arch__swab32(x)
-#define __arch__swab16(x) ___arch__swab16(x)
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#ifdef __XTENSA_EL__
-# include <linux/byteorder/little_endian.h>
-#elif defined(__XTENSA_EB__)
-# include <linux/byteorder/big_endian.h>
-#else
-# error processor byte order undefined!
-#endif
-
-#endif /* _XTENSA_BYTEORDER_H */
+#endif /* _XTENSA_SWAB_H */
diff --git a/include/asm-xtensa/syscall.h b/arch/xtensa/include/asm/syscall.h
index 05cebf8f62b1..05cebf8f62b1 100644
--- a/include/asm-xtensa/syscall.h
+++ b/arch/xtensa/include/asm/syscall.h
diff --git a/include/asm-xtensa/system.h b/arch/xtensa/include/asm/system.h
index 62b1e8f3c13c..62b1e8f3c13c 100644
--- a/include/asm-xtensa/system.h
+++ b/arch/xtensa/include/asm/system.h
diff --git a/include/asm-xtensa/termbits.h b/arch/xtensa/include/asm/termbits.h
index 85aa6a3c0b6e..85aa6a3c0b6e 100644
--- a/include/asm-xtensa/termbits.h
+++ b/arch/xtensa/include/asm/termbits.h
diff --git a/include/asm-xtensa/termios.h b/arch/xtensa/include/asm/termios.h
index 4673f42f88a7..4673f42f88a7 100644
--- a/include/asm-xtensa/termios.h
+++ b/arch/xtensa/include/asm/termios.h
diff --git a/include/asm-xtensa/thread_info.h b/arch/xtensa/include/asm/thread_info.h
index 0f4fe1faf9ba..0f4fe1faf9ba 100644
--- a/include/asm-xtensa/thread_info.h
+++ b/arch/xtensa/include/asm/thread_info.h
diff --git a/include/asm-xtensa/timex.h b/arch/xtensa/include/asm/timex.h
index b83a8181d448..b83a8181d448 100644
--- a/include/asm-xtensa/timex.h
+++ b/arch/xtensa/include/asm/timex.h
diff --git a/include/asm-xtensa/tlb.h b/arch/xtensa/include/asm/tlb.h
index 31c220faca02..31c220faca02 100644
--- a/include/asm-xtensa/tlb.h
+++ b/arch/xtensa/include/asm/tlb.h
diff --git a/include/asm-xtensa/tlbflush.h b/arch/xtensa/include/asm/tlbflush.h
index 46d240074f74..46d240074f74 100644
--- a/include/asm-xtensa/tlbflush.h
+++ b/arch/xtensa/include/asm/tlbflush.h
diff --git a/include/asm-xtensa/topology.h b/arch/xtensa/include/asm/topology.h
index 7309e38a0ccb..7309e38a0ccb 100644
--- a/include/asm-xtensa/topology.h
+++ b/arch/xtensa/include/asm/topology.h
diff --git a/include/asm-xtensa/types.h b/arch/xtensa/include/asm/types.h
index c89569a8da0c..c89569a8da0c 100644
--- a/include/asm-xtensa/types.h
+++ b/arch/xtensa/include/asm/types.h
diff --git a/include/asm-xtensa/uaccess.h b/arch/xtensa/include/asm/uaccess.h
index b8528426ab1f..b8528426ab1f 100644
--- a/include/asm-xtensa/uaccess.h
+++ b/arch/xtensa/include/asm/uaccess.h
diff --git a/include/asm-xtensa/ucontext.h b/arch/xtensa/include/asm/ucontext.h
index 94c94ed3e00a..94c94ed3e00a 100644
--- a/include/asm-xtensa/ucontext.h
+++ b/arch/xtensa/include/asm/ucontext.h
diff --git a/include/asm-xtensa/unaligned.h b/arch/xtensa/include/asm/unaligned.h
index 8f3424fc5d18..8e7ed046bfed 100644
--- a/include/asm-xtensa/unaligned.h
+++ b/arch/xtensa/include/asm/unaligned.h
@@ -10,20 +10,20 @@
 #ifndef _ASM_XTENSA_UNALIGNED_H
 #define _ASM_XTENSA_UNALIGNED_H
 
-#ifdef __XTENSA_EL__
-# include <linux/unaligned/le_memmove.h>
+#include <asm/byteorder.h>
+
+#ifdef __LITTLE_ENDIAN
+# include <linux/unaligned/le_struct.h>
 # include <linux/unaligned/be_byteshift.h>
 # include <linux/unaligned/generic.h>
 # define get_unaligned  __get_unaligned_le
 # define put_unaligned  __put_unaligned_le
-#elif defined(__XTENSA_EB__)
-# include <linux/unaligned/be_memmove.h>
+#else
+# include <linux/unaligned/be_struct.h>
 # include <linux/unaligned/le_byteshift.h>
 # include <linux/unaligned/generic.h>
 # define get_unaligned  __get_unaligned_be
 # define put_unaligned  __put_unaligned_be
-#else
-# error processor byte order undefined!
 #endif
 
 #endif  /* _ASM_XTENSA_UNALIGNED_H */
diff --git a/include/asm-xtensa/unistd.h b/arch/xtensa/include/asm/unistd.h
index c092c8fbb2cf..c092c8fbb2cf 100644
--- a/include/asm-xtensa/unistd.h
+++ b/arch/xtensa/include/asm/unistd.h
diff --git a/include/asm-xtensa/user.h b/arch/xtensa/include/asm/user.h
index 2c3ed23354a8..2c3ed23354a8 100644
--- a/include/asm-xtensa/user.h
+++ b/arch/xtensa/include/asm/user.h
diff --git a/include/asm-xtensa/vga.h b/arch/xtensa/include/asm/vga.h
index 1fd8cab3a297..1fd8cab3a297 100644
--- a/include/asm-xtensa/vga.h
+++ b/arch/xtensa/include/asm/vga.h
diff --git a/include/asm-xtensa/xor.h b/arch/xtensa/include/asm/xor.h
index e7b1f083991d..e7b1f083991d 100644
--- a/include/asm-xtensa/xor.h
+++ b/arch/xtensa/include/asm/xor.h
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index dfd35dcc1cb5..a51d36a27389 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -25,7 +25,7 @@
 #include <asm/page.h>
 #include <asm/signal.h>
 #include <asm/tlbflush.h>
-#include <asm/variant/tie-asm.h>
+#include <variant/tie-asm.h>
 
 /* Unimplemented features. */
 
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index 51f4fb6f16f9..d506774f4b05 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -16,7 +16,7 @@
 
 #include <asm-generic/vmlinux.lds.h>
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 OUTPUT_ARCH(xtensa)
 ENTRY(_start)
 
diff --git a/arch/xtensa/lib/checksum.S b/arch/xtensa/lib/checksum.S
index 9d9cd990afa6..df397f932d0e 100644
--- a/arch/xtensa/lib/checksum.S
+++ b/arch/xtensa/lib/checksum.S
@@ -16,7 +16,7 @@
 
 #include <asm/errno.h>
 #include <linux/linkage.h>
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 /*
  * computes a partial checksum, e.g. for TCP/UDP fragments
diff --git a/arch/xtensa/lib/memcopy.S b/arch/xtensa/lib/memcopy.S
index ddda8f4bc862..ea59dcd03866 100644
--- a/arch/xtensa/lib/memcopy.S
+++ b/arch/xtensa/lib/memcopy.S
@@ -9,7 +9,7 @@
  * Copyright (C) 2002 - 2005 Tensilica Inc.
  */
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
         .macro  src_b   r, w0, w1
 #ifdef __XTENSA_EB__
diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S
index 56a17495b2db..10b8c400f175 100644
--- a/arch/xtensa/lib/memset.S
+++ b/arch/xtensa/lib/memset.S
@@ -11,7 +11,7 @@
  *  Copyright (C) 2002 Tensilica Inc.
  */
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 /*
  * void *memset(void *dst, int c, size_t length)
diff --git a/arch/xtensa/lib/strncpy_user.S b/arch/xtensa/lib/strncpy_user.S
index b2655d94558d..9f603cdaaa68 100644
--- a/arch/xtensa/lib/strncpy_user.S
+++ b/arch/xtensa/lib/strncpy_user.S
@@ -11,7 +11,7 @@
  *  Copyright (C) 2002 Tensilica Inc.
  */
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 #include <linux/errno.h>
 
 /* Load or store instructions that may cause exceptions use the EX macro. */
diff --git a/arch/xtensa/lib/strnlen_user.S b/arch/xtensa/lib/strnlen_user.S
index ad3f616322ca..23f2a89816a1 100644
--- a/arch/xtensa/lib/strnlen_user.S
+++ b/arch/xtensa/lib/strnlen_user.S
@@ -11,7 +11,7 @@
  *  Copyright (C) 2002 Tensilica Inc.
  */
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 /* Load or store instructions that may cause exceptions use the EX macro. */
 
diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S
index a8ab1d4fe0ae..46d60314bb16 100644
--- a/arch/xtensa/lib/usercopy.S
+++ b/arch/xtensa/lib/usercopy.S
@@ -53,7 +53,7 @@
  *      a11/ original length
  */
 
-#include <asm/variant/core.h>
+#include <variant/core.h>
 
 #ifdef __XTENSA_EB__
 #define ALIGN(R, W0, W1) src    R, W0, W1
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c
index 9141e3690731..efed8897bef3 100644
--- a/arch/xtensa/platforms/iss/console.c
+++ b/arch/xtensa/platforms/iss/console.c
@@ -1,5 +1,5 @@
 /*
- * arch/xtensa/platform-iss/console.c
+ * arch/xtensa/platforms/iss/console.c
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -24,7 +24,7 @@
 #include <asm/uaccess.h>
 #include <asm/irq.h>
 
-#include <asm/platform/simcall.h>
+#include <platform/simcall.h>
 
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
diff --git a/include/asm-xtensa/platform-iss/hardware.h b/arch/xtensa/platforms/iss/include/platform/hardware.h
index 6930c12adc16..6930c12adc16 100644
--- a/include/asm-xtensa/platform-iss/hardware.h
+++ b/arch/xtensa/platforms/iss/include/platform/hardware.h
diff --git a/include/asm-xtensa/platform-iss/simcall.h b/arch/xtensa/platforms/iss/include/platform/simcall.h
index b7952c06a2b7..b7952c06a2b7 100644
--- a/include/asm-xtensa/platform-iss/simcall.h
+++ b/arch/xtensa/platforms/iss/include/platform/simcall.h
diff --git a/arch/xtensa/platforms/iss/io.c b/arch/xtensa/platforms/iss/io.c
index 5b161a5cb65f..571d0b24f895 100644
--- a/arch/xtensa/platforms/iss/io.c
+++ b/arch/xtensa/platforms/iss/io.c
@@ -3,7 +3,7 @@
 #if 0
 
 #include <asm/io.h>
-#include <xtensa/simcall.h>
+#include <platform/platform-iss/simcall.h>
 
 extern int __simc ();
 
diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c
index 64f057d89e73..edad4156d89a 100644
--- a/arch/xtensa/platforms/iss/network.c
+++ b/arch/xtensa/platforms/iss/network.c
@@ -1,6 +1,6 @@
 /*
  *
- * arch/xtensa/platform-iss/network.c
+ * arch/xtensa/platforms/iss/network.c
  *
  * Platform specific initialization.
  *
@@ -33,7 +33,7 @@
 #include <linux/rtnetlink.h>
 #include <linux/platform_device.h>
 
-#include <asm/platform/simcall.h>
+#include <platform/simcall.h>
 
 #define DRIVER_NAME "iss-netdev"
 #define ETH_MAX_PACKET 1500
diff --git a/arch/xtensa/platforms/xt2000/Makefile b/arch/xtensa/platforms/xt2000/Makefile
new file mode 100644
index 000000000000..54d018e45bfc
--- /dev/null
+++ b/arch/xtensa/platforms/xt2000/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Tensilica XT2000 Emulation Board
+#
+
+obj-y                   = setup.o
diff --git a/arch/xtensa/platforms/xt2000/include/platform/hardware.h b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
new file mode 100644
index 000000000000..41459ad07766
--- /dev/null
+++ b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
@@ -0,0 +1,55 @@
+/*
+ * platform/hardware.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Tensilica Inc.
+ */
+
+/*
+ * This file contains the hardware configuration of the XT2000 board.
+ */
+
+#ifndef _XTENSA_XT2000_HARDWARE_H
+#define _XTENSA_XT2000_HARDWARE_H
+
+#include <variant/core.h>
+#include <asm/io.h>
+
+/* 
+ * Memory configuration.
+ */
+
+#define PLATFORM_DEFAULT_MEM_START 0x00000000
+#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
+
+/*
+ * Number of platform IRQs
+ */
+#define PLATFORM_NR_IRQS 3
+/*
+ * On-board components.
+ */
+
+#define SONIC83934_INTNUM       XCHAL_EXTINT3_NUM
+#define SONIC83934_ADDR         IOADDR(0x0d030000)
+
+/*
+ * V3-PCI
+ */
+
+/* The XT2000 uses the V3 as a cascaded interrupt controller for the PCI bus */
+
+#define IRQ_PCI_A               (XCHAL_NUM_INTERRUPTS + 0)
+#define IRQ_PCI_B               (XCHAL_NUM_INTERRUPTS + 1)
+#define IRQ_PCI_C               (XCHAL_NUM_INTERRUPTS + 2)
+
+/*
+ * Various other components.
+ */
+
+#define XT2000_LED_ADDR         IOADDR(0x0d040000)
+
+#endif /* _XTENSA_XT2000_HARDWARE_H */
diff --git a/arch/xtensa/platforms/xt2000/include/platform/serial.h b/arch/xtensa/platforms/xt2000/include/platform/serial.h
new file mode 100644
index 000000000000..7226cf732b47
--- /dev/null
+++ b/arch/xtensa/platforms/xt2000/include/platform/serial.h
@@ -0,0 +1,28 @@
+/*
+ * platform/serial.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_XT2000_SERIAL_H
+#define _XTENSA_XT2000_SERIAL_H
+
+#include <variant/core.h>
+#include <asm/io.h>
+
+/*  National-Semi PC16552D DUART:  */
+
+#define DUART16552_1_INTNUM     XCHAL_EXTINT4_NUM
+#define DUART16552_2_INTNUM     XCHAL_EXTINT5_NUM
+
+#define DUART16552_1_ADDR       IOADDR(0x0d050020)      /* channel 1 */
+#define DUART16552_2_ADDR       IOADDR(0x0d050000)      /* channel 2 */
+
+#define DUART16552_XTAL_FREQ    18432000        /* crystal frequency in Hz */
+#define BASE_BAUD ( DUART16552_XTAL_FREQ / 16 )
+
+#endif /* _XTENSA_XT2000_SERIAL_H */
diff --git a/arch/xtensa/platforms/xt2000/setup.c b/arch/xtensa/platforms/xt2000/setup.c
new file mode 100644
index 000000000000..9e83940ac265
--- /dev/null
+++ b/arch/xtensa/platforms/xt2000/setup.c
@@ -0,0 +1,181 @@
+/*
+ * arch/xtensa/platforms/xt2000/setup.c
+ *
+ * Platform specific functions for the XT2000 board.
+ *
+ * Authors:     Chris Zankel <chris@zankel.net>
+ *              Joe Taylor <joe@tensilica.com>
+ *
+ * Copyright 2001 - 2004 Tensilica Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+
+#include <asm/processor.h>
+#include <asm/platform.h>
+#include <asm/bootparam.h>
+#include <platform/hardware.h>
+#include <platform/serial.h>
+
+/* Assumes s points to an 8-chr string.  No checking for NULL. */
+
+static void led_print (int f, char *s)
+{
+        unsigned long* led_addr = (unsigned long*) (XT2000_LED_ADDR + 0xE0) + f;
+        int i;
+        for (i = f; i < 8; i++)
+                if ((*led_addr++ = *s++) == 0)
+                    break;
+}
+
+void platform_halt(void)
+{
+        led_print (0, "  HALT  ");
+        local_irq_disable();
+        while (1);
+}
+
+void platform_power_off(void)
+{
+        led_print (0, "POWEROFF");
+        local_irq_disable();
+        while (1);
+}
+
+void platform_restart(void)
+{
+        /* Flush and reset the mmu, simulate a processor reset, and
+         * jump to the reset vector. */
+
+        __asm__ __volatile__ ("movi     a2, 15\n\t"
+                              "wsr      a2, " __stringify(ICOUNTLEVEL) "\n\t"
+                              "movi     a2, 0\n\t"
+                              "wsr      a2, " __stringify(ICOUNT) "\n\t"
+                              "wsr      a2, " __stringify(IBREAKENABLE) "\n\t"
+                              "wsr      a2, " __stringify(LCOUNT) "\n\t"
+                              "movi     a2, 0x1f\n\t"
+                              "wsr      a2, " __stringify(PS) "\n\t"
+                              "isync\n\t"
+                              "jx       %0\n\t"
+                              :
+                              : "a" (XCHAL_RESET_VECTOR_VADDR)
+                              : "a2"
+                              );
+
+        /* control never gets here */
+}
+
+void __init platform_setup(char** cmdline)
+{
+        led_print (0, "LINUX   ");
+}
+
+/* early initialization */
+
+extern sysmem_info_t __initdata sysmem;
+
+void platform_init(bp_tag_t* first)
+{
+        /* Set default memory block if not provided by the bootloader. */
+
+        if (sysmem.nr_banks == 0) {
+                sysmem.nr_banks = 1;
+                sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
+                sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
+                                     + PLATFORM_DEFAULT_MEM_SIZE;
+        }
+}
+
+/* Heartbeat. Let the LED blink. */
+
+void platform_heartbeat(void)
+{
+        static int i=0, t = 0;
+
+        if (--t < 0)
+        {
+                t = 59;
+                led_print(7, i ? ".": " ");
+                i ^= 1;
+        }
+}
+
+//#define RS_TABLE_SIZE 2
+//#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
+
+#define _SERIAL_PORT(_base,_irq)                                        \
+{                                                                       \
+        .mapbase        = (_base),                                      \
+        .membase        = (void*)(_base),                               \
+        .irq            = (_irq),                                       \
+        .uartclk        = DUART16552_XTAL_FREQ,                         \
+        .iotype         = UPIO_MEM,                                     \
+        .flags          = UPF_BOOT_AUTOCONF,                            \
+        .regshift       = 2,                                            \
+}
+
+static struct plat_serial8250_port xt2000_serial_data[] = {
+#if XCHAL_HAVE_BE
+        _SERIAL_PORT(DUART16552_1_ADDR + 3, DUART16552_1_INTNUM),
+        _SERIAL_PORT(DUART16552_2_ADDR + 3, DUART16552_2_INTNUM),
+#else
+        _SERIAL_PORT(DUART16552_1_ADDR, DUART16552_1_INTNUM),
+        _SERIAL_PORT(DUART16552_2_ADDR, DUART16552_2_INTNUM),
+#endif
+        { }
+};
+
+static struct platform_device xt2000_serial8250_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev            = {
+            .platform_data = xt2000_serial_data,
+        },
+};
+
+static struct resource xt2000_sonic_res[] = {
+        {
+                .start = SONIC83934_ADDR,
+                .end   = SONIC83934_ADDR + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = SONIC83934_INTNUM,
+                .end = SONIC83934_INTNUM,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device xt2000_sonic_device = {
+        .name           = "xtsonic",
+        .num_resources  = ARRAY_SIZE(xt2000_sonic_res),
+        .resource               = xt2000_sonic_res,
+};
+
+static int __init xt2000_setup_devinit(void)
+{
+        platform_device_register(&xt2000_serial8250_device);
+        platform_device_register(&xt2000_sonic_device);
+
+        return 0;
+}
+
+device_initcall(xt2000_setup_devinit);
diff --git a/include/asm-xtensa/variant-dc232b/core.h b/arch/xtensa/variants/dc232b/include/variant/core.h
index 525bd3d90154..525bd3d90154 100644
--- a/include/asm-xtensa/variant-dc232b/core.h
+++ b/arch/xtensa/variants/dc232b/include/variant/core.h
diff --git a/include/asm-xtensa/variant-dc232b/tie-asm.h b/arch/xtensa/variants/dc232b/include/variant/tie-asm.h
index ed4f53f529db..ed4f53f529db 100644
--- a/include/asm-xtensa/variant-dc232b/tie-asm.h
+++ b/arch/xtensa/variants/dc232b/include/variant/tie-asm.h
diff --git a/include/asm-xtensa/variant-dc232b/tie.h b/arch/xtensa/variants/dc232b/include/variant/tie.h
index 018e81af4393..018e81af4393 100644
--- a/include/asm-xtensa/variant-dc232b/tie.h
+++ b/arch/xtensa/variants/dc232b/include/variant/tie.h
diff --git a/include/asm-xtensa/variant-fsf/core.h b/arch/xtensa/variants/fsf/include/variant/core.h
index 2f337605c744..2f337605c744 100644
--- a/include/asm-xtensa/variant-fsf/core.h
+++ b/arch/xtensa/variants/fsf/include/variant/core.h
diff --git a/include/asm-xtensa/variant-fsf/tie-asm.h b/arch/xtensa/variants/fsf/include/variant/tie-asm.h
index 68a73bf4ffc5..68a73bf4ffc5 100644
--- a/include/asm-xtensa/variant-fsf/tie-asm.h
+++ b/arch/xtensa/variants/fsf/include/variant/tie-asm.h
diff --git a/include/asm-xtensa/variant-fsf/tie.h b/arch/xtensa/variants/fsf/include/variant/tie.h
index bf4020116df5..bf4020116df5 100644
--- a/include/asm-xtensa/variant-fsf/tie.h
+++ b/arch/xtensa/variants/fsf/include/variant/tie.h
diff --git a/drivers/Makefile b/drivers/Makefile
index fceb71a741c3..e121b66ef082 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_ATA_OVER_ETH)	+= block/aoe/
 obj-$(CONFIG_PARIDE)            += block/paride/
 obj-$(CONFIG_TC)                += tc/
 obj-$(CONFIG_UWB)               += uwb/
+obj-$(CONFIG_USB_OTG_UTILS)     += usb/otg/
 obj-$(CONFIG_USB)               += usb/
 obj-$(CONFIG_USB_MUSB_HDRC)     += usb/musb/
 obj-$(CONFIG_PCI)               += usb/
diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c
index 63a17b55b39b..7a0f4aa4fa1e 100644
--- a/drivers/acpi/acpi_memhotplug.c
+++ b/drivers/acpi/acpi_memhotplug.c
@@ -20,7 +20,7 @@
  *
  *
  * ACPI based HotPlug driver that supports Memory Hotplug
- * This driver fields notifications from firmare for memory add
+ * This driver fields notifications from firmware for memory add
  * and remove operations and alerts the VM of the affected memory
  * ranges.
  */
diff --git a/drivers/acpi/executer/exprep.c b/drivers/acpi/executer/exprep.c
index 5d438c32989d..a7dc87ecee37 100644
--- a/drivers/acpi/executer/exprep.c
+++ b/drivers/acpi/executer/exprep.c
@@ -404,7 +404,7 @@ acpi_ex_prep_common_field_object(union acpi_operand_object *obj_desc,
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Construct an union acpi_operand_object of type def_field and
+ * DESCRIPTION: Construct a union acpi_operand_object of type def_field and
  *              connect it to the parent Node.
  *
  ******************************************************************************/
diff --git a/drivers/acpi/executer/exresolv.c b/drivers/acpi/executer/exresolv.c
index 89571b92a522..60e8c47128e9 100644
--- a/drivers/acpi/executer/exresolv.c
+++ b/drivers/acpi/executer/exresolv.c
@@ -146,7 +146,7 @@ acpi_ex_resolve_object_to_value(union acpi_operand_object **stack_ptr,
 
         stack_desc = *stack_ptr;
 
-        /* This is an union acpi_operand_object    */
+        /* This is a union acpi_operand_object    */
 
         switch (ACPI_GET_OBJECT_TYPE(stack_desc)) {
         case ACPI_TYPE_LOCAL_REFERENCE:
diff --git a/drivers/acpi/executer/exstore.c b/drivers/acpi/executer/exstore.c
index 3318df4cbd98..1c118ba78adb 100644
--- a/drivers/acpi/executer/exstore.c
+++ b/drivers/acpi/executer/exstore.c
@@ -274,7 +274,7 @@ acpi_ex_do_debug_object(union acpi_operand_object *source_desc,
  *
  * PARAMETERS:  *source_desc        - Value to be stored
  *              *dest_desc          - Where to store it.  Must be an NS node
- *                                    or an union acpi_operand_object of type
+ *                                    or a union acpi_operand_object of type
  *                                    Reference;
  *              walk_state          - Current walk state
  *
diff --git a/drivers/acpi/resources/rscreate.c b/drivers/acpi/resources/rscreate.c
index c0bbfa2c4193..08b8d73e6ee5 100644
--- a/drivers/acpi/resources/rscreate.c
+++ b/drivers/acpi/resources/rscreate.c
@@ -124,7 +124,7 @@ acpi_rs_create_resource_list(union acpi_operand_object *aml_buffer,
  *
  * FUNCTION:    acpi_rs_create_pci_routing_table
  *
- * PARAMETERS:  package_object          - Pointer to an union acpi_operand_object
+ * PARAMETERS:  package_object          - Pointer to a union acpi_operand_object
  *                                        package
  *              output_buffer           - Pointer to the user's buffer
  *
diff --git a/drivers/acpi/utilities/utobject.c b/drivers/acpi/utilities/utobject.c
index c354e7a42bcd..4bef3cfbaccb 100644
--- a/drivers/acpi/utilities/utobject.c
+++ b/drivers/acpi/utilities/utobject.c
@@ -297,7 +297,7 @@ union acpi_operand_object *acpi_ut_create_string_object(acpi_size string_size)
  *
  * RETURN:      TRUE if object is valid, FALSE otherwise
  *
- * DESCRIPTION: Validate a pointer to be an union acpi_operand_object
+ * DESCRIPTION: Validate a pointer to be a union acpi_operand_object
  *
  ******************************************************************************/
 
@@ -389,7 +389,7 @@ void acpi_ut_delete_object_desc(union acpi_operand_object *object)
 {
         ACPI_FUNCTION_TRACE_PTR(ut_delete_object_desc, object);
 
-        /* Object must be an union acpi_operand_object    */
+        /* Object must be a union acpi_operand_object    */
 
         if (ACPI_GET_DESCRIPTOR_TYPE(object) != ACPI_DESC_TYPE_OPERAND) {
                 ACPI_ERROR((AE_INFO,
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index fecca4223f8e..f178a450ec08 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -56,6 +56,7 @@
 #include <linux/workqueue.h>
 #include <linux/scatterlist.h>
 #include <linux/io.h>
+#include <linux/async.h>
 #include <scsi/scsi.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_host.h>
@@ -5909,6 +5910,54 @@ void ata_host_init(struct ata_host *host, struct device *dev,
         host->ops = ops;
 }
 
+
+static void async_port_probe(void *data, async_cookie_t cookie)
+{
+        int rc;
+        struct ata_port *ap = data;
+        /* probe */
+        if (ap->ops->error_handler) {
+                struct ata_eh_info *ehi = &ap->link.eh_info;
+                unsigned long flags;
+
+                ata_port_probe(ap);
+
+                /* kick EH for boot probing */
+                spin_lock_irqsave(ap->lock, flags);
+
+                ehi->probe_mask |= ATA_ALL_DEVICES;
+                ehi->action |= ATA_EH_RESET | ATA_EH_LPM;
+                ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
+
+                ap->pflags &= ~ATA_PFLAG_INITIALIZING;
+                ap->pflags |= ATA_PFLAG_LOADING;
+                ata_port_schedule_eh(ap);
+
+                spin_unlock_irqrestore(ap->lock, flags);
+
+                /* wait for EH to finish */
+                ata_port_wait_eh(ap);
+        } else {
+                DPRINTK("ata%u: bus probe begin\n", ap->print_id);
+                rc = ata_bus_probe(ap);
+                DPRINTK("ata%u: bus probe end\n", ap->print_id);
+
+                if (rc) {
+                        /* FIXME: do something useful here?
+                         * Current libata behavior will
+                         * tear down everything when
+                         * the module is removed
+                         * or the h/w is unplugged.
+                         */
+                }
+        }
+
+        /* in order to keep device order, we need to synchronize at this point */
+        async_synchronize_cookie(cookie);
+
+        ata_scsi_scan_host(ap, 1);
+
+}
 /**
  *      ata_host_register - register initialized ATA host
  *      @host: ATA host to register
@@ -5988,52 +6037,9 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht)
         DPRINTK("probe begin\n");
         for (i = 0; i < host->n_ports; i++) {
                 struct ata_port *ap = host->ports[i];
-
-                /* probe */
-                if (ap->ops->error_handler) {
-                        struct ata_eh_info *ehi = &ap->link.eh_info;
-                        unsigned long flags;
-
-                        ata_port_probe(ap);
-
-                        /* kick EH for boot probing */
-                        spin_lock_irqsave(ap->lock, flags);
-
-                        ehi->probe_mask |= ATA_ALL_DEVICES;
-                        ehi->action |= ATA_EH_RESET | ATA_EH_LPM;
-                        ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
-
-                        ap->pflags &= ~ATA_PFLAG_INITIALIZING;
-                        ap->pflags |= ATA_PFLAG_LOADING;
-                        ata_port_schedule_eh(ap);
-
-                        spin_unlock_irqrestore(ap->lock, flags);
-
-                        /* wait for EH to finish */
-                        ata_port_wait_eh(ap);
-                } else {
-                        DPRINTK("ata%u: bus probe begin\n", ap->print_id);
-                        rc = ata_bus_probe(ap);
-                        DPRINTK("ata%u: bus probe end\n", ap->print_id);
-
-                        if (rc) {
-                                /* FIXME: do something useful here?
-                                 * Current libata behavior will
-                                 * tear down everything when
-                                 * the module is removed
-                                 * or the h/w is unplugged.
-                                 */
-                        }
-                }
-        }
-
-        /* probes are done, now scan each port's disk(s) */
-        DPRINTK("host probe begin\n");
-        for (i = 0; i < host->n_ports; i++) {
-                struct ata_port *ap = host->ports[i];
-
-                ata_scsi_scan_host(ap, 1);
+                async_schedule(async_port_probe, ap);
         }
+        DPRINTK("probe end\n");
 
         return 0;
 }
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index d8e8c49c0cbd..8f006f96ff53 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -54,7 +54,7 @@ config FIRMWARE_IN_KERNEL
           such firmware, and do not wish to use an initrd.
 
           This single option controls the inclusion of firmware for
-          every driver which uses request_firmare() and ships its
+          every driver which uses request_firmware() and ships its
           firmware in the kernel source tree, to avoid a proliferation
           of 'Include firmware for xxx device' options.
 
diff --git a/drivers/base/topology.c b/drivers/base/topology.c
index a8bc1cbcfa7c..a778fb52b11f 100644
--- a/drivers/base/topology.c
+++ b/drivers/base/topology.c
@@ -28,6 +28,7 @@
 #include <linux/mm.h>
 #include <linux/cpu.h>
 #include <linux/module.h>
+#include <linux/hardirq.h>
 #include <linux/topology.h>
 
 #define define_one_ro(_name)            \
diff --git a/drivers/block/ub.c b/drivers/block/ub.c
index 048d71d244d7..12fb816db7b0 100644
--- a/drivers/block/ub.c
+++ b/drivers/block/ub.c
@@ -1579,7 +1579,7 @@ static void ub_reset_task(struct work_struct *work)
         struct ub_dev *sc = container_of(work, struct ub_dev, reset_work);
         unsigned long flags;
         struct ub_lun *lun;
-        int lkr, rc;
+        int rc;
 
         if (!sc->reset) {
                 printk(KERN_WARNING "%s: Running reset unrequested\n",
@@ -1597,10 +1597,11 @@ static void ub_reset_task(struct work_struct *work)
         } else if (sc->dev->actconfig->desc.bNumInterfaces != 1) {
                 ;
         } else {
-                if ((lkr = usb_lock_device_for_reset(sc->dev, sc->intf)) < 0) {
+                rc = usb_lock_device_for_reset(sc->dev, sc->intf);
+                if (rc < 0) {
                         printk(KERN_NOTICE
                             "%s: usb_lock_device_for_reset failed (%d)\n",
-                            sc->name, lkr);
+                            sc->name, rc);
                 } else {
                         rc = usb_reset_device(sc->dev);
                         if (rc < 0) {
@@ -1608,9 +1609,7 @@ static void ub_reset_task(struct work_struct *work)
                                     "usb_lock_device_for_reset failed (%d)\n",
                                     sc->name, rc);
                         }
-
-                        if (lkr)
-                                usb_unlock_device(sc->dev);
+                        usb_unlock_device(sc->dev);
                 }
         }
 
diff --git a/drivers/char/epca.c b/drivers/char/epca.c
index 39ad820b2350..af7c13ca9493 100644
--- a/drivers/char/epca.c
+++ b/drivers/char/epca.c
@@ -769,7 +769,7 @@ static int pc_open(struct tty_struct *tty, struct file *filp)
         /* Check status of board configured in system.  */
 
         /*
-         * I check to see if the epca_setup routine detected an user error. It
+         * I check to see if the epca_setup routine detected a user error. It
          * might be better to put this in pc_init, but for the moment it goes
          * here.
          */
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 5f076aef74fa..a8c8d9c19d74 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -83,7 +83,7 @@ config CPU_FREQ_DEFAULT_GOV_USERSPACE
         select CPU_FREQ_GOV_USERSPACE
         help
           Use the CPUFreq governor 'userspace' as default. This allows
-          you to set the CPU frequency manually or when an userspace 
+          you to set the CPU frequency manually or when a userspace 
           program shall be able to set the CPU dynamically without having
           to enable the userspace governor manually.
 
@@ -138,7 +138,7 @@ config CPU_FREQ_GOV_USERSPACE
         tristate "'userspace' governor for userspace frequency scaling"
         help
           Enable this cpufreq governor when you either want to set the
-          CPU frequency manually or when an userspace program shall
+          CPU frequency manually or when a userspace program shall
           be able to set the CPU dynamically, like on LART 
           <http://www.lartmaker.nl/>.
 
diff --git a/drivers/firewire/fw-card.c b/drivers/firewire/fw-card.c
index 418c18f07e9d..799f94424c8a 100644
--- a/drivers/firewire/fw-card.c
+++ b/drivers/firewire/fw-card.c
@@ -75,7 +75,7 @@ generate_config_rom(struct fw_card *card, size_t *config_rom_length)
          * controller, block reads to the config rom accesses the host
          * memory, but quadlet read access the hardware bus info block
          * registers.  That's just crack, but it means we should make
-         * sure the contents of bus info block in host memory mathces
+         * sure the contents of bus info block in host memory matches
          * the version stored in the OHCI registers.
          */
 
@@ -189,6 +189,17 @@ static const char gap_count_table[] = {
         63, 5, 7, 8, 10, 13, 16, 18, 21, 24, 26, 29, 32, 35, 37, 40
 };
 
+void
+fw_schedule_bm_work(struct fw_card *card, unsigned long delay)
+{
+        int scheduled;
+
+        fw_card_get(card);
+        scheduled = schedule_delayed_work(&card->work, delay);
+        if (!scheduled)
+                fw_card_put(card);
+}
+
 static void
 fw_card_bm_work(struct work_struct *work)
 {
@@ -206,7 +217,7 @@ fw_card_bm_work(struct work_struct *work)
 
         if (local_node == NULL) {
                 spin_unlock_irqrestore(&card->lock, flags);
-                return;
+                goto out_put_card;
         }
         fw_node_get(local_node);
         fw_node_get(root_node);
@@ -280,7 +291,7 @@ fw_card_bm_work(struct work_struct *work)
                  * this task 100ms from now.
                  */
                 spin_unlock_irqrestore(&card->lock, flags);
-                schedule_delayed_work(&card->work, DIV_ROUND_UP(HZ, 10));
+                fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 10));
                 goto out;
         }
 
@@ -355,6 +366,8 @@ fw_card_bm_work(struct work_struct *work)
                 fw_device_put(root_device);
         fw_node_put(root_node);
         fw_node_put(local_node);
+ out_put_card:
+        fw_card_put(card);
 }
 
 static void
@@ -510,7 +523,6 @@ fw_core_remove_card(struct fw_card *card)
         fw_card_put(card);
         wait_for_completion(&card->done);
 
-        cancel_delayed_work_sync(&card->work);
         WARN_ON(!list_empty(&card->transaction_list));
         del_timer_sync(&card->flush_timer);
 }
diff --git a/drivers/firewire/fw-device.c b/drivers/firewire/fw-device.c
index 6b9be42c7b98..c173be383725 100644
--- a/drivers/firewire/fw-device.c
+++ b/drivers/firewire/fw-device.c
@@ -617,7 +617,7 @@ static int shutdown_unit(struct device *device, void *data)
  */
 DECLARE_RWSEM(fw_device_rwsem);
 
-static DEFINE_IDR(fw_device_idr);
+DEFINE_IDR(fw_device_idr);
 int fw_cdev_major;
 
 struct fw_device *fw_device_get_by_devt(dev_t devt)
@@ -689,7 +689,7 @@ static void fw_device_init(struct work_struct *work)
                         fw_notify("giving up on config rom for node id %x\n",
                                   device->node_id);
                         if (device->node == device->card->root_node)
-                                schedule_delayed_work(&device->card->work, 0);
+                                fw_schedule_bm_work(device->card, 0);
                         fw_device_release(&device->device);
                 }
                 return;
@@ -758,7 +758,7 @@ static void fw_device_init(struct work_struct *work)
          * pretty harmless.
          */
         if (device->node == device->card->root_node)
-                schedule_delayed_work(&device->card->work, 0);
+                fw_schedule_bm_work(device->card, 0);
 
         return;
 
@@ -892,7 +892,7 @@ static void fw_device_refresh(struct work_struct *work)
         fw_device_shutdown(work);
  out:
         if (node_id == card->root_node->node_id)
-                schedule_delayed_work(&card->work, 0);
+                fw_schedule_bm_work(card, 0);
 }
 
 void fw_node_event(struct fw_card *card, struct fw_node *node, int event)
diff --git a/drivers/firewire/fw-device.h b/drivers/firewire/fw-device.h
index 42305bbac72f..df51732608d9 100644
--- a/drivers/firewire/fw-device.h
+++ b/drivers/firewire/fw-device.h
@@ -21,6 +21,7 @@
 
 #include <linux/fs.h>
 #include <linux/cdev.h>
+#include <linux/idr.h>
 #include <linux/rwsem.h>
 #include <asm/atomic.h>
 
@@ -99,6 +100,7 @@ void fw_device_cdev_update(struct fw_device *device);
 void fw_device_cdev_remove(struct fw_device *device);
 
 extern struct rw_semaphore fw_device_rwsem;
+extern struct idr fw_device_idr;
 extern int fw_cdev_major;
 
 /*
diff --git a/drivers/firewire/fw-sbp2.c b/drivers/firewire/fw-sbp2.c
index e54403ee59e7..e88d5067448c 100644
--- a/drivers/firewire/fw-sbp2.c
+++ b/drivers/firewire/fw-sbp2.c
@@ -670,17 +670,6 @@ static void sbp2_agent_reset_no_wait(struct sbp2_logical_unit *lu)
                         &d, sizeof(d), complete_agent_reset_write_no_wait, t);
 }
 
-static void sbp2_set_generation(struct sbp2_logical_unit *lu, int generation)
-{
-        struct fw_card *card = fw_device(lu->tgt->unit->device.parent)->card;
-        unsigned long flags;
-
-        /* serialize with comparisons of lu->generation and card->generation */
-        spin_lock_irqsave(&card->lock, flags);
-        lu->generation = generation;
-        spin_unlock_irqrestore(&card->lock, flags);
-}
-
 static inline void sbp2_allow_block(struct sbp2_logical_unit *lu)
 {
         /*
@@ -884,7 +873,7 @@ static void sbp2_login(struct work_struct *work)
                 goto out;
 
         generation    = device->generation;
-        smp_rmb();    /* node_id must not be older than generation */
+        smp_rmb();    /* node IDs must not be older than generation */
         node_id       = device->node_id;
         local_node_id = device->card->node_id;
 
@@ -908,7 +897,8 @@ static void sbp2_login(struct work_struct *work)
 
         tgt->node_id      = node_id;
         tgt->address_high = local_node_id << 16;
-        sbp2_set_generation(lu, generation);
+        smp_wmb();        /* node IDs must not be older than generation */
+        lu->generation    = generation;
 
         lu->command_block_agent_address =
                 ((u64)(be32_to_cpu(response.command_block_agent.high) & 0xffff)
@@ -1201,7 +1191,7 @@ static void sbp2_reconnect(struct work_struct *work)
                 goto out;
 
         generation    = device->generation;
-        smp_rmb();    /* node_id must not be older than generation */
+        smp_rmb();    /* node IDs must not be older than generation */
         node_id       = device->node_id;
         local_node_id = device->card->node_id;
 
@@ -1228,7 +1218,8 @@ static void sbp2_reconnect(struct work_struct *work)
 
         tgt->node_id      = node_id;
         tgt->address_high = local_node_id << 16;
-        sbp2_set_generation(lu, generation);
+        smp_wmb();        /* node IDs must not be older than generation */
+        lu->generation    = generation;
 
         fw_notify("%s: reconnected to LUN %04x (%d retries)\n",
                   tgt->bus_id, lu->lun, lu->retries);
diff --git a/drivers/firewire/fw-topology.c b/drivers/firewire/fw-topology.c
index 5e204713002d..c9be6e6948c4 100644
--- a/drivers/firewire/fw-topology.c
+++ b/drivers/firewire/fw-topology.c
@@ -355,6 +355,9 @@ report_lost_node(struct fw_card *card,
 {
         fw_node_event(card, node, FW_NODE_DESTROYED);
         fw_node_put(node);
+
+        /* Topology has changed - reset bus manager retry counter */
+        card->bm_retries = 0;
 }
 
 static void
@@ -374,6 +377,9 @@ report_found_node(struct fw_card *card,
         }
 
         fw_node_event(card, node, FW_NODE_CREATED);
+
+        /* Topology has changed - reset bus manager retry counter */
+        card->bm_retries = 0;
 }
 
 void fw_destroy_nodes(struct fw_card *card)
@@ -514,14 +520,6 @@ fw_core_handle_bus_reset(struct fw_card *card,
 
         spin_lock_irqsave(&card->lock, flags);
 
-        /*
-         * If the new topology has a different self_id_count the topology
-         * changed, either nodes were added or removed. In that case we
-         * reset the IRM reset counter.
-         */
-        if (card->self_id_count != self_id_count)
-                card->bm_retries = 0;
-
         card->node_id = node_id;
         /*
          * Update node_id before generation to prevent anybody from using
@@ -530,7 +528,7 @@ fw_core_handle_bus_reset(struct fw_card *card,
         smp_wmb();
         card->generation = generation;
         card->reset_jiffies = jiffies;
-        schedule_delayed_work(&card->work, 0);
+        fw_schedule_bm_work(card, 0);
 
         local_node = build_tree(card, self_ids, self_id_count);
 
diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/fw-transaction.c
index 2884f876397b..699ac041f39a 100644
--- a/drivers/firewire/fw-transaction.c
+++ b/drivers/firewire/fw-transaction.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/completion.h>
+#include <linux/idr.h>
 #include <linux/kernel.h>
 #include <linux/kref.h>
 #include <linux/module.h>
@@ -971,6 +972,7 @@ static void __exit fw_core_cleanup(void)
 {
         unregister_chrdev(fw_cdev_major, "firewire");
         bus_unregister(&fw_bus_type);
+        idr_destroy(&fw_device_idr);
 }
 
 module_init(fw_core_init);
diff --git a/drivers/firewire/fw-transaction.h b/drivers/firewire/fw-transaction.h
index 839466f0a795..c9ab12a15f6e 100644
--- a/drivers/firewire/fw-transaction.h
+++ b/drivers/firewire/fw-transaction.h
@@ -237,14 +237,6 @@ struct fw_card {
         int link_speed;
         int config_rom_generation;
 
-        /*
-         * We need to store up to 4 self ID for a maximum of 63
-         * devices plus 3 words for the topology map header.
-         */
-        int self_id_count;
-        u32 topology_map[252 + 3];
-        u32 broadcast_channel;
-
         spinlock_t lock; /* Take this lock when handling the lists in
                           * this struct. */
         struct fw_node *local_node;
@@ -262,6 +254,9 @@ struct fw_card {
         struct delayed_work work;
         int bm_retries;
         int bm_generation;
+
+        u32 broadcast_channel;
+        u32 topology_map[(CSR_TOPOLOGY_MAP_END - CSR_TOPOLOGY_MAP) / 4];
 };
 
 static inline struct fw_card *fw_card_get(struct fw_card *card)
@@ -278,6 +273,8 @@ static inline void fw_card_put(struct fw_card *card)
         kref_put(&card->kref, fw_card_release);
 }
 
+extern void fw_schedule_bm_work(struct fw_card *card, unsigned long delay);
+
 /*
  * The iso packet format allows for an immediate header/payload part
  * stored in 'header' immediately after the packet info plus an
diff --git a/drivers/hid/usbhid/hid-core.c b/drivers/hid/usbhid/hid-core.c
index 03cb494af1c5..f0a0f72238ab 100644
--- a/drivers/hid/usbhid/hid-core.c
+++ b/drivers/hid/usbhid/hid-core.c
@@ -102,7 +102,7 @@ static void hid_reset(struct work_struct *work)
         struct usbhid_device *usbhid =
                 container_of(work, struct usbhid_device, reset_work);
         struct hid_device *hid = usbhid->hid;
-        int rc_lock, rc = 0;
+        int rc = 0;
 
         if (test_bit(HID_CLEAR_HALT, &usbhid->iofl)) {
                 dev_dbg(&usbhid->intf->dev, "clear halt\n");
@@ -113,11 +113,10 @@ static void hid_reset(struct work_struct *work)
 
         else if (test_bit(HID_RESET_PENDING, &usbhid->iofl)) {
                 dev_dbg(&usbhid->intf->dev, "resetting device\n");
-                rc = rc_lock = usb_lock_device_for_reset(hid_to_usb_dev(hid), usbhid->intf);
-                if (rc_lock >= 0) {
+                rc = usb_lock_device_for_reset(hid_to_usb_dev(hid), usbhid->intf);
+                if (rc == 0) {
                         rc = usb_reset_device(hid_to_usb_dev(hid));
-                        if (rc_lock)
-                                usb_unlock_device(hid_to_usb_dev(hid));
+                        usb_unlock_device(hid_to_usb_dev(hid));
                 }
                 clear_bit(HID_RESET_PENDING, &usbhid->iofl);
         }
diff --git a/drivers/hid/usbhid/hiddev.c b/drivers/hid/usbhid/hiddev.c
index 6a98f9f572b0..d73eea382ab3 100644
--- a/drivers/hid/usbhid/hiddev.c
+++ b/drivers/hid/usbhid/hiddev.c
@@ -874,12 +874,14 @@ int hiddev_connect(struct hid_device *hid, unsigned int force)
         INIT_LIST_HEAD(&hiddev->list);
         spin_lock_init(&hiddev->list_lock);
         mutex_init(&hiddev->existancelock);
+        hid->hiddev = hiddev;
         hiddev->hid = hid;
         hiddev->exist = 1;
 
         retval = usb_register_dev(usbhid->intf, &hiddev_class);
         if (retval) {
                 err_hid("Not able to get a minor for this device.");
+                hid->hiddev = NULL;
                 kfree(hiddev);
                 return -1;
         } else {
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index c709e821f04b..4b33bc82cc24 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -284,11 +284,12 @@ config SENSORS_F71805F
           will be called f71805f.
 
 config SENSORS_F71882FG
-        tristate "Fintek F71882FG and F71883FG"
+        tristate "Fintek F71862FG, F71882FG and F8000"
         depends on EXPERIMENTAL
         help
           If you say yes here you get support for hardware monitoring
-          features of the Fintek F71882FG and F71883FG Super-I/O chips.
+          features of the Fintek F71882FG/F71883FG, F71862FG/71863FG
+          and F8000 Super-I/O chips.
 
           This driver can also be built as a module.  If so, the module
           will be called f71882fg.
@@ -304,9 +305,13 @@ config SENSORS_F75375S
           will be called f75375s.
 
 config SENSORS_FSCHER
-        tristate "FSC Hermes"
+        tristate "FSC Hermes (DEPRECATED)"
         depends on X86 && I2C
         help
+          This driver is DEPRECATED please use the new merged fschmd
+          ("FSC Poseidon, Scylla, Hermes, Heimdall and Heracles") driver
+          instead.
+
           If you say yes here you get support for Fujitsu Siemens
           Computers Hermes sensor chips.
 
@@ -314,9 +319,13 @@ config SENSORS_FSCHER
           will be called fscher.
 
 config SENSORS_FSCPOS
-        tristate "FSC Poseidon"
+        tristate "FSC Poseidon (DEPRECATED)"
         depends on X86 && I2C
         help
+          This driver is DEPRECATED please use the new merged fschmd
+          ("FSC Poseidon, Scylla, Hermes, Heimdall and Heracles") driver
+          instead.
+
           If you say yes here you get support for Fujitsu Siemens
           Computers Poseidon sensor chips.
 
@@ -325,14 +334,15 @@ config SENSORS_FSCPOS
 
 config SENSORS_FSCHMD
         tristate "FSC Poseidon, Scylla, Hermes, Heimdall and Heracles"
-        depends on X86 && I2C && EXPERIMENTAL
+        depends on X86 && I2C
         help
           If you say yes here you get support for various Fujitsu Siemens
-          Computers sensor chips.
+          Computers sensor chips, including support for the integrated
+          watchdog.
 
-          This is a new merged driver for FSC sensor chips which is intended
-          as a replacment for the fscpos, fscscy and fscher drivers and adds
-          support for several other FCS sensor chips.
+          This is a merged driver for FSC sensor chips replacing the fscpos,
+          fscscy and fscher drivers and adding support for several other FSC
+          sensor chips.
 
           This driver can also be built as a module.  If so, the module
           will be called fschmd.
@@ -399,7 +409,8 @@ config SENSORS_IT87
         select HWMON_VID
         help
           If you say yes here you get support for ITE IT8705F, IT8712F,
-          IT8716F, IT8718F and IT8726F sensor chips, and the SiS960 clone.
+          IT8716F, IT8718F, IT8720F and IT8726F sensor chips, and the
+          SiS960 clone.
 
           This driver can also be built as a module.  If so, the module
           will be called it87.
@@ -417,11 +428,12 @@ config SENSORS_LM63
           will be called lm63.
 
 config SENSORS_LM70
-        tristate "National Semiconductor LM70"
+        tristate "National Semiconductor LM70 / Texas Instruments TMP121"
         depends on SPI_MASTER && EXPERIMENTAL
         help
           If you say yes here you get support for the National Semiconductor
-          LM70 digital temperature sensor chip.
+          LM70 and Texas Instruments TMP121/TMP123 digital temperature
+          sensor chips.
 
           This driver can also be built as a module.  If so, the module
           will be called lm70.
@@ -548,6 +560,17 @@ config SENSORS_LM93
           This driver can also be built as a module.  If so, the module
           will be called lm93.
 
+config SENSORS_LTC4245
+        tristate "Linear Technology LTC4245"
+        depends on I2C && EXPERIMENTAL
+        default n
+        help
+          If you say yes here you get support for Linear Technology LTC4245
+          Multiple Supply Hot Swap Controller I2C interface.
+
+          This driver can also be built as a module. If so, the module will
+          be called ltc4245.
+
 config SENSORS_MAX1111
         tristate "Maxim MAX1111 Multichannel, Serial 8-bit ADC chip"
         depends on SPI_MASTER
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 58fc5be5355d..8fd124eff646 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_SENSORS_LM87)	+= lm87.o
 obj-$(CONFIG_SENSORS_LM90)      += lm90.o
 obj-$(CONFIG_SENSORS_LM92)      += lm92.o
 obj-$(CONFIG_SENSORS_LM93)      += lm93.o
+obj-$(CONFIG_SENSORS_LTC4245)   += ltc4245.o
 obj-$(CONFIG_SENSORS_MAX1111)   += max1111.o
 obj-$(CONFIG_SENSORS_MAX1619)   += max1619.o
 obj-$(CONFIG_SENSORS_MAX6650)   += max6650.o
diff --git a/drivers/hwmon/asb100.c b/drivers/hwmon/asb100.c
index 8a45a2e6ba8a..8acf82977e7b 100644
--- a/drivers/hwmon/asb100.c
+++ b/drivers/hwmon/asb100.c
@@ -53,7 +53,10 @@ static const unsigned short normal_i2c[] = { 0x2d, I2C_CLIENT_END };
 
 /* Insmod parameters */
 I2C_CLIENT_INSMOD_1(asb100);
-I2C_CLIENT_MODULE_PARM(force_subclients, "List of subclient addresses: "
+
+static unsigned short force_subclients[4];
+module_param_array(force_subclients, short, NULL, 0);
+MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
         "{bus, clientaddr, subclientaddr1, subclientaddr2}");
 
 /* Voltage IN registers 0-6 */
diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c
index 27a5d397f9a1..3df202a9ad72 100644
--- a/drivers/hwmon/dme1737.c
+++ b/drivers/hwmon/dme1737.c
@@ -34,6 +34,7 @@
 #include <linux/hwmon-vid.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 /* ISA device, if found */
@@ -2361,6 +2362,10 @@ static int __init dme1737_isa_device_add(unsigned short addr)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         if (!(pdev = platform_device_alloc("dme1737", addr))) {
                 printk(KERN_ERR "dme1737: Failed to allocate device.\n");
                 err = -ENOMEM;
diff --git a/drivers/hwmon/f71805f.c b/drivers/hwmon/f71805f.c
index 7a14a2dbb752..899876579253 100644
--- a/drivers/hwmon/f71805f.c
+++ b/drivers/hwmon/f71805f.c
@@ -39,6 +39,7 @@
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
 #include <linux/ioport.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static unsigned short force_id;
@@ -1455,6 +1456,10 @@ static int __init f71805f_device_add(unsigned short address,
         }
 
         res.name = pdev->name;
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit_device_put;
+
         err = platform_device_add_resources(pdev, &res, 1);
         if (err) {
                 printk(KERN_ERR DRVNAME ": Device resource addition failed "
diff --git a/drivers/hwmon/f71882fg.c b/drivers/hwmon/f71882fg.c
index 67067e9a323e..609cafff86bc 100644
--- a/drivers/hwmon/f71882fg.c
+++ b/drivers/hwmon/f71882fg.c
@@ -1,6 +1,6 @@
 /***************************************************************************
  *   Copyright (C) 2006 by Hans Edgington <hans@edgington.nl>              *
- *   Copyright (C) 2007 by Hans de Goede  <j.w.r.degoede@hhs.nl>           *
+ *   Copyright (C) 2007,2008 by Hans de Goede <hdegoede@redhat.com>        *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
@@ -27,11 +27,12 @@
 #include <linux/hwmon-sysfs.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/acpi.h>
 
 #define DRVNAME "f71882fg"
 
-#define SIO_F71882FG_LD_HWM     0x04    /* Hardware monitor logical device*/
+#define SIO_F71882FG_LD_HWM     0x04    /* Hardware monitor logical device */
 #define SIO_UNLOCK_KEY          0x87    /* Key to enable Super-I/O */
 #define SIO_LOCK_KEY            0xAA    /* Key to diasble Super-I/O */
 
@@ -43,7 +44,9 @@
 #define SIO_REG_ADDR            0x60    /* Logical device address (2 bytes) */
 
 #define SIO_FINTEK_ID           0x1934  /* Manufacturers ID */
+#define SIO_F71862_ID           0x0601  /* Chipset ID */
 #define SIO_F71882_ID           0x0541  /* Chipset ID */
+#define SIO_F8000_ID            0x0581  /* Chipset ID */
 
 #define REGION_LENGTH           8
 #define ADDR_REG_OFFSET         5
@@ -51,25 +54,36 @@
 
 #define F71882FG_REG_PECI               0x0A
 
-#define F71882FG_REG_IN_STATUS          0x12
-#define F71882FG_REG_IN_BEEP            0x13
+#define F71882FG_REG_IN_STATUS          0x12 /* f71882fg only */
+#define F71882FG_REG_IN_BEEP            0x13 /* f71882fg only */
 #define F71882FG_REG_IN(nr)             (0x20  + (nr))
-#define F71882FG_REG_IN1_HIGH           0x32
+#define F71882FG_REG_IN1_HIGH           0x32 /* f71882fg only */
 
 #define F71882FG_REG_FAN(nr)            (0xA0 + (16 * (nr)))
+#define F71882FG_REG_FAN_TARGET(nr)     (0xA2 + (16 * (nr)))
+#define F71882FG_REG_FAN_FULL_SPEED(nr) (0xA4 + (16 * (nr)))
 #define F71882FG_REG_FAN_STATUS         0x92
 #define F71882FG_REG_FAN_BEEP           0x93
 
-#define F71882FG_REG_TEMP(nr)           (0x72 + 2 * (nr))
-#define F71882FG_REG_TEMP_OVT(nr)       (0x82 + 2 * (nr))
-#define F71882FG_REG_TEMP_HIGH(nr)      (0x83 + 2 * (nr))
+#define F71882FG_REG_TEMP(nr)           (0x70 + 2 * (nr))
+#define F71882FG_REG_TEMP_OVT(nr)       (0x80 + 2 * (nr))
+#define F71882FG_REG_TEMP_HIGH(nr)      (0x81 + 2 * (nr))
 #define F71882FG_REG_TEMP_STATUS        0x62
 #define F71882FG_REG_TEMP_BEEP          0x63
-#define F71882FG_REG_TEMP_HYST1         0x6C
-#define F71882FG_REG_TEMP_HYST23        0x6D
+#define F71882FG_REG_TEMP_HYST(nr)      (0x6C + (nr))
 #define F71882FG_REG_TEMP_TYPE          0x6B
 #define F71882FG_REG_TEMP_DIODE_OPEN    0x6F
 
+#define F71882FG_REG_PWM(nr)            (0xA3 + (16 * (nr)))
+#define F71882FG_REG_PWM_TYPE           0x94
+#define F71882FG_REG_PWM_ENABLE         0x96
+
+#define F71882FG_REG_FAN_HYST(nr)       (0x98 + (nr))
+
+#define F71882FG_REG_POINT_PWM(pwm, point)      (0xAA + (point) + (16 * (pwm)))
+#define F71882FG_REG_POINT_TEMP(pwm, point)     (0xA6 + (point) + (16 * (pwm)))
+#define F71882FG_REG_POINT_MAPPING(nr)          (0xAF + 16 * (nr))
+
 #define F71882FG_REG_START              0x01
 
 #define FAN_MIN_DETECT                  366 /* Lowest detectable fanspeed */
@@ -78,7 +92,15 @@ static unsigned short force_id;
 module_param(force_id, ushort, 0);
 MODULE_PARM_DESC(force_id, "Override the detected device ID");
 
-static struct platform_device *f71882fg_pdev = NULL;
+enum chips { f71862fg, f71882fg, f8000 };
+
+static const char *f71882fg_names[] = {
+        "f71862fg",
+        "f71882fg",
+        "f8000",
+};
+
+static struct platform_device *f71882fg_pdev;
 
 /* Super-I/O Function prototypes */
 static inline int superio_inb(int base, int reg);
@@ -87,8 +109,13 @@ static inline void superio_enter(int base);
 static inline void superio_select(int base, int ld);
 static inline void superio_exit(int base);
 
+struct f71882fg_sio_data {
+        enum chips type;
+};
+
 struct f71882fg_data {
         unsigned short addr;
+        enum chips type;
         struct device *hwmon_dev;
 
         struct mutex update_lock;
@@ -102,19 +129,30 @@ struct f71882fg_data {
         u8      in_status;
         u8      in_beep;
         u16     fan[4];
+        u16     fan_target[4];
+        u16     fan_full_speed[4];
         u8      fan_status;
         u8      fan_beep;
-        u8      temp[3];
-        u8      temp_ovt[3];
-        u8      temp_high[3];
-        u8      temp_hyst[3];
-        u8      temp_type[3];
+        /* Note: all models have only 3 temperature channels, but on some
+           they are addressed as 0-2 and on others as 1-3, so for coding
+           convenience we reserve space for 4 channels */
+        u8      temp[4];
+        u8      temp_ovt[4];
+        u8      temp_high[4];
+        u8      temp_hyst[2]; /* 2 hysts stored per reg */
+        u8      temp_type[4];
         u8      temp_status;
         u8      temp_beep;
         u8      temp_diode_open;
+        u8      pwm[4];
+        u8      pwm_enable;
+        u8      pwm_auto_point_hyst[2];
+        u8      pwm_auto_point_mapping[4];
+        u8      pwm_auto_point_pwm[4][5];
+        u8      pwm_auto_point_temp[4][4];
 };
 
-/* Sysfs in*/
+/* Sysfs in */
 static ssize_t show_in(struct device *dev, struct device_attribute *devattr,
         char *buf);
 static ssize_t show_in_max(struct device *dev, struct device_attribute
@@ -130,6 +168,10 @@ static ssize_t show_in_alarm(struct device *dev, struct device_attribute
 /* Sysfs Fan */
 static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
         char *buf);
+static ssize_t show_fan_full_speed(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_fan_full_speed(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
 static ssize_t show_fan_beep(struct device *dev, struct device_attribute
         *devattr, char *buf);
 static ssize_t store_fan_beep(struct device *dev, struct device_attribute
@@ -163,16 +205,41 @@ static ssize_t show_temp_alarm(struct device *dev, struct device_attribute
         *devattr, char *buf);
 static ssize_t show_temp_fault(struct device *dev, struct device_attribute
         *devattr, char *buf);
+/* PWM and Auto point control */
+static ssize_t show_pwm(struct device *dev, struct device_attribute *devattr,
+        char *buf);
+static ssize_t store_pwm(struct device *dev, struct device_attribute *devattr,
+        const char *buf, size_t count);
+static ssize_t show_pwm_enable(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_enable(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
+static ssize_t show_pwm_interpolate(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_interpolate(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
+static ssize_t show_pwm_auto_point_channel(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_auto_point_channel(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
+static ssize_t show_pwm_auto_point_temp_hyst(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_auto_point_temp_hyst(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
+static ssize_t show_pwm_auto_point_pwm(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_auto_point_pwm(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
+static ssize_t show_pwm_auto_point_temp(struct device *dev,
+        struct device_attribute *devattr, char *buf);
+static ssize_t store_pwm_auto_point_temp(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count);
 /* Sysfs misc */
 static ssize_t show_name(struct device *dev, struct device_attribute *devattr,
         char *buf);
 
 static int __devinit f71882fg_probe(struct platform_device * pdev);
-static int __devexit f71882fg_remove(struct platform_device *pdev);
-static int __init f71882fg_init(void);
-static int __init f71882fg_find(int sioaddr, unsigned short *address);
-static int __init f71882fg_device_add(unsigned short address);
-static void __exit f71882fg_exit(void);
+static int f71882fg_remove(struct platform_device *pdev);
 
 static struct platform_driver f71882fg_driver = {
         .driver = {
@@ -183,86 +250,531 @@ static struct platform_driver f71882fg_driver = {
         .remove         = __devexit_p(f71882fg_remove),
 };
 
-static struct device_attribute f71882fg_dev_attr[] =
-{
-        __ATTR( name, S_IRUGO, show_name, NULL ),
+static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
+
+/* Temp and in attr common to both the f71862fg and f71882fg */
+static struct sensor_device_attribute_2 f718x2fg_in_temp_attr[] = {
+        SENSOR_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0),
+        SENSOR_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 0, 1),
+        SENSOR_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 0, 2),
+        SENSOR_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 0, 3),
+        SENSOR_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 0, 4),
+        SENSOR_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 0, 5),
+        SENSOR_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 0, 6),
+        SENSOR_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 0, 7),
+        SENSOR_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 0, 8),
+        SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 1),
+        SENSOR_ATTR_2(temp1_max, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 1),
+        SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
+                store_temp_max_hyst, 0, 1),
+        /* Should really be temp1_max_alarm, but older versions did not handle
+           the max and crit alarms separately and lm_sensors v2 depends on the
+           presence of temp#_alarm files. The same goes for temp2/3 _alarm. */
+        SENSOR_ATTR_2(temp1_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 1),
+        SENSOR_ATTR_2(temp1_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 1),
+        SENSOR_ATTR_2(temp1_crit, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 1),
+        SENSOR_ATTR_2(temp1_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
+                0, 1),
+        SENSOR_ATTR_2(temp1_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 5),
+        SENSOR_ATTR_2(temp1_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 5),
+        SENSOR_ATTR_2(temp1_type, S_IRUGO, show_temp_type, NULL, 0, 1),
+        SENSOR_ATTR_2(temp1_fault, S_IRUGO, show_temp_fault, NULL, 0, 1),
+        SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 2),
+        SENSOR_ATTR_2(temp2_max, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 2),
+        SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
+                store_temp_max_hyst, 0, 2),
+        /* Should be temp2_max_alarm, see temp1_alarm note */
+        SENSOR_ATTR_2(temp2_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 2),
+        SENSOR_ATTR_2(temp2_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 2),
+        SENSOR_ATTR_2(temp2_crit, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 2),
+        SENSOR_ATTR_2(temp2_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
+                0, 2),
+        SENSOR_ATTR_2(temp2_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 6),
+        SENSOR_ATTR_2(temp2_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 6),
+        SENSOR_ATTR_2(temp2_type, S_IRUGO, show_temp_type, NULL, 0, 2),
+        SENSOR_ATTR_2(temp2_fault, S_IRUGO, show_temp_fault, NULL, 0, 2),
+        SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 3),
+        SENSOR_ATTR_2(temp3_max, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 3),
+        SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
+                store_temp_max_hyst, 0, 3),
+        /* Should be temp3_max_alarm, see temp1_alarm note */
+        SENSOR_ATTR_2(temp3_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 3),
+        SENSOR_ATTR_2(temp3_max_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 3),
+        SENSOR_ATTR_2(temp3_crit, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 3),
+        SENSOR_ATTR_2(temp3_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL,
+                0, 3),
+        SENSOR_ATTR_2(temp3_crit_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 7),
+        SENSOR_ATTR_2(temp3_crit_beep, S_IRUGO|S_IWUSR, show_temp_beep,
+                store_temp_beep, 0, 7),
+        SENSOR_ATTR_2(temp3_type, S_IRUGO, show_temp_type, NULL, 0, 3),
+        SENSOR_ATTR_2(temp3_fault, S_IRUGO, show_temp_fault, NULL, 0, 3),
+};
+
+/* Temp and in attr found only on the f71882fg */
+static struct sensor_device_attribute_2 f71882fg_in_temp_attr[] = {
+        SENSOR_ATTR_2(in1_max, S_IRUGO|S_IWUSR, show_in_max, store_in_max,
+                0, 1),
+        SENSOR_ATTR_2(in1_beep, S_IRUGO|S_IWUSR, show_in_beep, store_in_beep,
+                0, 1),
+        SENSOR_ATTR_2(in1_alarm, S_IRUGO, show_in_alarm, NULL, 0, 1),
+};
+
+/* Temp and in attr for the f8000
+   Note on the f8000 temp_ovt (crit) is used as max, and temp_high (max)
+   is used as hysteresis value to clear alarms
+ */
+static struct sensor_device_attribute_2 f8000_in_temp_attr[] = {
+        SENSOR_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0),
+        SENSOR_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 0, 1),
+        SENSOR_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 0, 2),
+        SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0),
+        SENSOR_ATTR_2(temp1_max, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 0),
+        SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 0),
+        SENSOR_ATTR_2(temp1_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 4),
+        SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 1),
+        SENSOR_ATTR_2(temp2_max, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 1),
+        SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 1),
+        SENSOR_ATTR_2(temp2_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 5),
+        SENSOR_ATTR_2(temp2_type, S_IRUGO, show_temp_type, NULL, 0, 1),
+        SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 2),
+        SENSOR_ATTR_2(temp3_max, S_IRUGO|S_IWUSR, show_temp_crit,
+                store_temp_crit, 0, 2),
+        SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max,
+                store_temp_max, 0, 2),
+        SENSOR_ATTR_2(temp3_alarm, S_IRUGO, show_temp_alarm, NULL, 0, 6),
+};
+
+/* Fan / PWM attr common to all models */
+static struct sensor_device_attribute_2 fxxxx_fan_attr[] = {
+        SENSOR_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0),
+        SENSOR_ATTR_2(fan1_full_speed, S_IRUGO|S_IWUSR,
+                      show_fan_full_speed,
+                      store_fan_full_speed, 0, 0),
+        SENSOR_ATTR_2(fan1_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 0),
+        SENSOR_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 0, 1),
+        SENSOR_ATTR_2(fan2_full_speed, S_IRUGO|S_IWUSR,
+                      show_fan_full_speed,
+                      store_fan_full_speed, 0, 1),
+        SENSOR_ATTR_2(fan2_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 1),
+        SENSOR_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 0, 2),
+        SENSOR_ATTR_2(fan3_full_speed, S_IRUGO|S_IWUSR,
+                      show_fan_full_speed,
+                      store_fan_full_speed, 0, 2),
+        SENSOR_ATTR_2(fan3_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 2),
+
+        SENSOR_ATTR_2(pwm1, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 0),
+        SENSOR_ATTR_2(pwm1_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
+                      store_pwm_enable, 0, 0),
+        SENSOR_ATTR_2(pwm1_interpolate, S_IRUGO|S_IWUSR,
+                      show_pwm_interpolate, store_pwm_interpolate, 0, 0),
+        SENSOR_ATTR_2(pwm1_auto_channels_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_channel,
+                      store_pwm_auto_point_channel, 0, 0),
+
+        SENSOR_ATTR_2(pwm2, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 1),
+        SENSOR_ATTR_2(pwm2_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
+                      store_pwm_enable, 0, 1),
+        SENSOR_ATTR_2(pwm2_interpolate, S_IRUGO|S_IWUSR,
+                      show_pwm_interpolate, store_pwm_interpolate, 0, 1),
+        SENSOR_ATTR_2(pwm2_auto_channels_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_channel,
+                      store_pwm_auto_point_channel, 0, 1),
+
+        SENSOR_ATTR_2(pwm3_interpolate, S_IRUGO|S_IWUSR,
+                      show_pwm_interpolate, store_pwm_interpolate, 0, 2),
+        SENSOR_ATTR_2(pwm3_auto_channels_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_channel,
+                      store_pwm_auto_point_channel, 0, 2),
 };
 
-static struct sensor_device_attribute f71882fg_in_temp_attr[] =
-{
-        SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
-        SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
-        SENSOR_ATTR(in1_max, S_IRUGO|S_IWUSR, show_in_max, store_in_max, 1),
-        SENSOR_ATTR(in1_beep, S_IRUGO|S_IWUSR, show_in_beep, store_in_beep, 1),
-        SENSOR_ATTR(in1_alarm, S_IRUGO, show_in_alarm, NULL, 1),
-        SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
-        SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
-        SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
-        SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
-        SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
-        SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
-        SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
-        SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
-        SENSOR_ATTR(temp1_max, S_IRUGO|S_IWUSR, show_temp_max,
-                store_temp_max, 0),
-        SENSOR_ATTR(temp1_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
-                store_temp_max_hyst, 0),
-        SENSOR_ATTR(temp1_crit, S_IRUGO|S_IWUSR, show_temp_crit,
-                store_temp_crit, 0),
-        SENSOR_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL, 0),
-        SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
-        SENSOR_ATTR(temp1_beep, S_IRUGO|S_IWUSR, show_temp_beep,
-                store_temp_beep, 0),
-        SENSOR_ATTR(temp1_alarm, S_IRUGO, show_temp_alarm, NULL, 0),
-        SENSOR_ATTR(temp1_fault, S_IRUGO, show_temp_fault, NULL, 0),
-        SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
-        SENSOR_ATTR(temp2_max, S_IRUGO|S_IWUSR, show_temp_max,
-                store_temp_max, 1),
-        SENSOR_ATTR(temp2_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
-                store_temp_max_hyst, 1),
-        SENSOR_ATTR(temp2_crit, S_IRUGO|S_IWUSR, show_temp_crit,
-                store_temp_crit, 1),
-        SENSOR_ATTR(temp2_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL, 1),
-        SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
-        SENSOR_ATTR(temp2_beep, S_IRUGO|S_IWUSR, show_temp_beep,
-                store_temp_beep, 1),
-        SENSOR_ATTR(temp2_alarm, S_IRUGO, show_temp_alarm, NULL, 1),
-        SENSOR_ATTR(temp2_fault, S_IRUGO, show_temp_fault, NULL, 1),
-        SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
-        SENSOR_ATTR(temp3_max, S_IRUGO|S_IWUSR, show_temp_max,
-                store_temp_max, 2),
-        SENSOR_ATTR(temp3_max_hyst, S_IRUGO|S_IWUSR, show_temp_max_hyst,
-                store_temp_max_hyst, 2),
-        SENSOR_ATTR(temp3_crit, S_IRUGO|S_IWUSR, show_temp_crit,
-                store_temp_crit, 2),
-        SENSOR_ATTR(temp3_crit_hyst, S_IRUGO, show_temp_crit_hyst, NULL, 2),
-        SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
-        SENSOR_ATTR(temp3_beep, S_IRUGO|S_IWUSR, show_temp_beep,
-                store_temp_beep, 2),
-        SENSOR_ATTR(temp3_alarm, S_IRUGO, show_temp_alarm, NULL, 2),
-        SENSOR_ATTR(temp3_fault, S_IRUGO, show_temp_fault, NULL, 2)
+/* Fan / PWM attr for the f71862fg, less pwms and less zones per pwm than the
+   f71882fg */
+static struct sensor_device_attribute_2 f71862fg_fan_attr[] = {
+        SENSOR_ATTR_2(fan1_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 0),
+        SENSOR_ATTR_2(fan2_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 1),
+        SENSOR_ATTR_2(fan3_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 2),
+
+        SENSOR_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 0),
+        SENSOR_ATTR_2(pwm1_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 0),
+        SENSOR_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 0),
+
+        SENSOR_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 1),
+        SENSOR_ATTR_2(pwm2_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 1),
+        SENSOR_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 1),
+
+        SENSOR_ATTR_2(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 2),
+        SENSOR_ATTR_2(pwm3_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
+                      store_pwm_enable, 0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 2),
 };
 
-static struct sensor_device_attribute f71882fg_fan_attr[] =
-{
-        SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
-        SENSOR_ATTR(fan1_beep, S_IRUGO|S_IWUSR, show_fan_beep,
-                store_fan_beep, 0),
-        SENSOR_ATTR(fan1_alarm, S_IRUGO, show_fan_alarm, NULL, 0),
-        SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
-        SENSOR_ATTR(fan2_beep, S_IRUGO|S_IWUSR, show_fan_beep,
-                store_fan_beep, 1),
-        SENSOR_ATTR(fan2_alarm, S_IRUGO, show_fan_alarm, NULL, 1),
-        SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
-        SENSOR_ATTR(fan3_beep, S_IRUGO|S_IWUSR, show_fan_beep,
-                store_fan_beep, 2),
-        SENSOR_ATTR(fan3_alarm, S_IRUGO, show_fan_alarm, NULL, 2),
-        SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
-        SENSOR_ATTR(fan4_beep, S_IRUGO|S_IWUSR, show_fan_beep,
-                store_fan_beep, 3),
-        SENSOR_ATTR(fan4_alarm, S_IRUGO, show_fan_alarm, NULL, 3)
+/* Fan / PWM attr for the f71882fg */
+static struct sensor_device_attribute_2 f71882fg_fan_attr[] = {
+        SENSOR_ATTR_2(fan1_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 0),
+        SENSOR_ATTR_2(fan2_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 1),
+        SENSOR_ATTR_2(fan3_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 2),
+        SENSOR_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 0, 3),
+        SENSOR_ATTR_2(fan4_full_speed, S_IRUGO|S_IWUSR,
+                      show_fan_full_speed,
+                      store_fan_full_speed, 0, 3),
+        SENSOR_ATTR_2(fan4_beep, S_IRUGO|S_IWUSR, show_fan_beep,
+                store_fan_beep, 0, 3),
+        SENSOR_ATTR_2(fan4_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 3),
+
+        SENSOR_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 0),
+        SENSOR_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 0),
+        SENSOR_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 0),
+        SENSOR_ATTR_2(pwm1_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 0),
+        SENSOR_ATTR_2(pwm1_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 0),
+        SENSOR_ATTR_2(pwm1_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 0),
+        SENSOR_ATTR_2(pwm1_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 0),
+        SENSOR_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 0),
+        SENSOR_ATTR_2(pwm1_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 0),
+        SENSOR_ATTR_2(pwm1_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 0),
+        SENSOR_ATTR_2(pwm1_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 0),
+
+        SENSOR_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 1),
+        SENSOR_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 1),
+        SENSOR_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 1),
+        SENSOR_ATTR_2(pwm2_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 1),
+        SENSOR_ATTR_2(pwm2_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 1),
+        SENSOR_ATTR_2(pwm2_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 1),
+        SENSOR_ATTR_2(pwm2_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 1),
+        SENSOR_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 1),
+        SENSOR_ATTR_2(pwm2_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 1),
+        SENSOR_ATTR_2(pwm2_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 1),
+        SENSOR_ATTR_2(pwm2_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 1),
+
+        SENSOR_ATTR_2(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 2),
+        SENSOR_ATTR_2(pwm3_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
+                      store_pwm_enable, 0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 2),
+        SENSOR_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 2),
+        SENSOR_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 2),
+        SENSOR_ATTR_2(pwm3_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 2),
+        SENSOR_ATTR_2(pwm3_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 2),
+        SENSOR_ATTR_2(pwm3_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 2),
+        SENSOR_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 2),
+        SENSOR_ATTR_2(pwm3_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 2),
+        SENSOR_ATTR_2(pwm3_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 2),
+        SENSOR_ATTR_2(pwm3_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 2),
+
+        SENSOR_ATTR_2(pwm4, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0, 3),
+        SENSOR_ATTR_2(pwm4_enable, S_IRUGO|S_IWUSR, show_pwm_enable,
+                      store_pwm_enable, 0, 3),
+        SENSOR_ATTR_2(pwm4_interpolate, S_IRUGO|S_IWUSR,
+                      show_pwm_interpolate, store_pwm_interpolate, 0, 3),
+        SENSOR_ATTR_2(pwm4_auto_channels_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_channel,
+                      store_pwm_auto_point_channel, 0, 3),
+        SENSOR_ATTR_2(pwm4_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 3),
+        SENSOR_ATTR_2(pwm4_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 3),
+        SENSOR_ATTR_2(pwm4_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 3),
+        SENSOR_ATTR_2(pwm4_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 3),
+        SENSOR_ATTR_2(pwm4_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 3),
+        SENSOR_ATTR_2(pwm4_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 3),
+        SENSOR_ATTR_2(pwm4_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 3),
+        SENSOR_ATTR_2(pwm4_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 3),
+        SENSOR_ATTR_2(pwm4_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 3),
+        SENSOR_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 3),
+        SENSOR_ATTR_2(pwm4_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 3),
+        SENSOR_ATTR_2(pwm4_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 3),
+        SENSOR_ATTR_2(pwm4_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 3),
 };
 
+/* Fan / PWM attr for the f8000, zones mapped to temp instead of to pwm!
+   Also the register block at offset A0 maps to TEMP1 (so our temp2, as the
+   F8000 starts counting temps at 0), B0 maps the TEMP2 and C0 maps to TEMP0 */
+static struct sensor_device_attribute_2 f8000_fan_attr[] = {
+        SENSOR_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 0, 3),
+
+        SENSOR_ATTR_2(pwm3, S_IRUGO, show_pwm, NULL, 0, 2),
+
+        SENSOR_ATTR_2(temp1_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 2),
+        SENSOR_ATTR_2(temp1_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 2),
+        SENSOR_ATTR_2(temp1_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 2),
+        SENSOR_ATTR_2(temp1_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 2),
+        SENSOR_ATTR_2(temp1_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 2),
+        SENSOR_ATTR_2(temp1_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 2),
+        SENSOR_ATTR_2(temp1_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 2),
+        SENSOR_ATTR_2(temp1_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 2),
+        SENSOR_ATTR_2(temp1_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 2),
+        SENSOR_ATTR_2(temp1_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 2),
+        SENSOR_ATTR_2(temp1_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 2),
+        SENSOR_ATTR_2(temp1_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 2),
+        SENSOR_ATTR_2(temp1_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 2),
+
+        SENSOR_ATTR_2(temp2_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 0),
+        SENSOR_ATTR_2(temp2_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 0),
+        SENSOR_ATTR_2(temp2_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 0),
+        SENSOR_ATTR_2(temp2_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 0),
+        SENSOR_ATTR_2(temp2_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 0),
+        SENSOR_ATTR_2(temp2_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 0),
+        SENSOR_ATTR_2(temp2_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 0),
+        SENSOR_ATTR_2(temp2_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 0),
+        SENSOR_ATTR_2(temp2_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 0),
+        SENSOR_ATTR_2(temp2_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 0),
+        SENSOR_ATTR_2(temp2_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 0),
+        SENSOR_ATTR_2(temp2_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 0),
+        SENSOR_ATTR_2(temp2_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 0),
+
+        SENSOR_ATTR_2(temp3_auto_point1_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      0, 1),
+        SENSOR_ATTR_2(temp3_auto_point2_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      1, 1),
+        SENSOR_ATTR_2(temp3_auto_point3_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      2, 1),
+        SENSOR_ATTR_2(temp3_auto_point4_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      3, 1),
+        SENSOR_ATTR_2(temp3_auto_point5_pwm, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_pwm, store_pwm_auto_point_pwm,
+                      4, 1),
+        SENSOR_ATTR_2(temp3_auto_point1_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      0, 1),
+        SENSOR_ATTR_2(temp3_auto_point2_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      1, 1),
+        SENSOR_ATTR_2(temp3_auto_point3_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      2, 1),
+        SENSOR_ATTR_2(temp3_auto_point4_temp, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp, store_pwm_auto_point_temp,
+                      3, 1),
+        SENSOR_ATTR_2(temp3_auto_point1_temp_hyst, S_IRUGO|S_IWUSR,
+                      show_pwm_auto_point_temp_hyst,
+                      store_pwm_auto_point_temp_hyst,
+                      0, 1),
+        SENSOR_ATTR_2(temp3_auto_point2_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 1, 1),
+        SENSOR_ATTR_2(temp3_auto_point3_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 2, 1),
+        SENSOR_ATTR_2(temp3_auto_point4_temp_hyst, S_IRUGO,
+                      show_pwm_auto_point_temp_hyst, NULL, 3, 1),
+};
 
 /* Super I/O functions */
 static inline int superio_inb(int base, int reg)
@@ -299,11 +811,16 @@ static inline void superio_exit(int base)
         outb(SIO_LOCK_KEY, base);
 }
 
-static inline u16 fan_from_reg(u16 reg)
+static inline int fan_from_reg(u16 reg)
 {
         return reg ? (1500000 / reg) : 0;
 }
 
+static inline u16 fan_to_reg(int fan)
+{
+        return fan ? (1500000 / fan) : 0;
+}
+
 static u8 f71882fg_read8(struct f71882fg_data *data, u8 reg)
 {
         u8 val;
@@ -332,52 +849,111 @@ static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val)
         outb(val, data->addr + DATA_REG_OFFSET);
 }
 
-static struct f71882fg_data *f71882fg_update_device(struct device * dev)
+static void f71882fg_write16(struct f71882fg_data *data, u8 reg, u16 val)
+{
+        outb(reg++, data->addr + ADDR_REG_OFFSET);
+        outb(val >> 8, data->addr + DATA_REG_OFFSET);
+        outb(reg, data->addr + ADDR_REG_OFFSET);
+        outb(val & 255, data->addr + DATA_REG_OFFSET);
+}
+
+static struct f71882fg_data *f71882fg_update_device(struct device *dev)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr, reg, reg2;
+        int nr, reg = 0, reg2;
+        int nr_fans = (data->type == f71882fg) ? 4 : 3;
+        int nr_ins = (data->type == f8000) ? 3 : 9;
+        int temp_start = (data->type == f8000) ? 0 : 1;
 
         mutex_lock(&data->update_lock);
 
         /* Update once every 60 seconds */
         if ( time_after(jiffies, data->last_limits + 60 * HZ ) ||
                         !data->valid) {
-                data->in1_max = f71882fg_read8(data, F71882FG_REG_IN1_HIGH);
-                data->in_beep = f71882fg_read8(data, F71882FG_REG_IN_BEEP);
+                if (data->type == f71882fg) {
+                        data->in1_max =
+                                f71882fg_read8(data, F71882FG_REG_IN1_HIGH);
+                        data->in_beep =
+                                f71882fg_read8(data, F71882FG_REG_IN_BEEP);
+                }
 
                 /* Get High & boundary temps*/
-                for (nr = 0; nr < 3; nr++) {
+                for (nr = temp_start; nr < 3 + temp_start; nr++) {
                         data->temp_ovt[nr] = f71882fg_read8(data,
                                                 F71882FG_REG_TEMP_OVT(nr));
                         data->temp_high[nr] = f71882fg_read8(data,
                                                 F71882FG_REG_TEMP_HIGH(nr));
                 }
 
-                /* Have to hardcode hyst*/
-                data->temp_hyst[0] = f71882fg_read8(data,
-                                                F71882FG_REG_TEMP_HYST1) >> 4;
-                /* Hyst temps 2 & 3 stored in same register */
-                reg = f71882fg_read8(data, F71882FG_REG_TEMP_HYST23);
-                data->temp_hyst[1] = reg & 0x0F;
-                data->temp_hyst[2] = reg >> 4;
-
-                /* Have to hardcode type, because temp1 is special */
-                reg  = f71882fg_read8(data, F71882FG_REG_TEMP_TYPE);
+                if (data->type != f8000) {
+                        data->fan_beep = f71882fg_read8(data,
+                                                F71882FG_REG_FAN_BEEP);
+                        data->temp_beep = f71882fg_read8(data,
+                                                F71882FG_REG_TEMP_BEEP);
+                        data->temp_hyst[0] = f71882fg_read8(data,
+                                                F71882FG_REG_TEMP_HYST(0));
+                        data->temp_hyst[1] = f71882fg_read8(data,
+                                                F71882FG_REG_TEMP_HYST(1));
+                        /* Have to hardcode type, because temp1 is special */
+                        reg  = f71882fg_read8(data, F71882FG_REG_TEMP_TYPE);
+                        data->temp_type[2] = (reg & 0x04) ? 2 : 4;
+                        data->temp_type[3] = (reg & 0x08) ? 2 : 4;
+                }
                 reg2 = f71882fg_read8(data, F71882FG_REG_PECI);
                 if ((reg2 & 0x03) == 0x01)
-                        data->temp_type[0] = 6 /* PECI */;
+                        data->temp_type[1] = 6 /* PECI */;
                 else if ((reg2 & 0x03) == 0x02)
-                        data->temp_type[0] = 5 /* AMDSI */;
+                        data->temp_type[1] = 5 /* AMDSI */;
+                else if (data->type != f8000)
+                        data->temp_type[1] = (reg & 0x02) ? 2 : 4;
                 else
-                        data->temp_type[0] = (reg & 0x02) ? 2 : 4;
-
-                data->temp_type[1] = (reg & 0x04) ? 2 : 4;
-                data->temp_type[2] = (reg & 0x08) ? 2 : 4;
-
-                data->temp_beep = f71882fg_read8(data, F71882FG_REG_TEMP_BEEP);
-
-                data->fan_beep = f71882fg_read8(data, F71882FG_REG_FAN_BEEP);
-
+                        data->temp_type[1] = 2; /* F8000 only supports BJT */
+
+                data->pwm_enable = f71882fg_read8(data,
+                                                  F71882FG_REG_PWM_ENABLE);
+                data->pwm_auto_point_hyst[0] =
+                        f71882fg_read8(data, F71882FG_REG_FAN_HYST(0));
+                data->pwm_auto_point_hyst[1] =
+                        f71882fg_read8(data, F71882FG_REG_FAN_HYST(1));
+
+                for (nr = 0; nr < nr_fans; nr++) {
+                        data->pwm_auto_point_mapping[nr] =
+                            f71882fg_read8(data,
+                                           F71882FG_REG_POINT_MAPPING(nr));
+
+                        if (data->type != f71862fg) {
+                                int point;
+                                for (point = 0; point < 5; point++) {
+                                        data->pwm_auto_point_pwm[nr][point] =
+                                                f71882fg_read8(data,
+                                                        F71882FG_REG_POINT_PWM
+                                                        (nr, point));
+                                }
+                                for (point = 0; point < 4; point++) {
+                                        data->pwm_auto_point_temp[nr][point] =
+                                                f71882fg_read8(data,
+                                                        F71882FG_REG_POINT_TEMP
+                                                        (nr, point));
+                                }
+                        } else {
+                                data->pwm_auto_point_pwm[nr][1] =
+                                        f71882fg_read8(data,
+                                                F71882FG_REG_POINT_PWM
+                                                (nr, 1));
+                                data->pwm_auto_point_pwm[nr][4] =
+                                        f71882fg_read8(data,
+                                                F71882FG_REG_POINT_PWM
+                                                (nr, 4));
+                                data->pwm_auto_point_temp[nr][0] =
+                                        f71882fg_read8(data,
+                                                F71882FG_REG_POINT_TEMP
+                                                (nr, 0));
+                                data->pwm_auto_point_temp[nr][3] =
+                                        f71882fg_read8(data,
+                                                F71882FG_REG_POINT_TEMP
+                                                (nr, 3));
+                        }
+                }
                 data->last_limits = jiffies;
         }
 
@@ -387,19 +963,32 @@ static struct f71882fg_data *f71882fg_update_device(struct device * dev)
                                                 F71882FG_REG_TEMP_STATUS);
                 data->temp_diode_open = f71882fg_read8(data,
                                                 F71882FG_REG_TEMP_DIODE_OPEN);
-                for (nr = 0; nr < 3; nr++)
+                for (nr = temp_start; nr < 3 + temp_start; nr++)
                         data->temp[nr] = f71882fg_read8(data,
                                                 F71882FG_REG_TEMP(nr));
 
                 data->fan_status = f71882fg_read8(data,
                                                 F71882FG_REG_FAN_STATUS);
-                for (nr = 0; nr < 4; nr++)
+                for (nr = 0; nr < nr_fans; nr++) {
                         data->fan[nr] = f71882fg_read16(data,
                                                 F71882FG_REG_FAN(nr));
+                        data->fan_target[nr] =
+                            f71882fg_read16(data, F71882FG_REG_FAN_TARGET(nr));
+                        data->fan_full_speed[nr] =
+                            f71882fg_read16(data,
+                                            F71882FG_REG_FAN_FULL_SPEED(nr));
+                        data->pwm[nr] =
+                            f71882fg_read8(data, F71882FG_REG_PWM(nr));
+                }
 
-                data->in_status = f71882fg_read8(data,
+                /* The f8000 can monitor 1 more fan, but has no pwm for it */
+                if (data->type == f8000)
+                        data->fan[3] = f71882fg_read16(data,
+                                                F71882FG_REG_FAN(3));
+                if (data->type == f71882fg)
+                        data->in_status = f71882fg_read8(data,
                                                 F71882FG_REG_IN_STATUS);
-                for (nr = 0; nr < 9; nr++)
+                for (nr = 0; nr < nr_ins; nr++)
                         data->in[nr] = f71882fg_read8(data,
                                                 F71882FG_REG_IN(nr));
 
@@ -417,7 +1006,7 @@ static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
         char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
         int speed = fan_from_reg(data->fan[nr]);
 
         if (speed == FAN_MIN_DETECT)
@@ -426,11 +1015,39 @@ static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
         return sprintf(buf, "%d\n", speed);
 }
 
+static ssize_t show_fan_full_speed(struct device *dev,
+                                   struct device_attribute *devattr, char *buf)
+{
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int speed = fan_from_reg(data->fan_full_speed[nr]);
+        return sprintf(buf, "%d\n", speed);
+}
+
+static ssize_t store_fan_full_speed(struct device *dev,
+                                    struct device_attribute *devattr,
+                                    const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10);
+
+        val = SENSORS_LIMIT(val, 23, 1500000);
+        val = fan_to_reg(val);
+
+        mutex_lock(&data->update_lock);
+        f71882fg_write16(data, F71882FG_REG_FAN_FULL_SPEED(nr), val);
+        data->fan_full_speed[nr] = val;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
 static ssize_t show_fan_beep(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         if (data->fan_beep & (1 << nr))
                 return sprintf(buf, "1\n");
@@ -442,10 +1059,11 @@ static ssize_t store_fan_beep(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        unsigned long val = simple_strtoul(buf, NULL, 10);
 
         mutex_lock(&data->update_lock);
+        data->fan_beep = f71882fg_read8(data, F71882FG_REG_FAN_BEEP);
         if (val)
                 data->fan_beep |= 1 << nr;
         else
@@ -461,7 +1079,7 @@ static ssize_t show_fan_alarm(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         if (data->fan_status & (1 << nr))
                 return sprintf(buf, "1\n");
@@ -473,7 +1091,7 @@ static ssize_t show_in(struct device *dev, struct device_attribute *devattr,
         char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         return sprintf(buf, "%d\n", data->in[nr] * 8);
 }
@@ -490,10 +1108,8 @@ static ssize_t store_in_max(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int val = simple_strtoul(buf, NULL, 10) / 8;
-
-        if (val > 255)
-                val = 255;
+        long val = simple_strtol(buf, NULL, 10) / 8;
+        val = SENSORS_LIMIT(val, 0, 255);
 
         mutex_lock(&data->update_lock);
         f71882fg_write8(data, F71882FG_REG_IN1_HIGH, val);
@@ -507,7 +1123,7 @@ static ssize_t show_in_beep(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         if (data->in_beep & (1 << nr))
                 return sprintf(buf, "1\n");
@@ -519,10 +1135,11 @@ static ssize_t store_in_beep(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        unsigned long val = simple_strtoul(buf, NULL, 10);
 
         mutex_lock(&data->update_lock);
+        data->in_beep = f71882fg_read8(data, F71882FG_REG_IN_BEEP);
         if (val)
                 data->in_beep |= 1 << nr;
         else
@@ -538,7 +1155,7 @@ static ssize_t show_in_alarm(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         if (data->in_status & (1 << nr))
                 return sprintf(buf, "1\n");
@@ -550,7 +1167,7 @@ static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
         char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         return sprintf(buf, "%d\n", data->temp[nr] * 1000);
 }
@@ -559,7 +1176,7 @@ static ssize_t show_temp_max(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         return sprintf(buf, "%d\n", data->temp_high[nr] * 1000);
 }
@@ -568,11 +1185,9 @@ static ssize_t store_temp_max(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10) / 1000;
-
-        if (val > 255)
-                val = 255;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10) / 1000;
+        val = SENSORS_LIMIT(val, 0, 255);
 
         mutex_lock(&data->update_lock);
         f71882fg_write8(data, F71882FG_REG_TEMP_HIGH(nr), val);
@@ -586,48 +1201,46 @@ static ssize_t show_temp_max_hyst(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int temp_max_hyst;
+
+        mutex_lock(&data->update_lock);
+        if (nr & 1)
+                temp_max_hyst = data->temp_hyst[nr / 2] >> 4;
+        else
+                temp_max_hyst = data->temp_hyst[nr / 2] & 0x0f;
+        temp_max_hyst = (data->temp_high[nr] - temp_max_hyst) * 1000;
+        mutex_unlock(&data->update_lock);
 
-        return sprintf(buf, "%d\n",
-                (data->temp_high[nr] - data->temp_hyst[nr]) * 1000);
+        return sprintf(buf, "%d\n", temp_max_hyst);
 }
 
 static ssize_t store_temp_max_hyst(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10) / 1000;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10) / 1000;
         ssize_t ret = count;
+        u8 reg;
 
         mutex_lock(&data->update_lock);
 
         /* convert abs to relative and check */
+        data->temp_high[nr] = f71882fg_read8(data, F71882FG_REG_TEMP_HIGH(nr));
+        val = SENSORS_LIMIT(val, data->temp_high[nr] - 15,
+                            data->temp_high[nr]);
         val = data->temp_high[nr] - val;
-        if (val < 0 || val > 15) {
-                ret = -EINVAL;
-                goto store_temp_max_hyst_exit;
-        }
-
-        data->temp_hyst[nr] = val;
 
         /* convert value to register contents */
-        switch (nr) {
-                case 0:
-                        val = val << 4;
-                        break;
-                case 1:
-                        val = val | (data->temp_hyst[2] << 4);
-                        break;
-                case 2:
-                        val = data->temp_hyst[1] | (val << 4);
-                        break;
-        }
-
-        f71882fg_write8(data, nr ? F71882FG_REG_TEMP_HYST23 :
-                F71882FG_REG_TEMP_HYST1, val);
+        reg = f71882fg_read8(data, F71882FG_REG_TEMP_HYST(nr / 2));
+        if (nr & 1)
+                reg = (reg & 0x0f) | (val << 4);
+        else
+                reg = (reg & 0xf0) | val;
+        f71882fg_write8(data, F71882FG_REG_TEMP_HYST(nr / 2), reg);
+        data->temp_hyst[nr / 2] = reg;
 
-store_temp_max_hyst_exit:
         mutex_unlock(&data->update_lock);
         return ret;
 }
@@ -636,7 +1249,7 @@ static ssize_t show_temp_crit(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         return sprintf(buf, "%d\n", data->temp_ovt[nr] * 1000);
 }
@@ -645,11 +1258,9 @@ static ssize_t store_temp_crit(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10) / 1000;
-
-        if (val > 255)
-                val = 255;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10) / 1000;
+        val = SENSORS_LIMIT(val, 0, 255);
 
         mutex_lock(&data->update_lock);
         f71882fg_write8(data, F71882FG_REG_TEMP_OVT(nr), val);
@@ -663,17 +1274,25 @@ static ssize_t show_temp_crit_hyst(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int temp_crit_hyst;
+
+        mutex_lock(&data->update_lock);
+        if (nr & 1)
+                temp_crit_hyst = data->temp_hyst[nr / 2] >> 4;
+        else
+                temp_crit_hyst = data->temp_hyst[nr / 2] & 0x0f;
+        temp_crit_hyst = (data->temp_ovt[nr] - temp_crit_hyst) * 1000;
+        mutex_unlock(&data->update_lock);
 
-        return sprintf(buf, "%d\n",
-                (data->temp_ovt[nr] - data->temp_hyst[nr]) * 1000);
+        return sprintf(buf, "%d\n", temp_crit_hyst);
 }
 
 static ssize_t show_temp_type(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
         return sprintf(buf, "%d\n", data->temp_type[nr]);
 }
@@ -682,9 +1301,9 @@ static ssize_t show_temp_beep(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
-        if (data->temp_beep & (1 << (nr + 1)))
+        if (data->temp_beep & (1 << nr))
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
@@ -694,14 +1313,15 @@ static ssize_t store_temp_beep(struct device *dev, struct device_attribute
         *devattr, const char *buf, size_t count)
 {
         struct f71882fg_data *data = dev_get_drvdata(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
-        int val = simple_strtoul(buf, NULL, 10);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        unsigned long val = simple_strtoul(buf, NULL, 10);
 
         mutex_lock(&data->update_lock);
+        data->temp_beep = f71882fg_read8(data, F71882FG_REG_TEMP_BEEP);
         if (val)
-                data->temp_beep |= 1 << (nr + 1);
+                data->temp_beep |= 1 << nr;
         else
-                data->temp_beep &= ~(1 << (nr + 1));
+                data->temp_beep &= ~(1 << nr);
 
         f71882fg_write8(data, F71882FG_REG_TEMP_BEEP, data->temp_beep);
         mutex_unlock(&data->update_lock);
@@ -713,9 +1333,9 @@ static ssize_t show_temp_alarm(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
-        if (data->temp_status & (1 << (nr + 1)))
+        if (data->temp_status & (1 << nr))
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
@@ -725,113 +1345,528 @@ static ssize_t show_temp_fault(struct device *dev, struct device_attribute
         *devattr, char *buf)
 {
         struct f71882fg_data *data = f71882fg_update_device(dev);
-        int nr = to_sensor_dev_attr(devattr)->index;
+        int nr = to_sensor_dev_attr_2(devattr)->index;
 
-        if (data->temp_diode_open & (1 << (nr + 1)))
+        if (data->temp_diode_open & (1 << nr))
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
 }
 
+static ssize_t show_pwm(struct device *dev,
+                        struct device_attribute *devattr, char *buf)
+{
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int val, nr = to_sensor_dev_attr_2(devattr)->index;
+        mutex_lock(&data->update_lock);
+        if (data->pwm_enable & (1 << (2 * nr)))
+                /* PWM mode */
+                val = data->pwm[nr];
+        else {
+                /* RPM mode */
+                val = 255 * fan_from_reg(data->fan_target[nr])
+                        / fan_from_reg(data->fan_full_speed[nr]);
+        }
+        mutex_unlock(&data->update_lock);
+        return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t store_pwm(struct device *dev,
+                         struct device_attribute *devattr, const char *buf,
+                         size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10);
+        val = SENSORS_LIMIT(val, 0, 255);
+
+        mutex_lock(&data->update_lock);
+        data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
+        if ((data->type == f8000 && ((data->pwm_enable >> 2 * nr) & 3) != 2) ||
+            (data->type != f8000 && !((data->pwm_enable >> 2 * nr) & 2))) {
+                count = -EROFS;
+                goto leave;
+        }
+        if (data->pwm_enable & (1 << (2 * nr))) {
+                /* PWM mode */
+                f71882fg_write8(data, F71882FG_REG_PWM(nr), val);
+                data->pwm[nr] = val;
+        } else {
+                /* RPM mode */
+                int target, full_speed;
+                full_speed = f71882fg_read16(data,
+                                             F71882FG_REG_FAN_FULL_SPEED(nr));
+                target = fan_to_reg(val * fan_from_reg(full_speed) / 255);
+                f71882fg_write16(data, F71882FG_REG_FAN_TARGET(nr), target);
+                data->fan_target[nr] = target;
+                data->fan_full_speed[nr] = full_speed;
+        }
+leave:
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_enable(struct device *dev,
+                               struct device_attribute *devattr, char *buf)
+{
+        int result = 0;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+
+        switch ((data->pwm_enable >> 2 * nr) & 3) {
+        case 0:
+        case 1:
+                result = 2; /* Normal auto mode */
+                break;
+        case 2:
+                result = 1; /* Manual mode */
+                break;
+        case 3:
+                if (data->type == f8000)
+                        result = 3; /* Thermostat mode */
+                else
+                        result = 1; /* Manual mode */
+                break;
+        }
+
+        return sprintf(buf, "%d\n", result);
+}
+
+static ssize_t store_pwm_enable(struct device *dev, struct device_attribute
+                                *devattr, const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        long val = simple_strtol(buf, NULL, 10);
+
+        mutex_lock(&data->update_lock);
+        data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
+        /* Special case for F8000 auto PWM mode / Thermostat mode */
+        if (data->type == f8000 && ((data->pwm_enable >> 2 * nr) & 1)) {
+                switch (val) {
+                case 2:
+                        data->pwm_enable &= ~(2 << (2 * nr));
+                        break;          /* Normal auto mode */
+                case 3:
+                        data->pwm_enable |= 2 << (2 * nr);
+                        break;          /* Thermostat mode */
+                default:
+                        count = -EINVAL;
+                        goto leave;
+                }
+        } else {
+                switch (val) {
+                case 1:
+                        data->pwm_enable |= 2 << (2 * nr);
+                        break;          /* Manual */
+                case 2:
+                        data->pwm_enable &= ~(2 << (2 * nr));
+                        break;          /* Normal auto mode */
+                default:
+                        count = -EINVAL;
+                        goto leave;
+                }
+        }
+        f71882fg_write8(data, F71882FG_REG_PWM_ENABLE, data->pwm_enable);
+leave:
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_auto_point_pwm(struct device *dev,
+                                       struct device_attribute *devattr,
+                                       char *buf)
+{
+        int result;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int pwm = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+
+        mutex_lock(&data->update_lock);
+        if (data->pwm_enable & (1 << (2 * pwm))) {
+                /* PWM mode */
+                result = data->pwm_auto_point_pwm[pwm][point];
+        } else {
+                /* RPM mode */
+                result = 32 * 255 / (32 + data->pwm_auto_point_pwm[pwm][point]);
+        }
+        mutex_unlock(&data->update_lock);
+
+        return sprintf(buf, "%d\n", result);
+}
+
+static ssize_t store_pwm_auto_point_pwm(struct device *dev,
+                                        struct device_attribute *devattr,
+                                        const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int pwm = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+        long val = simple_strtol(buf, NULL, 10);
+        val = SENSORS_LIMIT(val, 0, 255);
+
+        mutex_lock(&data->update_lock);
+        data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
+        if (data->pwm_enable & (1 << (2 * pwm))) {
+                /* PWM mode */
+        } else {
+                /* RPM mode */
+                if (val < 29)   /* Prevent negative numbers */
+                        val = 255;
+                else
+                        val = (255 - val) * 32 / val;
+        }
+        f71882fg_write8(data, F71882FG_REG_POINT_PWM(pwm, point), val);
+        data->pwm_auto_point_pwm[pwm][point] = val;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_auto_point_temp_hyst(struct device *dev,
+                                             struct device_attribute *devattr,
+                                             char *buf)
+{
+        int result = 0;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+
+        mutex_lock(&data->update_lock);
+        if (nr & 1)
+                result = data->pwm_auto_point_hyst[nr / 2] >> 4;
+        else
+                result = data->pwm_auto_point_hyst[nr / 2] & 0x0f;
+        result = 1000 * (data->pwm_auto_point_temp[nr][point] - result);
+        mutex_unlock(&data->update_lock);
+
+        return sprintf(buf, "%d\n", result);
+}
+
+static ssize_t store_pwm_auto_point_temp_hyst(struct device *dev,
+                                              struct device_attribute *devattr,
+                                              const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+        long val = simple_strtol(buf, NULL, 10) / 1000;
+        u8 reg;
+
+        mutex_lock(&data->update_lock);
+        data->pwm_auto_point_temp[nr][point] =
+                f71882fg_read8(data, F71882FG_REG_POINT_TEMP(nr, point));
+        val = SENSORS_LIMIT(val, data->pwm_auto_point_temp[nr][point] - 15,
+                                data->pwm_auto_point_temp[nr][point]);
+        val = data->pwm_auto_point_temp[nr][point] - val;
+
+        reg = f71882fg_read8(data, F71882FG_REG_FAN_HYST(nr / 2));
+        if (nr & 1)
+                reg = (reg & 0x0f) | (val << 4);
+        else
+                reg = (reg & 0xf0) | val;
+
+        f71882fg_write8(data, F71882FG_REG_FAN_HYST(nr / 2), reg);
+        data->pwm_auto_point_hyst[nr / 2] = reg;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_interpolate(struct device *dev,
+                                    struct device_attribute *devattr, char *buf)
+{
+        int result;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+
+        result = (data->pwm_auto_point_mapping[nr] >> 4) & 1;
+
+        return sprintf(buf, "%d\n", result);
+}
+
+static ssize_t store_pwm_interpolate(struct device *dev,
+                                     struct device_attribute *devattr,
+                                     const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        unsigned long val = simple_strtoul(buf, NULL, 10);
+
+        mutex_lock(&data->update_lock);
+        data->pwm_auto_point_mapping[nr] =
+                f71882fg_read8(data, F71882FG_REG_POINT_MAPPING(nr));
+        if (val)
+                val = data->pwm_auto_point_mapping[nr] | (1 << 4);
+        else
+                val = data->pwm_auto_point_mapping[nr] & (~(1 << 4));
+        f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val);
+        data->pwm_auto_point_mapping[nr] = val;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_auto_point_channel(struct device *dev,
+                                           struct device_attribute *devattr,
+                                           char *buf)
+{
+        int result;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int temp_start = (data->type == f8000) ? 0 : 1;
+
+        result = 1 << ((data->pwm_auto_point_mapping[nr] & 3) - temp_start);
+
+        return sprintf(buf, "%d\n", result);
+}
+
+static ssize_t store_pwm_auto_point_channel(struct device *dev,
+                                            struct device_attribute *devattr,
+                                            const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int nr = to_sensor_dev_attr_2(devattr)->index;
+        int temp_start = (data->type == f8000) ? 0 : 1;
+        long val = simple_strtol(buf, NULL, 10);
+
+        switch (val) {
+        case 1:
+                val = 0;
+                break;
+        case 2:
+                val = 1;
+                break;
+        case 4:
+                val = 2;
+                break;
+        default:
+                return -EINVAL;
+        }
+        val += temp_start;
+        mutex_lock(&data->update_lock);
+        data->pwm_auto_point_mapping[nr] =
+                f71882fg_read8(data, F71882FG_REG_POINT_MAPPING(nr));
+        val = (data->pwm_auto_point_mapping[nr] & 0xfc) | val;
+        f71882fg_write8(data, F71882FG_REG_POINT_MAPPING(nr), val);
+        data->pwm_auto_point_mapping[nr] = val;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
+static ssize_t show_pwm_auto_point_temp(struct device *dev,
+                                        struct device_attribute *devattr,
+                                        char *buf)
+{
+        int result;
+        struct f71882fg_data *data = f71882fg_update_device(dev);
+        int pwm = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+
+        result = data->pwm_auto_point_temp[pwm][point];
+        return sprintf(buf, "%d\n", 1000 * result);
+}
+
+static ssize_t store_pwm_auto_point_temp(struct device *dev,
+                                         struct device_attribute *devattr,
+                                         const char *buf, size_t count)
+{
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        int pwm = to_sensor_dev_attr_2(devattr)->index;
+        int point = to_sensor_dev_attr_2(devattr)->nr;
+        long val = simple_strtol(buf, NULL, 10) / 1000;
+        val = SENSORS_LIMIT(val, 0, 255);
+
+        mutex_lock(&data->update_lock);
+        f71882fg_write8(data, F71882FG_REG_POINT_TEMP(pwm, point), val);
+        data->pwm_auto_point_temp[pwm][point] = val;
+        mutex_unlock(&data->update_lock);
+
+        return count;
+}
+
 static ssize_t show_name(struct device *dev, struct device_attribute *devattr,
         char *buf)
 {
-        return sprintf(buf, DRVNAME "\n");
+        struct f71882fg_data *data = dev_get_drvdata(dev);
+        return sprintf(buf, "%s\n", f71882fg_names[data->type]);
 }
 
+static int __devinit f71882fg_create_sysfs_files(struct platform_device *pdev,
+        struct sensor_device_attribute_2 *attr, int count)
+{
+        int err, i;
+
+        for (i = 0; i < count; i++) {
+                err = device_create_file(&pdev->dev, &attr[i].dev_attr);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
 
-static int __devinit f71882fg_probe(struct platform_device * pdev)
+static int __devinit f71882fg_probe(struct platform_device *pdev)
 {
         struct f71882fg_data *data;
-        int err, i;
+        struct f71882fg_sio_data *sio_data = pdev->dev.platform_data;
+        int err, i, nr_fans = (sio_data->type == f71882fg) ? 4 : 3;
         u8 start_reg;
 
-        if (!(data = kzalloc(sizeof(struct f71882fg_data), GFP_KERNEL)))
+        data = kzalloc(sizeof(struct f71882fg_data), GFP_KERNEL);
+        if (!data)
                 return -ENOMEM;
 
         data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
+        data->type = sio_data->type;
         mutex_init(&data->update_lock);
         platform_set_drvdata(pdev, data);
 
-        /* Register sysfs interface files */
-        for (i = 0; i < ARRAY_SIZE(f71882fg_dev_attr); i++) {
-                err = device_create_file(&pdev->dev, &f71882fg_dev_attr[i]);
-                if (err)
-                        goto exit_unregister_sysfs;
+        start_reg = f71882fg_read8(data, F71882FG_REG_START);
+        if (start_reg & 0x04) {
+                dev_warn(&pdev->dev, "Hardware monitor is powered down\n");
+                err = -ENODEV;
+                goto exit_free;
+        }
+        if (!(start_reg & 0x03)) {
+                dev_warn(&pdev->dev, "Hardware monitoring not activated\n");
+                err = -ENODEV;
+                goto exit_free;
         }
 
-        start_reg = f71882fg_read8(data, F71882FG_REG_START);
+        data->pwm_enable = f71882fg_read8(data, F71882FG_REG_PWM_ENABLE);
+        /* If it is a 71862 and the fan / pwm part is enabled sanity check
+           the pwm settings */
+        if (data->type == f71862fg && (start_reg & 0x02)) {
+                if ((data->pwm_enable & 0x15) != 0x15) {
+                        dev_err(&pdev->dev,
+                                "Invalid (reserved) pwm settings: 0x%02x\n",
+                                (unsigned int)data->pwm_enable);
+                        err = -ENODEV;
+                        goto exit_free;
+                }
+        }
+
+        /* Register sysfs interface files */
+        err = device_create_file(&pdev->dev, &dev_attr_name);
+        if (err)
+                goto exit_unregister_sysfs;
+
         if (start_reg & 0x01) {
-                for (i = 0; i < ARRAY_SIZE(f71882fg_in_temp_attr); i++) {
-                        err = device_create_file(&pdev->dev,
-                                        &f71882fg_in_temp_attr[i].dev_attr);
+                switch (data->type) {
+                case f71882fg:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f71882fg_in_temp_attr,
+                                        ARRAY_SIZE(f71882fg_in_temp_attr));
                         if (err)
                                 goto exit_unregister_sysfs;
+                        /* fall through! */
+                case f71862fg:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f718x2fg_in_temp_attr,
+                                        ARRAY_SIZE(f718x2fg_in_temp_attr));
+                        break;
+                case f8000:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f8000_in_temp_attr,
+                                        ARRAY_SIZE(f8000_in_temp_attr));
+                        break;
                 }
+                if (err)
+                        goto exit_unregister_sysfs;
         }
 
         if (start_reg & 0x02) {
-                for (i = 0; i < ARRAY_SIZE(f71882fg_fan_attr); i++) {
-                        err = device_create_file(&pdev->dev,
-                                        &f71882fg_fan_attr[i].dev_attr);
-                        if (err)
-                                goto exit_unregister_sysfs;
+                err = f71882fg_create_sysfs_files(pdev, fxxxx_fan_attr,
+                                        ARRAY_SIZE(fxxxx_fan_attr));
+                if (err)
+                        goto exit_unregister_sysfs;
+
+                switch (data->type) {
+                case f71862fg:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f71862fg_fan_attr,
+                                        ARRAY_SIZE(f71862fg_fan_attr));
+                        break;
+                case f71882fg:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f71882fg_fan_attr,
+                                        ARRAY_SIZE(f71882fg_fan_attr));
+                        break;
+                case f8000:
+                        err = f71882fg_create_sysfs_files(pdev,
+                                        f8000_fan_attr,
+                                        ARRAY_SIZE(f8000_fan_attr));
+                        break;
                 }
+                if (err)
+                        goto exit_unregister_sysfs;
+
+                for (i = 0; i < nr_fans; i++)
+                        dev_info(&pdev->dev, "Fan: %d is in %s mode\n", i + 1,
+                                 (data->pwm_enable & (1 << 2 * i)) ?
+                                 "duty-cycle" : "RPM");
         }
 
         data->hwmon_dev = hwmon_device_register(&pdev->dev);
         if (IS_ERR(data->hwmon_dev)) {
                 err = PTR_ERR(data->hwmon_dev);
+                data->hwmon_dev = NULL;
                 goto exit_unregister_sysfs;
         }
 
         return 0;
 
 exit_unregister_sysfs:
-        for (i = 0; i < ARRAY_SIZE(f71882fg_dev_attr); i++)
-                device_remove_file(&pdev->dev, &f71882fg_dev_attr[i]);
-
-        for (i = 0; i < ARRAY_SIZE(f71882fg_in_temp_attr); i++)
-                device_remove_file(&pdev->dev,
-                                        &f71882fg_in_temp_attr[i].dev_attr);
-
-        for (i = 0; i < ARRAY_SIZE(f71882fg_fan_attr); i++)
-                device_remove_file(&pdev->dev, &f71882fg_fan_attr[i].dev_attr);
-
+        f71882fg_remove(pdev); /* Will unregister the sysfs files for us */
+        return err; /* f71882fg_remove() also frees our data */
+exit_free:
         kfree(data);
-
         return err;
 }
 
-static int __devexit f71882fg_remove(struct platform_device *pdev)
+static int f71882fg_remove(struct platform_device *pdev)
 {
         int i;
         struct f71882fg_data *data = platform_get_drvdata(pdev);
 
         platform_set_drvdata(pdev, NULL);
-        hwmon_device_unregister(data->hwmon_dev);
+        if (data->hwmon_dev)
+                hwmon_device_unregister(data->hwmon_dev);
+
+        /* Note we are not looping over all attr arrays we have as the ones
+           below are supersets of the ones skipped. */
+        device_remove_file(&pdev->dev, &dev_attr_name);
 
-        for (i = 0; i < ARRAY_SIZE(f71882fg_dev_attr); i++)
-                device_remove_file(&pdev->dev, &f71882fg_dev_attr[i]);
+        for (i = 0; i < ARRAY_SIZE(f718x2fg_in_temp_attr); i++)
+                device_remove_file(&pdev->dev,
+                                        &f718x2fg_in_temp_attr[i].dev_attr);
 
         for (i = 0; i < ARRAY_SIZE(f71882fg_in_temp_attr); i++)
                 device_remove_file(&pdev->dev,
                                         &f71882fg_in_temp_attr[i].dev_attr);
 
+        for (i = 0; i < ARRAY_SIZE(fxxxx_fan_attr); i++)
+                device_remove_file(&pdev->dev, &fxxxx_fan_attr[i].dev_attr);
+
         for (i = 0; i < ARRAY_SIZE(f71882fg_fan_attr); i++)
                 device_remove_file(&pdev->dev, &f71882fg_fan_attr[i].dev_attr);
 
+        for (i = 0; i < ARRAY_SIZE(f8000_fan_attr); i++)
+                device_remove_file(&pdev->dev, &f8000_fan_attr[i].dev_attr);
+
         kfree(data);
 
         return 0;
 }
 
-static int __init f71882fg_find(int sioaddr, unsigned short *address)
+static int __init f71882fg_find(int sioaddr, unsigned short *address,
+        struct f71882fg_sio_data *sio_data)
 {
         int err = -ENODEV;
         u16 devid;
-        u8 start_reg;
-        struct f71882fg_data data;
 
         superio_enter(sioaddr);
 
@@ -842,7 +1877,17 @@ static int __init f71882fg_find(int sioaddr, unsigned short *address)
         }
 
         devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
-        if (devid != SIO_F71882_ID) {
+        switch (devid) {
+        case SIO_F71862_ID:
+                sio_data->type = f71862fg;
+                break;
+        case SIO_F71882_ID:
+                sio_data->type = f71882fg;
+                break;
+        case SIO_F8000_ID:
+                sio_data->type = f8000;
+                break;
+        default:
                 printk(KERN_INFO DRVNAME ": Unsupported Fintek device\n");
                 goto exit;
         }
@@ -861,24 +1906,17 @@ static int __init f71882fg_find(int sioaddr, unsigned short *address)
         }
         *address &= ~(REGION_LENGTH - 1);       /* Ignore 3 LSB */
 
-        data.addr = *address;
-        start_reg = f71882fg_read8(&data, F71882FG_REG_START);
-        if (!(start_reg & 0x03)) {
-                printk(KERN_WARNING DRVNAME
-                        ": Hardware monitoring not activated\n");
-                goto exit;
-        }
-
         err = 0;
-        printk(KERN_INFO DRVNAME ": Found F71882FG chip at %#x, revision %d\n",
-                (unsigned int)*address,
+        printk(KERN_INFO DRVNAME ": Found %s chip at %#x, revision %d\n",
+                f71882fg_names[sio_data->type], (unsigned int)*address,
                 (int)superio_inb(sioaddr, SIO_REG_DEVREV));
 exit:
         superio_exit(sioaddr);
         return err;
 }
 
-static int __init f71882fg_device_add(unsigned short address)
+static int __init f71882fg_device_add(unsigned short address,
+        const struct f71882fg_sio_data *sio_data)
 {
         struct resource res = {
                 .start  = address,
@@ -892,12 +1930,23 @@ static int __init f71882fg_device_add(unsigned short address)
                 return -ENOMEM;
 
         res.name = f71882fg_pdev->name;
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                return err;
+
         err = platform_device_add_resources(f71882fg_pdev, &res, 1);
         if (err) {
                 printk(KERN_ERR DRVNAME ": Device resource addition failed\n");
                 goto exit_device_put;
         }
 
+        err = platform_device_add_data(f71882fg_pdev, sio_data,
+                                       sizeof(struct f71882fg_sio_data));
+        if (err) {
+                printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
+                goto exit_device_put;
+        }
+
         err = platform_device_add(f71882fg_pdev);
         if (err) {
                 printk(KERN_ERR DRVNAME ": Device addition failed\n");
@@ -916,14 +1965,20 @@ static int __init f71882fg_init(void)
 {
         int err = -ENODEV;
         unsigned short address;
+        struct f71882fg_sio_data sio_data;
+
+        memset(&sio_data, 0, sizeof(sio_data));
 
-        if (f71882fg_find(0x2e, &address) && f71882fg_find(0x4e, &address))
+        if (f71882fg_find(0x2e, &address, &sio_data) &&
+            f71882fg_find(0x4e, &address, &sio_data))
                 goto exit;
 
-        if ((err = platform_driver_register(&f71882fg_driver)))
+        err = platform_driver_register(&f71882fg_driver);
+        if (err)
                 goto exit;
 
-        if ((err = f71882fg_device_add(address)))
+        err = f71882fg_device_add(address, &sio_data);
+        if (err)
                 goto exit_driver;
 
         return 0;
@@ -941,7 +1996,7 @@ static void __exit f71882fg_exit(void)
 }
 
 MODULE_DESCRIPTION("F71882FG Hardware Monitoring Driver");
-MODULE_AUTHOR("Hans Edgington (hans@edgington.nl)");
+MODULE_AUTHOR("Hans Edgington, Hans de Goede (hdegoede@redhat.com)");
 MODULE_LICENSE("GPL");
 
 module_init(f71882fg_init);
diff --git a/drivers/hwmon/fschmd.c b/drivers/hwmon/fschmd.c
index 967170368933..d07f4ef75092 100644
--- a/drivers/hwmon/fschmd.c
+++ b/drivers/hwmon/fschmd.c
@@ -1,6 +1,6 @@
 /* fschmd.c
  *
- * Copyright (C) 2007 Hans de Goede <j.w.r.degoede@hhs.nl>
+ * Copyright (C) 2007,2008 Hans de Goede <hdegoede@redhat.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -42,11 +42,20 @@
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
 #include <linux/dmi.h>
+#include <linux/fs.h>
+#include <linux/watchdog.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <linux/kref.h>
 
 /* Addresses to scan */
 static const unsigned short normal_i2c[] = { 0x73, I2C_CLIENT_END };
 
 /* Insmod parameters */
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
+        __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 I2C_CLIENT_INSMOD_5(fscpos, fscher, fscscy, fschrc, fschmd);
 
 /*
@@ -63,19 +72,26 @@ I2C_CLIENT_INSMOD_5(fscpos, fscher, fscscy, fschrc, fschmd);
 #define FSCHMD_REG_EVENT_STATE          0x04
 #define FSCHMD_REG_CONTROL              0x05
 
-#define FSCHMD_CONTROL_ALERT_LED_MASK   0x01
+#define FSCHMD_CONTROL_ALERT_LED        0x01
 
-/* watchdog (support to be implemented) */
+/* watchdog */
 #define FSCHMD_REG_WDOG_PRESET          0x28
 #define FSCHMD_REG_WDOG_STATE           0x23
 #define FSCHMD_REG_WDOG_CONTROL         0x21
 
+#define FSCHMD_WDOG_CONTROL_TRIGGER     0x10
+#define FSCHMD_WDOG_CONTROL_STARTED     0x10 /* the same as trigger */
+#define FSCHMD_WDOG_CONTROL_STOP        0x20
+#define FSCHMD_WDOG_CONTROL_RESOLUTION  0x40
+
+#define FSCHMD_WDOG_STATE_CARDRESET     0x02
+
 /* voltages, weird order is to keep the same order as the old drivers */
 static const u8 FSCHMD_REG_VOLT[3] = { 0x45, 0x42, 0x48 };
 
 /* minimum pwm at which the fan is driven (pwm can by increased depending on
    the temp. Notice that for the scy some fans share there minimum speed.
-   Also notice that with the scy the sensor order is different then with the
+   Also notice that with the scy the sensor order is different than with the
    other chips, this order was in the 2.4 driver and kept for consistency. */
 static const u8 FSCHMD_REG_FAN_MIN[5][6] = {
         { 0x55, 0x65 },                                 /* pos */
@@ -115,8 +131,8 @@ static const u8 FSCHMD_REG_FAN_RIPPLE[5][6] = {
 static const int FSCHMD_NO_FAN_SENSORS[5] = { 3, 3, 6, 4, 5 };
 
 /* Fan status register bitmasks */
-#define FSCHMD_FAN_ALARM_MASK           0x04 /* called fault by FSC! */
-#define FSCHMD_FAN_NOT_PRESENT_MASK     0x08 /* not documented */
+#define FSCHMD_FAN_ALARM        0x04 /* called fault by FSC! */
+#define FSCHMD_FAN_NOT_PRESENT  0x08 /* not documented */
 
 
 /* actual temperature registers */
@@ -158,14 +174,11 @@ static const u8 FSCHER_REG_TEMP_AUTOP2[] =	{ 0x75, 0x85, 0x95 }; */
 static const int FSCHMD_NO_TEMP_SENSORS[5] = { 3, 3, 4, 3, 5 };
 
 /* temp status register bitmasks */
-#define FSCHMD_TEMP_WORKING_MASK        0x01
-#define FSCHMD_TEMP_ALERT_MASK          0x02
+#define FSCHMD_TEMP_WORKING     0x01
+#define FSCHMD_TEMP_ALERT       0x02
 /* there only really is an alarm if the sensor is working and alert == 1 */
 #define FSCHMD_TEMP_ALARM_MASK \
-        (FSCHMD_TEMP_WORKING_MASK | FSCHMD_TEMP_ALERT_MASK)
-
-/* our driver name */
-#define FSCHMD_NAME "fschmd"
+        (FSCHMD_TEMP_WORKING | FSCHMD_TEMP_ALERT)
 
 /*
  * Functions declarations
@@ -195,7 +208,7 @@ MODULE_DEVICE_TABLE(i2c, fschmd_id);
 static struct i2c_driver fschmd_driver = {
         .class          = I2C_CLASS_HWMON,
         .driver = {
-                .name   = FSCHMD_NAME,
+                .name   = "fschmd",
         },
         .probe          = fschmd_probe,
         .remove         = fschmd_remove,
@@ -209,14 +222,26 @@ static struct i2c_driver fschmd_driver = {
  */
 
 struct fschmd_data {
+        struct i2c_client *client;
         struct device *hwmon_dev;
         struct mutex update_lock;
+        struct mutex watchdog_lock;
+        struct list_head list; /* member of the watchdog_data_list */
+        struct kref kref;
+        struct miscdevice watchdog_miscdev;
         int kind;
+        unsigned long watchdog_is_open;
+        char watchdog_expect_close;
+        char watchdog_name[10]; /* must be unique to avoid sysfs conflict */
         char valid; /* zero until following fields are valid */
         unsigned long last_updated; /* in jiffies */
 
         /* register values */
+        u8 revision;            /* chip revision */
         u8 global_control;      /* global control register */
+        u8 watchdog_control;    /* watchdog control register */
+        u8 watchdog_state;      /* watchdog status register */
+        u8 watchdog_preset;     /* watchdog counter preset on trigger val */
         u8 volt[3];             /* 12, 5, battery voltage */
         u8 temp_act[5];         /* temperature */
         u8 temp_status[5];      /* status of sensor */
@@ -228,11 +253,28 @@ struct fschmd_data {
 };
 
 /* Global variables to hold information read from special DMI tables, which are
-   available on FSC machines with an fscher or later chip. */
+   available on FSC machines with an fscher or later chip. There is no need to
+   protect these with a lock as they are only modified from our attach function
+   which always gets called with the i2c-core lock held and never accessed
+   before the attach function is done with them. */
 static int dmi_mult[3] = { 490, 200, 100 };
 static int dmi_offset[3] = { 0, 0, 0 };
 static int dmi_vref = -1;
 
+/* Somewhat ugly :( global data pointer list with all fschmd devices, so that
+   we can find our device data as when using misc_register there is no other
+   method to get to ones device data from the open fop. */
+static LIST_HEAD(watchdog_data_list);
+/* Note this lock not only protect list access, but also data.kref access */
+static DEFINE_MUTEX(watchdog_data_mutex);
+
+/* Release our data struct when we're detached from the i2c client *and* all
+   references to our watchdog device are released */
+static void fschmd_release_resources(struct kref *ref)
+{
+        struct fschmd_data *data = container_of(ref, struct fschmd_data, kref);
+        kfree(data);
+}
 
 /*
  * Sysfs attr show / store functions
@@ -300,7 +342,7 @@ static ssize_t show_temp_fault(struct device *dev,
         struct fschmd_data *data = fschmd_update_device(dev);
 
         /* bit 0 set means sensor working ok, so no fault! */
-        if (data->temp_status[index] & FSCHMD_TEMP_WORKING_MASK)
+        if (data->temp_status[index] & FSCHMD_TEMP_WORKING)
                 return sprintf(buf, "0\n");
         else
                 return sprintf(buf, "1\n");
@@ -385,7 +427,7 @@ static ssize_t show_fan_alarm(struct device *dev,
         int index = to_sensor_dev_attr(devattr)->index;
         struct fschmd_data *data = fschmd_update_device(dev);
 
-        if (data->fan_status[index] & FSCHMD_FAN_ALARM_MASK)
+        if (data->fan_status[index] & FSCHMD_FAN_ALARM)
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
@@ -397,7 +439,7 @@ static ssize_t show_fan_fault(struct device *dev,
         int index = to_sensor_dev_attr(devattr)->index;
         struct fschmd_data *data = fschmd_update_device(dev);
 
-        if (data->fan_status[index] & FSCHMD_FAN_NOT_PRESENT_MASK)
+        if (data->fan_status[index] & FSCHMD_FAN_NOT_PRESENT)
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
@@ -449,7 +491,7 @@ static ssize_t show_alert_led(struct device *dev,
 {
         struct fschmd_data *data = fschmd_update_device(dev);
 
-        if (data->global_control & FSCHMD_CONTROL_ALERT_LED_MASK)
+        if (data->global_control & FSCHMD_CONTROL_ALERT_LED)
                 return sprintf(buf, "1\n");
         else
                 return sprintf(buf, "0\n");
@@ -467,9 +509,9 @@ static ssize_t store_alert_led(struct device *dev,
         reg = i2c_smbus_read_byte_data(to_i2c_client(dev), FSCHMD_REG_CONTROL);
 
         if (v)
-                reg |= FSCHMD_CONTROL_ALERT_LED_MASK;
+                reg |= FSCHMD_CONTROL_ALERT_LED;
         else
-                reg &= ~FSCHMD_CONTROL_ALERT_LED_MASK;
+                reg &= ~FSCHMD_CONTROL_ALERT_LED;
 
         i2c_smbus_write_byte_data(to_i2c_client(dev), FSCHMD_REG_CONTROL, reg);
 
@@ -551,7 +593,265 @@ static struct sensor_device_attribute fschmd_fan_attr[] = {
 
 
 /*
- * Real code
+ * Watchdog routines
+ */
+
+static int watchdog_set_timeout(struct fschmd_data *data, int timeout)
+{
+        int ret, resolution;
+        int kind = data->kind + 1; /* 0-x array index -> 1-x module param */
+
+        /* 2 second or 60 second resolution? */
+        if (timeout <= 510 || kind == fscpos || kind == fscscy)
+                resolution = 2;
+        else
+                resolution = 60;
+
+        if (timeout < resolution || timeout > (resolution * 255))
+                return -EINVAL;
+
+        mutex_lock(&data->watchdog_lock);
+        if (!data->client) {
+                ret = -ENODEV;
+                goto leave;
+        }
+
+        if (resolution == 2)
+                data->watchdog_control &= ~FSCHMD_WDOG_CONTROL_RESOLUTION;
+        else
+                data->watchdog_control |= FSCHMD_WDOG_CONTROL_RESOLUTION;
+
+        data->watchdog_preset = DIV_ROUND_UP(timeout, resolution);
+
+        /* Write new timeout value */
+        i2c_smbus_write_byte_data(data->client, FSCHMD_REG_WDOG_PRESET,
+                data->watchdog_preset);
+        /* Write new control register, do not trigger! */
+        i2c_smbus_write_byte_data(data->client, FSCHMD_REG_WDOG_CONTROL,
+                data->watchdog_control & ~FSCHMD_WDOG_CONTROL_TRIGGER);
+
+        ret = data->watchdog_preset * resolution;
+
+leave:
+        mutex_unlock(&data->watchdog_lock);
+        return ret;
+}
+
+static int watchdog_get_timeout(struct fschmd_data *data)
+{
+        int timeout;
+
+        mutex_lock(&data->watchdog_lock);
+        if (data->watchdog_control & FSCHMD_WDOG_CONTROL_RESOLUTION)
+                timeout = data->watchdog_preset * 60;
+        else
+                timeout = data->watchdog_preset * 2;
+        mutex_unlock(&data->watchdog_lock);
+
+        return timeout;
+}
+
+static int watchdog_trigger(struct fschmd_data *data)
+{
+        int ret = 0;
+
+        mutex_lock(&data->watchdog_lock);
+        if (!data->client) {
+                ret = -ENODEV;
+                goto leave;
+        }
+
+        data->watchdog_control |= FSCHMD_WDOG_CONTROL_TRIGGER;
+        i2c_smbus_write_byte_data(data->client, FSCHMD_REG_WDOG_CONTROL,
+                                        data->watchdog_control);
+leave:
+        mutex_unlock(&data->watchdog_lock);
+        return ret;
+}
+
+static int watchdog_stop(struct fschmd_data *data)
+{
+        int ret = 0;
+
+        mutex_lock(&data->watchdog_lock);
+        if (!data->client) {
+                ret = -ENODEV;
+                goto leave;
+        }
+
+        data->watchdog_control &= ~FSCHMD_WDOG_CONTROL_STARTED;
+        /* Don't store the stop flag in our watchdog control register copy, as
+           its a write only bit (read always returns 0) */
+        i2c_smbus_write_byte_data(data->client, FSCHMD_REG_WDOG_CONTROL,
+                data->watchdog_control | FSCHMD_WDOG_CONTROL_STOP);
+leave:
+        mutex_unlock(&data->watchdog_lock);
+        return ret;
+}
+
+static int watchdog_open(struct inode *inode, struct file *filp)
+{
+        struct fschmd_data *pos, *data = NULL;
+
+        /* We get called from drivers/char/misc.c with misc_mtx hold, and we
+           call misc_register() from fschmd_probe() with watchdog_data_mutex
+           hold, as misc_register() takes the misc_mtx lock, this is a possible
+           deadlock, so we use mutex_trylock here. */
+        if (!mutex_trylock(&watchdog_data_mutex))
+                return -ERESTARTSYS;
+        list_for_each_entry(pos, &watchdog_data_list, list) {
+                if (pos->watchdog_miscdev.minor == iminor(inode)) {
+                        data = pos;
+                        break;
+                }
+        }
+        /* Note we can never not have found data, so we don't check for this */
+        kref_get(&data->kref);
+        mutex_unlock(&watchdog_data_mutex);
+
+        if (test_and_set_bit(0, &data->watchdog_is_open))
+                return -EBUSY;
+
+        /* Start the watchdog */
+        watchdog_trigger(data);
+        filp->private_data = data;
+
+        return nonseekable_open(inode, filp);
+}
+
+static int watchdog_release(struct inode *inode, struct file *filp)
+{
+        struct fschmd_data *data = filp->private_data;
+
+        if (data->watchdog_expect_close) {
+                watchdog_stop(data);
+                data->watchdog_expect_close = 0;
+        } else {
+                watchdog_trigger(data);
+                dev_crit(&data->client->dev,
+                        "unexpected close, not stopping watchdog!\n");
+        }
+
+        clear_bit(0, &data->watchdog_is_open);
+
+        mutex_lock(&watchdog_data_mutex);
+        kref_put(&data->kref, fschmd_release_resources);
+        mutex_unlock(&watchdog_data_mutex);
+
+        return 0;
+}
+
+static ssize_t watchdog_write(struct file *filp, const char __user *buf,
+        size_t count, loff_t *offset)
+{
+        size_t ret;
+        struct fschmd_data *data = filp->private_data;
+
+        if (count) {
+                if (!nowayout) {
+                        size_t i;
+
+                        /* Clear it in case it was set with a previous write */
+                        data->watchdog_expect_close = 0;
+
+                        for (i = 0; i != count; i++) {
+                                char c;
+                                if (get_user(c, buf + i))
+                                        return -EFAULT;
+                                if (c == 'V')
+                                        data->watchdog_expect_close = 1;
+                        }
+                }
+                ret = watchdog_trigger(data);
+                if (ret < 0)
+                        return ret;
+        }
+        return count;
+}
+
+static int watchdog_ioctl(struct inode *inode, struct file *filp,
+        unsigned int cmd, unsigned long arg)
+{
+        static struct watchdog_info ident = {
+                .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
+                                WDIOF_CARDRESET,
+                .identity = "FSC watchdog"
+        };
+        int i, ret = 0;
+        struct fschmd_data *data = filp->private_data;
+
+        switch (cmd) {
+        case WDIOC_GETSUPPORT:
+                ident.firmware_version = data->revision;
+                if (!nowayout)
+                        ident.options |= WDIOF_MAGICCLOSE;
+                if (copy_to_user((void __user *)arg, &ident, sizeof(ident)))
+                        ret = -EFAULT;
+                break;
+
+        case WDIOC_GETSTATUS:
+                ret = put_user(0, (int __user *)arg);
+                break;
+
+        case WDIOC_GETBOOTSTATUS:
+                if (data->watchdog_state & FSCHMD_WDOG_STATE_CARDRESET)
+                        ret = put_user(WDIOF_CARDRESET, (int __user *)arg);
+                else
+                        ret = put_user(0, (int __user *)arg);
+                break;
+
+        case WDIOC_KEEPALIVE:
+                ret = watchdog_trigger(data);
+                break;
+
+        case WDIOC_GETTIMEOUT:
+                i = watchdog_get_timeout(data);
+                ret = put_user(i, (int __user *)arg);
+                break;
+
+        case WDIOC_SETTIMEOUT:
+                if (get_user(i, (int __user *)arg)) {
+                        ret = -EFAULT;
+                        break;
+                }
+                ret = watchdog_set_timeout(data, i);
+                if (ret > 0)
+                        ret = put_user(ret, (int __user *)arg);
+                break;
+
+        case WDIOC_SETOPTIONS:
+                if (get_user(i, (int __user *)arg)) {
+                        ret = -EFAULT;
+                        break;
+                }
+
+                if (i & WDIOS_DISABLECARD)
+                        ret = watchdog_stop(data);
+                else if (i & WDIOS_ENABLECARD)
+                        ret = watchdog_trigger(data);
+                else
+                        ret = -EINVAL;
+
+                break;
+        default:
+                ret = -ENOTTY;
+        }
+
+        return ret;
+}
+
+static struct file_operations watchdog_fops = {
+        .owner = THIS_MODULE,
+        .llseek = no_llseek,
+        .open = watchdog_open,
+        .release = watchdog_release,
+        .write = watchdog_write,
+        .ioctl = watchdog_ioctl,
+};
+
+
+/*
+ * Detect, register, unregister and update device functions
  */
 
 /* DMI decode routine to read voltage scaling factors from special DMI tables,
@@ -661,9 +961,9 @@ static int fschmd_probe(struct i2c_client *client,
                         const struct i2c_device_id *id)
 {
         struct fschmd_data *data;
-        u8 revision;
         const char * const names[5] = { "Poseidon", "Hermes", "Scylla",
                                         "Heracles", "Heimdall" };
+        const int watchdog_minors[] = { WATCHDOG_MINOR, 212, 213, 214, 215 };
         int i, err;
         enum chips kind = id->driver_data;
 
@@ -673,6 +973,13 @@ static int fschmd_probe(struct i2c_client *client,
 
         i2c_set_clientdata(client, data);
         mutex_init(&data->update_lock);
+        mutex_init(&data->watchdog_lock);
+        INIT_LIST_HEAD(&data->list);
+        kref_init(&data->kref);
+        /* Store client pointer in our data struct for watchdog usage
+           (where the client is found through a data ptr instead of the
+           otherway around) */
+        data->client = client;
 
         if (kind == fscpos) {
                 /* The Poseidon has hardwired temp limits, fill these
@@ -683,16 +990,27 @@ static int fschmd_probe(struct i2c_client *client,
         }
 
         /* Read the special DMI table for fscher and newer chips */
-        if (kind == fscher || kind >= fschrc) {
+        if ((kind == fscher || kind >= fschrc) && dmi_vref == -1) {
                 dmi_walk(fschmd_dmi_decode);
                 if (dmi_vref == -1) {
-                        printk(KERN_WARNING FSCHMD_NAME
-                                ": Couldn't get voltage scaling factors from "
+                        dev_warn(&client->dev,
+                                "Couldn't get voltage scaling factors from "
                                 "BIOS DMI table, using builtin defaults\n");
                         dmi_vref = 33;
                 }
         }
 
+        /* Read in some never changing registers */
+        data->revision = i2c_smbus_read_byte_data(client, FSCHMD_REG_REVISION);
+        data->global_control = i2c_smbus_read_byte_data(client,
+                                        FSCHMD_REG_CONTROL);
+        data->watchdog_control = i2c_smbus_read_byte_data(client,
+                                        FSCHMD_REG_WDOG_CONTROL);
+        data->watchdog_state = i2c_smbus_read_byte_data(client,
+                                        FSCHMD_REG_WDOG_STATE);
+        data->watchdog_preset = i2c_smbus_read_byte_data(client,
+                                        FSCHMD_REG_WDOG_PRESET);
+
         /* i2c kind goes from 1-5, we want from 0-4 to address arrays */
         data->kind = kind - 1;
 
@@ -735,9 +1053,43 @@ static int fschmd_probe(struct i2c_client *client,
                 goto exit_detach;
         }
 
-        revision = i2c_smbus_read_byte_data(client, FSCHMD_REG_REVISION);
-        printk(KERN_INFO FSCHMD_NAME ": Detected FSC %s chip, revision: %d\n",
-                names[data->kind], (int) revision);
+        /* We take the data_mutex lock early so that watchdog_open() cannot
+           run when misc_register() has completed, but we've not yet added
+           our data to the watchdog_data_list (and set the default timeout) */
+        mutex_lock(&watchdog_data_mutex);
+        for (i = 0; i < ARRAY_SIZE(watchdog_minors); i++) {
+                /* Register our watchdog part */
+                snprintf(data->watchdog_name, sizeof(data->watchdog_name),
+                        "watchdog%c", (i == 0) ? '\0' : ('0' + i));
+                data->watchdog_miscdev.name = data->watchdog_name;
+                data->watchdog_miscdev.fops = &watchdog_fops;
+                data->watchdog_miscdev.minor = watchdog_minors[i];
+                err = misc_register(&data->watchdog_miscdev);
+                if (err == -EBUSY)
+                        continue;
+                if (err) {
+                        data->watchdog_miscdev.minor = 0;
+                        dev_err(&client->dev,
+                                "Registering watchdog chardev: %d\n", err);
+                        break;
+                }
+
+                list_add(&data->list, &watchdog_data_list);
+                watchdog_set_timeout(data, 60);
+                dev_info(&client->dev,
+                        "Registered watchdog chardev major 10, minor: %d\n",
+                        watchdog_minors[i]);
+                break;
+        }
+        if (i == ARRAY_SIZE(watchdog_minors)) {
+                data->watchdog_miscdev.minor = 0;
+                dev_warn(&client->dev, "Couldn't register watchdog chardev "
+                        "(due to no free minor)\n");
+        }
+        mutex_unlock(&watchdog_data_mutex);
+
+        dev_info(&client->dev, "Detected FSC %s chip, revision: %d\n",
+                names[data->kind], (int) data->revision);
 
         return 0;
 
@@ -751,6 +1103,24 @@ static int fschmd_remove(struct i2c_client *client)
         struct fschmd_data *data = i2c_get_clientdata(client);
         int i;
 
+        /* Unregister the watchdog (if registered) */
+        if (data->watchdog_miscdev.minor) {
+                misc_deregister(&data->watchdog_miscdev);
+                if (data->watchdog_is_open) {
+                        dev_warn(&client->dev,
+                                "i2c client detached with watchdog open! "
+                                "Stopping watchdog.\n");
+                        watchdog_stop(data);
+                }
+                mutex_lock(&watchdog_data_mutex);
+                list_del(&data->list);
+                mutex_unlock(&watchdog_data_mutex);
+                /* Tell the watchdog code the client is gone */
+                mutex_lock(&data->watchdog_lock);
+                data->client = NULL;
+                mutex_unlock(&data->watchdog_lock);
+        }
+
         /* Check if registered in case we're called from fschmd_detect
            to cleanup after an error */
         if (data->hwmon_dev)
@@ -765,7 +1135,10 @@ static int fschmd_remove(struct i2c_client *client)
                 device_remove_file(&client->dev,
                                         &fschmd_fan_attr[i].dev_attr);
 
-        kfree(data);
+        mutex_lock(&watchdog_data_mutex);
+        kref_put(&data->kref, fschmd_release_resources);
+        mutex_unlock(&watchdog_data_mutex);
+
         return 0;
 }
 
@@ -798,7 +1171,7 @@ static struct fschmd_data *fschmd_update_device(struct device *dev)
                                         data->temp_act[i] < data->temp_max[i])
                                 i2c_smbus_write_byte_data(client,
                                         FSCHMD_REG_TEMP_STATE[data->kind][i],
-                                        FSCHMD_TEMP_ALERT_MASK);
+                                        FSCHMD_TEMP_ALERT);
                 }
 
                 for (i = 0; i < FSCHMD_NO_FAN_SENSORS[data->kind]; i++) {
@@ -816,28 +1189,17 @@ static struct fschmd_data *fschmd_update_device(struct device *dev)
                                         FSCHMD_REG_FAN_MIN[data->kind][i]);
 
                         /* reset fan status if speed is back to > 0 */
-                        if ((data->fan_status[i] & FSCHMD_FAN_ALARM_MASK) &&
+                        if ((data->fan_status[i] & FSCHMD_FAN_ALARM) &&
                                         data->fan_act[i])
                                 i2c_smbus_write_byte_data(client,
                                         FSCHMD_REG_FAN_STATE[data->kind][i],
-                                        FSCHMD_FAN_ALARM_MASK);
+                                        FSCHMD_FAN_ALARM);
                 }
 
                 for (i = 0; i < 3; i++)
                         data->volt[i] = i2c_smbus_read_byte_data(client,
                                                 FSCHMD_REG_VOLT[i]);
 
-                data->global_control = i2c_smbus_read_byte_data(client,
-                                                FSCHMD_REG_CONTROL);
-
-                /* To be implemented in the future
-                data->watchdog[0] = i2c_smbus_read_byte_data(client,
-                                                FSCHMD_REG_WDOG_PRESET);
-                data->watchdog[1] = i2c_smbus_read_byte_data(client,
-                                                FSCHMD_REG_WDOG_STATE);
-                data->watchdog[2] = i2c_smbus_read_byte_data(client,
-                                                FSCHMD_REG_WDOG_CONTROL); */
-
                 data->last_updated = jiffies;
                 data->valid = 1;
         }
@@ -857,7 +1219,7 @@ static void __exit fschmd_exit(void)
         i2c_del_driver(&fschmd_driver);
 }
 
-MODULE_AUTHOR("Hans de Goede <j.w.r.degoede@hhs.nl>");
+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
 MODULE_DESCRIPTION("FSC Poseidon, Hermes, Scylla, Heracles and "
                         "Heimdall driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/i5k_amb.c b/drivers/hwmon/i5k_amb.c
index 2ede9388096b..27d7f72a5f11 100644
--- a/drivers/hwmon/i5k_amb.c
+++ b/drivers/hwmon/i5k_amb.c
@@ -490,6 +490,13 @@ static unsigned long chipset_ids[] = {
         0
 };
 
+static struct pci_device_id i5k_amb_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5000_ERR) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR) },
+        { 0, }
+};
+MODULE_DEVICE_TABLE(pci, i5k_amb_ids);
+
 static int __devinit i5k_amb_probe(struct platform_device *pdev)
 {
         struct i5k_amb_data *data;
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index b74c95735f95..95a99c590da2 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -14,6 +14,7 @@
               IT8712F  Super I/O chip w/LPC interface
               IT8716F  Super I/O chip w/LPC interface
               IT8718F  Super I/O chip w/LPC interface
+              IT8720F  Super I/O chip w/LPC interface
               IT8726F  Super I/O chip w/LPC interface
               Sis950   A clone of the IT8705F
 
@@ -48,11 +49,12 @@
 #include <linux/sysfs.h>
 #include <linux/string.h>
 #include <linux/dmi.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 #define DRVNAME "it87"
 
-enum chips { it87, it8712, it8716, it8718 };
+enum chips { it87, it8712, it8716, it8718, it8720 };
 
 static unsigned short force_id;
 module_param(force_id, ushort, 0);
@@ -64,7 +66,10 @@ static struct platform_device *pdev;
 #define DEV     0x07    /* Register: Logical device select */
 #define VAL     0x2f    /* The value to read/write */
 #define PME     0x04    /* The device with the fan registers in it */
-#define GPIO    0x07    /* The device with the IT8718F VID value in it */
+
+/* The device with the IT8718F/IT8720F VID value in it */
+#define GPIO    0x07
+
 #define DEVID   0x20    /* Register: Device ID */
 #define DEVREV  0x22    /* Register: Device Revision */
 
@@ -113,6 +118,7 @@ superio_exit(void)
 #define IT8705F_DEVID 0x8705
 #define IT8716F_DEVID 0x8716
 #define IT8718F_DEVID 0x8718
+#define IT8720F_DEVID 0x8720
 #define IT8726F_DEVID 0x8726
 #define IT87_ACT_REG  0x30
 #define IT87_BASE_REG 0x60
@@ -150,8 +156,8 @@ static int fix_pwm_polarity;
 #define IT87_REG_ALARM2        0x02
 #define IT87_REG_ALARM3        0x03
 
-/* The IT8718F has the VID value in a different register, in Super-I/O
-   configuration space. */
+/* The IT8718F and IT8720F have the VID value in a different register, in
+   Super-I/O configuration space. */
 #define IT87_REG_VID           0x0a
 /* The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
    for fan divisors. Later IT8712F revisions must use 16-bit tachometer
@@ -282,7 +288,8 @@ static inline int has_16bit_fans(const struct it87_data *data)
         return (data->type == it87 && data->revision >= 0x03)
             || (data->type == it8712 && data->revision >= 0x08)
             || data->type == it8716
-            || data->type == it8718;
+            || data->type == it8718
+            || data->type == it8720;
 }
 
 static int it87_probe(struct platform_device *pdev);
@@ -992,6 +999,9 @@ static int __init it87_find(unsigned short *address,
         case IT8718F_DEVID:
                 sio_data->type = it8718;
                 break;
+        case IT8720F_DEVID:
+                sio_data->type = it8720;
+                break;
         case 0xffff:    /* No device at all */
                 goto exit;
         default:
@@ -1022,7 +1032,8 @@ static int __init it87_find(unsigned short *address,
                 int reg;
 
                 superio_select(GPIO);
-                if (chip_type == it8718)
+                if ((chip_type == it8718) ||
+                    (chip_type == it8720))
                         sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
 
                 reg = superio_inb(IT87_SIO_PINX2_REG);
@@ -1068,6 +1079,7 @@ static int __devinit it87_probe(struct platform_device *pdev)
                 "it8712",
                 "it8716",
                 "it8718",
+                "it8720",
         };
 
         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
@@ -1226,7 +1238,7 @@ static int __devinit it87_probe(struct platform_device *pdev)
         }
 
         if (data->type == it8712 || data->type == it8716
-         || data->type == it8718) {
+         || data->type == it8718 || data->type == it8720) {
                 data->vrm = vid_which_vrm();
                 /* VID reading from Super-I/O config space if available */
                 data->vid = sio_data->vid_value;
@@ -1374,7 +1386,7 @@ static void __devinit it87_init_device(struct platform_device *pdev)
                         it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
         }
 
-        /* Check if temperature channnels are reset manually or by some reason */
+        /* Check if temperature channels are reset manually or by some reason */
         tmp = it87_read_value(data, IT87_REG_TEMP_ENABLE);
         if ((tmp & 0x3f) == 0) {
                 /* Temp1,Temp3=thermistor; Temp2=thermal diode */
@@ -1513,7 +1525,8 @@ static struct it87_data *it87_update_device(struct device *dev)
 
                 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
                 /* The 8705 does not have VID capability.
-                   The 8718 does not use IT87_REG_VID for the same purpose. */
+                   The 8718 and the 8720 don't use IT87_REG_VID for the
+                   same purpose. */
                 if (data->type == it8712 || data->type == it8716) {
                         data->vid = it87_read_value(data, IT87_REG_VID);
                         /* The older IT8712F revisions had only 5 VID pins,
@@ -1540,6 +1553,10 @@ static int __init it87_device_add(unsigned short address,
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc(DRVNAME, address);
         if (!pdev) {
                 err = -ENOMEM;
@@ -1608,7 +1625,7 @@ static void __exit sm_it87_exit(void)
 
 MODULE_AUTHOR("Chris Gauthron, "
               "Jean Delvare <khali@linux-fr.org>");
-MODULE_DESCRIPTION("IT8705F/8712F/8716F/8718F/8726F, SiS950 driver");
+MODULE_DESCRIPTION("IT8705F/8712F/8716F/8718F/8720F/8726F, SiS950 driver");
 module_param(update_vbat, bool, 0);
 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
 module_param(fix_pwm_polarity, bool, 0);
diff --git a/drivers/hwmon/lm70.c b/drivers/hwmon/lm70.c
index d435f003292d..ae6204f33214 100644
--- a/drivers/hwmon/lm70.c
+++ b/drivers/hwmon/lm70.c
@@ -37,9 +37,13 @@
 
 #define DRVNAME         "lm70"
 
+#define LM70_CHIP_LM70          0       /* original NS LM70 */
+#define LM70_CHIP_TMP121        1       /* TI TMP121/TMP123 */
+
 struct lm70 {
         struct device *hwmon_dev;
         struct mutex lock;
+        unsigned int chip;
 };
 
 /* sysfs hook function */
@@ -47,7 +51,7 @@ static ssize_t lm70_sense_temp(struct device *dev,
                 struct device_attribute *attr, char *buf)
 {
         struct spi_device *spi = to_spi_device(dev);
-        int status, val;
+        int status, val = 0;
         u8 rxbuf[2];
         s16 raw=0;
         struct lm70 *p_lm70 = dev_get_drvdata(&spi->dev);
@@ -65,12 +69,12 @@ static ssize_t lm70_sense_temp(struct device *dev,
                 "spi_write_then_read failed with status %d\n", status);
                 goto out;
         }
-        dev_dbg(dev, "rxbuf[1] : 0x%x rxbuf[0] : 0x%x\n", rxbuf[1], rxbuf[0]);
-
-        raw = (rxbuf[1] << 8) + rxbuf[0];
-        dev_dbg(dev, "raw=0x%x\n", raw);
+        raw = (rxbuf[0] << 8) + rxbuf[1];
+        dev_dbg(dev, "rxbuf[0] : 0x%02x rxbuf[1] : 0x%02x raw=0x%04x\n",
+                rxbuf[0], rxbuf[1], raw);
 
         /*
+         * LM70:
          * The "raw" temperature read into rxbuf[] is a 16-bit signed 2's
          * complement value. Only the MSB 11 bits (1 sign + 10 temperature
          * bits) are meaningful; the LSB 5 bits are to be discarded.
@@ -80,8 +84,21 @@ static ssize_t lm70_sense_temp(struct device *dev,
          * by 0.25. Also multiply by 1000 to represent in millidegrees
          * Celsius.
          * So it's equivalent to multiplying by 0.25 * 1000 = 250.
+         *
+         * TMP121/TMP123:
+         * 13 bits of 2's complement data, discard LSB 3 bits,
+         * resolution 0.0625 degrees celsius.
          */
-        val = ((int)raw/32) * 250;
+        switch (p_lm70->chip) {
+        case LM70_CHIP_LM70:
+                val = ((int)raw / 32) * 250;
+                break;
+
+        case LM70_CHIP_TMP121:
+                val = ((int)raw / 8) * 625 / 10;
+                break;
+        }
+
         status = sprintf(buf, "%d\n", val); /* millidegrees Celsius */
 out:
         mutex_unlock(&p_lm70->lock);
@@ -93,27 +110,39 @@ static DEVICE_ATTR(temp1_input, S_IRUGO, lm70_sense_temp, NULL);
 static ssize_t lm70_show_name(struct device *dev, struct device_attribute
                               *devattr, char *buf)
 {
-        return sprintf(buf, "lm70\n");
+        struct lm70 *p_lm70 = dev_get_drvdata(dev);
+        int ret;
+
+        switch (p_lm70->chip) {
+        case LM70_CHIP_LM70:
+                ret = sprintf(buf, "lm70\n");
+                break;
+        case LM70_CHIP_TMP121:
+                ret = sprintf(buf, "tmp121\n");
+                break;
+        default:
+                ret = -EINVAL;
+        }
+        return ret;
 }
 
 static DEVICE_ATTR(name, S_IRUGO, lm70_show_name, NULL);
 
 /*----------------------------------------------------------------------*/
 
-static int __devinit lm70_probe(struct spi_device *spi)
+static int __devinit common_probe(struct spi_device *spi, int chip)
 {
         struct lm70 *p_lm70;
         int status;
 
-        /* signaling is SPI_MODE_0 on a 3-wire link (shared SI/SO) */
-        if ((spi->mode & (SPI_CPOL|SPI_CPHA)) || !(spi->mode & SPI_3WIRE))
-                return -EINVAL;
+        /* NOTE:  we assume 8-bit words, and convert to 16 bits manually */
 
         p_lm70 = kzalloc(sizeof *p_lm70, GFP_KERNEL);
         if (!p_lm70)
                 return -ENOMEM;
 
         mutex_init(&p_lm70->lock);
+        p_lm70->chip = chip;
 
         /* sysfs hook */
         p_lm70->hwmon_dev = hwmon_device_register(&spi->dev);
@@ -141,6 +170,24 @@ out_dev_reg_failed:
         return status;
 }
 
+static int __devinit lm70_probe(struct spi_device *spi)
+{
+        /* signaling is SPI_MODE_0 on a 3-wire link (shared SI/SO) */
+        if ((spi->mode & (SPI_CPOL | SPI_CPHA)) || !(spi->mode & SPI_3WIRE))
+                return -EINVAL;
+
+        return common_probe(spi, LM70_CHIP_LM70);
+}
+
+static int __devinit tmp121_probe(struct spi_device *spi)
+{
+        /* signaling is SPI_MODE_0 with only MISO connected */
+        if (spi->mode & (SPI_CPOL | SPI_CPHA))
+                return -EINVAL;
+
+        return common_probe(spi, LM70_CHIP_TMP121);
+}
+
 static int __devexit lm70_remove(struct spi_device *spi)
 {
         struct lm70 *p_lm70 = dev_get_drvdata(&spi->dev);
@@ -154,6 +201,15 @@ static int __devexit lm70_remove(struct spi_device *spi)
         return 0;
 }
 
+static struct spi_driver tmp121_driver = {
+        .driver = {
+                .name   = "tmp121",
+                .owner  = THIS_MODULE,
+        },
+        .probe  = tmp121_probe,
+        .remove = __devexit_p(lm70_remove),
+};
+
 static struct spi_driver lm70_driver = {
         .driver = {
                 .name   = "lm70",
@@ -165,17 +221,26 @@ static struct spi_driver lm70_driver = {
 
 static int __init init_lm70(void)
 {
-        return spi_register_driver(&lm70_driver);
+        int ret = spi_register_driver(&lm70_driver);
+        if (ret)
+                return ret;
+
+        ret = spi_register_driver(&tmp121_driver);
+        if (ret)
+                spi_unregister_driver(&lm70_driver);
+
+        return ret;
 }
 
 static void __exit cleanup_lm70(void)
 {
         spi_unregister_driver(&lm70_driver);
+        spi_unregister_driver(&tmp121_driver);
 }
 
 module_init(init_lm70);
 module_exit(cleanup_lm70);
 
 MODULE_AUTHOR("Kaiwan N Billimoria");
-MODULE_DESCRIPTION("National Semiconductor LM70 Linux driver");
+MODULE_DESCRIPTION("NS LM70 / TI TMP121/TMP123 Linux driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/ltc4245.c b/drivers/hwmon/ltc4245.c
new file mode 100644
index 000000000000..034b2c515848
--- /dev/null
+++ b/drivers/hwmon/ltc4245.c
@@ -0,0 +1,567 @@
+/*
+ * Driver for Linear Technology LTC4245 I2C Multiple Supply Hot Swap Controller
+ *
+ * Copyright (C) 2008 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This driver is based on the ds1621 and ina209 drivers.
+ *
+ * Datasheet:
+ * http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1006,C1140,P19392,D13517
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+
+/* Valid addresses are 0x20 - 0x3f
+ *
+ * For now, we do not probe, since some of these addresses
+ * are known to be unfriendly to probing */
+static const unsigned short normal_i2c[] = { I2C_CLIENT_END };
+
+/* Insmod parameters */
+I2C_CLIENT_INSMOD_1(ltc4245);
+
+/* Here are names of the chip's registers (a.k.a. commands) */
+enum ltc4245_cmd {
+        LTC4245_STATUS                  = 0x00, /* readonly */
+        LTC4245_ALERT                   = 0x01,
+        LTC4245_CONTROL                 = 0x02,
+        LTC4245_ON                      = 0x03,
+        LTC4245_FAULT1                  = 0x04,
+        LTC4245_FAULT2                  = 0x05,
+        LTC4245_GPIO                    = 0x06,
+        LTC4245_ADCADR                  = 0x07,
+
+        LTC4245_12VIN                   = 0x10,
+        LTC4245_12VSENSE                = 0x11,
+        LTC4245_12VOUT                  = 0x12,
+        LTC4245_5VIN                    = 0x13,
+        LTC4245_5VSENSE                 = 0x14,
+        LTC4245_5VOUT                   = 0x15,
+        LTC4245_3VIN                    = 0x16,
+        LTC4245_3VSENSE                 = 0x17,
+        LTC4245_3VOUT                   = 0x18,
+        LTC4245_VEEIN                   = 0x19,
+        LTC4245_VEESENSE                = 0x1a,
+        LTC4245_VEEOUT                  = 0x1b,
+        LTC4245_GPIOADC1                = 0x1c,
+        LTC4245_GPIOADC2                = 0x1d,
+        LTC4245_GPIOADC3                = 0x1e,
+};
+
+struct ltc4245_data {
+        struct device *hwmon_dev;
+
+        struct mutex update_lock;
+        bool valid;
+        unsigned long last_updated; /* in jiffies */
+
+        /* Control registers */
+        u8 cregs[0x08];
+
+        /* Voltage registers */
+        u8 vregs[0x0f];
+};
+
+static struct ltc4245_data *ltc4245_update_device(struct device *dev)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct ltc4245_data *data = i2c_get_clientdata(client);
+        s32 val;
+        int i;
+
+        mutex_lock(&data->update_lock);
+
+        if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
+
+                dev_dbg(&client->dev, "Starting ltc4245 update\n");
+
+                /* Read control registers -- 0x00 to 0x07 */
+                for (i = 0; i < ARRAY_SIZE(data->cregs); i++) {
+                        val = i2c_smbus_read_byte_data(client, i);
+                        if (unlikely(val < 0))
+                                data->cregs[i] = 0;
+                        else
+                                data->cregs[i] = val;
+                }
+
+                /* Read voltage registers -- 0x10 to 0x1f */
+                for (i = 0; i < ARRAY_SIZE(data->vregs); i++) {
+                        val = i2c_smbus_read_byte_data(client, i+0x10);
+                        if (unlikely(val < 0))
+                                data->vregs[i] = 0;
+                        else
+                                data->vregs[i] = val;
+                }
+
+                data->last_updated = jiffies;
+                data->valid = 1;
+        }
+
+        mutex_unlock(&data->update_lock);
+
+        return data;
+}
+
+/* Return the voltage from the given register in millivolts */
+static int ltc4245_get_voltage(struct device *dev, u8 reg)
+{
+        struct ltc4245_data *data = ltc4245_update_device(dev);
+        const u8 regval = data->vregs[reg - 0x10];
+        u32 voltage = 0;
+
+        switch (reg) {
+        case LTC4245_12VIN:
+        case LTC4245_12VOUT:
+                voltage = regval * 55;
+                break;
+        case LTC4245_5VIN:
+        case LTC4245_5VOUT:
+                voltage = regval * 22;
+                break;
+        case LTC4245_3VIN:
+        case LTC4245_3VOUT:
+                voltage = regval * 15;
+                break;
+        case LTC4245_VEEIN:
+        case LTC4245_VEEOUT:
+                voltage = regval * -55;
+                break;
+        case LTC4245_GPIOADC1:
+        case LTC4245_GPIOADC2:
+        case LTC4245_GPIOADC3:
+                voltage = regval * 10;
+                break;
+        default:
+                /* If we get here, the developer messed up */
+                WARN_ON_ONCE(1);
+                break;
+        }
+
+        return voltage;
+}
+
+/* Return the current in the given sense register in milliAmperes */
+static unsigned int ltc4245_get_current(struct device *dev, u8 reg)
+{
+        struct ltc4245_data *data = ltc4245_update_device(dev);
+        const u8 regval = data->vregs[reg - 0x10];
+        unsigned int voltage;
+        unsigned int curr;
+
+        /* The strange looking conversions that follow are fixed-point
+         * math, since we cannot do floating point in the kernel.
+         *
+         * Step 1: convert sense register to microVolts
+         * Step 2: convert voltage to milliAmperes
+         *
+         * If you play around with the V=IR equation, you come up with
+         * the following: X uV / Y mOhm == Z mA
+         *
+         * With the resistors that are fractions of a milliOhm, we multiply
+         * the voltage and resistance by 10, to shift the decimal point.
+         * Now we can use the normal division operator again.
+         */
+
+        switch (reg) {
+        case LTC4245_12VSENSE:
+                voltage = regval * 250; /* voltage in uV */
+                curr = voltage / 50; /* sense resistor 50 mOhm */
+                break;
+        case LTC4245_5VSENSE:
+                voltage = regval * 125; /* voltage in uV */
+                curr = (voltage * 10) / 35; /* sense resistor 3.5 mOhm */
+                break;
+        case LTC4245_3VSENSE:
+                voltage = regval * 125; /* voltage in uV */
+                curr = (voltage * 10) / 25; /* sense resistor 2.5 mOhm */
+                break;
+        case LTC4245_VEESENSE:
+                voltage = regval * 250; /* voltage in uV */
+                curr = voltage / 100; /* sense resistor 100 mOhm */
+                break;
+        default:
+                /* If we get here, the developer messed up */
+                WARN_ON_ONCE(1);
+                curr = 0;
+                break;
+        }
+
+        return curr;
+}
+
+static ssize_t ltc4245_show_voltage(struct device *dev,
+                                    struct device_attribute *da,
+                                    char *buf)
+{
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+        const int voltage = ltc4245_get_voltage(dev, attr->index);
+
+        return snprintf(buf, PAGE_SIZE, "%d\n", voltage);
+}
+
+static ssize_t ltc4245_show_current(struct device *dev,
+                                    struct device_attribute *da,
+                                    char *buf)
+{
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+        const unsigned int curr = ltc4245_get_current(dev, attr->index);
+
+        return snprintf(buf, PAGE_SIZE, "%u\n", curr);
+}
+
+static ssize_t ltc4245_show_power(struct device *dev,
+                                  struct device_attribute *da,
+                                  char *buf)
+{
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
+        const unsigned int curr = ltc4245_get_current(dev, attr->index);
+        const int output_voltage = ltc4245_get_voltage(dev, attr->index+1);
+
+        /* current in mA * voltage in mV == power in uW */
+        const unsigned int power = abs(output_voltage * curr);
+
+        return snprintf(buf, PAGE_SIZE, "%u\n", power);
+}
+
+static ssize_t ltc4245_show_alarm(struct device *dev,
+                                          struct device_attribute *da,
+                                          char *buf)
+{
+        struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(da);
+        struct ltc4245_data *data = ltc4245_update_device(dev);
+        const u8 reg = data->cregs[attr->index];
+        const u32 mask = attr->nr;
+
+        return snprintf(buf, PAGE_SIZE, "%u\n", (reg & mask) ? 1 : 0);
+}
+
+/* These macros are used below in constructing device attribute objects
+ * for use with sysfs_create_group() to make a sysfs device file
+ * for each register.
+ */
+
+#define LTC4245_VOLTAGE(name, ltc4245_cmd_idx) \
+        static SENSOR_DEVICE_ATTR(name, S_IRUGO, \
+        ltc4245_show_voltage, NULL, ltc4245_cmd_idx)
+
+#define LTC4245_CURRENT(name, ltc4245_cmd_idx) \
+        static SENSOR_DEVICE_ATTR(name, S_IRUGO, \
+        ltc4245_show_current, NULL, ltc4245_cmd_idx)
+
+#define LTC4245_POWER(name, ltc4245_cmd_idx) \
+        static SENSOR_DEVICE_ATTR(name, S_IRUGO, \
+        ltc4245_show_power, NULL, ltc4245_cmd_idx)
+
+#define LTC4245_ALARM(name, mask, reg) \
+        static SENSOR_DEVICE_ATTR_2(name, S_IRUGO, \
+        ltc4245_show_alarm, NULL, (mask), reg)
+
+/* Construct a sensor_device_attribute structure for each register */
+
+/* Input voltages */
+LTC4245_VOLTAGE(in1_input,                      LTC4245_12VIN);
+LTC4245_VOLTAGE(in2_input,                      LTC4245_5VIN);
+LTC4245_VOLTAGE(in3_input,                      LTC4245_3VIN);
+LTC4245_VOLTAGE(in4_input,                      LTC4245_VEEIN);
+
+/* Input undervoltage alarms */
+LTC4245_ALARM(in1_min_alarm,    (1 << 0),       LTC4245_FAULT1);
+LTC4245_ALARM(in2_min_alarm,    (1 << 1),       LTC4245_FAULT1);
+LTC4245_ALARM(in3_min_alarm,    (1 << 2),       LTC4245_FAULT1);
+LTC4245_ALARM(in4_min_alarm,    (1 << 3),       LTC4245_FAULT1);
+
+/* Currents (via sense resistor) */
+LTC4245_CURRENT(curr1_input,                    LTC4245_12VSENSE);
+LTC4245_CURRENT(curr2_input,                    LTC4245_5VSENSE);
+LTC4245_CURRENT(curr3_input,                    LTC4245_3VSENSE);
+LTC4245_CURRENT(curr4_input,                    LTC4245_VEESENSE);
+
+/* Overcurrent alarms */
+LTC4245_ALARM(curr1_max_alarm,  (1 << 4),       LTC4245_FAULT1);
+LTC4245_ALARM(curr2_max_alarm,  (1 << 5),       LTC4245_FAULT1);
+LTC4245_ALARM(curr3_max_alarm,  (1 << 6),       LTC4245_FAULT1);
+LTC4245_ALARM(curr4_max_alarm,  (1 << 7),       LTC4245_FAULT1);
+
+/* Output voltages */
+LTC4245_VOLTAGE(in5_input,                      LTC4245_12VOUT);
+LTC4245_VOLTAGE(in6_input,                      LTC4245_5VOUT);
+LTC4245_VOLTAGE(in7_input,                      LTC4245_3VOUT);
+LTC4245_VOLTAGE(in8_input,                      LTC4245_VEEOUT);
+
+/* Power Bad alarms */
+LTC4245_ALARM(in5_min_alarm,    (1 << 0),       LTC4245_FAULT2);
+LTC4245_ALARM(in6_min_alarm,    (1 << 1),       LTC4245_FAULT2);
+LTC4245_ALARM(in7_min_alarm,    (1 << 2),       LTC4245_FAULT2);
+LTC4245_ALARM(in8_min_alarm,    (1 << 3),       LTC4245_FAULT2);
+
+/* GPIO voltages */
+LTC4245_VOLTAGE(in9_input,                      LTC4245_GPIOADC1);
+LTC4245_VOLTAGE(in10_input,                     LTC4245_GPIOADC2);
+LTC4245_VOLTAGE(in11_input,                     LTC4245_GPIOADC3);
+
+/* Power Consumption (virtual) */
+LTC4245_POWER(power1_input,                     LTC4245_12VSENSE);
+LTC4245_POWER(power2_input,                     LTC4245_5VSENSE);
+LTC4245_POWER(power3_input,                     LTC4245_3VSENSE);
+LTC4245_POWER(power4_input,                     LTC4245_VEESENSE);
+
+/* Finally, construct an array of pointers to members of the above objects,
+ * as required for sysfs_create_group()
+ */
+static struct attribute *ltc4245_attributes[] = {
+        &sensor_dev_attr_in1_input.dev_attr.attr,
+        &sensor_dev_attr_in2_input.dev_attr.attr,
+        &sensor_dev_attr_in3_input.dev_attr.attr,
+        &sensor_dev_attr_in4_input.dev_attr.attr,
+
+        &sensor_dev_attr_in1_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in2_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in3_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in4_min_alarm.dev_attr.attr,
+
+        &sensor_dev_attr_curr1_input.dev_attr.attr,
+        &sensor_dev_attr_curr2_input.dev_attr.attr,
+        &sensor_dev_attr_curr3_input.dev_attr.attr,
+        &sensor_dev_attr_curr4_input.dev_attr.attr,
+
+        &sensor_dev_attr_curr1_max_alarm.dev_attr.attr,
+        &sensor_dev_attr_curr2_max_alarm.dev_attr.attr,
+        &sensor_dev_attr_curr3_max_alarm.dev_attr.attr,
+        &sensor_dev_attr_curr4_max_alarm.dev_attr.attr,
+
+        &sensor_dev_attr_in5_input.dev_attr.attr,
+        &sensor_dev_attr_in6_input.dev_attr.attr,
+        &sensor_dev_attr_in7_input.dev_attr.attr,
+        &sensor_dev_attr_in8_input.dev_attr.attr,
+
+        &sensor_dev_attr_in5_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in6_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in7_min_alarm.dev_attr.attr,
+        &sensor_dev_attr_in8_min_alarm.dev_attr.attr,
+
+        &sensor_dev_attr_in9_input.dev_attr.attr,
+        &sensor_dev_attr_in10_input.dev_attr.attr,
+        &sensor_dev_attr_in11_input.dev_attr.attr,
+
+        &sensor_dev_attr_power1_input.dev_attr.attr,
+        &sensor_dev_attr_power2_input.dev_attr.attr,
+        &sensor_dev_attr_power3_input.dev_attr.attr,
+        &sensor_dev_attr_power4_input.dev_attr.attr,
+
+        NULL,
+};
+
+static const struct attribute_group ltc4245_group = {
+        .attrs = ltc4245_attributes,
+};
+
+static int ltc4245_probe(struct i2c_client *client,
+                         const struct i2c_device_id *id)
+{
+        struct ltc4245_data *data;
+        int ret;
+
+        data = kzalloc(sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                ret = -ENOMEM;
+                goto out_kzalloc;
+        }
+
+        i2c_set_clientdata(client, data);
+        mutex_init(&data->update_lock);
+
+        /* Initialize the LTC4245 chip */
+        /* TODO */
+
+        /* Register sysfs hooks */
+        ret = sysfs_create_group(&client->dev.kobj, &ltc4245_group);
+        if (ret)
+                goto out_sysfs_create_group;
+
+        data->hwmon_dev = hwmon_device_register(&client->dev);
+        if (IS_ERR(data->hwmon_dev)) {
+                ret = PTR_ERR(data->hwmon_dev);
+                goto out_hwmon_device_register;
+        }
+
+        return 0;
+
+out_hwmon_device_register:
+        sysfs_remove_group(&client->dev.kobj, &ltc4245_group);
+out_sysfs_create_group:
+        kfree(data);
+out_kzalloc:
+        return ret;
+}
+
+static int ltc4245_remove(struct i2c_client *client)
+{
+        struct ltc4245_data *data = i2c_get_clientdata(client);
+
+        hwmon_device_unregister(data->hwmon_dev);
+        sysfs_remove_group(&client->dev.kobj, &ltc4245_group);
+
+        kfree(data);
+
+        return 0;
+}
+
+/* Check that some bits in a control register appear at all possible
+ * locations without changing value
+ *
+ * @client: the i2c client to use
+ * @reg: the register to read
+ * @bits: the bits to check (0xff checks all bits,
+ *                           0x03 checks only the last two bits)
+ *
+ * return -ERRNO if the register read failed
+ * return -ENODEV if the register value doesn't stay constant at all
+ * possible addresses
+ *
+ * return 0 for success
+ */
+static int ltc4245_check_control_reg(struct i2c_client *client, u8 reg, u8 bits)
+{
+        int i;
+        s32 v, voff1, voff2;
+
+        /* Read register and check for error */
+        v = i2c_smbus_read_byte_data(client, reg);
+        if (v < 0)
+                return v;
+
+        v &= bits;
+
+        for (i = 0x00; i < 0xff; i += 0x20) {
+
+                voff1 = i2c_smbus_read_byte_data(client, reg + i);
+                if (voff1 < 0)
+                        return voff1;
+
+                voff2 = i2c_smbus_read_byte_data(client, reg + i + 0x08);
+                if (voff2 < 0)
+                        return voff2;
+
+                voff1 &= bits;
+                voff2 &= bits;
+
+                if (v != voff1 || v != voff2)
+                        return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int ltc4245_detect(struct i2c_client *client,
+                          int kind,
+                          struct i2c_board_info *info)
+{
+        struct i2c_adapter *adapter = client->adapter;
+
+        if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+                return -ENODEV;
+
+        if (kind < 0) {         /* probed detection - check the chip type */
+                s32 v;          /* 8 bits from the chip, or -ERRNO */
+
+                /* Chip registers 0x00-0x07 are control registers
+                 * Chip registers 0x10-0x1f are data registers
+                 *
+                 * Address bits b7-b5 are ignored. This makes the chip "repeat"
+                 * in steps of 0x20. Any control registers should appear with
+                 * the same values across all duplicated addresses.
+                 *
+                 * Register 0x02 bit b2 is reserved, expect 0
+                 * Register 0x07 bits b7 to b4 are reserved, expect 0
+                 *
+                 * Registers 0x01, 0x02 are control registers and should not
+                 * change on their own.
+                 *
+                 * Register 0x06 bits b6 and b7 are control bits, and should
+                 * not change on their own.
+                 *
+                 * Register 0x07 bits b3 to b0 are control bits, and should
+                 * not change on their own.
+                 */
+
+                /* read register 0x02 reserved bit, expect 0 */
+                v = i2c_smbus_read_byte_data(client, LTC4245_CONTROL);
+                if (v < 0 || (v & 0x04) != 0)
+                        return -ENODEV;
+
+                /* read register 0x07 reserved bits, expect 0 */
+                v = i2c_smbus_read_byte_data(client, LTC4245_ADCADR);
+                if (v < 0 || (v & 0xf0) != 0)
+                        return -ENODEV;
+
+                /* check that the alert register appears at all locations */
+                if (ltc4245_check_control_reg(client, LTC4245_ALERT, 0xff))
+                        return -ENODEV;
+
+                /* check that the control register appears at all locations */
+                if (ltc4245_check_control_reg(client, LTC4245_CONTROL, 0xff))
+                        return -ENODEV;
+
+                /* check that register 0x06 bits b6 and b7 stay constant */
+                if (ltc4245_check_control_reg(client, LTC4245_GPIO, 0xc0))
+                        return -ENODEV;
+
+                /* check that register 0x07 bits b3-b0 stay constant */
+                if (ltc4245_check_control_reg(client, LTC4245_ADCADR, 0x0f))
+                        return -ENODEV;
+        }
+
+        strlcpy(info->type, "ltc4245", I2C_NAME_SIZE);
+        dev_info(&adapter->dev, "ltc4245 %s at address 0x%02x\n",
+                        kind < 0 ? "probed" : "forced",
+                        client->addr);
+
+        return 0;
+}
+
+static const struct i2c_device_id ltc4245_id[] = {
+        { "ltc4245", ltc4245 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, ltc4245_id);
+
+/* This is the driver that will be inserted */
+static struct i2c_driver ltc4245_driver = {
+        .class          = I2C_CLASS_HWMON,
+        .driver = {
+                .name   = "ltc4245",
+        },
+        .probe          = ltc4245_probe,
+        .remove         = ltc4245_remove,
+        .id_table       = ltc4245_id,
+        .detect         = ltc4245_detect,
+        .address_data   = &addr_data,
+};
+
+static int __init ltc4245_init(void)
+{
+        return i2c_add_driver(&ltc4245_driver);
+}
+
+static void __exit ltc4245_exit(void)
+{
+        i2c_del_driver(&ltc4245_driver);
+}
+
+MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
+MODULE_DESCRIPTION("LTC4245 driver");
+MODULE_LICENSE("GPL");
+
+module_init(ltc4245_init);
+module_exit(ltc4245_exit);
diff --git a/drivers/hwmon/pc87360.c b/drivers/hwmon/pc87360.c
index 5fbfa34c110e..fb052fea3744 100644
--- a/drivers/hwmon/pc87360.c
+++ b/drivers/hwmon/pc87360.c
@@ -43,6 +43,7 @@
 #include <linux/hwmon-vid.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static u8 devid;
@@ -1627,6 +1628,11 @@ static int __init pc87360_device_add(unsigned short address)
                         continue;
                 res.start = extra_isa[i];
                 res.end = extra_isa[i] + PC87360_EXTENT - 1;
+
+                err = acpi_check_resource_conflict(&res);
+                if (err)
+                        goto exit_device_put;
+
                 err = platform_device_add_resources(pdev, &res, 1);
                 if (err) {
                         printk(KERN_ERR "pc87360: Device resource[%d] "
diff --git a/drivers/hwmon/pc87427.c b/drivers/hwmon/pc87427.c
index 7265f22ae5cd..3a8a0f7a7736 100644
--- a/drivers/hwmon/pc87427.c
+++ b/drivers/hwmon/pc87427.c
@@ -32,6 +32,7 @@
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
 #include <linux/ioport.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static unsigned short force_id;
@@ -524,6 +525,10 @@ static int __init pc87427_device_add(unsigned short address)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc(DRVNAME, address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/sis5595.c b/drivers/hwmon/sis5595.c
index a276806f3d53..aa2e8318f167 100644
--- a/drivers/hwmon/sis5595.c
+++ b/drivers/hwmon/sis5595.c
@@ -62,6 +62,7 @@
 #include <linux/jiffies.h>
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 
@@ -727,6 +728,10 @@ static int __devinit sis5595_device_add(unsigned short address)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc("sis5595", address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/smsc47b397.c b/drivers/hwmon/smsc47b397.c
index eb03544c731c..6f6d52b4fb64 100644
--- a/drivers/hwmon/smsc47b397.c
+++ b/drivers/hwmon/smsc47b397.c
@@ -36,6 +36,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/mutex.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static unsigned short force_id;
@@ -303,6 +304,10 @@ static int __init smsc47b397_device_add(unsigned short address)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc(DRVNAME, address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/smsc47m1.c b/drivers/hwmon/smsc47m1.c
index d1b498548736..a92dbb97ee99 100644
--- a/drivers/hwmon/smsc47m1.c
+++ b/drivers/hwmon/smsc47m1.c
@@ -37,6 +37,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static unsigned short force_id;
@@ -705,6 +706,10 @@ static int __init smsc47m1_device_add(unsigned short address,
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc(DRVNAME, address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/via686a.c b/drivers/hwmon/via686a.c
index f1ee5e731968..a022aedcaacb 100644
--- a/drivers/hwmon/via686a.c
+++ b/drivers/hwmon/via686a.c
@@ -41,6 +41,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 #include <linux/sysfs.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 
@@ -783,6 +784,10 @@ static int __devinit via686a_device_add(unsigned short address)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc("via686a", address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/vt1211.c b/drivers/hwmon/vt1211.c
index 12b43590fa53..b0ce37852281 100644
--- a/drivers/hwmon/vt1211.c
+++ b/drivers/hwmon/vt1211.c
@@ -32,6 +32,7 @@
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/ioport.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static int uch_config = -1;
@@ -1259,6 +1260,10 @@ static int __init vt1211_device_add(unsigned short address)
         }
 
         res.name = pdev->name;
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto EXIT;
+
         err = platform_device_add_resources(pdev, &res, 1);
         if (err) {
                 printk(KERN_ERR DRVNAME ": Device resource addition failed "
diff --git a/drivers/hwmon/vt8231.c b/drivers/hwmon/vt8231.c
index 5bc57275cae8..9982b45fbb14 100644
--- a/drivers/hwmon/vt8231.c
+++ b/drivers/hwmon/vt8231.c
@@ -35,6 +35,7 @@
 #include <linux/hwmon-vid.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 
 static int force_addr;
@@ -894,6 +895,10 @@ static int __devinit vt8231_device_add(unsigned short address)
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc("vt8231", address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/w83627ehf.c b/drivers/hwmon/w83627ehf.c
index 075164dd65a7..cb808d015361 100644
--- a/drivers/hwmon/w83627ehf.c
+++ b/drivers/hwmon/w83627ehf.c
@@ -48,6 +48,7 @@
 #include <linux/hwmon-vid.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 #include "lm75.h"
 
@@ -502,7 +503,7 @@ static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
                 }
 
                 for (i = 0; i < 4; i++) {
-                        /* pwmcfg, tolarance mapped for i=0, i=1 to same reg */
+                        /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
                         if (i != 1) {
                                 pwmcfg = w83627ehf_read_value(data,
                                                 W83627EHF_REG_PWM_ENABLE[i]);
@@ -1544,6 +1545,11 @@ static int __init sensors_w83627ehf_init(void)
         res.start = address + IOREGION_OFFSET;
         res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
         res.flags = IORESOURCE_IO;
+
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         err = platform_device_add_resources(pdev, &res, 1);
         if (err) {
                 printk(KERN_ERR DRVNAME ": Device resource addition failed "
diff --git a/drivers/hwmon/w83627hf.c b/drivers/hwmon/w83627hf.c
index b30e5796cb26..389150ba30d3 100644
--- a/drivers/hwmon/w83627hf.c
+++ b/drivers/hwmon/w83627hf.c
@@ -50,6 +50,7 @@
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/ioport.h>
+#include <linux/acpi.h>
 #include <asm/io.h>
 #include "lm75.h"
 
@@ -1793,6 +1794,10 @@ static int __init w83627hf_device_add(unsigned short address,
         };
         int err;
 
+        err = acpi_check_resource_conflict(&res);
+        if (err)
+                goto exit;
+
         pdev = platform_device_alloc(DRVNAME, address);
         if (!pdev) {
                 err = -ENOMEM;
diff --git a/drivers/hwmon/w83781d.c b/drivers/hwmon/w83781d.c
index fc12bd412e3a..dbfb30c588d8 100644
--- a/drivers/hwmon/w83781d.c
+++ b/drivers/hwmon/w83781d.c
@@ -58,7 +58,10 @@ static const unsigned short normal_i2c[] = { 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d,
                                                 0x2e, 0x2f, I2C_CLIENT_END };
 /* Insmod parameters */
 I2C_CLIENT_INSMOD_4(w83781d, w83782d, w83783s, as99127f);
-I2C_CLIENT_MODULE_PARM(force_subclients, "List of subclient addresses: "
+
+static unsigned short force_subclients[4];
+module_param_array(force_subclients, short, NULL, 0);
+MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
                     "{bus, clientaddr, subclientaddr1, subclientaddr2}");
 
 static int reset;
diff --git a/drivers/hwmon/w83791d.c b/drivers/hwmon/w83791d.c
index 5768def8a4f2..97851c5ba3a3 100644
--- a/drivers/hwmon/w83791d.c
+++ b/drivers/hwmon/w83791d.c
@@ -53,7 +53,10 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f,
 
 /* Insmod parameters */
 I2C_CLIENT_INSMOD_1(w83791d);
-I2C_CLIENT_MODULE_PARM(force_subclients, "List of subclient addresses: "
+
+static unsigned short force_subclients[4];
+module_param_array(force_subclients, short, NULL, 0);
+MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
                         "{bus, clientaddr, subclientaddr1, subclientaddr2}");
 
 static int reset;
diff --git a/drivers/hwmon/w83792d.c b/drivers/hwmon/w83792d.c
index cf94c5b0c879..2be16194ddf3 100644
--- a/drivers/hwmon/w83792d.c
+++ b/drivers/hwmon/w83792d.c
@@ -51,7 +51,10 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f,
 
 /* Insmod parameters */
 I2C_CLIENT_INSMOD_1(w83792d);
-I2C_CLIENT_MODULE_PARM(force_subclients, "List of subclient addresses: "
+
+static unsigned short force_subclients[4];
+module_param_array(force_subclients, short, NULL, 0);
+MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
                         "{bus, clientaddr, subclientaddr1, subclientaddr2}");
 
 static int init;
diff --git a/drivers/hwmon/w83793.c b/drivers/hwmon/w83793.c
index 0a739f1c69be..47dd398f7258 100644
--- a/drivers/hwmon/w83793.c
+++ b/drivers/hwmon/w83793.c
@@ -42,7 +42,10 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f,
 
 /* Insmod parameters */
 I2C_CLIENT_INSMOD_1(w83793);
-I2C_CLIENT_MODULE_PARM(force_subclients, "List of subclient addresses: "
+
+static unsigned short force_subclients[4];
+module_param_array(force_subclients, short, NULL, 0);
+MODULE_PARM_DESC(force_subclients, "List of subclient addresses: "
                        "{bus, clientaddr, subclientaddr1, subclientaddr2}");
 
 static int reset;
diff --git a/drivers/i2c/busses/i2c-ali1563.c b/drivers/i2c/busses/i2c-ali1563.c
index fc3e5b026423..dd9e796fad69 100644
--- a/drivers/i2c/busses/i2c-ali1563.c
+++ b/drivers/i2c/busses/i2c-ali1563.c
@@ -399,8 +399,8 @@ static int __devinit ali1563_probe(struct pci_dev * dev,
         if ((error = ali1563_setup(dev)))
                 goto exit;
         ali1563_adapter.dev.parent = &dev->dev;
-        sprintf(ali1563_adapter.name,"SMBus ALi 1563 Adapter @ %04x",
-                ali1563_smba);
+        snprintf(ali1563_adapter.name, sizeof(ali1563_adapter.name),
+                 "SMBus ALi 1563 Adapter @ %04x", ali1563_smba);
         if ((error = i2c_add_adapter(&ali1563_adapter)))
                 goto exit_shutdown;
         return 0;
diff --git a/drivers/i2c/busses/i2c-amd756-s4882.c b/drivers/i2c/busses/i2c-amd756-s4882.c
index 8ba2bcf727d3..378fcb5d5783 100644
--- a/drivers/i2c/busses/i2c-amd756-s4882.c
+++ b/drivers/i2c/busses/i2c-amd756-s4882.c
@@ -197,8 +197,8 @@ static int __init amd756_s4882_init(void)
         for (i = 1; i < 5; i++) {
                 s4882_algo[i] = *(amd756_smbus.algo);
                 s4882_adapter[i] = amd756_smbus;
-                sprintf(s4882_adapter[i].name,
-                        "SMBus 8111 adapter (CPU%d)", i-1);
+                snprintf(s4882_adapter[i].name, sizeof(s4882_adapter[i].name),
+                         "SMBus 8111 adapter (CPU%d)", i-1);
                 s4882_adapter[i].algo = s4882_algo+i;
                 s4882_adapter[i].dev.parent = amd756_smbus.dev.parent;
         }
diff --git a/drivers/i2c/busses/i2c-amd756.c b/drivers/i2c/busses/i2c-amd756.c
index 424dad6f18d8..36bee5b9c952 100644
--- a/drivers/i2c/busses/i2c-amd756.c
+++ b/drivers/i2c/busses/i2c-amd756.c
@@ -380,8 +380,9 @@ static int __devinit amd756_probe(struct pci_dev *pdev,
         /* set up the sysfs linkage to our parent device */
         amd756_smbus.dev.parent = &pdev->dev;
 
-        sprintf(amd756_smbus.name, "SMBus %s adapter at %04x",
-                chipname[id->driver_data], amd756_ioport);
+        snprintf(amd756_smbus.name, sizeof(amd756_smbus.name),
+                 "SMBus %s adapter at %04x", chipname[id->driver_data],
+                 amd756_ioport);
 
         error = i2c_add_adapter(&amd756_smbus);
         if (error) {
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 9efb02137254..67d9dc5b351b 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -222,7 +222,7 @@ static int __devinit at91_i2c_probe(struct platform_device *pdev)
                 rc = -ENOMEM;
                 goto fail2;
         }
-        sprintf(adapter->name, "AT91");
+        snprintf(adapter->name, sizeof(adapter->name), "AT91");
         adapter->algo = &at91_algorithm;
         adapter->class = I2C_CLASS_HWMON;
         adapter->dev.parent = &pdev->dev;
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 3c855ff2992f..3fd2c417c1e0 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -656,7 +656,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
         p_adap->algo = &bfin_twi_algorithm;
         p_adap->algo_data = iface;
-        p_adap->class = I2C_CLASS_ALL;
+        p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
         p_adap->dev.parent = &pdev->dev;
 
         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 5123eb69a971..526625eaa84b 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -64,7 +64,7 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/acpi.h>
-#include <asm/io.h>
+#include <linux/io.h>
 
 /* I801 SMBus address offsets */
 #define SMBHSTSTS       (0 + i801_smba)
@@ -583,6 +583,40 @@ static struct pci_device_id i801_ids[] = {
 
 MODULE_DEVICE_TABLE (pci, i801_ids);
 
+#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
+static unsigned char apanel_addr;
+
+/* Scan the system ROM for the signature "FJKEYINF" */
+static __init const void __iomem *bios_signature(const void __iomem *bios)
+{
+        ssize_t offset;
+        const unsigned char signature[] = "FJKEYINF";
+
+        for (offset = 0; offset < 0x10000; offset += 0x10) {
+                if (check_signature(bios + offset, signature,
+                                    sizeof(signature)-1))
+                        return bios + offset;
+        }
+        return NULL;
+}
+
+static void __init input_apanel_init(void)
+{
+        void __iomem *bios;
+        const void __iomem *p;
+
+        bios = ioremap(0xF0000, 0x10000); /* Can't fail */
+        p = bios_signature(bios);
+        if (p) {
+                /* just use the first address */
+                apanel_addr = readb(p + 8 + 3) >> 1;
+        }
+        iounmap(bios);
+}
+#else
+static void __init input_apanel_init(void) {}
+#endif
+
 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
         unsigned char temp;
@@ -667,6 +701,19 @@ static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id
                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
                 goto exit_release;
         }
+
+        /* Register optional slaves */
+#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
+        if (apanel_addr) {
+                struct i2c_board_info info;
+
+                memset(&info, 0, sizeof(struct i2c_board_info));
+                info.addr = apanel_addr;
+                strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
+                i2c_new_device(&i801_adapter, &info);
+        }
+#endif
+
         return 0;
 
 exit_release:
@@ -717,6 +764,7 @@ static struct pci_driver i801_driver = {
 
 static int __init i2c_i801_init(void)
 {
+        input_apanel_init();
         return pci_register_driver(&i801_driver);
 }
 
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 587f5b2380d4..6af68146c342 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -1076,10 +1076,10 @@ static int i2c_pxa_probe(struct platform_device *dev)
 
 #ifdef CONFIG_I2C_PXA_SLAVE
         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
-               i2c->adap.dev.bus_id, i2c->slave_addr);
+               dev_name(&i2c->adap.dev), i2c->slave_addr);
 #else
         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
-               i2c->adap.dev.bus_id);
+               dev_name(&i2c->adap.dev));
 #endif
         return 0;
 
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index f69f91ffb469..5b7f95641ba4 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -906,7 +906,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, i2c);
 
-        dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
+        dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
         return 0;
 
  err_cpufreq:
diff --git a/drivers/i2c/busses/i2c-sh7760.c b/drivers/i2c/busses/i2c-sh7760.c
index 5e0e254976de..baa28b73ae42 100644
--- a/drivers/i2c/busses/i2c-sh7760.c
+++ b/drivers/i2c/busses/i2c-sh7760.c
@@ -475,7 +475,7 @@ static int __devinit sh7760_i2c_probe(struct platform_device *pdev)
 
         id->adap.nr = pdev->id;
         id->adap.algo = &sh7760_i2c_algo;
-        id->adap.class = I2C_CLASS_ALL;
+        id->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
         id->adap.retries = 3;
         id->adap.algo_data = id;
         id->adap.dev.parent = &pdev->dev;
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 6c3d60b939bf..1c01083b01b5 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -500,7 +500,7 @@ static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
                 for (n = res->start; hook && n <= res->end; n++) {
                         if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
-                                        dev->dev.bus_id, dev))
+                                        dev_name(&dev->dev), dev))
                                 goto rollback;
                 }
                 k++;
diff --git a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c
index dfc2d5eb6a68..8ce2daff985c 100644
--- a/drivers/i2c/busses/i2c-sis5595.c
+++ b/drivers/i2c/busses/i2c-sis5595.c
@@ -389,8 +389,8 @@ static int __devinit sis5595_probe(struct pci_dev *dev, const struct pci_device_
         /* set up the sysfs linkage to our parent device */
         sis5595_adapter.dev.parent = &dev->dev;
 
-        sprintf(sis5595_adapter.name, "SMBus SIS5595 adapter at %04x",
-                sis5595_base + SMB_INDEX);
+        snprintf(sis5595_adapter.name, sizeof(sis5595_adapter.name),
+                 "SMBus SIS5595 adapter at %04x", sis5595_base + SMB_INDEX);
         err = i2c_add_adapter(&sis5595_adapter);
         if (err) {
                 release_region(sis5595_base + SMB_INDEX, 2);
diff --git a/drivers/i2c/busses/i2c-sis630.c b/drivers/i2c/busses/i2c-sis630.c
index e7c4b790da54..9c9c016ff2b5 100644
--- a/drivers/i2c/busses/i2c-sis630.c
+++ b/drivers/i2c/busses/i2c-sis630.c
@@ -487,8 +487,8 @@ static int __devinit sis630_probe(struct pci_dev *dev, const struct pci_device_i
         /* set up the sysfs linkage to our parent device */
         sis630_adapter.dev.parent = &dev->dev;
 
-        sprintf(sis630_adapter.name, "SMBus SIS630 adapter at %04x",
-                acpi_base + SMB_STS);
+        snprintf(sis630_adapter.name, sizeof(sis630_adapter.name),
+                 "SMBus SIS630 adapter at %04x", acpi_base + SMB_STS);
 
         return i2c_add_adapter(&sis630_adapter);
 }
diff --git a/drivers/i2c/chips/Kconfig b/drivers/i2c/chips/Kconfig
index 864ac561fdbb..59c3d23f5bdc 100644
--- a/drivers/i2c/chips/Kconfig
+++ b/drivers/i2c/chips/Kconfig
@@ -114,18 +114,6 @@ config SENSORS_PCF8591
           These devices are hard to detect and rarely found on mainstream
           hardware.  If unsure, say N.
 
-config ISP1301_OMAP
-        tristate "Philips ISP1301 with OMAP OTG"
-        depends on ARCH_OMAP_OTG
-        help
-          If you say yes here you get support for the Philips ISP1301
-          USB-On-The-Go transceiver working with the OMAP OTG controller.
-          The ISP1301 is used in products including H2 and H3 development
-          boards for Texas Instruments OMAP processors.
-          
-          This driver can also be built as a module.  If so, the module
-          will be called isp1301_omap.
-
 config SENSORS_MAX6875
         tristate "Maxim MAX6875 Power supply supervisor"
         depends on EXPERIMENTAL
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 8b95f41a5001..83accaaf8164 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_SENSORS_PCA9539)	+= pca9539.o
 obj-$(CONFIG_SENSORS_PCF8574)   += pcf8574.o
 obj-$(CONFIG_PCF8575)           += pcf8575.o
 obj-$(CONFIG_SENSORS_PCF8591)   += pcf8591.o
-obj-$(CONFIG_ISP1301_OMAP)      += isp1301_omap.o
 obj-$(CONFIG_SENSORS_TSL2550)   += tsl2550.o
 obj-$(CONFIG_MCU_MPC8349EMITX)  += mcu_mpc8349emitx.o
 
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index c6a63f46bc15..b1c9abe24c7b 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -459,7 +459,7 @@ static int i2c_register_adapter(struct i2c_adapter *adap)
                 pr_debug("I2C adapter driver [%s] forgot to specify "
                          "physical device\n", adap->name);
         }
-        sprintf(adap->dev.bus_id, "i2c-%d", adap->nr);
+        dev_set_name(&adap->dev, "i2c-%d", adap->nr);
         adap->dev.release = &i2c_adapter_dev_release;
         adap->dev.class = &i2c_adapter_class;
         res = device_register(&adap->dev);
@@ -845,8 +845,8 @@ int i2c_attach_client(struct i2c_client *client)
         } else
                 client->dev.release = i2c_client_dev_release;
 
-        snprintf(&client->dev.bus_id[0], sizeof(client->dev.bus_id),
-                "%d-%04x", i2c_adapter_id(adapter), client->addr);
+        dev_set_name(&client->dev, "%d-%04x", i2c_adapter_id(adapter),
+                     client->addr);
         res = device_register(&client->dev);
         if (res)
                 goto out_err;
@@ -856,7 +856,7 @@ int i2c_attach_client(struct i2c_client *client)
         mutex_unlock(&adapter->clist_lock);
 
         dev_dbg(&adapter->dev, "client [%s] registered with bus id %s\n",
-                client->name, client->dev.bus_id);
+                client->name, dev_name(&client->dev));
 
         if (adapter->client_register)  {
                 if (adapter->client_register(client)) {
diff --git a/drivers/ieee1394/csr.c b/drivers/ieee1394/csr.c
index c90be4070e40..31400c8ae051 100644
--- a/drivers/ieee1394/csr.c
+++ b/drivers/ieee1394/csr.c
@@ -68,22 +68,22 @@ static struct hpsb_highlevel csr_highlevel = {
         .host_reset =   host_reset,
 };
 
-static struct hpsb_address_ops map_ops = {
+const static struct hpsb_address_ops map_ops = {
         .read = read_maps,
 };
 
-static struct hpsb_address_ops fcp_ops = {
+const static struct hpsb_address_ops fcp_ops = {
         .write = write_fcp,
 };
 
-static struct hpsb_address_ops reg_ops = {
+const static struct hpsb_address_ops reg_ops = {
         .read = read_regs,
         .write = write_regs,
         .lock = lock_regs,
         .lock64 = lock64_regs,
 };
 
-static struct hpsb_address_ops config_rom_ops = {
+const static struct hpsb_address_ops config_rom_ops = {
         .read = read_config_rom,
 };
 
@@ -217,7 +217,7 @@ static void add_host(struct hpsb_host *host)
 
         host->csr.generation = 2;
 
-        bus_info[1] = __constant_cpu_to_be32(0x31333934);
+        bus_info[1] = IEEE1394_BUSID_MAGIC;
         bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) |
                                   (1 << CSR_CMC_SHIFT) |
                                   (1 << CSR_ISC_SHIFT) |
@@ -250,7 +250,7 @@ static void remove_host(struct hpsb_host *host)
 {
         quadlet_t bus_info[CSR_BUS_INFO_SIZE];
 
-        bus_info[1] = __constant_cpu_to_be32(0x31333934);
+        bus_info[1] = IEEE1394_BUSID_MAGIC;
         bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) |
                                   (0 << CSR_CMC_SHIFT) |
                                   (0 << CSR_ISC_SHIFT) |
diff --git a/drivers/ieee1394/csr.h b/drivers/ieee1394/csr.h
index f11546550d84..90fb3f2192c3 100644
--- a/drivers/ieee1394/csr.h
+++ b/drivers/ieee1394/csr.h
@@ -50,11 +50,11 @@
 #define CSR_MAX_ROM_SHIFT               8
 #define CSR_GENERATION_SHIFT            4
 
-#define CSR_SET_BUS_INFO_GENERATION(csr, gen)                           \
-        ((csr)->bus_info_data[2] =                                      \
-                cpu_to_be32((be32_to_cpu((csr)->bus_info_data[2]) &     \
-                             ~(0xf << CSR_GENERATION_SHIFT)) |          \
-                            (gen) << CSR_GENERATION_SHIFT))
+static inline void csr_set_bus_info_generation(struct csr1212_csr *csr, u8 gen)
+{
+        csr->bus_info_data[2] &= ~cpu_to_be32(0xf << CSR_GENERATION_SHIFT);
+        csr->bus_info_data[2] |= cpu_to_be32((u32)gen << CSR_GENERATION_SHIFT);
+}
 
 struct csr_control {
         spinlock_t lock;
diff --git a/drivers/ieee1394/csr1212.c b/drivers/ieee1394/csr1212.c
index 5e38a68b8af2..a6dfeb0b3372 100644
--- a/drivers/ieee1394/csr1212.c
+++ b/drivers/ieee1394/csr1212.c
@@ -1077,15 +1077,10 @@ static int csr1212_parse_bus_info_block(struct csr1212_csr *csr)
         int i;
         int ret;
 
-        /* IEEE 1212 says that the entire bus info block should be readable in
-         * a single transaction regardless of the max_rom value.
-         * Unfortunately, many IEEE 1394 devices do not abide by that, so the
-         * bus info block will be read 1 quadlet at a time.  The rest of the
-         * ConfigROM will be read according to the max_rom field. */
         for (i = 0; i < csr->bus_info_len; i += sizeof(u32)) {
                 ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i,
-                        sizeof(u32), &csr->cache_head->data[bytes_to_quads(i)],
-                        csr->private);
+                                &csr->cache_head->data[bytes_to_quads(i)],
+                                csr->private);
                 if (ret != CSR1212_SUCCESS)
                         return ret;
 
@@ -1104,8 +1099,8 @@ static int csr1212_parse_bus_info_block(struct csr1212_csr *csr)
          * a time. */
         for (i = csr->bus_info_len; i <= csr->crc_len; i += sizeof(u32)) {
                 ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i,
-                        sizeof(u32), &csr->cache_head->data[bytes_to_quads(i)],
-                        csr->private);
+                                &csr->cache_head->data[bytes_to_quads(i)],
+                                csr->private);
                 if (ret != CSR1212_SUCCESS)
                         return ret;
         }
@@ -1289,7 +1284,7 @@ csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv)
 
                 if (csr->ops->bus_read(csr,
                                        CSR1212_REGISTER_SPACE_BASE + kv->offset,
-                                       sizeof(u32), &q, csr->private))
+                                       &q, csr->private))
                         return -EIO;
 
                 kv->value.leaf.len = be32_to_cpu(q) >> 16;
@@ -1372,17 +1367,8 @@ csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv)
                 addr = (CSR1212_CSR_ARCH_REG_SPACE_BASE + cache->offset +
                         cr->offset_end) & ~(csr->max_rom - 1);
 
-                if (csr->ops->bus_read(csr, addr, csr->max_rom, cache_ptr,
-                                       csr->private)) {
-                        if (csr->max_rom == 4)
-                                /* We've got problems! */
-                                return -EIO;
-
-                        /* Apperently the max_rom value was a lie, set it to
-                         * do quadlet reads and try again. */
-                        csr->max_rom = 4;
-                        continue;
-                }
+                if (csr->ops->bus_read(csr, addr, cache_ptr, csr->private))
+                        return -EIO;
 
                 cr->offset_end += csr->max_rom - (cr->offset_end &
                                                   (csr->max_rom - 1));
@@ -1433,7 +1419,6 @@ csr1212_get_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv)
 
 int csr1212_parse_csr(struct csr1212_csr *csr)
 {
-        static const int mr_map[] = { 4, 64, 1024, 0 };
         struct csr1212_dentry *dentry;
         int ret;
 
@@ -1443,15 +1428,13 @@ int csr1212_parse_csr(struct csr1212_csr *csr)
         if (ret != CSR1212_SUCCESS)
                 return ret;
 
-        if (!csr->ops->get_max_rom) {
-                csr->max_rom = mr_map[0];       /* default value */
-        } else {
-                int i = csr->ops->get_max_rom(csr->bus_info_data,
-                                              csr->private);
-                if (i & ~0x3)
-                        return -EINVAL;
-                csr->max_rom = mr_map[i];
-        }
+        /*
+         * There has been a buggy firmware with bus_info_block.max_rom > 0
+         * spotted which actually only supported quadlet read requests to the
+         * config ROM.  Therefore read everything quadlet by quadlet regardless
+         * of what the bus info block says.
+         */
+        csr->max_rom = 4;
 
         csr->cache_head->layout_head = csr->root_kv;
         csr->cache_head->layout_tail = csr->root_kv;
diff --git a/drivers/ieee1394/csr1212.h b/drivers/ieee1394/csr1212.h
index 043039fc63ec..a892d922dbc9 100644
--- a/drivers/ieee1394/csr1212.h
+++ b/drivers/ieee1394/csr1212.h
@@ -181,7 +181,7 @@ struct csr1212_csr_rom_cache {
 struct csr1212_csr {
         size_t bus_info_len;    /* bus info block length in bytes */
         size_t crc_len;         /* crc length in bytes */
-        u32 *bus_info_data;     /* bus info data incl bus name and EUI */
+        __be32 *bus_info_data;  /* bus info data incl bus name and EUI */
 
         void *private;          /* private, bus specific data */
         struct csr1212_bus_ops *ops;
@@ -200,7 +200,7 @@ struct csr1212_bus_ops {
          * entries located in the Units Space.  Must return 0 on success
          * anything else indicates an error. */
         int (*bus_read) (struct csr1212_csr *csr, u64 addr,
-                         u16 length, void *buffer, void *private);
+                         void *buffer, void *private);
 
         /* This function is used by csr1212 to allocate a region in units space
          * in the event that Config ROM entries don't all fit in the predefined
@@ -211,11 +211,6 @@ struct csr1212_bus_ops {
         /* This function is used by csr1212 to release a region in units space
          * that is no longer needed. */
         void (*release_addr) (u64 addr, void *private);
-
-        /* This function is used by csr1212 to determine the max read request
-         * supported by a remote node when reading the ConfigROM space.  Must
-         * return 0, 1, or 2 per IEEE 1212.  */
-        int (*get_max_rom) (u32 *bus_info, void *private);
 };
 
 
diff --git a/drivers/ieee1394/dv1394-private.h b/drivers/ieee1394/dv1394-private.h
index 7d1d2845b420..18b92cbf4a9f 100644
--- a/drivers/ieee1394/dv1394-private.h
+++ b/drivers/ieee1394/dv1394-private.h
@@ -77,11 +77,11 @@ static inline void fill_cip_header(struct CIP_header *cip,
    See the Texas Instruments OHCI 1394 chipset documentation.
 */
 
-struct output_more_immediate { u32 q[8]; };
-struct output_more { u32 q[4]; };
-struct output_last { u32 q[4]; };
-struct input_more { u32 q[4]; };
-struct input_last { u32 q[4]; };
+struct output_more_immediate { __le32 q[8]; };
+struct output_more { __le32 q[4]; };
+struct output_last { __le32 q[4]; };
+struct input_more { __le32 q[4]; };
+struct input_last { __le32 q[4]; };
 
 /* outputs */
 
@@ -92,9 +92,9 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi,
                                               unsigned int  payload_size)
 {
         omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */
-        omi->q[1] = 0;
-        omi->q[2] = 0;
-        omi->q[3] = 0;
+        omi->q[1] = cpu_to_le32(0);
+        omi->q[2] = cpu_to_le32(0);
+        omi->q[3] = cpu_to_le32(0);
 
         /* IT packet header */
         omi->q[4] = cpu_to_le32(  (0x0 << 16)  /* IEEE1394_SPEED_100 */
@@ -106,8 +106,8 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi,
         /* reserved field; mimic behavior of my Sony DSR-40 */
         omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0);
 
-        omi->q[6] = 0;
-        omi->q[7] = 0;
+        omi->q[6] = cpu_to_le32(0);
+        omi->q[7] = cpu_to_le32(0);
 }
 
 static inline void fill_output_more(struct output_more *om,
@@ -116,8 +116,8 @@ static inline void fill_output_more(struct output_more *om,
 {
         om->q[0] = cpu_to_le32(data_size);
         om->q[1] = cpu_to_le32(data_phys_addr);
-        om->q[2] = 0;
-        om->q[3] = 0;
+        om->q[2] = cpu_to_le32(0);
+        om->q[3] = cpu_to_le32(0);
 }
 
 static inline void fill_output_last(struct output_last *ol,
@@ -140,8 +140,8 @@ static inline void fill_output_last(struct output_last *ol,
 
         ol->q[0] = cpu_to_le32(temp);
         ol->q[1] = cpu_to_le32(data_phys_addr);
-        ol->q[2] = 0;
-        ol->q[3] = 0;
+        ol->q[2] = cpu_to_le32(0);
+        ol->q[3] = cpu_to_le32(0);
 }
 
 /* inputs */
@@ -161,8 +161,8 @@ static inline void fill_input_more(struct input_more *im,
 
         im->q[0] = cpu_to_le32(temp);
         im->q[1] = cpu_to_le32(data_phys_addr);
-        im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */
-        im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */
+        im->q[2] = cpu_to_le32(0); /* branchAddress and Z not use in packet-per-buffer mode */
+        im->q[3] = cpu_to_le32(0); /* xferStatus & resCount, resCount must be initialize to data_size */
 }
  
 static inline void fill_input_last(struct input_last *il,
@@ -331,7 +331,7 @@ struct frame {
 
         /* points to status/timestamp field of first DMA packet */
         /* (we'll check it later to monitor timestamp accuracy) */
-        u32 *frame_begin_timestamp;
+        __le32 *frame_begin_timestamp;
 
         /* the timestamp we assigned to the first packet in the frame */
         u32 assigned_timestamp;
@@ -348,15 +348,15 @@ struct frame {
            that can cause interrupts. We'll check these from the
            interrupt handler.
         */
-        u32 *mid_frame_timestamp;
-        u32 *frame_end_timestamp;
+        __le32 *mid_frame_timestamp;
+        __le32 *frame_end_timestamp;
 
         /* branch address field of final packet. This is effectively
            the "tail" in the chain of DMA descriptor blocks.
            We will fill it with the address of the first DMA descriptor
            block in the subsequent frame, once it is ready.
         */
-        u32 *frame_end_branch;
+        __le32 *frame_end_branch;
 
         /* the number of descriptors in the first descriptor block
            of the frame. Needed to start DMA */
@@ -365,10 +365,10 @@ struct frame {
 
 
 struct packet {
-        u16     timestamp;
+        __le16  timestamp;
         u16     invalid;
         u16     iso_header;
-        u16     data_length;
+        __le16  data_length;
         u32     cip_h1;
         u32     cip_h2;
         unsigned char data[480];
diff --git a/drivers/ieee1394/dv1394.c b/drivers/ieee1394/dv1394.c
index c19f23267157..a329e6bd5d2d 100644
--- a/drivers/ieee1394/dv1394.c
+++ b/drivers/ieee1394/dv1394.c
@@ -265,7 +265,7 @@ static void frame_prepare(struct video_card *video, unsigned int this_frame)
         /* these flags denote packets that need special attention */
         int empty_packet, first_packet, last_packet, mid_packet;
 
-        u32 *branch_address, *last_branch_address = NULL;
+        __le32 *branch_address, *last_branch_address = NULL;
         unsigned long data_p;
         int first_packet_empty = 0;
         u32 cycleTimer, ct_sec, ct_cyc, ct_off;
@@ -848,7 +848,7 @@ static void receive_packets(struct video_card *video)
         dma_addr_t block_dma = 0;
         struct packet *data = NULL;
         dma_addr_t data_dma = 0;
-        u32 *last_branch_address = NULL;
+        __le32 *last_branch_address = NULL;
         unsigned long irq_flags;
         int want_interrupt = 0;
         struct frame *f = NULL;
@@ -2110,17 +2110,17 @@ static void ir_tasklet_func(unsigned long data)
                         f = video->frames[next_i / MAX_PACKETS];
                         next = &(f->descriptor_pool[next_i % MAX_PACKETS]);
                         next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma;
-                        next->u.in.il.q[0] |= 3 << 20; /* enable interrupt */
-                        next->u.in.il.q[2] = 0; /* disable branch */
+                        next->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
+                        next->u.in.il.q[2] = cpu_to_le32(0); /* disable branch */
 
                         /* link previous to next */
                         prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1);
                         f = video->frames[prev_i / MAX_PACKETS];
                         prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]);
                         if (prev_i % (MAX_PACKETS/2)) {
-                                prev->u.in.il.q[0] &= ~(3 << 20); /* no interrupt */
+                                prev->u.in.il.q[0] &= ~cpu_to_le32(3 << 20); /* no interrupt */
                         } else {
-                                prev->u.in.il.q[0] |= 3 << 20; /* enable interrupt */
+                                prev->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */
                         }
                         prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */
                         wmb();
diff --git a/drivers/ieee1394/eth1394.c b/drivers/ieee1394/eth1394.c
index 20128692b339..a074bfd5f825 100644
--- a/drivers/ieee1394/eth1394.c
+++ b/drivers/ieee1394/eth1394.c
@@ -92,7 +92,7 @@ struct partial_datagram {
         struct list_head list;
         u16 dgl;
         u16 dg_size;
-        u16 ether_type;
+        __be16 ether_type;
         struct sk_buff *skb;
         char *pbuf;
         struct list_head frag_info;
@@ -181,7 +181,7 @@ static void ether1394_remove_host(struct hpsb_host *host);
 static void ether1394_host_reset(struct hpsb_host *host);
 
 /* Function for incoming 1394 packets */
-static struct hpsb_address_ops addr_ops = {
+const static struct hpsb_address_ops addr_ops = {
         .write =        ether1394_write,
 };
 
@@ -767,7 +767,7 @@ static int ether1394_header_parse(const struct sk_buff *skb,
 static int ether1394_header_cache(const struct neighbour *neigh,
                                   struct hh_cache *hh)
 {
-        unsigned short type = hh->hh_type;
+        __be16 type = hh->hh_type;
         struct net_device *dev = neigh->dev;
         struct eth1394hdr *eth =
                 (struct eth1394hdr *)((u8 *)hh->hh_data + 16 - ETH1394_HLEN);
@@ -795,7 +795,7 @@ static void ether1394_header_cache_update(struct hh_cache *hh,
  ******************************************/
 
 /* Copied from net/ethernet/eth.c */
-static u16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev)
+static __be16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev)
 {
         struct eth1394hdr *eth;
         unsigned char *rawp;
@@ -829,17 +829,17 @@ static u16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev)
 
 /* Parse an encapsulated IP1394 header into an ethernet frame packet.
  * We also perform ARP translation here, if need be.  */
-static u16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev,
+static __be16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev,
                                  nodeid_t srcid, nodeid_t destid,
-                                 u16 ether_type)
+                                 __be16 ether_type)
 {
         struct eth1394_priv *priv = netdev_priv(dev);
-        u64 dest_hw;
-        unsigned short ret = 0;
+        __be64 dest_hw;
+        __be16 ret = 0;
 
         /* Setup our hw addresses. We use these to build the ethernet header. */
         if (destid == (LOCAL_BUS | ALL_NODES))
-                dest_hw = ~0ULL;  /* broadcast */
+                dest_hw = ~cpu_to_be64(0);  /* broadcast */
         else
                 dest_hw = cpu_to_be64((u64)priv->host->csr.guid_hi << 32 |
                                       priv->host->csr.guid_lo);
@@ -873,7 +873,7 @@ static u16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev,
                 node = eth1394_find_node_guid(&priv->ip_node_list,
                                               be64_to_cpu(guid));
                 if (!node)
-                        return 0;
+                        return cpu_to_be16(0);
 
                 node_info =
                     (struct eth1394_node_info *)node->ud->device.driver_data;
@@ -1063,7 +1063,7 @@ static int ether1394_data_handler(struct net_device *dev, int srcid, int destid,
         unsigned long flags;
         struct eth1394_priv *priv = netdev_priv(dev);
         union eth1394_hdr *hdr = (union eth1394_hdr *)buf;
-        u16 ether_type = 0;  /* initialized to clear warning */
+        __be16 ether_type = cpu_to_be16(0);  /* initialized to clear warning */
         int hdr_len;
         struct unit_directory *ud = priv->ud_list[NODEID_TO_NODE(srcid)];
         struct eth1394_node_info *node_info;
@@ -1259,7 +1259,7 @@ static int ether1394_write(struct hpsb_host *host, int srcid, int destid,
 
 static void ether1394_iso(struct hpsb_iso *iso)
 {
-        quadlet_t *data;
+        __be32 *data;
         char *buf;
         struct eth1394_host_info *hi;
         struct net_device *dev;
@@ -1283,7 +1283,7 @@ static void ether1394_iso(struct hpsb_iso *iso)
         for (i = 0; i < nready; i++) {
                 struct hpsb_iso_packet_info *info =
                         &iso->infos[(iso->first_packet + i) % iso->buf_packets];
-                data = (quadlet_t *)(iso->data_buf.kvirt + info->offset);
+                data = (__be32 *)(iso->data_buf.kvirt + info->offset);
 
                 /* skip over GASP header */
                 buf = (char *)data + 8;
@@ -1614,7 +1614,7 @@ static int ether1394_tx(struct sk_buff *skb, struct net_device *dev)
                 if (max_payload < dg_size + hdr_type_len[ETH1394_HDR_LF_UF])
                         priv->bc_dgl++;
         } else {
-                __be64 guid = get_unaligned((u64 *)hdr_buf.h_dest);
+                __be64 guid = get_unaligned((__be64 *)hdr_buf.h_dest);
 
                 node = eth1394_find_node_guid(&priv->ip_node_list,
                                               be64_to_cpu(guid));
diff --git a/drivers/ieee1394/eth1394.h b/drivers/ieee1394/eth1394.h
index 4f3e2dd46f00..e1b5ea80f623 100644
--- a/drivers/ieee1394/eth1394.h
+++ b/drivers/ieee1394/eth1394.h
@@ -82,7 +82,7 @@ struct eth1394_priv {
 
 struct eth1394hdr {
         unsigned char   h_dest[ETH1394_ALEN];   /* destination eth1394 addr     */
-        unsigned short  h_proto;                /* packet type ID field */
+        __be16          h_proto;                /* packet type ID field */
 }  __attribute__((packed));
 
 static inline struct eth1394hdr *eth1394_hdr(const struct sk_buff *skb)
@@ -99,13 +99,13 @@ typedef enum {ETH1394_GASP, ETH1394_WRREQ} eth1394_tx_type;
 struct eth1394_uf_hdr {
         u16 lf:2;
         u16 res:14;
-        u16 ether_type;         /* Ethernet packet type */
+        __be16 ether_type;              /* Ethernet packet type */
 } __attribute__((packed));
 #elif defined __LITTLE_ENDIAN_BITFIELD
 struct eth1394_uf_hdr {
         u16 res:14;
         u16 lf:2;
-        u16 ether_type;
+        __be16 ether_type;
 } __attribute__((packed));
 #else
 #error Unknown bit field type
@@ -117,7 +117,7 @@ struct eth1394_ff_hdr {
         u16 lf:2;
         u16 res1:2;
         u16 dg_size:12;         /* Datagram size */
-        u16 ether_type;         /* Ethernet packet type */
+        __be16 ether_type;              /* Ethernet packet type */
         u16 dgl;                /* Datagram label */
         u16 res2;
 } __attribute__((packed));
@@ -126,7 +126,7 @@ struct eth1394_ff_hdr {
         u16 dg_size:12;
         u16 res1:2;
         u16 lf:2;
-        u16 ether_type;
+        __be16 ether_type;
         u16 dgl;
         u16 res2;
 } __attribute__((packed));
@@ -207,11 +207,11 @@ struct eth1394_arp {
         u16 opcode;             /* ARP Opcode   */
         /* Above is exactly the same format as struct arphdr */
 
-        u64 s_uniq_id;          /* Sender's 64bit EUI                   */
+        __be64 s_uniq_id;       /* Sender's 64bit EUI           */
         u8 max_rec;             /* Sender's max packet size             */
         u8 sspd;                /* Sender's max speed                   */
-        u16 fifo_hi;            /* hi 16bits of sender's FIFO addr      */
-        u32 fifo_lo;            /* lo 32bits of sender's FIFO addr      */
+        __be16 fifo_hi;         /* hi 16bits of sender's FIFO addr      */
+        __be32 fifo_lo;         /* lo 32bits of sender's FIFO addr      */
         u32 sip;                /* Sender's IP Address                  */
         u32 tip;                /* IP Address of requested hw addr      */
 };
diff --git a/drivers/ieee1394/highlevel.c b/drivers/ieee1394/highlevel.c
index 272543a42a43..600e391c8fe7 100644
--- a/drivers/ieee1394/highlevel.c
+++ b/drivers/ieee1394/highlevel.c
@@ -320,7 +320,7 @@ void hpsb_unregister_highlevel(struct hpsb_highlevel *hl)
  */
 u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl,
                                          struct hpsb_host *host,
-                                         struct hpsb_address_ops *ops,
+                                         const struct hpsb_address_ops *ops,
                                          u64 size, u64 alignment,
                                          u64 start, u64 end)
 {
@@ -407,7 +407,8 @@ u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl,
  * are automatically deallocated together with the hpsb_highlevel @hl.
  */
 int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host,
-                            struct hpsb_address_ops *ops, u64 start, u64 end)
+                            const struct hpsb_address_ops *ops,
+                            u64 start, u64 end)
 {
         struct hpsb_address_serve *as;
         struct list_head *lh;
@@ -420,7 +421,7 @@ int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host,
                 return 0;
         }
 
-        as = kmalloc(sizeof(*as), GFP_ATOMIC);
+        as = kmalloc(sizeof(*as), GFP_KERNEL);
         if (!as)
                 return 0;
 
@@ -477,7 +478,7 @@ int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host,
         return retval;
 }
 
-static struct hpsb_address_ops dummy_ops;
+const static struct hpsb_address_ops dummy_ops;
 
 /* dummy address spaces as lower and upper bounds of the host's a.s. list */
 static void init_hpsb_highlevel(struct hpsb_host *host)
diff --git a/drivers/ieee1394/highlevel.h b/drivers/ieee1394/highlevel.h
index bc5d0854c17e..9dba89fc60ad 100644
--- a/drivers/ieee1394/highlevel.h
+++ b/drivers/ieee1394/highlevel.h
@@ -15,7 +15,7 @@ struct hpsb_host;
 struct hpsb_address_serve {
         struct list_head host_list;     /* per host list */
         struct list_head hl_list;       /* hpsb_highlevel list */
-        struct hpsb_address_ops *op;
+        const struct hpsb_address_ops *op;
         struct hpsb_host *host;
         u64 start;      /* first address handled, quadlet aligned */
         u64 end;        /* first address behind, quadlet aligned */
@@ -119,11 +119,12 @@ void hpsb_unregister_highlevel(struct hpsb_highlevel *hl);
 
 u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl,
                                          struct hpsb_host *host,
-                                         struct hpsb_address_ops *ops,
+                                         const struct hpsb_address_ops *ops,
                                          u64 size, u64 alignment,
                                          u64 start, u64 end);
 int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host,
-                            struct hpsb_address_ops *ops, u64 start, u64 end);
+                            const struct hpsb_address_ops *ops,
+                            u64 start, u64 end);
 int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host,
                               u64 start);
 
diff --git a/drivers/ieee1394/hosts.c b/drivers/ieee1394/hosts.c
index 237d0c9d69c6..e947d8ffac85 100644
--- a/drivers/ieee1394/hosts.c
+++ b/drivers/ieee1394/hosts.c
@@ -34,18 +34,18 @@ static void delayed_reset_bus(struct work_struct *work)
 {
         struct hpsb_host *host =
                 container_of(work, struct hpsb_host, delayed_reset.work);
-        int generation = host->csr.generation + 1;
+        u8 generation = host->csr.generation + 1;
 
         /* The generation field rolls over to 2 rather than 0 per IEEE
          * 1394a-2000. */
         if (generation > 0xf || generation < 2)
                 generation = 2;
 
-        CSR_SET_BUS_INFO_GENERATION(host->csr.rom, generation);
+        csr_set_bus_info_generation(host->csr.rom, generation);
         if (csr1212_generate_csr_image(host->csr.rom) != CSR1212_SUCCESS) {
                 /* CSR image creation failed.
                  * Reset generation field and do not issue a bus reset. */
-                CSR_SET_BUS_INFO_GENERATION(host->csr.rom,
+                csr_set_bus_info_generation(host->csr.rom,
                                             host->csr.generation);
                 return;
         }
diff --git a/drivers/ieee1394/hosts.h b/drivers/ieee1394/hosts.h
index dd229950acca..49c359022c54 100644
--- a/drivers/ieee1394/hosts.h
+++ b/drivers/ieee1394/hosts.h
@@ -154,7 +154,7 @@ struct hpsb_host_driver {
          * to set the hardware ConfigROM if the hardware supports handling
          * reads to the ConfigROM on its own. */
         void (*set_hw_config_rom)(struct hpsb_host *host,
-                                  quadlet_t *config_rom);
+                                  __be32 *config_rom);
 
         /* This function shall implement packet transmission based on
          * packet->type.  It shall CRC both parts of the packet (unless
diff --git a/drivers/ieee1394/ieee1394.h b/drivers/ieee1394/ieee1394.h
index 40492074c013..e0ae0d3d747f 100644
--- a/drivers/ieee1394/ieee1394.h
+++ b/drivers/ieee1394/ieee1394.h
@@ -121,6 +121,9 @@ extern const char *hpsb_speedto_str[];
 
 #include <asm/byteorder.h>
 
+/* '1' '3' '9' '4' in ASCII */
+#define IEEE1394_BUSID_MAGIC    cpu_to_be32(0x31333934)
+
 #ifdef __BIG_ENDIAN_BITFIELD
 
 struct selfid {
diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c
index 79ef5fd928ae..906c5a98d814 100644
--- a/drivers/ieee1394/nodemgr.c
+++ b/drivers/ieee1394/nodemgr.c
@@ -67,7 +67,7 @@ static int nodemgr_check_speed(struct nodemgr_csr_info *ci, u64 addr,
         for (i = IEEE1394_SPEED_100; i <= old_speed; i++) {
                 *speed = i;
                 error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr,
-                                  &q, sizeof(quadlet_t));
+                                  &q, 4);
                 if (error)
                         break;
                 *buffer = q;
@@ -85,7 +85,7 @@ static int nodemgr_check_speed(struct nodemgr_csr_info *ci, u64 addr,
         return error;
 }
 
-static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length,
+static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr,
                             void *buffer, void *__ci)
 {
         struct nodemgr_csr_info *ci = (struct nodemgr_csr_info*)__ci;
@@ -93,7 +93,7 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length,
 
         for (i = 1; ; i++) {
                 error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr,
-                                  buffer, length);
+                                  buffer, 4);
                 if (!error) {
                         ci->speed_unverified = 0;
                         break;
@@ -104,7 +104,7 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length,
 
                 /* The ieee1394_core guessed the node's speed capability from
                  * the self ID.  Check whether a lower speed works. */
-                if (ci->speed_unverified && length == sizeof(quadlet_t)) {
+                if (ci->speed_unverified) {
                         error = nodemgr_check_speed(ci, addr, buffer);
                         if (!error)
                                 break;
@@ -115,20 +115,8 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length,
         return error;
 }
 
-#define OUI_FREECOM_TECHNOLOGIES_GMBH 0x0001db
-
-static int nodemgr_get_max_rom(quadlet_t *bus_info_data, void *__ci)
-{
-        /* Freecom FireWire Hard Drive firmware bug */
-        if (be32_to_cpu(bus_info_data[3]) >> 8 == OUI_FREECOM_TECHNOLOGIES_GMBH)
-                return 0;
-
-        return (be32_to_cpu(bus_info_data[2]) >> 8) & 0x3;
-}
-
 static struct csr1212_bus_ops nodemgr_csr_ops = {
         .bus_read =     nodemgr_bus_read,
-        .get_max_rom =  nodemgr_get_max_rom
 };
 
 
diff --git a/drivers/ieee1394/nodemgr.h b/drivers/ieee1394/nodemgr.h
index 4f287a3561ba..15ea09733e84 100644
--- a/drivers/ieee1394/nodemgr.h
+++ b/drivers/ieee1394/nodemgr.h
@@ -31,9 +31,6 @@ struct csr1212_keyval;
 struct hpsb_host;
 struct ieee1394_device_id;
 
-/* '1' '3' '9' '4' in ASCII */
-#define IEEE1394_BUSID_MAGIC    __constant_cpu_to_be32(0x31333934)
-
 /* This is the start of a Node entry structure. It should be a stable API
  * for which to gather info from the Node Manager about devices attached
  * to the bus.  */
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c
index e509e13cb7a7..65c1429e4129 100644
--- a/drivers/ieee1394/ohci1394.c
+++ b/drivers/ieee1394/ohci1394.c
@@ -2973,7 +2973,7 @@ alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
         return 0;
 }
 
-static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom)
+static void ohci_set_hw_config_rom(struct hpsb_host *host, __be32 *config_rom)
 {
         struct ti_ohci *ohci = host->hostdata;
 
@@ -3199,15 +3199,16 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
         /* Now enable LPS, which we need in order to start accessing
          * most of the registers.  In fact, on some cards (ALI M5251),
          * accessing registers in the SClk domain without LPS enabled
-         * will lock up the machine.  Wait 50msec to make sure we have
-         * full link enabled.  */
+         * will lock up the machine. */
         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
 
         /* Disable and clear interrupts */
         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
 
-        mdelay(50);
+        /* Flush MMIO writes and wait to make sure we have full link enabled. */
+        reg_read(ohci, OHCI1394_Version);
+        msleep(50);
 
         /* Determine the number of available IR and IT contexts. */
         ohci->nb_iso_rcv_ctx =
@@ -3233,8 +3234,9 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
          * we need to get to that "no event", so enough should be initialized
          * by that point.
          */
-        if (request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
-                         OHCI1394_DRIVER_NAME, ohci)) {
+        err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
+                          OHCI1394_DRIVER_NAME, ohci);
+        if (err) {
                 PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq);
                 goto err;
         }
@@ -3381,6 +3383,7 @@ static int ohci1394_pci_suspend(struct pci_dev *dev, pm_message_t state)
         ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
         ohci_soft_reset(ohci);
 
+        free_irq(dev->irq, ohci);
         err = pci_save_state(dev);
         if (err) {
                 PRINT(KERN_ERR, "pci_save_state failed with %d", err);
@@ -3420,7 +3423,16 @@ static int ohci1394_pci_resume(struct pci_dev *dev)
         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
-        mdelay(50);
+        reg_read(ohci, OHCI1394_Version);
+        msleep(50);
+
+        err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
+                          OHCI1394_DRIVER_NAME, ohci);
+        if (err) {
+                PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq);
+                return err;
+        }
+
         ohci_initialize(ohci);
 
         hpsb_resume_host(ohci->host);
diff --git a/drivers/ieee1394/pcilynx.c b/drivers/ieee1394/pcilynx.c
index 7aee1ac97c80..dc15cadb06ef 100644
--- a/drivers/ieee1394/pcilynx.c
+++ b/drivers/ieee1394/pcilynx.c
@@ -1463,7 +1463,7 @@ static int __devinit add_card(struct pci_dev *dev,
 
                                 /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */
                                 if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) &&
-                                    (lynx->bus_info_block[1] == __constant_cpu_to_be32(0x31333934)))
+                                    (lynx->bus_info_block[1] == IEEE1394_BUSID_MAGIC))
                                 {
                                         PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from");
                                 } else {
diff --git a/drivers/ieee1394/pcilynx.h b/drivers/ieee1394/pcilynx.h
index ec27321f6724..693a169acea3 100644
--- a/drivers/ieee1394/pcilynx.h
+++ b/drivers/ieee1394/pcilynx.h
@@ -52,7 +52,7 @@ struct ti_lynx {
         void __iomem *local_rom;
         void __iomem *local_ram;
         void __iomem *aux_port;
-        quadlet_t bus_info_block[5];
+        __be32 bus_info_block[5];
 
         /*
          * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
diff --git a/drivers/ieee1394/raw1394.c b/drivers/ieee1394/raw1394.c
index bf7e761c12b1..bad66c65b0d6 100644
--- a/drivers/ieee1394/raw1394.c
+++ b/drivers/ieee1394/raw1394.c
@@ -90,7 +90,7 @@ static int arm_lock(struct hpsb_host *host, int nodeid, quadlet_t * store,
 static int arm_lock64(struct hpsb_host *host, int nodeid, octlet_t * store,
                       u64 addr, octlet_t data, octlet_t arg, int ext_tcode,
                       u16 flags);
-static struct hpsb_address_ops arm_ops = {
+const static struct hpsb_address_ops arm_ops = {
         .read = arm_read,
         .write = arm_write,
         .lock = arm_lock,
diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c
index a373c18cf7b8..ab1034ccb7fb 100644
--- a/drivers/ieee1394/sbp2.c
+++ b/drivers/ieee1394/sbp2.c
@@ -265,7 +265,7 @@ static struct hpsb_highlevel sbp2_highlevel = {
         .host_reset     = sbp2_host_reset,
 };
 
-static struct hpsb_address_ops sbp2_ops = {
+const static struct hpsb_address_ops sbp2_ops = {
         .write          = sbp2_handle_status_write
 };
 
@@ -275,7 +275,7 @@ static int sbp2_handle_physdma_write(struct hpsb_host *, int, int, quadlet_t *,
 static int sbp2_handle_physdma_read(struct hpsb_host *, int, quadlet_t *, u64,
                                     size_t, u16);
 
-static struct hpsb_address_ops sbp2_physdma_ops = {
+const static struct hpsb_address_ops sbp2_physdma_ops = {
         .read           = sbp2_handle_physdma_read,
         .write          = sbp2_handle_physdma_write,
 };
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c
index a3c5af1d7ec0..de5263beab4a 100644
--- a/drivers/infiniband/hw/mlx4/cq.c
+++ b/drivers/infiniband/hw/mlx4/cq.c
@@ -367,7 +367,7 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
                 if (err)
                         goto out;
         } else {
-                /* Can't be smaller then the number of outstanding CQEs */
+                /* Can't be smaller than the number of outstanding CQEs */
                 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
                 if (entries < outst_cqe + 1) {
                         err = 0;
diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c
index f6e9f39a527b..c3c8b9bc40ae 100644
--- a/drivers/input/keyboard/atkbd.c
+++ b/drivers/input/keyboard/atkbd.c
@@ -65,7 +65,7 @@ MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and
 
 /*
  * Scancode to keycode tables. These are just the default setting, and
- * are loadable via an userland utility.
+ * are loadable via a userland utility.
  */
 
 static const unsigned short atkbd_set2_keycode[512] = {
diff --git a/drivers/input/misc/apanel.c b/drivers/input/misc/apanel.c
index d82f7f727f7a..71b82434264d 100644
--- a/drivers/input/misc/apanel.c
+++ b/drivers/input/misc/apanel.c
@@ -57,7 +57,7 @@ static enum apanel_chip device_chip[APANEL_DEV_MAX];
 
 struct apanel {
         struct input_polled_dev *ipdev;
-        struct i2c_client client;
+        struct i2c_client *client;
         unsigned short keymap[MAX_PANEL_KEYS];
         u16    nkeys;
         u16    led_bits;
@@ -66,16 +66,7 @@ struct apanel {
 };
 
 
-static int apanel_probe(struct i2c_adapter *, int, int);
-
-/* for now, we only support one address */
-static unsigned short normal_i2c[] = {0, I2C_CLIENT_END};
-static unsigned short ignore = I2C_CLIENT_END;
-static struct i2c_client_address_data addr_data = {
-        .normal_i2c     = normal_i2c,
-        .probe          = &ignore,
-        .ignore         = &ignore,
-};
+static int apanel_probe(struct i2c_client *, const struct i2c_device_id *);
 
 static void report_key(struct input_dev *input, unsigned keycode)
 {
@@ -103,12 +94,12 @@ static void apanel_poll(struct input_polled_dev *ipdev)
         s32 data;
         int i;
 
-        data = i2c_smbus_read_word_data(&ap->client, cmd);
+        data = i2c_smbus_read_word_data(ap->client, cmd);
         if (data < 0)
                 return; /* ignore errors (due to ACPI??) */
 
         /* write back to clear latch */
-        i2c_smbus_write_word_data(&ap->client, cmd, 0);
+        i2c_smbus_write_word_data(ap->client, cmd, 0);
 
         if (!data)
                 return;
@@ -124,7 +115,7 @@ static void led_update(struct work_struct *work)
 {
         struct apanel *ap = container_of(work, struct apanel, led_work);
 
-        i2c_smbus_write_word_data(&ap->client, 0x10, ap->led_bits);
+        i2c_smbus_write_word_data(ap->client, 0x10, ap->led_bits);
 }
 
 static void mail_led_set(struct led_classdev *led,
@@ -140,7 +131,7 @@ static void mail_led_set(struct led_classdev *led,
         schedule_work(&ap->led_work);
 }
 
-static int apanel_detach_client(struct i2c_client *client)
+static int apanel_remove(struct i2c_client *client)
 {
         struct apanel *ap = i2c_get_clientdata(client);
 
@@ -148,43 +139,33 @@ static int apanel_detach_client(struct i2c_client *client)
                 led_classdev_unregister(&ap->mail_led);
 
         input_unregister_polled_device(ap->ipdev);
-        i2c_detach_client(&ap->client);
         input_free_polled_device(ap->ipdev);
 
         return 0;
 }
 
-/* Function is invoked for every i2c adapter. */
-static int apanel_attach_adapter(struct i2c_adapter *adap)
-{
-        dev_dbg(&adap->dev, APANEL ": attach adapter id=%d\n", adap->id);
-
-        /* Our device is connected only to i801 on laptop */
-        if (adap->id != I2C_HW_SMBUS_I801)
-                return -ENODEV;
-
-        return i2c_probe(adap, &addr_data, apanel_probe);
-}
-
 static void apanel_shutdown(struct i2c_client *client)
 {
-        apanel_detach_client(client);
+        apanel_remove(client);
 }
 
+static struct i2c_device_id apanel_id[] = {
+        { "fujitsu_apanel", 0 },
+        { }
+};
+MODULE_DEVICE_TABLE(i2c, apanel_id);
+
 static struct i2c_driver apanel_driver = {
         .driver = {
                 .name = APANEL,
         },
-        .attach_adapter = &apanel_attach_adapter,
-        .detach_client  = &apanel_detach_client,
+        .probe          = &apanel_probe,
+        .remove         = &apanel_remove,
         .shutdown       = &apanel_shutdown,
+        .id_table       = apanel_id,
 };
 
 static struct apanel apanel = {
-        .client = {
-                .driver = &apanel_driver,
-                .name   = APANEL,
-        },
         .keymap = {
                 [0] = KEY_MAIL,
                 [1] = KEY_WWW,
@@ -204,7 +185,8 @@ static struct apanel apanel = {
 };
 
 /* NB: Only one panel on the i2c. */
-static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
+static int apanel_probe(struct i2c_client *client,
+                        const struct i2c_device_id *id)
 {
         struct apanel *ap;
         struct input_polled_dev *ipdev;
@@ -212,9 +194,6 @@ static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
         u8 cmd = device_chip[APANEL_DEV_APPBTN] == CHIP_OZ992C ? 0 : 8;
         int i, err = -ENOMEM;
 
-        dev_dbg(&bus->dev, APANEL ": probe adapter %p addr %d kind %d\n",
-                bus, address, kind);
-
         ap = &apanel;
 
         ipdev = input_allocate_polled_device();
@@ -222,18 +201,13 @@ static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
                 goto out1;
 
         ap->ipdev = ipdev;
-        ap->client.adapter = bus;
-        ap->client.addr = address;
-
-        i2c_set_clientdata(&ap->client, ap);
+        ap->client = client;
 
-        err = i2c_attach_client(&ap->client);
-        if (err)
-                goto out2;
+        i2c_set_clientdata(client, ap);
 
-        err = i2c_smbus_write_word_data(&ap->client, cmd, 0);
+        err = i2c_smbus_write_word_data(client, cmd, 0);
         if (err) {
-                dev_warn(&ap->client.dev, APANEL ": smbus write error %d\n",
+                dev_warn(&client->dev, APANEL ": smbus write error %d\n",
                          err);
                 goto out3;
         }
@@ -246,7 +220,7 @@ static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
         idev->name = APANEL_NAME " buttons";
         idev->phys = "apanel/input0";
         idev->id.bustype = BUS_HOST;
-        idev->dev.parent = &ap->client.dev;
+        idev->dev.parent = &client->dev;
 
         set_bit(EV_KEY, idev->evbit);
 
@@ -264,7 +238,7 @@ static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
 
         INIT_WORK(&ap->led_work, led_update);
         if (device_chip[APANEL_DEV_LED] != CHIP_NONE) {
-                err = led_classdev_register(&ap->client.dev, &ap->mail_led);
+                err = led_classdev_register(&client->dev, &ap->mail_led);
                 if (err)
                         goto out4;
         }
@@ -273,8 +247,6 @@ static int apanel_probe(struct i2c_adapter *bus, int address, int kind)
 out4:
         input_unregister_polled_device(ipdev);
 out3:
-        i2c_detach_client(&ap->client);
-out2:
         input_free_polled_device(ipdev);
 out1:
         return err;
@@ -301,6 +273,7 @@ static int __init apanel_init(void)
         void __iomem *bios;
         const void __iomem *p;
         u8 devno;
+        unsigned char i2c_addr;
         int found = 0;
 
         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
@@ -313,7 +286,7 @@ static int __init apanel_init(void)
 
         /* just use the first address */
         p += 8;
-        normal_i2c[0] = readb(p+3) >> 1;
+        i2c_addr = readb(p + 3) >> 1;
 
         for ( ; (devno = readb(p)) & 0x7f; p += 4) {
                 unsigned char method, slave, chip;
@@ -322,7 +295,7 @@ static int __init apanel_init(void)
                 chip = readb(p + 2);
                 slave = readb(p + 3) >> 1;
 
-                if (slave != normal_i2c[0]) {
+                if (slave != i2c_addr) {
                         pr_notice(APANEL ": only one SMBus slave "
                                   "address supported, skiping device...\n");
                         continue;
diff --git a/drivers/input/touchscreen/da9034-ts.c b/drivers/input/touchscreen/da9034-ts.c
index 4342e77814b5..fa67d782c3c3 100644
--- a/drivers/input/touchscreen/da9034-ts.c
+++ b/drivers/input/touchscreen/da9034-ts.c
@@ -16,6 +16,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
+#include <linux/workqueue.h>
 #include <linux/mfd/da903x.h>
 
 #define DA9034_MANUAL_CTRL      0x50
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index b52659620d50..173cf55c64d0 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -138,7 +138,7 @@ config PMAC_BACKLIGHT
           Say Y here to enable Macintosh specific extensions of the generic
           backlight code. With this enabled, the brightness keys on older
           PowerBooks will be enabled so you can change the screen brightness.
-          Newer models should use an userspace daemon like pbbuttonsd.
+          Newer models should use a userspace daemon like pbbuttonsd.
 
 config PMAC_BACKLIGHT_LEGACY
         bool "Provide legacy ioctl's on /dev/pmu for the backlight"
diff --git a/drivers/media/video/cafe_ccic.c b/drivers/media/video/cafe_ccic.c
index 34a39d2e4703..46fd573a4f15 100644
--- a/drivers/media/video/cafe_ccic.c
+++ b/drivers/media/video/cafe_ccic.c
@@ -569,7 +569,6 @@ static int cafe_smbus_setup(struct cafe_camera *cam)
 
         cafe_smbus_enable_irq(cam);
         adap->id = I2C_HW_SMBUS_CAFE;
-        adap->class = I2C_CLASS_CAM_DIGITAL;
         adap->owner = THIS_MODULE;
         adap->client_register = cafe_smbus_attach;
         adap->client_unregister = cafe_smbus_detach;
diff --git a/drivers/media/video/ov7670.c b/drivers/media/video/ov7670.c
index ca26b0c50cf2..05c14a29375a 100644
--- a/drivers/media/video/ov7670.c
+++ b/drivers/media/video/ov7670.c
@@ -1347,7 +1347,6 @@ static struct i2c_driver ov7670_driver = {
                 .name = "ov7670",
         },
         .id             = I2C_DRIVERID_OV7670,
-        .class          = I2C_CLASS_CAM_DIGITAL,
         .attach_adapter = ov7670_attach,
         .detach_client  = ov7670_detach,
         .command        = ov7670_command,
diff --git a/drivers/media/video/ovcamchip/ovcamchip_core.c b/drivers/media/video/ovcamchip/ovcamchip_core.c
index 2c4acbf5a4fe..c841f4e4fbe4 100644
--- a/drivers/media/video/ovcamchip/ovcamchip_core.c
+++ b/drivers/media/video/ovcamchip/ovcamchip_core.c
@@ -405,7 +405,6 @@ static struct i2c_driver driver = {
                 .name =         "ovcamchip",
         },
         .id =                   I2C_DRIVERID_OVCAMCHIP,
-        .class =                I2C_CLASS_CAM_DIGITAL,
         .attach_adapter =       ovcamchip_attach,
         .detach_client =        ovcamchip_detach,
         .command =              ovcamchip_command,
diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw.c b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
index 8fb92ac78c7b..fa304e5f252a 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
@@ -3655,7 +3655,7 @@ void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
         int ret;
         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
-        if (ret == 1) {
+        if (ret == 0) {
                 ret = usb_reset_device(hdw->usb_dev);
                 usb_unlock_device(hdw->usb_dev);
         } else {
diff --git a/drivers/media/video/w9968cf.c b/drivers/media/video/w9968cf.c
index a3997b7d4366..105a832531f2 100644
--- a/drivers/media/video/w9968cf.c
+++ b/drivers/media/video/w9968cf.c
@@ -1553,7 +1553,6 @@ static int w9968cf_i2c_init(struct w9968cf_device* cam)
 
         static struct i2c_adapter adap = {
                 .id =                I2C_HW_SMBUS_W9968CF,
-                .class =             I2C_CLASS_CAM_DIGITAL,
                 .owner =             THIS_MODULE,
                 .client_register =   w9968cf_i2c_attach_inform,
                 .client_unregister = w9968cf_i2c_detach_inform,
diff --git a/drivers/message/i2o/i2o_scsi.c b/drivers/message/i2o/i2o_scsi.c
index 1bcdbbb9e7d3..3d45817e6dcd 100644
--- a/drivers/message/i2o/i2o_scsi.c
+++ b/drivers/message/i2o/i2o_scsi.c
@@ -390,7 +390,7 @@ static int i2o_scsi_reply(struct i2o_controller *c, u32 m,
  *      @i2o_dev: the I2O device which was added
  *
  *      If a I2O device is added we catch the notification, because I2O classes
- *      other then SCSI peripheral will not be received through
+ *      other than SCSI peripheral will not be received through
  *      i2o_scsi_probe().
  */
 static void i2o_scsi_notify_device_add(struct i2o_device *i2o_dev)
diff --git a/drivers/misc/ibmasm/event.c b/drivers/misc/ibmasm/event.c
index fda6a4d3bf23..68a0a5b94795 100644
--- a/drivers/misc/ibmasm/event.c
+++ b/drivers/misc/ibmasm/event.c
@@ -50,7 +50,7 @@ static void wake_up_event_readers(struct service_processor *sp)
  * Store the event in the circular event buffer, wake up any sleeping
  * event readers.
  * There is no reader marker in the buffer, therefore readers are
- * responsible for keeping up with the writer, or they will loose events.
+ * responsible for keeping up with the writer, or they will lose events.
  */
 void ibmasm_receive_event(struct service_processor *sp, void *data, unsigned int data_size)
 {
diff --git a/drivers/misc/phantom.c b/drivers/misc/phantom.c
index abdebe347383..fa57b67593ae 100644
--- a/drivers/misc/phantom.c
+++ b/drivers/misc/phantom.c
@@ -6,7 +6,7 @@
  *  the Free Software Foundation; either version 2 of the License, or
  *  (at your option) any later version.
  *
- *  You need an userspace library to cooperate with this driver. It (and other
+ *  You need a userspace library to cooperate with this driver. It (and other
  *  info) may be obtained here:
  *  http://www.fi.muni.cz/~xslaby/phantom.html
  *  or alternatively, you might use OpenHaptics provided by Sensable.
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 7a3f2436b011..1e97916914ad 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -25,8 +25,8 @@
 #include <linux/stat.h>
 
 #include <linux/mmc/host.h>
+#include <linux/atmel-mci.h>
 
-#include <asm/atmel-mci.h>
 #include <asm/io.h>
 #include <asm/unaligned.h>
 
diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c
index d38bca64bb15..d2fd550f7e09 100644
--- a/drivers/mtd/devices/pmc551.c
+++ b/drivers/mtd/devices/pmc551.c
@@ -34,7 +34,7 @@
  *      aperture size, not the dram size, and the V370PDC supplies no
  *      other method for memory size discovery.  This problem is
  *      mostly only relevant when compiled as a module, as the
- *      unloading of the module with an aperture size smaller then
+ *      unloading of the module with an aperture size smaller than
  *      the ram will cause the driver to detect the onboard memory
  *      size to be equal to the aperture size when the module is
  *      reloaded.  Soooo, to help, the module supports an msize
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 048a606cebde..25def348e5ba 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -717,7 +717,7 @@ write_error:
  * to the real data size, although the @buf buffer has to contain the
  * alignment. In all other cases, @len has to be aligned.
  *
- * It is prohibited to write more then once to logical eraseblocks of static
+ * It is prohibited to write more than once to logical eraseblocks of static
  * volumes. This function returns zero in case of success and a negative error
  * code in case of failure.
  */
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index a74118c05745..fe81039f2a7c 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -465,7 +465,7 @@ out:
  * This function synchronously erases physical eraseblock @pnum. If @torture
  * flag is not zero, the physical eraseblock is checked by means of writing
  * different patterns to it and reading them back. If the torturing is enabled,
- * the physical eraseblock is erased more then once.
+ * the physical eraseblock is erased more than once.
  *
  * This function returns the number of erasures made in case of success, %-EIO
  * if the erasure failed or the torturing test failed, and other negative error
diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c
index 41d47e1cf15c..ecde202a5a12 100644
--- a/drivers/mtd/ubi/scan.c
+++ b/drivers/mtd/ubi/scan.c
@@ -478,7 +478,7 @@ int ubi_scan_add_used(struct ubi_device *ubi, struct ubi_scan_info *si,
                         return 0;
                 } else {
                         /*
-                         * This logical eraseblock is older then the one found
+                         * This logical eraseblock is older than the one found
                          * previously.
                          */
                         if (cmp_res & 4)
diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h
index 2ad940409053..8419fdccc79c 100644
--- a/drivers/mtd/ubi/ubi-media.h
+++ b/drivers/mtd/ubi/ubi-media.h
@@ -135,7 +135,7 @@ enum {
  * The erase counter header takes 64 bytes and has a plenty of unused space for
  * future usage. The unused fields are zeroed. The @version field is used to
  * indicate the version of UBI implementation which is supposed to be able to
- * work with this UBI image. If @version is greater then the current UBI
+ * work with this UBI image. If @version is greater than the current UBI
  * version, the image is rejected. This may be useful in future if something
  * is changed radically. This field is duplicated in the volume identifier
  * header.
@@ -187,7 +187,7 @@ struct ubi_ec_hdr {
  * (sequence number) is used to distinguish between older and newer versions of
  * logical eraseblocks.
  *
- * There are 2 situations when there may be more then one physical eraseblock
+ * There are 2 situations when there may be more than one physical eraseblock
  * corresponding to the same logical eraseblock, i.e., having the same @vol_id
  * and @lnum values in the volume identifier header. Suppose we have a logical
  * eraseblock L and it is mapped to the physical eraseblock P.
diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index 333c8941552f..1afc61e7455d 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -577,7 +577,7 @@ static int init_volumes(struct ubi_device *ubi, const struct ubi_scan_info *si,
                 if (vtbl[i].flags & UBI_VTBL_AUTORESIZE_FLG) {
                         /* Auto re-size flag may be set only for one volume */
                         if (ubi->autoresize_vol_id != -1) {
-                                ubi_err("more then one auto-resize volume (%d "
+                                ubi_err("more than one auto-resize volume (%d "
                                         "and %d)", ubi->autoresize_vol_id, i);
                                 kfree(vol);
                                 return -EINVAL;
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 14901cb82c18..891534f8210d 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -128,7 +128,7 @@
  * situation when the picked physical eraseblock is constantly erased after the
  * data is written to it. So, we have a constant which limits the highest erase
  * counter of the free physical eraseblock to pick. Namely, the WL sub-system
- * does not pick eraseblocks with erase counter greater then the lowest erase
+ * does not pick eraseblocks with erase counter greater than the lowest erase
  * counter plus %WL_FREE_MAX_DIFF.
  */
 #define WL_FREE_MAX_DIFF (2*UBI_WL_THRESHOLD)
@@ -917,7 +917,7 @@ static int ensure_wear_leveling(struct ubi_device *ubi)
                 /*
                  * We schedule wear-leveling only if the difference between the
                  * lowest erase counter of used physical eraseblocks and a high
-                 * erase counter of free physical eraseblocks is greater then
+                 * erase counter of free physical eraseblocks is greater than
                  * %UBI_WL_THRESHOLD.
                  */
                 e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9a18270c1081..97ea7c60e002 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2614,6 +2614,8 @@ source "drivers/net/tokenring/Kconfig"
 
 source "drivers/net/wireless/Kconfig"
 
+source "drivers/net/wimax/Kconfig"
+
 source "drivers/net/usb/Kconfig"
 
 source "drivers/net/pcmcia/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e5c34b464211..a3c5c002f224 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -263,3 +263,4 @@ obj-$(CONFIG_NIU) += niu.o
 obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
 obj-$(CONFIG_SFC) += sfc/
 
+obj-$(CONFIG_WIMAX) += wimax/
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 67de94f1f30e..fefa6ab13064 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -3359,7 +3359,7 @@ static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
         u8 shift = 8*4;
         u8 digit;
         if (len < 10) {
-                /* Need more then 10chars for this format */
+                /* Need more than 10chars for this format */
                 *str_ptr = '\0';
                 return -EINVAL;
         }
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index d04eef53571e..e1a3fc1303ee 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -6758,7 +6758,7 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
  *
- * For phy's older then IGP, this function simply reads the polarity bit in the
+ * For phy's older than IGP, this function simply reads the polarity bit in the
  * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
  * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
  * return 0.  If the link speed is 1000 Mbps the polarity status is in the
@@ -6834,7 +6834,7 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
  *
- * For phy's older then IGP, this function reads the Downshift bit in the Phy
+ * For phy's older than IGP, this function reads the Downshift bit in the Phy
  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
  * Link Health register.  In IGP this bit is latched high, so the driver must
  * read it immediately after link is established.
diff --git a/drivers/net/slip.h b/drivers/net/slip.h
index 853e0f6ec710..9ea5c11287d2 100644
--- a/drivers/net/slip.h
+++ b/drivers/net/slip.h
@@ -75,7 +75,7 @@ struct slip {
   unsigned long         tx_errors;      /* Planned stuff                */
   unsigned long         rx_dropped;     /* No memory for skb            */
   unsigned long         tx_dropped;     /* When MTU change              */
-  unsigned long         rx_over_errors; /* Frame bigger then SLIP buf.  */
+  unsigned long         rx_over_errors; /* Frame bigger than SLIP buf.  */
 #ifdef SL_INCLUDE_CSLIP
   unsigned long         tx_compressed;
   unsigned long         rx_compressed;
diff --git a/drivers/net/tehuti.c b/drivers/net/tehuti.c
index a10a83a11d9f..a7a4dc4d6313 100644
--- a/drivers/net/tehuti.c
+++ b/drivers/net/tehuti.c
@@ -1004,7 +1004,7 @@ static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
  * skb for rx. It assumes that Rx is desabled in HW
  * funcs are grouped for better cache usage
  *
- * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be
+ * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
  * filled and packets will be dropped by nic without getting into host or
  * cousing interrupt. Anyway, in that condition, host has no chance to proccess
  * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
@@ -1826,7 +1826,7 @@ static void bdx_tx_free(struct bdx_priv *priv)
  *
  * Pushes desc to TxD fifo and overlaps it if needed.
  * NOTE: this func does not check for available space. this is responsibility
- *    of the caller. Neither does it check that data size is smaller then
+ *    of the caller. Neither does it check that data size is smaller than
  *    fifo size.
  */
 static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
diff --git a/drivers/net/tokenring/smctr.c b/drivers/net/tokenring/smctr.c
index a011666342ff..50eb29ce3c87 100644
--- a/drivers/net/tokenring/smctr.c
+++ b/drivers/net/tokenring/smctr.c
@@ -3064,7 +3064,7 @@ static int smctr_load_node_addr(struct net_device *dev)
  * will consequently cause a timeout.
  *
  * NOTE 1: If the monitor_state is MS_BEACON_TEST_STATE, all transmit
- * queues other then the one used for the lobe_media_test should be
+ * queues other than the one used for the lobe_media_test should be
  * disabled.!?
  *
  * NOTE 2: If the monitor_state is MS_BEACON_TEST_STATE and the receive_mask
diff --git a/drivers/net/usb/kaweth.c b/drivers/net/usb/kaweth.c
index 2ee034f70d1c..3073ca25a0b0 100644
--- a/drivers/net/usb/kaweth.c
+++ b/drivers/net/usb/kaweth.c
@@ -283,9 +283,9 @@ static int kaweth_control(struct kaweth_device *kaweth,
 
         dr->bRequestType= requesttype;
         dr->bRequest = request;
-        dr->wValue = cpu_to_le16p(&value);
-        dr->wIndex = cpu_to_le16p(&index);
-        dr->wLength = cpu_to_le16p(&size);
+        dr->wValue = cpu_to_le16(value);
+        dr->wIndex = cpu_to_le16(index);
+        dr->wLength = cpu_to_le16(size);
 
         return kaweth_internal_control_msg(kaweth->dev,
                                         pipe,
diff --git a/drivers/net/usb/pegasus.c b/drivers/net/usb/pegasus.c
index 166880c113d6..d9241f1c0803 100644
--- a/drivers/net/usb/pegasus.c
+++ b/drivers/net/usb/pegasus.c
@@ -150,8 +150,8 @@ static int get_registers(pegasus_t * pegasus, __u16 indx, __u16 size,
         pegasus->dr.bRequestType = PEGASUS_REQT_READ;
         pegasus->dr.bRequest = PEGASUS_REQ_GET_REGS;
         pegasus->dr.wValue = cpu_to_le16(0);
-        pegasus->dr.wIndex = cpu_to_le16p(&indx);
-        pegasus->dr.wLength = cpu_to_le16p(&size);
+        pegasus->dr.wIndex = cpu_to_le16(indx);
+        pegasus->dr.wLength = cpu_to_le16(size);
         pegasus->ctrl_urb->transfer_buffer_length = size;
 
         usb_fill_control_urb(pegasus->ctrl_urb, pegasus->usb,
@@ -208,8 +208,8 @@ static int set_registers(pegasus_t * pegasus, __u16 indx, __u16 size,
         pegasus->dr.bRequestType = PEGASUS_REQT_WRITE;
         pegasus->dr.bRequest = PEGASUS_REQ_SET_REGS;
         pegasus->dr.wValue = cpu_to_le16(0);
-        pegasus->dr.wIndex = cpu_to_le16p(&indx);
-        pegasus->dr.wLength = cpu_to_le16p(&size);
+        pegasus->dr.wIndex = cpu_to_le16(indx);
+        pegasus->dr.wLength = cpu_to_le16(size);
         pegasus->ctrl_urb->transfer_buffer_length = size;
 
         usb_fill_control_urb(pegasus->ctrl_urb, pegasus->usb,
@@ -261,7 +261,7 @@ static int set_register(pegasus_t * pegasus, __u16 indx, __u8 data)
         pegasus->dr.bRequestType = PEGASUS_REQT_WRITE;
         pegasus->dr.bRequest = PEGASUS_REQ_SET_REG;
         pegasus->dr.wValue = cpu_to_le16(data);
-        pegasus->dr.wIndex = cpu_to_le16p(&indx);
+        pegasus->dr.wIndex = cpu_to_le16(indx);
         pegasus->dr.wLength = cpu_to_le16(1);
         pegasus->ctrl_urb->transfer_buffer_length = 1;
 
@@ -476,7 +476,7 @@ static inline void get_node_id(pegasus_t * pegasus, __u8 * id)
 
         for (i = 0; i < 3; i++) {
                 read_eprom_word(pegasus, i, &w16);
-                ((__le16 *) id)[i] = cpu_to_le16p(&w16);
+                ((__le16 *) id)[i] = cpu_to_le16(w16);
         }
 }
 
diff --git a/drivers/net/wimax/Kconfig b/drivers/net/wimax/Kconfig
new file mode 100644
index 000000000000..565018ec1e3b
--- /dev/null
+++ b/drivers/net/wimax/Kconfig
@@ -0,0 +1,17 @@
+#
+# WiMAX LAN device drivers configuration
+#
+
+
+comment "Enable WiMAX (Networking options) to see the WiMAX drivers"
+        depends on WIMAX = n
+
+if WIMAX
+
+menu "WiMAX Wireless Broadband devices"
+
+source "drivers/net/wimax/i2400m/Kconfig"
+
+endmenu
+
+endif
diff --git a/drivers/net/wimax/Makefile b/drivers/net/wimax/Makefile
new file mode 100644
index 000000000000..992bc02bc016
--- /dev/null
+++ b/drivers/net/wimax/Makefile
@@ -0,0 +1,5 @@
+
+obj-$(CONFIG_WIMAX_I2400M)      += i2400m/
+
+# (from Sam Ravnborg) force kbuild to create built-in.o
+obj- := dummy.o
diff --git a/drivers/net/wimax/i2400m/Kconfig b/drivers/net/wimax/i2400m/Kconfig
new file mode 100644
index 000000000000..d623b3d99a4b
--- /dev/null
+++ b/drivers/net/wimax/i2400m/Kconfig
@@ -0,0 +1,49 @@
+
+config WIMAX_I2400M
+        tristate
+        depends on WIMAX
+        select FW_LOADER
+
+comment "Enable USB support to see WiMAX USB drivers"
+        depends on USB = n
+
+comment "Enable MMC support to see WiMAX SDIO drivers"
+        depends on MMC = n
+
+config WIMAX_I2400M_USB
+        tristate "Intel Wireless WiMAX Connection 2400 over USB (including 5x50)"
+        depends on WIMAX && USB
+        select WIMAX_I2400M
+        help
+          Select if you have a device based on the Intel WiMAX
+          Connection 2400 over USB (like any of the Intel Wireless
+          WiMAX/WiFi Link 5x50 series).
+
+          If unsure, it is safe to select M (module).
+
+config WIMAX_I2400M_SDIO
+        tristate "Intel Wireless WiMAX Connection 2400 over SDIO"
+        depends on WIMAX && MMC
+        select WIMAX_I2400M
+        help
+          Select if you have a device based on the Intel WiMAX
+          Connection 2400 over SDIO.
+
+          If unsure, it is safe to select M (module).
+
+config WIMAX_I2400M_DEBUG_LEVEL
+        int "WiMAX i2400m debug level"
+        depends on WIMAX_I2400M
+        default 8
+        help
+
+          Select the maximum debug verbosity level to be compiled into
+          the WiMAX i2400m driver code.
+
+          By default, this is disabled at runtime and can be
+          selectively enabled at runtime for different parts of the
+          code using the sysfs debug-levels file.
+
+          If set at zero, this will compile out all the debug code.
+
+          It is recommended that it is left at 8.
diff --git a/drivers/net/wimax/i2400m/Makefile b/drivers/net/wimax/i2400m/Makefile
new file mode 100644
index 000000000000..1696e936cf5a
--- /dev/null
+++ b/drivers/net/wimax/i2400m/Makefile
@@ -0,0 +1,29 @@
+
+obj-$(CONFIG_WIMAX_I2400M) += i2400m.o
+obj-$(CONFIG_WIMAX_I2400M_USB) += i2400m-usb.o
+obj-$(CONFIG_WIMAX_I2400M_SDIO) += i2400m-sdio.o
+
+i2400m-y :=             \
+        control.o       \
+        driver.o        \
+        fw.o            \
+        op-rfkill.o     \
+        netdev.o        \
+        tx.o            \
+        rx.o
+
+i2400m-$(CONFIG_DEBUG_FS) += debugfs.o
+
+i2400m-usb-y :=                 \
+        usb-fw.o                \
+        usb-notif.o             \
+        usb-tx.o                \
+        usb-rx.o                \
+        usb.o
+
+
+i2400m-sdio-y :=                \
+        sdio.o                  \
+        sdio-tx.o               \
+        sdio-fw.o               \
+        sdio-rx.o
diff --git a/drivers/net/wimax/i2400m/control.c b/drivers/net/wimax/i2400m/control.c
new file mode 100644
index 000000000000..d3d37fed6893
--- /dev/null
+++ b/drivers/net/wimax/i2400m/control.c
@@ -0,0 +1,1291 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Miscellaneous control functions for managing the device
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ * This is a collection of functions used to control the device (plus
+ * a few helpers).
+ *
+ * There are utilities for handling TLV buffers, hooks on the device's
+ * reports to act on device changes of state [i2400m_report_hook()],
+ * on acks to commands [i2400m_msg_ack_hook()], a helper for sending
+ * commands to the device and blocking until a reply arrives
+ * [i2400m_msg_to_dev()], a few high level commands for manipulating
+ * the device state, powersving mode and configuration plus the
+ * routines to setup the device once communication is stablished with
+ * it [i2400m_dev_initialize()].
+ *
+ * ROADMAP
+ *
+ * i2400m_dev_initalize()       Called by i2400m_dev_start()
+ *   i2400m_set_init_config()
+ *   i2400m_firmware_check()
+ *   i2400m_cmd_get_state()
+ * i2400m_dev_shutdown()        Called by i2400m_dev_stop()
+ *   i2400m->bus_reset()
+ *
+ * i2400m_{cmd,get,set}_*()
+ *   i2400m_msg_to_dev()
+ *   i2400m_msg_check_status()
+ *
+ * i2400m_report_hook()         Called on reception of an event
+ *   i2400m_report_state_hook()
+ *     i2400m_tlv_buffer_walk()
+ *     i2400m_tlv_match()
+ *     i2400m_report_tlv_system_state()
+ *     i2400m_report_tlv_rf_switches_status()
+ *     i2400m_report_tlv_media_status()
+ *   i2400m_cmd_enter_powersave()
+ *
+ * i2400m_msg_ack_hook()        Called on reception of a reply to a
+ *                              command, get or set
+ */
+
+#include <stdarg.h>
+#include "i2400m.h"
+#include <linux/kernel.h>
+#include <linux/wimax/i2400m.h>
+
+
+#define D_SUBMODULE control
+#include "debug-levels.h"
+
+
+/*
+ * Return if a TLV is of a give type and size
+ *
+ * @tlv_hdr: pointer to the TLV
+ * @tlv_type: type of the TLV we are looking for
+ * @tlv_size: expected size of the TLV we are looking for (if -1,
+ *            don't check the size). This includes the header
+ * Returns: 0 if the TLV matches
+ *          < 0 if it doesn't match at all
+ *          > 0 total TLV + payload size, if the type matches, but not
+ *              the size
+ */
+static
+ssize_t i2400m_tlv_match(const struct i2400m_tlv_hdr *tlv,
+                     enum i2400m_tlv tlv_type, ssize_t tlv_size)
+{
+        if (le16_to_cpu(tlv->type) != tlv_type) /* Not our type? skip */
+                return -1;
+        if (tlv_size != -1
+            && le16_to_cpu(tlv->length) + sizeof(*tlv) != tlv_size) {
+                size_t size = le16_to_cpu(tlv->length) + sizeof(*tlv);
+                printk(KERN_WARNING "W: tlv type 0x%x mismatched because of "
+                       "size (got %zu vs %zu expected)\n",
+                       tlv_type, size, tlv_size);
+                return size;
+        }
+        return 0;
+}
+
+
+/*
+ * Given a buffer of TLVs, iterate over them
+ *
+ * @i2400m: device instance
+ * @tlv_buf: pointer to the beginning of the TLV buffer
+ * @buf_size: buffer size in bytes
+ * @tlv_pos: seek position; this is assumed to be a pointer returned
+ *           by i2400m_tlv_buffer_walk() [and thus, validated]. The
+ *           TLV returned will be the one following this one.
+ *
+ * Usage:
+ *
+ * tlv_itr = NULL;
+ * while (tlv_itr = i2400m_tlv_buffer_walk(i2400m, buf, size, tlv_itr))  {
+ *         ...
+ *         // Do stuff with tlv_itr, DON'T MODIFY IT
+ *         ...
+ * }
+ */
+static
+const struct i2400m_tlv_hdr *i2400m_tlv_buffer_walk(
+        struct i2400m *i2400m,
+        const void *tlv_buf, size_t buf_size,
+        const struct i2400m_tlv_hdr *tlv_pos)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_tlv_hdr *tlv_top = tlv_buf + buf_size;
+        size_t offset, length, avail_size;
+        unsigned type;
+
+        if (tlv_pos == NULL)    /* Take the first one? */
+                tlv_pos = tlv_buf;
+        else                    /* Nope, the next one */
+                tlv_pos = (void *) tlv_pos
+                        + le16_to_cpu(tlv_pos->length) + sizeof(*tlv_pos);
+        if (tlv_pos == tlv_top) {       /* buffer done */
+                tlv_pos = NULL;
+                goto error_beyond_end;
+        }
+        if (tlv_pos > tlv_top) {
+                tlv_pos = NULL;
+                WARN_ON(1);
+                goto error_beyond_end;
+        }
+        offset = (void *) tlv_pos - (void *) tlv_buf;
+        avail_size = buf_size - offset;
+        if (avail_size < sizeof(*tlv_pos)) {
+                dev_err(dev, "HW BUG? tlv_buf %p [%zu bytes], tlv @%zu: "
+                        "short header\n", tlv_buf, buf_size, offset);
+                goto error_short_header;
+        }
+        type = le16_to_cpu(tlv_pos->type);
+        length = le16_to_cpu(tlv_pos->length);
+        if (avail_size < sizeof(*tlv_pos) + length) {
+                dev_err(dev, "HW BUG? tlv_buf %p [%zu bytes], "
+                        "tlv type 0x%04x @%zu: "
+                        "short data (%zu bytes vs %zu needed)\n",
+                        tlv_buf, buf_size, type, offset, avail_size,
+                        sizeof(*tlv_pos) + length);
+                goto error_short_header;
+        }
+error_short_header:
+error_beyond_end:
+        return tlv_pos;
+}
+
+
+/*
+ * Find a TLV in a buffer of sequential TLVs
+ *
+ * @i2400m: device descriptor
+ * @tlv_hdr: pointer to the first TLV in the sequence
+ * @size: size of the buffer in bytes; all TLVs are assumed to fit
+ *        fully in the buffer (otherwise we'll complain).
+ * @tlv_type: type of the TLV we are looking for
+ * @tlv_size: expected size of the TLV we are looking for (if -1,
+ *            don't check the size). This includes the header
+ *
+ * Returns: NULL if the TLV is not found, otherwise a pointer to
+ *          it. If the sizes don't match, an error is printed and NULL
+ *          returned.
+ */
+static
+const struct i2400m_tlv_hdr *i2400m_tlv_find(
+        struct i2400m *i2400m,
+        const struct i2400m_tlv_hdr *tlv_hdr, size_t size,
+        enum i2400m_tlv tlv_type, ssize_t tlv_size)
+{
+        ssize_t match;
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_tlv_hdr *tlv = NULL;
+        while ((tlv = i2400m_tlv_buffer_walk(i2400m, tlv_hdr, size, tlv))) {
+                match = i2400m_tlv_match(tlv, tlv_type, tlv_size);
+                if (match == 0)         /* found it :) */
+                        break;
+                if (match > 0)
+                        dev_warn(dev, "TLV type 0x%04x found with size "
+                                 "mismatch (%zu vs %zu needed)\n",
+                                 tlv_type, match, tlv_size);
+        }
+        return tlv;
+}
+
+
+static const struct
+{
+        char *msg;
+        int errno;
+} ms_to_errno[I2400M_MS_MAX] = {
+        [I2400M_MS_DONE_OK] = { "", 0 },
+        [I2400M_MS_DONE_IN_PROGRESS] = { "", 0 },
+        [I2400M_MS_INVALID_OP] = { "invalid opcode", -ENOSYS },
+        [I2400M_MS_BAD_STATE] = { "invalid state", -EILSEQ },
+        [I2400M_MS_ILLEGAL_VALUE] = { "illegal value", -EINVAL },
+        [I2400M_MS_MISSING_PARAMS] = { "missing parameters", -ENOMSG },
+        [I2400M_MS_VERSION_ERROR] = { "bad version", -EIO },
+        [I2400M_MS_ACCESSIBILITY_ERROR] = { "accesibility error", -EIO },
+        [I2400M_MS_BUSY] = { "busy", -EBUSY },
+        [I2400M_MS_CORRUPTED_TLV] = { "corrupted TLV", -EILSEQ },
+        [I2400M_MS_UNINITIALIZED] = { "not unitialized", -EILSEQ },
+        [I2400M_MS_UNKNOWN_ERROR] = { "unknown error", -EIO },
+        [I2400M_MS_PRODUCTION_ERROR] = { "production error", -EIO },
+        [I2400M_MS_NO_RF] = { "no RF", -EIO },
+        [I2400M_MS_NOT_READY_FOR_POWERSAVE] =
+                { "not ready for powersave", -EACCES },
+        [I2400M_MS_THERMAL_CRITICAL] = { "thermal critical", -EL3HLT },
+};
+
+
+/*
+ * i2400m_msg_check_status - translate a message's status code
+ *
+ * @i2400m: device descriptor
+ * @l3l4_hdr: message header
+ * @strbuf: buffer to place a formatted error message (unless NULL).
+ * @strbuf_size: max amount of available space; larger messages will
+ * be truncated.
+ *
+ * Returns: errno code corresponding to the status code in @l3l4_hdr
+ *          and a message in @strbuf describing the error.
+ */
+int i2400m_msg_check_status(const struct i2400m_l3l4_hdr *l3l4_hdr,
+                            char *strbuf, size_t strbuf_size)
+{
+        int result;
+        enum i2400m_ms status = le16_to_cpu(l3l4_hdr->status);
+        const char *str;
+
+        if (status == 0)
+                return 0;
+        if (status > ARRAY_SIZE(ms_to_errno)) {
+                str = "unknown status code";
+                result = -EBADR;
+        } else {
+                str = ms_to_errno[status].msg;
+                result = ms_to_errno[status].errno;
+        }
+        if (strbuf)
+                snprintf(strbuf, strbuf_size, "%s (%d)", str, status);
+        return result;
+}
+
+
+/*
+ * Act on a TLV System State reported by the device
+ *
+ * @i2400m: device descriptor
+ * @ss: validated System State TLV
+ */
+static
+void i2400m_report_tlv_system_state(struct i2400m *i2400m,
+                                    const struct i2400m_tlv_system_state *ss)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        enum i2400m_system_state i2400m_state = le32_to_cpu(ss->state);
+
+        d_fnstart(3, dev, "(i2400m %p ss %p [%u])\n", i2400m, ss, i2400m_state);
+
+        if (unlikely(i2400m->ready == 0))       /* act if up */
+                goto out;
+        if (i2400m->state != i2400m_state) {
+                i2400m->state = i2400m_state;
+                wake_up_all(&i2400m->state_wq);
+        }
+        switch (i2400m_state) {
+        case I2400M_SS_UNINITIALIZED:
+        case I2400M_SS_INIT:
+        case I2400M_SS_CONFIG:
+        case I2400M_SS_PRODUCTION:
+                wimax_state_change(wimax_dev, WIMAX_ST_UNINITIALIZED);
+                break;
+
+        case I2400M_SS_RF_OFF:
+        case I2400M_SS_RF_SHUTDOWN:
+                wimax_state_change(wimax_dev, WIMAX_ST_RADIO_OFF);
+                break;
+
+        case I2400M_SS_READY:
+        case I2400M_SS_STANDBY:
+        case I2400M_SS_SLEEPACTIVE:
+                wimax_state_change(wimax_dev, WIMAX_ST_READY);
+                break;
+
+        case I2400M_SS_CONNECTING:
+        case I2400M_SS_WIMAX_CONNECTED:
+                wimax_state_change(wimax_dev, WIMAX_ST_READY);
+                break;
+
+        case I2400M_SS_SCAN:
+        case I2400M_SS_OUT_OF_ZONE:
+                wimax_state_change(wimax_dev, WIMAX_ST_SCANNING);
+                break;
+
+        case I2400M_SS_IDLE:
+                d_printf(1, dev, "entering BS-negotiated idle mode\n");
+        case I2400M_SS_DISCONNECTING:
+        case I2400M_SS_DATA_PATH_CONNECTED:
+                wimax_state_change(wimax_dev, WIMAX_ST_CONNECTED);
+                break;
+
+        default:
+                /* Huh? just in case, shut it down */
+                dev_err(dev, "HW BUG? unknown state %u: shutting down\n",
+                        i2400m_state);
+                i2400m->bus_reset(i2400m, I2400M_RT_WARM);
+                break;
+        };
+out:
+        d_fnend(3, dev, "(i2400m %p ss %p [%u]) = void\n",
+                i2400m, ss, i2400m_state);
+}
+
+
+/*
+ * Parse and act on a TLV Media Status sent by the device
+ *
+ * @i2400m: device descriptor
+ * @ms: validated Media Status TLV
+ *
+ * This will set the carrier up on down based on the device's link
+ * report. This is done asides of what the WiMAX stack does based on
+ * the device's state as sometimes we need to do a link-renew (the BS
+ * wants us to renew a DHCP lease, for example).
+ *
+ * In fact, doc says that everytime we get a link-up, we should do a
+ * DHCP negotiation...
+ */
+static
+void i2400m_report_tlv_media_status(struct i2400m *i2400m,
+                                    const struct i2400m_tlv_media_status *ms)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        struct net_device *net_dev = wimax_dev->net_dev;
+        enum i2400m_media_status status = le32_to_cpu(ms->media_status);
+
+        d_fnstart(3, dev, "(i2400m %p ms %p [%u])\n", i2400m, ms, status);
+
+        if (unlikely(i2400m->ready == 0))       /* act if up */
+                goto out;
+        switch (status) {
+        case I2400M_MEDIA_STATUS_LINK_UP:
+                netif_carrier_on(net_dev);
+                break;
+        case I2400M_MEDIA_STATUS_LINK_DOWN:
+                netif_carrier_off(net_dev);
+                break;
+        /*
+         * This is the network telling us we need to retrain the DHCP
+         * lease -- so far, we are trusting the WiMAX Network Service
+         * in user space to pick this up and poke the DHCP client.
+         */
+        case I2400M_MEDIA_STATUS_LINK_RENEW:
+                netif_carrier_on(net_dev);
+                break;
+        default:
+                dev_err(dev, "HW BUG? unknown media status %u\n",
+                        status);
+        };
+out:
+        d_fnend(3, dev, "(i2400m %p ms %p [%u]) = void\n",
+                i2400m, ms, status);
+}
+
+
+/*
+ * Parse a 'state report' and extract carrier on/off information
+ *
+ * @i2400m: device descriptor
+ * @l3l4_hdr: pointer to message; it has been already validated for
+ *            consistent size.
+ * @size: size of the message (header + payload). The header length
+ *        declaration is assumed to be congruent with @size (as in
+ *        sizeof(*l3l4_hdr) + l3l4_hdr->length == size)
+ *
+ * Extract from the report state the system state TLV and infer from
+ * there if we have a carrier or not. Update our local state and tell
+ * netdev.
+ *
+ * When setting the carrier, it's fine to set OFF twice (for example),
+ * as netif_carrier_off() will not generate two OFF events (just on
+ * the transitions).
+ */
+static
+void i2400m_report_state_hook(struct i2400m *i2400m,
+                              const struct i2400m_l3l4_hdr *l3l4_hdr,
+                              size_t size, const char *tag)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_tlv_hdr *tlv;
+        const struct i2400m_tlv_system_state *ss;
+        const struct i2400m_tlv_rf_switches_status *rfss;
+        const struct i2400m_tlv_media_status *ms;
+        size_t tlv_size = le16_to_cpu(l3l4_hdr->length);
+
+        d_fnstart(4, dev, "(i2400m %p, l3l4_hdr %p, size %zu, %s)\n",
+                  i2400m, l3l4_hdr, size, tag);
+        tlv = NULL;
+
+        while ((tlv = i2400m_tlv_buffer_walk(i2400m, &l3l4_hdr->pl,
+                                             tlv_size, tlv))) {
+                if (0 == i2400m_tlv_match(tlv, I2400M_TLV_SYSTEM_STATE,
+                                          sizeof(*ss))) {
+                        ss = container_of(tlv, typeof(*ss), hdr);
+                        d_printf(2, dev, "%s: system state TLV "
+                                 "found (0x%04x), state 0x%08x\n",
+                                 tag, I2400M_TLV_SYSTEM_STATE,
+                                 le32_to_cpu(ss->state));
+                        i2400m_report_tlv_system_state(i2400m, ss);
+                }
+                if (0 == i2400m_tlv_match(tlv, I2400M_TLV_RF_STATUS,
+                                          sizeof(*rfss))) {
+                        rfss = container_of(tlv, typeof(*rfss), hdr);
+                        d_printf(2, dev, "%s: RF status TLV "
+                                 "found (0x%04x), sw 0x%02x hw 0x%02x\n",
+                                 tag, I2400M_TLV_RF_STATUS,
+                                 le32_to_cpu(rfss->sw_rf_switch),
+                                 le32_to_cpu(rfss->hw_rf_switch));
+                        i2400m_report_tlv_rf_switches_status(i2400m, rfss);
+                }
+                if (0 == i2400m_tlv_match(tlv, I2400M_TLV_MEDIA_STATUS,
+                                          sizeof(*ms))) {
+                        ms = container_of(tlv, typeof(*ms), hdr);
+                        d_printf(2, dev, "%s: Media Status TLV: %u\n",
+                                 tag, le32_to_cpu(ms->media_status));
+                        i2400m_report_tlv_media_status(i2400m, ms);
+                }
+        }
+        d_fnend(4, dev, "(i2400m %p, l3l4_hdr %p, size %zu, %s) = void\n",
+                i2400m, l3l4_hdr, size, tag);
+}
+
+
+/*
+ * i2400m_report_hook - (maybe) act on a report
+ *
+ * @i2400m: device descriptor
+ * @l3l4_hdr: pointer to message; it has been already validated for
+ *            consistent size.
+ * @size: size of the message (header + payload). The header length
+ *        declaration is assumed to be congruent with @size (as in
+ *        sizeof(*l3l4_hdr) + l3l4_hdr->length == size)
+ *
+ * Extract information we might need (like carrien on/off) from a
+ * device report.
+ */
+void i2400m_report_hook(struct i2400m *i2400m,
+                        const struct i2400m_l3l4_hdr *l3l4_hdr, size_t size)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        unsigned msg_type;
+
+        d_fnstart(3, dev, "(i2400m %p l3l4_hdr %p size %zu)\n",
+                  i2400m, l3l4_hdr, size);
+        /* Chew on the message, we might need some information from
+         * here */
+        msg_type = le16_to_cpu(l3l4_hdr->type);
+        switch (msg_type) {
+        case I2400M_MT_REPORT_STATE:    /* carrier detection... */
+                i2400m_report_state_hook(i2400m,
+                                         l3l4_hdr, size, "REPORT STATE");
+                break;
+        /* If the device is ready for power save, then ask it to do
+         * it. */
+        case I2400M_MT_REPORT_POWERSAVE_READY:  /* zzzzz */
+                if (l3l4_hdr->status == cpu_to_le16(I2400M_MS_DONE_OK)) {
+                        d_printf(1, dev, "ready for powersave, requesting\n");
+                        i2400m_cmd_enter_powersave(i2400m);
+                }
+                break;
+        };
+        d_fnend(3, dev, "(i2400m %p l3l4_hdr %p size %zu) = void\n",
+                i2400m, l3l4_hdr, size);
+}
+
+
+/*
+ * i2400m_msg_ack_hook - process cmd/set/get ack for internal status
+ *
+ * @i2400m: device descriptor
+ * @l3l4_hdr: pointer to message; it has been already validated for
+ *            consistent size.
+ * @size: size of the message
+ *
+ * Extract information we might need from acks to commands and act on
+ * it. This is akin to i2400m_report_hook(). Note most of this
+ * processing should be done in the function that calls the
+ * command. This is here for some cases where it can't happen...
+ */
+void i2400m_msg_ack_hook(struct i2400m *i2400m,
+                         const struct i2400m_l3l4_hdr *l3l4_hdr, size_t size)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        unsigned ack_type, ack_status;
+        char strerr[32];
+
+        /* Chew on the message, we might need some information from
+         * here */
+        ack_type = le16_to_cpu(l3l4_hdr->type);
+        ack_status = le16_to_cpu(l3l4_hdr->status);
+        switch (ack_type) {
+        case I2400M_MT_CMD_ENTER_POWERSAVE:
+                /* This is just left here for the sake of example, as
+                 * the processing is done somewhere else. */
+                if (0) {
+                        result = i2400m_msg_check_status(
+                                l3l4_hdr, strerr, sizeof(strerr));
+                        if (result >= 0)
+                                d_printf(1, dev, "ready for power save: %zd\n",
+                                         size);
+                }
+                break;
+        };
+        return;
+}
+
+
+/*
+ * i2400m_msg_size_check() - verify message size and header are congruent
+ *
+ * It is ok if the total message size is larger than the expected
+ * size, as there can be padding.
+ */
+int i2400m_msg_size_check(struct i2400m *i2400m,
+                          const struct i2400m_l3l4_hdr *l3l4_hdr,
+                          size_t msg_size)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        size_t expected_size;
+        d_fnstart(4, dev, "(i2400m %p l3l4_hdr %p msg_size %zu)\n",
+                  i2400m, l3l4_hdr, msg_size);
+        if (msg_size < sizeof(*l3l4_hdr)) {
+                dev_err(dev, "bad size for message header "
+                        "(expected at least %zu, got %zu)\n",
+                        (size_t) sizeof(*l3l4_hdr), msg_size);
+                result = -EIO;
+                goto error_hdr_size;
+        }
+        expected_size = le16_to_cpu(l3l4_hdr->length) + sizeof(*l3l4_hdr);
+        if (msg_size < expected_size) {
+                dev_err(dev, "bad size for message code 0x%04x (expected %zu, "
+                        "got %zu)\n", le16_to_cpu(l3l4_hdr->type),
+                        expected_size, msg_size);
+                result = -EIO;
+        } else
+                result = 0;
+error_hdr_size:
+        d_fnend(4, dev,
+                "(i2400m %p l3l4_hdr %p msg_size %zu) = %d\n",
+                i2400m, l3l4_hdr, msg_size, result);
+        return result;
+}
+
+
+
+/*
+ * Cancel a wait for a command ACK
+ *
+ * @i2400m: device descriptor
+ * @code: [negative] errno code to cancel with (don't use
+ *     -EINPROGRESS)
+ *
+ * If there is an ack already filled out, free it.
+ */
+void i2400m_msg_to_dev_cancel_wait(struct i2400m *i2400m, int code)
+{
+        struct sk_buff *ack_skb;
+        unsigned long flags;
+
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        ack_skb = i2400m->ack_skb;
+        if (ack_skb && !IS_ERR(ack_skb))
+                kfree(ack_skb);
+        i2400m->ack_skb = ERR_PTR(code);
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+}
+
+
+/**
+ * i2400m_msg_to_dev - Send a control message to the device and get a response
+ *
+ * @i2400m: device descriptor
+ *
+ * @msg_skb: an skb  *
+ *
+ * @buf: pointer to the buffer containing the message to be sent; it
+ *           has to start with a &struct i2400M_l3l4_hdr and then
+ *           followed by the payload. Once this function returns, the
+ *           buffer can be reused.
+ *
+ * @buf_len: buffer size
+ *
+ * Returns:
+ *
+ * Pointer to skb containing the ack message. You need to check the
+ * pointer with IS_ERR(), as it might be an error code. Error codes
+ * could happen because:
+ *
+ *  - the message wasn't formatted correctly
+ *  - couldn't send the message
+ *  - failed waiting for a response
+ *  - the ack message wasn't formatted correctly
+ *
+ * The returned skb has been allocated with wimax_msg_to_user_alloc(),
+ * it contains the reponse in a netlink attribute and is ready to be
+ * passed up to user space with wimax_msg_to_user_send(). To access
+ * the payload and its length, use wimax_msg_{data,len}() on the skb.
+ *
+ * The skb has to be freed with kfree_skb() once done.
+ *
+ * Description:
+ *
+ * This function delivers a message/command to the device and waits
+ * for an ack to be received. The format is described in
+ * linux/wimax/i2400m.h. In summary, a command/get/set is followed by an
+ * ack.
+ *
+ * This function will not check the ack status, that's left up to the
+ * caller.  Once done with the ack skb, it has to be kfree_skb()ed.
+ *
+ * The i2400m handles only one message at the same time, thus we need
+ * the mutex to exclude other players.
+ *
+ * We write the message and then wait for an answer to come back. The
+ * RX path intercepts control messages and handles them in
+ * i2400m_rx_ctl(). Reports (notifications) are (maybe) processed
+ * locally and then forwarded (as needed) to user space on the WiMAX
+ * stack message pipe. Acks are saved and passed back to us through an
+ * skb in i2400m->ack_skb which is ready to be given to generic
+ * netlink if need be.
+ */
+struct sk_buff *i2400m_msg_to_dev(struct i2400m *i2400m,
+                                  const void *buf, size_t buf_len)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_l3l4_hdr *msg_l3l4_hdr;
+        struct sk_buff *ack_skb;
+        const struct i2400m_l3l4_hdr *ack_l3l4_hdr;
+        size_t ack_len;
+        int ack_timeout;
+        unsigned msg_type;
+        unsigned long flags;
+
+        d_fnstart(3, dev, "(i2400m %p buf %p len %zu)\n",
+                  i2400m, buf, buf_len);
+
+        if (i2400m->boot_mode)
+                return ERR_PTR(-ENODEV);
+
+        msg_l3l4_hdr = buf;
+        /* Check msg & payload consistency */
+        result = i2400m_msg_size_check(i2400m, msg_l3l4_hdr, buf_len);
+        if (result < 0)
+                goto error_bad_msg;
+        msg_type = le16_to_cpu(msg_l3l4_hdr->type);
+        d_printf(1, dev, "CMD/GET/SET 0x%04x %zu bytes\n",
+                 msg_type, buf_len);
+        d_dump(2, dev, buf, buf_len);
+
+        /* Setup the completion, ack_skb ("we are waiting") and send
+         * the message to the device */
+        mutex_lock(&i2400m->msg_mutex);
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        i2400m->ack_skb = ERR_PTR(-EINPROGRESS);
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        init_completion(&i2400m->msg_completion);
+        result = i2400m_tx(i2400m, buf, buf_len, I2400M_PT_CTRL);
+        if (result < 0) {
+                dev_err(dev, "can't send message 0x%04x: %d\n",
+                        le16_to_cpu(msg_l3l4_hdr->type), result);
+                goto error_tx;
+        }
+
+        /* Some commands take longer to execute because of crypto ops,
+         * so we give them some more leeway on timeout */
+        switch (msg_type) {
+        case I2400M_MT_GET_TLS_OPERATION_RESULT:
+        case I2400M_MT_CMD_SEND_EAP_RESPONSE:
+                ack_timeout = 5 * HZ;
+                break;
+        default:
+                ack_timeout = HZ;
+        };
+
+        /* The RX path in rx.c will put any response for this message
+         * in i2400m->ack_skb and wake us up. If we cancel the wait,
+         * we need to change the value of i2400m->ack_skb to something
+         * not -EINPROGRESS so RX knows there is no one waiting. */
+        result = wait_for_completion_interruptible_timeout(
+                &i2400m->msg_completion, ack_timeout);
+        if (result == 0) {
+                dev_err(dev, "timeout waiting for reply to message 0x%04x\n",
+                        msg_type);
+                result = -ETIMEDOUT;
+                i2400m_msg_to_dev_cancel_wait(i2400m, result);
+                goto error_wait_for_completion;
+        } else if (result < 0) {
+                dev_err(dev, "error waiting for reply to message 0x%04x: %d\n",
+                        msg_type, result);
+                i2400m_msg_to_dev_cancel_wait(i2400m, result);
+                goto error_wait_for_completion;
+        }
+
+        /* Pull out the ack data from i2400m->ack_skb -- see if it is
+         * an error and act accordingly */
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        ack_skb = i2400m->ack_skb;
+        if (IS_ERR(ack_skb))
+                result = PTR_ERR(ack_skb);
+        else
+                result = 0;
+        i2400m->ack_skb = NULL;
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        if (result < 0)
+                goto error_ack_status;
+        ack_l3l4_hdr = wimax_msg_data_len(ack_skb, &ack_len);
+
+        /* Check the ack and deliver it if it is ok */
+        result = i2400m_msg_size_check(i2400m, ack_l3l4_hdr, ack_len);
+        if (result < 0) {
+                dev_err(dev, "HW BUG? reply to message 0x%04x: %d\n",
+                        msg_type, result);
+                goto error_bad_ack_len;
+        }
+        if (msg_type != le16_to_cpu(ack_l3l4_hdr->type)) {
+                dev_err(dev, "HW BUG? bad reply 0x%04x to message 0x%04x\n",
+                        le16_to_cpu(ack_l3l4_hdr->type), msg_type);
+                result = -EIO;
+                goto error_bad_ack_type;
+        }
+        i2400m_msg_ack_hook(i2400m, ack_l3l4_hdr, ack_len);
+        mutex_unlock(&i2400m->msg_mutex);
+        d_fnend(3, dev, "(i2400m %p buf %p len %zu) = %p\n",
+                i2400m, buf, buf_len, ack_skb);
+        return ack_skb;
+
+error_bad_ack_type:
+error_bad_ack_len:
+        kfree_skb(ack_skb);
+error_ack_status:
+error_wait_for_completion:
+error_tx:
+        mutex_unlock(&i2400m->msg_mutex);
+error_bad_msg:
+        d_fnend(3, dev, "(i2400m %p buf %p len %zu) = %d\n",
+                i2400m, buf, buf_len, result);
+        return ERR_PTR(result);
+}
+
+
+/*
+ * Definitions for the Enter Power Save command
+ *
+ * The Enter Power Save command requests the device to go into power
+ * saving mode. The device will ack or nak the command depending on it
+ * being ready for it. If it acks, we tell the USB subsystem to
+ *
+ * As well, the device might request to go into power saving mode by
+ * sending a report (REPORT_POWERSAVE_READY), in which case, we issue
+ * this command. The hookups in the RX coder allow
+ */
+enum {
+        I2400M_WAKEUP_ENABLED  = 0x01,
+        I2400M_WAKEUP_DISABLED = 0x02,
+        I2400M_TLV_TYPE_WAKEUP_MODE = 144,
+};
+
+struct i2400m_cmd_enter_power_save {
+        struct i2400m_l3l4_hdr hdr;
+        struct i2400m_tlv_hdr tlv;
+        __le32 val;
+} __attribute__((packed));
+
+
+/*
+ * Request entering power save
+ *
+ * This command is (mainly) executed when the device indicates that it
+ * is ready to go into powersave mode via a REPORT_POWERSAVE_READY.
+ */
+int i2400m_cmd_enter_powersave(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_cmd_enter_power_save *cmd;
+        char strerr[32];
+
+        result = -ENOMEM;
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->hdr.type = cpu_to_le16(I2400M_MT_CMD_ENTER_POWERSAVE);
+        cmd->hdr.length = cpu_to_le16(sizeof(*cmd) - sizeof(cmd->hdr));
+        cmd->hdr.version = cpu_to_le16(I2400M_L3L4_VERSION);
+        cmd->tlv.type = cpu_to_le16(I2400M_TLV_TYPE_WAKEUP_MODE);
+        cmd->tlv.length = cpu_to_le16(sizeof(cmd->val));
+        cmd->val = cpu_to_le32(I2400M_WAKEUP_ENABLED);
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        result = PTR_ERR(ack_skb);
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'Enter power save' command: %d\n",
+                        result);
+                goto error_msg_to_dev;
+        }
+        result = i2400m_msg_check_status(wimax_msg_data(ack_skb),
+                                         strerr, sizeof(strerr));
+        if (result == -EACCES)
+                d_printf(1, dev, "Cannot enter power save mode\n");
+        else if (result < 0)
+                dev_err(dev, "'Enter power save' (0x%04x) command failed: "
+                        "%d - %s\n", I2400M_MT_CMD_ENTER_POWERSAVE,
+                        result, strerr);
+        else
+                d_printf(1, dev, "device ready to power save\n");
+        kfree_skb(ack_skb);
+error_msg_to_dev:
+        kfree(cmd);
+error_alloc:
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_cmd_enter_powersave);
+
+
+/*
+ * Definitions for getting device information
+ */
+enum {
+        I2400M_TLV_DETAILED_DEVICE_INFO = 140
+};
+
+/**
+ * i2400m_get_device_info - Query the device for detailed device information
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: an skb whose skb->data points to a 'struct
+ *    i2400m_tlv_detailed_device_info'. When done, kfree_skb() it. The
+ *    skb is *guaranteed* to contain the whole TLV data structure.
+ *
+ *    On error, IS_ERR(skb) is true and ERR_PTR(skb) is the error
+ *    code.
+ */
+struct sk_buff *i2400m_get_device_info(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_l3l4_hdr *cmd;
+        const struct i2400m_l3l4_hdr *ack;
+        size_t ack_len;
+        const struct i2400m_tlv_hdr *tlv;
+        const struct i2400m_tlv_detailed_device_info *ddi;
+        char strerr[32];
+
+        ack_skb = ERR_PTR(-ENOMEM);
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->type = cpu_to_le16(I2400M_MT_GET_DEVICE_INFO);
+        cmd->length = 0;
+        cmd->version = cpu_to_le16(I2400M_L3L4_VERSION);
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'get device info' command: %ld\n",
+                        PTR_ERR(ack_skb));
+                goto error_msg_to_dev;
+        }
+        ack = wimax_msg_data_len(ack_skb, &ack_len);
+        result = i2400m_msg_check_status(ack, strerr, sizeof(strerr));
+        if (result < 0) {
+                dev_err(dev, "'get device info' (0x%04x) command failed: "
+                        "%d - %s\n", I2400M_MT_GET_DEVICE_INFO, result,
+                        strerr);
+                goto error_cmd_failed;
+        }
+        tlv = i2400m_tlv_find(i2400m, ack->pl, ack_len - sizeof(*ack),
+                              I2400M_TLV_DETAILED_DEVICE_INFO, sizeof(*ddi));
+        if (tlv == NULL) {
+                dev_err(dev, "GET DEVICE INFO: "
+                        "detailed device info TLV not found (0x%04x)\n",
+                        I2400M_TLV_DETAILED_DEVICE_INFO);
+                result = -EIO;
+                goto error_no_tlv;
+        }
+        skb_pull(ack_skb, (void *) tlv - (void *) ack_skb->data);
+error_msg_to_dev:
+        kfree(cmd);
+error_alloc:
+        return ack_skb;
+
+error_no_tlv:
+error_cmd_failed:
+        kfree_skb(ack_skb);
+        kfree(cmd);
+        return ERR_PTR(result);
+}
+
+
+/* Firmware interface versions we support */
+enum {
+        I2400M_HDIv_MAJOR = 9,
+        I2400M_HDIv_MAJOR_2 = 8,
+        I2400M_HDIv_MINOR = 1,
+};
+
+
+/**
+ * i2400m_firmware_check - check firmware versions are compatible with
+ * the driver
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: 0 if ok, < 0 errno code an error and a message in the
+ *    kernel log.
+ *
+ * Long function, but quite simple; first chunk launches the command
+ * and double checks the reply for the right TLV. Then we process the
+ * TLV (where the meat is).
+ */
+int i2400m_firmware_check(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_l3l4_hdr *cmd;
+        const struct i2400m_l3l4_hdr *ack;
+        size_t ack_len;
+        const struct i2400m_tlv_hdr *tlv;
+        const struct i2400m_tlv_l4_message_versions *l4mv;
+        char strerr[32];
+        unsigned major, minor, branch;
+
+        result = -ENOMEM;
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->type = cpu_to_le16(I2400M_MT_GET_LM_VERSION);
+        cmd->length = 0;
+        cmd->version = cpu_to_le16(I2400M_L3L4_VERSION);
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        if (IS_ERR(ack_skb)) {
+                result = PTR_ERR(ack_skb);
+                dev_err(dev, "Failed to issue 'get lm version' command: %-d\n",
+                        result);
+                goto error_msg_to_dev;
+        }
+        ack = wimax_msg_data_len(ack_skb, &ack_len);
+        result = i2400m_msg_check_status(ack, strerr, sizeof(strerr));
+        if (result < 0) {
+                dev_err(dev, "'get lm version' (0x%04x) command failed: "
+                        "%d - %s\n", I2400M_MT_GET_LM_VERSION, result,
+                        strerr);
+                goto error_cmd_failed;
+        }
+        tlv = i2400m_tlv_find(i2400m, ack->pl, ack_len - sizeof(*ack),
+                              I2400M_TLV_L4_MESSAGE_VERSIONS, sizeof(*l4mv));
+        if (tlv == NULL) {
+                dev_err(dev, "get lm version: TLV not found (0x%04x)\n",
+                        I2400M_TLV_L4_MESSAGE_VERSIONS);
+                result = -EIO;
+                goto error_no_tlv;
+        }
+        l4mv = container_of(tlv, typeof(*l4mv), hdr);
+        major = le16_to_cpu(l4mv->major);
+        minor = le16_to_cpu(l4mv->minor);
+        branch = le16_to_cpu(l4mv->branch);
+        result = -EINVAL;
+        if (major != I2400M_HDIv_MAJOR
+            && major != I2400M_HDIv_MAJOR_2) {
+                dev_err(dev, "unsupported major fw interface version "
+                        "%u.%u.%u\n", major, minor, branch);
+                goto error_bad_major;
+        }
+        if (major == I2400M_HDIv_MAJOR_2)
+                dev_err(dev, "deprecated major fw interface version "
+                        "%u.%u.%u\n", major, minor, branch);
+        result = 0;
+        if (minor != I2400M_HDIv_MINOR)
+                dev_warn(dev, "untested minor fw firmware version %u.%u.%u\n",
+                         major, minor, branch);
+error_bad_major:
+        dev_info(dev, "firmware interface version %u.%u.%u\n",
+                 major, minor, branch);
+error_no_tlv:
+error_cmd_failed:
+        kfree_skb(ack_skb);
+error_msg_to_dev:
+        kfree(cmd);
+error_alloc:
+        return result;
+}
+
+
+/*
+ * Send an DoExitIdle command to the device to ask it to go out of
+ * basestation-idle mode.
+ *
+ * @i2400m: device descriptor
+ *
+ * This starts a renegotiation with the basestation that might involve
+ * another crypto handshake with user space.
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ */
+int i2400m_cmd_exit_idle(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_l3l4_hdr *cmd;
+        char strerr[32];
+
+        result = -ENOMEM;
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->type = cpu_to_le16(I2400M_MT_CMD_EXIT_IDLE);
+        cmd->length = 0;
+        cmd->version = cpu_to_le16(I2400M_L3L4_VERSION);
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        result = PTR_ERR(ack_skb);
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'exit idle' command: %d\n",
+                        result);
+                goto error_msg_to_dev;
+        }
+        result = i2400m_msg_check_status(wimax_msg_data(ack_skb),
+                                         strerr, sizeof(strerr));
+        kfree_skb(ack_skb);
+error_msg_to_dev:
+        kfree(cmd);
+error_alloc:
+        return result;
+
+}
+
+
+/*
+ * Query the device for its state, update the WiMAX stack's idea of it
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * Executes a 'Get State' command and parses the returned
+ * TLVs.
+ *
+ * Because this is almost identical to a 'Report State', we use
+ * i2400m_report_state_hook() to parse the answer. This will set the
+ * carrier state, as well as the RF Kill switches state.
+ */
+int i2400m_cmd_get_state(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_l3l4_hdr *cmd;
+        const struct i2400m_l3l4_hdr *ack;
+        size_t ack_len;
+        char strerr[32];
+
+        result = -ENOMEM;
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->type = cpu_to_le16(I2400M_MT_GET_STATE);
+        cmd->length = 0;
+        cmd->version = cpu_to_le16(I2400M_L3L4_VERSION);
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'get state' command: %ld\n",
+                        PTR_ERR(ack_skb));
+                result = PTR_ERR(ack_skb);
+                goto error_msg_to_dev;
+        }
+        ack = wimax_msg_data_len(ack_skb, &ack_len);
+        result = i2400m_msg_check_status(ack, strerr, sizeof(strerr));
+        if (result < 0) {
+                dev_err(dev, "'get state' (0x%04x) command failed: "
+                        "%d - %s\n", I2400M_MT_GET_STATE, result, strerr);
+                goto error_cmd_failed;
+        }
+        i2400m_report_state_hook(i2400m, ack, ack_len - sizeof(*ack),
+                                 "GET STATE");
+        result = 0;
+        kfree_skb(ack_skb);
+error_cmd_failed:
+error_msg_to_dev:
+        kfree(cmd);
+error_alloc:
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_cmd_get_state);
+
+
+/**
+ * Set basic configuration settings
+ *
+ * @i2400m: device descriptor
+ * @args: array of pointers to the TLV headers to send for
+ *     configuration (each followed by its payload).
+ *     TLV headers and payloads must be properly initialized, with the
+ *     right endianess (LE).
+ * @arg_size: number of pointers in the @args array
+ */
+int i2400m_set_init_config(struct i2400m *i2400m,
+                           const struct i2400m_tlv_hdr **arg, size_t args)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct i2400m_l3l4_hdr *cmd;
+        char strerr[32];
+        unsigned argc, argsize, tlv_size;
+        const struct i2400m_tlv_hdr *tlv_hdr;
+        void *buf, *itr;
+
+        d_fnstart(3, dev, "(i2400m %p arg %p args %zu)\n", i2400m, arg, args);
+        result = 0;
+        if (args == 0)
+                goto none;
+        /* Compute the size of all the TLVs, so we can alloc a
+         * contiguous command block to copy them. */
+        argsize = 0;
+        for (argc = 0; argc < args; argc++) {
+                tlv_hdr = arg[argc];
+                argsize += sizeof(*tlv_hdr) + le16_to_cpu(tlv_hdr->length);
+        }
+        WARN_ON(argc >= 9);     /* As per hw spec */
+
+        /* Alloc the space for the command and TLVs*/
+        result = -ENOMEM;
+        buf = kzalloc(sizeof(*cmd) + argsize, GFP_KERNEL);
+        if (buf == NULL)
+                goto error_alloc;
+        cmd = buf;
+        cmd->type = cpu_to_le16(I2400M_MT_SET_INIT_CONFIG);
+        cmd->length = cpu_to_le16(argsize);
+        cmd->version = cpu_to_le16(I2400M_L3L4_VERSION);
+
+        /* Copy the TLVs */
+        itr = buf + sizeof(*cmd);
+        for (argc = 0; argc < args; argc++) {
+                tlv_hdr = arg[argc];
+                tlv_size = sizeof(*tlv_hdr) + le16_to_cpu(tlv_hdr->length);
+                memcpy(itr, tlv_hdr, tlv_size);
+                itr += tlv_size;
+        }
+
+        /* Send the message! */
+        ack_skb = i2400m_msg_to_dev(i2400m, buf, sizeof(*cmd) + argsize);
+        result = PTR_ERR(ack_skb);
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'init config' command: %d\n",
+                        result);
+
+                goto error_msg_to_dev;
+        }
+        result = i2400m_msg_check_status(wimax_msg_data(ack_skb),
+                                         strerr, sizeof(strerr));
+        if (result < 0)
+                dev_err(dev, "'init config' (0x%04x) command failed: %d - %s\n",
+                        I2400M_MT_SET_INIT_CONFIG, result, strerr);
+        kfree_skb(ack_skb);
+error_msg_to_dev:
+        kfree(buf);
+error_alloc:
+none:
+        d_fnend(3, dev, "(i2400m %p arg %p args %zu) = %d\n",
+                i2400m, arg, args, result);
+        return result;
+
+}
+EXPORT_SYMBOL_GPL(i2400m_set_init_config);
+
+
+/**
+ * i2400m_dev_initialize - Initialize the device once communications are ready
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * Configures the device to work the way we like it.
+ *
+ * At the point of this call, the device is registered with the WiMAX
+ * and netdev stacks, firmware is uploaded and we can talk to the
+ * device normally.
+ */
+int i2400m_dev_initialize(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_tlv_config_idle_parameters idle_params;
+        const struct i2400m_tlv_hdr *args[9];
+        unsigned argc = 0;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        /* Useless for now...might change */
+        if (i2400m_idle_mode_disabled) {
+                idle_params.hdr.type =
+                        cpu_to_le16(I2400M_TLV_CONFIG_IDLE_PARAMETERS);
+                idle_params.hdr.length = cpu_to_le16(
+                        sizeof(idle_params) - sizeof(idle_params.hdr));
+                idle_params.idle_timeout = 0;
+                idle_params.idle_paging_interval = 0;
+                args[argc++] = &idle_params.hdr;
+        }
+        result = i2400m_set_init_config(i2400m, args, argc);
+        if (result < 0)
+                goto error;
+        result = i2400m_firmware_check(i2400m); /* fw versions ok? */
+        if (result < 0)
+                goto error;
+        /*
+         * Update state: Here it just calls a get state; parsing the
+         * result (System State TLV and RF Status TLV [done in the rx
+         * path hooks]) will set the hardware and software RF-Kill
+         * status.
+         */
+        result = i2400m_cmd_get_state(i2400m);
+error:
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+}
+
+
+/**
+ * i2400m_dev_shutdown - Shutdown a running device
+ *
+ * @i2400m: device descriptor
+ *
+ * Gracefully stops the device, moving it to the lowest power
+ * consumption state possible.
+ */
+void i2400m_dev_shutdown(struct i2400m *i2400m)
+{
+        int result = -ENODEV;
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        result = i2400m->bus_reset(i2400m, I2400M_RT_WARM);
+        d_fnend(3, dev, "(i2400m %p) = void [%d]\n", i2400m, result);
+        return;
+}
diff --git a/drivers/net/wimax/i2400m/debug-levels.h b/drivers/net/wimax/i2400m/debug-levels.h
new file mode 100644
index 000000000000..3183baa16a52
--- /dev/null
+++ b/drivers/net/wimax/i2400m/debug-levels.h
@@ -0,0 +1,45 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Debug levels control file for the i2400m module
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __debug_levels__h__
+#define __debug_levels__h__
+
+/* Maximum compile and run time debug level for all submodules */
+#define D_MODULENAME i2400m
+#define D_MASTER CONFIG_WIMAX_I2400M_DEBUG_LEVEL
+
+#include <linux/wimax/debug.h>
+
+/* List of all the enabled modules */
+enum d_module {
+        D_SUBMODULE_DECLARE(control),
+        D_SUBMODULE_DECLARE(driver),
+        D_SUBMODULE_DECLARE(debugfs),
+        D_SUBMODULE_DECLARE(fw),
+        D_SUBMODULE_DECLARE(netdev),
+        D_SUBMODULE_DECLARE(rfkill),
+        D_SUBMODULE_DECLARE(rx),
+        D_SUBMODULE_DECLARE(tx),
+};
+
+
+#endif /* #ifndef __debug_levels__h__ */
diff --git a/drivers/net/wimax/i2400m/debugfs.c b/drivers/net/wimax/i2400m/debugfs.c
new file mode 100644
index 000000000000..626632985977
--- /dev/null
+++ b/drivers/net/wimax/i2400m/debugfs.c
@@ -0,0 +1,392 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Debugfs interfaces to manipulate driver and device information
+ *
+ *
+ * Copyright (C) 2007 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include "i2400m.h"
+
+
+#define D_SUBMODULE debugfs
+#include "debug-levels.h"
+
+static
+int debugfs_netdev_queue_stopped_get(void *data, u64 *val)
+{
+        struct i2400m *i2400m = data;
+        *val = netif_queue_stopped(i2400m->wimax_dev.net_dev);
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_netdev_queue_stopped,
+                        debugfs_netdev_queue_stopped_get,
+                        NULL, "%llu\n");
+
+
+static
+struct dentry *debugfs_create_netdev_queue_stopped(
+        const char *name, struct dentry *parent, struct i2400m *i2400m)
+{
+        return debugfs_create_file(name, 0400, parent, i2400m,
+                                   &fops_netdev_queue_stopped);
+}
+
+
+/*
+ * inode->i_private has the @data argument to debugfs_create_file()
+ */
+static
+int i2400m_stats_open(struct inode *inode, struct file *filp)
+{
+        filp->private_data = inode->i_private;
+        return 0;
+}
+
+/*
+ * We don't allow partial reads of this file, as then the reader would
+ * get weirdly confused data as it is updated.
+ *
+ * So or you read it all or nothing; if you try to read with an offset
+ * != 0, we consider you are done reading.
+ */
+static
+ssize_t i2400m_rx_stats_read(struct file *filp, char __user *buffer,
+                             size_t count, loff_t *ppos)
+{
+        struct i2400m *i2400m = filp->private_data;
+        char buf[128];
+        unsigned long flags;
+
+        if (*ppos != 0)
+                return 0;
+        if (count < sizeof(buf))
+                return -ENOSPC;
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        snprintf(buf, sizeof(buf), "%u %u %u %u %u %u %u\n",
+                 i2400m->rx_pl_num, i2400m->rx_pl_min,
+                 i2400m->rx_pl_max, i2400m->rx_num,
+                 i2400m->rx_size_acc,
+                 i2400m->rx_size_min, i2400m->rx_size_max);
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        return simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
+}
+
+
+/* Any write clears the stats */
+static
+ssize_t i2400m_rx_stats_write(struct file *filp, const char __user *buffer,
+                              size_t count, loff_t *ppos)
+{
+        struct i2400m *i2400m = filp->private_data;
+        unsigned long flags;
+
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        i2400m->rx_pl_num = 0;
+        i2400m->rx_pl_max = 0;
+        i2400m->rx_pl_min = UINT_MAX;
+        i2400m->rx_num = 0;
+        i2400m->rx_size_acc = 0;
+        i2400m->rx_size_min = UINT_MAX;
+        i2400m->rx_size_max = 0;
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        return count;
+}
+
+static
+const struct file_operations i2400m_rx_stats_fops = {
+        .owner =        THIS_MODULE,
+        .open =         i2400m_stats_open,
+        .read =         i2400m_rx_stats_read,
+        .write =        i2400m_rx_stats_write,
+};
+
+
+/* See i2400m_rx_stats_read() */
+static
+ssize_t i2400m_tx_stats_read(struct file *filp, char __user *buffer,
+                             size_t count, loff_t *ppos)
+{
+        struct i2400m *i2400m = filp->private_data;
+        char buf[128];
+        unsigned long flags;
+
+        if (*ppos != 0)
+                return 0;
+        if (count < sizeof(buf))
+                return -ENOSPC;
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+        snprintf(buf, sizeof(buf), "%u %u %u %u %u %u %u\n",
+                 i2400m->tx_pl_num, i2400m->tx_pl_min,
+                 i2400m->tx_pl_max, i2400m->tx_num,
+                 i2400m->tx_size_acc,
+                 i2400m->tx_size_min, i2400m->tx_size_max);
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        return simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
+}
+
+/* Any write clears the stats */
+static
+ssize_t i2400m_tx_stats_write(struct file *filp, const char __user *buffer,
+                              size_t count, loff_t *ppos)
+{
+        struct i2400m *i2400m = filp->private_data;
+        unsigned long flags;
+
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+        i2400m->tx_pl_num = 0;
+        i2400m->tx_pl_max = 0;
+        i2400m->tx_pl_min = UINT_MAX;
+        i2400m->tx_num = 0;
+        i2400m->tx_size_acc = 0;
+        i2400m->tx_size_min = UINT_MAX;
+        i2400m->tx_size_max = 0;
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        return count;
+}
+
+static
+const struct file_operations i2400m_tx_stats_fops = {
+        .owner =        THIS_MODULE,
+        .open =         i2400m_stats_open,
+        .read =         i2400m_tx_stats_read,
+        .write =        i2400m_tx_stats_write,
+};
+
+
+/* Write 1 to ask the device to go into suspend */
+static
+int debugfs_i2400m_suspend_set(void *data, u64 val)
+{
+        int result;
+        struct i2400m *i2400m = data;
+        result = i2400m_cmd_enter_powersave(i2400m);
+        if (result >= 0)
+                result = 0;
+        return result;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_i2400m_suspend,
+                        NULL, debugfs_i2400m_suspend_set,
+                        "%llu\n");
+
+static
+struct dentry *debugfs_create_i2400m_suspend(
+        const char *name, struct dentry *parent, struct i2400m *i2400m)
+{
+        return debugfs_create_file(name, 0200, parent, i2400m,
+                                   &fops_i2400m_suspend);
+}
+
+
+/*
+ * Reset the device
+ *
+ * Write 0 to ask the device to soft reset, 1 to cold reset, 2 to bus
+ * reset (as defined by enum i2400m_reset_type).
+ */
+static
+int debugfs_i2400m_reset_set(void *data, u64 val)
+{
+        int result;
+        struct i2400m *i2400m = data;
+        enum i2400m_reset_type rt = val;
+        switch(rt) {
+        case I2400M_RT_WARM:
+        case I2400M_RT_COLD:
+        case I2400M_RT_BUS:
+                result = i2400m->bus_reset(i2400m, rt);
+                if (result >= 0)
+                        result = 0;
+        default:
+                result = -EINVAL;
+        }
+        return result;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_i2400m_reset,
+                        NULL, debugfs_i2400m_reset_set,
+                        "%llu\n");
+
+static
+struct dentry *debugfs_create_i2400m_reset(
+        const char *name, struct dentry *parent, struct i2400m *i2400m)
+{
+        return debugfs_create_file(name, 0200, parent, i2400m,
+                                   &fops_i2400m_reset);
+}
+
+/*
+ * Debug levels control; see debug.h
+ */
+struct d_level D_LEVEL[] = {
+        D_SUBMODULE_DEFINE(control),
+        D_SUBMODULE_DEFINE(driver),
+        D_SUBMODULE_DEFINE(debugfs),
+        D_SUBMODULE_DEFINE(fw),
+        D_SUBMODULE_DEFINE(netdev),
+        D_SUBMODULE_DEFINE(rfkill),
+        D_SUBMODULE_DEFINE(rx),
+        D_SUBMODULE_DEFINE(tx),
+};
+size_t D_LEVEL_SIZE = ARRAY_SIZE(D_LEVEL);
+
+#define __debugfs_register(prefix, name, parent)                        \
+do {                                                                    \
+        result = d_level_register_debugfs(prefix, name, parent);        \
+        if (result < 0)                                                 \
+                goto error;                                             \
+} while (0)
+
+
+int i2400m_debugfs_add(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct dentry *dentry = i2400m->wimax_dev.debugfs_dentry;
+        struct dentry *fd;
+
+        dentry = debugfs_create_dir("i2400m", dentry);
+        result = PTR_ERR(dentry);
+        if (IS_ERR(dentry)) {
+                if (result == -ENODEV)
+                        result = 0;     /* No debugfs support */
+                goto error;
+        }
+        i2400m->debugfs_dentry = dentry;
+        __debugfs_register("dl_", control, dentry);
+        __debugfs_register("dl_", driver, dentry);
+        __debugfs_register("dl_", debugfs, dentry);
+        __debugfs_register("dl_", fw, dentry);
+        __debugfs_register("dl_", netdev, dentry);
+        __debugfs_register("dl_", rfkill, dentry);
+        __debugfs_register("dl_", rx, dentry);
+        __debugfs_register("dl_", tx, dentry);
+
+        fd = debugfs_create_size_t("tx_in", 0400, dentry,
+                                   &i2400m->tx_in);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "tx_in: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_size_t("tx_out", 0400, dentry,
+                                   &i2400m->tx_out);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "tx_out: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_u32("state", 0600, dentry,
+                                &i2400m->state);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "state: %d\n", result);
+                goto error;
+        }
+
+        /*
+         * Trace received messages from user space
+         *
+         * In order to tap the bidirectional message stream in the
+         * 'msg' pipe, user space can read from the 'msg' pipe;
+         * however, due to limitations in libnl, we can't know what
+         * the different applications are sending down to the kernel.
+         *
+         * So we have this hack where the driver will echo any message
+         * received on the msg pipe from user space [through a call to
+         * wimax_dev->op_msg_from_user() into
+         * i2400m_op_msg_from_user()] into the 'trace' pipe that this
+         * driver creates.
+         *
+         * So then, reading from both the 'trace' and 'msg' pipes in
+         * user space will provide a full dump of the traffic.
+         *
+         * Write 1 to activate, 0 to clear.
+         *
+         * It is not really very atomic, but it is also not too
+         * critical.
+         */
+        fd = debugfs_create_u8("trace_msg_from_user", 0600, dentry,
+                               &i2400m->trace_msg_from_user);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "trace_msg_from_user: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_netdev_queue_stopped("netdev_queue_stopped",
+                                                 dentry, i2400m);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "netdev_queue_stopped: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_file("rx_stats", 0600, dentry, i2400m,
+                                 &i2400m_rx_stats_fops);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "rx_stats: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_file("tx_stats", 0600, dentry, i2400m,
+                                 &i2400m_tx_stats_fops);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "tx_stats: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_i2400m_suspend("suspend", dentry, i2400m);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry suspend: %d\n",
+                        result);
+                goto error;
+        }
+
+        fd = debugfs_create_i2400m_reset("reset", dentry, i2400m);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry reset: %d\n", result);
+                goto error;
+        }
+
+        result = 0;
+error:
+        return result;
+}
+
+void i2400m_debugfs_rm(struct i2400m *i2400m)
+{
+        debugfs_remove_recursive(i2400m->debugfs_dentry);
+}
diff --git a/drivers/net/wimax/i2400m/driver.c b/drivers/net/wimax/i2400m/driver.c
new file mode 100644
index 000000000000..5f98047e18cf
--- /dev/null
+++ b/drivers/net/wimax/i2400m/driver.c
@@ -0,0 +1,728 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Generic probe/disconnect, reset and message passing
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * See i2400m.h for driver documentation. This contains helpers for
+ * the driver model glue [_setup()/_release()], handling device resets
+ * [_dev_reset_handle()], and the backends for the WiMAX stack ops
+ * reset [_op_reset()] and message from user [_op_msg_from_user()].
+ *
+ * ROADMAP:
+ *
+ * i2400m_op_msg_from_user()
+ *   i2400m_msg_to_dev()
+ *   wimax_msg_to_user_send()
+ *
+ * i2400m_op_reset()
+ *   i240m->bus_reset()
+ *
+ * i2400m_dev_reset_handle()
+ *   __i2400m_dev_reset_handle()
+ *     __i2400m_dev_stop()
+ *     __i2400m_dev_start()
+ *
+ * i2400m_setup()
+ *   i2400m_bootrom_init()
+ *   register_netdev()
+ *   i2400m_dev_start()
+ *     __i2400m_dev_start()
+ *       i2400m_dev_bootstrap()
+ *       i2400m_tx_setup()
+ *       i2400m->bus_dev_start()
+ *       i2400m_check_mac_addr()
+ *   wimax_dev_add()
+ *
+ * i2400m_release()
+ *   wimax_dev_rm()
+ *   i2400m_dev_stop()
+ *     __i2400m_dev_stop()
+ *       i2400m_dev_shutdown()
+ *       i2400m->bus_dev_stop()
+ *       i2400m_tx_release()
+ *   unregister_netdev()
+ */
+#include "i2400m.h"
+#include <linux/wimax/i2400m.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#define D_SUBMODULE driver
+#include "debug-levels.h"
+
+
+int i2400m_idle_mode_disabled;  /* 0 (idle mode enabled) by default */
+module_param_named(idle_mode_disabled, i2400m_idle_mode_disabled, int, 0644);
+MODULE_PARM_DESC(idle_mode_disabled,
+                 "If true, the device will not enable idle mode negotiation "
+                 "with the base station (when connected) to save power.");
+
+/**
+ * i2400m_queue_work - schedule work on a i2400m's queue
+ *
+ * @i2400m: device descriptor
+ *
+ * @fn: function to run to execute work. It gets passed a 'struct
+ *     work_struct' that is wrapped in a 'struct i2400m_work'. Once
+ *     done, you have to (1) i2400m_put(i2400m_work->i2400m) and then
+ *     (2) kfree(i2400m_work).
+ *
+ * @gfp_flags: GFP flags for memory allocation.
+ *
+ * @pl: pointer to a payload buffer that you want to pass to the _work
+ *     function. Use this to pack (for example) a struct with extra
+ *     arguments.
+ *
+ * @pl_size: size of the payload buffer.
+ *
+ * We do this quite often, so this just saves typing; allocate a
+ * wrapper for a i2400m, get a ref to it, pack arguments and launch
+ * the work.
+ *
+ * A usual workflow is:
+ *
+ * struct my_work_args {
+ *         void *something;
+ *         int whatever;
+ * };
+ * ...
+ *
+ * struct my_work_args my_args = {
+ *         .something = FOO,
+ *         .whaetever = BLAH
+ * };
+ * i2400m_queue_work(i2400m, 1, my_work_function, GFP_KERNEL,
+ *                   &args, sizeof(args))
+ *
+ * And now the work function can unpack the arguments and call the
+ * real function (or do the job itself):
+ *
+ * static
+ * void my_work_fn((struct work_struct *ws)
+ * {
+ *         struct i2400m_work *iw =
+ *                 container_of(ws, struct i2400m_work, ws);
+ *         struct my_work_args *my_args = (void *) iw->pl;
+ *
+ *         my_work(iw->i2400m, my_args->something, my_args->whatevert);
+ * }
+ */
+int i2400m_queue_work(struct i2400m *i2400m,
+                      void (*fn)(struct work_struct *), gfp_t gfp_flags,
+                      const void *pl, size_t pl_size)
+{
+        int result;
+        struct i2400m_work *iw;
+
+        BUG_ON(i2400m->work_queue == NULL);
+        result = -ENOMEM;
+        iw = kzalloc(sizeof(*iw) + pl_size, gfp_flags);
+        if (iw == NULL)
+                goto error_kzalloc;
+        iw->i2400m = i2400m_get(i2400m);
+        memcpy(iw->pl, pl, pl_size);
+        INIT_WORK(&iw->ws, fn);
+        result = queue_work(i2400m->work_queue, &iw->ws);
+error_kzalloc:
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_queue_work);
+
+
+/*
+ * Schedule i2400m's specific work on the system's queue.
+ *
+ * Used for a few cases where we really need it; otherwise, identical
+ * to i2400m_queue_work().
+ *
+ * Returns < 0 errno code on error, 1 if ok.
+ *
+ * If it returns zero, something really bad happened, as it means the
+ * works struct was already queued, but we have just allocated it, so
+ * it should not happen.
+ */
+int i2400m_schedule_work(struct i2400m *i2400m,
+                         void (*fn)(struct work_struct *), gfp_t gfp_flags)
+{
+        int result;
+        struct i2400m_work *iw;
+
+        BUG_ON(i2400m->work_queue == NULL);
+        result = -ENOMEM;
+        iw = kzalloc(sizeof(*iw), gfp_flags);
+        if (iw == NULL)
+                goto error_kzalloc;
+        iw->i2400m = i2400m_get(i2400m);
+        INIT_WORK(&iw->ws, fn);
+        result = schedule_work(&iw->ws);
+        if (result == 0)
+                result = -ENXIO;
+error_kzalloc:
+        return result;
+}
+
+
+/*
+ * WiMAX stack operation: relay a message from user space
+ *
+ * @wimax_dev: device descriptor
+ * @pipe_name: named pipe the message is for
+ * @msg_buf: pointer to the message bytes
+ * @msg_len: length of the buffer
+ * @genl_info: passed by the generic netlink layer
+ *
+ * The WiMAX stack will call this function when a message was received
+ * from user space.
+ *
+ * For the i2400m, this is an L3L4 message, as specified in
+ * include/linux/wimax/i2400m.h, and thus prefixed with a 'struct
+ * i2400m_l3l4_hdr'. Driver (and device) expect the messages to be
+ * coded in Little Endian.
+ *
+ * This function just verifies that the header declaration and the
+ * payload are consistent and then deals with it, either forwarding it
+ * to the device or procesing it locally.
+ *
+ * In the i2400m, messages are basically commands that will carry an
+ * ack, so we use i2400m_msg_to_dev() and then deliver the ack back to
+ * user space. The rx.c code might intercept the response and use it
+ * to update the driver's state, but then it will pass it on so it can
+ * be relayed back to user space.
+ *
+ * Note that asynchronous events from the device are processed and
+ * sent to user space in rx.c.
+ */
+static
+int i2400m_op_msg_from_user(struct wimax_dev *wimax_dev,
+                            const char *pipe_name,
+                            const void *msg_buf, size_t msg_len,
+                            const struct genl_info *genl_info)
+{
+        int result;
+        struct i2400m *i2400m = wimax_dev_to_i2400m(wimax_dev);
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+
+        d_fnstart(4, dev, "(wimax_dev %p [i2400m %p] msg_buf %p "
+                  "msg_len %zu genl_info %p)\n", wimax_dev, i2400m,
+                  msg_buf, msg_len, genl_info);
+        ack_skb = i2400m_msg_to_dev(i2400m, msg_buf, msg_len);
+        result = PTR_ERR(ack_skb);
+        if (IS_ERR(ack_skb))
+                goto error_msg_to_dev;
+        if (unlikely(i2400m->trace_msg_from_user))
+                wimax_msg(&i2400m->wimax_dev, "trace",
+                          msg_buf, msg_len, GFP_KERNEL);
+        result = wimax_msg_send(&i2400m->wimax_dev, ack_skb);
+error_msg_to_dev:
+        d_fnend(4, dev, "(wimax_dev %p [i2400m %p] msg_buf %p msg_len %zu "
+                "genl_info %p) = %d\n", wimax_dev, i2400m, msg_buf, msg_len,
+                genl_info, result);
+        return result;
+}
+
+
+/*
+ * Context to wait for a reset to finalize
+ */
+struct i2400m_reset_ctx {
+        struct completion completion;
+        int result;
+};
+
+
+/*
+ * WiMAX stack operation: reset a device
+ *
+ * @wimax_dev: device descriptor
+ *
+ * See the documentation for wimax_reset() and wimax_dev->op_reset for
+ * the requirements of this function. The WiMAX stack guarantees
+ * serialization on calls to this function.
+ *
+ * Do a warm reset on the device; if it fails, resort to a cold reset
+ * and return -ENODEV. On successful warm reset, we need to block
+ * until it is complete.
+ *
+ * The bus-driver implementation of reset takes care of falling back
+ * to cold reset if warm fails.
+ */
+static
+int i2400m_op_reset(struct wimax_dev *wimax_dev)
+{
+        int result;
+        struct i2400m *i2400m = wimax_dev_to_i2400m(wimax_dev);
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_reset_ctx ctx = {
+                .completion = COMPLETION_INITIALIZER_ONSTACK(ctx.completion),
+                .result = 0,
+        };
+
+        d_fnstart(4, dev, "(wimax_dev %p)\n", wimax_dev);
+        mutex_lock(&i2400m->init_mutex);
+        i2400m->reset_ctx = &ctx;
+        mutex_unlock(&i2400m->init_mutex);
+        result = i2400m->bus_reset(i2400m, I2400M_RT_WARM);
+        if (result < 0)
+                goto out;
+        result = wait_for_completion_timeout(&ctx.completion, 4*HZ);
+        if (result == 0)
+                result = -ETIMEDOUT;
+        else if (result > 0)
+                result = ctx.result;
+        /* if result < 0, pass it on */
+        mutex_lock(&i2400m->init_mutex);
+        i2400m->reset_ctx = NULL;
+        mutex_unlock(&i2400m->init_mutex);
+out:
+        d_fnend(4, dev, "(wimax_dev %p) = %d\n", wimax_dev, result);
+        return result;
+}
+
+
+/*
+ * Check the MAC address we got from boot mode is ok
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ */
+static
+int i2400m_check_mac_addr(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *skb;
+        const struct i2400m_tlv_detailed_device_info *ddi;
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+        const unsigned char zeromac[ETH_ALEN] = { 0 };
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        skb = i2400m_get_device_info(i2400m);
+        if (IS_ERR(skb)) {
+                result = PTR_ERR(skb);
+                dev_err(dev, "Cannot verify MAC address, error reading: %d\n",
+                        result);
+                goto error;
+        }
+        /* Extract MAC addresss */
+        ddi = (void *) skb->data;
+        BUILD_BUG_ON(ETH_ALEN != sizeof(ddi->mac_address));
+        d_printf(2, dev, "GET DEVICE INFO: mac addr "
+                 "%02x:%02x:%02x:%02x:%02x:%02x\n",
+                 ddi->mac_address[0], ddi->mac_address[1],
+                 ddi->mac_address[2], ddi->mac_address[3],
+                 ddi->mac_address[4], ddi->mac_address[5]);
+        if (!memcmp(net_dev->perm_addr, ddi->mac_address,
+                   sizeof(ddi->mac_address)))
+                goto ok;
+        dev_warn(dev, "warning: device reports a different MAC address "
+                 "to that of boot mode's\n");
+        dev_warn(dev, "device reports     %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 ddi->mac_address[0], ddi->mac_address[1],
+                 ddi->mac_address[2], ddi->mac_address[3],
+                 ddi->mac_address[4], ddi->mac_address[5]);
+        dev_warn(dev, "boot mode reported %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 net_dev->perm_addr[0], net_dev->perm_addr[1],
+                 net_dev->perm_addr[2], net_dev->perm_addr[3],
+                 net_dev->perm_addr[4], net_dev->perm_addr[5]);
+        if (!memcmp(zeromac, ddi->mac_address, sizeof(zeromac)))
+                dev_err(dev, "device reports an invalid MAC address, "
+                        "not updating\n");
+        else {
+                dev_warn(dev, "updating MAC address\n");
+                net_dev->addr_len = ETH_ALEN;
+                memcpy(net_dev->perm_addr, ddi->mac_address, ETH_ALEN);
+                memcpy(net_dev->dev_addr, ddi->mac_address, ETH_ALEN);
+        }
+ok:
+        result = 0;
+        kfree_skb(skb);
+error:
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+}
+
+
+/**
+ * __i2400m_dev_start - Bring up driver communication with the device
+ *
+ * @i2400m: device descriptor
+ * @flags: boot mode flags
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * Uploads firmware and brings up all the resources needed to be able
+ * to communicate with the device.
+ *
+ * TX needs to be setup before the bus-specific code (otherwise on
+ * shutdown, the bus-tx code could try to access it).
+ */
+static
+int __i2400m_dev_start(struct i2400m *i2400m, enum i2400m_bri flags)
+{
+        int result;
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        struct net_device *net_dev = wimax_dev->net_dev;
+        struct device *dev = i2400m_dev(i2400m);
+        int times = 3;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+retry:
+        result = i2400m_dev_bootstrap(i2400m, flags);
+        if (result < 0) {
+                dev_err(dev, "cannot bootstrap device: %d\n", result);
+                goto error_bootstrap;
+        }
+        result = i2400m_tx_setup(i2400m);
+        if (result < 0)
+                goto error_tx_setup;
+        result = i2400m->bus_dev_start(i2400m);
+        if (result < 0)
+                goto error_bus_dev_start;
+        i2400m->work_queue = create_singlethread_workqueue(wimax_dev->name);
+        if (i2400m->work_queue == NULL) {
+                result = -ENOMEM;
+                dev_err(dev, "cannot create workqueue\n");
+                goto error_create_workqueue;
+        }
+        /* At this point is ok to send commands to the device */
+        result = i2400m_check_mac_addr(i2400m);
+        if (result < 0)
+                goto error_check_mac_addr;
+        i2400m->ready = 1;
+        wimax_state_change(wimax_dev, WIMAX_ST_UNINITIALIZED);
+        result = i2400m_dev_initialize(i2400m);
+        if (result < 0)
+                goto error_dev_initialize;
+        /* At this point, reports will come for the device and set it
+         * to the right state if it is different than UNINITIALIZED */
+        d_fnend(3, dev, "(net_dev %p [i2400m %p]) = %d\n",
+                net_dev, i2400m, result);
+        return result;
+
+error_dev_initialize:
+error_check_mac_addr:
+        destroy_workqueue(i2400m->work_queue);
+error_create_workqueue:
+        i2400m->bus_dev_stop(i2400m);
+error_bus_dev_start:
+        i2400m_tx_release(i2400m);
+error_tx_setup:
+error_bootstrap:
+        if (result == -ERESTARTSYS && times-- > 0) {
+                flags = I2400M_BRI_SOFT;
+                goto retry;
+        }
+        d_fnend(3, dev, "(net_dev %p [i2400m %p]) = %d\n",
+                net_dev, i2400m, result);
+        return result;
+}
+
+
+static
+int i2400m_dev_start(struct i2400m *i2400m, enum i2400m_bri bm_flags)
+{
+        int result;
+        mutex_lock(&i2400m->init_mutex);        /* Well, start the device */
+        result = __i2400m_dev_start(i2400m, bm_flags);
+        if (result >= 0)
+                i2400m->updown = 1;
+        mutex_unlock(&i2400m->init_mutex);
+        return result;
+}
+
+
+/**
+ * i2400m_dev_stop - Tear down driver communication with the device
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * Releases all the resources allocated to communicate with the device.
+ */
+static
+void __i2400m_dev_stop(struct i2400m *i2400m)
+{
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        wimax_state_change(wimax_dev, __WIMAX_ST_QUIESCING);
+        i2400m_dev_shutdown(i2400m);
+        i2400m->ready = 0;
+        destroy_workqueue(i2400m->work_queue);
+        i2400m->bus_dev_stop(i2400m);
+        i2400m_tx_release(i2400m);
+        wimax_state_change(wimax_dev, WIMAX_ST_DOWN);
+        d_fnend(3, dev, "(i2400m %p) = 0\n", i2400m);
+}
+
+
+/*
+ * Watch out -- we only need to stop if there is a need for it. The
+ * device could have reset itself and failed to come up again (see
+ * _i2400m_dev_reset_handle()).
+ */
+static
+void i2400m_dev_stop(struct i2400m *i2400m)
+{
+        mutex_lock(&i2400m->init_mutex);
+        if (i2400m->updown) {
+                __i2400m_dev_stop(i2400m);
+                i2400m->updown = 0;
+        }
+        mutex_unlock(&i2400m->init_mutex);
+}
+
+
+/*
+ * The device has rebooted; fix up the device and the driver
+ *
+ * Tear down the driver communication with the device, reload the
+ * firmware and reinitialize the communication with the device.
+ *
+ * If someone calls a reset when the device's firmware is down, in
+ * theory we won't see it because we are not listening. However, just
+ * in case, leave the code to handle it.
+ *
+ * If there is a reset context, use it; this means someone is waiting
+ * for us to tell him when the reset operation is complete and the
+ * device is ready to rock again.
+ *
+ * NOTE: if we are in the process of bringing up or down the
+ *       communication with the device [running i2400m_dev_start() or
+ *       _stop()], don't do anything, let it fail and handle it.
+ *
+ * This function is ran always in a thread context
+ */
+static
+void __i2400m_dev_reset_handle(struct work_struct *ws)
+{
+        int result;
+        struct i2400m_work *iw = container_of(ws, struct i2400m_work, ws);
+        struct i2400m *i2400m = iw->i2400m;
+        struct device *dev = i2400m_dev(i2400m);
+        enum wimax_st wimax_state;
+        struct i2400m_reset_ctx *ctx = i2400m->reset_ctx;
+
+        d_fnstart(3, dev, "(ws %p i2400m %p)\n", ws, i2400m);
+        result = 0;
+        if (mutex_trylock(&i2400m->init_mutex) == 0) {
+                /* We are still in i2400m_dev_start() [let it fail] or
+                 * i2400m_dev_stop() [we are shutting down anyway, so
+                 * ignore it] or we are resetting somewhere else. */
+                dev_err(dev, "device rebooted\n");
+                i2400m_msg_to_dev_cancel_wait(i2400m, -ERESTARTSYS);
+                complete(&i2400m->msg_completion);
+                goto out;
+        }
+        wimax_state = wimax_state_get(&i2400m->wimax_dev);
+        if (wimax_state < WIMAX_ST_UNINITIALIZED) {
+                dev_info(dev, "device rebooted: it is down, ignoring\n");
+                goto out_unlock;        /* ifconfig up/down wasn't called */
+        }
+        dev_err(dev, "device rebooted: reinitializing driver\n");
+        __i2400m_dev_stop(i2400m);
+        i2400m->updown = 0;
+        result = __i2400m_dev_start(i2400m,
+                                    I2400M_BRI_SOFT | I2400M_BRI_MAC_REINIT);
+        if (result < 0) {
+                dev_err(dev, "device reboot: cannot start the device: %d\n",
+                        result);
+                result = i2400m->bus_reset(i2400m, I2400M_RT_BUS);
+                if (result >= 0)
+                        result = -ENODEV;
+        } else
+                i2400m->updown = 1;
+out_unlock:
+        if (i2400m->reset_ctx) {
+                ctx->result = result;
+                complete(&ctx->completion);
+        }
+        mutex_unlock(&i2400m->init_mutex);
+out:
+        i2400m_put(i2400m);
+        kfree(iw);
+        d_fnend(3, dev, "(ws %p i2400m %p) = void\n", ws, i2400m);
+        return;
+}
+
+
+/**
+ * i2400m_dev_reset_handle - Handle a device's reset in a thread context
+ *
+ * Schedule a device reset handling out on a thread context, so it
+ * is safe to call from atomic context. We can't use the i2400m's
+ * queue as we are going to destroy it and reinitialize it as part of
+ * the driver bringup/bringup process.
+ *
+ * See __i2400m_dev_reset_handle() for details; that takes care of
+ * reinitializing the driver to handle the reset, calling into the
+ * bus-specific functions ops as needed.
+ */
+int i2400m_dev_reset_handle(struct i2400m *i2400m)
+{
+        return i2400m_schedule_work(i2400m, __i2400m_dev_reset_handle,
+                                    GFP_ATOMIC);
+}
+EXPORT_SYMBOL_GPL(i2400m_dev_reset_handle);
+
+
+/**
+ * i2400m_setup - bus-generic setup function for the i2400m device
+ *
+ * @i2400m: device descriptor (bus-specific parts have been initialized)
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * Initializes the bus-generic parts of the i2400m driver; the
+ * bus-specific parts have been initialized, function pointers filled
+ * out by the bus-specific probe function.
+ *
+ * As well, this registers the WiMAX and net device nodes. Once this
+ * function returns, the device is operative and has to be ready to
+ * receive and send network traffic and WiMAX control operations.
+ */
+int i2400m_setup(struct i2400m *i2400m, enum i2400m_bri bm_flags)
+{
+        int result = -ENODEV;
+        struct device *dev = i2400m_dev(i2400m);
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+
+        snprintf(wimax_dev->name, sizeof(wimax_dev->name),
+                 "i2400m-%s:%s", dev->bus->name, dev->bus_id);
+
+        i2400m->bm_cmd_buf = kzalloc(I2400M_BM_CMD_BUF_SIZE, GFP_KERNEL);
+        if (i2400m->bm_cmd_buf == NULL) {
+                dev_err(dev, "cannot allocate USB command buffer\n");
+                goto error_bm_cmd_kzalloc;
+        }
+        i2400m->bm_ack_buf = kzalloc(I2400M_BM_ACK_BUF_SIZE, GFP_KERNEL);
+        if (i2400m->bm_ack_buf == NULL) {
+                dev_err(dev, "cannot allocate USB ack buffer\n");
+                goto error_bm_ack_buf_kzalloc;
+        }
+        result = i2400m_bootrom_init(i2400m, bm_flags);
+        if (result < 0) {
+                dev_err(dev, "read mac addr: bootrom init "
+                        "failed: %d\n", result);
+                goto error_bootrom_init;
+        }
+        result = i2400m_read_mac_addr(i2400m);
+        if (result < 0)
+                goto error_read_mac_addr;
+
+        result = register_netdev(net_dev);      /* Okey dokey, bring it up */
+        if (result < 0) {
+                dev_err(dev, "cannot register i2400m network device: %d\n",
+                        result);
+                goto error_register_netdev;
+        }
+        netif_carrier_off(net_dev);
+
+        result = i2400m_dev_start(i2400m, bm_flags);
+        if (result < 0)
+                goto error_dev_start;
+
+        i2400m->wimax_dev.op_msg_from_user = i2400m_op_msg_from_user;
+        i2400m->wimax_dev.op_rfkill_sw_toggle = i2400m_op_rfkill_sw_toggle;
+        i2400m->wimax_dev.op_reset = i2400m_op_reset;
+        result = wimax_dev_add(&i2400m->wimax_dev, net_dev);
+        if (result < 0)
+                goto error_wimax_dev_add;
+        /* User space needs to do some init stuff */
+        wimax_state_change(wimax_dev, WIMAX_ST_UNINITIALIZED);
+
+        /* Now setup all that requires a registered net and wimax device. */
+        result = i2400m_debugfs_add(i2400m);
+        if (result < 0) {
+                dev_err(dev, "cannot setup i2400m's debugfs: %d\n", result);
+                goto error_debugfs_setup;
+        }
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+
+error_debugfs_setup:
+        wimax_dev_rm(&i2400m->wimax_dev);
+error_wimax_dev_add:
+        i2400m_dev_stop(i2400m);
+error_dev_start:
+        unregister_netdev(net_dev);
+error_register_netdev:
+error_read_mac_addr:
+error_bootrom_init:
+        kfree(i2400m->bm_ack_buf);
+error_bm_ack_buf_kzalloc:
+        kfree(i2400m->bm_cmd_buf);
+error_bm_cmd_kzalloc:
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_setup);
+
+
+/**
+ * i2400m_release - release the bus-generic driver resources
+ *
+ * Sends a disconnect message and undoes any setup done by i2400m_setup()
+ */
+void i2400m_release(struct i2400m *i2400m)
+{
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        netif_stop_queue(i2400m->wimax_dev.net_dev);
+
+        i2400m_debugfs_rm(i2400m);
+        wimax_dev_rm(&i2400m->wimax_dev);
+        i2400m_dev_stop(i2400m);
+        unregister_netdev(i2400m->wimax_dev.net_dev);
+        kfree(i2400m->bm_ack_buf);
+        kfree(i2400m->bm_cmd_buf);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+EXPORT_SYMBOL_GPL(i2400m_release);
+
+
+static
+int __init i2400m_driver_init(void)
+{
+        return 0;
+}
+module_init(i2400m_driver_init);
+
+static
+void __exit i2400m_driver_exit(void)
+{
+        /* for scheds i2400m_dev_reset_handle() */
+        flush_scheduled_work();
+        return;
+}
+module_exit(i2400m_driver_exit);
+
+MODULE_AUTHOR("Intel Corporation <linux-wimax@intel.com>");
+MODULE_DESCRIPTION("Intel 2400M WiMAX networking bus-generic driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/wimax/i2400m/fw.c b/drivers/net/wimax/i2400m/fw.c
new file mode 100644
index 000000000000..1d8271f34c38
--- /dev/null
+++ b/drivers/net/wimax/i2400m/fw.c
@@ -0,0 +1,1095 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Firmware uploader
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * THE PROCEDURE
+ *
+ * (this is decribed for USB, but for SDIO is similar)
+ *
+ * The 2400m works in two modes: boot-mode or normal mode. In boot
+ * mode we can execute only a handful of commands targeted at
+ * uploading the firmware and launching it.
+ *
+ * The 2400m enters boot mode when it is first connected to the
+ * system, when it crashes and when you ask it to reboot. There are
+ * two submodes of the boot mode: signed and non-signed. Signed takes
+ * firmwares signed with a certain private key, non-signed takes any
+ * firmware. Normal hardware takes only signed firmware.
+ *
+ * Upon entrance to boot mode, the device sends a few zero length
+ * packets (ZLPs) on the notification endpoint, then a reboot barker
+ * (4 le32 words with value I2400M_{S,N}BOOT_BARKER). We ack it by
+ * sending the same barker on the bulk out endpoint. The device acks
+ * with a reboot ack barker (4 le32 words with value 0xfeedbabe) and
+ * then the device is fully rebooted. At this point we can upload the
+ * firmware.
+ *
+ * This process is accomplished by the i2400m_bootrom_init()
+ * function. All the device interaction happens through the
+ * i2400m_bm_cmd() [boot mode command]. Special return values will
+ * indicate if the device resets.
+ *
+ * After this, we read the MAC address and then (if needed)
+ * reinitialize the device. We need to read it ahead of time because
+ * in the future, we might not upload the firmware until userspace
+ * 'ifconfig up's the device.
+ *
+ * We can then upload the firmware file. The file is composed of a BCF
+ * header (basic data, keys and signatures) and a list of write
+ * commands and payloads. We first upload the header
+ * [i2400m_dnload_init()] and then pass the commands and payloads
+ * verbatim to the i2400m_bm_cmd() function
+ * [i2400m_dnload_bcf()]. Then we tell the device to jump to the new
+ * firmware [i2400m_dnload_finalize()].
+ *
+ * Once firmware is uploaded, we are good to go :)
+ *
+ * When we don't know in which mode we are, we first try by sending a
+ * warm reset request that will take us to boot-mode. If we time out
+ * waiting for a reboot barker, that means maybe we are already in
+ * boot mode, so we send a reboot barker.
+ *
+ * COMMAND EXECUTION
+ *
+ * This code (and process) is single threaded; for executing commands,
+ * we post a URB to the notification endpoint, post the command, wait
+ * for data on the notification buffer. We don't need to worry about
+ * others as we know we are the only ones in there.
+ *
+ * BACKEND IMPLEMENTATION
+ *
+ * This code is bus-generic; the bus-specific driver provides back end
+ * implementations to send a boot mode command to the device and to
+ * read an acknolwedgement from it (or an asynchronous notification)
+ * from it.
+ *
+ * ROADMAP
+ *
+ * i2400m_dev_bootstrap               Called by __i2400m_dev_start()
+ *   request_firmware
+ *   i2400m_fw_check
+ *   i2400m_fw_dnload
+ *   release_firmware
+ *
+ * i2400m_fw_dnload
+ *   i2400m_bootrom_init
+ *     i2400m_bm_cmd
+ *     i2400m->bus_reset
+ *   i2400m_dnload_init
+ *     i2400m_dnload_init_signed
+ *     i2400m_dnload_init_nonsigned
+ *       i2400m_download_chunk
+ *         i2400m_bm_cmd
+ *   i2400m_dnload_bcf
+ *     i2400m_bm_cmd
+ *   i2400m_dnload_finalize
+ *     i2400m_bm_cmd
+ *
+ * i2400m_bm_cmd
+ *   i2400m->bus_bm_cmd_send()
+ *   i2400m->bus_bm_wait_for_ack
+ *   __i2400m_bm_ack_verify
+ *
+ * i2400m_bm_cmd_prepare              Used by bus-drivers to prep
+ *                                    commands before sending
+ */
+#include <linux/firmware.h>
+#include <linux/sched.h>
+#include <linux/usb.h>
+#include "i2400m.h"
+
+
+#define D_SUBMODULE fw
+#include "debug-levels.h"
+
+
+static const __le32 i2400m_ACK_BARKER[4] = {
+        __constant_cpu_to_le32(I2400M_ACK_BARKER),
+        __constant_cpu_to_le32(I2400M_ACK_BARKER),
+        __constant_cpu_to_le32(I2400M_ACK_BARKER),
+        __constant_cpu_to_le32(I2400M_ACK_BARKER)
+};
+
+
+/**
+ * Prepare a boot-mode command for delivery
+ *
+ * @cmd: pointer to bootrom header to prepare
+ *
+ * Computes checksum if so needed. After calling this function, DO NOT
+ * modify the command or header as the checksum won't work anymore.
+ *
+ * We do it from here because some times we cannot do it in the
+ * original context the command was sent (it is a const), so when we
+ * copy it to our staging buffer, we add the checksum there.
+ */
+void i2400m_bm_cmd_prepare(struct i2400m_bootrom_header *cmd)
+{
+        if (i2400m_brh_get_use_checksum(cmd)) {
+                int i;
+                u32 checksum = 0;
+                const u32 *checksum_ptr = (void *) cmd->payload;
+                for (i = 0; i < cmd->data_size / 4; i++)
+                        checksum += cpu_to_le32(*checksum_ptr++);
+                checksum += cmd->command + cmd->target_addr + cmd->data_size;
+                cmd->block_checksum = cpu_to_le32(checksum);
+        }
+}
+EXPORT_SYMBOL_GPL(i2400m_bm_cmd_prepare);
+
+
+/*
+ * Verify the ack data received
+ *
+ * Given a reply to a boot mode command, chew it and verify everything
+ * is ok.
+ *
+ * @opcode: opcode which generated this ack. For error messages.
+ * @ack: pointer to ack data we received
+ * @ack_size: size of that data buffer
+ * @flags: I2400M_BM_CMD_* flags we called the command with.
+ *
+ * Way too long function -- maybe it should be further split
+ */
+static
+ssize_t __i2400m_bm_ack_verify(struct i2400m *i2400m, int opcode,
+                               struct i2400m_bootrom_header *ack,
+                               size_t ack_size, int flags)
+{
+        ssize_t result = -ENOMEM;
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(8, dev, "(i2400m %p opcode %d ack %p size %zu)\n",
+                  i2400m, opcode, ack, ack_size);
+        if (ack_size < sizeof(*ack)) {
+                result = -EIO;
+                dev_err(dev, "boot-mode cmd %d: HW BUG? notification didn't "
+                        "return enough data (%zu bytes vs %zu expected)\n",
+                        opcode, ack_size, sizeof(*ack));
+                goto error_ack_short;
+        }
+        if (ack_size == sizeof(i2400m_NBOOT_BARKER)
+                 && memcmp(ack, i2400m_NBOOT_BARKER, sizeof(*ack)) == 0) {
+                result = -ERESTARTSYS;
+                i2400m->sboot = 0;
+                d_printf(6, dev, "boot-mode cmd %d: "
+                         "HW non-signed boot barker\n", opcode);
+                goto error_reboot;
+        }
+        if (ack_size == sizeof(i2400m_SBOOT_BARKER)
+                 && memcmp(ack, i2400m_SBOOT_BARKER, sizeof(*ack)) == 0) {
+                result = -ERESTARTSYS;
+                i2400m->sboot = 1;
+                d_printf(6, dev, "boot-mode cmd %d: HW signed reboot barker\n",
+                         opcode);
+                goto error_reboot;
+        }
+        if (ack_size == sizeof(i2400m_ACK_BARKER)
+                 && memcmp(ack, i2400m_ACK_BARKER, sizeof(*ack)) == 0) {
+                result = -EISCONN;
+                d_printf(3, dev, "boot-mode cmd %d: HW reboot ack barker\n",
+                         opcode);
+                goto error_reboot_ack;
+        }
+        result = 0;
+        if (flags & I2400M_BM_CMD_RAW)
+                goto out_raw;
+        ack->data_size = le32_to_cpu(ack->data_size);
+        ack->target_addr = le32_to_cpu(ack->target_addr);
+        ack->block_checksum = le32_to_cpu(ack->block_checksum);
+        d_printf(5, dev, "boot-mode cmd %d: notification for opcode %u "
+                 "response %u csum %u rr %u da %u\n",
+                 opcode, i2400m_brh_get_opcode(ack),
+                 i2400m_brh_get_response(ack),
+                 i2400m_brh_get_use_checksum(ack),
+                 i2400m_brh_get_response_required(ack),
+                 i2400m_brh_get_direct_access(ack));
+        result = -EIO;
+        if (i2400m_brh_get_signature(ack) != 0xcbbc) {
+                dev_err(dev, "boot-mode cmd %d: HW BUG? wrong signature "
+                        "0x%04x\n", opcode, i2400m_brh_get_signature(ack));
+                goto error_ack_signature;
+        }
+        if (opcode != -1 && opcode != i2400m_brh_get_opcode(ack)) {
+                dev_err(dev, "boot-mode cmd %d: HW BUG? "
+                        "received response for opcode %u, expected %u\n",
+                        opcode, i2400m_brh_get_opcode(ack), opcode);
+                goto error_ack_opcode;
+        }
+        if (i2400m_brh_get_response(ack) != 0) {        /* failed? */
+                dev_err(dev, "boot-mode cmd %d: error; hw response %u\n",
+                        opcode, i2400m_brh_get_response(ack));
+                goto error_ack_failed;
+        }
+        if (ack_size < ack->data_size + sizeof(*ack)) {
+                dev_err(dev, "boot-mode cmd %d: SW BUG "
+                        "driver provided only %zu bytes for %zu bytes "
+                        "of data\n", opcode, ack_size,
+                        (size_t) le32_to_cpu(ack->data_size) + sizeof(*ack));
+                goto error_ack_short_buffer;
+        }
+        result = ack_size;
+        /* Don't you love this stack of empty targets? Well, I don't
+         * either, but it helps track exactly who comes in here and
+         * why :) */
+error_ack_short_buffer:
+error_ack_failed:
+error_ack_opcode:
+error_ack_signature:
+out_raw:
+error_reboot_ack:
+error_reboot:
+error_ack_short:
+        d_fnend(8, dev, "(i2400m %p opcode %d ack %p size %zu) = %d\n",
+                i2400m, opcode, ack, ack_size, (int) result);
+        return result;
+}
+
+
+/**
+ * i2400m_bm_cmd - Execute a boot mode command
+ *
+ * @cmd: buffer containing the command data (pointing at the header).
+ *     This data can be ANYWHERE (for USB, we will copy it to an
+ *     specific buffer). Make sure everything is in proper little
+ *     endian.
+ *
+ *     A raw buffer can be also sent, just cast it and set flags to
+ *     I2400M_BM_CMD_RAW.
+ *
+ *     This function will generate a checksum for you if the
+ *     checksum bit in the command is set (unless I2400M_BM_CMD_RAW
+ *     is set).
+ *
+ *     You can use the i2400m->bm_cmd_buf to stage your commands and
+ *     send them.
+ *
+ *     If NULL, no command is sent (we just wait for an ack).
+ *
+ * @cmd_size: size of the command. Will be auto padded to the
+ *     bus-specific drivers padding requirements.
+ *
+ * @ack: buffer where to place the acknowledgement. If it is a regular
+ *     command response, all fields will be returned with the right,
+ *     native endianess.
+ *
+ *     You *cannot* use i2400m->bm_ack_buf for this buffer.
+ *
+ * @ack_size: size of @ack, 16 aligned; you need to provide at least
+ *     sizeof(*ack) bytes and then enough to contain the return data
+ *     from the command
+ *
+ * @flags: see I2400M_BM_CMD_* above.
+ *
+ * @returns: bytes received by the notification; if < 0, an errno code
+ *     denoting an error or:
+ *
+ *     -ERESTARTSYS  The device has rebooted
+ *
+ * Executes a boot-mode command and waits for a response, doing basic
+ * validation on it; if a zero length response is received, it retries
+ * waiting for a response until a non-zero one is received (timing out
+ * after %I2400M_BOOT_RETRIES retries).
+ */
+static
+ssize_t i2400m_bm_cmd(struct i2400m *i2400m,
+                      const struct i2400m_bootrom_header *cmd, size_t cmd_size,
+                      struct i2400m_bootrom_header *ack, size_t ack_size,
+                      int flags)
+{
+        ssize_t result = -ENOMEM, rx_bytes;
+        struct device *dev = i2400m_dev(i2400m);
+        int opcode = cmd == NULL ? -1 : i2400m_brh_get_opcode(cmd);
+
+        d_fnstart(6, dev, "(i2400m %p cmd %p size %zu ack %p size %zu)\n",
+                  i2400m, cmd, cmd_size, ack, ack_size);
+        BUG_ON(ack_size < sizeof(*ack));
+        BUG_ON(i2400m->boot_mode == 0);
+
+        if (cmd != NULL) {              /* send the command */
+                memcpy(i2400m->bm_cmd_buf, cmd, cmd_size);
+                result = i2400m->bus_bm_cmd_send(i2400m, cmd, cmd_size, flags);
+                if (result < 0)
+                        goto error_cmd_send;
+                if ((flags & I2400M_BM_CMD_RAW) == 0)
+                        d_printf(5, dev,
+                                 "boot-mode cmd %d csum %u rr %u da %u: "
+                                 "addr 0x%04x size %u block csum 0x%04x\n",
+                                 opcode, i2400m_brh_get_use_checksum(cmd),
+                                 i2400m_brh_get_response_required(cmd),
+                                 i2400m_brh_get_direct_access(cmd),
+                                 cmd->target_addr, cmd->data_size,
+                                 cmd->block_checksum);
+        }
+        result = i2400m->bus_bm_wait_for_ack(i2400m, ack, ack_size);
+        if (result < 0) {
+                dev_err(dev, "boot-mode cmd %d: error waiting for an ack: %d\n",
+                        opcode, (int) result);  /* bah, %zd doesn't work */
+                goto error_wait_for_ack;
+        }
+        rx_bytes = result;
+        /* verify the ack and read more if neccessary [result is the
+         * final amount of bytes we get in the ack]  */
+        result = __i2400m_bm_ack_verify(i2400m, opcode, ack, ack_size, flags);
+        if (result < 0)
+                goto error_bad_ack;
+        /* Don't you love this stack of empty targets? Well, I don't
+         * either, but it helps track exactly who comes in here and
+         * why :) */
+        result = rx_bytes;
+error_bad_ack:
+error_wait_for_ack:
+error_cmd_send:
+        d_fnend(6, dev, "(i2400m %p cmd %p size %zu ack %p size %zu) = %d\n",
+                i2400m, cmd, cmd_size, ack, ack_size, (int) result);
+        return result;
+}
+
+
+/**
+ * i2400m_download_chunk - write a single chunk of data to the device's memory
+ *
+ * @i2400m: device descriptor
+ * @buf: the buffer to write
+ * @buf_len: length of the buffer to write
+ * @addr: address in the device memory space
+ * @direct: bootrom write mode
+ * @do_csum: should a checksum validation be performed
+ */
+static int i2400m_download_chunk(struct i2400m *i2400m, const void *chunk,
+                                 size_t __chunk_len, unsigned long addr,
+                                 unsigned int direct, unsigned int do_csum)
+{
+        int ret;
+        size_t chunk_len = ALIGN(__chunk_len, I2400M_PL_PAD);
+        struct device *dev = i2400m_dev(i2400m);
+        struct {
+                struct i2400m_bootrom_header cmd;
+                u8 cmd_payload[chunk_len];
+        } __attribute__((packed)) *buf;
+        struct i2400m_bootrom_header ack;
+
+        d_fnstart(5, dev, "(i2400m %p chunk %p __chunk_len %zu addr 0x%08lx "
+                  "direct %u do_csum %u)\n", i2400m, chunk, __chunk_len,
+                  addr, direct, do_csum);
+        buf = i2400m->bm_cmd_buf;
+        memcpy(buf->cmd_payload, chunk, __chunk_len);
+        memset(buf->cmd_payload + __chunk_len, 0xad, chunk_len - __chunk_len);
+
+        buf->cmd.command = i2400m_brh_command(I2400M_BRH_WRITE,
+                                              __chunk_len & 0x3 ? 0 : do_csum,
+                                              __chunk_len & 0xf ? 0 : direct);
+        buf->cmd.target_addr = cpu_to_le32(addr);
+        buf->cmd.data_size = cpu_to_le32(__chunk_len);
+        ret = i2400m_bm_cmd(i2400m, &buf->cmd, sizeof(buf->cmd) + chunk_len,
+                            &ack, sizeof(ack), 0);
+        if (ret >= 0)
+                ret = 0;
+        d_fnend(5, dev, "(i2400m %p chunk %p __chunk_len %zu addr 0x%08lx "
+                "direct %u do_csum %u) = %d\n", i2400m, chunk, __chunk_len,
+                addr, direct, do_csum, ret);
+        return ret;
+}
+
+
+/*
+ * Download a BCF file's sections to the device
+ *
+ * @i2400m: device descriptor
+ * @bcf: pointer to firmware data (followed by the payloads). Assumed
+ *       verified and consistent.
+ * @bcf_len: length (in bytes) of the @bcf buffer.
+ *
+ * Returns: < 0 errno code on error or the offset to the jump instruction.
+ *
+ * Given a BCF file, downloads each section (a command and a payload)
+ * to the device's address space. Actually, it just executes each
+ * command i the BCF file.
+ *
+ * The section size has to be aligned to 4 bytes AND the padding has
+ * to be taken from the firmware file, as the signature takes it into
+ * account.
+ */
+static
+ssize_t i2400m_dnload_bcf(struct i2400m *i2400m,
+                          const struct i2400m_bcf_hdr *bcf, size_t bcf_len)
+{
+        ssize_t ret;
+        struct device *dev = i2400m_dev(i2400m);
+        size_t offset,          /* iterator offset */
+                data_size,      /* Size of the data payload */
+                section_size,   /* Size of the whole section (cmd + payload) */
+                section = 1;
+        const struct i2400m_bootrom_header *bh;
+        struct i2400m_bootrom_header ack;
+
+        d_fnstart(3, dev, "(i2400m %p bcf %p bcf_len %zu)\n",
+                  i2400m, bcf, bcf_len);
+        /* Iterate over the command blocks in the BCF file that start
+         * after the header */
+        offset = le32_to_cpu(bcf->header_len) * sizeof(u32);
+        while (1) {     /* start sending the file */
+                bh = (void *) bcf + offset;
+                data_size = le32_to_cpu(bh->data_size);
+                section_size = ALIGN(sizeof(*bh) + data_size, 4);
+                d_printf(7, dev,
+                         "downloading section #%zu (@%zu %zu B) to 0x%08x\n",
+                         section, offset, sizeof(*bh) + data_size,
+                         le32_to_cpu(bh->target_addr));
+                if (i2400m_brh_get_opcode(bh) == I2400M_BRH_SIGNED_JUMP) {
+                        /* Secure boot needs to stop here */
+                        d_printf(5, dev,  "signed jump found @%zu\n", offset);
+                        break;
+                }
+                if (offset + section_size == bcf_len)
+                        /* Non-secure boot stops here */
+                        break;
+                if (offset + section_size > bcf_len) {
+                        dev_err(dev, "fw %s: bad section #%zu, "
+                                "end (@%zu) beyond EOF (@%zu)\n",
+                                i2400m->bus_fw_name, section,
+                                offset + section_size,  bcf_len);
+                        ret = -EINVAL;
+                        goto error_section_beyond_eof;
+                }
+                __i2400m_msleep(20);
+                ret = i2400m_bm_cmd(i2400m, bh, section_size,
+                                    &ack, sizeof(ack), I2400M_BM_CMD_RAW);
+                if (ret < 0) {
+                        dev_err(dev, "fw %s: section #%zu (@%zu %zu B) "
+                                "failed %d\n", i2400m->bus_fw_name, section,
+                                offset, sizeof(*bh) + data_size, (int) ret);
+                        goto error_send;
+                }
+                offset += section_size;
+                section++;
+        }
+        ret = offset;
+error_section_beyond_eof:
+error_send:
+        d_fnend(3, dev, "(i2400m %p bcf %p bcf_len %zu) = %d\n",
+                i2400m, bcf, bcf_len, (int) ret);
+        return ret;
+}
+
+
+/*
+ * Do the final steps of uploading firmware
+ *
+ * Depending on the boot mode (signed vs non-signed), different
+ * actions need to be taken.
+ */
+static
+int i2400m_dnload_finalize(struct i2400m *i2400m,
+                           const struct i2400m_bcf_hdr *bcf, size_t offset)
+{
+        int ret = 0;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_bootrom_header *cmd, ack;
+        struct {
+                struct i2400m_bootrom_header cmd;
+                u8 cmd_pl[0];
+        } __attribute__((packed)) *cmd_buf;
+        size_t signature_block_offset, signature_block_size;
+
+        d_fnstart(3, dev, "offset %zu\n", offset);
+        cmd = (void *) bcf + offset;
+        if (i2400m->sboot == 0) {
+                struct i2400m_bootrom_header jump_ack;
+                d_printf(3, dev, "unsecure boot, jumping to 0x%08x\n",
+                        le32_to_cpu(cmd->target_addr));
+                i2400m_brh_set_opcode(cmd, I2400M_BRH_JUMP);
+                cmd->data_size = 0;
+                ret = i2400m_bm_cmd(i2400m, cmd, sizeof(*cmd),
+                                    &jump_ack, sizeof(jump_ack), 0);
+        } else {
+                d_printf(3, dev, "secure boot, jumping to 0x%08x\n",
+                         le32_to_cpu(cmd->target_addr));
+                cmd_buf = i2400m->bm_cmd_buf;
+                memcpy(&cmd_buf->cmd, cmd, sizeof(*cmd));
+                signature_block_offset =
+                        sizeof(*bcf)
+                        + le32_to_cpu(bcf->key_size) * sizeof(u32)
+                        + le32_to_cpu(bcf->exponent_size) * sizeof(u32);
+                signature_block_size =
+                        le32_to_cpu(bcf->modulus_size) * sizeof(u32);
+                memcpy(cmd_buf->cmd_pl, (void *) bcf + signature_block_offset,
+                       signature_block_size);
+                ret = i2400m_bm_cmd(i2400m, &cmd_buf->cmd,
+                                    sizeof(cmd_buf->cmd) + signature_block_size,
+                                    &ack, sizeof(ack), I2400M_BM_CMD_RAW);
+        }
+        d_fnend(3, dev, "returning %d\n", ret);
+        return ret;
+}
+
+
+/**
+ * i2400m_bootrom_init - Reboots a powered device into boot mode
+ *
+ * @i2400m: device descriptor
+ * @flags:
+ *      I2400M_BRI_SOFT: a reboot notification has been seen
+ *          already, so don't wait for it.
+ *
+ *      I2400M_BRI_NO_REBOOT: Don't send a reboot command, but wait
+ *          for a reboot barker notification. This is a one shot; if
+ *          the state machine needs to send a reboot command it will.
+ *
+ * Returns:
+ *
+ *     < 0 errno code on error, 0 if ok.
+ *
+ *     i2400m->sboot set to 0 for unsecure boot process, 1 for secure
+ *     boot process.
+ *
+ * Description:
+ *
+ * Tries hard enough to put the device in boot-mode. There are two
+ * main phases to this:
+ *
+ * a. (1) send a reboot command and (2) get a reboot barker
+ * b. (1) ack the reboot sending a reboot barker and (2) getting an
+ *        ack barker in return
+ *
+ * We want to skip (a) in some cases [soft]. The state machine is
+ * horrible, but it is basically: on each phase, send what has to be
+ * sent (if any), wait for the answer and act on the answer. We might
+ * have to backtrack and retry, so we keep a max tries counter for
+ * that.
+ *
+ * If we get a timeout after sending a warm reset, we do it again.
+ */
+int i2400m_bootrom_init(struct i2400m *i2400m, enum i2400m_bri flags)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_bootrom_header *cmd;
+        struct i2400m_bootrom_header ack;
+        int count = I2400M_BOOT_RETRIES;
+        int ack_timeout_cnt = 1;
+
+        BUILD_BUG_ON(sizeof(*cmd) != sizeof(i2400m_NBOOT_BARKER));
+        BUILD_BUG_ON(sizeof(ack) != sizeof(i2400m_ACK_BARKER));
+
+        d_fnstart(4, dev, "(i2400m %p flags 0x%08x)\n", i2400m, flags);
+        result = -ENOMEM;
+        cmd = i2400m->bm_cmd_buf;
+        if (flags & I2400M_BRI_SOFT)
+                goto do_reboot_ack;
+do_reboot:
+        if (--count < 0)
+                goto error_timeout;
+        d_printf(4, dev, "device reboot: reboot command [%d # left]\n",
+                 count);
+        if ((flags & I2400M_BRI_NO_REBOOT) == 0)
+                i2400m->bus_reset(i2400m, I2400M_RT_WARM);
+        result = i2400m_bm_cmd(i2400m, NULL, 0, &ack, sizeof(ack),
+                               I2400M_BM_CMD_RAW);
+        flags &= ~I2400M_BRI_NO_REBOOT;
+        switch (result) {
+        case -ERESTARTSYS:
+                d_printf(4, dev, "device reboot: got reboot barker\n");
+                break;
+        case -EISCONN:  /* we don't know how it got here...but we follow it */
+                d_printf(4, dev, "device reboot: got ack barker - whatever\n");
+                goto do_reboot;
+        case -ETIMEDOUT:        /* device has timed out, we might be in boot
+                                 * mode already and expecting an ack, let's try
+                                 * that */
+                dev_info(dev, "warm reset timed out, trying an ack\n");
+                goto do_reboot_ack;
+        case -EPROTO:
+        case -ESHUTDOWN:        /* dev is gone */
+        case -EINTR:            /* user cancelled */
+                goto error_dev_gone;
+        default:
+                dev_err(dev, "device reboot: error %d while waiting "
+                        "for reboot barker - rebooting\n", result);
+                goto do_reboot;
+        }
+        /* At this point we ack back with 4 REBOOT barkers and expect
+         * 4 ACK barkers. This is ugly, as we send a raw command --
+         * hence the cast. _bm_cmd() will catch the reboot ack
+         * notification and report it as -EISCONN. */
+do_reboot_ack:
+        d_printf(4, dev, "device reboot ack: sending ack [%d # left]\n", count);
+        if (i2400m->sboot == 0)
+                memcpy(cmd, i2400m_NBOOT_BARKER,
+                       sizeof(i2400m_NBOOT_BARKER));
+        else
+                memcpy(cmd, i2400m_SBOOT_BARKER,
+                       sizeof(i2400m_SBOOT_BARKER));
+        result = i2400m_bm_cmd(i2400m, cmd, sizeof(*cmd),
+                               &ack, sizeof(ack), I2400M_BM_CMD_RAW);
+        switch (result) {
+        case -ERESTARTSYS:
+                d_printf(4, dev, "reboot ack: got reboot barker - retrying\n");
+                if (--count < 0)
+                        goto error_timeout;
+                goto do_reboot_ack;
+        case -EISCONN:
+                d_printf(4, dev, "reboot ack: got ack barker - good\n");
+                break;
+        case -ETIMEDOUT:        /* no response, maybe it is the other type? */
+                if (ack_timeout_cnt-- >= 0) {
+                        d_printf(4, dev, "reboot ack timedout: "
+                                 "trying the other type?\n");
+                        i2400m->sboot = !i2400m->sboot;
+                        goto do_reboot_ack;
+                } else {
+                        dev_err(dev, "reboot ack timedout too long: "
+                                "trying reboot\n");
+                        goto do_reboot;
+                }
+                break;
+        case -EPROTO:
+        case -ESHUTDOWN:        /* dev is gone */
+                goto error_dev_gone;
+        default:
+                dev_err(dev, "device reboot ack: error %d while waiting for "
+                        "reboot ack barker - rebooting\n", result);
+                goto do_reboot;
+        }
+        d_printf(2, dev, "device reboot ack: got ack barker - boot done\n");
+        result = 0;
+exit_timeout:
+error_dev_gone:
+        d_fnend(4, dev, "(i2400m %p flags 0x%08x) = %d\n",
+                i2400m, flags, result);
+        return result;
+
+error_timeout:
+        dev_err(dev, "Timed out waiting for reboot ack, resetting\n");
+        i2400m->bus_reset(i2400m, I2400M_RT_BUS);
+        result = -ETIMEDOUT;
+        goto exit_timeout;
+}
+
+
+/*
+ * Read the MAC addr
+ *
+ * The position this function reads is fixed in device memory and
+ * always available, even without firmware.
+ *
+ * Note we specify we want to read only six bytes, but provide space
+ * for 16, as we always get it rounded up.
+ */
+int i2400m_read_mac_addr(struct i2400m *i2400m)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+        struct i2400m_bootrom_header *cmd;
+        struct {
+                struct i2400m_bootrom_header ack;
+                u8 ack_pl[16];
+        } __attribute__((packed)) ack_buf;
+
+        d_fnstart(5, dev, "(i2400m %p)\n", i2400m);
+        cmd = i2400m->bm_cmd_buf;
+        cmd->command = i2400m_brh_command(I2400M_BRH_READ, 0, 1);
+        cmd->target_addr = cpu_to_le32(0x00203fe8);
+        cmd->data_size = cpu_to_le32(6);
+        result = i2400m_bm_cmd(i2400m, cmd, sizeof(*cmd),
+                               &ack_buf.ack, sizeof(ack_buf), 0);
+        if (result < 0) {
+                dev_err(dev, "BM: read mac addr failed: %d\n", result);
+                goto error_read_mac;
+        }
+        d_printf(2, dev,
+                 "mac addr is %02x:%02x:%02x:%02x:%02x:%02x\n",
+                 ack_buf.ack_pl[0], ack_buf.ack_pl[1],
+                 ack_buf.ack_pl[2], ack_buf.ack_pl[3],
+                 ack_buf.ack_pl[4], ack_buf.ack_pl[5]);
+        if (i2400m->bus_bm_mac_addr_impaired == 1) {
+                ack_buf.ack_pl[0] = 0x00;
+                ack_buf.ack_pl[1] = 0x16;
+                ack_buf.ack_pl[2] = 0xd3;
+                get_random_bytes(&ack_buf.ack_pl[3], 3);
+                dev_err(dev, "BM is MAC addr impaired, faking MAC addr to "
+                        "mac addr is %02x:%02x:%02x:%02x:%02x:%02x\n",
+                        ack_buf.ack_pl[0], ack_buf.ack_pl[1],
+                        ack_buf.ack_pl[2], ack_buf.ack_pl[3],
+                        ack_buf.ack_pl[4], ack_buf.ack_pl[5]);
+                result = 0;
+        }
+        net_dev->addr_len = ETH_ALEN;
+        memcpy(net_dev->perm_addr, ack_buf.ack_pl, ETH_ALEN);
+        memcpy(net_dev->dev_addr, ack_buf.ack_pl, ETH_ALEN);
+error_read_mac:
+        d_fnend(5, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+}
+
+
+/*
+ * Initialize a non signed boot
+ *
+ * This implies sending some magic values to the device's memory. Note
+ * we convert the values to little endian in the same array
+ * declaration.
+ */
+static
+int i2400m_dnload_init_nonsigned(struct i2400m *i2400m)
+{
+#define POKE(a, d) {                                    \
+        .address = __constant_cpu_to_le32(a),           \
+        .data = __constant_cpu_to_le32(d)               \
+}
+        static const struct {
+                __le32 address;
+                __le32 data;
+        } i2400m_pokes[] = {
+                POKE(0x081A58, 0xA7810230),
+                POKE(0x080040, 0x00000000),
+                POKE(0x080048, 0x00000082),
+                POKE(0x08004C, 0x0000081F),
+                POKE(0x080054, 0x00000085),
+                POKE(0x080058, 0x00000180),
+                POKE(0x08005C, 0x00000018),
+                POKE(0x080060, 0x00000010),
+                POKE(0x080574, 0x00000001),
+                POKE(0x080550, 0x00000005),
+                POKE(0xAE0000, 0x00000000),
+        };
+#undef POKE
+        unsigned i;
+        int ret;
+        struct device *dev = i2400m_dev(i2400m);
+
+        dev_warn(dev, "WARNING!!! non-signed boot UNTESTED PATH!\n");
+
+        d_fnstart(5, dev, "(i2400m %p)\n", i2400m);
+        for (i = 0; i < ARRAY_SIZE(i2400m_pokes); i++) {
+                ret = i2400m_download_chunk(i2400m, &i2400m_pokes[i].data,
+                                            sizeof(i2400m_pokes[i].data),
+                                            i2400m_pokes[i].address, 1, 1);
+                if (ret < 0)
+                        break;
+        }
+        d_fnend(5, dev, "(i2400m %p) = %d\n", i2400m, ret);
+        return ret;
+}
+
+
+/*
+ * Initialize the signed boot process
+ *
+ * @i2400m: device descriptor
+ *
+ * @bcf_hdr: pointer to the firmware header; assumes it is fully in
+ *     memory (it has gone through basic validation).
+ *
+ * Returns: 0 if ok, < 0 errno code on error, -ERESTARTSYS if the hw
+ *     rebooted.
+ *
+ * This writes the firmware BCF header to the device using the
+ * HASH_PAYLOAD_ONLY command.
+ */
+static
+int i2400m_dnload_init_signed(struct i2400m *i2400m,
+                              const struct i2400m_bcf_hdr *bcf_hdr)
+{
+        int ret;
+        struct device *dev = i2400m_dev(i2400m);
+        struct {
+                struct i2400m_bootrom_header cmd;
+                struct i2400m_bcf_hdr cmd_pl;
+        } __attribute__((packed)) *cmd_buf;
+        struct i2400m_bootrom_header ack;
+
+        d_fnstart(5, dev, "(i2400m %p bcf_hdr %p)\n", i2400m, bcf_hdr);
+        cmd_buf = i2400m->bm_cmd_buf;
+        cmd_buf->cmd.command =
+                i2400m_brh_command(I2400M_BRH_HASH_PAYLOAD_ONLY, 0, 0);
+        cmd_buf->cmd.target_addr = 0;
+        cmd_buf->cmd.data_size = cpu_to_le32(sizeof(cmd_buf->cmd_pl));
+        memcpy(&cmd_buf->cmd_pl, bcf_hdr, sizeof(*bcf_hdr));
+        ret = i2400m_bm_cmd(i2400m, &cmd_buf->cmd, sizeof(*cmd_buf),
+                            &ack, sizeof(ack), 0);
+        if (ret >= 0)
+                ret = 0;
+        d_fnend(5, dev, "(i2400m %p bcf_hdr %p) = %d\n", i2400m, bcf_hdr, ret);
+        return ret;
+}
+
+
+/*
+ * Initialize the firmware download at the device size
+ *
+ * Multiplex to the one that matters based on the device's mode
+ * (signed or non-signed).
+ */
+static
+int i2400m_dnload_init(struct i2400m *i2400m, const struct i2400m_bcf_hdr *bcf)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        u32 module_id = le32_to_cpu(bcf->module_id);
+
+        if (i2400m->sboot == 0
+            && (module_id & I2400M_BCF_MOD_ID_POKES) == 0) {
+                /* non-signed boot process without pokes */
+                result = i2400m_dnload_init_nonsigned(i2400m);
+                if (result == -ERESTARTSYS)
+                        return result;
+                if (result < 0)
+                        dev_err(dev, "fw %s: non-signed download "
+                                "initialization failed: %d\n",
+                                i2400m->bus_fw_name, result);
+        } else if (i2400m->sboot == 0
+                 && (module_id & I2400M_BCF_MOD_ID_POKES)) {
+                /* non-signed boot process with pokes, nothing to do */
+                result = 0;
+        } else {                 /* signed boot process */
+                result = i2400m_dnload_init_signed(i2400m, bcf);
+                if (result == -ERESTARTSYS)
+                        return result;
+                if (result < 0)
+                        dev_err(dev, "fw %s: signed boot download "
+                                "initialization failed: %d\n",
+                                i2400m->bus_fw_name, result);
+        }
+        return result;
+}
+
+
+/*
+ * Run quick consistency tests on the firmware file
+ *
+ * Check for the firmware being made for the i2400m device,
+ * etc...These checks are mostly informative, as the device will make
+ * them too; but the driver's response is more informative on what
+ * went wrong.
+ */
+static
+int i2400m_fw_check(struct i2400m *i2400m,
+                    const struct i2400m_bcf_hdr *bcf,
+                    size_t bcf_size)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        unsigned module_type, header_len, major_version, minor_version,
+                module_id, module_vendor, date, size;
+
+        /* Check hard errors */
+        result = -EINVAL;
+        if (bcf_size < sizeof(*bcf)) {  /* big enough header? */
+                dev_err(dev, "firmware %s too short: "
+                        "%zu B vs %zu (at least) expected\n",
+                        i2400m->bus_fw_name, bcf_size, sizeof(*bcf));
+                goto error;
+        }
+
+        module_type = bcf->module_type;
+        header_len = sizeof(u32) * le32_to_cpu(bcf->header_len);
+        major_version = le32_to_cpu(bcf->header_version) & 0xffff0000 >> 16;
+        minor_version = le32_to_cpu(bcf->header_version) & 0x0000ffff;
+        module_id = le32_to_cpu(bcf->module_id);
+        module_vendor = le32_to_cpu(bcf->module_vendor);
+        date = le32_to_cpu(bcf->date);
+        size = sizeof(u32) * le32_to_cpu(bcf->size);
+
+        if (bcf_size != size) {         /* annoyingly paranoid */
+                dev_err(dev, "firmware %s: bad size, got "
+                        "%zu B vs %u expected\n",
+                        i2400m->bus_fw_name, bcf_size, size);
+                goto error;
+        }
+
+        d_printf(2, dev, "type 0x%x id 0x%x vendor 0x%x; header v%u.%u (%zu B) "
+                 "date %08x (%zu B)\n",
+                 module_type, module_id, module_vendor,
+                 major_version, minor_version, (size_t) header_len,
+                 date, (size_t) size);
+
+        if (module_type != 6) {         /* built for the right hardware? */
+                dev_err(dev, "bad fw %s: unexpected module type 0x%x; "
+                        "aborting\n", i2400m->bus_fw_name, module_type);
+                goto error;
+        }
+
+        /* Check soft-er errors */
+        result = 0;
+        if (module_vendor != 0x8086)
+                dev_err(dev, "bad fw %s? unexpected vendor 0x%04x\n",
+                        i2400m->bus_fw_name, module_vendor);
+        if (date < 0x20080300)
+                dev_err(dev, "bad fw %s? build date too old %08x\n",
+                        i2400m->bus_fw_name, date);
+error:
+        return result;
+}
+
+
+/*
+ * Download the firmware to the device
+ *
+ * @i2400m: device descriptor
+ * @bcf: pointer to loaded (and minimally verified for consistency)
+ *    firmware
+ * @bcf_size: size of the @bcf buffer (header plus payloads)
+ *
+ * The process for doing this is described in this file's header.
+ *
+ * Note we only reinitialize boot-mode if the flags say so. Some hw
+ * iterations need it, some don't. In any case, if we loop, we always
+ * need to reinitialize the boot room, hence the flags modification.
+ */
+static
+int i2400m_fw_dnload(struct i2400m *i2400m, const struct i2400m_bcf_hdr *bcf,
+                     size_t bcf_size, enum i2400m_bri flags)
+{
+        int ret = 0;
+        struct device *dev = i2400m_dev(i2400m);
+        int count = I2400M_BOOT_RETRIES;
+
+        d_fnstart(5, dev, "(i2400m %p bcf %p size %zu)\n",
+                  i2400m, bcf, bcf_size);
+        i2400m->boot_mode = 1;
+hw_reboot:
+        if (count-- == 0) {
+                ret = -ERESTARTSYS;
+                dev_err(dev, "device rebooted too many times, aborting\n");
+                goto error_too_many_reboots;
+        }
+        if (flags & I2400M_BRI_MAC_REINIT) {
+                ret = i2400m_bootrom_init(i2400m, flags);
+                if (ret < 0) {
+                        dev_err(dev, "bootrom init failed: %d\n", ret);
+                        goto error_bootrom_init;
+                }
+        }
+        flags |= I2400M_BRI_MAC_REINIT;
+
+        /*
+         * Initialize the download, push the bytes to the device and
+         * then jump to the new firmware. Note @ret is passed with the
+         * offset of the jump instruction to _dnload_finalize()
+         */
+        ret = i2400m_dnload_init(i2400m, bcf);  /* Init device's dnload */
+        if (ret == -ERESTARTSYS)
+                goto error_dev_rebooted;
+        if (ret < 0)
+                goto error_dnload_init;
+
+        ret = i2400m_dnload_bcf(i2400m, bcf, bcf_size);
+        if (ret == -ERESTARTSYS)
+                goto error_dev_rebooted;
+        if (ret < 0) {
+                dev_err(dev, "fw %s: download failed: %d\n",
+                        i2400m->bus_fw_name, ret);
+                goto error_dnload_bcf;
+        }
+
+        ret = i2400m_dnload_finalize(i2400m, bcf, ret);
+        if (ret == -ERESTARTSYS)
+                goto error_dev_rebooted;
+        if (ret < 0) {
+                dev_err(dev, "fw %s: "
+                        "download finalization failed: %d\n",
+                        i2400m->bus_fw_name, ret);
+                goto error_dnload_finalize;
+        }
+
+        d_printf(2, dev, "fw %s successfully uploaded\n",
+                 i2400m->bus_fw_name);
+        i2400m->boot_mode = 0;
+error_dnload_finalize:
+error_dnload_bcf:
+error_dnload_init:
+error_bootrom_init:
+error_too_many_reboots:
+        d_fnend(5, dev, "(i2400m %p bcf %p size %zu) = %d\n",
+                i2400m, bcf, bcf_size, ret);
+        return ret;
+
+error_dev_rebooted:
+        dev_err(dev, "device rebooted, %d tries left\n", count);
+        /* we got the notification already, no need to wait for it again */
+        flags |= I2400M_BRI_SOFT;
+        goto hw_reboot;
+}
+
+
+/**
+ * i2400m_dev_bootstrap - Bring the device to a known state and upload firmware
+ *
+ * @i2400m: device descriptor
+ *
+ * Returns: >= 0 if ok, < 0 errno code on error.
+ *
+ * This sets up the firmware upload environment, loads the firmware
+ * file from disk, verifies and then calls the firmware upload process
+ * per se.
+ *
+ * Can be called either from probe, or after a warm reset.  Can not be
+ * called from within an interrupt.  All the flow in this code is
+ * single-threade; all I/Os are synchronous.
+ */
+int i2400m_dev_bootstrap(struct i2400m *i2400m, enum i2400m_bri flags)
+{
+        int ret = 0;
+        struct device *dev = i2400m_dev(i2400m);
+        const struct firmware *fw;
+        const struct i2400m_bcf_hdr *bcf;       /* Firmware data */
+
+        d_fnstart(5, dev, "(i2400m %p)\n", i2400m);
+        /* Load firmware files to memory. */
+        ret = request_firmware(&fw, i2400m->bus_fw_name, dev);
+        if (ret) {
+                dev_err(dev, "fw %s: request failed: %d\n",
+                        i2400m->bus_fw_name, ret);
+                goto error_fw_req;
+        }
+        bcf = (void *) fw->data;
+
+        ret = i2400m_fw_check(i2400m, bcf, fw->size);
+        if (ret < 0)
+                goto error_fw_bad;
+        ret = i2400m_fw_dnload(i2400m, bcf, fw->size, flags);
+error_fw_bad:
+        release_firmware(fw);
+error_fw_req:
+        d_fnend(5, dev, "(i2400m %p) = %d\n", i2400m, ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(i2400m_dev_bootstrap);
diff --git a/drivers/net/wimax/i2400m/i2400m-sdio.h b/drivers/net/wimax/i2400m/i2400m-sdio.h
new file mode 100644
index 000000000000..08c2fb739234
--- /dev/null
+++ b/drivers/net/wimax/i2400m/i2400m-sdio.h
@@ -0,0 +1,132 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * SDIO-specific i2400m driver definitions
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Brian Bian <brian.bian@intel.com>
+ * Dirk Brandewie <dirk.j.brandewie@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * This driver implements the bus-specific part of the i2400m for
+ * SDIO. Check i2400m.h for a generic driver description.
+ *
+ * ARCHITECTURE
+ *
+ * This driver sits under the bus-generic i2400m driver, providing the
+ * connection to the device.
+ *
+ * When probed, all the function pointers are setup and then the
+ * bus-generic code called. The generic driver will then use the
+ * provided pointers for uploading firmware (i2400ms_bus_bm*() in
+ * sdio-fw.c) and then setting up the device (i2400ms_dev_*() in
+ * sdio.c).
+ *
+ * Once firmware is uploaded, TX functions (sdio-tx.c) are called when
+ * data is ready for transmission in the TX fifo; then the SDIO IRQ is
+ * fired and data is available (sdio-rx.c), it is sent to the generic
+ * driver for processing with i2400m_rx.
+ */
+
+#ifndef __I2400M_SDIO_H__
+#define __I2400M_SDIO_H__
+
+#include "i2400m.h"
+
+/* Host-Device interface for SDIO */
+enum {
+        I2400MS_BLK_SIZE = 256,
+        I2400MS_PL_SIZE_MAX = 0x3E00,
+
+        I2400MS_DATA_ADDR = 0x0,
+        I2400MS_INTR_STATUS_ADDR = 0x13,
+        I2400MS_INTR_CLEAR_ADDR = 0x13,
+        I2400MS_INTR_ENABLE_ADDR = 0x14,
+        I2400MS_INTR_GET_SIZE_ADDR = 0x2C,
+        /* The number of ticks to wait for the device to signal that
+         * it is ready */
+        I2400MS_INIT_SLEEP_INTERVAL = 10,
+};
+
+
+/**
+ * struct i2400ms - descriptor for a SDIO connected i2400m
+ *
+ * @i2400m: bus-generic i2400m implementation; has to be first (see
+ *     it's documentation in i2400m.h).
+ *
+ * @func: pointer to our SDIO function
+ *
+ * @tx_worker: workqueue struct used to TX data when the bus-generic
+ *     code signals packets are pending for transmission to the device.
+ *
+ * @tx_workqueue: workqeueue used for data TX; we don't use the
+ *     system's workqueue as that might cause deadlocks with code in
+ *     the bus-generic driver.
+ */
+struct i2400ms {
+        struct i2400m i2400m;           /* FIRST! See doc */
+        struct sdio_func *func;
+
+        struct work_struct tx_worker;
+        struct workqueue_struct *tx_workqueue;
+        char tx_wq_name[32];
+
+        struct dentry *debugfs_dentry;
+};
+
+
+static inline
+void i2400ms_init(struct i2400ms *i2400ms)
+{
+        i2400m_init(&i2400ms->i2400m);
+}
+
+
+extern int i2400ms_rx_setup(struct i2400ms *);
+extern void i2400ms_rx_release(struct i2400ms *);
+extern ssize_t __i2400ms_rx_get_size(struct i2400ms *);
+
+extern int i2400ms_tx_setup(struct i2400ms *);
+extern void i2400ms_tx_release(struct i2400ms *);
+extern void i2400ms_bus_tx_kick(struct i2400m *);
+
+extern ssize_t i2400ms_bus_bm_cmd_send(struct i2400m *,
+                                       const struct i2400m_bootrom_header *,
+                                       size_t, int);
+extern ssize_t i2400ms_bus_bm_wait_for_ack(struct i2400m *,
+                                           struct i2400m_bootrom_header *,
+                                           size_t);
+#endif /* #ifndef __I2400M_SDIO_H__ */
diff --git a/drivers/net/wimax/i2400m/i2400m-usb.h b/drivers/net/wimax/i2400m/i2400m-usb.h
new file mode 100644
index 000000000000..6f76558b170f
--- /dev/null
+++ b/drivers/net/wimax/i2400m/i2400m-usb.h
@@ -0,0 +1,264 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * USB-specific i2400m driver definitions
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * This driver implements the bus-specific part of the i2400m for
+ * USB. Check i2400m.h for a generic driver description.
+ *
+ * ARCHITECTURE
+ *
+ * This driver listens to notifications sent from the notification
+ * endpoint (in usb-notif.c); when data is ready to read, the code in
+ * there schedules a read from the device (usb-rx.c) and then passes
+ * the data to the generic RX code (rx.c).
+ *
+ * When the generic driver needs to send data (network or control), it
+ * queues up in the TX FIFO (tx.c) and that will notify the driver
+ * through the i2400m->bus_tx_kick() callback
+ * (usb-tx.c:i2400mu_bus_tx_kick) which will send the items in the
+ * FIFO queue.
+ *
+ * This driver, as well, implements the USB-specific ops for the generic
+ * driver to be able to setup/teardown communication with the device
+ * [i2400m_bus_dev_start() and i2400m_bus_dev_stop()], reseting the
+ * device [i2400m_bus_reset()] and performing firmware upload
+ * [i2400m_bus_bm_cmd() and i2400_bus_bm_wait_for_ack()].
+ */
+
+#ifndef __I2400M_USB_H__
+#define __I2400M_USB_H__
+
+#include "i2400m.h"
+#include <linux/kthread.h>
+
+
+/*
+ * Error Density Count: cheapo error density (over time) counter
+ *
+ * Originally by Reinette Chatre <reinette.chatre@intel.com>
+ *
+ * Embed an 'struct edc' somewhere. Each time there is a soft or
+ * retryable error, call edc_inc() and check if the error top
+ * watermark has been reached.
+ */
+enum {
+        EDC_MAX_ERRORS = 10,
+        EDC_ERROR_TIMEFRAME = HZ,
+};
+
+/* error density counter */
+struct edc {
+        unsigned long timestart;
+        u16 errorcount;
+};
+
+static inline void edc_init(struct edc *edc)
+{
+        edc->timestart = jiffies;
+}
+
+/**
+ * edc_inc - report a soft error and check if we are over the watermark
+ *
+ * @edc: pointer to error density counter.
+ * @max_err: maximum number of errors we can accept over the timeframe
+ * @timeframe: lenght of the timeframe (in jiffies).
+ *
+ * Returns: !0 1 if maximum acceptable errors per timeframe has been
+ *     exceeded. 0 otherwise.
+ *
+ * This is way to determine if the number of acceptable errors per time
+ * period has been exceeded. It is not accurate as there are cases in which
+ * this scheme will not work, for example if there are periodic occurences
+ * of errors that straddle updates to the start time. This scheme is
+ * sufficient for our usage.
+ *
+ * To use, embed a 'struct edc' somewhere, initialize it with
+ * edc_init() and when an error hits:
+ *
+ * if (do_something_fails_with_a_soft_error) {
+ *        if (edc_inc(&my->edc, MAX_ERRORS, MAX_TIMEFRAME))
+ *                 Ops, hard error, do something about it
+ *        else
+ *                 Retry or ignore, depending on whatever
+ * }
+ */
+static inline int edc_inc(struct edc *edc, u16 max_err, u16 timeframe)
+{
+        unsigned long now;
+
+        now = jiffies;
+        if (now - edc->timestart > timeframe) {
+                edc->errorcount = 1;
+                edc->timestart = now;
+        } else if (++edc->errorcount > max_err) {
+                edc->errorcount = 0;
+                edc->timestart = now;
+                return 1;
+        }
+        return 0;
+}
+
+/* Host-Device interface for USB */
+enum {
+        I2400MU_MAX_NOTIFICATION_LEN = 256,
+        I2400MU_BLK_SIZE = 16,
+        I2400MU_PL_SIZE_MAX = 0x3EFF,
+
+        /* Endpoints */
+        I2400MU_EP_BULK_OUT = 0,
+        I2400MU_EP_NOTIFICATION,
+        I2400MU_EP_RESET_COLD,
+        I2400MU_EP_BULK_IN,
+};
+
+
+/**
+ * struct i2400mu - descriptor for a USB connected i2400m
+ *
+ * @i2400m: bus-generic i2400m implementation; has to be first (see
+ *     it's documentation in i2400m.h).
+ *
+ * @usb_dev: pointer to our USB device
+ *
+ * @usb_iface: pointer to our USB interface
+ *
+ * @urb_edc: error density counter; used to keep a density-on-time tab
+ *     on how many soft (retryable or ignorable) errors we get. If we
+ *     go over the threshold, we consider the bus transport is failing
+ *     too much and reset.
+ *
+ * @notif_urb: URB for receiving notifications from the device.
+ *
+ * @tx_kthread: thread we use for data TX. We use a thread because in
+ *     order to do deep power saving and put the device to sleep, we
+ *     need to call usb_autopm_*() [blocking functions].
+ *
+ * @tx_wq: waitqueue for the TX kthread to sleep when there is no data
+ *     to be sent; when more data is available, it is woken up by
+ *     i2400mu_bus_tx_kick().
+ *
+ * @rx_kthread: thread we use for data RX. We use a thread because in
+ *     order to do deep power saving and put the device to sleep, we
+ *     need to call usb_autopm_*() [blocking functions].
+ *
+ * @rx_wq: waitqueue for the RX kthread to sleep when there is no data
+ *     to receive. When data is available, it is woken up by
+ *     usb-notif.c:i2400mu_notification_grok().
+ *
+ * @rx_pending_count: number of rx-data-ready notifications that were
+ *     still not handled by the RX kthread.
+ *
+ * @rx_size: current RX buffer size that is being used.
+ *
+ * @rx_size_acc: accumulator of the sizes of the previous read
+ *     transactions.
+ *
+ * @rx_size_cnt: number of read transactions accumulated in
+ *     @rx_size_acc.
+ *
+ * @do_autopm: disable(0)/enable(>0) calling the
+ *     usb_autopm_get/put_interface() barriers when executing
+ *     commands. See doc in i2400mu_suspend() for more information.
+ *
+ * @rx_size_auto_shrink: if true, the rx_size is shrinked
+ *     automatically based on the average size of the received
+ *     transactions. This allows the receive code to allocate smaller
+ *     chunks of memory and thus reduce pressure on the memory
+ *     allocator by not wasting so much space. By default it is
+ *     enabled.
+ *
+ * @debugfs_dentry: hookup for debugfs files.
+ *     These have to be in a separate directory, a child of
+ *     (wimax_dev->debugfs_dentry) so they can be removed when the
+ *     module unloads, as we don't keep each dentry.
+ */
+struct i2400mu {
+        struct i2400m i2400m;           /* FIRST! See doc */
+
+        struct usb_device *usb_dev;
+        struct usb_interface *usb_iface;
+        struct edc urb_edc;             /* Error density counter */
+
+        struct urb *notif_urb;
+        struct task_struct *tx_kthread;
+        wait_queue_head_t tx_wq;
+
+        struct task_struct *rx_kthread;
+        wait_queue_head_t rx_wq;
+        atomic_t rx_pending_count;
+        size_t rx_size, rx_size_acc, rx_size_cnt;
+        atomic_t do_autopm;
+        u8 rx_size_auto_shrink;
+
+        struct dentry *debugfs_dentry;
+};
+
+
+static inline
+void i2400mu_init(struct i2400mu *i2400mu)
+{
+        i2400m_init(&i2400mu->i2400m);
+        edc_init(&i2400mu->urb_edc);
+        init_waitqueue_head(&i2400mu->tx_wq);
+        atomic_set(&i2400mu->rx_pending_count, 0);
+        init_waitqueue_head(&i2400mu->rx_wq);
+        i2400mu->rx_size = PAGE_SIZE - sizeof(struct skb_shared_info);
+        atomic_set(&i2400mu->do_autopm, 1);
+        i2400mu->rx_size_auto_shrink = 1;
+}
+
+extern int i2400mu_notification_setup(struct i2400mu *);
+extern void i2400mu_notification_release(struct i2400mu *);
+
+extern int i2400mu_rx_setup(struct i2400mu *);
+extern void i2400mu_rx_release(struct i2400mu *);
+extern void i2400mu_rx_kick(struct i2400mu *);
+
+extern int i2400mu_tx_setup(struct i2400mu *);
+extern void i2400mu_tx_release(struct i2400mu *);
+extern void i2400mu_bus_tx_kick(struct i2400m *);
+
+extern ssize_t i2400mu_bus_bm_cmd_send(struct i2400m *,
+                                       const struct i2400m_bootrom_header *,
+                                       size_t, int);
+extern ssize_t i2400mu_bus_bm_wait_for_ack(struct i2400m *,
+                                           struct i2400m_bootrom_header *,
+                                           size_t);
+#endif /* #ifndef __I2400M_USB_H__ */
diff --git a/drivers/net/wimax/i2400m/i2400m.h b/drivers/net/wimax/i2400m/i2400m.h
new file mode 100644
index 000000000000..067c871cc226
--- /dev/null
+++ b/drivers/net/wimax/i2400m/i2400m.h
@@ -0,0 +1,755 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Declarations for bus-generic internal APIs
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * GENERAL DRIVER ARCHITECTURE
+ *
+ * The i2400m driver is split in the following two major parts:
+ *
+ *  - bus specific driver
+ *  - bus generic driver (this part)
+ *
+ * The bus specific driver sets up stuff specific to the bus the
+ * device is connected to (USB, SDIO, PCI, tam-tam...non-authoritative
+ * nor binding list) which is basically the device-model management
+ * (probe/disconnect, etc), moving data from device to kernel and
+ * back, doing the power saving details and reseting the device.
+ *
+ * For details on each bus-specific driver, see it's include file,
+ * i2400m-BUSNAME.h
+ *
+ * The bus-generic functionality break up is:
+ *
+ *  - Firmware upload: fw.c - takes care of uploading firmware to the
+ *        device. bus-specific driver just needs to provides a way to
+ *        execute boot-mode commands and to reset the device.
+ *
+ *  - RX handling: rx.c - receives data from the bus-specific code and
+ *        feeds it to the network or WiMAX stack or uses it to modify
+ *        the driver state. bus-specific driver only has to receive
+ *        frames and pass them to this module.
+ *
+ *  - TX handling: tx.c - manages the TX FIFO queue and provides means
+ *        for the bus-specific TX code to pull data from the FIFO
+ *        queue. bus-specific code just pulls frames from this module
+ *        to sends them to the device.
+ *
+ *  - netdev glue: netdev.c - interface with Linux networking
+ *        stack. Pass around data frames, and configure when the
+ *        device is up and running or shutdown (through ifconfig up /
+ *        down). Bus-generic only.
+ *
+ *  - control ops: control.c - implements various commmands for
+ *        controlling the device. bus-generic only.
+ *
+ *  - device model glue: driver.c - implements helpers for the
+ *        device-model glue done by the bus-specific layer
+ *        (setup/release the driver resources), turning the device on
+ *        and off, handling the device reboots/resets and a few simple
+ *        WiMAX stack ops.
+ *
+ * Code is also broken up in linux-glue / device-glue.
+ *
+ * Linux glue contains functions that deal mostly with gluing with the
+ * rest of the Linux kernel.
+ *
+ * Device-glue are functions that deal mostly with the way the device
+ * does things and talk the device's language.
+ *
+ * device-glue code is licensed BSD so other open source OSes can take
+ * it to implement their drivers.
+ *
+ *
+ * APIs AND HEADER FILES
+ *
+ * This bus generic code exports three APIs:
+ *
+ *  - HDI (host-device interface) definitions common to all busses
+ *    (include/linux/wimax/i2400m.h); these can be also used by user
+ *    space code.
+ *  - internal API for the bus-generic code
+ *  - external API for the bus-specific drivers
+ *
+ *
+ * LIFE CYCLE:
+ *
+ * When the bus-specific driver probes, it allocates a network device
+ * with enough space for it's data structue, that must contain a
+ * &struct i2400m at the top.
+ *
+ * On probe, it needs to fill the i2400m members marked as [fill], as
+ * well as i2400m->wimax_dev.net_dev and call i2400m_setup(). The
+ * i2400m driver will only register with the WiMAX and network stacks;
+ * the only access done to the device is to read the MAC address so we
+ * can register a network device. This calls i2400m_dev_start() to
+ * load firmware, setup communication with the device and configure it
+ * for operation.
+ *
+ * At this point, control and data communications are possible.
+ *
+ * On disconnect/driver unload, the bus-specific disconnect function
+ * calls i2400m_release() to undo i2400m_setup(). i2400m_dev_stop()
+ * shuts the firmware down and releases resources uses to communicate
+ * with the device.
+ *
+ * While the device is up, it might reset. The bus-specific driver has
+ * to catch that situation and call i2400m_dev_reset_handle() to deal
+ * with it (reset the internal driver structures and go back to square
+ * one).
+ */
+
+#ifndef __I2400M_H__
+#define __I2400M_H__
+
+#include <linux/usb.h>
+#include <linux/netdevice.h>
+#include <linux/completion.h>
+#include <linux/rwsem.h>
+#include <asm/atomic.h>
+#include <net/wimax.h>
+#include <linux/wimax/i2400m.h>
+#include <asm/byteorder.h>
+
+/* Misc constants */
+enum {
+        /* Firmware uploading */
+        I2400M_BOOT_RETRIES = 3,
+        /* Size of the Boot Mode Command buffer */
+        I2400M_BM_CMD_BUF_SIZE = 16 * 1024,
+        I2400M_BM_ACK_BUF_SIZE = 256,
+};
+
+
+/* Firmware version we request when pulling the fw image file */
+#define I2400M_FW_VERSION "1.3"
+
+
+/**
+ * i2400m_reset_type - methods to reset a device
+ *
+ * @I2400M_RT_WARM: Reset without device disconnection, device handles
+ *     are kept valid but state is back to power on, with firmware
+ *     re-uploaded.
+ * @I2400M_RT_COLD: Tell the device to disconnect itself from the bus
+ *     and reconnect. Renders all device handles invalid.
+ * @I2400M_RT_BUS: Tells the bus to reset the device; last measure
+ *     used when both types above don't work.
+ */
+enum i2400m_reset_type {
+        I2400M_RT_WARM, /* first measure */
+        I2400M_RT_COLD, /* second measure */
+        I2400M_RT_BUS,  /* call in artillery */
+};
+
+struct i2400m_reset_ctx;
+
+/**
+ * struct i2400m - descriptor for an Intel 2400m
+ *
+ * Members marked with [fill] must be filled out/initialized before
+ * calling i2400m_setup().
+ *
+ * @bus_tx_block_size: [fill] SDIO imposes a 256 block size, USB 16,
+ *     so we have a tx_blk_size variable that the bus layer sets to
+ *     tell the engine how much of that we need.
+ *
+ * @bus_pl_size_max: [fill] Maximum payload size.
+ *
+ * @bus_dev_start: [fill] Function called by the bus-generic code
+ *     [i2400m_dev_start()] to setup the bus-specific communications
+ *     to the the device. See LIFE CYCLE above.
+ *
+ *     NOTE: Doesn't need to upload the firmware, as that is taken
+ *     care of by the bus-generic code.
+ *
+ * @bus_dev_stop: [fill] Function called by the bus-generic code
+ *     [i2400m_dev_stop()] to shutdown the bus-specific communications
+ *     to the the device. See LIFE CYCLE above.
+ *
+ *     This function does not need to reset the device, just tear down
+ *     all the host resources created to  handle communication with
+ *     the device.
+ *
+ * @bus_tx_kick: [fill] Function called by the bus-generic code to let
+ *     the bus-specific code know that there is data available in the
+ *     TX FIFO for transmission to the device.
+ *
+ *     This function cannot sleep.
+ *
+ * @bus_reset: [fill] Function called by the bus-generic code to reset
+ *     the device in in various ways. Doesn't need to wait for the
+ *     reset to finish.
+ *
+ *     If warm or cold reset fail, this function is expected to do a
+ *     bus-specific reset (eg: USB reset) to get the device to a
+ *     working state (even if it implies device disconecction).
+ *
+ *     Note the warm reset is used by the firmware uploader to
+ *     reinitialize the device.
+ *
+ *     IMPORTANT: this is called very early in the device setup
+ *     process, so it cannot rely on common infrastructure being laid
+ *     out.
+ *
+ * @bus_bm_cmd_send: [fill] Function called to send a boot-mode
+ *     command. Flags are defined in 'enum i2400m_bm_cmd_flags'. This
+ *     is synchronous and has to return 0 if ok or < 0 errno code in
+ *     any error condition.
+ *
+ * @bus_bm_wait_for_ack: [fill] Function called to wait for a
+ *     boot-mode notification (that can be a response to a previously
+ *     issued command or an asynchronous one). Will read until all the
+ *     indicated size is read or timeout. Reading more or less data
+ *     than asked for is an error condition. Return 0 if ok, < 0 errno
+ *     code on error.
+ *
+ *     The caller to this function will check if the response is a
+ *     barker that indicates the device going into reset mode.
+ *
+ * @bus_fw_name: [fill] name of the firmware image (in most cases,
+ *     they are all the same for a single release, except that they
+ *     have the type of the bus embedded in the name (eg:
+ *     i2400m-fw-X-VERSION.sbcf, where X is the bus name).
+ *
+ * @bus_bm_mac_addr_impaired: [fill] Set to true if the device's MAC
+ *     address provided in boot mode is kind of broken and needs to
+ *     be re-read later on.
+ *
+ *
+ * @wimax_dev: WiMAX generic device for linkage into the kernel WiMAX
+ *     stack. Due to the way a net_device is allocated, we need to
+ *     force this to be the first field so that we can get from
+ *     netdev_priv() the right pointer.
+ *
+ * @state: device's state (as reported by it)
+ *
+ * @state_wq: waitqueue that is woken up whenever the state changes
+ *
+ * @tx_lock: spinlock to protect TX members
+ *
+ * @tx_buf: FIFO buffer for TX; we queue data here
+ *
+ * @tx_in: FIFO index for incoming data. Note this doesn't wrap around
+ *     and it is always greater than @tx_out.
+ *
+ * @tx_out: FIFO index for outgoing data
+ *
+ * @tx_msg: current TX message that is active in the FIFO for
+ *     appending payloads.
+ *
+ * @tx_sequence: current sequence number for TX messages from the
+ *     device to the host.
+ *
+ * @tx_msg_size: size of the current message being transmitted by the
+ *     bus-specific code.
+ *
+ * @tx_pl_num: total number of payloads sent
+ *
+ * @tx_pl_max: maximum number of payloads sent in a TX message
+ *
+ * @tx_pl_min: minimum number of payloads sent in a TX message
+ *
+ * @tx_num: number of TX messages sent
+ *
+ * @tx_size_acc: number of bytes in all TX messages sent
+ *     (this is different to net_dev's statistics as it also counts
+ *     control messages).
+ *
+ * @tx_size_min: smallest TX message sent.
+ *
+ * @tx_size_max: biggest TX message sent.
+ *
+ * @rx_lock: spinlock to protect RX members
+ *
+ * @rx_pl_num: total number of payloads received
+ *
+ * @rx_pl_max: maximum number of payloads received in a RX message
+ *
+ * @rx_pl_min: minimum number of payloads received in a RX message
+ *
+ * @rx_num: number of RX messages received
+ *
+ * @rx_size_acc: number of bytes in all RX messages received
+ *     (this is different to net_dev's statistics as it also counts
+ *     control messages).
+ *
+ * @rx_size_min: smallest RX message received.
+ *
+ * @rx_size_max: buggest RX message received.
+ *
+ * @init_mutex: Mutex used for serializing the device bringup
+ *     sequence; this way if the device reboots in the middle, we
+ *     don't try to do a bringup again while we are tearing down the
+ *     one that failed.
+ *
+ *     Can't reuse @msg_mutex because from within the bringup sequence
+ *     we need to send messages to the device and thus use @msg_mutex.
+ *
+ * @msg_mutex: mutex used to send control commands to the device (we
+ *     only allow one at a time, per host-device interface design).
+ *
+ * @msg_completion: used to wait for an ack to a control command sent
+ *     to the device.
+ *
+ * @ack_skb: used to store the actual ack to a control command if the
+ *     reception of the command was successful. Otherwise, a ERR_PTR()
+ *     errno code that indicates what failed with the ack reception.
+ *
+ *     Only valid after @msg_completion is woken up. Only updateable
+ *     if @msg_completion is armed. Only touched by
+ *     i2400m_msg_to_dev().
+ *
+ *     Protected by @rx_lock. In theory the command execution flow is
+ *     sequential, but in case the device sends an out-of-phase or
+ *     very delayed response, we need to avoid it trampling current
+ *     execution.
+ *
+ * @bm_cmd_buf: boot mode command buffer for composing firmware upload
+ *     commands.
+ *
+ *     USB can't r/w to stack, vmalloc, etc...as well, we end up
+ *     having to alloc/free a lot to compose commands, so we use these
+ *     for stagging and not having to realloc all the time.
+ *
+ *     This assumes the code always runs serialized. Only one thread
+ *     can call i2400m_bm_cmd() at the same time.
+ *
+ * @bm_ack_buf: boot mode acknoledge buffer for staging reception of
+ *     responses to commands.
+ *
+ *     See @bm_cmd_buf.
+ *
+ * @work_queue: work queue for processing device reports. This
+ *     workqueue cannot be used for processing TX or RX to the device,
+ *     as from it we'll process device reports, which might require
+ *     further communication with the device.
+ *
+ * @debugfs_dentry: hookup for debugfs files.
+ *     These have to be in a separate directory, a child of
+ *     (wimax_dev->debugfs_dentry) so they can be removed when the
+ *     module unloads, as we don't keep each dentry.
+ */
+struct i2400m {
+        struct wimax_dev wimax_dev;     /* FIRST! See doc */
+
+        unsigned updown:1;              /* Network device is up or down */
+        unsigned boot_mode:1;           /* is the device in boot mode? */
+        unsigned sboot:1;               /* signed or unsigned fw boot */
+        unsigned ready:1;               /* all probing steps done */
+        u8 trace_msg_from_user;         /* echo rx msgs to 'trace' pipe */
+                                        /* typed u8 so debugfs/u8 can tweak */
+        enum i2400m_system_state state;
+        wait_queue_head_t state_wq;     /* Woken up when on state updates */
+
+        size_t bus_tx_block_size;
+        size_t bus_pl_size_max;
+        int (*bus_dev_start)(struct i2400m *);
+        void (*bus_dev_stop)(struct i2400m *);
+        void (*bus_tx_kick)(struct i2400m *);
+        int (*bus_reset)(struct i2400m *, enum i2400m_reset_type);
+        ssize_t (*bus_bm_cmd_send)(struct i2400m *,
+                                   const struct i2400m_bootrom_header *,
+                                   size_t, int flags);
+        ssize_t (*bus_bm_wait_for_ack)(struct i2400m *,
+                                       struct i2400m_bootrom_header *, size_t);
+        const char *bus_fw_name;
+        unsigned bus_bm_mac_addr_impaired:1;
+
+        spinlock_t tx_lock;             /* protect TX state */
+        void *tx_buf;
+        size_t tx_in, tx_out;
+        struct i2400m_msg_hdr *tx_msg;
+        size_t tx_sequence, tx_msg_size;
+        /* TX stats */
+        unsigned tx_pl_num, tx_pl_max, tx_pl_min,
+                tx_num, tx_size_acc, tx_size_min, tx_size_max;
+
+        /* RX stats */
+        spinlock_t rx_lock;             /* protect RX state */
+        unsigned rx_pl_num, rx_pl_max, rx_pl_min,
+                rx_num, rx_size_acc, rx_size_min, rx_size_max;
+
+        struct mutex msg_mutex;         /* serialize command execution */
+        struct completion msg_completion;
+        struct sk_buff *ack_skb;        /* protected by rx_lock */
+
+        void *bm_ack_buf;               /* for receiving acks over USB */
+        void *bm_cmd_buf;               /* for issuing commands over USB */
+
+        struct workqueue_struct *work_queue;
+
+        struct mutex init_mutex;        /* protect bringup seq */
+        struct i2400m_reset_ctx *reset_ctx;     /* protected by init_mutex */
+
+        struct work_struct wake_tx_ws;
+        struct sk_buff *wake_tx_skb;
+
+        struct dentry *debugfs_dentry;
+};
+
+
+/*
+ * Initialize a 'struct i2400m' from all zeroes
+ *
+ * This is a bus-generic API call.
+ */
+static inline
+void i2400m_init(struct i2400m *i2400m)
+{
+        wimax_dev_init(&i2400m->wimax_dev);
+
+        i2400m->boot_mode = 1;
+        init_waitqueue_head(&i2400m->state_wq);
+
+        spin_lock_init(&i2400m->tx_lock);
+        i2400m->tx_pl_min = UINT_MAX;
+        i2400m->tx_size_min = UINT_MAX;
+
+        spin_lock_init(&i2400m->rx_lock);
+        i2400m->rx_pl_min = UINT_MAX;
+        i2400m->rx_size_min = UINT_MAX;
+
+        mutex_init(&i2400m->msg_mutex);
+        init_completion(&i2400m->msg_completion);
+
+        mutex_init(&i2400m->init_mutex);
+        /* wake_tx_ws is initialized in i2400m_tx_setup() */
+}
+
+
+/*
+ * Bus-generic internal APIs
+ * -------------------------
+ */
+
+static inline
+struct i2400m *wimax_dev_to_i2400m(struct wimax_dev *wimax_dev)
+{
+        return container_of(wimax_dev, struct i2400m, wimax_dev);
+}
+
+static inline
+struct i2400m *net_dev_to_i2400m(struct net_device *net_dev)
+{
+        return wimax_dev_to_i2400m(netdev_priv(net_dev));
+}
+
+/*
+ * Boot mode support
+ */
+
+/**
+ * i2400m_bm_cmd_flags - flags to i2400m_bm_cmd()
+ *
+ * @I2400M_BM_CMD_RAW: send the command block as-is, without doing any
+ *     extra processing for adding CRC.
+ */
+enum i2400m_bm_cmd_flags {
+        I2400M_BM_CMD_RAW       = 1 << 2,
+};
+
+/**
+ * i2400m_bri - Boot-ROM indicators
+ *
+ * Flags for i2400m_bootrom_init() and i2400m_dev_bootstrap() [which
+ * are passed from things like i2400m_setup()]. Can be combined with
+ * |.
+ *
+ * @I2400M_BRI_SOFT: The device rebooted already and a reboot
+ *     barker received, proceed directly to ack the boot sequence.
+ * @I2400M_BRI_NO_REBOOT: Do not reboot the device and proceed
+ *     directly to wait for a reboot barker from the device.
+ * @I2400M_BRI_MAC_REINIT: We need to reinitialize the boot
+ *     rom after reading the MAC adress. This is quite a dirty hack,
+ *     if you ask me -- the device requires the bootrom to be
+ *     intialized after reading the MAC address.
+ */
+enum i2400m_bri {
+        I2400M_BRI_SOFT       = 1 << 1,
+        I2400M_BRI_NO_REBOOT  = 1 << 2,
+        I2400M_BRI_MAC_REINIT = 1 << 3,
+};
+
+extern void i2400m_bm_cmd_prepare(struct i2400m_bootrom_header *);
+extern int i2400m_dev_bootstrap(struct i2400m *, enum i2400m_bri);
+extern int i2400m_read_mac_addr(struct i2400m *);
+extern int i2400m_bootrom_init(struct i2400m *, enum i2400m_bri);
+
+/* Make/grok boot-rom header commands */
+
+static inline
+__le32 i2400m_brh_command(enum i2400m_brh_opcode opcode, unsigned use_checksum,
+                          unsigned direct_access)
+{
+        return cpu_to_le32(
+                I2400M_BRH_SIGNATURE
+                | (direct_access ? I2400M_BRH_DIRECT_ACCESS : 0)
+                | I2400M_BRH_RESPONSE_REQUIRED /* response always required */
+                | (use_checksum ? I2400M_BRH_USE_CHECKSUM : 0)
+                | (opcode & I2400M_BRH_OPCODE_MASK));
+}
+
+static inline
+void i2400m_brh_set_opcode(struct i2400m_bootrom_header *hdr,
+                           enum i2400m_brh_opcode opcode)
+{
+        hdr->command = cpu_to_le32(
+                (le32_to_cpu(hdr->command) & ~I2400M_BRH_OPCODE_MASK)
+                | (opcode & I2400M_BRH_OPCODE_MASK));
+}
+
+static inline
+unsigned i2400m_brh_get_opcode(const struct i2400m_bootrom_header *hdr)
+{
+        return le32_to_cpu(hdr->command) & I2400M_BRH_OPCODE_MASK;
+}
+
+static inline
+unsigned i2400m_brh_get_response(const struct i2400m_bootrom_header *hdr)
+{
+        return (le32_to_cpu(hdr->command) & I2400M_BRH_RESPONSE_MASK)
+                >> I2400M_BRH_RESPONSE_SHIFT;
+}
+
+static inline
+unsigned i2400m_brh_get_use_checksum(const struct i2400m_bootrom_header *hdr)
+{
+        return le32_to_cpu(hdr->command) & I2400M_BRH_USE_CHECKSUM;
+}
+
+static inline
+unsigned i2400m_brh_get_response_required(
+        const struct i2400m_bootrom_header *hdr)
+{
+        return le32_to_cpu(hdr->command) & I2400M_BRH_RESPONSE_REQUIRED;
+}
+
+static inline
+unsigned i2400m_brh_get_direct_access(const struct i2400m_bootrom_header *hdr)
+{
+        return le32_to_cpu(hdr->command) & I2400M_BRH_DIRECT_ACCESS;
+}
+
+static inline
+unsigned i2400m_brh_get_signature(const struct i2400m_bootrom_header *hdr)
+{
+        return (le32_to_cpu(hdr->command) & I2400M_BRH_SIGNATURE_MASK)
+                >> I2400M_BRH_SIGNATURE_SHIFT;
+}
+
+
+/*
+ * Driver / device setup and internal functions
+ */
+extern void i2400m_netdev_setup(struct net_device *net_dev);
+extern int i2400m_tx_setup(struct i2400m *);
+extern void i2400m_wake_tx_work(struct work_struct *);
+extern void i2400m_tx_release(struct i2400m *);
+
+extern void i2400m_net_rx(struct i2400m *, struct sk_buff *, unsigned,
+                          const void *, int);
+enum i2400m_pt;
+extern int i2400m_tx(struct i2400m *, const void *, size_t, enum i2400m_pt);
+
+#ifdef CONFIG_DEBUG_FS
+extern int i2400m_debugfs_add(struct i2400m *);
+extern void i2400m_debugfs_rm(struct i2400m *);
+#else
+static inline int i2400m_debugfs_add(struct i2400m *i2400m)
+{
+        return 0;
+}
+static inline void i2400m_debugfs_rm(struct i2400m *i2400m) {}
+#endif
+
+/* Called by _dev_start()/_dev_stop() to initialize the device itself */
+extern int i2400m_dev_initialize(struct i2400m *);
+extern void i2400m_dev_shutdown(struct i2400m *);
+
+extern struct attribute_group i2400m_dev_attr_group;
+
+extern int i2400m_schedule_work(struct i2400m *,
+                                void (*)(struct work_struct *), gfp_t);
+
+/* HDI message's payload description handling */
+
+static inline
+size_t i2400m_pld_size(const struct i2400m_pld *pld)
+{
+        return I2400M_PLD_SIZE_MASK & le32_to_cpu(pld->val);
+}
+
+static inline
+enum i2400m_pt i2400m_pld_type(const struct i2400m_pld *pld)
+{
+        return (I2400M_PLD_TYPE_MASK & le32_to_cpu(pld->val))
+                >> I2400M_PLD_TYPE_SHIFT;
+}
+
+static inline
+void i2400m_pld_set(struct i2400m_pld *pld, size_t size,
+                    enum i2400m_pt type)
+{
+        pld->val = cpu_to_le32(
+                ((type << I2400M_PLD_TYPE_SHIFT) & I2400M_PLD_TYPE_MASK)
+                |  (size & I2400M_PLD_SIZE_MASK));
+}
+
+
+/*
+ * API for the bus-specific drivers
+ * --------------------------------
+ */
+
+static inline
+struct i2400m *i2400m_get(struct i2400m *i2400m)
+{
+        dev_hold(i2400m->wimax_dev.net_dev);
+        return i2400m;
+}
+
+static inline
+void i2400m_put(struct i2400m *i2400m)
+{
+        dev_put(i2400m->wimax_dev.net_dev);
+}
+
+extern int i2400m_dev_reset_handle(struct i2400m *);
+
+/*
+ * _setup()/_release() are called by the probe/disconnect functions of
+ * the bus-specific drivers.
+ */
+extern int i2400m_setup(struct i2400m *, enum i2400m_bri bm_flags);
+extern void i2400m_release(struct i2400m *);
+
+extern int i2400m_rx(struct i2400m *, struct sk_buff *);
+extern struct i2400m_msg_hdr *i2400m_tx_msg_get(struct i2400m *, size_t *);
+extern void i2400m_tx_msg_sent(struct i2400m *);
+
+static const __le32 i2400m_NBOOT_BARKER[4] = {
+        __constant_cpu_to_le32(I2400M_NBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_NBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_NBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_NBOOT_BARKER)
+};
+
+static const __le32 i2400m_SBOOT_BARKER[4] = {
+        __constant_cpu_to_le32(I2400M_SBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_SBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_SBOOT_BARKER),
+        __constant_cpu_to_le32(I2400M_SBOOT_BARKER)
+};
+
+
+/*
+ * Utility functions
+ */
+
+static inline
+struct device *i2400m_dev(struct i2400m *i2400m)
+{
+        return i2400m->wimax_dev.net_dev->dev.parent;
+}
+
+/*
+ * Helper for scheduling simple work functions
+ *
+ * This struct can get any kind of payload attached (normally in the
+ * form of a struct where you pack the stuff you want to pass to the
+ * _work function).
+ */
+struct i2400m_work {
+        struct work_struct ws;
+        struct i2400m *i2400m;
+        u8 pl[0];
+};
+extern int i2400m_queue_work(struct i2400m *,
+                             void (*)(struct work_struct *), gfp_t,
+                                const void *, size_t);
+
+extern int i2400m_msg_check_status(const struct i2400m_l3l4_hdr *,
+                                   char *, size_t);
+extern int i2400m_msg_size_check(struct i2400m *,
+                                 const struct i2400m_l3l4_hdr *, size_t);
+extern struct sk_buff *i2400m_msg_to_dev(struct i2400m *, const void *, size_t);
+extern void i2400m_msg_to_dev_cancel_wait(struct i2400m *, int);
+extern void i2400m_msg_ack_hook(struct i2400m *,
+                                const struct i2400m_l3l4_hdr *, size_t);
+extern void i2400m_report_hook(struct i2400m *,
+                               const struct i2400m_l3l4_hdr *, size_t);
+extern int i2400m_cmd_enter_powersave(struct i2400m *);
+extern int i2400m_cmd_get_state(struct i2400m *);
+extern int i2400m_cmd_exit_idle(struct i2400m *);
+extern struct sk_buff *i2400m_get_device_info(struct i2400m *);
+extern int i2400m_firmware_check(struct i2400m *);
+extern int i2400m_set_init_config(struct i2400m *,
+                                  const struct i2400m_tlv_hdr **, size_t);
+
+static inline
+struct usb_endpoint_descriptor *usb_get_epd(struct usb_interface *iface, int ep)
+{
+        return &iface->cur_altsetting->endpoint[ep].desc;
+}
+
+extern int i2400m_op_rfkill_sw_toggle(struct wimax_dev *,
+                                      enum wimax_rf_state);
+extern void i2400m_report_tlv_rf_switches_status(
+        struct i2400m *, const struct i2400m_tlv_rf_switches_status *);
+
+
+/*
+ * Do a millisecond-sleep for allowing wireshark to dump all the data
+ * packets. Used only for debugging.
+ */
+static inline
+void __i2400m_msleep(unsigned ms)
+{
+#if 1
+#else
+        msleep(ms);
+#endif
+}
+
+/* Module parameters */
+
+extern int i2400m_idle_mode_disabled;
+
+
+#endif /* #ifndef __I2400M_H__ */
diff --git a/drivers/net/wimax/i2400m/netdev.c b/drivers/net/wimax/i2400m/netdev.c
new file mode 100644
index 000000000000..63fe708e8a31
--- /dev/null
+++ b/drivers/net/wimax/i2400m/netdev.c
@@ -0,0 +1,524 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Glue with the networking stack
+ *
+ *
+ * Copyright (C) 2007 Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This implements an ethernet device for the i2400m.
+ *
+ * We fake being an ethernet device to simplify the support from user
+ * space and from the other side. The world is (sadly) configured to
+ * take in only Ethernet devices...
+ *
+ * Because of this, currently there is an copy-each-rxed-packet
+ * overhead on the RX path. Each IP packet has to be reallocated to
+ * add an ethernet header (as there is no space in what we get from
+ * the device). This is a known drawback and coming versions of the
+ * device's firmware are being changed to add header space that can be
+ * used to insert the ethernet header without having to reallocate and
+ * copy.
+ *
+ * TX error handling is tricky; because we have to FIFO/queue the
+ * buffers for transmission (as the hardware likes it aggregated), we
+ * just give the skb to the TX subsystem and by the time it is
+ * transmitted, we have long forgotten about it. So we just don't care
+ * too much about it.
+ *
+ * Note that when the device is in idle mode with the basestation, we
+ * need to negotiate coming back up online. That involves negotiation
+ * and possible user space interaction. Thus, we defer to a workqueue
+ * to do all that. By default, we only queue a single packet and drop
+ * the rest, as potentially the time to go back from idle to normal is
+ * long.
+ *
+ * ROADMAP
+ *
+ * i2400m_open         Called on ifconfig up
+ * i2400m_stop         Called on ifconfig down
+ *
+ * i2400m_hard_start_xmit Called by the network stack to send a packet
+ *   i2400m_net_wake_tx   Wake up device from basestation-IDLE & TX
+ *     i2400m_wake_tx_work
+ *       i2400m_cmd_exit_idle
+ *       i2400m_tx
+ *   i2400m_net_tx        TX a data frame
+ *     i2400m_tx
+ *
+ * i2400m_change_mtu      Called on ifconfig mtu XXX
+ *
+ * i2400m_tx_timeout      Called when the device times out
+ *
+ * i2400m_net_rx          Called by the RX code when a data frame is
+ *                        available.
+ * i2400m_netdev_setup    Called to setup all the netdev stuff from
+ *                        alloc_netdev.
+ */
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include "i2400m.h"
+
+
+#define D_SUBMODULE netdev
+#include "debug-levels.h"
+
+enum {
+/* netdev interface */
+        /*
+         * Out of NWG spec (R1_v1.2.2), 3.3.3 ASN Bearer Plane MTU Size
+         *
+         * The MTU is 1400 or less
+         */
+        I2400M_MAX_MTU = 1400,
+        I2400M_TX_TIMEOUT = HZ,
+        I2400M_TX_QLEN = 5,
+};
+
+
+static
+int i2400m_open(struct net_device *net_dev)
+{
+        int result;
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(net_dev %p [i2400m %p])\n", net_dev, i2400m);
+        if (i2400m->ready == 0) {
+                dev_err(dev, "Device is still initializing\n");
+                result = -EBUSY;
+        } else
+                result = 0;
+        d_fnend(3, dev, "(net_dev %p [i2400m %p]) = %d\n",
+                net_dev, i2400m, result);
+        return result;
+}
+
+
+/*
+ *
+ * On kernel versions where cancel_work_sync() didn't return anything,
+ * we rely on wake_tx_skb() being non-NULL.
+ */
+static
+int i2400m_stop(struct net_device *net_dev)
+{
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(net_dev %p [i2400m %p])\n", net_dev, i2400m);
+        /* See i2400m_hard_start_xmit(), references are taken there
+         * and here we release them if the work was still
+         * pending. Note we can't differentiate work not pending vs
+         * never scheduled, so the NULL check does that. */
+        if (cancel_work_sync(&i2400m->wake_tx_ws) == 0
+            && i2400m->wake_tx_skb != NULL) {
+                unsigned long flags;
+                struct sk_buff *wake_tx_skb;
+                spin_lock_irqsave(&i2400m->tx_lock, flags);
+                wake_tx_skb = i2400m->wake_tx_skb;      /* compat help */
+                i2400m->wake_tx_skb = NULL;     /* compat help */
+                spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+                i2400m_put(i2400m);
+                kfree_skb(wake_tx_skb);
+        }
+        d_fnend(3, dev, "(net_dev %p [i2400m %p]) = 0\n", net_dev, i2400m);
+        return 0;
+}
+
+
+/*
+ * Wake up the device and transmit a held SKB, then restart the net queue
+ *
+ * When the device goes into basestation-idle mode, we need to tell it
+ * to exit that mode; it will negotiate with the base station, user
+ * space may have to intervene to rehandshake crypto and then tell us
+ * when it is ready to transmit the packet we have "queued". Still we
+ * need to give it sometime after it reports being ok.
+ *
+ * On error, there is not much we can do. If the error was on TX, we
+ * still wake the queue up to see if the next packet will be luckier.
+ *
+ * If _cmd_exit_idle() fails...well, it could be many things; most
+ * commonly it is that something else took the device out of IDLE mode
+ * (for example, the base station). In that case we get an -EILSEQ and
+ * we are just going to ignore that one. If the device is back to
+ * connected, then fine -- if it is someother state, the packet will
+ * be dropped anyway.
+ */
+void i2400m_wake_tx_work(struct work_struct *ws)
+{
+        int result;
+        struct i2400m *i2400m = container_of(ws, struct i2400m, wake_tx_ws);
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *skb = i2400m->wake_tx_skb;
+        unsigned long flags;
+
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+        skb = i2400m->wake_tx_skb;
+        i2400m->wake_tx_skb = NULL;
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+
+        d_fnstart(3, dev, "(ws %p i2400m %p skb %p)\n", ws, i2400m, skb);
+        result = -EINVAL;
+        if (skb == NULL) {
+                dev_err(dev, "WAKE&TX: skb dissapeared!\n");
+                goto out_put;
+        }
+        result = i2400m_cmd_exit_idle(i2400m);
+        if (result == -EILSEQ)
+                result = 0;
+        if (result < 0) {
+                dev_err(dev, "WAKE&TX: device didn't get out of idle: "
+                        "%d\n", result);
+                        goto error;
+        }
+        result = wait_event_timeout(i2400m->state_wq,
+                                    i2400m->state != I2400M_SS_IDLE, 5 * HZ);
+        if (result == 0)
+                result = -ETIMEDOUT;
+        if (result < 0) {
+                dev_err(dev, "WAKE&TX: error waiting for device to exit IDLE: "
+                        "%d\n", result);
+                goto error;
+        }
+        msleep(20);     /* device still needs some time or it drops it */
+        result = i2400m_tx(i2400m, skb->data, skb->len, I2400M_PT_DATA);
+        netif_wake_queue(i2400m->wimax_dev.net_dev);
+error:
+        kfree_skb(skb); /* refcount transferred by _hard_start_xmit() */
+out_put:
+        i2400m_put(i2400m);
+        d_fnend(3, dev, "(ws %p i2400m %p skb %p) = void [%d]\n",
+                ws, i2400m, skb, result);
+}
+
+
+/*
+ * Prepare the data payload TX header
+ *
+ * The i2400m expects a 4 byte header in front of a data packet.
+ *
+ * Because we pretend to be an ethernet device, this packet comes with
+ * an ethernet header. Pull it and push our header.
+ */
+static
+void i2400m_tx_prep_header(struct sk_buff *skb)
+{
+        struct i2400m_pl_data_hdr *pl_hdr;
+        skb_pull(skb, ETH_HLEN);
+        pl_hdr = (struct i2400m_pl_data_hdr *) skb_push(skb, sizeof(*pl_hdr));
+        pl_hdr->reserved = 0;
+}
+
+
+/*
+ * TX an skb to an idle device
+ *
+ * When the device is in basestation-idle mode, we need to wake it up
+ * and then TX. So we queue a work_struct for doing so.
+ *
+ * We need to get an extra ref for the skb (so it is not dropped), as
+ * well as be careful not to queue more than one request (won't help
+ * at all). If more than one request comes or there are errors, we
+ * just drop the packets (see i2400m_hard_start_xmit()).
+ */
+static
+int i2400m_net_wake_tx(struct i2400m *i2400m, struct net_device *net_dev,
+                       struct sk_buff *skb)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        unsigned long flags;
+
+        d_fnstart(3, dev, "(skb %p net_dev %p)\n", skb, net_dev);
+        if (net_ratelimit()) {
+                d_printf(3, dev, "WAKE&NETTX: "
+                         "skb %p sending %d bytes to radio\n",
+                         skb, skb->len);
+                d_dump(4, dev, skb->data, skb->len);
+        }
+        /* We hold a ref count for i2400m and skb, so when
+         * stopping() the device, we need to cancel that work
+         * and if pending, release those resources. */
+        result = 0;
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+        if (!work_pending(&i2400m->wake_tx_ws)) {
+                netif_stop_queue(net_dev);
+                i2400m_get(i2400m);
+                i2400m->wake_tx_skb = skb_get(skb);     /* transfer ref count */
+                i2400m_tx_prep_header(skb);
+                result = schedule_work(&i2400m->wake_tx_ws);
+                WARN_ON(result == 0);
+        }
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        if (result == 0) {
+                /* Yes, this happens even if we stopped the
+                 * queue -- blame the queue disciplines that
+                 * queue without looking -- I guess there is a reason
+                 * for that. */
+                if (net_ratelimit())
+                        d_printf(1, dev, "NETTX: device exiting idle, "
+                                 "dropping skb %p, queue running %d\n",
+                                 skb, netif_queue_stopped(net_dev));
+                result = -EBUSY;
+        }
+        d_fnend(3, dev, "(skb %p net_dev %p) = %d\n", skb, net_dev, result);
+        return result;
+}
+
+
+/*
+ * Transmit a packet to the base station on behalf of the network stack.
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * We need to pull the ethernet header and add the hardware header,
+ * which is currently set to all zeroes and reserved.
+ */
+static
+int i2400m_net_tx(struct i2400m *i2400m, struct net_device *net_dev,
+                  struct sk_buff *skb)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(i2400m %p net_dev %p skb %p)\n",
+                  i2400m, net_dev, skb);
+        /* FIXME: check eth hdr, only IPv4 is routed by the device as of now */
+        net_dev->trans_start = jiffies;
+        i2400m_tx_prep_header(skb);
+        d_printf(3, dev, "NETTX: skb %p sending %d bytes to radio\n",
+                 skb, skb->len);
+        d_dump(4, dev, skb->data, skb->len);
+        result = i2400m_tx(i2400m, skb->data, skb->len, I2400M_PT_DATA);
+        d_fnend(3, dev, "(i2400m %p net_dev %p skb %p) = %d\n",
+                i2400m, net_dev, skb, result);
+        return result;
+}
+
+
+/*
+ * Transmit a packet to the base station on behalf of the network stack
+ *
+ *
+ * Returns: NETDEV_TX_OK (always, even in case of error)
+ *
+ * In case of error, we just drop it. Reasons:
+ *
+ *  - we add a hw header to each skb, and if the network stack
+ *    retries, we have no way to know if that skb has it or not.
+ *
+ *  - network protocols have their own drop-recovery mechanisms
+ *
+ *  - there is not much else we can do
+ *
+ * If the device is idle, we need to wake it up; that is an operation
+ * that will sleep. See i2400m_net_wake_tx() for details.
+ */
+static
+int i2400m_hard_start_xmit(struct sk_buff *skb,
+                           struct net_device *net_dev)
+{
+        int result;
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(skb %p net_dev %p)\n", skb, net_dev);
+        if (i2400m->state == I2400M_SS_IDLE)
+                result = i2400m_net_wake_tx(i2400m, net_dev, skb);
+        else
+                result = i2400m_net_tx(i2400m, net_dev, skb);
+        if (result <  0)
+                net_dev->stats.tx_dropped++;
+        else {
+                net_dev->stats.tx_packets++;
+                net_dev->stats.tx_bytes += skb->len;
+        }
+        kfree_skb(skb);
+        result = NETDEV_TX_OK;
+        d_fnend(3, dev, "(skb %p net_dev %p) = %d\n", skb, net_dev, result);
+        return result;
+}
+
+
+static
+int i2400m_change_mtu(struct net_device *net_dev, int new_mtu)
+{
+        int result;
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct device *dev = i2400m_dev(i2400m);
+
+        if (new_mtu >= I2400M_MAX_MTU) {
+                dev_err(dev, "Cannot change MTU to %d (max is %d)\n",
+                        new_mtu, I2400M_MAX_MTU);
+                result = -EINVAL;
+        } else {
+                net_dev->mtu = new_mtu;
+                result = 0;
+        }
+        return result;
+}
+
+
+static
+void i2400m_tx_timeout(struct net_device *net_dev)
+{
+        /*
+         * We might want to kick the device
+         *
+         * There is not much we can do though, as the device requires
+         * that we send the data aggregated. By the time we receive
+         * this, there might be data pending to be sent or not...
+         */
+        net_dev->stats.tx_errors++;
+        return;
+}
+
+
+/*
+ * Create a fake ethernet header
+ *
+ * For emulating an ethernet device, every received IP header has to
+ * be prefixed with an ethernet header.
+ *
+ * What we receive has (potentially) many IP packets concatenated with
+ * no ETH_HLEN bytes prefixed. Thus there is no space for an eth
+ * header.
+ *
+ * We would have to reallocate or do ugly fragment tricks in order to
+ * add it.
+ *
+ * But what we do is use the header space of the RX transaction
+ * (*msg_hdr) as we don't need it anymore; then we'll point all the
+ * data skbs there, as they share the same backing store.
+ *
+ * We only support IPv4 for v3 firmware.
+ */
+static
+void i2400m_rx_fake_eth_header(struct net_device *net_dev,
+                               void *_eth_hdr)
+{
+        struct ethhdr *eth_hdr = _eth_hdr;
+
+        memcpy(eth_hdr->h_dest, net_dev->dev_addr, sizeof(eth_hdr->h_dest));
+        memset(eth_hdr->h_source, 0, sizeof(eth_hdr->h_dest));
+        eth_hdr->h_proto = __constant_cpu_to_be16(ETH_P_IP);
+}
+
+
+/*
+ * i2400m_net_rx - pass a network packet to the stack
+ *
+ * @i2400m: device instance
+ * @skb_rx: the skb where the buffer pointed to by @buf is
+ * @i: 1 if payload is the only one
+ * @buf: pointer to the buffer containing the data
+ * @len: buffer's length
+ *
+ * We just clone the skb and set it up so that it's skb->data pointer
+ * points to "buf" and it's length.
+ *
+ * Note that if the payload is the last (or the only one) in a
+ * multi-payload message, we don't clone the SKB but just reuse it.
+ *
+ * This function is normally run from a thread context. However, we
+ * still use netif_rx() instead of netif_receive_skb() as was
+ * recommended in the mailing list. Reason is in some stress tests
+ * when sending/receiving a lot of data we seem to hit a softlock in
+ * the kernel's TCP implementation [aroudn tcp_delay_timer()]. Using
+ * netif_rx() took care of the issue.
+ *
+ * This is, of course, still open to do more research on why running
+ * with netif_receive_skb() hits this softlock. FIXME.
+ *
+ * FIXME: currently we don't do any efforts at distinguishing if what
+ * we got was an IPv4 or IPv6 header, to setup the protocol field
+ * correctly.
+ */
+void i2400m_net_rx(struct i2400m *i2400m, struct sk_buff *skb_rx,
+                   unsigned i, const void *buf, int buf_len)
+{
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *skb;
+
+        d_fnstart(2, dev, "(i2400m %p buf %p buf_len %d)\n",
+                  i2400m, buf, buf_len);
+        if (i) {
+                skb = skb_get(skb_rx);
+                d_printf(2, dev, "RX: reusing first payload skb %p\n", skb);
+                skb_pull(skb, buf - (void *) skb->data);
+                skb_trim(skb, (void *) skb_end_pointer(skb) - buf);
+        } else {
+                /* Yes, this is bad -- a lot of overhead -- see
+                 * comments at the top of the file */
+                skb = __netdev_alloc_skb(net_dev, buf_len, GFP_KERNEL);
+                if (skb == NULL) {
+                        dev_err(dev, "NETRX: no memory to realloc skb\n");
+                        net_dev->stats.rx_dropped++;
+                        goto error_skb_realloc;
+                }
+                memcpy(skb_put(skb, buf_len), buf, buf_len);
+        }
+        i2400m_rx_fake_eth_header(i2400m->wimax_dev.net_dev,
+                                  skb->data - ETH_HLEN);
+        skb_set_mac_header(skb, -ETH_HLEN);
+        skb->dev = i2400m->wimax_dev.net_dev;
+        skb->protocol = htons(ETH_P_IP);
+        net_dev->stats.rx_packets++;
+        net_dev->stats.rx_bytes += buf_len;
+        d_printf(3, dev, "NETRX: receiving %d bytes to network stack\n",
+                buf_len);
+        d_dump(4, dev, buf, buf_len);
+        netif_rx_ni(skb);       /* see notes in function header */
+error_skb_realloc:
+        d_fnend(2, dev, "(i2400m %p buf %p buf_len %d) = void\n",
+                i2400m, buf, buf_len);
+}
+
+
+/**
+ * i2400m_netdev_setup - Setup setup @net_dev's i2400m private data
+ *
+ * Called by alloc_netdev()
+ */
+void i2400m_netdev_setup(struct net_device *net_dev)
+{
+        d_fnstart(3, NULL, "(net_dev %p)\n", net_dev);
+        ether_setup(net_dev);
+        net_dev->mtu = I2400M_MAX_MTU;
+        net_dev->tx_queue_len = I2400M_TX_QLEN;
+        net_dev->features =
+                  NETIF_F_VLAN_CHALLENGED
+                | NETIF_F_HIGHDMA;
+        net_dev->flags =
+                IFF_NOARP               /* i2400m is apure IP device */
+                & (~IFF_BROADCAST       /* i2400m is P2P */
+                   & ~IFF_MULTICAST);
+        net_dev->watchdog_timeo = I2400M_TX_TIMEOUT;
+        net_dev->open = i2400m_open;
+        net_dev->stop = i2400m_stop;
+        net_dev->hard_start_xmit = i2400m_hard_start_xmit;
+        net_dev->change_mtu = i2400m_change_mtu;
+        net_dev->tx_timeout = i2400m_tx_timeout;
+        d_fnend(3, NULL, "(net_dev %p) = void\n", net_dev);
+}
+EXPORT_SYMBOL_GPL(i2400m_netdev_setup);
+
diff --git a/drivers/net/wimax/i2400m/op-rfkill.c b/drivers/net/wimax/i2400m/op-rfkill.c
new file mode 100644
index 000000000000..487ec58cea46
--- /dev/null
+++ b/drivers/net/wimax/i2400m/op-rfkill.c
@@ -0,0 +1,207 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Implement backend for the WiMAX stack rfkill support
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * The WiMAX kernel stack integrates into RF-Kill and keeps the
+ * switches's status. We just need to:
+ *
+ * - report changes in the HW RF Kill switch [with
+ *   wimax_rfkill_{sw,hw}_report(), which happens when we detect those
+ *   indications coming through hardware reports]. We also do it on
+ *   initialization to let the stack know the intial HW state.
+ *
+ * - implement indications from the stack to change the SW RF Kill
+ *   switch (coming from sysfs, the wimax stack or user space).
+ */
+#include "i2400m.h"
+#include <linux/wimax/i2400m.h>
+
+
+
+#define D_SUBMODULE rfkill
+#include "debug-levels.h"
+
+/*
+ * Return true if the i2400m radio is in the requested wimax_rf_state state
+ *
+ */
+static
+int i2400m_radio_is(struct i2400m *i2400m, enum wimax_rf_state state)
+{
+        if (state == WIMAX_RF_OFF)
+                return i2400m->state == I2400M_SS_RF_OFF
+                        || i2400m->state == I2400M_SS_RF_SHUTDOWN;
+        else if (state == WIMAX_RF_ON)
+                /* state == WIMAX_RF_ON */
+                return i2400m->state != I2400M_SS_RF_OFF
+                        && i2400m->state != I2400M_SS_RF_SHUTDOWN;
+        else
+                BUG();
+}
+
+
+/*
+ * WiMAX stack operation: implement SW RFKill toggling
+ *
+ * @wimax_dev: device descriptor
+ * @skb: skb where the message has been received; skb->data is
+ *       expected to point to the message payload.
+ * @genl_info: passed by the generic netlink layer
+ *
+ * Generic Netlink will call this function when a message is sent from
+ * userspace to change the software RF-Kill switch status.
+ *
+ * This function will set the device's sofware RF-Kill switch state to
+ * match what is requested.
+ *
+ * NOTE: the i2400m has a strict state machine; we can only set the
+ *       RF-Kill switch when it is on, the HW RF-Kill is on and the
+ *       device is initialized. So we ignore errors steaming from not
+ *       being in the right state (-EILSEQ).
+ */
+int i2400m_op_rfkill_sw_toggle(struct wimax_dev *wimax_dev,
+                               enum wimax_rf_state state)
+{
+        int result;
+        struct i2400m *i2400m = wimax_dev_to_i2400m(wimax_dev);
+        struct device *dev = i2400m_dev(i2400m);
+        struct sk_buff *ack_skb;
+        struct {
+                struct i2400m_l3l4_hdr hdr;
+                struct i2400m_tlv_rf_operation sw_rf;
+        } __attribute__((packed)) *cmd;
+        char strerr[32];
+
+        d_fnstart(4, dev, "(wimax_dev %p state %d)\n", wimax_dev, state);
+
+        result = -ENOMEM;
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                goto error_alloc;
+        cmd->hdr.type = cpu_to_le16(I2400M_MT_CMD_RF_CONTROL);
+        cmd->hdr.length = sizeof(cmd->sw_rf);
+        cmd->hdr.version = cpu_to_le16(I2400M_L3L4_VERSION);
+        cmd->sw_rf.hdr.type = cpu_to_le16(I2400M_TLV_RF_OPERATION);
+        cmd->sw_rf.hdr.length = cpu_to_le16(sizeof(cmd->sw_rf.status));
+        switch (state) {
+        case WIMAX_RF_OFF:      /* RFKILL ON, radio OFF */
+                cmd->sw_rf.status = cpu_to_le32(2);
+                break;
+        case WIMAX_RF_ON:       /* RFKILL OFF, radio ON */
+                cmd->sw_rf.status = cpu_to_le32(1);
+                break;
+        default:
+                BUG();
+        }
+
+        ack_skb = i2400m_msg_to_dev(i2400m, cmd, sizeof(*cmd));
+        result = PTR_ERR(ack_skb);
+        if (IS_ERR(ack_skb)) {
+                dev_err(dev, "Failed to issue 'RF Control' command: %d\n",
+                        result);
+                goto error_msg_to_dev;
+        }
+        result = i2400m_msg_check_status(wimax_msg_data(ack_skb),
+                                         strerr, sizeof(strerr));
+        if (result < 0) {
+                dev_err(dev, "'RF Control' (0x%04x) command failed: %d - %s\n",
+                        I2400M_MT_CMD_RF_CONTROL, result, strerr);
+                goto error_cmd;
+        }
+
+        /* Now we wait for the state to change to RADIO_OFF or RADIO_ON */
+        result = wait_event_timeout(
+                i2400m->state_wq, i2400m_radio_is(i2400m, state),
+                5 * HZ);
+        if (result == 0)
+                result = -ETIMEDOUT;
+        if (result < 0)
+                dev_err(dev, "Error waiting for device to toggle RF state: "
+                        "%d\n", result);
+        result = 0;
+error_cmd:
+        kfree_skb(ack_skb);
+error_msg_to_dev:
+error_alloc:
+        d_fnend(4, dev, "(wimax_dev %p state %d) = %d\n",
+                wimax_dev, state, result);
+        return result;
+}
+
+
+/*
+ * Inform the WiMAX stack of changes in the RF Kill switches reported
+ * by the device
+ *
+ * @i2400m: device descriptor
+ * @rfss: TLV for RF Switches status; already validated
+ *
+ * NOTE: the reports on RF switch status cannot be trusted
+ *       or used until the device is in a state of RADIO_OFF
+ *       or greater.
+ */
+void i2400m_report_tlv_rf_switches_status(
+        struct i2400m *i2400m,
+        const struct i2400m_tlv_rf_switches_status *rfss)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        enum i2400m_rf_switch_status hw, sw;
+        enum wimax_st wimax_state;
+
+        sw = le32_to_cpu(rfss->sw_rf_switch);
+        hw = le32_to_cpu(rfss->hw_rf_switch);
+
+        d_fnstart(3, dev, "(i2400m %p rfss %p [hw %u sw %u])\n",
+                  i2400m, rfss, hw, sw);
+        /* We only process rw switch evens when the device has been
+         * fully initialized */
+        wimax_state = wimax_state_get(&i2400m->wimax_dev);
+        if (wimax_state < WIMAX_ST_RADIO_OFF) {
+                d_printf(3, dev, "ignoring RF switches report, state %u\n",
+                         wimax_state);
+                goto out;
+        }
+        switch (sw) {
+        case I2400M_RF_SWITCH_ON:       /* RF Kill disabled (radio on) */
+                wimax_report_rfkill_sw(&i2400m->wimax_dev, WIMAX_RF_ON);
+                break;
+        case I2400M_RF_SWITCH_OFF:      /* RF Kill enabled (radio off) */
+                wimax_report_rfkill_sw(&i2400m->wimax_dev, WIMAX_RF_OFF);
+                break;
+        default:
+                dev_err(dev, "HW BUG? Unknown RF SW state 0x%x\n", sw);
+        }
+
+        switch (hw) {
+        case I2400M_RF_SWITCH_ON:       /* RF Kill disabled (radio on) */
+                wimax_report_rfkill_hw(&i2400m->wimax_dev, WIMAX_RF_ON);
+                break;
+        case I2400M_RF_SWITCH_OFF:      /* RF Kill enabled (radio off) */
+                wimax_report_rfkill_hw(&i2400m->wimax_dev, WIMAX_RF_OFF);
+                break;
+        default:
+                dev_err(dev, "HW BUG? Unknown RF HW state 0x%x\n", hw);
+        }
+out:
+        d_fnend(3, dev, "(i2400m %p rfss %p [hw %u sw %u]) = void\n",
+                i2400m, rfss, hw, sw);
+}
diff --git a/drivers/net/wimax/i2400m/rx.c b/drivers/net/wimax/i2400m/rx.c
new file mode 100644
index 000000000000..6922022710ac
--- /dev/null
+++ b/drivers/net/wimax/i2400m/rx.c
@@ -0,0 +1,534 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Handle incoming traffic and deliver it to the control or data planes
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Use skb_clone(), break up processing in chunks
+ *  - Split transport/device specific
+ *  - Make buffer size dynamic to exert less memory pressure
+ *
+ *
+ * This handles the RX path.
+ *
+ * We receive an RX message from the bus-specific driver, which
+ * contains one or more payloads that have potentially different
+ * destinataries (data or control paths).
+ *
+ * So we just take that payload from the transport specific code in
+ * the form of an skb, break it up in chunks (a cloned skb each in the
+ * case of network packets) and pass it to netdev or to the
+ * command/ack handler (and from there to the WiMAX stack).
+ *
+ * PROTOCOL FORMAT
+ *
+ * The format of the buffer is:
+ *
+ * HEADER                      (struct i2400m_msg_hdr)
+ * PAYLOAD DESCRIPTOR 0        (struct i2400m_pld)
+ * PAYLOAD DESCRIPTOR 1
+ * ...
+ * PAYLOAD DESCRIPTOR N
+ * PAYLOAD 0                   (raw bytes)
+ * PAYLOAD 1
+ * ...
+ * PAYLOAD N
+ *
+ * See tx.c for a deeper description on alignment requirements and
+ * other fun facts of it.
+ *
+ * ROADMAP
+ *
+ * i2400m_rx
+ *   i2400m_rx_msg_hdr_check
+ *   i2400m_rx_pl_descr_check
+ *   i2400m_rx_payload
+ *     i2400m_net_rx
+ *     i2400m_rx_ctl
+ *       i2400m_msg_size_check
+ *       i2400m_report_hook_work    [in a workqueue]
+ *         i2400m_report_hook
+ *       wimax_msg_to_user
+ *       i2400m_rx_ctl_ack
+ *         wimax_msg_to_user_alloc
+ *     i2400m_rx_trace
+ *       i2400m_msg_size_check
+ *       wimax_msg
+ */
+#include <linux/kernel.h>
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/workqueue.h>
+#include "i2400m.h"
+
+
+#define D_SUBMODULE rx
+#include "debug-levels.h"
+
+struct i2400m_report_hook_args {
+        struct sk_buff *skb_rx;
+        const struct i2400m_l3l4_hdr *l3l4_hdr;
+        size_t size;
+};
+
+
+/*
+ * Execute i2400m_report_hook in a workqueue
+ *
+ * Unpacks arguments from the deferred call, executes it and then
+ * drops the references.
+ *
+ * Obvious NOTE: References are needed because we are a separate
+ *     thread; otherwise the buffer changes under us because it is
+ *     released by the original caller.
+ */
+static
+void i2400m_report_hook_work(struct work_struct *ws)
+{
+        struct i2400m_work *iw =
+                container_of(ws, struct i2400m_work, ws);
+        struct i2400m_report_hook_args *args = (void *) iw->pl;
+        i2400m_report_hook(iw->i2400m, args->l3l4_hdr, args->size);
+        kfree_skb(args->skb_rx);
+        i2400m_put(iw->i2400m);
+        kfree(iw);
+}
+
+
+/*
+ * Process an ack to a command
+ *
+ * @i2400m: device descriptor
+ * @payload: pointer to message
+ * @size: size of the message
+ *
+ * Pass the acknodledgment (in an skb) to the thread that is waiting
+ * for it in i2400m->msg_completion.
+ *
+ * We need to coordinate properly with the thread waiting for the
+ * ack. Check if it is waiting or if it is gone. We loose the spinlock
+ * to avoid allocating on atomic contexts (yeah, could use GFP_ATOMIC,
+ * but this is not so speed critical).
+ */
+static
+void i2400m_rx_ctl_ack(struct i2400m *i2400m,
+                       const void *payload, size_t size)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        unsigned long flags;
+        struct sk_buff *ack_skb;
+
+        /* Anyone waiting for an answer? */
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        if (i2400m->ack_skb != ERR_PTR(-EINPROGRESS)) {
+                dev_err(dev, "Huh? reply to command with no waiters\n");
+                goto error_no_waiter;
+        }
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+
+        ack_skb = wimax_msg_alloc(wimax_dev, NULL, payload, size, GFP_KERNEL);
+
+        /* Check waiter didn't time out waiting for the answer... */
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        if (i2400m->ack_skb != ERR_PTR(-EINPROGRESS)) {
+                d_printf(1, dev, "Huh? waiter for command reply cancelled\n");
+                goto error_waiter_cancelled;
+        }
+        if (ack_skb == NULL) {
+                dev_err(dev, "CMD/GET/SET ack: cannot allocate SKB\n");
+                i2400m->ack_skb = ERR_PTR(-ENOMEM);
+        } else
+                i2400m->ack_skb = ack_skb;
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        complete(&i2400m->msg_completion);
+        return;
+
+error_waiter_cancelled:
+        if (ack_skb)
+                kfree_skb(ack_skb);
+error_no_waiter:
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+        return;
+}
+
+
+/*
+ * Receive and process a control payload
+ *
+ * @i2400m: device descriptor
+ * @skb_rx: skb that contains the payload (for reference counting)
+ * @payload: pointer to message
+ * @size: size of the message
+ *
+ * There are two types of control RX messages: reports (asynchronous,
+ * like your every day interrupts) and 'acks' (reponses to a command,
+ * get or set request).
+ *
+ * If it is a report, we run hooks on it (to extract information for
+ * things we need to do in the driver) and then pass it over to the
+ * WiMAX stack to send it to user space.
+ *
+ * NOTE: report processing is done in a workqueue specific to the
+ *     generic driver, to avoid deadlocks in the system.
+ *
+ * If it is not a report, it is an ack to a previously executed
+ * command, set or get, so wake up whoever is waiting for it from
+ * i2400m_msg_to_dev(). i2400m_rx_ctl_ack() takes care of that.
+ *
+ * Note that the sizes we pass to other functions from here are the
+ * sizes of the _l3l4_hdr + payload, not full buffer sizes, as we have
+ * verified in _msg_size_check() that they are congruent.
+ *
+ * For reports: We can't clone the original skb where the data is
+ * because we need to send this up via netlink; netlink has to add
+ * headers and we can't overwrite what's preceeding the payload...as
+ * it is another message. So we just dup them.
+ */
+static
+void i2400m_rx_ctl(struct i2400m *i2400m, struct sk_buff *skb_rx,
+                   const void *payload, size_t size)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_l3l4_hdr *l3l4_hdr = payload;
+        unsigned msg_type;
+
+        result = i2400m_msg_size_check(i2400m, l3l4_hdr, size);
+        if (result < 0) {
+                dev_err(dev, "HW BUG? device sent a bad message: %d\n",
+                        result);
+                goto error_check;
+        }
+        msg_type = le16_to_cpu(l3l4_hdr->type);
+        d_printf(1, dev, "%s 0x%04x: %zu bytes\n",
+                 msg_type & I2400M_MT_REPORT_MASK ? "REPORT" : "CMD/SET/GET",
+                 msg_type, size);
+        d_dump(2, dev, l3l4_hdr, size);
+        if (msg_type & I2400M_MT_REPORT_MASK) {
+                /* These hooks have to be ran serialized; as well, the
+                 * handling might force the execution of commands, and
+                 * that might cause reentrancy issues with
+                 * bus-specific subdrivers and workqueues. So we run
+                 * it in a separate workqueue. */
+                struct i2400m_report_hook_args args = {
+                        .skb_rx = skb_rx,
+                        .l3l4_hdr = l3l4_hdr,
+                        .size = size
+                };
+                if (unlikely(i2400m->ready == 0))       /* only send if up */
+                        return;
+                skb_get(skb_rx);
+                i2400m_queue_work(i2400m, i2400m_report_hook_work,
+                                  GFP_KERNEL, &args, sizeof(args));
+                result = wimax_msg(&i2400m->wimax_dev, NULL, l3l4_hdr, size,
+                                   GFP_KERNEL);
+                if (result < 0)
+                        dev_err(dev, "error sending report to userspace: %d\n",
+                                result);
+        } else          /* an ack to a CMD, GET or SET */
+                i2400m_rx_ctl_ack(i2400m, payload, size);
+error_check:
+        return;
+}
+
+
+
+
+/*
+ * Receive and send up a trace
+ *
+ * @i2400m: device descriptor
+ * @skb_rx: skb that contains the trace (for reference counting)
+ * @payload: pointer to trace message inside the skb
+ * @size: size of the message
+ *
+ * THe i2400m might produce trace information (diagnostics) and we
+ * send them through a different kernel-to-user pipe (to avoid
+ * clogging it).
+ *
+ * As in i2400m_rx_ctl(), we can't clone the original skb where the
+ * data is because we need to send this up via netlink; netlink has to
+ * add headers and we can't overwrite what's preceeding the
+ * payload...as it is another message. So we just dup them.
+ */
+static
+void i2400m_rx_trace(struct i2400m *i2400m,
+                     const void *payload, size_t size)
+{
+        int result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+        const struct i2400m_l3l4_hdr *l3l4_hdr = payload;
+        unsigned msg_type;
+
+        result = i2400m_msg_size_check(i2400m, l3l4_hdr, size);
+        if (result < 0) {
+                dev_err(dev, "HW BUG? device sent a bad trace message: %d\n",
+                        result);
+                goto error_check;
+        }
+        msg_type = le16_to_cpu(l3l4_hdr->type);
+        d_printf(1, dev, "Trace %s 0x%04x: %zu bytes\n",
+                 msg_type & I2400M_MT_REPORT_MASK ? "REPORT" : "CMD/SET/GET",
+                 msg_type, size);
+        d_dump(2, dev, l3l4_hdr, size);
+        if (unlikely(i2400m->ready == 0))       /* only send if up */
+                return;
+        result = wimax_msg(wimax_dev, "trace", l3l4_hdr, size, GFP_KERNEL);
+        if (result < 0)
+                dev_err(dev, "error sending trace to userspace: %d\n",
+                        result);
+error_check:
+        return;
+}
+
+
+/*
+ * Act on a received payload
+ *
+ * @i2400m: device instance
+ * @skb_rx: skb where the transaction was received
+ * @single: 1 if there is only one payload, 0 otherwise
+ * @pld: payload descriptor
+ * @payload: payload data
+ *
+ * Upon reception of a payload, look at its guts in the payload
+ * descriptor and decide what to do with it.
+ */
+static
+void i2400m_rx_payload(struct i2400m *i2400m, struct sk_buff *skb_rx,
+                       unsigned single, const struct i2400m_pld *pld,
+                       const void *payload)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        size_t pl_size = i2400m_pld_size(pld);
+        enum i2400m_pt pl_type = i2400m_pld_type(pld);
+
+        switch (pl_type) {
+        case I2400M_PT_DATA:
+                d_printf(3, dev, "RX: data payload %zu bytes\n", pl_size);
+                i2400m_net_rx(i2400m, skb_rx, single, payload, pl_size);
+                break;
+        case I2400M_PT_CTRL:
+                i2400m_rx_ctl(i2400m, skb_rx, payload, pl_size);
+                break;
+        case I2400M_PT_TRACE:
+                i2400m_rx_trace(i2400m, payload, pl_size);
+                break;
+        default:        /* Anything else shouldn't come to the host */
+                if (printk_ratelimit())
+                        dev_err(dev, "RX: HW BUG? unexpected payload type %u\n",
+                                pl_type);
+        }
+}
+
+
+/*
+ * Check a received transaction's message header
+ *
+ * @i2400m: device descriptor
+ * @msg_hdr: message header
+ * @buf_size: size of the received buffer
+ *
+ * Check that the declarations done by a RX buffer message header are
+ * sane and consistent with the amount of data that was received.
+ */
+static
+int i2400m_rx_msg_hdr_check(struct i2400m *i2400m,
+                            const struct i2400m_msg_hdr *msg_hdr,
+                            size_t buf_size)
+{
+        int result = -EIO;
+        struct device *dev = i2400m_dev(i2400m);
+        if (buf_size < sizeof(*msg_hdr)) {
+                dev_err(dev, "RX: HW BUG? message with short header (%zu "
+                        "vs %zu bytes expected)\n", buf_size, sizeof(*msg_hdr));
+                goto error;
+        }
+        if (msg_hdr->barker != cpu_to_le32(I2400M_D2H_MSG_BARKER)) {
+                dev_err(dev, "RX: HW BUG? message received with unknown "
+                        "barker 0x%08x (buf_size %zu bytes)\n",
+                        le32_to_cpu(msg_hdr->barker), buf_size);
+                goto error;
+        }
+        if (msg_hdr->num_pls == 0) {
+                dev_err(dev, "RX: HW BUG? zero payload packets in message\n");
+                goto error;
+        }
+        if (le16_to_cpu(msg_hdr->num_pls) > I2400M_MAX_PLS_IN_MSG) {
+                dev_err(dev, "RX: HW BUG? message contains more payload "
+                        "than maximum; ignoring.\n");
+                goto error;
+        }
+        result = 0;
+error:
+        return result;
+}
+
+
+/*
+ * Check a payload descriptor against the received data
+ *
+ * @i2400m: device descriptor
+ * @pld: payload descriptor
+ * @pl_itr: offset (in bytes) in the received buffer the payload is
+ *          located
+ * @buf_size: size of the received buffer
+ *
+ * Given a payload descriptor (part of a RX buffer), check it is sane
+ * and that the data it declares fits in the buffer.
+ */
+static
+int i2400m_rx_pl_descr_check(struct i2400m *i2400m,
+                              const struct i2400m_pld *pld,
+                              size_t pl_itr, size_t buf_size)
+{
+        int result = -EIO;
+        struct device *dev = i2400m_dev(i2400m);
+        size_t pl_size = i2400m_pld_size(pld);
+        enum i2400m_pt pl_type = i2400m_pld_type(pld);
+
+        if (pl_size > i2400m->bus_pl_size_max) {
+                dev_err(dev, "RX: HW BUG? payload @%zu: size %zu is "
+                        "bigger than maximum %zu; ignoring message\n",
+                        pl_itr, pl_size, i2400m->bus_pl_size_max);
+                goto error;
+        }
+        if (pl_itr + pl_size > buf_size) {      /* enough? */
+                dev_err(dev, "RX: HW BUG? payload @%zu: size %zu "
+                        "goes beyond the received buffer "
+                        "size (%zu bytes); ignoring message\n",
+                        pl_itr, pl_size, buf_size);
+                goto error;
+        }
+        if (pl_type >= I2400M_PT_ILLEGAL) {
+                dev_err(dev, "RX: HW BUG? illegal payload type %u; "
+                        "ignoring message\n", pl_type);
+                goto error;
+        }
+        result = 0;
+error:
+        return result;
+}
+
+
+/**
+ * i2400m_rx - Receive a buffer of data from the device
+ *
+ * @i2400m: device descriptor
+ * @skb: skbuff where the data has been received
+ *
+ * Parse in a buffer of data that contains an RX message sent from the
+ * device. See the file header for the format. Run all checks on the
+ * buffer header, then run over each payload's descriptors, verify
+ * their consistency and act on each payload's contents.  If
+ * everything is succesful, update the device's statistics.
+ *
+ * Note: You need to set the skb to contain only the length of the
+ * received buffer; for that, use skb_trim(skb, RECEIVED_SIZE).
+ *
+ * Returns:
+ *
+ * 0 if ok, < 0 errno on error
+ *
+ * If ok, this function owns now the skb and the caller DOESN'T have
+ * to run kfree_skb() on it. However, on error, the caller still owns
+ * the skb and it is responsible for releasing it.
+ */
+int i2400m_rx(struct i2400m *i2400m, struct sk_buff *skb)
+{
+        int i, result;
+        struct device *dev = i2400m_dev(i2400m);
+        const struct i2400m_msg_hdr *msg_hdr;
+        size_t pl_itr, pl_size, skb_len;
+        unsigned long flags;
+        unsigned num_pls;
+
+        skb_len = skb->len;
+        d_fnstart(4, dev, "(i2400m %p skb %p [size %zu])\n",
+                  i2400m, skb, skb_len);
+        result = -EIO;
+        msg_hdr = (void *) skb->data;
+        result = i2400m_rx_msg_hdr_check(i2400m, msg_hdr, skb->len);
+        if (result < 0)
+                goto error_msg_hdr_check;
+        result = -EIO;
+        num_pls = le16_to_cpu(msg_hdr->num_pls);
+        pl_itr = sizeof(*msg_hdr) +     /* Check payload descriptor(s) */
+                num_pls * sizeof(msg_hdr->pld[0]);
+        pl_itr = ALIGN(pl_itr, I2400M_PL_PAD);
+        if (pl_itr > skb->len) {        /* got all the payload descriptors? */
+                dev_err(dev, "RX: HW BUG? message too short (%u bytes) for "
+                        "%u payload descriptors (%zu each, total %zu)\n",
+                        skb->len, num_pls, sizeof(msg_hdr->pld[0]), pl_itr);
+                goto error_pl_descr_short;
+        }
+        /* Walk each payload payload--check we really got it */
+        for (i = 0; i < num_pls; i++) {
+                /* work around old gcc warnings */
+                pl_size = i2400m_pld_size(&msg_hdr->pld[i]);
+                result = i2400m_rx_pl_descr_check(i2400m, &msg_hdr->pld[i],
+                                                  pl_itr, skb->len);
+                if (result < 0)
+                        goto error_pl_descr_check;
+                i2400m_rx_payload(i2400m, skb, num_pls == 1, &msg_hdr->pld[i],
+                                  skb->data + pl_itr);
+                pl_itr += ALIGN(pl_size, I2400M_PL_PAD);
+                cond_resched();         /* Don't monopolize */
+        }
+        kfree_skb(skb);
+        /* Update device statistics */
+        spin_lock_irqsave(&i2400m->rx_lock, flags);
+        i2400m->rx_pl_num += i;
+        if (i > i2400m->rx_pl_max)
+                i2400m->rx_pl_max = i;
+        if (i < i2400m->rx_pl_min)
+                i2400m->rx_pl_min = i;
+        i2400m->rx_num++;
+        i2400m->rx_size_acc += skb->len;
+        if (skb->len < i2400m->rx_size_min)
+                i2400m->rx_size_min = skb->len;
+        if (skb->len > i2400m->rx_size_max)
+                i2400m->rx_size_max = skb->len;
+        spin_unlock_irqrestore(&i2400m->rx_lock, flags);
+error_pl_descr_check:
+error_pl_descr_short:
+error_msg_hdr_check:
+        d_fnend(4, dev, "(i2400m %p skb %p [size %zu]) = %d\n",
+                i2400m, skb, skb_len, result);
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_rx);
diff --git a/drivers/net/wimax/i2400m/sdio-debug-levels.h b/drivers/net/wimax/i2400m/sdio-debug-levels.h
new file mode 100644
index 000000000000..c51998741301
--- /dev/null
+++ b/drivers/net/wimax/i2400m/sdio-debug-levels.h
@@ -0,0 +1,22 @@
+/*
+ * debug levels control file for the i2400m module's
+ */
+#ifndef __debug_levels__h__
+#define __debug_levels__h__
+
+/* Maximum compile and run time debug level for all submodules */
+#define D_MODULENAME i2400m_sdio
+#define D_MASTER CONFIG_WIMAX_I2400M_DEBUG_LEVEL
+
+#include <linux/wimax/debug.h>
+
+/* List of all the enabled modules */
+enum d_module {
+        D_SUBMODULE_DECLARE(main),
+        D_SUBMODULE_DECLARE(tx),
+        D_SUBMODULE_DECLARE(rx),
+        D_SUBMODULE_DECLARE(fw)
+};
+
+
+#endif /* #ifndef __debug_levels__h__ */
diff --git a/drivers/net/wimax/i2400m/sdio-fw.c b/drivers/net/wimax/i2400m/sdio-fw.c
new file mode 100644
index 000000000000..3487205d8f50
--- /dev/null
+++ b/drivers/net/wimax/i2400m/sdio-fw.c
@@ -0,0 +1,224 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Firmware uploader's SDIO specifics
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Bus generic/specific split for USB
+ *
+ * Dirk Brandewie <dirk.j.brandewie@intel.com>
+ *  - Initial implementation for SDIO
+ *
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - SDIO rehash for changes in the bus-driver model
+ *
+ * THE PROCEDURE
+ *
+ * See fw.c for the generic description of this procedure.
+ *
+ * This file implements only the SDIO specifics. It boils down to how
+ * to send a command and waiting for an acknowledgement from the
+ * device. We do polled reads.
+ *
+ * COMMAND EXECUTION
+ *
+ * THe generic firmware upload code will call i2400m_bus_bm_cmd_send()
+ * to send commands.
+ *
+ * The SDIO devices expects things in 256 byte blocks, so it will pad
+ * it, compute the checksum (if needed) and pass it to SDIO.
+ *
+ * ACK RECEPTION
+ *
+ * This works in polling mode -- the fw loader says when to wait for
+ * data and for that it calls i2400ms_bus_bm_wait_for_ack().
+ *
+ * This will poll the device for data until it is received. We need to
+ * receive at least as much bytes as where asked for (although it'll
+ * always be a multiple of 256 bytes).
+ */
+#include <linux/mmc/sdio_func.h>
+#include "i2400m-sdio.h"
+
+
+#define D_SUBMODULE fw
+#include "sdio-debug-levels.h"
+
+/*
+ * Send a boot-mode command to the SDIO function
+ *
+ * We use a bounce buffer (i2400m->bm_cmd_buf) because we need to
+ * touch the header if the RAW flag is not set.
+ *
+ * @flags: pass thru from i2400m_bm_cmd()
+ * @return: cmd_size if ok, < 0 errno code on error.
+ *
+ * Note the command is padded to the SDIO block size for the device.
+ */
+ssize_t i2400ms_bus_bm_cmd_send(struct i2400m *i2400m,
+                                const struct i2400m_bootrom_header *_cmd,
+                                size_t cmd_size, int flags)
+{
+        ssize_t result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        int opcode = _cmd == NULL ? -1 : i2400m_brh_get_opcode(_cmd);
+        struct i2400m_bootrom_header *cmd;
+        /* SDIO restriction */
+        size_t cmd_size_a = ALIGN(cmd_size, I2400MS_BLK_SIZE);
+
+        d_fnstart(5, dev, "(i2400m %p cmd %p size %zu)\n",
+                  i2400m, _cmd, cmd_size);
+        result = -E2BIG;
+        if (cmd_size > I2400M_BM_CMD_BUF_SIZE)
+                goto error_too_big;
+
+        memcpy(i2400m->bm_cmd_buf, _cmd, cmd_size);     /* Prep command */
+        cmd = i2400m->bm_cmd_buf;
+        if (cmd_size_a > cmd_size)                      /* Zero pad space */
+                memset(i2400m->bm_cmd_buf + cmd_size, 0, cmd_size_a - cmd_size);
+        if ((flags & I2400M_BM_CMD_RAW) == 0) {
+                if (WARN_ON(i2400m_brh_get_response_required(cmd) == 0))
+                        dev_warn(dev, "SW BUG: response_required == 0\n");
+                i2400m_bm_cmd_prepare(cmd);
+        }
+        d_printf(4, dev, "BM cmd %d: %zu bytes (%zu padded)\n",
+                 opcode, cmd_size, cmd_size_a);
+        d_dump(5, dev, cmd, cmd_size);
+
+        sdio_claim_host(i2400ms->func);                 /* Send & check */
+        result = sdio_memcpy_toio(i2400ms->func, I2400MS_DATA_ADDR,
+                                  i2400m->bm_cmd_buf, cmd_size_a);
+        sdio_release_host(i2400ms->func);
+        if (result < 0) {
+                dev_err(dev, "BM cmd %d: cannot send: %ld\n",
+                        opcode, (long) result);
+                goto error_cmd_send;
+        }
+        result = cmd_size;
+error_cmd_send:
+error_too_big:
+        d_fnend(5, dev, "(i2400m %p cmd %p size %zu) = %d\n",
+                i2400m, _cmd, cmd_size, (int) result);
+        return result;
+}
+
+
+/*
+ * Read an ack from the device's boot-mode (polling)
+ *
+ * @i2400m:
+ * @_ack: pointer to where to store the read data
+ * @ack_size: how many bytes we should read
+ *
+ * Returns: < 0 errno code on error; otherwise, amount of received bytes.
+ *
+ * The ACK for a BM command is always at least sizeof(*ack) bytes, so
+ * check for that. We don't need to check for device reboots
+ *
+ * NOTE: We do an artificial timeout of 1 sec over the SDIO timeout;
+ *     this way we have control over it...there is no way that I know
+ *     of setting an SDIO transaction timeout.
+ */
+ssize_t i2400ms_bus_bm_wait_for_ack(struct i2400m *i2400m,
+                                    struct i2400m_bootrom_header *ack,
+                                    size_t ack_size)
+{
+        int result;
+        ssize_t rx_size;
+        u64 timeout;
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+
+        BUG_ON(sizeof(*ack) > ack_size);
+
+        d_fnstart(5, dev, "(i2400m %p ack %p size %zu)\n",
+                  i2400m, ack, ack_size);
+
+        timeout = get_jiffies_64() + 2 * HZ;
+        sdio_claim_host(func);
+        while (1) {
+                if (time_after64(get_jiffies_64(), timeout)) {
+                        rx_size = -ETIMEDOUT;
+                        dev_err(dev, "timeout waiting for ack data\n");
+                        goto error_timedout;
+                }
+
+                /* Find the RX size, check if it fits or not -- it if
+                 * doesn't fit, fail, as we have no way to dispose of
+                 * the extra data. */
+                rx_size = __i2400ms_rx_get_size(i2400ms);
+                if (rx_size < 0)
+                        goto error_rx_get_size;
+                result = -ENOSPC;               /* Check it fits */
+                if (rx_size < sizeof(*ack)) {
+                        rx_size = -EIO;
+                        dev_err(dev, "HW BUG? received is too small (%zu vs "
+                                "%zu needed)\n", sizeof(*ack), rx_size);
+                        goto error_too_small;
+                }
+                if (rx_size > I2400M_BM_ACK_BUF_SIZE) {
+                        dev_err(dev, "SW BUG? BM_ACK_BUF is too small (%u vs "
+                                "%zu needed)\n", I2400M_BM_ACK_BUF_SIZE,
+                                rx_size);
+                        goto error_too_small;
+                }
+
+                /* Read it */
+                result = sdio_memcpy_fromio(func, i2400m->bm_ack_buf,
+                                            I2400MS_DATA_ADDR, rx_size);
+                if (result == -ETIMEDOUT || result == -ETIME)
+                        continue;
+                if (result < 0) {
+                        dev_err(dev, "BM SDIO receive (%zu B) failed: %d\n",
+                                rx_size, result);
+                        goto error_read;
+                } else
+                        break;
+        }
+        rx_size = min((ssize_t)ack_size, rx_size);
+        memcpy(ack, i2400m->bm_ack_buf, rx_size);
+error_read:
+error_too_small:
+error_rx_get_size:
+error_timedout:
+        sdio_release_host(func);
+        d_fnend(5, dev, "(i2400m %p ack %p size %zu) = %ld\n",
+                i2400m, ack, ack_size, (long) rx_size);
+        return rx_size;
+}
diff --git a/drivers/net/wimax/i2400m/sdio-rx.c b/drivers/net/wimax/i2400m/sdio-rx.c
new file mode 100644
index 000000000000..a3008b904f7d
--- /dev/null
+++ b/drivers/net/wimax/i2400m/sdio-rx.c
@@ -0,0 +1,255 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * SDIO RX handling
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Dirk Brandewie <dirk.j.brandewie@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * This handles the RX path on SDIO.
+ *
+ * The SDIO bus driver calls the "irq" routine when data is available.
+ * This is not a traditional interrupt routine since the SDIO bus
+ * driver calls us from its irq thread context.  Because of this
+ * sleeping in the SDIO RX IRQ routine is okay.
+ *
+ * From there on, we obtain the size of the data that is available,
+ * allocate an skb, copy it and then pass it to the generic driver's
+ * RX routine [i2400m_rx()].
+ *
+ * ROADMAP
+ *
+ * i2400ms_irq()
+ *   i2400ms_rx()
+ *     __i2400ms_rx_get_size()
+ *     i2400m_rx()
+ *
+ * i2400ms_rx_setup()
+ *
+ * i2400ms_rx_release()
+ */
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <linux/skbuff.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include "i2400m-sdio.h"
+
+#define D_SUBMODULE rx
+#include "sdio-debug-levels.h"
+
+
+/*
+ * Read and return the amount of bytes available for RX
+ *
+ * The RX size has to be read like this: byte reads of three
+ * sequential locations; then glue'em together.
+ *
+ * sdio_readl() doesn't work.
+ */
+ssize_t __i2400ms_rx_get_size(struct i2400ms *i2400ms)
+{
+        int ret, cnt, val;
+        ssize_t rx_size;
+        unsigned xfer_size_addr;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &i2400ms->func->dev;
+
+        d_fnstart(7, dev, "(i2400ms %p)\n", i2400ms);
+        xfer_size_addr = I2400MS_INTR_GET_SIZE_ADDR;
+        rx_size = 0;
+        for (cnt = 0; cnt < 3; cnt++) {
+                val = sdio_readb(func, xfer_size_addr + cnt, &ret);
+                if (ret < 0) {
+                        dev_err(dev, "RX: Can't read byte %d of RX size from "
+                                "0x%08x: %d\n", cnt, xfer_size_addr + cnt, ret);
+                        rx_size = ret;
+                        goto error_read;
+                }
+                rx_size = rx_size << 8 | (val & 0xff);
+        }
+        d_printf(6, dev, "RX: rx_size is %ld\n", (long) rx_size);
+error_read:
+        d_fnend(7, dev, "(i2400ms %p) = %ld\n", i2400ms, (long) rx_size);
+        return rx_size;
+}
+
+
+/*
+ * Read data from the device (when in normal)
+ *
+ * Allocate an SKB of the right size, read the data in and then
+ * deliver it to the generic layer.
+ *
+ * We also check for a reboot barker. That means the device died and
+ * we have to reboot it.
+ */
+static
+void i2400ms_rx(struct i2400ms *i2400ms)
+{
+        int ret;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+        struct i2400m *i2400m = &i2400ms->i2400m;
+        struct sk_buff *skb;
+        ssize_t rx_size;
+
+        d_fnstart(7, dev, "(i2400ms %p)\n", i2400ms);
+        rx_size = __i2400ms_rx_get_size(i2400ms);
+        if (rx_size < 0) {
+                ret = rx_size;
+                goto error_get_size;
+        }
+        ret = -ENOMEM;
+        skb = alloc_skb(rx_size, GFP_ATOMIC);
+        if (NULL == skb) {
+                dev_err(dev, "RX: unable to alloc skb\n");
+                goto error_alloc_skb;
+        }
+
+        ret = sdio_memcpy_fromio(func, skb->data,
+                                 I2400MS_DATA_ADDR, rx_size);
+        if (ret < 0) {
+                dev_err(dev, "RX: SDIO data read failed: %d\n", ret);
+                goto error_memcpy_fromio;
+        }
+        /* Check if device has reset */
+        if (!memcmp(skb->data, i2400m_NBOOT_BARKER,
+                    sizeof(i2400m_NBOOT_BARKER))
+            || !memcmp(skb->data, i2400m_SBOOT_BARKER,
+                       sizeof(i2400m_SBOOT_BARKER))) {
+                ret = i2400m_dev_reset_handle(i2400m);
+                kfree_skb(skb);
+        } else {
+                skb_put(skb, rx_size);
+                i2400m_rx(i2400m, skb);
+        }
+        d_fnend(7, dev, "(i2400ms %p) = void\n", i2400ms);
+        return;
+
+error_memcpy_fromio:
+        kfree_skb(skb);
+error_alloc_skb:
+error_get_size:
+        d_fnend(7, dev, "(i2400ms %p) = %d\n", i2400ms, ret);
+        return;
+}
+
+
+/*
+ * Process an interrupt from the SDIO card
+ *
+ * FIXME: need to process other events that are not just ready-to-read
+ *
+ * Checks there is data ready and then proceeds to read it.
+ */
+static
+void i2400ms_irq(struct sdio_func *func)
+{
+        int ret;
+        struct i2400ms *i2400ms = sdio_get_drvdata(func);
+        struct i2400m *i2400m = &i2400ms->i2400m;
+        struct device *dev = &func->dev;
+        int val;
+
+        d_fnstart(6, dev, "(i2400ms %p)\n", i2400ms);
+        val = sdio_readb(func, I2400MS_INTR_STATUS_ADDR, &ret);
+        if (ret < 0) {
+                dev_err(dev, "RX: Can't read interrupt status: %d\n", ret);
+                goto error_no_irq;
+        }
+        if (!val) {
+                dev_err(dev, "RX: BUG? got IRQ but no interrupt ready?\n");
+                goto error_no_irq;
+        }
+        sdio_writeb(func, 1, I2400MS_INTR_CLEAR_ADDR, &ret);
+        if (WARN_ON(i2400m->boot_mode != 0))
+                dev_err(dev, "RX: SW BUG? boot mode and IRQ is up?\n");
+        else
+                i2400ms_rx(i2400ms);
+error_no_irq:
+        d_fnend(6, dev, "(i2400ms %p) = void\n", i2400ms);
+        return;
+}
+
+
+/*
+ * Setup SDIO RX
+ *
+ * Hooks up the IRQ handler and then enables IRQs.
+ */
+int i2400ms_rx_setup(struct i2400ms *i2400ms)
+{
+        int result;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+
+        d_fnstart(5, dev, "(i2400ms %p)\n", i2400ms);
+        sdio_claim_host(func);
+        result = sdio_claim_irq(func, i2400ms_irq);
+        if (result < 0) {
+                dev_err(dev, "Cannot claim IRQ: %d\n", result);
+                goto error_irq_claim;
+        }
+        result = 0;
+        sdio_writeb(func, 1, I2400MS_INTR_ENABLE_ADDR, &result);
+        if (result < 0) {
+                sdio_release_irq(func);
+                dev_err(dev, "Failed to enable interrupts %d\n", result);
+        }
+error_irq_claim:
+        sdio_release_host(func);
+        d_fnend(5, dev, "(i2400ms %p) = %d\n", i2400ms, result);
+        return result;
+}
+
+
+/*
+ * Tear down SDIO RX
+ *
+ * Disables IRQs in the device and removes the IRQ handler.
+ */
+void i2400ms_rx_release(struct i2400ms *i2400ms)
+{
+        int result;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+
+        d_fnstart(5, dev, "(i2400ms %p)\n", i2400ms);
+        sdio_claim_host(func);
+        sdio_writeb(func, 0, I2400MS_INTR_ENABLE_ADDR, &result);
+        sdio_release_irq(func);
+        sdio_release_host(func);
+        d_fnend(5, dev, "(i2400ms %p) = %d\n", i2400ms, result);
+}
diff --git a/drivers/net/wimax/i2400m/sdio-tx.c b/drivers/net/wimax/i2400m/sdio-tx.c
new file mode 100644
index 000000000000..5105a5ebc44f
--- /dev/null
+++ b/drivers/net/wimax/i2400m/sdio-tx.c
@@ -0,0 +1,153 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * SDIO TX transaction backends
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Dirk Brandewie <dirk.j.brandewie@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * Takes the TX messages in the i2400m's driver TX FIFO and sends them
+ * to the device until there are no more.
+ *
+ * If we fail sending the message, we just drop it. There isn't much
+ * we can do at this point. Most of the traffic is network, which has
+ * recovery methods for dropped packets.
+ *
+ * The SDIO functions are not atomic, so we can't run from the context
+ * where i2400m->bus_tx_kick() [i2400ms_bus_tx_kick()] is being called
+ * (some times atomic). Thus, the actual TX work is deferred to a
+ * workqueue.
+ *
+ * ROADMAP
+ *
+ * i2400ms_bus_tx_kick()
+ *   i2400ms_tx_submit()     [through workqueue]
+ *
+ * i2400m_tx_setup()
+ *
+ * i2400m_tx_release()
+ */
+#include <linux/mmc/sdio_func.h>
+#include "i2400m-sdio.h"
+
+#define D_SUBMODULE tx
+#include "sdio-debug-levels.h"
+
+
+/*
+ * Pull TX transations from the TX FIFO and send them to the device
+ * until there are no more.
+ */
+static
+void i2400ms_tx_submit(struct work_struct *ws)
+{
+        int result;
+        struct i2400ms *i2400ms = container_of(ws, struct i2400ms, tx_worker);
+        struct i2400m *i2400m = &i2400ms->i2400m;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+        struct i2400m_msg_hdr *tx_msg;
+        size_t tx_msg_size;
+
+        d_fnstart(4, dev, "(i2400ms %p, i2400m %p)\n", i2400ms, i2400ms);
+
+        while (NULL != (tx_msg = i2400m_tx_msg_get(i2400m, &tx_msg_size))) {
+                d_printf(2, dev, "TX: submitting %zu bytes\n", tx_msg_size);
+                d_dump(5, dev, tx_msg, tx_msg_size);
+
+                sdio_claim_host(func);
+                result = sdio_memcpy_toio(func, 0, tx_msg, tx_msg_size);
+                sdio_release_host(func);
+
+                i2400m_tx_msg_sent(i2400m);
+
+                if (result < 0) {
+                        dev_err(dev, "TX: cannot submit TX; tx_msg @%zu %zu B:"
+                                " %d\n", (void *) tx_msg - i2400m->tx_buf,
+                                tx_msg_size, result);
+                }
+
+                d_printf(2, dev, "TX: %zub submitted\n", tx_msg_size);
+        }
+
+        d_fnend(4, dev, "(i2400ms %p) = void\n", i2400ms);
+}
+
+
+/*
+ * The generic driver notifies us that there is data ready for TX
+ *
+ * Schedule a run of i2400ms_tx_submit() to handle it.
+ */
+void i2400ms_bus_tx_kick(struct i2400m *i2400m)
+{
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        struct device *dev = &i2400ms->func->dev;
+
+        d_fnstart(3, dev, "(i2400m %p) = void\n", i2400m);
+
+        /* schedule tx work, this is because tx may block, therefore
+         * it has to run in a thread context.
+         */
+        queue_work(i2400ms->tx_workqueue, &i2400ms->tx_worker);
+
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+
+int i2400ms_tx_setup(struct i2400ms *i2400ms)
+{
+        int result;
+        struct device *dev = &i2400ms->func->dev;
+        struct i2400m *i2400m = &i2400ms->i2400m;
+
+        d_fnstart(5, dev, "(i2400ms %p)\n", i2400ms);
+
+        INIT_WORK(&i2400ms->tx_worker, i2400ms_tx_submit);
+        snprintf(i2400ms->tx_wq_name, sizeof(i2400ms->tx_wq_name),
+                 "%s-tx", i2400m->wimax_dev.name);
+        i2400ms->tx_workqueue =
+                create_singlethread_workqueue(i2400ms->tx_wq_name);
+        if (NULL == i2400ms->tx_workqueue) {
+                dev_err(dev, "TX: failed to create workqueue\n");
+                result = -ENOMEM;
+        } else
+                result = 0;
+        d_fnend(5, dev, "(i2400ms %p) = %d\n", i2400ms, result);
+        return result;
+}
+
+void i2400ms_tx_release(struct i2400ms *i2400ms)
+{
+        destroy_workqueue(i2400ms->tx_workqueue);
+}
diff --git a/drivers/net/wimax/i2400m/sdio.c b/drivers/net/wimax/i2400m/sdio.c
new file mode 100644
index 000000000000..1bfa283bbd8a
--- /dev/null
+++ b/drivers/net/wimax/i2400m/sdio.c
@@ -0,0 +1,511 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Linux driver model glue for the SDIO device, reset & fw upload
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Dirk Brandewie <dirk.j.brandewie@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * See i2400m-sdio.h for a general description of this driver.
+ *
+ * This file implements driver model glue, and hook ups for the
+ * generic driver to implement the bus-specific functions (device
+ * communication setup/tear down, firmware upload and resetting).
+ *
+ * ROADMAP
+ *
+ * i2400m_probe()
+ *   alloc_netdev()
+ *     i2400ms_netdev_setup()
+ *       i2400ms_init()
+ *       i2400m_netdev_setup()
+ *   i2400ms_enable_function()
+ *   i2400m_setup()
+ *
+ * i2400m_remove()
+ *     i2400m_release()
+ *     free_netdev(net_dev)
+ *
+ * i2400ms_bus_reset()            Called by i2400m->bus_reset
+ *   __i2400ms_reset()
+ *     __i2400ms_send_barker()
+ *
+ * i2400ms_bus_dev_start()        Called by i2400m_dev_start() [who is
+ *   i2400ms_tx_setup()           called by i2400m_setup()]
+ *   i2400ms_rx_setup()
+ *
+ * i2400ms_bus_dev_stop()         Called by i2400m_dev_stop() [who is
+ *   i2400ms_rx_release()         is called by i2400m_release()]
+ *   i2400ms_tx_release()
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include "i2400m-sdio.h"
+#include <linux/wimax/i2400m.h>
+
+#define D_SUBMODULE main
+#include "sdio-debug-levels.h"
+
+/* IOE WiMAX function timeout in seconds */
+static int ioe_timeout = 2;
+module_param(ioe_timeout, int, 0);
+
+/* Our firmware file name */
+#define I2400MS_FW_FILE_NAME "i2400m-fw-sdio-" I2400M_FW_VERSION ".sbcf"
+
+/*
+ * Enable the SDIO function
+ *
+ * Tries to enable the SDIO function; might fail if it is still not
+ * ready (in some hardware, the SDIO WiMAX function is only enabled
+ * when we ask it to explicitly doing). Tries until a timeout is
+ * reached.
+ *
+ * The reverse of this is...sdio_disable_function()
+ *
+ * Returns: 0 if the SDIO function was enabled, < 0 errno code on
+ *     error (-ENODEV when it was unable to enable the function).
+ */
+static
+int i2400ms_enable_function(struct sdio_func *func)
+{
+        u64 timeout;
+        int err;
+        struct device *dev = &func->dev;
+
+        d_fnstart(3, dev, "(func %p)\n", func);
+        /* Setup timeout (FIXME: This needs to read the CIS table to
+         * get a real timeout) and then wait for the device to signal
+         * it is ready */
+        timeout = get_jiffies_64() + ioe_timeout * HZ;
+        err = -ENODEV;
+        while (err != 0 && time_before64(get_jiffies_64(), timeout)) {
+                sdio_claim_host(func);
+                err = sdio_enable_func(func);
+                if (0 == err) {
+                        sdio_release_host(func);
+                        d_printf(2, dev, "SDIO function enabled\n");
+                        goto function_enabled;
+                }
+                d_printf(2, dev, "SDIO function failed to enable: %d\n", err);
+                sdio_disable_func(func);
+                sdio_release_host(func);
+                msleep(I2400MS_INIT_SLEEP_INTERVAL);
+        }
+        /* If timed out, device is not there yet -- get -ENODEV so
+         * the device driver core will retry later on. */
+        if (err == -ETIME) {
+                dev_err(dev, "Can't enable WiMAX function; "
+                        " has the function been enabled?\n");
+                err = -ENODEV;
+        }
+function_enabled:
+        d_fnend(3, dev, "(func %p) = %d\n", func, err);
+        return err;
+}
+
+
+/*
+ * Setup driver resources needed to communicate with the device
+ *
+ * The fw needs some time to settle, and it was just uploaded,
+ * so give it a break first. I'd prefer to just wait for the device to
+ * send something, but seems the poking we do to enable SDIO stuff
+ * interferes with it, so just give it a break before starting...
+ */
+static
+int i2400ms_bus_dev_start(struct i2400m *i2400m)
+{
+        int result;
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        msleep(200);
+        result = i2400ms_rx_setup(i2400ms);
+        if (result < 0)
+                goto error_rx_setup;
+        result = i2400ms_tx_setup(i2400ms);
+        if (result < 0)
+                goto error_tx_setup;
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+
+        i2400ms_tx_release(i2400ms);
+error_tx_setup:
+        i2400ms_rx_release(i2400ms);
+error_rx_setup:
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+        return result;
+}
+
+
+static
+void i2400ms_bus_dev_stop(struct i2400m *i2400m)
+{
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        i2400ms_rx_release(i2400ms);
+        i2400ms_tx_release(i2400ms);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+
+
+/*
+ * Sends a barker buffer to the device
+ *
+ * This helper will allocate a kmalloced buffer and use it to transmit
+ * (then free it). Reason for this is that the SDIO host controller
+ * expects alignment (unknown exactly which) which the stack won't
+ * really provide and certain arches/host-controller combinations
+ * cannot use stack/vmalloc/text areas for DMA transfers.
+ */
+static
+int __i2400ms_send_barker(struct i2400ms *i2400ms,
+                          const __le32 *barker, size_t barker_size)
+{
+        int  ret;
+        struct sdio_func *func = i2400ms->func;
+        struct device *dev = &func->dev;
+        void *buffer;
+
+        ret = -ENOMEM;
+        buffer = kmalloc(I2400MS_BLK_SIZE, GFP_KERNEL);
+        if (buffer == NULL)
+                goto error_kzalloc;
+
+        memcpy(buffer, barker, barker_size);
+        sdio_claim_host(func);
+        ret = sdio_memcpy_toio(func, 0, buffer, I2400MS_BLK_SIZE);
+        sdio_release_host(func);
+
+        if (ret < 0)
+                d_printf(0, dev, "E: barker error: %d\n", ret);
+
+        kfree(buffer);
+error_kzalloc:
+        return ret;
+}
+
+
+/*
+ * Reset a device at different levels (warm, cold or bus)
+ *
+ * @i2400ms: device descriptor
+ * @reset_type: soft, warm or bus reset (I2400M_RT_WARM/SOFT/BUS)
+ *
+ * FIXME: not tested -- need to confirm expected effects
+ *
+ * Warm and cold resets get an SDIO reset if they fail (unimplemented)
+ *
+ * Warm reset:
+ *
+ * The device will be fully reset internally, but won't be
+ * disconnected from the USB bus (so no reenumeration will
+ * happen). Firmware upload will be neccessary.
+ *
+ * The device will send a reboot barker in the notification endpoint
+ * that will trigger the driver to reinitialize the state
+ * automatically from notif.c:i2400m_notification_grok() into
+ * i2400m_dev_bootstrap_delayed().
+ *
+ * Cold and bus (USB) reset:
+ *
+ * The device will be fully reset internally, disconnected from the
+ * USB bus an a reenumeration will happen. Firmware upload will be
+ * neccessary. Thus, we don't do any locking or struct
+ * reinitialization, as we are going to be fully disconnected and
+ * reenumerated.
+ *
+ * Note we need to return -ENODEV if a warm reset was requested and we
+ * had to resort to a bus reset. See i2400m_op_reset(), wimax_reset()
+ * and wimax_dev->op_reset.
+ *
+ * WARNING: no driver state saved/fixed
+ */
+static
+int i2400ms_bus_reset(struct i2400m *i2400m, enum i2400m_reset_type rt)
+{
+        int result;
+        struct i2400ms *i2400ms =
+                container_of(i2400m, struct i2400ms, i2400m);
+        struct device *dev = i2400m_dev(i2400m);
+        static const __le32 i2400m_WARM_BOOT_BARKER[4] = {
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+        };
+        static const __le32 i2400m_COLD_BOOT_BARKER[4] = {
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+        };
+
+        if (rt == I2400M_RT_WARM)
+                result = __i2400ms_send_barker(i2400ms, i2400m_WARM_BOOT_BARKER,
+                                               sizeof(i2400m_WARM_BOOT_BARKER));
+        else if (rt == I2400M_RT_COLD)
+                result = __i2400ms_send_barker(i2400ms, i2400m_COLD_BOOT_BARKER,
+                                               sizeof(i2400m_COLD_BOOT_BARKER));
+        else if (rt == I2400M_RT_BUS) {
+do_bus_reset:
+                dev_err(dev, "FIXME: SDIO bus reset not implemented\n");
+                result = rt == I2400M_RT_WARM ? -ENODEV : -ENOSYS;
+        } else
+                BUG();
+        if (result < 0 && rt != I2400M_RT_BUS) {
+                dev_err(dev, "%s reset failed (%d); trying SDIO reset\n",
+                        rt == I2400M_RT_WARM ? "warm" : "cold", result);
+                rt = I2400M_RT_BUS;
+                goto do_bus_reset;
+        }
+        return result;
+}
+
+
+static
+void i2400ms_netdev_setup(struct net_device *net_dev)
+{
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct i2400ms *i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        i2400ms_init(i2400ms);
+        i2400m_netdev_setup(net_dev);
+}
+
+
+/*
+ * Debug levels control; see debug.h
+ */
+struct d_level D_LEVEL[] = {
+        D_SUBMODULE_DEFINE(main),
+        D_SUBMODULE_DEFINE(tx),
+        D_SUBMODULE_DEFINE(rx),
+        D_SUBMODULE_DEFINE(fw),
+};
+size_t D_LEVEL_SIZE = ARRAY_SIZE(D_LEVEL);
+
+
+#define __debugfs_register(prefix, name, parent)                        \
+do {                                                                    \
+        result = d_level_register_debugfs(prefix, name, parent);        \
+        if (result < 0)                                                 \
+                goto error;                                             \
+} while (0)
+
+
+static
+int i2400ms_debugfs_add(struct i2400ms *i2400ms)
+{
+        int result;
+        struct dentry *dentry = i2400ms->i2400m.wimax_dev.debugfs_dentry;
+
+        dentry = debugfs_create_dir("i2400m-usb", dentry);
+        result = PTR_ERR(dentry);
+        if (IS_ERR(dentry)) {
+                if (result == -ENODEV)
+                        result = 0;     /* No debugfs support */
+                goto error;
+        }
+        i2400ms->debugfs_dentry = dentry;
+        __debugfs_register("dl_", main, dentry);
+        __debugfs_register("dl_", tx, dentry);
+        __debugfs_register("dl_", rx, dentry);
+        __debugfs_register("dl_", fw, dentry);
+
+        return 0;
+
+error:
+        debugfs_remove_recursive(i2400ms->debugfs_dentry);
+        return result;
+}
+
+
+/*
+ * Probe a i2400m interface and register it
+ *
+ * @func:    SDIO function
+ * @id:      SDIO device ID
+ * @returns: 0 if ok, < 0 errno code on error.
+ *
+ * Alloc a net device, initialize the bus-specific details and then
+ * calls the bus-generic initialization routine. That will register
+ * the wimax and netdev devices, upload the firmware [using
+ * _bus_bm_*()], call _bus_dev_start() to finalize the setup of the
+ * communication with the device and then will start to talk to it to
+ * finnish setting it up.
+ *
+ * Initialization is tricky; some instances of the hw are packed with
+ * others in a way that requires a third driver that enables the WiMAX
+ * function. In those cases, we can't enable the SDIO function and
+ * we'll return with -ENODEV. When the driver that enables the WiMAX
+ * function does its thing, it has to do a bus_rescan_devices() on the
+ * SDIO bus so this driver is called again to enumerate the WiMAX
+ * function.
+ */
+static
+int i2400ms_probe(struct sdio_func *func,
+                  const struct sdio_device_id *id)
+{
+        int result;
+        struct net_device *net_dev;
+        struct device *dev = &func->dev;
+        struct i2400m *i2400m;
+        struct i2400ms *i2400ms;
+
+        /* Allocate instance [calls i2400m_netdev_setup() on it]. */
+        result = -ENOMEM;
+        net_dev = alloc_netdev(sizeof(*i2400ms), "wmx%d",
+                               i2400ms_netdev_setup);
+        if (net_dev == NULL) {
+                dev_err(dev, "no memory for network device instance\n");
+                goto error_alloc_netdev;
+        }
+        SET_NETDEV_DEV(net_dev, dev);
+        i2400m = net_dev_to_i2400m(net_dev);
+        i2400ms = container_of(i2400m, struct i2400ms, i2400m);
+        i2400m->wimax_dev.net_dev = net_dev;
+        i2400ms->func = func;
+        sdio_set_drvdata(func, i2400ms);
+
+        i2400m->bus_tx_block_size = I2400MS_BLK_SIZE;
+        i2400m->bus_pl_size_max = I2400MS_PL_SIZE_MAX;
+        i2400m->bus_dev_start = i2400ms_bus_dev_start;
+        i2400m->bus_dev_stop = i2400ms_bus_dev_stop;
+        i2400m->bus_tx_kick = i2400ms_bus_tx_kick;
+        i2400m->bus_reset = i2400ms_bus_reset;
+        i2400m->bus_bm_cmd_send = i2400ms_bus_bm_cmd_send;
+        i2400m->bus_bm_wait_for_ack = i2400ms_bus_bm_wait_for_ack;
+        i2400m->bus_fw_name = I2400MS_FW_FILE_NAME;
+        i2400m->bus_bm_mac_addr_impaired = 1;
+
+        result = i2400ms_enable_function(i2400ms->func);
+        if (result < 0) {
+                dev_err(dev, "Cannot enable SDIO function: %d\n", result);
+                goto error_func_enable;
+        }
+
+        sdio_claim_host(func);
+        result = sdio_set_block_size(func, I2400MS_BLK_SIZE);
+        if (result < 0) {
+                dev_err(dev, "Failed to set block size: %d\n", result);
+                goto error_set_blk_size;
+        }
+        sdio_release_host(func);
+
+        result = i2400m_setup(i2400m, I2400M_BRI_NO_REBOOT);
+        if (result < 0) {
+                dev_err(dev, "cannot setup device: %d\n", result);
+                goto error_setup;
+        }
+
+        result = i2400ms_debugfs_add(i2400ms);
+        if (result < 0) {
+                dev_err(dev, "cannot create SDIO debugfs: %d\n",
+                        result);
+                goto error_debugfs_add;
+        }
+        return 0;
+
+error_debugfs_add:
+        i2400m_release(i2400m);
+error_setup:
+        sdio_set_drvdata(func, NULL);
+        sdio_claim_host(func);
+error_set_blk_size:
+        sdio_disable_func(func);
+        sdio_release_host(func);
+error_func_enable:
+        free_netdev(net_dev);
+error_alloc_netdev:
+        return result;
+}
+
+
+static
+void i2400ms_remove(struct sdio_func *func)
+{
+        struct device *dev = &func->dev;
+        struct i2400ms *i2400ms = sdio_get_drvdata(func);
+        struct i2400m *i2400m = &i2400ms->i2400m;
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+
+        d_fnstart(3, dev, "SDIO func %p\n", func);
+        debugfs_remove_recursive(i2400ms->debugfs_dentry);
+        i2400m_release(i2400m);
+        sdio_set_drvdata(func, NULL);
+        sdio_claim_host(func);
+        sdio_disable_func(func);
+        sdio_release_host(func);
+        free_netdev(net_dev);
+        d_fnend(3, dev, "SDIO func %p\n", func);
+}
+
+enum {
+        I2400MS_INTEL_VID = 0x89,
+};
+
+static
+const struct sdio_device_id i2400ms_sdio_ids[] = {
+        /* Intel: i2400m WiMAX over SDIO */
+        { SDIO_DEVICE(I2400MS_INTEL_VID, 0x1402) },
+        { },                    /* end: all zeroes */
+};
+MODULE_DEVICE_TABLE(sdio, i2400ms_sdio_ids);
+
+
+static
+struct sdio_driver i2400m_sdio_driver = {
+        .name           = KBUILD_MODNAME,
+        .probe          = i2400ms_probe,
+        .remove         = i2400ms_remove,
+        .id_table       = i2400ms_sdio_ids,
+};
+
+
+static
+int __init i2400ms_driver_init(void)
+{
+        return sdio_register_driver(&i2400m_sdio_driver);
+}
+module_init(i2400ms_driver_init);
+
+
+static
+void __exit i2400ms_driver_exit(void)
+{
+        flush_scheduled_work(); /* for the stuff we schedule */
+        sdio_unregister_driver(&i2400m_sdio_driver);
+}
+module_exit(i2400ms_driver_exit);
+
+
+MODULE_AUTHOR("Intel Corporation <linux-wimax@intel.com>");
+MODULE_DESCRIPTION("Intel 2400M WiMAX networking for SDIO");
+MODULE_LICENSE("GPL");
+MODULE_FIRMWARE(I2400MS_FW_FILE_NAME);
diff --git a/drivers/net/wimax/i2400m/tx.c b/drivers/net/wimax/i2400m/tx.c
new file mode 100644
index 000000000000..613a88ffd651
--- /dev/null
+++ b/drivers/net/wimax/i2400m/tx.c
@@ -0,0 +1,817 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Generic (non-bus specific) TX handling
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Rewritten to use a single FIFO to lower the memory allocation
+ *    pressure and optimize cache hits when copying to the queue, as
+ *    well as splitting out bus-specific code.
+ *
+ *
+ * Implements data transmission to the device; this is done through a
+ * software FIFO, as data/control frames can be coalesced (while the
+ * device is reading the previous tx transaction, others accumulate).
+ *
+ * A FIFO is used because at the end it is resource-cheaper that trying
+ * to implement scatter/gather over USB. As well, most traffic is going
+ * to be download (vs upload).
+ *
+ * The format for sending/receiving data to/from the i2400m is
+ * described in detail in rx.c:PROTOCOL FORMAT. In here we implement
+ * the transmission of that. This is split between a bus-independent
+ * part that just prepares everything and a bus-specific part that
+ * does the actual transmission over the bus to the device (in the
+ * bus-specific driver).
+ *
+ *
+ * The general format of a device-host transaction is MSG-HDR, PLD1,
+ * PLD2...PLDN, PL1, PL2,...PLN, PADDING.
+ *
+ * Because we need the send payload descriptors and then payloads and
+ * because it is kind of expensive to do scatterlists in USB (one URB
+ * per node), it becomes cheaper to append all the data to a FIFO
+ * (copying to a FIFO potentially in cache is cheaper).
+ *
+ * Then the bus-specific code takes the parts of that FIFO that are
+ * written and passes them to the device.
+ *
+ * So the concepts to keep in mind there are:
+ *
+ * We use a FIFO to queue the data in a linear buffer. We first append
+ * a MSG-HDR, space for I2400M_TX_PLD_MAX payload descriptors and then
+ * go appending payloads until we run out of space or of payload
+ * descriptors. Then we append padding to make the whole transaction a
+ * multiple of i2400m->bus_tx_block_size (as defined by the bus layer).
+ *
+ * - A TX message: a combination of a message header, payload
+ *   descriptors and payloads.
+ *
+ *     Open: it is marked as active (i2400m->tx_msg is valid) and we
+ *       can keep adding payloads to it.
+ *
+ *     Closed: we are not appending more payloads to this TX message
+ *       (exahusted space in the queue, too many payloads or
+ *       whichever).  We have appended padding so the whole message
+ *       length is aligned to i2400m->bus_tx_block_size (as set by the
+ *       bus/transport layer).
+ *
+ * - Most of the time we keep a TX message open to which we append
+ *   payloads.
+ *
+ * - If we are going to append and there is no more space (we are at
+ *   the end of the FIFO), we close the message, mark the rest of the
+ *   FIFO space unusable (skip_tail), create a new message at the
+ *   beginning of the FIFO (if there is space) and append the message
+ *   there.
+ *
+ *   This is because we need to give linear TX messages to the bus
+ *   engine. So we don't write a message to the remaining FIFO space
+ *   until the tail and continue at the head of it.
+ *
+ * - We overload one of the fields in the message header to use it as
+ *   'size' of the TX message, so we can iterate over them. It also
+ *   contains a flag that indicates if we have to skip it or not.
+ *   When we send the buffer, we update that to its real on-the-wire
+ *   value.
+ *
+ * - The MSG-HDR PLD1...PLD2 stuff has to be a size multiple of 16.
+ *
+ *   It follows that if MSG-HDR says we have N messages, the whole
+ *   header + descriptors is 16 + 4*N; for those to be a multiple of
+ *   16, it follows that N can be 4, 8, 12, ... (32, 48, 64, 80...
+ *   bytes).
+ *
+ *   So if we have only 1 payload, we have to submit a header that in
+ *   all truth has space for 4.
+ *
+ *   The implication is that we reserve space for 12 (64 bytes); but
+ *   if we fill up only (eg) 2, our header becomes 32 bytes only. So
+ *   the TX engine has to shift those 32 bytes of msg header and 2
+ *   payloads and padding so that right after it the payloads start
+ *   and the TX engine has to know about that.
+ *
+ *   It is cheaper to move the header up than the whole payloads down.
+ *
+ *   We do this in i2400m_tx_close(). See 'i2400m_msg_hdr->offset'.
+ *
+ * - Each payload has to be size-padded to 16 bytes; before appending
+ *   it, we just do it.
+ *
+ * - The whole message has to be padded to i2400m->bus_tx_block_size;
+ *   we do this at close time. Thus, when reserving space for the
+ *   payload, we always make sure there is also free space for this
+ *   padding that sooner or later will happen.
+ *
+ * When we append a message, we tell the bus specific code to kick in
+ * TXs. It will TX (in parallel) until the buffer is exhausted--hence
+ * the lockin we do. The TX code will only send a TX message at the
+ * time (which remember, might contain more than one payload). Of
+ * course, when the bus-specific driver attempts to TX a message that
+ * is still open, it gets closed first.
+ *
+ * Gee, this is messy; well a picture. In the example below we have a
+ * partially full FIFO, with a closed message ready to be delivered
+ * (with a moved message header to make sure it is size-aligned to
+ * 16), TAIL room that was unusable (and thus is marked with a message
+ * header that says 'skip this') and at the head of the buffer, an
+ * imcomplete message with a couple of payloads.
+ *
+ * N   ___________________________________________________
+ *    |                                                   |
+ *    |     TAIL room                                     |
+ *    |                                                   |
+ *    |  msg_hdr to skip (size |= 0x80000)                |
+ *    |---------------------------------------------------|-------
+ *    |                                                   |  /|\
+ *    |                                                   |   |
+ *    |  TX message padding                               |   |
+ *    |                                                   |   |
+ *    |                                                   |   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|   |
+ *    |                                                   |   |
+ *    |  payload 1                                        |   |
+ *    |                                                   | N * tx_block_size
+ *    |                                                   |   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|   |
+ *    |                                                   |   |
+ *    |  payload 1                                        |   |
+ *    |                                                   |   |
+ *    |                                                   |   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|- -|- - - -
+ *    |  padding 3                  /|\                   |   |   /|\
+ *    |  padding 2                   |                    |   |    |
+ *    |  pld 1                32 bytes (2 * 16)           |   |    |
+ *    |  pld 0                       |                    |   |    |
+ *    |  moved msg_hdr              \|/                   |  \|/   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|- - -   |
+ *    |                                                   |    _PLD_SIZE
+ *    |  unused                                           |        |
+ *    |                                                   |        |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|        |
+ *    |  msg_hdr (size X)       [this message is closed]  |       \|/
+ *    |===================================================|========== <=== OUT
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |          Free rooom                               |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |===================================================|========== <=== IN
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |                                                   |
+ *    |  payload 1                                        |
+ *    |                                                   |
+ *    |                                                   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|
+ *    |                                                   |
+ *    |  payload 0                                        |
+ *    |                                                   |
+ *    |                                                   |
+ *    |- - - - - - - - - - - - - - - - - - - - - - - - - -|
+ *    |  pld 11                     /|\                   |
+ *    |  ...                         |                    |
+ *    |  pld 1                64 bytes (2 * 16)           |
+ *    |  pld 0                       |                    |
+ *    |  msg_hdr (size X)           \|/ [message is open] |
+ * 0   ---------------------------------------------------
+ *
+ *
+ * ROADMAP
+ *
+ * i2400m_tx_setup()           Called by i2400m_setup
+ * i2400m_tx_release()         Called by i2400m_release()
+ *
+ *  i2400m_tx()                 Called to send data or control frames
+ *    i2400m_tx_fifo_push()     Allocates append-space in the FIFO
+ *    i2400m_tx_new()           Opens a new message in the FIFO
+ *    i2400m_tx_fits()          Checks if a new payload fits in the message
+ *    i2400m_tx_close()         Closes an open message in the FIFO
+ *    i2400m_tx_skip_tail()     Marks unusable FIFO tail space
+ *    i2400m->bus_tx_kick()
+ *
+ * Now i2400m->bus_tx_kick() is the the bus-specific driver backend
+ * implementation; that would do:
+ *
+ * i2400m->bus_tx_kick()
+ *   i2400m_tx_msg_get()        Gets first message ready to go
+ *   ...sends it...
+ *   i2400m_tx_msg_sent()       Ack the message is sent; repeat from
+ *                              _tx_msg_get() until it returns NULL
+ *                               (FIFO empty).
+ */
+#include <linux/netdevice.h>
+#include "i2400m.h"
+
+
+#define D_SUBMODULE tx
+#include "debug-levels.h"
+
+enum {
+        /**
+         * TX Buffer size
+         *
+         * Doc says maximum transaction is 16KiB. If we had 16KiB en
+         * route and 16KiB being queued, it boils down to needing
+         * 32KiB.
+         */
+        I2400M_TX_BUF_SIZE = 32768,
+        /**
+         * Message header and payload descriptors have to be 16
+         * aligned (16 + 4 * N = 16 * M). If we take that average sent
+         * packets are MTU size (~1400-~1500) it follows that we could
+         * fit at most 10-11 payloads in one transaction. To meet the
+         * alignment requirement, that means we need to leave space
+         * for 12 (64 bytes). To simplify, we leave space for that. If
+         * at the end there are less, we pad up to the nearest
+         * multiple of 16.
+         */
+        I2400M_TX_PLD_MAX = 12,
+        I2400M_TX_PLD_SIZE = sizeof(struct i2400m_msg_hdr)
+        + I2400M_TX_PLD_MAX * sizeof(struct i2400m_pld),
+        I2400M_TX_SKIP = 0x80000000,
+};
+
+#define TAIL_FULL ((void *)~(unsigned long)NULL)
+
+/*
+ * Allocate @size bytes in the TX fifo, return a pointer to it
+ *
+ * @i2400m: device descriptor
+ * @size: size of the buffer we need to allocate
+ * @padding: ensure that there is at least this many bytes of free
+ *     contiguous space in the fifo. This is needed because later on
+ *     we might need to add padding.
+ *
+ * Returns:
+ *
+ *     Pointer to the allocated space. NULL if there is no
+ *     space. TAIL_FULL if there is no space at the tail but there is at
+ *     the head (Case B below).
+ *
+ * These are the two basic cases we need to keep an eye for -- it is
+ * much better explained in linux/kernel/kfifo.c, but this code
+ * basically does the same. No rocket science here.
+ *
+ *       Case A               Case B
+ * N  ___________          ___________
+ *   | tail room |        |   data    |
+ *   |           |        |           |
+ *   |<-  IN   ->|        |<-  OUT  ->|
+ *   |           |        |           |
+ *   |   data    |        |   room    |
+ *   |           |        |           |
+ *   |<-  OUT  ->|        |<-  IN   ->|
+ *   |           |        |           |
+ *   | head room |        |   data    |
+ * 0  -----------          -----------
+ *
+ * We allocate only *contiguous* space.
+ *
+ * We can allocate only from 'room'. In Case B, it is simple; in case
+ * A, we only try from the tail room; if it is not enough, we just
+ * fail and return TAIL_FULL and let the caller figure out if we wants to
+ * skip the tail room and try to allocate from the head.
+ *
+ * Note:
+ *
+ *     Assumes i2400m->tx_lock is taken, and we use that as a barrier
+ *
+ *     The indexes keep increasing and we reset them to zero when we
+ *     pop data off the queue
+ */
+static
+void *i2400m_tx_fifo_push(struct i2400m *i2400m, size_t size, size_t padding)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        size_t room, tail_room, needed_size;
+        void *ptr;
+
+        needed_size = size + padding;
+        room = I2400M_TX_BUF_SIZE - (i2400m->tx_in - i2400m->tx_out);
+        if (room < needed_size) { /* this takes care of Case B */
+                d_printf(2, dev, "fifo push %zu/%zu: no space\n",
+                         size, padding);
+                return NULL;
+        }
+        /* Is there space at the tail? */
+        tail_room = I2400M_TX_BUF_SIZE - i2400m->tx_in % I2400M_TX_BUF_SIZE;
+        if (tail_room < needed_size) {
+                if (i2400m->tx_out % I2400M_TX_BUF_SIZE
+                    < i2400m->tx_in % I2400M_TX_BUF_SIZE) {
+                        d_printf(2, dev, "fifo push %zu/%zu: tail full\n",
+                                 size, padding);
+                        return TAIL_FULL;       /* There might be head space */
+                } else {
+                        d_printf(2, dev, "fifo push %zu/%zu: no head space\n",
+                                 size, padding);
+                        return NULL;    /* There is no space */
+                }
+        }
+        ptr = i2400m->tx_buf + i2400m->tx_in % I2400M_TX_BUF_SIZE;
+        d_printf(2, dev, "fifo push %zu/%zu: at @%zu\n", size, padding,
+                 i2400m->tx_in % I2400M_TX_BUF_SIZE);
+        i2400m->tx_in += size;
+        return ptr;
+}
+
+
+/*
+ * Mark the tail of the FIFO buffer as 'to-skip'
+ *
+ * We should never hit the BUG_ON() because all the sizes we push to
+ * the FIFO are padded to be a multiple of 16 -- the size of *msg
+ * (I2400M_PL_PAD for the payloads, I2400M_TX_PLD_SIZE for the
+ * header).
+ *
+ * Note:
+ *
+ *     Assumes i2400m->tx_lock is taken, and we use that as a barrier
+ */
+static
+void i2400m_tx_skip_tail(struct i2400m *i2400m)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        size_t tx_in = i2400m->tx_in % I2400M_TX_BUF_SIZE;
+        size_t tail_room = I2400M_TX_BUF_SIZE - tx_in;
+        struct i2400m_msg_hdr *msg = i2400m->tx_buf + tx_in;
+        BUG_ON(tail_room < sizeof(*msg));
+        msg->size = tail_room | I2400M_TX_SKIP;
+        d_printf(2, dev, "skip tail: skipping %zu bytes @%zu\n",
+                 tail_room, tx_in);
+        i2400m->tx_in += tail_room;
+}
+
+
+/*
+ * Check if a skb will fit in the TX queue's current active TX
+ * message (if there are still descriptors left unused).
+ *
+ * Returns:
+ *     0 if the message won't fit, 1 if it will.
+ *
+ * Note:
+ *
+ *     Assumes a TX message is active (i2400m->tx_msg).
+ *
+ *     Assumes i2400m->tx_lock is taken, and we use that as a barrier
+ */
+static
+unsigned i2400m_tx_fits(struct i2400m *i2400m)
+{
+        struct i2400m_msg_hdr *msg_hdr = i2400m->tx_msg;
+        return le16_to_cpu(msg_hdr->num_pls) < I2400M_TX_PLD_MAX;
+
+}
+
+
+/*
+ * Start a new TX message header in the queue.
+ *
+ * Reserve memory from the base FIFO engine and then just initialize
+ * the message header.
+ *
+ * We allocate the biggest TX message header we might need (one that'd
+ * fit I2400M_TX_PLD_MAX payloads) -- when it is closed it will be
+ * 'ironed it out' and the unneeded parts removed.
+ *
+ * NOTE:
+ *
+ *     Assumes that the previous message is CLOSED (eg: either
+ *     there was none or 'i2400m_tx_close()' was called on it).
+ *
+ *     Assumes i2400m->tx_lock is taken, and we use that as a barrier
+ */
+static
+void i2400m_tx_new(struct i2400m *i2400m)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_msg_hdr *tx_msg;
+        BUG_ON(i2400m->tx_msg != NULL);
+try_head:
+        tx_msg = i2400m_tx_fifo_push(i2400m, I2400M_TX_PLD_SIZE, 0);
+        if (tx_msg == NULL)
+                goto out;
+        else if (tx_msg == TAIL_FULL) {
+                i2400m_tx_skip_tail(i2400m);
+                d_printf(2, dev, "new TX message: tail full, trying head\n");
+                goto try_head;
+        }
+        memset(tx_msg, 0, I2400M_TX_PLD_SIZE);
+        tx_msg->size = I2400M_TX_PLD_SIZE;
+out:
+        i2400m->tx_msg = tx_msg;
+        d_printf(2, dev, "new TX message: %p @%zu\n",
+                 tx_msg, (void *) tx_msg - i2400m->tx_buf);
+}
+
+
+/*
+ * Finalize the current TX message header
+ *
+ * Sets the message header to be at the proper location depending on
+ * how many descriptors we have (check documentation at the file's
+ * header for more info on that).
+ *
+ * Appends padding bytes to make sure the whole TX message (counting
+ * from the 'relocated' message header) is aligned to
+ * tx_block_size. We assume the _append() code has left enough space
+ * in the FIFO for that. If there are no payloads, just pass, as it
+ * won't be transferred.
+ *
+ * The amount of padding bytes depends on how many payloads are in the
+ * TX message, as the "msg header and payload descriptors" will be
+ * shifted up in the buffer.
+ */
+static
+void i2400m_tx_close(struct i2400m *i2400m)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_msg_hdr *tx_msg = i2400m->tx_msg;
+        struct i2400m_msg_hdr *tx_msg_moved;
+        size_t aligned_size, padding, hdr_size;
+        void *pad_buf;
+
+        if (tx_msg->size & I2400M_TX_SKIP)      /* a skipper? nothing to do */
+                goto out;
+
+        /* Relocate the message header
+         *
+         * Find the current header size, align it to 16 and if we need
+         * to move it so the tail is next to the payloads, move it and
+         * set the offset.
+         *
+         * If it moved, this header is good only for transmission; the
+         * original one (it is kept if we moved) is still used to
+         * figure out where the next TX message starts (and where the
+         * offset to the moved header is).
+         */
+        hdr_size = sizeof(*tx_msg)
+                + le16_to_cpu(tx_msg->num_pls) * sizeof(tx_msg->pld[0]);
+        hdr_size = ALIGN(hdr_size, I2400M_PL_PAD);
+        tx_msg->offset = I2400M_TX_PLD_SIZE - hdr_size;
+        tx_msg_moved = (void *) tx_msg + tx_msg->offset;
+        memmove(tx_msg_moved, tx_msg, hdr_size);
+        tx_msg_moved->size -= tx_msg->offset;
+        /*
+         * Now figure out how much we have to add to the (moved!)
+         * message so the size is a multiple of i2400m->bus_tx_block_size.
+         */
+        aligned_size = ALIGN(tx_msg_moved->size, i2400m->bus_tx_block_size);
+        padding = aligned_size - tx_msg_moved->size;
+        if (padding > 0) {
+                pad_buf = i2400m_tx_fifo_push(i2400m, padding, 0);
+                if (unlikely(WARN_ON(pad_buf == NULL
+                                     || pad_buf == TAIL_FULL))) {
+                        /* This should not happen -- append should verify
+                         * there is always space left at least to append
+                         * tx_block_size */
+                        dev_err(dev,
+                                "SW BUG! Possible data leakage from memory the "
+                                "device should not read for padding - "
+                                "size %lu aligned_size %zu tx_buf %p in "
+                                "%zu out %zu\n",
+                                (unsigned long) tx_msg_moved->size,
+                                aligned_size, i2400m->tx_buf, i2400m->tx_in,
+                                i2400m->tx_out);
+                } else
+                        memset(pad_buf, 0xad, padding);
+        }
+        tx_msg_moved->padding = cpu_to_le16(padding);
+        tx_msg_moved->size += padding;
+        if (tx_msg != tx_msg_moved)
+                tx_msg->size += padding;
+out:
+        i2400m->tx_msg = NULL;
+}
+
+
+/**
+ * i2400m_tx - send the data in a buffer to the device
+ *
+ * @buf: pointer to the buffer to transmit
+ *
+ * @buf_len: buffer size
+ *
+ * @pl_type: type of the payload we are sending.
+ *
+ * Returns:
+ *     0 if ok, < 0 errno code on error (-ENOSPC, if there is no more
+ *     room for the message in the queue).
+ *
+ * Appends the buffer to the TX FIFO and notifies the bus-specific
+ * part of the driver that there is new data ready to transmit.
+ * Once this function returns, the buffer has been copied, so it can
+ * be reused.
+ *
+ * The steps followed to append are explained in detail in the file
+ * header.
+ *
+ * Whenever we write to a message, we increase msg->size, so it
+ * reflects exactly how big the message is. This is needed so that if
+ * we concatenate two messages before they can be sent, the code that
+ * sends the messages can find the boundaries (and it will replace the
+ * size with the real barker before sending).
+ *
+ * Note:
+ *
+ *     Cold and warm reset payloads need to be sent as a single
+ *     payload, so we handle that.
+ */
+int i2400m_tx(struct i2400m *i2400m, const void *buf, size_t buf_len,
+              enum i2400m_pt pl_type)
+{
+        int result = -ENOSPC;
+        struct device *dev = i2400m_dev(i2400m);
+        unsigned long flags;
+        size_t padded_len;
+        void *ptr;
+        unsigned is_singleton = pl_type == I2400M_PT_RESET_WARM
+                || pl_type == I2400M_PT_RESET_COLD;
+
+        d_fnstart(3, dev, "(i2400m %p skb %p [%zu bytes] pt %u)\n",
+                  i2400m, buf, buf_len, pl_type);
+        padded_len = ALIGN(buf_len, I2400M_PL_PAD);
+        d_printf(5, dev, "padded_len %zd buf_len %zd\n", padded_len, buf_len);
+        /* If there is no current TX message, create one; if the
+         * current one is out of payload slots or we have a singleton,
+         * close it and start a new one */
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+try_new:
+        if (unlikely(i2400m->tx_msg == NULL))
+                i2400m_tx_new(i2400m);
+        else if (unlikely(!i2400m_tx_fits(i2400m)
+                          || (is_singleton && i2400m->tx_msg->num_pls != 0))) {
+                d_printf(2, dev, "closing TX message (fits %u singleton "
+                         "%u num_pls %u)\n", i2400m_tx_fits(i2400m),
+                         is_singleton, i2400m->tx_msg->num_pls);
+                i2400m_tx_close(i2400m);
+                i2400m_tx_new(i2400m);
+        }
+        if (i2400m->tx_msg->size + padded_len > I2400M_TX_BUF_SIZE / 2) {
+                d_printf(2, dev, "TX: message too big, going new\n");
+                i2400m_tx_close(i2400m);
+                i2400m_tx_new(i2400m);
+        }
+        if (i2400m->tx_msg == NULL)
+                goto error_tx_new;
+        /* So we have a current message header; now append space for
+         * the message -- if there is not enough, try the head */
+        ptr = i2400m_tx_fifo_push(i2400m, padded_len,
+                                  i2400m->bus_tx_block_size);
+        if (ptr == TAIL_FULL) { /* Tail is full, try head */
+                d_printf(2, dev, "pl append: tail full\n");
+                i2400m_tx_close(i2400m);
+                i2400m_tx_skip_tail(i2400m);
+                goto try_new;
+        } else if (ptr == NULL) {       /* All full */
+                result = -ENOSPC;
+                d_printf(2, dev, "pl append: all full\n");
+        } else {                        /* Got space, copy it, set padding */
+                struct i2400m_msg_hdr *tx_msg = i2400m->tx_msg;
+                unsigned num_pls = le16_to_cpu(tx_msg->num_pls);
+                memcpy(ptr, buf, buf_len);
+                memset(ptr + buf_len, 0xad, padded_len - buf_len);
+                i2400m_pld_set(&tx_msg->pld[num_pls], buf_len, pl_type);
+                d_printf(3, dev, "pld 0x%08x (type 0x%1x len 0x%04zx\n",
+                         le32_to_cpu(tx_msg->pld[num_pls].val),
+                         pl_type, buf_len);
+                tx_msg->num_pls = le16_to_cpu(num_pls+1);
+                tx_msg->size += padded_len;
+                d_printf(2, dev, "TX: appended %zu b (up to %u b) pl #%u \n",
+                        padded_len, tx_msg->size, num_pls+1);
+                d_printf(2, dev,
+                         "TX: appended hdr @%zu %zu b pl #%u @%zu %zu/%zu b\n",
+                         (void *)tx_msg - i2400m->tx_buf, (size_t)tx_msg->size,
+                         num_pls+1, ptr - i2400m->tx_buf, buf_len, padded_len);
+                result = 0;
+                if (is_singleton)
+                        i2400m_tx_close(i2400m);
+        }
+error_tx_new:
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        i2400m->bus_tx_kick(i2400m);    /* always kick, might free up space */
+        d_fnend(3, dev, "(i2400m %p skb %p [%zu bytes] pt %u) = %d\n",
+                i2400m, buf, buf_len, pl_type, result);
+        return result;
+}
+EXPORT_SYMBOL_GPL(i2400m_tx);
+
+
+/**
+ * i2400m_tx_msg_get - Get the first TX message in the FIFO to start sending it
+ *
+ * @i2400m: device descriptors
+ * @bus_size: where to place the size of the TX message
+ *
+ * Called by the bus-specific driver to get the first TX message at
+ * the FIF that is ready for transmission.
+ *
+ * It sets the state in @i2400m to indicate the bus-specific driver is
+ * transfering that message (i2400m->tx_msg_size).
+ *
+ * Once the transfer is completed, call i2400m_tx_msg_sent().
+ *
+ * Notes:
+ *
+ *     The size of the TX message to be transmitted might be smaller than
+ *     that of the TX message in the FIFO (in case the header was
+ *     shorter). Hence, we copy it in @bus_size, for the bus layer to
+ *     use. We keep the message's size in i2400m->tx_msg_size so that
+ *     when the bus later is done transferring we know how much to
+ *     advance the fifo.
+ *
+ *     We collect statistics here as all the data is available and we
+ *     assume it is going to work [see i2400m_tx_msg_sent()].
+ */
+struct i2400m_msg_hdr *i2400m_tx_msg_get(struct i2400m *i2400m,
+                                         size_t *bus_size)
+{
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400m_msg_hdr *tx_msg, *tx_msg_moved;
+        unsigned long flags, pls;
+
+        d_fnstart(3, dev, "(i2400m %p bus_size %p)\n", i2400m, bus_size);
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+skip:
+        tx_msg_moved = NULL;
+        if (i2400m->tx_in == i2400m->tx_out) {  /* Empty FIFO? */
+                i2400m->tx_in = 0;
+                i2400m->tx_out = 0;
+                d_printf(2, dev, "TX: FIFO empty: resetting\n");
+                goto out_unlock;
+        }
+        tx_msg = i2400m->tx_buf + i2400m->tx_out % I2400M_TX_BUF_SIZE;
+        if (tx_msg->size & I2400M_TX_SKIP) {    /* skip? */
+                d_printf(2, dev, "TX: skip: msg @%zu (%zu b)\n",
+                         i2400m->tx_out % I2400M_TX_BUF_SIZE,
+                         (size_t) tx_msg->size & ~I2400M_TX_SKIP);
+                i2400m->tx_out += tx_msg->size & ~I2400M_TX_SKIP;
+                goto skip;
+        }
+
+        if (tx_msg->num_pls == 0) {             /* No payloads? */
+                if (tx_msg == i2400m->tx_msg) { /* open, we are done */
+                        d_printf(2, dev,
+                                 "TX: FIFO empty: open msg w/o payloads @%zu\n",
+                                 (void *) tx_msg - i2400m->tx_buf);
+                        tx_msg = NULL;
+                        goto out_unlock;
+                } else {                        /* closed, skip it */
+                        d_printf(2, dev,
+                                 "TX: skip msg w/o payloads @%zu (%zu b)\n",
+                                 (void *) tx_msg - i2400m->tx_buf,
+                                 (size_t) tx_msg->size);
+                        i2400m->tx_out += tx_msg->size & ~I2400M_TX_SKIP;
+                        goto skip;
+                }
+        }
+        if (tx_msg == i2400m->tx_msg)           /* open msg? */
+                i2400m_tx_close(i2400m);
+
+        /* Now we have a valid TX message (with payloads) to TX */
+        tx_msg_moved = (void *) tx_msg + tx_msg->offset;
+        i2400m->tx_msg_size = tx_msg->size;
+        *bus_size = tx_msg_moved->size;
+        d_printf(2, dev, "TX: pid %d msg hdr at @%zu offset +@%zu "
+                 "size %zu bus_size %zu\n",
+                 current->pid, (void *) tx_msg - i2400m->tx_buf,
+                 (size_t) tx_msg->offset, (size_t) tx_msg->size,
+                 (size_t) tx_msg_moved->size);
+        tx_msg_moved->barker = le32_to_cpu(I2400M_H2D_PREVIEW_BARKER);
+        tx_msg_moved->sequence = le32_to_cpu(i2400m->tx_sequence++);
+
+        pls = le32_to_cpu(tx_msg_moved->num_pls);
+        i2400m->tx_pl_num += pls;               /* Update stats */
+        if (pls > i2400m->tx_pl_max)
+                i2400m->tx_pl_max = pls;
+        if (pls < i2400m->tx_pl_min)
+                i2400m->tx_pl_min = pls;
+        i2400m->tx_num++;
+        i2400m->tx_size_acc += *bus_size;
+        if (*bus_size < i2400m->tx_size_min)
+                i2400m->tx_size_min = *bus_size;
+        if (*bus_size > i2400m->tx_size_max)
+                i2400m->tx_size_max = *bus_size;
+out_unlock:
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        d_fnstart(3, dev, "(i2400m %p bus_size %p [%zu]) = %p\n",
+                  i2400m, bus_size, *bus_size, tx_msg_moved);
+        return tx_msg_moved;
+}
+EXPORT_SYMBOL_GPL(i2400m_tx_msg_get);
+
+
+/**
+ * i2400m_tx_msg_sent - indicate the transmission of a TX message
+ *
+ * @i2400m: device descriptor
+ *
+ * Called by the bus-specific driver when a message has been sent;
+ * this pops it from the FIFO; and as there is space, start the queue
+ * in case it was stopped.
+ *
+ * Should be called even if the message send failed and we are
+ * dropping this TX message.
+ */
+void i2400m_tx_msg_sent(struct i2400m *i2400m)
+{
+        unsigned n;
+        unsigned long flags;
+        struct device *dev = i2400m_dev(i2400m);
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        spin_lock_irqsave(&i2400m->tx_lock, flags);
+        i2400m->tx_out += i2400m->tx_msg_size;
+        d_printf(2, dev, "TX: sent %zu b\n", (size_t) i2400m->tx_msg_size);
+        i2400m->tx_msg_size = 0;
+        BUG_ON(i2400m->tx_out > i2400m->tx_in);
+        /* level them FIFO markers off */
+        n = i2400m->tx_out / I2400M_TX_BUF_SIZE;
+        i2400m->tx_out %= I2400M_TX_BUF_SIZE;
+        i2400m->tx_in -= n * I2400M_TX_BUF_SIZE;
+        netif_start_queue(i2400m->wimax_dev.net_dev);
+        spin_unlock_irqrestore(&i2400m->tx_lock, flags);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+EXPORT_SYMBOL_GPL(i2400m_tx_msg_sent);
+
+
+/**
+ * i2400m_tx_setup - Initialize the TX queue and infrastructure
+ *
+ * Make sure we reset the TX sequence to zero, as when this function
+ * is called, the firmware has been just restarted.
+ */
+int i2400m_tx_setup(struct i2400m *i2400m)
+{
+        int result;
+
+        /* Do this here only once -- can't do on
+         * i2400m_hard_start_xmit() as we'll cause race conditions if
+         * the WS was scheduled on another CPU */
+        INIT_WORK(&i2400m->wake_tx_ws, i2400m_wake_tx_work);
+
+        i2400m->tx_sequence = 0;
+        i2400m->tx_buf = kmalloc(I2400M_TX_BUF_SIZE, GFP_KERNEL);
+        if (i2400m->tx_buf == NULL)
+                result = -ENOMEM;
+        else
+                result = 0;
+        /* Huh? the bus layer has to define this... */
+        BUG_ON(i2400m->bus_tx_block_size == 0);
+        return result;
+
+}
+
+
+/**
+ * i2400m_tx_release - Tear down the TX queue and infrastructure
+ */
+void i2400m_tx_release(struct i2400m *i2400m)
+{
+        kfree(i2400m->tx_buf);
+}
diff --git a/drivers/net/wimax/i2400m/usb-debug-levels.h b/drivers/net/wimax/i2400m/usb-debug-levels.h
new file mode 100644
index 000000000000..e4358bd880be
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb-debug-levels.h
@@ -0,0 +1,42 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Debug levels control file for the i2400m-usb module
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __debug_levels__h__
+#define __debug_levels__h__
+
+/* Maximum compile and run time debug level for all submodules */
+#define D_MODULENAME i2400m_usb
+#define D_MASTER CONFIG_WIMAX_I2400M_DEBUG_LEVEL
+
+#include <linux/wimax/debug.h>
+
+/* List of all the enabled modules */
+enum d_module {
+        D_SUBMODULE_DECLARE(usb),
+        D_SUBMODULE_DECLARE(fw),
+        D_SUBMODULE_DECLARE(notif),
+        D_SUBMODULE_DECLARE(rx),
+        D_SUBMODULE_DECLARE(tx),
+};
+
+
+#endif /* #ifndef __debug_levels__h__ */
diff --git a/drivers/net/wimax/i2400m/usb-fw.c b/drivers/net/wimax/i2400m/usb-fw.c
new file mode 100644
index 000000000000..5ad287c228b8
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb-fw.c
@@ -0,0 +1,340 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Firmware uploader's USB specifics
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - bus generic/specific split
+ *
+ * THE PROCEDURE
+ *
+ * See fw.c for the generic description of this procedure.
+ *
+ * This file implements only the USB specifics. It boils down to how
+ * to send a command and waiting for an acknowledgement from the
+ * device.
+ *
+ * This code (and process) is single threaded. It assumes it is the
+ * only thread poking around (guaranteed by fw.c).
+ *
+ * COMMAND EXECUTION
+ *
+ * A write URB is posted with the buffer to the bulk output endpoint.
+ *
+ * ACK RECEPTION
+ *
+ * We just post a URB to the notification endpoint and wait for
+ * data. We repeat until we get all the data we expect (as indicated
+ * by the call from the bus generic code).
+ *
+ * The data is not read from the bulk in endpoint for boot mode.
+ *
+ * ROADMAP
+ *
+ * i2400mu_bus_bm_cmd_send
+ *   i2400m_bm_cmd_prepare...
+ *   i2400mu_tx_bulk_out
+ *
+ * i2400mu_bus_bm_wait_for_ack
+ *   i2400m_notif_submit
+ */
+#include <linux/usb.h>
+#include "i2400m-usb.h"
+
+
+#define D_SUBMODULE fw
+#include "usb-debug-levels.h"
+
+
+/*
+ * Synchronous write to the device
+ *
+ * Takes care of updating EDC counts and thus, handle device errors.
+ */
+static
+ssize_t i2400mu_tx_bulk_out(struct i2400mu *i2400mu, void *buf, size_t buf_size)
+{
+        int result;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        int len;
+        struct usb_endpoint_descriptor *epd;
+        int pipe, do_autopm = 1;
+
+        result = usb_autopm_get_interface(i2400mu->usb_iface);
+        if (result < 0) {
+                dev_err(dev, "BM-CMD: can't get autopm: %d\n", result);
+                do_autopm = 0;
+        }
+        epd = usb_get_epd(i2400mu->usb_iface, I2400MU_EP_BULK_OUT);
+        pipe = usb_sndbulkpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+retry:
+        result = usb_bulk_msg(i2400mu->usb_dev, pipe, buf, buf_size, &len, HZ);
+        switch (result) {
+        case 0:
+                if (len != buf_size) {
+                        dev_err(dev, "BM-CMD: short write (%u B vs %zu "
+                                "expected)\n", len, buf_size);
+                        result = -EIO;
+                        break;
+                }
+                result = len;
+                break;
+        case -EINVAL:                   /* while removing driver */
+        case -ENODEV:                   /* dev disconnect ... */
+        case -ENOENT:                   /* just ignore it */
+        case -ESHUTDOWN:                /* and exit */
+        case -ECONNRESET:
+                result = -ESHUTDOWN;
+                break;
+        case -ETIMEDOUT:                        /* bah... */
+                break;
+        default:                                /* any other? */
+                if (edc_inc(&i2400mu->urb_edc,
+                            EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME)) {
+                                dev_err(dev, "BM-CMD: maximum errors in "
+                                        "URB exceeded; resetting device\n");
+                                usb_queue_reset_device(i2400mu->usb_iface);
+                                result = -ENODEV;
+                                break;
+                }
+                dev_err(dev, "BM-CMD: URB error %d, retrying\n",
+                        result);
+                goto retry;
+        }
+        result = len;
+        if (do_autopm)
+                usb_autopm_put_interface(i2400mu->usb_iface);
+        return result;
+}
+
+
+/*
+ * Send a boot-mode command over the bulk-out pipe
+ *
+ * Command can be a raw command, which requires no preparation (and
+ * which might not even be following the command format). Checks that
+ * the right amount of data was transfered.
+ *
+ * To satisfy USB requirements (no onstack, vmalloc or in data segment
+ * buffers), we copy the command to i2400m->bm_cmd_buf and send it from
+ * there.
+ *
+ * @flags: pass thru from i2400m_bm_cmd()
+ * @return: cmd_size if ok, < 0 errno code on error.
+ */
+ssize_t i2400mu_bus_bm_cmd_send(struct i2400m *i2400m,
+                                const struct i2400m_bootrom_header *_cmd,
+                                size_t cmd_size, int flags)
+{
+        ssize_t result;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        int opcode = _cmd == NULL ? -1 : i2400m_brh_get_opcode(_cmd);
+        struct i2400m_bootrom_header *cmd;
+        size_t cmd_size_a = ALIGN(cmd_size, 16);        /* USB restriction */
+
+        d_fnstart(8, dev, "(i2400m %p cmd %p size %zu)\n",
+                  i2400m, _cmd, cmd_size);
+        result = -E2BIG;
+        if (cmd_size > I2400M_BM_CMD_BUF_SIZE)
+                goto error_too_big;
+        memcpy(i2400m->bm_cmd_buf, _cmd, cmd_size);
+        cmd = i2400m->bm_cmd_buf;
+        if (cmd_size_a > cmd_size)                      /* Zero pad space */
+                memset(i2400m->bm_cmd_buf + cmd_size, 0, cmd_size_a - cmd_size);
+        if ((flags & I2400M_BM_CMD_RAW) == 0) {
+                if (WARN_ON(i2400m_brh_get_response_required(cmd) == 0))
+                        dev_warn(dev, "SW BUG: response_required == 0\n");
+                i2400m_bm_cmd_prepare(cmd);
+        }
+        result = i2400mu_tx_bulk_out(i2400mu, i2400m->bm_cmd_buf, cmd_size);
+        if (result < 0) {
+                dev_err(dev, "boot-mode cmd %d: cannot send: %zd\n",
+                        opcode, result);
+                goto error_cmd_send;
+        }
+        if (result != cmd_size) {               /* all was transferred? */
+                dev_err(dev, "boot-mode cmd %d: incomplete transfer "
+                        "(%zu vs %zu submitted)\n",  opcode, result, cmd_size);
+                result = -EIO;
+                goto error_cmd_size;
+        }
+error_cmd_size:
+error_cmd_send:
+error_too_big:
+        d_fnend(8, dev, "(i2400m %p cmd %p size %zu) = %zd\n",
+                i2400m, _cmd, cmd_size, result);
+        return result;
+}
+
+
+static
+void __i2400mu_bm_notif_cb(struct urb *urb)
+{
+        complete(urb->context);
+}
+
+
+/*
+ * submit a read to the notification endpoint
+ *
+ * @i2400m: device descriptor
+ * @urb: urb to use
+ * @completion: completion varible to complete when done
+ *
+ * Data is always read to i2400m->bm_ack_buf
+ */
+static
+int i2400mu_notif_submit(struct i2400mu *i2400mu, struct urb *urb,
+                         struct completion *completion)
+{
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct usb_endpoint_descriptor *epd;
+        int pipe;
+
+        epd = usb_get_epd(i2400mu->usb_iface, I2400MU_EP_NOTIFICATION);
+        pipe = usb_rcvintpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+        usb_fill_int_urb(urb, i2400mu->usb_dev, pipe,
+                         i2400m->bm_ack_buf, I2400M_BM_ACK_BUF_SIZE,
+                         __i2400mu_bm_notif_cb, completion,
+                         epd->bInterval);
+        return usb_submit_urb(urb, GFP_KERNEL);
+}
+
+
+/*
+ * Read an ack from  the notification endpoint
+ *
+ * @i2400m:
+ * @_ack: pointer to where to store the read data
+ * @ack_size: how many bytes we should read
+ *
+ * Returns: < 0 errno code on error; otherwise, amount of received bytes.
+ *
+ * Submits a notification read, appends the read data to the given ack
+ * buffer and then repeats (until @ack_size bytes have been
+ * received).
+ */
+ssize_t i2400mu_bus_bm_wait_for_ack(struct i2400m *i2400m,
+                                    struct i2400m_bootrom_header *_ack,
+                                    size_t ack_size)
+{
+        ssize_t result = -ENOMEM;
+        struct device *dev = i2400m_dev(i2400m);
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        struct urb notif_urb;
+        void *ack = _ack;
+        size_t offset, len;
+        long val;
+        int do_autopm = 1;
+        DECLARE_COMPLETION_ONSTACK(notif_completion);
+
+        d_fnstart(8, dev, "(i2400m %p ack %p size %zu)\n",
+                  i2400m, ack, ack_size);
+        BUG_ON(_ack == i2400m->bm_ack_buf);
+        result = usb_autopm_get_interface(i2400mu->usb_iface);
+        if (result < 0) {
+                dev_err(dev, "BM-ACK: can't get autopm: %d\n", (int) result);
+                do_autopm = 0;
+        }
+        usb_init_urb(&notif_urb);       /* ready notifications */
+        usb_get_urb(&notif_urb);
+        offset = 0;
+        while (offset < ack_size) {
+                init_completion(&notif_completion);
+                result = i2400mu_notif_submit(i2400mu, &notif_urb,
+                                              &notif_completion);
+                if (result < 0)
+                        goto error_notif_urb_submit;
+                val = wait_for_completion_interruptible_timeout(
+                        &notif_completion, HZ);
+                if (val == 0) {
+                        result = -ETIMEDOUT;
+                        usb_kill_urb(&notif_urb);       /* Timedout */
+                        goto error_notif_wait;
+                }
+                if (val == -ERESTARTSYS) {
+                        result = -EINTR;                /* Interrupted */
+                        usb_kill_urb(&notif_urb);
+                        goto error_notif_wait;
+                }
+                result = notif_urb.status;              /* How was the ack? */
+                switch (result) {
+                case 0:
+                        break;
+                case -EINVAL:                   /* while removing driver */
+                case -ENODEV:                   /* dev disconnect ... */
+                case -ENOENT:                   /* just ignore it */
+                case -ESHUTDOWN:                /* and exit */
+                case -ECONNRESET:
+                        result = -ESHUTDOWN;
+                        goto error_dev_gone;
+                default:                                /* any other? */
+                        usb_kill_urb(&notif_urb);       /* Timedout */
+                        if (edc_inc(&i2400mu->urb_edc,
+                                    EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME))
+                                goto error_exceeded;
+                        dev_err(dev, "BM-ACK: URB error %d, "
+                                "retrying\n", notif_urb.status);
+                        continue;       /* retry */
+                }
+                if (notif_urb.actual_length == 0) {
+                        d_printf(6, dev, "ZLP received, retrying\n");
+                        continue;
+                }
+                /* Got data, append it to the buffer */
+                len = min(ack_size - offset, (size_t) notif_urb.actual_length);
+                memcpy(ack + offset, i2400m->bm_ack_buf, len);
+                offset += len;
+        }
+        result = offset;
+error_notif_urb_submit:
+error_notif_wait:
+error_dev_gone:
+out:
+        if (do_autopm)
+                usb_autopm_put_interface(i2400mu->usb_iface);
+        d_fnend(8, dev, "(i2400m %p ack %p size %zu) = %zd\n",
+                i2400m, ack, ack_size, result);
+        return result;
+
+error_exceeded:
+        dev_err(dev, "bm: maximum errors in notification URB exceeded; "
+                "resetting device\n");
+        usb_queue_reset_device(i2400mu->usb_iface);
+        goto out;
+}
diff --git a/drivers/net/wimax/i2400m/usb-notif.c b/drivers/net/wimax/i2400m/usb-notif.c
new file mode 100644
index 000000000000..9702c22b2497
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb-notif.c
@@ -0,0 +1,269 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m over USB
+ * Notification handling
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * The notification endpoint is active when the device is not in boot
+ * mode; in here we just read and get notifications; based on those,
+ * we act to either reinitialize the device after a reboot or to
+ * submit a RX request.
+ *
+ * ROADMAP
+ *
+ * i2400mu_usb_notification_setup()
+ *
+ * i2400mu_usb_notification_release()
+ *
+ * i2400mu_usb_notification_cb()        Called when a URB is ready
+ *   i2400mu_notif_grok()
+ *     i2400m_dev_reset_handle()
+ *     i2400mu_rx_kick()
+ */
+#include <linux/usb.h>
+#include "i2400m-usb.h"
+
+
+#define D_SUBMODULE notif
+#include "usb-debug-levels.h"
+
+
+static const
+__le32 i2400m_ZERO_BARKER[4] = { 0, 0, 0, 0 };
+
+
+/*
+ * Process a received notification
+ *
+ * In normal operation mode, we can only receive two types of payloads
+ * on the notification endpoint:
+ *
+ *   - a reboot barker, we do a bootstrap (the device has reseted).
+ *
+ *   - a block of zeroes: there is pending data in the IN endpoint
+ */
+static
+int i2400mu_notification_grok(struct i2400mu *i2400mu, const void *buf,
+                                 size_t buf_len)
+{
+        int ret;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+
+        d_fnstart(4, dev, "(i2400m %p buf %p buf_len %zu)\n",
+                  i2400mu, buf, buf_len);
+        ret = -EIO;
+        if (buf_len < sizeof(i2400m_NBOOT_BARKER))
+                /* Not a bug, just ignore */
+                goto error_bad_size;
+        if (!memcmp(i2400m_NBOOT_BARKER, buf, sizeof(i2400m_NBOOT_BARKER))
+            || !memcmp(i2400m_SBOOT_BARKER, buf, sizeof(i2400m_SBOOT_BARKER)))
+                ret = i2400m_dev_reset_handle(i2400m);
+        else if (!memcmp(i2400m_ZERO_BARKER, buf, sizeof(i2400m_ZERO_BARKER))) {
+                i2400mu_rx_kick(i2400mu);
+                ret = 0;
+        } else {        /* Unknown or unexpected data in the notif message */
+                char prefix[64];
+                ret = -EIO;
+                dev_err(dev, "HW BUG? Unknown/unexpected data in notification "
+                        "message (%zu bytes)\n", buf_len);
+                snprintf(prefix, sizeof(prefix), "%s %s: ",
+                         dev_driver_string(dev) , dev->bus_id);
+                if (buf_len > 64) {
+                        print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
+                                       8, 4, buf, 64, 0);
+                        printk(KERN_ERR "%s... (only first 64 bytes "
+                               "dumped)\n", prefix);
+                } else
+                        print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
+                                       8, 4, buf, buf_len, 0);
+        }
+error_bad_size:
+        d_fnend(4, dev, "(i2400m %p buf %p buf_len %zu) = %d\n",
+                i2400mu, buf, buf_len, ret);
+        return ret;
+}
+
+
+/*
+ * URB callback for the notification endpoint
+ *
+ * @urb: the urb received from the notification endpoint
+ *
+ * This function will just process the USB side of the transaction,
+ * checking everything is fine, pass the processing to
+ * i2400m_notification_grok() and resubmit the URB.
+ */
+static
+void i2400mu_notification_cb(struct urb *urb)
+{
+        int ret;
+        struct i2400mu *i2400mu = urb->context;
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(4, dev, "(urb %p status %d actual_length %d)\n",
+                  urb, urb->status, urb->actual_length);
+        ret = urb->status;
+        switch (ret) {
+        case 0:
+                ret = i2400mu_notification_grok(i2400mu, urb->transfer_buffer,
+                                                urb->actual_length);
+                if (ret == -EIO && edc_inc(&i2400mu->urb_edc, EDC_MAX_ERRORS,
+                                           EDC_ERROR_TIMEFRAME))
+                        goto error_exceeded;
+                if (ret == -ENOMEM)     /* uff...power cycle? shutdown? */
+                        goto error_exceeded;
+                break;
+        case -EINVAL:                   /* while removing driver */
+        case -ENODEV:                   /* dev disconnect ... */
+        case -ENOENT:                   /* ditto */
+        case -ESHUTDOWN:                /* URB killed */
+        case -ECONNRESET:               /* disconnection */
+                goto out;               /* Notify around */
+        default:                        /* Some error? */
+                if (edc_inc(&i2400mu->urb_edc,
+                            EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME))
+                        goto error_exceeded;
+                dev_err(dev, "notification: URB error %d, retrying\n",
+                        urb->status);
+        }
+        usb_mark_last_busy(i2400mu->usb_dev);
+        ret = usb_submit_urb(i2400mu->notif_urb, GFP_ATOMIC);
+        switch (ret) {
+        case 0:
+        case -EINVAL:                   /* while removing driver */
+        case -ENODEV:                   /* dev disconnect ... */
+        case -ENOENT:                   /* ditto */
+        case -ESHUTDOWN:                /* URB killed */
+        case -ECONNRESET:               /* disconnection */
+                break;                  /* just ignore */
+        default:                        /* Some error? */
+                dev_err(dev, "notification: cannot submit URB: %d\n", ret);
+                goto error_submit;
+        }
+        d_fnend(4, dev, "(urb %p status %d actual_length %d) = void\n",
+                urb, urb->status, urb->actual_length);
+        return;
+
+error_exceeded:
+        dev_err(dev, "maximum errors in notification URB exceeded; "
+                "resetting device\n");
+error_submit:
+        usb_queue_reset_device(i2400mu->usb_iface);
+out:
+        d_fnend(4, dev, "(urb %p status %d actual_length %d) = void\n",
+                urb, urb->status, urb->actual_length);
+        return;
+}
+
+
+/*
+ * setup the notification endpoint
+ *
+ * @i2400m: device descriptor
+ *
+ * This procedure prepares the notification urb and handler for receiving
+ * unsolicited barkers from the device.
+ */
+int i2400mu_notification_setup(struct i2400mu *i2400mu)
+{
+        struct device *dev = &i2400mu->usb_iface->dev;
+        int usb_pipe, ret = 0;
+        struct usb_endpoint_descriptor *epd;
+        char *buf;
+
+        d_fnstart(4, dev, "(i2400m %p)\n", i2400mu);
+        buf = kmalloc(I2400MU_MAX_NOTIFICATION_LEN, GFP_KERNEL | GFP_DMA);
+        if (buf == NULL) {
+                dev_err(dev, "notification: buffer allocation failed\n");
+                ret = -ENOMEM;
+                goto error_buf_alloc;
+        }
+
+        i2400mu->notif_urb = usb_alloc_urb(0, GFP_KERNEL);
+        if (!i2400mu->notif_urb) {
+                ret = -ENOMEM;
+                dev_err(dev, "notification: cannot allocate URB\n");
+                goto error_alloc_urb;
+        }
+        epd = usb_get_epd(i2400mu->usb_iface, I2400MU_EP_NOTIFICATION);
+        usb_pipe = usb_rcvintpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+        usb_fill_int_urb(i2400mu->notif_urb, i2400mu->usb_dev, usb_pipe,
+                         buf, I2400MU_MAX_NOTIFICATION_LEN,
+                         i2400mu_notification_cb, i2400mu, epd->bInterval);
+        ret = usb_submit_urb(i2400mu->notif_urb, GFP_KERNEL);
+        if (ret != 0) {
+                dev_err(dev, "notification: cannot submit URB: %d\n", ret);
+                goto error_submit;
+        }
+        d_fnend(4, dev, "(i2400m %p) = %d\n", i2400mu, ret);
+        return ret;
+
+error_submit:
+        usb_free_urb(i2400mu->notif_urb);
+error_alloc_urb:
+        kfree(buf);
+error_buf_alloc:
+        d_fnend(4, dev, "(i2400m %p) = %d\n", i2400mu, ret);
+        return ret;
+}
+
+
+/*
+ * Tear down of the notification mechanism
+ *
+ * @i2400m: device descriptor
+ *
+ * Kill the interrupt endpoint urb, free any allocated resources.
+ *
+ * We need to check if we have done it before as for example,
+ * _suspend() call this; if after a suspend() we get a _disconnect()
+ * (as the case is when hibernating), nothing bad happens.
+ */
+void i2400mu_notification_release(struct i2400mu *i2400mu)
+{
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(4, dev, "(i2400mu %p)\n", i2400mu);
+        if (i2400mu->notif_urb != NULL) {
+                usb_kill_urb(i2400mu->notif_urb);
+                kfree(i2400mu->notif_urb->transfer_buffer);
+                usb_free_urb(i2400mu->notif_urb);
+                i2400mu->notif_urb = NULL;
+        }
+        d_fnend(4, dev, "(i2400mu %p)\n", i2400mu);
+}
diff --git a/drivers/net/wimax/i2400m/usb-rx.c b/drivers/net/wimax/i2400m/usb-rx.c
new file mode 100644
index 000000000000..074cc1f89853
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb-rx.c
@@ -0,0 +1,417 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * USB RX handling
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Use skb_clone(), break up processing in chunks
+ *  - Split transport/device specific
+ *  - Make buffer size dynamic to exert less memory pressure
+ *
+ *
+ * This handles the RX path on USB.
+ *
+ * When a notification is received that says 'there is RX data ready',
+ * we call i2400mu_rx_kick(); that wakes up the RX kthread, which
+ * reads a buffer from USB and passes it to i2400m_rx() in the generic
+ * handling code. The RX buffer has an specific format that is
+ * described in rx.c.
+ *
+ * We use a kernel thread in a loop because:
+ *
+ *  - we want to be able to call the USB power management get/put
+ *    functions (blocking) before each transaction.
+ *
+ *  - We might get a lot of notifications and we don't want to submit
+ *    a zillion reads; by serializing, we are throttling.
+ *
+ *  - RX data processing can get heavy enough so that it is not
+ *    appropiate for doing it in the USB callback; thus we run it in a
+ *    process context.
+ *
+ * We provide a read buffer of an arbitrary size (short of a page); if
+ * the callback reports -EOVERFLOW, it means it was too small, so we
+ * just double the size and retry (being careful to append, as
+ * sometimes the device provided some data). Every now and then we
+ * check if the average packet size is smaller than the current packet
+ * size and if so, we halve it. At the end, the size of the
+ * preallocated buffer should be following the average received
+ * transaction size, adapting dynamically to it.
+ *
+ * ROADMAP
+ *
+ * i2400mu_rx_kick()               Called from notif.c when we get a
+ *                                 'data ready' notification
+ * i2400mu_rxd()                   Kernel RX daemon
+ *   i2400mu_rx()                  Receive USB data
+ *   i2400m_rx()                   Send data to generic i2400m RX handling
+ *
+ * i2400mu_rx_setup()              called from i2400mu_bus_dev_start()
+ *
+ * i2400mu_rx_release()            called from i2400mu_bus_dev_stop()
+ */
+#include <linux/workqueue.h>
+#include <linux/usb.h>
+#include "i2400m-usb.h"
+
+
+#define D_SUBMODULE rx
+#include "usb-debug-levels.h"
+
+/*
+ * Dynamic RX size
+ *
+ * We can't let the rx_size be a multiple of 512 bytes (the RX
+ * endpoint's max packet size). On some USB host controllers (we
+ * haven't been able to fully characterize which), if the device is
+ * about to send (for example) X bytes and we only post a buffer to
+ * receive n*512, it will fail to mark that as babble (so that
+ * i2400mu_rx() [case -EOVERFLOW] can resize the buffer and get the
+ * rest).
+ *
+ * So on growing or shrinking, if it is a multiple of the
+ * maxpacketsize, we remove some (instead of incresing some, so in a
+ * buddy allocator we try to waste less space).
+ *
+ * Note we also need a hook for this on i2400mu_rx() -- when we do the
+ * first read, we are sure we won't hit this spot because
+ * i240mm->rx_size has been set properly. However, if we have to
+ * double because of -EOVERFLOW, when we launch the read to get the
+ * rest of the data, we *have* to make sure that also is not a
+ * multiple of the max_pkt_size.
+ */
+
+static
+size_t i2400mu_rx_size_grow(struct i2400mu *i2400mu)
+{
+        struct device *dev = &i2400mu->usb_iface->dev;
+        size_t rx_size;
+        const size_t max_pkt_size = 512;
+
+        rx_size = 2 * i2400mu->rx_size;
+        if (rx_size % max_pkt_size == 0) {
+                rx_size -= 8;
+                d_printf(1, dev,
+                         "RX: expected size grew to %zu [adjusted -8] "
+                         "from %zu\n",
+                         rx_size, i2400mu->rx_size);
+        } else
+                d_printf(1, dev,
+                         "RX: expected size grew to %zu from %zu\n",
+                         rx_size, i2400mu->rx_size);
+        return rx_size;
+}
+
+
+static
+void i2400mu_rx_size_maybe_shrink(struct i2400mu *i2400mu)
+{
+        const size_t max_pkt_size = 512;
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        if (unlikely(i2400mu->rx_size_cnt >= 100
+                     && i2400mu->rx_size_auto_shrink)) {
+                size_t avg_rx_size =
+                        i2400mu->rx_size_acc / i2400mu->rx_size_cnt;
+                size_t new_rx_size = i2400mu->rx_size / 2;
+                if (avg_rx_size < new_rx_size) {
+                        if (new_rx_size % max_pkt_size == 0) {
+                                new_rx_size -= 8;
+                                d_printf(1, dev,
+                                         "RX: expected size shrank to %zu "
+                                         "[adjusted -8] from %zu\n",
+                                         new_rx_size, i2400mu->rx_size);
+                        } else
+                                d_printf(1, dev,
+                                         "RX: expected size shrank to %zu "
+                                         "from %zu\n",
+                                         new_rx_size, i2400mu->rx_size);
+                        i2400mu->rx_size = new_rx_size;
+                        i2400mu->rx_size_cnt = 0;
+                        i2400mu->rx_size_acc = i2400mu->rx_size;
+                }
+        }
+}
+
+/*
+ * Receive a message with payloads from the USB bus into an skb
+ *
+ * @i2400mu: USB device descriptor
+ * @rx_skb: skb where to place the received message
+ *
+ * Deals with all the USB-specifics of receiving, dynamically
+ * increasing the buffer size if so needed. Returns the payload in the
+ * skb, ready to process. On a zero-length packet, we retry.
+ *
+ * On soft USB errors, we retry (until they become too frequent and
+ * then are promoted to hard); on hard USB errors, we reset the
+ * device. On other errors (skb realloacation, we just drop it and
+ * hope for the next invocation to solve it).
+ *
+ * Returns: pointer to the skb if ok, ERR_PTR on error.
+ *   NOTE: this function might realloc the skb (if it is too small),
+ *   so always update with the one returned.
+ *   ERR_PTR() is < 0 on error.
+ */
+static
+struct sk_buff *i2400mu_rx(struct i2400mu *i2400mu, struct sk_buff *rx_skb)
+{
+        int result = 0;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        int usb_pipe, read_size, rx_size, do_autopm;
+        struct usb_endpoint_descriptor *epd;
+        const size_t max_pkt_size = 512;
+
+        d_fnstart(4, dev, "(i2400mu %p)\n", i2400mu);
+        do_autopm = atomic_read(&i2400mu->do_autopm);
+        result = do_autopm ?
+                usb_autopm_get_interface(i2400mu->usb_iface) : 0;
+        if (result < 0) {
+                dev_err(dev, "RX: can't get autopm: %d\n", result);
+                do_autopm = 0;
+        }
+        epd = usb_get_epd(i2400mu->usb_iface, I2400MU_EP_BULK_IN);
+        usb_pipe = usb_rcvbulkpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+retry:
+        rx_size = skb_end_pointer(rx_skb) - rx_skb->data - rx_skb->len;
+        if (unlikely(rx_size % max_pkt_size == 0)) {
+                rx_size -= 8;
+                d_printf(1, dev, "RX: rx_size adapted to %d [-8]\n", rx_size);
+        }
+        result = usb_bulk_msg(
+                i2400mu->usb_dev, usb_pipe, rx_skb->data + rx_skb->len,
+                rx_size, &read_size, HZ);
+        usb_mark_last_busy(i2400mu->usb_dev);
+        switch (result) {
+        case 0:
+                if (read_size == 0)
+                        goto retry;     /* ZLP, just resubmit */
+                skb_put(rx_skb, read_size);
+                break;
+        case -EINVAL:                   /* while removing driver */
+        case -ENODEV:                   /* dev disconnect ... */
+        case -ENOENT:                   /* just ignore it */
+        case -ESHUTDOWN:
+        case -ECONNRESET:
+                break;
+        case -EOVERFLOW: {              /* too small, reallocate */
+                struct sk_buff *new_skb;
+                rx_size = i2400mu_rx_size_grow(i2400mu);
+                if (rx_size <= (1 << 16))       /* cap it */
+                        i2400mu->rx_size = rx_size;
+                else if (printk_ratelimit()) {
+                        dev_err(dev, "BUG? rx_size up to %d\n", rx_size);
+                        result = -EINVAL;
+                        goto out;
+                }
+                skb_put(rx_skb, read_size);
+                new_skb = skb_copy_expand(rx_skb, 0, rx_size - rx_skb->len,
+                                          GFP_KERNEL);
+                if (new_skb == NULL) {
+                        if (printk_ratelimit())
+                                dev_err(dev, "RX: Can't reallocate skb to %d; "
+                                        "RX dropped\n", rx_size);
+                        kfree(rx_skb);
+                        result = 0;
+                        goto out;       /* drop it...*/
+                }
+                kfree_skb(rx_skb);
+                rx_skb = new_skb;
+                i2400mu->rx_size_cnt = 0;
+                i2400mu->rx_size_acc = i2400mu->rx_size;
+                d_printf(1, dev, "RX: size changed to %d, received %d, "
+                         "copied %d, capacity %ld\n",
+                         rx_size, read_size, rx_skb->len,
+                         (long) (skb_end_pointer(new_skb) - new_skb->head));
+                goto retry;
+        }
+                /* In most cases, it happens due to the hardware scheduling a
+                 * read when there was no data - unfortunately, we have no way
+                 * to tell this timeout from a USB timeout. So we just ignore
+                 * it. */
+        case -ETIMEDOUT:
+                dev_err(dev, "RX: timeout: %d\n", result);
+                result = 0;
+                break;
+        default:                        /* Any error */
+                if (edc_inc(&i2400mu->urb_edc,
+                            EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME))
+                        goto error_reset;
+                dev_err(dev, "RX: error receiving URB: %d, retrying\n", result);
+                goto retry;
+        }
+out:
+        if (do_autopm)
+                usb_autopm_put_interface(i2400mu->usb_iface);
+        d_fnend(4, dev, "(i2400mu %p) = %p\n", i2400mu, rx_skb);
+        return rx_skb;
+
+error_reset:
+        dev_err(dev, "RX: maximum errors in URB exceeded; "
+                "resetting device\n");
+        usb_queue_reset_device(i2400mu->usb_iface);
+        rx_skb = ERR_PTR(result);
+        goto out;
+}
+
+
+/*
+ * Kernel thread for USB reception of data
+ *
+ * This thread waits for a kick; once kicked, it will allocate an skb
+ * and receive a single message to it from USB (using
+ * i2400mu_rx()). Once received, it is passed to the generic i2400m RX
+ * code for processing.
+ *
+ * When done processing, it runs some dirty statistics to verify if
+ * the last 100 messages received were smaller than half of the
+ * current RX buffer size. In that case, the RX buffer size is
+ * halved. This will helps lowering the pressure on the memory
+ * allocator.
+ *
+ * Hard errors force the thread to exit.
+ */
+static
+int i2400mu_rxd(void *_i2400mu)
+{
+        int result = 0;
+        struct i2400mu *i2400mu = _i2400mu;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+        size_t pending;
+        int rx_size;
+        struct sk_buff *rx_skb;
+
+        d_fnstart(4, dev, "(i2400mu %p)\n", i2400mu);
+        while (1) {
+                d_printf(2, dev, "TX: waiting for messages\n");
+                pending = 0;
+                wait_event_interruptible(
+                        i2400mu->rx_wq,
+                        (kthread_should_stop()  /* check this first! */
+                         || (pending = atomic_read(&i2400mu->rx_pending_count)))
+                        );
+                if (kthread_should_stop())
+                        break;
+                if (pending == 0)
+                        continue;
+                rx_size = i2400mu->rx_size;
+                d_printf(2, dev, "RX: reading up to %d bytes\n", rx_size);
+                rx_skb = __netdev_alloc_skb(net_dev, rx_size, GFP_KERNEL);
+                if (rx_skb == NULL) {
+                        dev_err(dev, "RX: can't allocate skb [%d bytes]\n",
+                                rx_size);
+                        msleep(50);     /* give it some time? */
+                        continue;
+                }
+
+                /* Receive the message with the payloads */
+                rx_skb = i2400mu_rx(i2400mu, rx_skb);
+                result = PTR_ERR(rx_skb);
+                if (IS_ERR(rx_skb))
+                        goto out;
+                atomic_dec(&i2400mu->rx_pending_count);
+                if (rx_skb->len == 0) { /* some ignorable condition */
+                        kfree_skb(rx_skb);
+                        continue;
+                }
+
+                /* Deliver the message to the generic i2400m code */
+                i2400mu->rx_size_cnt++;
+                i2400mu->rx_size_acc += rx_skb->len;
+                result = i2400m_rx(i2400m, rx_skb);
+                if (result == -EIO
+                    && edc_inc(&i2400mu->urb_edc,
+                               EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME)) {
+                        goto error_reset;
+                }
+
+                /* Maybe adjust RX buffer size */
+                i2400mu_rx_size_maybe_shrink(i2400mu);
+        }
+        result = 0;
+out:
+        d_fnend(4, dev, "(i2400mu %p) = %d\n", i2400mu, result);
+        return result;
+
+error_reset:
+        dev_err(dev, "RX: maximum errors in received buffer exceeded; "
+                "resetting device\n");
+        usb_queue_reset_device(i2400mu->usb_iface);
+        goto out;
+}
+
+
+/*
+ * Start reading from the device
+ *
+ * @i2400m: device instance
+ *
+ * Notify the RX thread that there is data pending.
+ */
+void i2400mu_rx_kick(struct i2400mu *i2400mu)
+{
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(3, dev, "(i2400mu %p)\n", i2400m);
+        atomic_inc(&i2400mu->rx_pending_count);
+        wake_up_all(&i2400mu->rx_wq);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+
+
+int i2400mu_rx_setup(struct i2400mu *i2400mu)
+{
+        int result = 0;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+
+        i2400mu->rx_kthread = kthread_run(i2400mu_rxd, i2400mu, "%s-rx",
+                                          wimax_dev->name);
+        if (IS_ERR(i2400mu->rx_kthread)) {
+                result = PTR_ERR(i2400mu->rx_kthread);
+                dev_err(dev, "RX: cannot start thread: %d\n", result);
+        }
+        return result;
+}
+
+void i2400mu_rx_release(struct i2400mu *i2400mu)
+{
+        kthread_stop(i2400mu->rx_kthread);
+}
+
diff --git a/drivers/net/wimax/i2400m/usb-tx.c b/drivers/net/wimax/i2400m/usb-tx.c
new file mode 100644
index 000000000000..dfd893356f49
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb-tx.c
@@ -0,0 +1,229 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * USB specific TX handling
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *  - Initial implementation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Split transport/device specific
+ *
+ *
+ * Takes the TX messages in the i2400m's driver TX FIFO and sends them
+ * to the device until there are no more.
+ *
+ * If we fail sending the message, we just drop it. There isn't much
+ * we can do at this point. We could also retry, but the USB stack has
+ * already retried and still failed, so there is not much of a
+ * point. As well, most of the traffic is network, which has recovery
+ * methods for dropped packets.
+ *
+ * For sending we just obtain a FIFO buffer to send, send it to the
+ * USB bulk out, tell the TX FIFO code we have sent it; query for
+ * another one, etc... until done.
+ *
+ * We use a thread so we can call usb_autopm_enable() and
+ * usb_autopm_disable() for each transaction; this way when the device
+ * goes idle, it will suspend. It also has less overhead than a
+ * dedicated workqueue, as it is being used for a single task.
+ *
+ * ROADMAP
+ *
+ * i2400mu_tx_setup()
+ * i2400mu_tx_release()
+ *
+ * i2400mu_bus_tx_kick()        - Called by the tx.c code when there
+ *                                is new data in the FIFO.
+ * i2400mu_txd()
+ *   i2400m_tx_msg_get()
+ *   i2400m_tx_msg_sent()
+ */
+#include "i2400m-usb.h"
+
+
+#define D_SUBMODULE tx
+#include "usb-debug-levels.h"
+
+
+/*
+ * Get the next TX message in the TX FIFO and send it to the device
+ *
+ * Note that any iteration consumes a message to be sent, no matter if
+ * it succeeds or fails (we have no real way to retry or complain).
+ *
+ * Return: 0 if ok, < 0 errno code on hard error.
+ */
+static
+int i2400mu_tx(struct i2400mu *i2400mu, struct i2400m_msg_hdr *tx_msg,
+               size_t tx_msg_size)
+{
+        int result = 0;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        int usb_pipe, sent_size, do_autopm;
+        struct usb_endpoint_descriptor *epd;
+
+        d_fnstart(4, dev, "(i2400mu %p)\n", i2400mu);
+        do_autopm = atomic_read(&i2400mu->do_autopm);
+        result = do_autopm ?
+                usb_autopm_get_interface(i2400mu->usb_iface) : 0;
+        if (result < 0) {
+                dev_err(dev, "TX: can't get autopm: %d\n", result);
+                do_autopm = 0;
+        }
+        epd = usb_get_epd(i2400mu->usb_iface, I2400MU_EP_BULK_OUT);
+        usb_pipe = usb_sndbulkpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+retry:
+        result = usb_bulk_msg(i2400mu->usb_dev, usb_pipe,
+                              tx_msg, tx_msg_size, &sent_size, HZ);
+        usb_mark_last_busy(i2400mu->usb_dev);
+        switch (result) {
+        case 0:
+                if (sent_size != tx_msg_size) { /* Too short? drop it */
+                        dev_err(dev, "TX: short write (%d B vs %zu "
+                                "expected)\n", sent_size, tx_msg_size);
+                        result = -EIO;
+                }
+                break;
+        case -EINVAL:                   /* while removing driver */
+        case -ENODEV:                   /* dev disconnect ... */
+        case -ENOENT:                   /* just ignore it */
+        case -ESHUTDOWN:                /* and exit */
+        case -ECONNRESET:
+                result = -ESHUTDOWN;
+                break;
+        default:                        /* Some error? */
+                if (edc_inc(&i2400mu->urb_edc,
+                            EDC_MAX_ERRORS, EDC_ERROR_TIMEFRAME)) {
+                        dev_err(dev, "TX: maximum errors in URB "
+                                "exceeded; resetting device\n");
+                        usb_queue_reset_device(i2400mu->usb_iface);
+                } else {
+                        dev_err(dev, "TX: cannot send URB; retrying. "
+                                "tx_msg @%zu %zu B [%d sent]: %d\n",
+                                (void *) tx_msg - i2400m->tx_buf,
+                                tx_msg_size, sent_size, result);
+                        goto retry;
+                }
+        }
+        if (do_autopm)
+                usb_autopm_put_interface(i2400mu->usb_iface);
+        d_fnend(4, dev, "(i2400mu %p) = result\n", i2400mu);
+        return result;
+}
+
+
+/*
+ * Get the next TX message in the TX FIFO and send it to the device
+ *
+ * Note we exit the loop if i2400mu_tx() fails; that funtion only
+ * fails on hard error (failing to tx a buffer not being one of them,
+ * see its doc).
+ *
+ * Return: 0
+ */
+static
+int i2400mu_txd(void *_i2400mu)
+{
+        int result = 0;
+        struct i2400mu *i2400mu = _i2400mu;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct i2400m_msg_hdr *tx_msg;
+        size_t tx_msg_size;
+
+        d_fnstart(4, dev, "(i2400mu %p)\n", i2400mu);
+
+        while (1) {
+                d_printf(2, dev, "TX: waiting for messages\n");
+                tx_msg = NULL;
+                wait_event_interruptible(
+                        i2400mu->tx_wq,
+                        (kthread_should_stop()  /* check this first! */
+                         || (tx_msg = i2400m_tx_msg_get(i2400m, &tx_msg_size)))
+                        );
+                if (kthread_should_stop())
+                        break;
+                WARN_ON(tx_msg == NULL);        /* should not happen...*/
+                d_printf(2, dev, "TX: submitting %zu bytes\n", tx_msg_size);
+                d_dump(5, dev, tx_msg, tx_msg_size);
+                /* Yeah, we ignore errors ... not much we can do */
+                i2400mu_tx(i2400mu, tx_msg, tx_msg_size);
+                i2400m_tx_msg_sent(i2400m);     /* ack it, advance the FIFO */
+                if (result < 0)
+                        break;
+        }
+        d_fnend(4, dev, "(i2400mu %p) = %d\n", i2400mu, result);
+        return result;
+}
+
+
+/*
+ * i2400m TX engine notifies us that there is data in the FIFO ready
+ * for TX
+ *
+ * If there is a URB in flight, don't do anything; when it finishes,
+ * it will see there is data in the FIFO and send it. Else, just
+ * submit a write.
+ */
+void i2400mu_bus_tx_kick(struct i2400m *i2400m)
+{
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(3, dev, "(i2400m %p) = void\n", i2400m);
+        wake_up_all(&i2400mu->tx_wq);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+
+
+int i2400mu_tx_setup(struct i2400mu *i2400mu)
+{
+        int result = 0;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct wimax_dev *wimax_dev = &i2400m->wimax_dev;
+
+        i2400mu->tx_kthread = kthread_run(i2400mu_txd, i2400mu, "%s-tx",
+                                          wimax_dev->name);
+        if (IS_ERR(i2400mu->tx_kthread)) {
+                result = PTR_ERR(i2400mu->tx_kthread);
+                dev_err(dev, "TX: cannot start thread: %d\n", result);
+        }
+        return result;
+}
+
+void i2400mu_tx_release(struct i2400mu *i2400mu)
+{
+        kthread_stop(i2400mu->tx_kthread);
+}
diff --git a/drivers/net/wimax/i2400m/usb.c b/drivers/net/wimax/i2400m/usb.c
new file mode 100644
index 000000000000..6d4b65fd9c17
--- /dev/null
+++ b/drivers/net/wimax/i2400m/usb.c
@@ -0,0 +1,591 @@
+/*
+ * Intel Wireless WiMAX Connection 2400m
+ * Linux driver model glue for USB device, reset & fw upload
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ * Yanir Lubetkin <yanirx.lubetkin@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * See i2400m-usb.h for a general description of this driver.
+ *
+ * This file implements driver model glue, and hook ups for the
+ * generic driver to implement the bus-specific functions (device
+ * communication setup/tear down, firmware upload and resetting).
+ *
+ * ROADMAP
+ *
+ * i2400mu_probe()
+ *   alloc_netdev()...
+ *     i2400mu_netdev_setup()
+ *       i2400mu_init()
+ *       i2400m_netdev_setup()
+ *   i2400m_setup()...
+ *
+ * i2400mu_disconnect
+ *   i2400m_release()
+ *   free_netdev()
+ *
+ * i2400mu_suspend()
+ *   i2400m_cmd_enter_powersave()
+ *   i2400mu_notification_release()
+ *
+ * i2400mu_resume()
+ *   i2400mu_notification_setup()
+ *
+ * i2400mu_bus_dev_start()        Called by i2400m_dev_start() [who is
+ *   i2400mu_tx_setup()           called by i2400m_setup()]
+ *   i2400mu_rx_setup()
+ *   i2400mu_notification_setup()
+ *
+ * i2400mu_bus_dev_stop()         Called by i2400m_dev_stop() [who is
+ *   i2400mu_notification_release()  called by i2400m_release()]
+ *   i2400mu_rx_release()
+ *   i2400mu_tx_release()
+ *
+ * i2400mu_bus_reset()            Called by i2400m->bus_reset
+ *   __i2400mu_reset()
+ *     __i2400mu_send_barker()
+ *   usb_reset_device()
+ */
+#include "i2400m-usb.h"
+#include <linux/wimax/i2400m.h>
+#include <linux/debugfs.h>
+
+
+#define D_SUBMODULE usb
+#include "usb-debug-levels.h"
+
+
+/* Our firmware file name */
+#define I2400MU_FW_FILE_NAME "i2400m-fw-usb-" I2400M_FW_VERSION ".sbcf"
+
+static
+int i2400mu_bus_dev_start(struct i2400m *i2400m)
+{
+        int result;
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        result = i2400mu_tx_setup(i2400mu);
+        if (result < 0)
+                goto error_usb_tx_setup;
+        result = i2400mu_rx_setup(i2400mu);
+        if (result < 0)
+                goto error_usb_rx_setup;
+        result = i2400mu_notification_setup(i2400mu);
+        if (result < 0)
+                goto error_notif_setup;
+        d_fnend(3, dev, "(i2400m %p) = %d\n", i2400m, result);
+        return result;
+
+error_notif_setup:
+        i2400mu_rx_release(i2400mu);
+error_usb_rx_setup:
+        i2400mu_tx_release(i2400mu);
+error_usb_tx_setup:
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+        return result;
+}
+
+
+static
+void i2400mu_bus_dev_stop(struct i2400m *i2400m)
+{
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        struct device *dev = &i2400mu->usb_iface->dev;
+
+        d_fnstart(3, dev, "(i2400m %p)\n", i2400m);
+        i2400mu_notification_release(i2400mu);
+        i2400mu_rx_release(i2400mu);
+        i2400mu_tx_release(i2400mu);
+        d_fnend(3, dev, "(i2400m %p) = void\n", i2400m);
+}
+
+
+/*
+ * Sends a barker buffer to the device
+ *
+ * This helper will allocate a kmalloced buffer and use it to transmit
+ * (then free it). Reason for this is that other arches cannot use
+ * stack/vmalloc/text areas for DMA transfers.
+ *
+ * Error recovery here is simpler: anything is considered a hard error
+ * and will move the reset code to use a last-resort bus-based reset.
+ */
+static
+int __i2400mu_send_barker(struct i2400mu *i2400mu,
+                          const __le32 *barker,
+                          size_t barker_size,
+                          unsigned endpoint)
+{
+        struct usb_endpoint_descriptor *epd = NULL;
+        int pipe, actual_len, ret;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        void *buffer;
+        int do_autopm = 1;
+
+        ret = usb_autopm_get_interface(i2400mu->usb_iface);
+        if (ret < 0) {
+                dev_err(dev, "RESET: can't get autopm: %d\n", ret);
+                do_autopm = 0;
+        }
+        ret = -ENOMEM;
+        buffer = kmalloc(barker_size, GFP_KERNEL);
+        if (buffer == NULL)
+                goto error_kzalloc;
+        epd = usb_get_epd(i2400mu->usb_iface, endpoint);
+        pipe = usb_sndbulkpipe(i2400mu->usb_dev, epd->bEndpointAddress);
+        memcpy(buffer, barker, barker_size);
+        ret = usb_bulk_msg(i2400mu->usb_dev, pipe, buffer, barker_size,
+                           &actual_len, HZ);
+        if (ret < 0) {
+                if (ret != -EINVAL)
+                        dev_err(dev, "E: barker error: %d\n", ret);
+        } else if (actual_len != barker_size) {
+                dev_err(dev, "E: only %d bytes transmitted\n", actual_len);
+                ret = -EIO;
+        }
+        kfree(buffer);
+error_kzalloc:
+        if (do_autopm)
+                usb_autopm_put_interface(i2400mu->usb_iface);
+        return ret;
+}
+
+
+/*
+ * Reset a device at different levels (warm, cold or bus)
+ *
+ * @i2400m: device descriptor
+ * @reset_type: soft, warm or bus reset (I2400M_RT_WARM/SOFT/BUS)
+ *
+ * Warm and cold resets get a USB reset if they fail.
+ *
+ * Warm reset:
+ *
+ * The device will be fully reset internally, but won't be
+ * disconnected from the USB bus (so no reenumeration will
+ * happen). Firmware upload will be neccessary.
+ *
+ * The device will send a reboot barker in the notification endpoint
+ * that will trigger the driver to reinitialize the state
+ * automatically from notif.c:i2400m_notification_grok() into
+ * i2400m_dev_bootstrap_delayed().
+ *
+ * Cold and bus (USB) reset:
+ *
+ * The device will be fully reset internally, disconnected from the
+ * USB bus an a reenumeration will happen. Firmware upload will be
+ * neccessary. Thus, we don't do any locking or struct
+ * reinitialization, as we are going to be fully disconnected and
+ * reenumerated.
+ *
+ * Note we need to return -ENODEV if a warm reset was requested and we
+ * had to resort to a bus reset. See i2400m_op_reset(), wimax_reset()
+ * and wimax_dev->op_reset.
+ *
+ * WARNING: no driver state saved/fixed
+ */
+static
+int i2400mu_bus_reset(struct i2400m *i2400m, enum i2400m_reset_type rt)
+{
+        int result;
+        struct i2400mu *i2400mu =
+                container_of(i2400m, struct i2400mu, i2400m);
+        struct device *dev = i2400m_dev(i2400m);
+        static const __le32 i2400m_WARM_BOOT_BARKER[4] = {
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_WARM_RESET_BARKER),
+        };
+        static const __le32 i2400m_COLD_BOOT_BARKER[4] = {
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+                __constant_cpu_to_le32(I2400M_COLD_RESET_BARKER),
+        };
+
+        d_fnstart(3, dev, "(i2400m %p rt %u)\n", i2400m, rt);
+        if (rt == I2400M_RT_WARM)
+                result = __i2400mu_send_barker(i2400mu, i2400m_WARM_BOOT_BARKER,
+                                               sizeof(i2400m_WARM_BOOT_BARKER),
+                                               I2400MU_EP_BULK_OUT);
+        else if (rt == I2400M_RT_COLD)
+                result = __i2400mu_send_barker(i2400mu, i2400m_COLD_BOOT_BARKER,
+                                               sizeof(i2400m_COLD_BOOT_BARKER),
+                                               I2400MU_EP_RESET_COLD);
+        else if (rt == I2400M_RT_BUS) {
+do_bus_reset:
+                result = usb_reset_device(i2400mu->usb_dev);
+                switch (result) {
+                case 0:
+                case -EINVAL:   /* device is gone */
+                case -ENODEV:
+                case -ENOENT:
+                case -ESHUTDOWN:
+                        result = rt == I2400M_RT_WARM ? -ENODEV : 0;
+                        break;  /* We assume the device is disconnected */
+                default:
+                        dev_err(dev, "USB reset failed (%d), giving up!\n",
+                                result);
+                }
+        } else
+                BUG();
+        if (result < 0
+            && result != -EINVAL        /* device is gone */
+            && rt != I2400M_RT_BUS) {
+                dev_err(dev, "%s reset failed (%d); trying USB reset\n",
+                        rt == I2400M_RT_WARM ? "warm" : "cold", result);
+                rt = I2400M_RT_BUS;
+                goto do_bus_reset;
+        }
+        d_fnend(3, dev, "(i2400m %p rt %u) = %d\n", i2400m, rt, result);
+        return result;
+}
+
+
+static
+void i2400mu_netdev_setup(struct net_device *net_dev)
+{
+        struct i2400m *i2400m = net_dev_to_i2400m(net_dev);
+        struct i2400mu *i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        i2400mu_init(i2400mu);
+        i2400m_netdev_setup(net_dev);
+}
+
+
+/*
+ * Debug levels control; see debug.h
+ */
+struct d_level D_LEVEL[] = {
+        D_SUBMODULE_DEFINE(usb),
+        D_SUBMODULE_DEFINE(fw),
+        D_SUBMODULE_DEFINE(notif),
+        D_SUBMODULE_DEFINE(rx),
+        D_SUBMODULE_DEFINE(tx),
+};
+size_t D_LEVEL_SIZE = ARRAY_SIZE(D_LEVEL);
+
+
+#define __debugfs_register(prefix, name, parent)                        \
+do {                                                                    \
+        result = d_level_register_debugfs(prefix, name, parent);        \
+        if (result < 0)                                                 \
+                goto error;                                             \
+} while (0)
+
+
+static
+int i2400mu_debugfs_add(struct i2400mu *i2400mu)
+{
+        int result;
+        struct device *dev = &i2400mu->usb_iface->dev;
+        struct dentry *dentry = i2400mu->i2400m.wimax_dev.debugfs_dentry;
+        struct dentry *fd;
+
+        dentry = debugfs_create_dir("i2400m-usb", dentry);
+        result = PTR_ERR(dentry);
+        if (IS_ERR(dentry)) {
+                if (result == -ENODEV)
+                        result = 0;     /* No debugfs support */
+                goto error;
+        }
+        i2400mu->debugfs_dentry = dentry;
+        __debugfs_register("dl_", usb, dentry);
+        __debugfs_register("dl_", fw, dentry);
+        __debugfs_register("dl_", notif, dentry);
+        __debugfs_register("dl_", rx, dentry);
+        __debugfs_register("dl_", tx, dentry);
+
+        /* Don't touch these if you don't know what you are doing */
+        fd = debugfs_create_u8("rx_size_auto_shrink", 0600, dentry,
+                               &i2400mu->rx_size_auto_shrink);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "rx_size_auto_shrink: %d\n", result);
+                goto error;
+        }
+
+        fd = debugfs_create_size_t("rx_size", 0600, dentry,
+                                   &i2400mu->rx_size);
+        result = PTR_ERR(fd);
+        if (IS_ERR(fd) && result != -ENODEV) {
+                dev_err(dev, "Can't create debugfs entry "
+                        "rx_size: %d\n", result);
+                goto error;
+        }
+
+        return 0;
+
+error:
+        debugfs_remove_recursive(i2400mu->debugfs_dentry);
+        return result;
+}
+
+
+/*
+ * Probe a i2400m interface and register it
+ *
+ * @iface:   USB interface to link to
+ * @id:      USB class/subclass/protocol id
+ * @returns: 0 if ok, < 0 errno code on error.
+ *
+ * Alloc a net device, initialize the bus-specific details and then
+ * calls the bus-generic initialization routine. That will register
+ * the wimax and netdev devices, upload the firmware [using
+ * _bus_bm_*()], call _bus_dev_start() to finalize the setup of the
+ * communication with the device and then will start to talk to it to
+ * finnish setting it up.
+ */
+static
+int i2400mu_probe(struct usb_interface *iface,
+                  const struct usb_device_id *id)
+{
+        int result;
+        struct net_device *net_dev;
+        struct device *dev = &iface->dev;
+        struct i2400m *i2400m;
+        struct i2400mu *i2400mu;
+        struct usb_device *usb_dev = interface_to_usbdev(iface);
+
+        if (usb_dev->speed != USB_SPEED_HIGH)
+                dev_err(dev, "device not connected as high speed\n");
+
+        /* Allocate instance [calls i2400m_netdev_setup() on it]. */
+        result = -ENOMEM;
+        net_dev = alloc_netdev(sizeof(*i2400mu), "wmx%d",
+                               i2400mu_netdev_setup);
+        if (net_dev == NULL) {
+                dev_err(dev, "no memory for network device instance\n");
+                goto error_alloc_netdev;
+        }
+        SET_NETDEV_DEV(net_dev, dev);
+        i2400m = net_dev_to_i2400m(net_dev);
+        i2400mu = container_of(i2400m, struct i2400mu, i2400m);
+        i2400m->wimax_dev.net_dev = net_dev;
+        i2400mu->usb_dev = usb_get_dev(usb_dev);
+        i2400mu->usb_iface = iface;
+        usb_set_intfdata(iface, i2400mu);
+
+        i2400m->bus_tx_block_size = I2400MU_BLK_SIZE;
+        i2400m->bus_pl_size_max = I2400MU_PL_SIZE_MAX;
+        i2400m->bus_dev_start = i2400mu_bus_dev_start;
+        i2400m->bus_dev_stop = i2400mu_bus_dev_stop;
+        i2400m->bus_tx_kick = i2400mu_bus_tx_kick;
+        i2400m->bus_reset = i2400mu_bus_reset;
+        i2400m->bus_bm_cmd_send = i2400mu_bus_bm_cmd_send;
+        i2400m->bus_bm_wait_for_ack = i2400mu_bus_bm_wait_for_ack;
+        i2400m->bus_fw_name = I2400MU_FW_FILE_NAME;
+        i2400m->bus_bm_mac_addr_impaired = 0;
+
+        iface->needs_remote_wakeup = 1;         /* autosuspend (15s delay) */
+        device_init_wakeup(dev, 1);
+        usb_autopm_enable(i2400mu->usb_iface);
+        usb_dev->autosuspend_delay = 15 * HZ;
+        usb_dev->autosuspend_disabled = 0;
+
+        result = i2400m_setup(i2400m, I2400M_BRI_MAC_REINIT);
+        if (result < 0) {
+                dev_err(dev, "cannot setup device: %d\n", result);
+                goto error_setup;
+        }
+        result = i2400mu_debugfs_add(i2400mu);
+        if (result < 0) {
+                dev_err(dev, "Can't register i2400mu's debugfs: %d\n", result);
+                goto error_debugfs_add;
+        }
+        return 0;
+
+error_debugfs_add:
+        i2400m_release(i2400m);
+error_setup:
+        usb_set_intfdata(iface, NULL);
+        usb_put_dev(i2400mu->usb_dev);
+        free_netdev(net_dev);
+error_alloc_netdev:
+        return result;
+}
+
+
+/*
+ * Disconect a i2400m from the system.
+ *
+ * i2400m_stop() has been called before, so al the rx and tx contexts
+ * have been taken down already. Make sure the queue is stopped,
+ * unregister netdev and i2400m, free and kill.
+ */
+static
+void i2400mu_disconnect(struct usb_interface *iface)
+{
+        struct i2400mu *i2400mu = usb_get_intfdata(iface);
+        struct i2400m *i2400m = &i2400mu->i2400m;
+        struct net_device *net_dev = i2400m->wimax_dev.net_dev;
+        struct device *dev = &iface->dev;
+
+        d_fnstart(3, dev, "(iface %p i2400m %p)\n", iface, i2400m);
+
+        debugfs_remove_recursive(i2400mu->debugfs_dentry);
+        i2400m_release(i2400m);
+        usb_set_intfdata(iface, NULL);
+        usb_put_dev(i2400mu->usb_dev);
+        free_netdev(net_dev);
+        d_fnend(3, dev, "(iface %p i2400m %p) = void\n", iface, i2400m);
+}
+
+
+/*
+ * Get the device ready for USB port or system standby and hibernation
+ *
+ * USB port and system standby are handled the same.
+ *
+ * When the system hibernates, the USB device is powered down and then
+ * up, so we don't really have to do much here, as it will be seen as
+ * a reconnect. Still for simplicity we consider this case the same as
+ * suspend, so that the device has a chance to do notify the base
+ * station (if connected).
+ *
+ * So at the end, the three cases require common handling.
+ *
+ * If at the time of this call the device's firmware is not loaded,
+ * nothing has to be done.
+ *
+ * If the firmware is loaded, we need to:
+ *
+ *  - tell the device to go into host interface power save mode, wait
+ *    for it to ack
+ *
+ *    This is quite more interesting than it is; we need to execute a
+ *    command, but this time, we don't want the code in usb-{tx,rx}.c
+ *    to call the usb_autopm_get/put_interface() barriers as it'd
+ *    deadlock, so we need to decrement i2400mu->do_autopm, that acts
+ *    as a poor man's semaphore. Ugly, but it works.
+ *
+ *    As well, the device might refuse going to sleep for whichever
+ *    reason. In this case we just fail. For system suspend/hibernate,
+ *    we *can't* fail. We look at usb_dev->auto_pm to see if the
+ *    suspend call comes from the USB stack or from the system and act
+ *    in consequence.
+ *
+ *  - stop the notification endpoint polling
+ */
+static
+int i2400mu_suspend(struct usb_interface *iface, pm_message_t pm_msg)
+{
+        int result = 0;
+        struct device *dev = &iface->dev;
+        struct i2400mu *i2400mu = usb_get_intfdata(iface);
+        struct usb_device *usb_dev = i2400mu->usb_dev;
+        struct i2400m *i2400m = &i2400mu->i2400m;
+
+        d_fnstart(3, dev, "(iface %p pm_msg %u)\n", iface, pm_msg.event);
+        if (i2400m->updown == 0)
+                goto no_firmware;
+        d_printf(1, dev, "fw up, requesting standby\n");
+        atomic_dec(&i2400mu->do_autopm);
+        result = i2400m_cmd_enter_powersave(i2400m);
+        atomic_inc(&i2400mu->do_autopm);
+        if (result < 0 && usb_dev->auto_pm == 0) {
+                /* System suspend, can't fail */
+                dev_err(dev, "failed to suspend, will reset on resume\n");
+                result = 0;
+        }
+        if (result < 0)
+                goto error_enter_powersave;
+        i2400mu_notification_release(i2400mu);
+        d_printf(1, dev, "fw up, got standby\n");
+error_enter_powersave:
+no_firmware:
+        d_fnend(3, dev, "(iface %p pm_msg %u) = %d\n",
+                iface, pm_msg.event, result);
+        return result;
+}
+
+
+static
+int i2400mu_resume(struct usb_interface *iface)
+{
+        int ret = 0;
+        struct device *dev = &iface->dev;
+        struct i2400mu *i2400mu = usb_get_intfdata(iface);
+        struct i2400m *i2400m = &i2400mu->i2400m;
+
+        d_fnstart(3, dev, "(iface %p)\n", iface);
+        if (i2400m->updown == 0) {
+                d_printf(1, dev, "fw was down, no resume neeed\n");
+                goto out;
+        }
+        d_printf(1, dev, "fw was up, resuming\n");
+        i2400mu_notification_setup(i2400mu);
+        /* USB has flow control, so we don't need to give it time to
+         * come back; otherwise, we'd use something like a get-state
+         * command... */
+out:
+        d_fnend(3, dev, "(iface %p) = %d\n", iface, ret);
+        return ret;
+}
+
+
+static
+struct usb_device_id i2400mu_id_table[] = {
+        { USB_DEVICE(0x8086, 0x0181) },
+        { USB_DEVICE(0x8086, 0x1403) },
+        { USB_DEVICE(0x8086, 0x1405) },
+        { USB_DEVICE(0x8086, 0x0180) },
+        { USB_DEVICE(0x8086, 0x0182) },
+        { USB_DEVICE(0x8086, 0x1406) },
+        { USB_DEVICE(0x8086, 0x1403) },
+        { },
+};
+MODULE_DEVICE_TABLE(usb, i2400mu_id_table);
+
+
+static
+struct usb_driver i2400mu_driver = {
+        .name = KBUILD_MODNAME,
+        .suspend = i2400mu_suspend,
+        .resume = i2400mu_resume,
+        .probe = i2400mu_probe,
+        .disconnect = i2400mu_disconnect,
+        .id_table = i2400mu_id_table,
+        .supports_autosuspend = 1,
+};
+
+static
+int __init i2400mu_driver_init(void)
+{
+        return usb_register(&i2400mu_driver);
+}
+module_init(i2400mu_driver_init);
+
+
+static
+void __exit i2400mu_driver_exit(void)
+{
+        flush_scheduled_work(); /* for the stuff we schedule from sysfs.c */
+        usb_deregister(&i2400mu_driver);
+}
+module_exit(i2400mu_driver_exit);
+
+MODULE_AUTHOR("Intel Corporation <linux-wimax@intel.com>");
+MODULE_DESCRIPTION("Intel 2400M WiMAX networking for USB");
+MODULE_LICENSE("GPL");
+MODULE_FIRMWARE(I2400MU_FW_FILE_NAME);
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 350157fcd080..4223672c4432 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -3836,7 +3836,7 @@ static int reset_atmel_card(struct net_device *dev)
            This routine is also responsible for initialising some
            hardware-specific fields in the atmel_private structure,
            including a copy of the firmware's hostinfo stucture
-           which is the route into the rest of the firmare datastructures. */
+           which is the route into the rest of the firmware datastructures. */
 
         struct atmel_private *priv = netdev_priv(dev);
         u8 configuration;
diff --git a/drivers/net/wireless/ipw2x00/ipw2100.c b/drivers/net/wireless/ipw2x00/ipw2100.c
index 1667065b86a7..823c2bf5e31e 100644
--- a/drivers/net/wireless/ipw2x00/ipw2100.c
+++ b/drivers/net/wireless/ipw2x00/ipw2100.c
@@ -1332,7 +1332,7 @@ static int ipw2100_power_cycle_adapter(struct ipw2100_priv *priv)
                        IPW_AUX_HOST_RESET_REG_STOP_MASTER);
 
         /* Step 2. Wait for stop Master Assert
-         *         (not more then 50us, otherwise ret error */
+         *         (not more than 50us, otherwise ret error */
         i = 5;
         do {
                 udelay(IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY);
@@ -1830,7 +1830,7 @@ static void ipw2100_down(struct ipw2100_priv *priv)
                 cancel_delayed_work(&priv->rf_kill);
         }
 
-        /* Kill the firmare hang check timer */
+        /* Kill the firmware hang check timer */
         if (!priv->stop_hang_check) {
                 priv->stop_hang_check = 1;
                 cancel_delayed_work(&priv->hang_check);
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index 37ad0d2fb64c..aee9cba13eb3 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -184,8 +184,8 @@ void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, unsigned int align,
          * Make room for new data, note that we increase both
          * headsize and tailsize when required. The tailsize is
          * only needed when ICV data needs to be inserted and
-         * the padding is smaller then the ICV data.
-         * When alignment requirements is greater then the
+         * the padding is smaller than the ICV data.
+         * When alignment requirements is greater than the
          * ICV data we must trim the skb to the correct size
          * because we need to remove the extra bytes.
          */
diff --git a/drivers/net/wireless/strip.c b/drivers/net/wireless/strip.c
index dd0de3a9ed4e..7015f2480550 100644
--- a/drivers/net/wireless/strip.c
+++ b/drivers/net/wireless/strip.c
@@ -236,7 +236,7 @@ struct strip {
         unsigned long tx_errors;        /* Planned stuff                */
         unsigned long rx_dropped;       /* No memory for skb            */
         unsigned long tx_dropped;       /* When MTU change              */
-        unsigned long rx_over_errors;   /* Frame bigger then STRIP buf. */
+        unsigned long rx_over_errors;   /* Frame bigger than STRIP buf. */
 
         unsigned long pps_timer;        /* Timer to determine pps       */
         unsigned long rx_pps_count;     /* Counter to determine pps     */
diff --git a/drivers/rtc/rtc-ds1511.c b/drivers/rtc/rtc-ds1511.c
index 23a07fe15a2c..0b6b7730c716 100644
--- a/drivers/rtc/rtc-ds1511.c
+++ b/drivers/rtc/rtc-ds1511.c
@@ -630,7 +630,7 @@ ds1511_rtc_init(void)
  static void __exit
 ds1511_rtc_exit(void)
 {
-        return platform_driver_unregister(&ds1511_rtc_driver);
+        platform_driver_unregister(&ds1511_rtc_driver);
 }
 
 module_init(ds1511_rtc_init);
diff --git a/drivers/rtc/rtc-stk17ta8.c b/drivers/rtc/rtc-stk17ta8.c
index dc0b6224ad9b..7d1547b0070e 100644
--- a/drivers/rtc/rtc-stk17ta8.c
+++ b/drivers/rtc/rtc-stk17ta8.c
@@ -399,7 +399,7 @@ static __init int stk17ta8_init(void)
 
 static __exit void stk17ta8_exit(void)
 {
-        return platform_driver_unregister(&stk17ta8_rtc_driver);
+        platform_driver_unregister(&stk17ta8_rtc_driver);
 }
 
 module_init(stk17ta8_init);
diff --git a/drivers/s390/block/dasd_eer.c b/drivers/s390/block/dasd_eer.c
index 892e2878d61b..f8e05ce98621 100644
--- a/drivers/s390/block/dasd_eer.c
+++ b/drivers/s390/block/dasd_eer.c
@@ -535,8 +535,8 @@ static int dasd_eer_open(struct inode *inp, struct file *filp)
             eerb->buffer_page_count > INT_MAX / PAGE_SIZE) {
                 kfree(eerb);
                 MESSAGE(KERN_WARNING, "can't open device since module "
-                        "parameter eer_pages is smaller then 1 or"
-                        " bigger then %d", (int)(INT_MAX / PAGE_SIZE));
+                        "parameter eer_pages is smaller than 1 or"
+                        " bigger than %d", (int)(INT_MAX / PAGE_SIZE));
                 unlock_kernel();
                 return -EINVAL;
         }
diff --git a/drivers/s390/char/vmlogrdr.c b/drivers/s390/char/vmlogrdr.c
index aabbeb909cc6..d8a2289fcb69 100644
--- a/drivers/s390/char/vmlogrdr.c
+++ b/drivers/s390/char/vmlogrdr.c
@@ -427,7 +427,7 @@ static int vmlogrdr_receive_data(struct vmlogrdr_priv_t *priv)
                         buffer = priv->buffer + sizeof(int);
                 }
                 /*
-                 * If the record is bigger then our buffer, we receive only
+                 * If the record is bigger than our buffer, we receive only
                  * a part of it. We can get the rest later.
                  */
                 if (iucv_data_count > NET_BUFFER_SIZE)
@@ -437,7 +437,7 @@ static int vmlogrdr_receive_data(struct vmlogrdr_priv_t *priv)
                                           0, buffer, iucv_data_count,
                                           &priv->residual_length);
                 spin_unlock_bh(&priv->priv_lock);
-                /* An rc of 5 indicates that the record was bigger then
+                /* An rc of 5 indicates that the record was bigger than
                  * the buffer, which is OK for us. A 9 indicates that the
                  * record was purged befor we could receive it.
                  */
diff --git a/drivers/scsi/a100u2w.c b/drivers/scsi/a100u2w.c
index 3c298c7253ee..964769f66eac 100644
--- a/drivers/scsi/a100u2w.c
+++ b/drivers/scsi/a100u2w.c
@@ -633,7 +633,7 @@ static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsig
                 return FAILED;
         }
 
-        /* Reset device is handled by the firmare, we fill in an SCB and
+        /* Reset device is handled by the firmware, we fill in an SCB and
            fire it at the controller, it does the rest */
         scb->opcode = ORC_BUSDEVRST;
         scb->target = target;
diff --git a/drivers/scsi/lpfc/lpfc_hbadisc.c b/drivers/scsi/lpfc/lpfc_hbadisc.c
index 8c64494444bf..311ed6dea726 100644
--- a/drivers/scsi/lpfc/lpfc_hbadisc.c
+++ b/drivers/scsi/lpfc/lpfc_hbadisc.c
@@ -1964,10 +1964,10 @@ lpfc_set_disctmo(struct lpfc_vport *vport)
         uint32_t tmo;
 
         if (vport->port_state == LPFC_LOCAL_CFG_LINK) {
-                /* For FAN, timeout should be greater then edtov */
+                /* For FAN, timeout should be greater than edtov */
                 tmo = (((phba->fc_edtov + 999) / 1000) + 1);
         } else {
-                /* Normal discovery timeout should be > then ELS/CT timeout
+                /* Normal discovery timeout should be > than ELS/CT timeout
                  * FC spec states we need 3 * ratov for CT requests
                  */
                 tmo = ((phba->fc_ratov * 3) + 3);
diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c
index 01dfdc8696f8..a36a120561e2 100644
--- a/drivers/scsi/lpfc/lpfc_sli.c
+++ b/drivers/scsi/lpfc/lpfc_sli.c
@@ -420,7 +420,7 @@ lpfc_sli_next_iocb_slot (struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
                 if (unlikely(pring->local_getidx >= max_cmd_idx)) {
                         lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
                                         "0315 Ring %d issue: portCmdGet %d "
-                                        "is bigger then cmd ring %d\n",
+                                        "is bigger than cmd ring %d\n",
                                         pring->ringno,
                                         pring->local_getidx, max_cmd_idx);
 
@@ -1628,12 +1628,12 @@ lpfc_sli_rsp_pointers_error(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
 {
         struct lpfc_pgp *pgp = &phba->port_gp[pring->ringno];
         /*
-         * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
+         * Ring <ringno> handler: portRspPut <portRspPut> is bigger than
          * rsp ring <portRspMax>
          */
         lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
                         "0312 Ring %d handler: portRspPut %d "
-                        "is bigger then rsp ring %d\n",
+                        "is bigger than rsp ring %d\n",
                         pring->ringno, le32_to_cpu(pgp->rspPutInx),
                         pring->numRiocb);
 
@@ -2083,12 +2083,12 @@ lpfc_sli_handle_slow_ring_event(struct lpfc_hba *phba,
         portRspPut = le32_to_cpu(pgp->rspPutInx);
         if (portRspPut >= portRspMax) {
                 /*
-                 * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
+                 * Ring <ringno> handler: portRspPut <portRspPut> is bigger than
                  * rsp ring <portRspMax>
                  */
                 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
                                 "0303 Ring %d handler: portRspPut %d "
-                                "is bigger then rsp ring %d\n",
+                                "is bigger than rsp ring %d\n",
                                 pring->ringno, portRspPut, portRspMax);
 
                 phba->link_state = LPFC_HBA_ERROR;
diff --git a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c
index 7dc62deb4087..9fdcd60c5493 100644
--- a/drivers/scsi/megaraid.c
+++ b/drivers/scsi/megaraid.c
@@ -1967,8 +1967,8 @@ megaraid_abort_and_reset(adapter_t *adapter, Scsi_Cmnd *cmd, int aor)
                         scb->state |= aor;
 
                         /*
-                         * Check if this command has firmare owenership. If
-                         * yes, we cannot reset this command. Whenever, f/w
+                         * Check if this command has firmware ownership. If
+                         * yes, we cannot reset this command. Whenever f/w
                          * completes this command, we will return appropriate
                          * status from ISR.
                          */
diff --git a/drivers/scsi/qla1280.c b/drivers/scsi/qla1280.c
index 8cb9240596ab..df09820e8916 100644
--- a/drivers/scsi/qla1280.c
+++ b/drivers/scsi/qla1280.c
@@ -128,7 +128,7 @@
         - Integrate ql12160_set_target_parameters() with 1280 version
         - Make qla1280_setup() non static
         - Do not call qla1280_check_for_dead_scsi_bus() on every I/O request
-          sent to the card - this command pauses the firmare!!!
+          sent to the card - this command pauses the firmware!!!
     Rev  3.23.15 Beta March 19, 2002, Jes Sorensen
         - Clean up qla1280.h - remove obsolete QL_DEBUG_LEVEL_x definitions
         - Remove a pile of pointless and confusing (srb_t **) and
@@ -659,7 +659,7 @@ static int qla1280_read_nvram(struct scsi_qla_host *ha)
         /* The firmware interface is, um, interesting, in that the
          * actual firmware image on the chip is little endian, thus,
          * the process of taking that image to the CPU would end up
-         * little endian.  However, the firmare interface requires it
+         * little endian.  However, the firmware interface requires it
          * to be read a word (two bytes) at a time.
          *
          * The net result of this would be that the word (and
diff --git a/drivers/scsi/qla4xxx/ql4_mbx.c b/drivers/scsi/qla4xxx/ql4_mbx.c
index c577d79bd7e8..051b0f5e8c8e 100644
--- a/drivers/scsi/qla4xxx/ql4_mbx.c
+++ b/drivers/scsi/qla4xxx/ql4_mbx.c
@@ -392,7 +392,7 @@ int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
                 ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
         else
                 dev_info(&ha->pdev->dev, "WARNING!!!  You have less than %d "
-                           "firmare IOCBs available (%d).\n",
+                           "firmware IOCBs available (%d).\n",
                            IOCB_HIWAT_CUSHION, ha->iocb_hiwat);
 
         return QLA_SUCCESS;
diff --git a/drivers/scsi/scsi_error.c b/drivers/scsi/scsi_error.c
index 381838ebd460..d86ebea9350a 100644
--- a/drivers/scsi/scsi_error.c
+++ b/drivers/scsi/scsi_error.c
@@ -1650,7 +1650,7 @@ int scsi_error_handler(void *data)
          * We use TASK_INTERRUPTIBLE so that the thread is not
          * counted against the load average as a running process.
          * We never actually get interrupted because kthread_run
-         * disables singal delivery for the created thread.
+         * disables signal delivery for the created thread.
          */
         set_current_state(TASK_INTERRUPTIBLE);
         while (!kthread_should_stop()) {
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index 18486b51668d..17914a346f71 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -32,6 +32,7 @@
 #include <linux/delay.h>
 #include <linux/kthread.h>
 #include <linux/spinlock.h>
+#include <linux/async.h>
 
 #include <scsi/scsi.h>
 #include <scsi/scsi_cmnd.h>
@@ -179,6 +180,8 @@ int scsi_complete_async_scans(void)
         spin_unlock(&async_scan_lock);
 
         kfree(data);
+        /* Synchronize async operations globally */
+        async_synchronize_full();
         return 0;
 }
 
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index 62b28d58e65e..e035c1114010 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -48,6 +48,7 @@
 #include <linux/delay.h>
 #include <linux/mutex.h>
 #include <linux/string_helpers.h>
+#include <linux/async.h>
 #include <asm/uaccess.h>
 
 #include <scsi/scsi.h>
@@ -1802,6 +1803,71 @@ static int sd_format_disk_name(char *prefix, int index, char *buf, int buflen)
         return 0;
 }
 
+/*
+ * The asynchronous part of sd_probe
+ */
+static void sd_probe_async(void *data, async_cookie_t cookie)
+{
+        struct scsi_disk *sdkp = data;
+        struct scsi_device *sdp;
+        struct gendisk *gd;
+        u32 index;
+        struct device *dev;
+
+        sdp = sdkp->device;
+        gd = sdkp->disk;
+        index = sdkp->index;
+        dev = &sdp->sdev_gendev;
+
+        if (!sdp->request_queue->rq_timeout) {
+                if (sdp->type != TYPE_MOD)
+                        blk_queue_rq_timeout(sdp->request_queue, SD_TIMEOUT);
+                else
+                        blk_queue_rq_timeout(sdp->request_queue,
+                                             SD_MOD_TIMEOUT);
+        }
+
+        device_initialize(&sdkp->dev);
+        sdkp->dev.parent = &sdp->sdev_gendev;
+        sdkp->dev.class = &sd_disk_class;
+        strncpy(sdkp->dev.bus_id, sdp->sdev_gendev.bus_id, BUS_ID_SIZE);
+
+        if (device_add(&sdkp->dev))
+                goto out_free_index;
+
+        get_device(&sdp->sdev_gendev);
+
+        if (index < SD_MAX_DISKS) {
+                gd->major = sd_major((index & 0xf0) >> 4);
+                gd->first_minor = ((index & 0xf) << 4) | (index & 0xfff00);
+                gd->minors = SD_MINORS;
+        }
+        gd->fops = &sd_fops;
+        gd->private_data = &sdkp->driver;
+        gd->queue = sdkp->device->request_queue;
+
+        sd_revalidate_disk(gd);
+
+        blk_queue_prep_rq(sdp->request_queue, sd_prep_fn);
+
+        gd->driverfs_dev = &sdp->sdev_gendev;
+        gd->flags = GENHD_FL_EXT_DEVT | GENHD_FL_DRIVERFS;
+        if (sdp->removable)
+                gd->flags |= GENHD_FL_REMOVABLE;
+
+        dev_set_drvdata(dev, sdkp);
+        add_disk(gd);
+        sd_dif_config_host(sdkp);
+
+        sd_printk(KERN_NOTICE, sdkp, "Attached SCSI %sdisk\n",
+                  sdp->removable ? "removable " : "");
+
+        return;
+
+ out_free_index:
+        ida_remove(&sd_index_ida, index);
+}
+
 /**
  *      sd_probe - called during driver initialization and whenever a
  *      new scsi device is attached to the system. It is called once
@@ -1865,48 +1931,7 @@ static int sd_probe(struct device *dev)
         sdkp->openers = 0;
         sdkp->previous_state = 1;
 
-        if (!sdp->request_queue->rq_timeout) {
-                if (sdp->type != TYPE_MOD)
-                        blk_queue_rq_timeout(sdp->request_queue, SD_TIMEOUT);
-                else
-                        blk_queue_rq_timeout(sdp->request_queue,
-                                             SD_MOD_TIMEOUT);
-        }
-
-        device_initialize(&sdkp->dev);
-        sdkp->dev.parent = &sdp->sdev_gendev;
-        sdkp->dev.class = &sd_disk_class;
-        strncpy(sdkp->dev.bus_id, sdp->sdev_gendev.bus_id, BUS_ID_SIZE);
-
-        if (device_add(&sdkp->dev))
-                goto out_free_index;
-
-        get_device(&sdp->sdev_gendev);
-
-        if (index < SD_MAX_DISKS) {
-                gd->major = sd_major((index & 0xf0) >> 4);
-                gd->first_minor = ((index & 0xf) << 4) | (index & 0xfff00);
-                gd->minors = SD_MINORS;
-        }
-        gd->fops = &sd_fops;
-        gd->private_data = &sdkp->driver;
-        gd->queue = sdkp->device->request_queue;
-
-        sd_revalidate_disk(gd);
-
-        blk_queue_prep_rq(sdp->request_queue, sd_prep_fn);
-
-        gd->driverfs_dev = &sdp->sdev_gendev;
-        gd->flags = GENHD_FL_EXT_DEVT | GENHD_FL_DRIVERFS;
-        if (sdp->removable)
-                gd->flags |= GENHD_FL_REMOVABLE;
-
-        dev_set_drvdata(dev, sdkp);
-        add_disk(gd);
-        sd_dif_config_host(sdkp);
-
-        sd_printk(KERN_NOTICE, sdkp, "Attached SCSI %sdisk\n",
-                  sdp->removable ? "removable " : "");
+        async_schedule(sd_probe_async, sdkp);
 
         return 0;
 
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index daa00567bc44..1889a63ebc22 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -3123,7 +3123,7 @@ static int __init serial8250_init(void)
         if (nr_uarts > UART_NR)
                 nr_uarts = UART_NR;
 
-        printk(KERN_INFO "Serial: 8250/16550 driver"
+        printk(KERN_INFO "Serial: 8250/16550 driver, "
                 "%d ports, IRQ sharing %sabled\n", nr_uarts,
                 share_irqs ? "en" : "dis");
 
diff --git a/drivers/serial/crisv10.c b/drivers/serial/crisv10.c
index 8b2c619a09f2..e642c22c80e2 100644
--- a/drivers/serial/crisv10.c
+++ b/drivers/serial/crisv10.c
@@ -1203,7 +1203,7 @@ static void e100_disable_txdma_channel(struct e100_serial *info)
         unsigned long flags;
 
         /* Disable output DMA channel for the serial port in question
-         * ( set to something other then serialX)
+         * ( set to something other than serialX)
          */
         local_irq_save(flags);
         DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
@@ -1266,7 +1266,7 @@ static void e100_disable_rxdma_channel(struct e100_serial *info)
         unsigned long flags;
 
         /* Disable input DMA channel for the serial port in question
-         * ( set to something other then serialX)
+         * ( set to something other than serialX)
          */
         local_irq_save(flags);
         if (info->line == 0) {
diff --git a/drivers/spi/spi_lm70llp.c b/drivers/spi/spi_lm70llp.c
index af6526767e2a..568c781ad91c 100644
--- a/drivers/spi/spi_lm70llp.c
+++ b/drivers/spi/spi_lm70llp.c
@@ -1,5 +1,5 @@
 /*
- * spi_lm70llp.c - driver for lm70llp eval board for the LM70 sensor
+ * spi_lm70llp.c - driver for LM70EVAL-LLP board for the LM70 sensor
  *
  * Copyright (C) 2006 Kaiwan N Billimoria <kaiwan@designergraphix.com>
  *
@@ -40,8 +40,12 @@
  * master controller driver.  The hwmon/lm70 driver is a "SPI protocol
  * driver", layered on top of this one and usable without the lm70llp.
  *
+ * Datasheet and Schematic:
  * The LM70 is a temperature sensor chip from National Semiconductor; its
  * datasheet is available at http://www.national.com/pf/LM/LM70.html
+ * The schematic for this particular board (the LM70EVAL-LLP) is
+ * available (on page 4) here:
+ *  http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
  *
  * Also see Documentation/spi/spi-lm70llp.  The SPI<->parport code here is
  * (heavily) based on spi-butterfly by David Brownell.
@@ -64,7 +68,7 @@
  *
  * Note that parport pin 13 actually gets inverted by the transistor
  * arrangement which lets either the parport or the LM70 drive the
- * SI/SO signal.
+ * SI/SO signal (see the schematic for details).
  */
 
 #define DRVNAME         "spi-lm70llp"
@@ -106,12 +110,16 @@ static inline struct spi_lm70llp *spidev_to_pp(struct spi_device *spi)
 static inline void deassertCS(struct spi_lm70llp *pp)
 {
         u8 data = parport_read_data(pp->port);
+
+        data &= ~0x80;          /* pull D7/SI-out low while de-asserted */
         parport_write_data(pp->port, data | nCS);
 }
 
 static inline void assertCS(struct spi_lm70llp *pp)
 {
         u8 data = parport_read_data(pp->port);
+
+        data |= 0x80;           /* pull D7/SI-out high so lm70 drives SO-in */
         parport_write_data(pp->port, data & ~nCS);
 }
 
@@ -184,22 +192,7 @@ static void lm70_chipselect(struct spi_device *spi, int value)
  */
 static u32 lm70_txrx(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits)
 {
-        static u32 sio=0;
-        static int first_time=1;
-
-        /* First time: perform SPI bitbang and return the LSB of
-         * the result of the SPI call.
-         */
-        if (first_time) {
-                sio = bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
-                first_time=0;
-                return (sio & 0x00ff);
-        }
-        /* Return the MSB of the result of the SPI call */
-        else {
-                first_time=1;
-                return (sio >> 8);
-        }
+        return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
 }
 
 static void spi_lm70llp_attach(struct parport *p)
@@ -293,10 +286,9 @@ static void spi_lm70llp_attach(struct parport *p)
                 status = -ENODEV;
                 goto out_bitbang_stop;
         }
-        pp->spidev_lm70->bits_per_word = 16;
+        pp->spidev_lm70->bits_per_word = 8;
 
         lm70llp = pp;
-
         return;
 
 out_bitbang_stop:
@@ -326,7 +318,6 @@ static void spi_lm70llp_detach(struct parport *p)
 
         /* power down */
         parport_write_data(pp->port, 0);
-        msleep(10);
 
         parport_release(pp->pd);
         parport_unregister_device(pp->pd);
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 289d81adfb9c..83babb0a1df7 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -150,4 +150,6 @@ source "drivers/usb/atm/Kconfig"
 
 source "drivers/usb/gadget/Kconfig"
 
+source "drivers/usb/otg/Kconfig"
+
 endif # USB_SUPPORT
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index d50a99f70aee..00b47ea24f86 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -1275,7 +1275,7 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message)
         struct acm *acm = usb_get_intfdata(intf);
         int cnt;
 
-        if (acm->dev->auto_pm) {
+        if (message.event & PM_EVENT_AUTO) {
                 int b;
 
                 spin_lock_irq(&acm->read_lock);
diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c
index 5a8ecc045e3f..3771d6e6d0cc 100644
--- a/drivers/usb/class/cdc-wdm.c
+++ b/drivers/usb/class/cdc-wdm.c
@@ -764,7 +764,8 @@ static int wdm_suspend(struct usb_interface *intf, pm_message_t message)
 
         mutex_lock(&desc->plock);
 #ifdef CONFIG_PM
-        if (interface_to_usbdev(desc->intf)->auto_pm && test_bit(WDM_IN_USE, &desc->flags)) {
+        if ((message.event & PM_EVENT_AUTO) &&
+                        test_bit(WDM_IN_USE, &desc->flags)) {
                 rv = -EBUSY;
         } else {
 #endif
diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c
index 43a863c5cc43..0f5c05f6f9df 100644
--- a/drivers/usb/class/usbtmc.c
+++ b/drivers/usb/class/usbtmc.c
@@ -21,6 +21,7 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/uaccess.h>
 #include <linux/kref.h>
@@ -482,7 +483,6 @@ static ssize_t usbtmc_write(struct file *filp, const char __user *buf,
         int retval;
         int actual;
         unsigned long int n_bytes;
-        int n;
         int remaining;
         int done;
         int this_part;
@@ -526,11 +526,8 @@ static ssize_t usbtmc_write(struct file *filp, const char __user *buf,
                         goto exit;
                 }
 
-                n_bytes = 12 + this_part;
-                if (this_part % 4)
-                        n_bytes += 4 - this_part % 4;
-                        for (n = 12 + this_part; n < n_bytes; n++)
-                                buffer[n] = 0;
+                n_bytes = roundup(12 + this_part, 4);
+                memset(buffer + 12 + this_part, 0, n_bytes - (12 + this_part));
 
                 retval = usb_bulk_msg(data->usb_dev,
                                       usb_sndbulkpipe(data->usb_dev,
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index aa79280df15d..26fece124e0e 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -981,9 +981,6 @@ static int proc_do_submiturb(struct dev_state *ps, struct usbdevfs_urb *uurb,
                 return -EINVAL;
         if (!uurb->buffer)
                 return -EINVAL;
-        if (uurb->signr != 0 && (uurb->signr < SIGRTMIN ||
-                                 uurb->signr > SIGRTMAX))
-                return -EINVAL;
         if (!(uurb->type == USBDEVFS_URB_TYPE_CONTROL &&
             (uurb->endpoint & ~USB_ENDPOINT_DIR_MASK) == 0)) {
                 ifnum = findintfep(ps->dev, uurb->endpoint);
@@ -1320,7 +1317,7 @@ static int get_urb32(struct usbdevfs_urb *kurb,
         if (__get_user(uptr, &uurb->buffer))
                 return -EFAULT;
         kurb->buffer = compat_ptr(uptr);
-        if (__get_user(uptr, &uurb->buffer))
+        if (__get_user(uptr, &uurb->usercontext))
                 return -EFAULT;
         kurb->usercontext = compat_ptr(uptr);
 
@@ -1401,8 +1398,6 @@ static int proc_disconnectsignal(struct dev_state *ps, void __user *arg)
 
         if (copy_from_user(&ds, arg, sizeof(ds)))
                 return -EFAULT;
-        if (ds.signr != 0 && (ds.signr < SIGRTMIN || ds.signr > SIGRTMAX))
-                return -EINVAL;
         ps->discsignr = ds.signr;
         ps->disccontext = ds.context;
         return 0;
diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
index 8c081308b0e2..98760553bc95 100644
--- a/drivers/usb/core/driver.c
+++ b/drivers/usb/core/driver.c
@@ -184,6 +184,20 @@ static int usb_unbind_device(struct device *dev)
         return 0;
 }
 
+/*
+ * Cancel any pending scheduled resets
+ *
+ * [see usb_queue_reset_device()]
+ *
+ * Called after unconfiguring / when releasing interfaces. See
+ * comments in __usb_queue_reset_device() regarding
+ * udev->reset_running.
+ */
+static void usb_cancel_queued_reset(struct usb_interface *iface)
+{
+        if (iface->reset_running == 0)
+                cancel_work_sync(&iface->reset_ws);
+}
 
 /* called from driver core with dev locked */
 static int usb_probe_interface(struct device *dev)
@@ -242,6 +256,7 @@ static int usb_probe_interface(struct device *dev)
                         mark_quiesced(intf);
                         intf->needs_remote_wakeup = 0;
                         intf->condition = USB_INTERFACE_UNBOUND;
+                        usb_cancel_queued_reset(intf);
                 } else
                         intf->condition = USB_INTERFACE_BOUND;
 
@@ -272,6 +287,7 @@ static int usb_unbind_interface(struct device *dev)
                 usb_disable_interface(udev, intf);
 
         driver->disconnect(intf);
+        usb_cancel_queued_reset(intf);
 
         /* Reset other interface state.
          * We cannot do a Set-Interface if the device is suspended or
@@ -279,9 +295,12 @@ static int usb_unbind_interface(struct device *dev)
          * altsetting means creating new endpoint device entries).
          * When either of these happens, defer the Set-Interface.
          */
-        if (intf->cur_altsetting->desc.bAlternateSetting == 0)
-                ;       /* Already in altsetting 0 so skip Set-Interface */
-        else if (!error && intf->dev.power.status == DPM_ON)
+        if (intf->cur_altsetting->desc.bAlternateSetting == 0) {
+                /* Already in altsetting 0 so skip Set-Interface.
+                 * Just re-enable it without affecting the endpoint toggles.
+                 */
+                usb_enable_interface(udev, intf, false);
+        } else if (!error && intf->dev.power.status == DPM_ON)
                 usb_set_interface(udev, intf->altsetting[0].
                                 desc.bInterfaceNumber, 0);
         else
@@ -380,8 +399,10 @@ void usb_driver_release_interface(struct usb_driver *driver,
         if (device_is_registered(dev)) {
                 iface->condition = USB_INTERFACE_UNBINDING;
                 device_release_driver(dev);
+        } else {
+                iface->condition = USB_INTERFACE_UNBOUND;
+                usb_cancel_queued_reset(iface);
         }
-
         dev->driver = NULL;
         usb_set_intfdata(iface, NULL);
 
@@ -904,7 +925,7 @@ static int usb_suspend_device(struct usb_device *udev, pm_message_t msg)
 }
 
 /* Caller has locked udev's pm_mutex */
-static int usb_resume_device(struct usb_device *udev)
+static int usb_resume_device(struct usb_device *udev, pm_message_t msg)
 {
         struct usb_device_driver        *udriver;
         int                             status = 0;
@@ -922,7 +943,7 @@ static int usb_resume_device(struct usb_device *udev)
                 udev->reset_resume = 1;
 
         udriver = to_usb_device_driver(udev->dev.driver);
-        status = udriver->resume(udev);
+        status = udriver->resume(udev, msg);
 
  done:
         dev_vdbg(&udev->dev, "%s: status %d\n", __func__, status);
@@ -942,7 +963,8 @@ static int usb_suspend_interface(struct usb_device *udev,
         if (udev->state == USB_STATE_NOTATTACHED || !is_active(intf))
                 goto done;
 
-        if (intf->condition == USB_INTERFACE_UNBOUND)   /* This can't happen */
+        /* This can happen; see usb_driver_release_interface() */
+        if (intf->condition == USB_INTERFACE_UNBOUND)
                 goto done;
         driver = to_usb_driver(intf->dev.driver);
 
@@ -950,7 +972,7 @@ static int usb_suspend_interface(struct usb_device *udev,
                 status = driver->suspend(intf, msg);
                 if (status == 0)
                         mark_quiesced(intf);
-                else if (!udev->auto_pm)
+                else if (!(msg.event & PM_EVENT_AUTO))
                         dev_err(&intf->dev, "%s error %d\n",
                                         "suspend", status);
         } else {
@@ -968,7 +990,7 @@ static int usb_suspend_interface(struct usb_device *udev,
 
 /* Caller has locked intf's usb_device's pm_mutex */
 static int usb_resume_interface(struct usb_device *udev,
-                struct usb_interface *intf, int reset_resume)
+                struct usb_interface *intf, pm_message_t msg, int reset_resume)
 {
         struct usb_driver       *driver;
         int                     status = 0;
@@ -1092,7 +1114,7 @@ static int autosuspend_check(struct usb_device *udev, int reschedule)
         if (reschedule) {
                 if (!timer_pending(&udev->autosuspend.timer)) {
                         queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
-                                round_jiffies_relative(suspend_time - j));
+                                round_jiffies_up_relative(suspend_time - j));
                 }
                 return -EAGAIN;
         }
@@ -1119,10 +1141,9 @@ static inline int autosuspend_check(struct usb_device *udev, int reschedule)
  * all the interfaces which were suspended are resumed so that they remain
  * in the same state as the device.
  *
- * If an autosuspend is in progress (@udev->auto_pm is set), the routine
- * checks first to make sure that neither the device itself or any of its
- * active interfaces is in use (pm_usage_cnt is greater than 0).  If they
- * are, the autosuspend fails.
+ * If an autosuspend is in progress the routine checks first to make sure
+ * that neither the device itself or any of its active interfaces is in use
+ * (pm_usage_cnt is greater than 0).  If they are, the autosuspend fails.
  *
  * If the suspend succeeds, the routine recursively queues an autosuspend
  * request for @udev's parent device, thereby propagating the change up
@@ -1157,7 +1178,7 @@ static int usb_suspend_both(struct usb_device *udev, pm_message_t msg)
 
         udev->do_remote_wakeup = device_may_wakeup(&udev->dev);
 
-        if (udev->auto_pm) {
+        if (msg.event & PM_EVENT_AUTO) {
                 status = autosuspend_check(udev, 0);
                 if (status < 0)
                         goto done;
@@ -1177,13 +1198,16 @@ static int usb_suspend_both(struct usb_device *udev, pm_message_t msg)
 
         /* If the suspend failed, resume interfaces that did get suspended */
         if (status != 0) {
+                pm_message_t msg2;
+
+                msg2.event = msg.event ^ (PM_EVENT_SUSPEND | PM_EVENT_RESUME);
                 while (--i >= 0) {
                         intf = udev->actconfig->interface[i];
-                        usb_resume_interface(udev, intf, 0);
+                        usb_resume_interface(udev, intf, msg2, 0);
                 }
 
                 /* Try another autosuspend when the interfaces aren't busy */
-                if (udev->auto_pm)
+                if (msg.event & PM_EVENT_AUTO)
                         autosuspend_check(udev, status == -EBUSY);
 
         /* If the suspend succeeded then prevent any more URB submissions,
@@ -1213,6 +1237,7 @@ static int usb_suspend_both(struct usb_device *udev, pm_message_t msg)
 /**
  * usb_resume_both - resume a USB device and its interfaces
  * @udev: the usb_device to resume
+ * @msg: Power Management message describing this state transition
  *
  * This is the central routine for resuming USB devices.  It calls the
  * the resume method for @udev and then calls the resume methods for all
@@ -1238,7 +1263,7 @@ static int usb_suspend_both(struct usb_device *udev, pm_message_t msg)
  *
  * This routine can run only in process context.
  */
-static int usb_resume_both(struct usb_device *udev)
+static int usb_resume_both(struct usb_device *udev, pm_message_t msg)
 {
         int                     status = 0;
         int                     i;
@@ -1254,14 +1279,15 @@ static int usb_resume_both(struct usb_device *udev)
 
         /* Propagate the resume up the tree, if necessary */
         if (udev->state == USB_STATE_SUSPENDED) {
-                if (udev->auto_pm && udev->autoresume_disabled) {
+                if ((msg.event & PM_EVENT_AUTO) &&
+                                udev->autoresume_disabled) {
                         status = -EPERM;
                         goto done;
                 }
                 if (parent) {
                         status = usb_autoresume_device(parent);
                         if (status == 0) {
-                                status = usb_resume_device(udev);
+                                status = usb_resume_device(udev, msg);
                                 if (status || udev->state ==
                                                 USB_STATE_NOTATTACHED) {
                                         usb_autosuspend_device(parent);
@@ -1284,15 +1310,16 @@ static int usb_resume_both(struct usb_device *udev)
                         /* We can't progagate beyond the USB subsystem,
                          * so if a root hub's controller is suspended
                          * then we're stuck. */
-                        status = usb_resume_device(udev);
+                        status = usb_resume_device(udev, msg);
                 }
         } else if (udev->reset_resume)
-                status = usb_resume_device(udev);
+                status = usb_resume_device(udev, msg);
 
         if (status == 0 && udev->actconfig) {
                 for (i = 0; i < udev->actconfig->desc.bNumInterfaces; i++) {
                         intf = udev->actconfig->interface[i];
-                        usb_resume_interface(udev, intf, udev->reset_resume);
+                        usb_resume_interface(udev, intf, msg,
+                                        udev->reset_resume);
                 }
         }
 
@@ -1320,13 +1347,13 @@ static int usb_autopm_do_device(struct usb_device *udev, int inc_usage_cnt)
                 udev->last_busy = jiffies;
         if (inc_usage_cnt >= 0 && udev->pm_usage_cnt > 0) {
                 if (udev->state == USB_STATE_SUSPENDED)
-                        status = usb_resume_both(udev);
+                        status = usb_resume_both(udev, PMSG_AUTO_RESUME);
                 if (status != 0)
                         udev->pm_usage_cnt -= inc_usage_cnt;
                 else if (inc_usage_cnt)
                         udev->last_busy = jiffies;
         } else if (inc_usage_cnt <= 0 && udev->pm_usage_cnt <= 0) {
-                status = usb_suspend_both(udev, PMSG_SUSPEND);
+                status = usb_suspend_both(udev, PMSG_AUTO_SUSPEND);
         }
         usb_pm_unlock(udev);
         return status;
@@ -1341,6 +1368,19 @@ void usb_autosuspend_work(struct work_struct *work)
         usb_autopm_do_device(udev, 0);
 }
 
+/* usb_autoresume_work - callback routine to autoresume a USB device */
+void usb_autoresume_work(struct work_struct *work)
+{
+        struct usb_device *udev =
+                container_of(work, struct usb_device, autoresume);
+
+        /* Wake it up, let the drivers do their thing, and then put it
+         * back to sleep.
+         */
+        if (usb_autopm_do_device(udev, 1) == 0)
+                usb_autopm_do_device(udev, -1);
+}
+
 /**
  * usb_autosuspend_device - delayed autosuspend of a USB device and its interfaces
  * @udev: the usb_device to autosuspend
@@ -1437,13 +1477,14 @@ static int usb_autopm_do_interface(struct usb_interface *intf,
                 udev->last_busy = jiffies;
                 if (inc_usage_cnt >= 0 && intf->pm_usage_cnt > 0) {
                         if (udev->state == USB_STATE_SUSPENDED)
-                                status = usb_resume_both(udev);
+                                status = usb_resume_both(udev,
+                                                PMSG_AUTO_RESUME);
                         if (status != 0)
                                 intf->pm_usage_cnt -= inc_usage_cnt;
                         else
                                 udev->last_busy = jiffies;
                 } else if (inc_usage_cnt <= 0 && intf->pm_usage_cnt <= 0) {
-                        status = usb_suspend_both(udev, PMSG_SUSPEND);
+                        status = usb_suspend_both(udev, PMSG_AUTO_SUSPEND);
                 }
         }
         usb_pm_unlock(udev);
@@ -1492,6 +1533,45 @@ void usb_autopm_put_interface(struct usb_interface *intf)
 EXPORT_SYMBOL_GPL(usb_autopm_put_interface);
 
 /**
+ * usb_autopm_put_interface_async - decrement a USB interface's PM-usage counter
+ * @intf: the usb_interface whose counter should be decremented
+ *
+ * This routine does essentially the same thing as
+ * usb_autopm_put_interface(): it decrements @intf's usage counter and
+ * queues a delayed autosuspend request if the counter is <= 0.  The
+ * difference is that it does not acquire the device's pm_mutex;
+ * callers must handle all synchronization issues themselves.
+ *
+ * Typically a driver would call this routine during an URB's completion
+ * handler, if no more URBs were pending.
+ *
+ * This routine can run in atomic context.
+ */
+void usb_autopm_put_interface_async(struct usb_interface *intf)
+{
+        struct usb_device       *udev = interface_to_usbdev(intf);
+        int                     status = 0;
+
+        if (intf->condition == USB_INTERFACE_UNBOUND) {
+                status = -ENODEV;
+        } else {
+                udev->last_busy = jiffies;
+                --intf->pm_usage_cnt;
+                if (udev->autosuspend_disabled || udev->autosuspend_delay < 0)
+                        status = -EPERM;
+                else if (intf->pm_usage_cnt <= 0 &&
+                                !timer_pending(&udev->autosuspend.timer)) {
+                        queue_delayed_work(ksuspend_usb_wq, &udev->autosuspend,
+                                        round_jiffies_up_relative(
+                                                udev->autosuspend_delay));
+                }
+        }
+        dev_vdbg(&intf->dev, "%s: status %d cnt %d\n",
+                        __func__, status, intf->pm_usage_cnt);
+}
+EXPORT_SYMBOL_GPL(usb_autopm_put_interface_async);
+
+/**
  * usb_autopm_get_interface - increment a USB interface's PM-usage counter
  * @intf: the usb_interface whose counter should be incremented
  *
@@ -1537,6 +1617,37 @@ int usb_autopm_get_interface(struct usb_interface *intf)
 EXPORT_SYMBOL_GPL(usb_autopm_get_interface);
 
 /**
+ * usb_autopm_get_interface_async - increment a USB interface's PM-usage counter
+ * @intf: the usb_interface whose counter should be incremented
+ *
+ * This routine does much the same thing as
+ * usb_autopm_get_interface(): it increments @intf's usage counter and
+ * queues an autoresume request if the result is > 0.  The differences
+ * are that it does not acquire the device's pm_mutex (callers must
+ * handle all synchronization issues themselves), and it does not
+ * autoresume the device directly (it only queues a request).  After a
+ * successful call, the device will generally not yet be resumed.
+ *
+ * This routine can run in atomic context.
+ */
+int usb_autopm_get_interface_async(struct usb_interface *intf)
+{
+        struct usb_device       *udev = interface_to_usbdev(intf);
+        int                     status = 0;
+
+        if (intf->condition == USB_INTERFACE_UNBOUND)
+                status = -ENODEV;
+        else if (udev->autoresume_disabled)
+                status = -EPERM;
+        else if (++intf->pm_usage_cnt > 0 && udev->state == USB_STATE_SUSPENDED)
+                queue_work(ksuspend_usb_wq, &udev->autoresume);
+        dev_vdbg(&intf->dev, "%s: status %d cnt %d\n",
+                        __func__, status, intf->pm_usage_cnt);
+        return status;
+}
+EXPORT_SYMBOL_GPL(usb_autopm_get_interface_async);
+
+/**
  * usb_autopm_set_interface - set a USB interface's autosuspend state
  * @intf: the usb_interface whose state should be set
  *
@@ -1563,6 +1674,9 @@ EXPORT_SYMBOL_GPL(usb_autopm_set_interface);
 void usb_autosuspend_work(struct work_struct *work)
 {}
 
+void usb_autoresume_work(struct work_struct *work)
+{}
+
 #endif /* CONFIG_USB_SUSPEND */
 
 /**
@@ -1595,6 +1709,7 @@ int usb_external_suspend_device(struct usb_device *udev, pm_message_t msg)
 /**
  * usb_external_resume_device - external resume of a USB device and its interfaces
  * @udev: the usb_device to resume
+ * @msg: Power Management message describing this state transition
  *
  * This routine handles external resume requests: ones not generated
  * internally by a USB driver (autoresume) but rather coming from the user
@@ -1603,13 +1718,13 @@ int usb_external_suspend_device(struct usb_device *udev, pm_message_t msg)
  *
  * The caller must hold @udev's device lock.
  */
-int usb_external_resume_device(struct usb_device *udev)
+int usb_external_resume_device(struct usb_device *udev, pm_message_t msg)
 {
         int     status;
 
         usb_pm_lock(udev);
         udev->auto_pm = 0;
-        status = usb_resume_both(udev);
+        status = usb_resume_both(udev, msg);
         udev->last_busy = jiffies;
         usb_pm_unlock(udev);
         if (status == 0)
@@ -1622,7 +1737,7 @@ int usb_external_resume_device(struct usb_device *udev)
         return status;
 }
 
-int usb_suspend(struct device *dev, pm_message_t message)
+int usb_suspend(struct device *dev, pm_message_t msg)
 {
         struct usb_device       *udev;
 
@@ -1641,10 +1756,10 @@ int usb_suspend(struct device *dev, pm_message_t message)
         }
 
         udev->skip_sys_resume = 0;
-        return usb_external_suspend_device(udev, message);
+        return usb_external_suspend_device(udev, msg);
 }
 
-int usb_resume(struct device *dev)
+int usb_resume(struct device *dev, pm_message_t msg)
 {
         struct usb_device       *udev;
 
@@ -1656,7 +1771,7 @@ int usb_resume(struct device *dev)
          */
         if (udev->skip_sys_resume)
                 return 0;
-        return usb_external_resume_device(udev);
+        return usb_external_resume_device(udev, msg);
 }
 
 #endif /* CONFIG_PM */
diff --git a/drivers/usb/core/endpoint.c b/drivers/usb/core/endpoint.c
index 946fae43d622..e1710f260b4f 100644
--- a/drivers/usb/core/endpoint.c
+++ b/drivers/usb/core/endpoint.c
@@ -276,7 +276,7 @@ static void ep_device_release(struct device *dev)
         kfree(ep_dev);
 }
 
-int usb_create_ep_files(struct device *parent,
+int usb_create_ep_devs(struct device *parent,
                         struct usb_host_endpoint *endpoint,
                         struct usb_device *udev)
 {
@@ -340,7 +340,7 @@ exit:
         return retval;
 }
 
-void usb_remove_ep_files(struct usb_host_endpoint *endpoint)
+void usb_remove_ep_devs(struct usb_host_endpoint *endpoint)
 {
         struct ep_device *ep_dev = endpoint->ep_dev;
 
diff --git a/drivers/usb/core/generic.c b/drivers/usb/core/generic.c
index 7e912f21fd36..30ecac3af15a 100644
--- a/drivers/usb/core/generic.c
+++ b/drivers/usb/core/generic.c
@@ -200,18 +200,18 @@ static int generic_suspend(struct usb_device *udev, pm_message_t msg)
          * interfaces manually by doing a bus (or "global") suspend.
          */
         if (!udev->parent)
-                rc = hcd_bus_suspend(udev);
+                rc = hcd_bus_suspend(udev, msg);
 
         /* Non-root devices don't need to do anything for FREEZE or PRETHAW */
         else if (msg.event == PM_EVENT_FREEZE || msg.event == PM_EVENT_PRETHAW)
                 rc = 0;
         else
-                rc = usb_port_suspend(udev);
+                rc = usb_port_suspend(udev, msg);
 
         return rc;
 }
 
-static int generic_resume(struct usb_device *udev)
+static int generic_resume(struct usb_device *udev, pm_message_t msg)
 {
         int rc;
 
@@ -221,9 +221,9 @@ static int generic_resume(struct usb_device *udev)
          * interfaces manually by doing a bus (or "global") resume.
          */
         if (!udev->parent)
-                rc = hcd_bus_resume(udev);
+                rc = hcd_bus_resume(udev, msg);
         else
-                rc = usb_port_resume(udev);
+                rc = usb_port_resume(udev, msg);
         return rc;
 }
 
diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
index 5b87ae7f0a6a..507741ed4482 100644
--- a/drivers/usb/core/hcd-pci.c
+++ b/drivers/usb/core/hcd-pci.c
@@ -128,6 +128,7 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
         }
 
         pci_set_master(dev);
+        device_set_wakeup_enable(&dev->dev, 1);
 
         retval = usb_add_hcd(hcd, dev->irq, IRQF_DISABLED | IRQF_SHARED);
         if (retval != 0)
@@ -191,17 +192,15 @@ EXPORT_SYMBOL_GPL(usb_hcd_pci_remove);
 /**
  * usb_hcd_pci_suspend - power management suspend of a PCI-based HCD
  * @dev: USB Host Controller being suspended
- * @message: semantics in flux
+ * @message: Power Management message describing this state transition
  *
- * Store this function in the HCD's struct pci_driver as suspend().
+ * Store this function in the HCD's struct pci_driver as .suspend.
  */
 int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t message)
 {
-        struct usb_hcd          *hcd;
+        struct usb_hcd          *hcd = pci_get_drvdata(dev);
         int                     retval = 0;
-        int                     has_pci_pm;
-
-        hcd = pci_get_drvdata(dev);
+        int                     wake, w;
 
         /* Root hub suspend should have stopped all downstream traffic,
          * and all bus master traffic.  And done so for both the interface
@@ -212,8 +211,15 @@ int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t message)
          * otherwise the swsusp will save (and restore) garbage state.
          */
         if (!(hcd->state == HC_STATE_SUSPENDED ||
-                        hcd->state == HC_STATE_HALT))
-                return -EBUSY;
+                        hcd->state == HC_STATE_HALT)) {
+                dev_warn(&dev->dev, "Root hub is not suspended\n");
+                retval = -EBUSY;
+                goto done;
+        }
+
+        /* We might already be suspended (runtime PM -- not yet written) */
+        if (dev->current_state != PCI_D0)
+                goto done;
 
         if (hcd->driver->pci_suspend) {
                 retval = hcd->driver->pci_suspend(hcd, message);
@@ -221,49 +227,60 @@ int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t message)
                 if (retval)
                         goto done;
         }
-        synchronize_irq(dev->irq);
 
-        /* FIXME until the generic PM interfaces change a lot more, this
-         * can't use PCI D1 and D2 states.  For example, the confusion
-         * between messages and states will need to vanish, and messages
-         * will need to provide a target system state again.
-         *
-         * It'll be important to learn characteristics of the target state,
-         * especially on embedded hardware where the HCD will often be in
-         * charge of an external VBUS power supply and one or more clocks.
-         * Some target system states will leave them active; others won't.
-         * (With PCI, that's often handled by platform BIOS code.)
-         */
+        synchronize_irq(dev->irq);
 
-        /* even when the PCI layer rejects some of the PCI calls
-         * below, HCs can try global suspend and reduce DMA traffic.
-         * PM-sensitive HCDs may already have done this.
+        /* Don't fail on error to enable wakeup.  We rely on pci code
+         * to reject requests the hardware can't implement, rather
+         * than coding the same thing.
          */
-        has_pci_pm = pci_find_capability(dev, PCI_CAP_ID_PM);
+        wake = (hcd->state == HC_STATE_SUSPENDED &&
+                        device_may_wakeup(&dev->dev));
+        w = pci_wake_from_d3(dev, wake);
+        if (w < 0)
+                wake = w;
+        dev_dbg(&dev->dev, "wakeup: %d\n", wake);
 
         /* Downstream ports from this root hub should already be quiesced, so
          * there will be no DMA activity.  Now we can shut down the upstream
          * link (except maybe for PME# resume signaling) and enter some PCI
          * low power state, if the hardware allows.
          */
-        if (hcd->state == HC_STATE_SUSPENDED) {
+        pci_disable_device(dev);
+ done:
+        return retval;
+}
+EXPORT_SYMBOL_GPL(usb_hcd_pci_suspend);
 
-                /* no DMA or IRQs except when HC is active */
-                if (dev->current_state == PCI_D0) {
-                        pci_save_state(dev);
-                        pci_disable_device(dev);
-                }
+/**
+ * usb_hcd_pci_suspend_late - suspend a PCI-based HCD after IRQs are disabled
+ * @dev: USB Host Controller being suspended
+ * @message: Power Management message describing this state transition
+ *
+ * Store this function in the HCD's struct pci_driver as .suspend_late.
+ */
+int usb_hcd_pci_suspend_late(struct pci_dev *dev, pm_message_t message)
+{
+        int                     retval = 0;
+        int                     has_pci_pm;
 
-                if (message.event == PM_EVENT_FREEZE ||
-                                message.event == PM_EVENT_PRETHAW) {
-                        dev_dbg(hcd->self.controller, "--> no state change\n");
-                        goto done;
-                }
+        /* We might already be suspended (runtime PM -- not yet written) */
+        if (dev->current_state != PCI_D0)
+                goto done;
 
-                if (!has_pci_pm) {
-                        dev_dbg(hcd->self.controller, "--> PCI D0/legacy\n");
-                        goto done;
-                }
+        pci_save_state(dev);
+
+        /* Don't change state if we don't need to */
+        if (message.event == PM_EVENT_FREEZE ||
+                        message.event == PM_EVENT_PRETHAW) {
+                dev_dbg(&dev->dev, "--> no state change\n");
+                goto done;
+        }
+
+        has_pci_pm = pci_find_capability(dev, PCI_CAP_ID_PM);
+        if (!has_pci_pm) {
+                dev_dbg(&dev->dev, "--> PCI D0 legacy\n");
+        } else {
 
                 /* NOTE:  dev->current_state becomes nonzero only here, and
                  * only for devices that support PCI PM.  Also, exiting
@@ -273,35 +290,16 @@ int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t message)
                 retval = pci_set_power_state(dev, PCI_D3hot);
                 suspend_report_result(pci_set_power_state, retval);
                 if (retval == 0) {
-                        int wake = device_can_wakeup(&hcd->self.root_hub->dev);
-
-                        wake = wake && device_may_wakeup(hcd->self.controller);
-
-                        dev_dbg(hcd->self.controller, "--> PCI D3%s\n",
-                                        wake ? "/wakeup" : "");
-
-                        /* Ignore these return values.  We rely on pci code to
-                         * reject requests the hardware can't implement, rather
-                         * than coding the same thing.
-                         */
-                        (void) pci_enable_wake(dev, PCI_D3hot, wake);
-                        (void) pci_enable_wake(dev, PCI_D3cold, wake);
+                        dev_dbg(&dev->dev, "--> PCI D3\n");
                 } else {
                         dev_dbg(&dev->dev, "PCI D3 suspend fail, %d\n",
                                         retval);
-                        (void) usb_hcd_pci_resume(dev);
+                        pci_restore_state(dev);
                 }
-
-        } else if (hcd->state != HC_STATE_HALT) {
-                dev_dbg(hcd->self.controller, "hcd state %d; not suspended\n",
-                        hcd->state);
-                WARN_ON(1);
-                retval = -EINVAL;
         }
 
-done:
-        if (retval == 0) {
 #ifdef CONFIG_PPC_PMAC
+        if (retval == 0) {
                 /* Disable ASIC clocks for USB */
                 if (machine_is(powermac)) {
                         struct device_node      *of_node;
@@ -311,30 +309,24 @@ done:
                                 pmac_call_feature(PMAC_FTR_USB_ENABLE,
                                                         of_node, 0, 0);
                 }
-#endif
         }
+#endif
 
+ done:
         return retval;
 }
-EXPORT_SYMBOL_GPL(usb_hcd_pci_suspend);
+EXPORT_SYMBOL_GPL(usb_hcd_pci_suspend_late);
 
 /**
- * usb_hcd_pci_resume - power management resume of a PCI-based HCD
+ * usb_hcd_pci_resume_early - resume a PCI-based HCD before IRQs are enabled
  * @dev: USB Host Controller being resumed
  *
- * Store this function in the HCD's struct pci_driver as resume().
+ * Store this function in the HCD's struct pci_driver as .resume_early.
  */
-int usb_hcd_pci_resume(struct pci_dev *dev)
+int usb_hcd_pci_resume_early(struct pci_dev *dev)
 {
-        struct usb_hcd          *hcd;
-        int                     retval;
-
-        hcd = pci_get_drvdata(dev);
-        if (hcd->state != HC_STATE_SUSPENDED) {
-                dev_dbg(hcd->self.controller,
-                                "can't resume, not suspended!\n");
-                return 0;
-        }
+        int             retval = 0;
+        pci_power_t     state = dev->current_state;
 
 #ifdef CONFIG_PPC_PMAC
         /* Reenable ASIC clocks for USB */
@@ -352,7 +344,7 @@ int usb_hcd_pci_resume(struct pci_dev *dev)
          * calls "standby", "suspend to RAM", and so on).  There are also
          * dirty cases when swsusp fakes a suspend in "shutdown" mode.
          */
-        if (dev->current_state != PCI_D0) {
+        if (state != PCI_D0) {
 #ifdef  DEBUG
                 int     pci_pm;
                 u16     pmcr;
@@ -364,8 +356,7 @@ int usb_hcd_pci_resume(struct pci_dev *dev)
                         /* Clean case:  power to USB and to HC registers was
                          * maintained; remote wakeup is easy.
                          */
-                        dev_dbg(hcd->self.controller, "resume from PCI D%d\n",
-                                        pmcr);
+                        dev_dbg(&dev->dev, "resume from PCI D%d\n", pmcr);
                 } else {
                         /* Clean:  HC lost Vcc power, D0 uninitialized
                          *   + Vaux may have preserved port and transceiver
@@ -376,32 +367,55 @@ int usb_hcd_pci_resume(struct pci_dev *dev)
                          *   + after BIOS init
                          *   + after Linux init (HCD statically linked)
                          */
-                        dev_dbg(hcd->self.controller,
-                                "PCI D0, from previous PCI D%d\n",
-                                dev->current_state);
+                        dev_dbg(&dev->dev, "resume from previous PCI D%d\n",
+                                        state);
                 }
 #endif
-                /* yes, ignore these results too... */
-                (void) pci_enable_wake(dev, dev->current_state, 0);
-                (void) pci_enable_wake(dev, PCI_D3cold, 0);
+
+                retval = pci_set_power_state(dev, PCI_D0);
         } else {
                 /* Same basic cases: clean (powered/not), dirty */
-                dev_dbg(hcd->self.controller, "PCI legacy resume\n");
+                dev_dbg(&dev->dev, "PCI legacy resume\n");
+        }
+
+        if (retval < 0)
+                dev_err(&dev->dev, "can't resume: %d\n", retval);
+        else
+                pci_restore_state(dev);
+
+        return retval;
+}
+EXPORT_SYMBOL_GPL(usb_hcd_pci_resume_early);
+
+/**
+ * usb_hcd_pci_resume - power management resume of a PCI-based HCD
+ * @dev: USB Host Controller being resumed
+ *
+ * Store this function in the HCD's struct pci_driver as .resume.
+ */
+int usb_hcd_pci_resume(struct pci_dev *dev)
+{
+        struct usb_hcd          *hcd;
+        int                     retval;
+
+        hcd = pci_get_drvdata(dev);
+        if (hcd->state != HC_STATE_SUSPENDED) {
+                dev_dbg(hcd->self.controller,
+                                "can't resume, not suspended!\n");
+                return 0;
         }
 
-        /* NOTE:  the PCI API itself is asymmetric here.  We don't need to
-         * pci_set_power_state(PCI_D0) since that's part of re-enabling;
-         * but that won't re-enable bus mastering.  Yet pci_disable_device()
-         * explicitly disables bus mastering...
-         */
         retval = pci_enable_device(dev);
         if (retval < 0) {
-                dev_err(hcd->self.controller,
-                        "can't re-enable after resume, %d!\n", retval);
+                dev_err(&dev->dev, "can't re-enable after resume, %d!\n",
+                                retval);
                 return retval;
         }
+
         pci_set_master(dev);
-        pci_restore_state(dev);
+
+        /* yes, ignore this result too... */
+        (void) pci_wake_from_d3(dev, 0);
 
         clear_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
 
@@ -413,7 +427,6 @@ int usb_hcd_pci_resume(struct pci_dev *dev)
                         usb_hc_died(hcd);
                 }
         }
-
         return retval;
 }
 EXPORT_SYMBOL_GPL(usb_hcd_pci_resume);
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index e1b42626d04d..3c711db55d86 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -1010,7 +1010,7 @@ int usb_hcd_link_urb_to_ep(struct usb_hcd *hcd, struct urb *urb)
         spin_lock(&hcd_urb_list_lock);
 
         /* Check that the URB isn't being killed */
-        if (unlikely(urb->reject)) {
+        if (unlikely(atomic_read(&urb->reject))) {
                 rc = -EPERM;
                 goto done;
         }
@@ -1340,7 +1340,7 @@ int usb_hcd_submit_urb (struct urb *urb, gfp_t mem_flags)
                 INIT_LIST_HEAD(&urb->urb_list);
                 atomic_dec(&urb->use_count);
                 atomic_dec(&urb->dev->urbnum);
-                if (urb->reject)
+                if (atomic_read(&urb->reject))
                         wake_up(&usb_kill_urb_queue);
                 usb_put_urb(urb);
         }
@@ -1444,7 +1444,7 @@ void usb_hcd_giveback_urb(struct usb_hcd *hcd, struct urb *urb, int status)
         urb->status = status;
         urb->complete (urb);
         atomic_dec (&urb->use_count);
-        if (unlikely (urb->reject))
+        if (unlikely(atomic_read(&urb->reject)))
                 wake_up (&usb_kill_urb_queue);
         usb_put_urb (urb);
 }
@@ -1573,14 +1573,14 @@ int usb_hcd_get_frame_number (struct usb_device *udev)
 
 #ifdef  CONFIG_PM
 
-int hcd_bus_suspend(struct usb_device *rhdev)
+int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg)
 {
         struct usb_hcd  *hcd = container_of(rhdev->bus, struct usb_hcd, self);
         int             status;
         int             old_state = hcd->state;
 
         dev_dbg(&rhdev->dev, "bus %s%s\n",
-                        rhdev->auto_pm ? "auto-" : "", "suspend");
+                        (msg.event & PM_EVENT_AUTO ? "auto-" : ""), "suspend");
         if (!hcd->driver->bus_suspend) {
                 status = -ENOENT;
         } else {
@@ -1598,14 +1598,14 @@ int hcd_bus_suspend(struct usb_device *rhdev)
         return status;
 }
 
-int hcd_bus_resume(struct usb_device *rhdev)
+int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg)
 {
         struct usb_hcd  *hcd = container_of(rhdev->bus, struct usb_hcd, self);
         int             status;
         int             old_state = hcd->state;
 
         dev_dbg(&rhdev->dev, "usb %s%s\n",
-                        rhdev->auto_pm ? "auto-" : "", "resume");
+                        (msg.event & PM_EVENT_AUTO ? "auto-" : ""), "resume");
         if (!hcd->driver->bus_resume)
                 return -ENOENT;
         if (hcd->state == HC_STATE_RUNNING)
@@ -1638,7 +1638,7 @@ static void hcd_resume_work(struct work_struct *work)
 
         usb_lock_device(udev);
         usb_mark_last_busy(udev);
-        usb_external_resume_device(udev);
+        usb_external_resume_device(udev, PMSG_REMOTE_RESUME);
         usb_unlock_device(udev);
 }
 
@@ -2028,7 +2028,7 @@ EXPORT_SYMBOL_GPL(usb_hcd_platform_shutdown);
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_USB_MON)
+#if defined(CONFIG_USB_MON) || defined(CONFIG_USB_MON_MODULE)
 
 struct usb_mon_operations *mon_ops;
 
@@ -2064,4 +2064,4 @@ void usb_mon_deregister (void)
 }
 EXPORT_SYMBOL_GPL (usb_mon_deregister);
 
-#endif /* CONFIG_USB_MON */
+#endif /* CONFIG_USB_MON || CONFIG_USB_MON_MODULE */
diff --git a/drivers/usb/core/hcd.h b/drivers/usb/core/hcd.h
index 9465e70f4dd0..572d2cf46e8d 100644
--- a/drivers/usb/core/hcd.h
+++ b/drivers/usb/core/hcd.h
@@ -16,6 +16,8 @@
  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#ifndef __USB_CORE_HCD_H
+#define __USB_CORE_HCD_H
 
 #ifdef __KERNEL__
 
@@ -254,7 +256,9 @@ extern int usb_hcd_pci_probe(struct pci_dev *dev,
 extern void usb_hcd_pci_remove(struct pci_dev *dev);
 
 #ifdef CONFIG_PM
-extern int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t state);
+extern int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t msg);
+extern int usb_hcd_pci_suspend_late(struct pci_dev *dev, pm_message_t msg);
+extern int usb_hcd_pci_resume_early(struct pci_dev *dev);
 extern int usb_hcd_pci_resume(struct pci_dev *dev);
 #endif /* CONFIG_PM */
 
@@ -386,8 +390,8 @@ extern int usb_find_interface_driver(struct usb_device *dev,
 #ifdef CONFIG_PM
 extern void usb_hcd_resume_root_hub(struct usb_hcd *hcd);
 extern void usb_root_hub_lost_power(struct usb_device *rhdev);
-extern int hcd_bus_suspend(struct usb_device *rhdev);
-extern int hcd_bus_resume(struct usb_device *rhdev);
+extern int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg);
+extern int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg);
 #else
 static inline void usb_hcd_resume_root_hub(struct usb_hcd *hcd)
 {
@@ -419,7 +423,7 @@ static inline void usbfs_cleanup(void) { }
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_USB_MON)
+#if defined(CONFIG_USB_MON) || defined(CONFIG_USB_MON_MODULE)
 
 struct usb_mon_operations {
         void (*urb_submit)(struct usb_bus *bus, struct urb *urb);
@@ -461,7 +465,7 @@ static inline void usbmon_urb_submit_error(struct usb_bus *bus, struct urb *urb,
 static inline void usbmon_urb_complete(struct usb_bus *bus, struct urb *urb,
                 int status) {}
 
-#endif /* CONFIG_USB_MON */
+#endif /* CONFIG_USB_MON || CONFIG_USB_MON_MODULE */
 
 /*-------------------------------------------------------------------------*/
 
@@ -490,3 +494,5 @@ extern struct rw_semaphore ehci_cf_port_reset_rwsem;
 extern unsigned long usb_hcds_loaded;
 
 #endif /* __KERNEL__ */
+
+#endif /* __USB_CORE_HCD_H */
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index b19cbfcd51da..d5d0e40b1e2d 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -107,7 +107,9 @@ MODULE_PARM_DESC (blinkenlights, "true to cycle leds on hubs");
 /* define initial 64-byte descriptor request timeout in milliseconds */
 static int initial_descriptor_timeout = USB_CTRL_GET_TIMEOUT;
 module_param(initial_descriptor_timeout, int, S_IRUGO|S_IWUSR);
-MODULE_PARM_DESC(initial_descriptor_timeout, "initial 64-byte descriptor request timeout in milliseconds (default 5000 - 5.0 seconds)");
+MODULE_PARM_DESC(initial_descriptor_timeout,
+                "initial 64-byte descriptor request timeout in milliseconds "
+                "(default 5000 - 5.0 seconds)");
 
 /*
  * As of 2.6.10 we introduce a new USB device initialization scheme which
@@ -1136,8 +1138,8 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
         hdev = interface_to_usbdev(intf);
 
         if (hdev->level == MAX_TOPO_LEVEL) {
-                dev_err(&intf->dev, "Unsupported bus topology: "
-                                "hub nested too deep\n");
+                dev_err(&intf->dev,
+                        "Unsupported bus topology: hub nested too deep\n");
                 return -E2BIG;
         }
 
@@ -1374,8 +1376,9 @@ static void usb_stop_pm(struct usb_device *udev)
                 usb_autosuspend_device(udev->parent);
         usb_pm_unlock(udev);
 
-        /* Stop any autosuspend requests already submitted */
-        cancel_rearming_delayed_work(&udev->autosuspend);
+        /* Stop any autosuspend or autoresume requests already submitted */
+        cancel_delayed_work_sync(&udev->autosuspend);
+        cancel_work_sync(&udev->autoresume);
 }
 
 #else
@@ -1434,17 +1437,12 @@ void usb_disconnect(struct usb_device **pdev)
         usb_disable_device(udev, 0);
         usb_hcd_synchronize_unlinks(udev);
 
+        usb_remove_ep_devs(&udev->ep0);
         usb_unlock_device(udev);
 
-        /* Remove the device-specific files from sysfs.  This must be
-         * done with udev unlocked, because some of the attribute
-         * routines try to acquire the device lock.
-         */
-        usb_remove_sysfs_dev_files(udev);
-
         /* Unregister the device.  The device driver is responsible
-         * for removing the device files from usbfs and sysfs and for
-         * de-configuring the device.
+         * for de-configuring the device and invoking the remove-device
+         * notifier chain (used by usbfs and possibly others).
          */
         device_del(&udev->dev);
 
@@ -1476,8 +1474,8 @@ static void announce_device(struct usb_device *udev)
         dev_info(&udev->dev, "New USB device found, idVendor=%04x, idProduct=%04x\n",
                 le16_to_cpu(udev->descriptor.idVendor),
                 le16_to_cpu(udev->descriptor.idProduct));
-        dev_info(&udev->dev, "New USB device strings: Mfr=%d, Product=%d, "
-                "SerialNumber=%d\n",
+        dev_info(&udev->dev,
+                "New USB device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
                 udev->descriptor.iManufacturer,
                 udev->descriptor.iProduct,
                 udev->descriptor.iSerialNumber);
@@ -1542,7 +1540,7 @@ static int usb_configure_device_otg(struct usb_device *udev)
                                          * customize to match your product.
                                          */
                                         dev_info(&udev->dev,
-                                                "can't set HNP mode; %d\n",
+                                                "can't set HNP mode: %d\n",
                                                 err);
                                         bus->b_hnp_enable = 0;
                                 }
@@ -1635,6 +1633,10 @@ int usb_new_device(struct usb_device *udev)
 {
         int err;
 
+        /* Increment the parent's count of unsuspended children */
+        if (udev->parent)
+                usb_autoresume_device(udev->parent);
+
         usb_detect_quirks(udev);                /* Determine quirks */
         err = usb_configure_device(udev);       /* detect & probe dev/intfs */
         if (err < 0)
@@ -1643,13 +1645,12 @@ int usb_new_device(struct usb_device *udev)
         udev->dev.devt = MKDEV(USB_DEVICE_MAJOR,
                         (((udev->bus->busnum-1) * 128) + (udev->devnum-1)));
 
-        /* Increment the parent's count of unsuspended children */
-        if (udev->parent)
-                usb_autoresume_device(udev->parent);
+        /* Tell the world! */
+        announce_device(udev);
 
         /* Register the device.  The device driver is responsible
-         * for adding the device files to sysfs and for configuring
-         * the device.
+         * for configuring the device and invoking the add-device
+         * notifier chain (used by usbfs and possibly others).
          */
         err = device_add(&udev->dev);
         if (err) {
@@ -1657,15 +1658,12 @@ int usb_new_device(struct usb_device *udev)
                 goto fail;
         }
 
-        /* put device-specific files into sysfs */
-        usb_create_sysfs_dev_files(udev);
-
-        /* Tell the world! */
-        announce_device(udev);
+        (void) usb_create_ep_devs(&udev->dev, &udev->ep0, udev);
         return err;
 
 fail:
         usb_set_device_state(udev, USB_STATE_NOTATTACHED);
+        usb_stop_pm(udev);
         return err;
 }
 
@@ -1982,7 +1980,7 @@ static int check_port_resume_type(struct usb_device *udev,
  *
  * Returns 0 on success, else negative errno.
  */
-int usb_port_suspend(struct usb_device *udev)
+int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
 {
         struct usb_hub  *hub = hdev_to_hub(udev->parent);
         int             port1 = udev->portnum;
@@ -2021,7 +2019,7 @@ int usb_port_suspend(struct usb_device *udev)
         } else {
                 /* device has up to 10 msec to fully suspend */
                 dev_dbg(&udev->dev, "usb %ssuspend\n",
-                                udev->auto_pm ? "auto-" : "");
+                                (msg.event & PM_EVENT_AUTO ? "auto-" : ""));
                 usb_set_device_state(udev, USB_STATE_SUSPENDED);
                 msleep(10);
         }
@@ -2045,8 +2043,8 @@ static int finish_port_resume(struct usb_device *udev)
         u16     devstatus;
 
         /* caller owns the udev device lock */
-        dev_dbg(&udev->dev, "finish %sresume\n",
-                        udev->reset_resume ? "reset-" : "");
+        dev_dbg(&udev->dev, "%s\n",
+                udev->reset_resume ? "finish reset-resume" : "finish resume");
 
         /* usb ch9 identifies four variants of SUSPENDED, based on what
          * state the device resumes to.  Linux currently won't see the
@@ -2098,8 +2096,9 @@ static int finish_port_resume(struct usb_device *udev)
                                         NULL, 0,
                                         USB_CTRL_SET_TIMEOUT);
                         if (status)
-                                dev_dbg(&udev->dev, "disable remote "
-                                        "wakeup, status %d\n", status);
+                                dev_dbg(&udev->dev,
+                                        "disable remote wakeup, status %d\n",
+                                        status);
                 }
                 status = 0;
         }
@@ -2140,7 +2139,7 @@ static int finish_port_resume(struct usb_device *udev)
  *
  * Returns 0 on success, else negative errno.
  */
-int usb_port_resume(struct usb_device *udev)
+int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 {
         struct usb_hub  *hub = hdev_to_hub(udev->parent);
         int             port1 = udev->portnum;
@@ -2165,7 +2164,7 @@ int usb_port_resume(struct usb_device *udev)
         } else {
                 /* drive resume for at least 20 msec */
                 dev_dbg(&udev->dev, "usb %sresume\n",
-                                udev->auto_pm ? "auto-" : "");
+                                (msg.event & PM_EVENT_AUTO ? "auto-" : ""));
                 msleep(25);
 
                 /* Virtual root hubs can trigger on GET_PORT_STATUS to
@@ -2206,7 +2205,7 @@ static int remote_wakeup(struct usb_device *udev)
         if (udev->state == USB_STATE_SUSPENDED) {
                 dev_dbg(&udev->dev, "usb %sresume\n", "wakeup-");
                 usb_mark_last_busy(udev);
-                status = usb_external_resume_device(udev);
+                status = usb_external_resume_device(udev, PMSG_REMOTE_RESUME);
         }
         return status;
 }
@@ -2215,14 +2214,14 @@ static int remote_wakeup(struct usb_device *udev)
 
 /* When CONFIG_USB_SUSPEND isn't set, we never suspend or resume any ports. */
 
-int usb_port_suspend(struct usb_device *udev)
+int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
 {
         return 0;
 }
 
 /* However we may need to do a reset-resume */
 
-int usb_port_resume(struct usb_device *udev)
+int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 {
         struct usb_hub  *hub = hdev_to_hub(udev->parent);
         int             port1 = udev->portnum;
@@ -2262,7 +2261,7 @@ static int hub_suspend(struct usb_interface *intf, pm_message_t msg)
 
                 udev = hdev->children [port1-1];
                 if (udev && udev->can_submit) {
-                        if (!hdev->auto_pm)
+                        if (!(msg.event & PM_EVENT_AUTO))
                                 dev_dbg(&intf->dev, "port %d nyet suspended\n",
                                                 port1);
                         return -EBUSY;
@@ -2385,7 +2384,7 @@ void usb_ep0_reinit(struct usb_device *udev)
 {
         usb_disable_endpoint(udev, 0 + USB_DIR_IN);
         usb_disable_endpoint(udev, 0 + USB_DIR_OUT);
-        usb_enable_endpoint(udev, &udev->ep0);
+        usb_enable_endpoint(udev, &udev->ep0, true);
 }
 EXPORT_SYMBOL_GPL(usb_ep0_reinit);
 
@@ -2582,9 +2581,9 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
                                 goto fail;
                         }
                         if (r) {
-                                dev_err(&udev->dev, "device descriptor "
-                                                "read/%s, error %d\n",
-                                                "64", r);
+                                dev_err(&udev->dev,
+                                        "device descriptor read/64, error %d\n",
+                                        r);
                                 retval = -EMSGSIZE;
                                 continue;
                         }
@@ -2621,9 +2620,9 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
 
                 retval = usb_get_device_descriptor(udev, 8);
                 if (retval < 8) {
-                        dev_err(&udev->dev, "device descriptor "
-                                        "read/%s, error %d\n",
-                                        "8", retval);
+                        dev_err(&udev->dev,
+                                        "device descriptor read/8, error %d\n",
+                                        retval);
                         if (retval >= 0)
                                 retval = -EMSGSIZE;
                 } else {
@@ -2650,8 +2649,8 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
   
         retval = usb_get_device_descriptor(udev, USB_DT_DEVICE_SIZE);
         if (retval < (signed)sizeof(udev->descriptor)) {
-                dev_err(&udev->dev, "device descriptor read/%s, error %d\n",
-                        "all", retval);
+                dev_err(&udev->dev, "device descriptor read/all, error %d\n",
+                        retval);
                 if (retval >= 0)
                         retval = -ENOMSG;
                 goto fail;
@@ -2719,9 +2718,9 @@ hub_power_remaining (struct usb_hub *hub)
                 else
                         delta = 8;
                 if (delta > hub->mA_per_port)
-                        dev_warn(&udev->dev, "%dmA is over %umA budget "
-                                        "for port %d!\n",
-                                        delta, hub->mA_per_port, port1);
+                        dev_warn(&udev->dev,
+                                 "%dmA is over %umA budget for port %d!\n",
+                                 delta, hub->mA_per_port, port1);
                 remaining -= delta;
         }
         if (remaining < 0) {
@@ -3517,3 +3516,46 @@ int usb_reset_device(struct usb_device *udev)
         return ret;
 }
 EXPORT_SYMBOL_GPL(usb_reset_device);
+
+
+/**
+ * usb_queue_reset_device - Reset a USB device from an atomic context
+ * @iface: USB interface belonging to the device to reset
+ *
+ * This function can be used to reset a USB device from an atomic
+ * context, where usb_reset_device() won't work (as it blocks).
+ *
+ * Doing a reset via this method is functionally equivalent to calling
+ * usb_reset_device(), except for the fact that it is delayed to a
+ * workqueue. This means that any drivers bound to other interfaces
+ * might be unbound, as well as users from usbfs in user space.
+ *
+ * Corner cases:
+ *
+ * - Scheduling two resets at the same time from two different drivers
+ *   attached to two different interfaces of the same device is
+ *   possible; depending on how the driver attached to each interface
+ *   handles ->pre_reset(), the second reset might happen or not.
+ *
+ * - If a driver is unbound and it had a pending reset, the reset will
+ *   be cancelled.
+ *
+ * - This function can be called during .probe() or .disconnect()
+ *   times. On return from .disconnect(), any pending resets will be
+ *   cancelled.
+ *
+ * There is no no need to lock/unlock the @reset_ws as schedule_work()
+ * does its own.
+ *
+ * NOTE: We don't do any reference count tracking because it is not
+ *     needed. The lifecycle of the work_struct is tied to the
+ *     usb_interface. Before destroying the interface we cancel the
+ *     work_struct, so the fact that work_struct is queued and or
+ *     running means the interface (and thus, the device) exist and
+ *     are referenced.
+ */
+void usb_queue_reset_device(struct usb_interface *iface)
+{
+        schedule_work(&iface->reset_ws);
+}
+EXPORT_SYMBOL_GPL(usb_queue_reset_device);
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 6d1048faf08e..de51667dd64d 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -18,6 +18,8 @@
 #include "hcd.h"        /* for usbcore internals */
 #include "usb.h"
 
+static void cancel_async_set_config(struct usb_device *udev);
+
 struct api_context {
         struct completion       done;
         int                     status;
@@ -139,9 +141,9 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, __u8 request,
 
         dr->bRequestType = requesttype;
         dr->bRequest = request;
-        dr->wValue = cpu_to_le16p(&value);
-        dr->wIndex = cpu_to_le16p(&index);
-        dr->wLength = cpu_to_le16p(&size);
+        dr->wValue = cpu_to_le16(value);
+        dr->wIndex = cpu_to_le16(index);
+        dr->wLength = cpu_to_le16(size);
 
         /* dbg("usb_control_msg"); */
 
@@ -1004,6 +1006,34 @@ int usb_clear_halt(struct usb_device *dev, int pipe)
 }
 EXPORT_SYMBOL_GPL(usb_clear_halt);
 
+static int create_intf_ep_devs(struct usb_interface *intf)
+{
+        struct usb_device *udev = interface_to_usbdev(intf);
+        struct usb_host_interface *alt = intf->cur_altsetting;
+        int i;
+
+        if (intf->ep_devs_created || intf->unregistering)
+                return 0;
+
+        for (i = 0; i < alt->desc.bNumEndpoints; ++i)
+                (void) usb_create_ep_devs(&intf->dev, &alt->endpoint[i], udev);
+        intf->ep_devs_created = 1;
+        return 0;
+}
+
+static void remove_intf_ep_devs(struct usb_interface *intf)
+{
+        struct usb_host_interface *alt = intf->cur_altsetting;
+        int i;
+
+        if (!intf->ep_devs_created)
+                return;
+
+        for (i = 0; i < alt->desc.bNumEndpoints; ++i)
+                usb_remove_ep_devs(&alt->endpoint[i]);
+        intf->ep_devs_created = 0;
+}
+
 /**
  * usb_disable_endpoint -- Disable an endpoint by address
  * @dev: the device whose endpoint is being disabled
@@ -1092,7 +1122,7 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0)
                         dev_dbg(&dev->dev, "unregistering interface %s\n",
                                 dev_name(&interface->dev));
                         interface->unregistering = 1;
-                        usb_remove_sysfs_intf_files(interface);
+                        remove_intf_ep_devs(interface);
                         device_del(&interface->dev);
                 }
 
@@ -1113,22 +1143,26 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0)
  * usb_enable_endpoint - Enable an endpoint for USB communications
  * @dev: the device whose interface is being enabled
  * @ep: the endpoint
+ * @reset_toggle: flag to set the endpoint's toggle back to 0
  *
- * Resets the endpoint toggle, and sets dev->ep_{in,out} pointers.
+ * Resets the endpoint toggle if asked, and sets dev->ep_{in,out} pointers.
  * For control endpoints, both the input and output sides are handled.
  */
-void usb_enable_endpoint(struct usb_device *dev, struct usb_host_endpoint *ep)
+void usb_enable_endpoint(struct usb_device *dev, struct usb_host_endpoint *ep,
+                bool reset_toggle)
 {
         int epnum = usb_endpoint_num(&ep->desc);
         int is_out = usb_endpoint_dir_out(&ep->desc);
         int is_control = usb_endpoint_xfer_control(&ep->desc);
 
         if (is_out || is_control) {
-                usb_settoggle(dev, epnum, 1, 0);
+                if (reset_toggle)
+                        usb_settoggle(dev, epnum, 1, 0);
                 dev->ep_out[epnum] = ep;
         }
         if (!is_out || is_control) {
-                usb_settoggle(dev, epnum, 0, 0);
+                if (reset_toggle)
+                        usb_settoggle(dev, epnum, 0, 0);
                 dev->ep_in[epnum] = ep;
         }
         ep->enabled = 1;
@@ -1138,17 +1172,18 @@ void usb_enable_endpoint(struct usb_device *dev, struct usb_host_endpoint *ep)
  * usb_enable_interface - Enable all the endpoints for an interface
  * @dev: the device whose interface is being enabled
  * @intf: pointer to the interface descriptor
+ * @reset_toggles: flag to set the endpoints' toggles back to 0
  *
  * Enables all the endpoints for the interface's current altsetting.
  */
-static void usb_enable_interface(struct usb_device *dev,
-                                 struct usb_interface *intf)
+void usb_enable_interface(struct usb_device *dev,
+                struct usb_interface *intf, bool reset_toggles)
 {
         struct usb_host_interface *alt = intf->cur_altsetting;
         int i;
 
         for (i = 0; i < alt->desc.bNumEndpoints; ++i)
-                usb_enable_endpoint(dev, &alt->endpoint[i]);
+                usb_enable_endpoint(dev, &alt->endpoint[i], reset_toggles);
 }
 
 /**
@@ -1235,8 +1270,10 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate)
          */
 
         /* prevent submissions using previous endpoint settings */
-        if (iface->cur_altsetting != alt)
+        if (iface->cur_altsetting != alt) {
+                remove_intf_ep_devs(iface);
                 usb_remove_sysfs_intf_files(iface);
+        }
         usb_disable_interface(dev, iface);
 
         iface->cur_altsetting = alt;
@@ -1271,10 +1308,11 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate)
          * during the SETUP stage - hence EP0 toggles are "don't care" here.
          * (Likewise, EP0 never "halts" on well designed devices.)
          */
-        usb_enable_interface(dev, iface);
-        if (device_is_registered(&iface->dev))
+        usb_enable_interface(dev, iface, true);
+        if (device_is_registered(&iface->dev)) {
                 usb_create_sysfs_intf_files(iface);
-
+                create_intf_ep_devs(iface);
+        }
         return 0;
 }
 EXPORT_SYMBOL_GPL(usb_set_interface);
@@ -1334,7 +1372,6 @@ int usb_reset_configuration(struct usb_device *dev)
                 struct usb_interface *intf = config->interface[i];
                 struct usb_host_interface *alt;
 
-                usb_remove_sysfs_intf_files(intf);
                 alt = usb_altnum_to_altsetting(intf, 0);
 
                 /* No altsetting 0?  We'll assume the first altsetting.
@@ -1345,10 +1382,16 @@ int usb_reset_configuration(struct usb_device *dev)
                 if (!alt)
                         alt = &intf->altsetting[0];
 
+                if (alt != intf->cur_altsetting) {
+                        remove_intf_ep_devs(intf);
+                        usb_remove_sysfs_intf_files(intf);
+                }
                 intf->cur_altsetting = alt;
-                usb_enable_interface(dev, intf);
-                if (device_is_registered(&intf->dev))
+                usb_enable_interface(dev, intf, true);
+                if (device_is_registered(&intf->dev)) {
                         usb_create_sysfs_intf_files(intf);
+                        create_intf_ep_devs(intf);
+                }
         }
         return 0;
 }
@@ -1441,6 +1484,46 @@ static struct usb_interface_assoc_descriptor *find_iad(struct usb_device *dev,
         return retval;
 }
 
+
+/*
+ * Internal function to queue a device reset
+ *
+ * This is initialized into the workstruct in 'struct
+ * usb_device->reset_ws' that is launched by
+ * message.c:usb_set_configuration() when initializing each 'struct
+ * usb_interface'.
+ *
+ * It is safe to get the USB device without reference counts because
+ * the life cycle of @iface is bound to the life cycle of @udev. Then,
+ * this function will be ran only if @iface is alive (and before
+ * freeing it any scheduled instances of it will have been cancelled).
+ *
+ * We need to set a flag (usb_dev->reset_running) because when we call
+ * the reset, the interfaces might be unbound. The current interface
+ * cannot try to remove the queued work as it would cause a deadlock
+ * (you cannot remove your work from within your executing
+ * workqueue). This flag lets it know, so that
+ * usb_cancel_queued_reset() doesn't try to do it.
+ *
+ * See usb_queue_reset_device() for more details
+ */
+void __usb_queue_reset_device(struct work_struct *ws)
+{
+        int rc;
+        struct usb_interface *iface =
+                container_of(ws, struct usb_interface, reset_ws);
+        struct usb_device *udev = interface_to_usbdev(iface);
+
+        rc = usb_lock_device_for_reset(udev, iface);
+        if (rc >= 0) {
+                iface->reset_running = 1;
+                usb_reset_device(udev);
+                iface->reset_running = 0;
+                usb_unlock_device(udev);
+        }
+}
+
+
 /*
  * usb_set_configuration - Makes a particular device setting be current
  * @dev: the device whose configuration is being updated
@@ -1560,6 +1643,9 @@ free_interfaces:
         if (dev->state != USB_STATE_ADDRESS)
                 usb_disable_device(dev, 1);     /* Skip ep0 */
 
+        /* Get rid of pending async Set-Config requests for this device */
+        cancel_async_set_config(dev);
+
         ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
                               USB_REQ_SET_CONFIGURATION, 0, configuration, 0,
                               NULL, 0, USB_CTRL_SET_TIMEOUT);
@@ -1604,13 +1690,14 @@ free_interfaces:
                         alt = &intf->altsetting[0];
 
                 intf->cur_altsetting = alt;
-                usb_enable_interface(dev, intf);
+                usb_enable_interface(dev, intf, true);
                 intf->dev.parent = &dev->dev;
                 intf->dev.driver = NULL;
                 intf->dev.bus = &usb_bus_type;
                 intf->dev.type = &usb_if_device_type;
                 intf->dev.groups = usb_interface_groups;
                 intf->dev.dma_mask = dev->dev.dma_mask;
+                INIT_WORK(&intf->reset_ws, __usb_queue_reset_device);
                 device_initialize(&intf->dev);
                 mark_quiesced(intf);
                 dev_set_name(&intf->dev, "%d-%s:%d.%d",
@@ -1641,17 +1728,21 @@ free_interfaces:
                                 dev_name(&intf->dev), ret);
                         continue;
                 }
-                usb_create_sysfs_intf_files(intf);
+                create_intf_ep_devs(intf);
         }
 
         usb_autosuspend_device(dev);
         return 0;
 }
 
+static LIST_HEAD(set_config_list);
+static DEFINE_SPINLOCK(set_config_lock);
+
 struct set_config_request {
         struct usb_device       *udev;
         int                     config;
         struct work_struct      work;
+        struct list_head        node;
 };
 
 /* Worker routine for usb_driver_set_configuration() */
@@ -1659,14 +1750,35 @@ static void driver_set_config_work(struct work_struct *work)
 {
         struct set_config_request *req =
                 container_of(work, struct set_config_request, work);
+        struct usb_device *udev = req->udev;
+
+        usb_lock_device(udev);
+        spin_lock(&set_config_lock);
+        list_del(&req->node);
+        spin_unlock(&set_config_lock);
 
-        usb_lock_device(req->udev);
-        usb_set_configuration(req->udev, req->config);
-        usb_unlock_device(req->udev);
-        usb_put_dev(req->udev);
+        if (req->config >= -1)          /* Is req still valid? */
+                usb_set_configuration(udev, req->config);
+        usb_unlock_device(udev);
+        usb_put_dev(udev);
         kfree(req);
 }
 
+/* Cancel pending Set-Config requests for a device whose configuration
+ * was just changed
+ */
+static void cancel_async_set_config(struct usb_device *udev)
+{
+        struct set_config_request *req;
+
+        spin_lock(&set_config_lock);
+        list_for_each_entry(req, &set_config_list, node) {
+                if (req->udev == udev)
+                        req->config = -999;     /* Mark as cancelled */
+        }
+        spin_unlock(&set_config_lock);
+}
+
 /**
  * usb_driver_set_configuration - Provide a way for drivers to change device configurations
  * @udev: the device whose configuration is being updated
@@ -1698,6 +1810,10 @@ int usb_driver_set_configuration(struct usb_device *udev, int config)
         req->config = config;
         INIT_WORK(&req->work, driver_set_config_work);
 
+        spin_lock(&set_config_lock);
+        list_add(&req->node, &set_config_list);
+        spin_unlock(&set_config_lock);
+
         usb_get_dev(udev);
         schedule_work(&req->work);
         return 0;
diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c
index 4fb65fdc9dc3..4cc2456ef3be 100644
--- a/drivers/usb/core/sysfs.c
+++ b/drivers/usb/core/sysfs.c
@@ -359,19 +359,19 @@ set_level(struct device *dev, struct device_attribute *attr,
                         strncmp(buf, on_string, len) == 0) {
                 udev->autosuspend_disabled = 1;
                 udev->autoresume_disabled = 0;
-                rc = usb_external_resume_device(udev);
+                rc = usb_external_resume_device(udev, PMSG_USER_RESUME);
 
         } else if (len == sizeof auto_string - 1 &&
                         strncmp(buf, auto_string, len) == 0) {
                 udev->autosuspend_disabled = 0;
                 udev->autoresume_disabled = 0;
-                rc = usb_external_resume_device(udev);
+                rc = usb_external_resume_device(udev, PMSG_USER_RESUME);
 
         } else if (len == sizeof suspend_string - 1 &&
                         strncmp(buf, suspend_string, len) == 0) {
                 udev->autosuspend_disabled = 0;
                 udev->autoresume_disabled = 1;
-                rc = usb_external_suspend_device(udev, PMSG_SUSPEND);
+                rc = usb_external_suspend_device(udev, PMSG_USER_SUSPEND);
 
         } else
                 rc = -EINVAL;
@@ -629,9 +629,6 @@ int usb_create_sysfs_dev_files(struct usb_device *udev)
         struct device *dev = &udev->dev;
         int retval;
 
-        /* Unforunately these attributes cannot be created before
-         * the uevent is broadcast.
-         */
         retval = device_create_bin_file(dev, &dev_bin_attr_descriptors);
         if (retval)
                 goto error;
@@ -643,11 +640,7 @@ int usb_create_sysfs_dev_files(struct usb_device *udev)
         retval = add_power_attributes(dev);
         if (retval)
                 goto error;
-
-        retval = usb_create_ep_files(dev, &udev->ep0, udev);
-        if (retval)
-                goto error;
-        return 0;
+        return retval;
 error:
         usb_remove_sysfs_dev_files(udev);
         return retval;
@@ -657,7 +650,6 @@ void usb_remove_sysfs_dev_files(struct usb_device *udev)
 {
         struct device *dev = &udev->dev;
 
-        usb_remove_ep_files(&udev->ep0);
         remove_power_attributes(dev);
         remove_persist_attributes(dev);
         device_remove_bin_file(dev, &dev_bin_attr_descriptors);
@@ -812,28 +804,6 @@ struct attribute_group *usb_interface_groups[] = {
         NULL
 };
 
-static inline void usb_create_intf_ep_files(struct usb_interface *intf,
-                struct usb_device *udev)
-{
-        struct usb_host_interface *iface_desc;
-        int i;
-
-        iface_desc = intf->cur_altsetting;
-        for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i)
-                usb_create_ep_files(&intf->dev, &iface_desc->endpoint[i],
-                                udev);
-}
-
-static inline void usb_remove_intf_ep_files(struct usb_interface *intf)
-{
-        struct usb_host_interface *iface_desc;
-        int i;
-
-        iface_desc = intf->cur_altsetting;
-        for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i)
-                usb_remove_ep_files(&iface_desc->endpoint[i]);
-}
-
 int usb_create_sysfs_intf_files(struct usb_interface *intf)
 {
         struct usb_device *udev = interface_to_usbdev(intf);
@@ -843,26 +813,19 @@ int usb_create_sysfs_intf_files(struct usb_interface *intf)
         if (intf->sysfs_files_created || intf->unregistering)
                 return 0;
 
-        /* The interface string may be present in some altsettings
-         * and missing in others.  Hence its attribute cannot be created
-         * before the uevent is broadcast.
-         */
         if (alt->string == NULL)
                 alt->string = usb_cache_string(udev, alt->desc.iInterface);
         if (alt->string)
                 retval = device_create_file(&intf->dev, &dev_attr_interface);
-        usb_create_intf_ep_files(intf, udev);
         intf->sysfs_files_created = 1;
         return 0;
 }
 
 void usb_remove_sysfs_intf_files(struct usb_interface *intf)
 {
-        struct device *dev = &intf->dev;
-
         if (!intf->sysfs_files_created)
                 return;
-        usb_remove_intf_ep_files(intf);
-        device_remove_file(dev, &dev_attr_interface);
+
+        device_remove_file(&intf->dev, &dev_attr_interface);
         intf->sysfs_files_created = 0;
 }
diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c
index 1f68af9db3f7..58bc5e3c2560 100644
--- a/drivers/usb/core/urb.c
+++ b/drivers/usb/core/urb.c
@@ -10,7 +10,6 @@
 
 #define to_urb(d) container_of(d, struct urb, kref)
 
-static DEFINE_SPINLOCK(usb_reject_lock);
 
 static void urb_destroy(struct kref *kref)
 {
@@ -131,9 +130,7 @@ void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor)
         urb->anchor = anchor;
 
         if (unlikely(anchor->poisoned)) {
-                spin_lock(&usb_reject_lock);
-                urb->reject++;
-                spin_unlock(&usb_reject_lock);
+                atomic_inc(&urb->reject);
         }
 
         spin_unlock_irqrestore(&anchor->lock, flags);
@@ -565,16 +562,12 @@ void usb_kill_urb(struct urb *urb)
         might_sleep();
         if (!(urb && urb->dev && urb->ep))
                 return;
-        spin_lock_irq(&usb_reject_lock);
-        ++urb->reject;
-        spin_unlock_irq(&usb_reject_lock);
+        atomic_inc(&urb->reject);
 
         usb_hcd_unlink_urb(urb, -ENOENT);
         wait_event(usb_kill_urb_queue, atomic_read(&urb->use_count) == 0);
 
-        spin_lock_irq(&usb_reject_lock);
-        --urb->reject;
-        spin_unlock_irq(&usb_reject_lock);
+        atomic_dec(&urb->reject);
 }
 EXPORT_SYMBOL_GPL(usb_kill_urb);
 
@@ -606,9 +599,7 @@ void usb_poison_urb(struct urb *urb)
         might_sleep();
         if (!(urb && urb->dev && urb->ep))
                 return;
-        spin_lock_irq(&usb_reject_lock);
-        ++urb->reject;
-        spin_unlock_irq(&usb_reject_lock);
+        atomic_inc(&urb->reject);
 
         usb_hcd_unlink_urb(urb, -ENOENT);
         wait_event(usb_kill_urb_queue, atomic_read(&urb->use_count) == 0);
@@ -617,14 +608,10 @@ EXPORT_SYMBOL_GPL(usb_poison_urb);
 
 void usb_unpoison_urb(struct urb *urb)
 {
-        unsigned long flags;
-
         if (!urb)
                 return;
 
-        spin_lock_irqsave(&usb_reject_lock, flags);
-        --urb->reject;
-        spin_unlock_irqrestore(&usb_reject_lock, flags);
+        atomic_dec(&urb->reject);
 }
 EXPORT_SYMBOL_GPL(usb_unpoison_urb);
 
@@ -692,6 +679,26 @@ void usb_poison_anchored_urbs(struct usb_anchor *anchor)
 EXPORT_SYMBOL_GPL(usb_poison_anchored_urbs);
 
 /**
+ * usb_unpoison_anchored_urbs - let an anchor be used successfully again
+ * @anchor: anchor the requests are bound to
+ *
+ * Reverses the effect of usb_poison_anchored_urbs
+ * the anchor can be used normally after it returns
+ */
+void usb_unpoison_anchored_urbs(struct usb_anchor *anchor)
+{
+        unsigned long flags;
+        struct urb *lazarus;
+
+        spin_lock_irqsave(&anchor->lock, flags);
+        list_for_each_entry(lazarus, &anchor->urb_list, anchor_list) {
+                usb_unpoison_urb(lazarus);
+        }
+        anchor->poisoned = 0;
+        spin_unlock_irqrestore(&anchor->lock, flags);
+}
+EXPORT_SYMBOL_GPL(usb_unpoison_anchored_urbs);
+/**
  * usb_unlink_anchored_urbs - asynchronously cancel transfer requests en masse
  * @anchor: anchor the requests are bound to
  *
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index 399e15fc5052..dcfc072630c1 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -253,7 +253,7 @@ static int usb_dev_prepare(struct device *dev)
 static void usb_dev_complete(struct device *dev)
 {
         /* Currently used only for rebinding interfaces */
-        usb_resume(dev);        /* Implement eventually? */
+        usb_resume(dev, PMSG_RESUME);   /* Message event is meaningless */
 }
 
 static int usb_dev_suspend(struct device *dev)
@@ -263,7 +263,7 @@ static int usb_dev_suspend(struct device *dev)
 
 static int usb_dev_resume(struct device *dev)
 {
-        return usb_resume(dev);
+        return usb_resume(dev, PMSG_RESUME);
 }
 
 static int usb_dev_freeze(struct device *dev)
@@ -273,7 +273,7 @@ static int usb_dev_freeze(struct device *dev)
 
 static int usb_dev_thaw(struct device *dev)
 {
-        return usb_resume(dev);
+        return usb_resume(dev, PMSG_THAW);
 }
 
 static int usb_dev_poweroff(struct device *dev)
@@ -283,7 +283,7 @@ static int usb_dev_poweroff(struct device *dev)
 
 static int usb_dev_restore(struct device *dev)
 {
-        return usb_resume(dev);
+        return usb_resume(dev, PMSG_RESTORE);
 }
 
 static struct dev_pm_ops usb_device_pm_ops = {
@@ -362,7 +362,7 @@ struct usb_device *usb_alloc_dev(struct usb_device *parent,
         dev->ep0.desc.bLength = USB_DT_ENDPOINT_SIZE;
         dev->ep0.desc.bDescriptorType = USB_DT_ENDPOINT;
         /* ep0 maxpacket comes later, from device descriptor */
-        usb_enable_endpoint(dev, &dev->ep0);
+        usb_enable_endpoint(dev, &dev->ep0, true);
         dev->can_submit = 1;
 
         /* Save readable and stable topology id, distinguishing devices
@@ -402,6 +402,7 @@ struct usb_device *usb_alloc_dev(struct usb_device *parent,
 #ifdef  CONFIG_PM
         mutex_init(&dev->pm_mutex);
         INIT_DELAYED_WORK(&dev->autosuspend, usb_autosuspend_work);
+        INIT_WORK(&dev->autoresume, usb_autoresume_work);
         dev->autosuspend_delay = usb_autosuspend_delay * HZ;
         dev->connect_time = jiffies;
         dev->active_duration = -jiffies;
@@ -513,10 +514,7 @@ EXPORT_SYMBOL_GPL(usb_put_intf);
  * disconnect; in some drivers (such as usb-storage) the disconnect()
  * or suspend() method will block waiting for a device reset to complete.
  *
- * Returns a negative error code for failure, otherwise 1 or 0 to indicate
- * that the device will or will not have to be unlocked.  (0 can be
- * returned when an interface is given and is BINDING, because in that
- * case the driver already owns the device lock.)
+ * Returns a negative error code for failure, otherwise 0.
  */
 int usb_lock_device_for_reset(struct usb_device *udev,
                               const struct usb_interface *iface)
@@ -527,16 +525,9 @@ int usb_lock_device_for_reset(struct usb_device *udev,
                 return -ENODEV;
         if (udev->state == USB_STATE_SUSPENDED)
                 return -EHOSTUNREACH;
-        if (iface) {
-                switch (iface->condition) {
-                case USB_INTERFACE_BINDING:
-                        return 0;
-                case USB_INTERFACE_BOUND:
-                        break;
-                default:
-                        return -EINTR;
-                }
-        }
+        if (iface && (iface->condition == USB_INTERFACE_UNBINDING ||
+                        iface->condition == USB_INTERFACE_UNBOUND))
+                return -EINTR;
 
         while (usb_trylock_device(udev) != 0) {
 
@@ -550,10 +541,11 @@ int usb_lock_device_for_reset(struct usb_device *udev,
                         return -ENODEV;
                 if (udev->state == USB_STATE_SUSPENDED)
                         return -EHOSTUNREACH;
-                if (iface && iface->condition != USB_INTERFACE_BOUND)
+                if (iface && (iface->condition == USB_INTERFACE_UNBINDING ||
+                                iface->condition == USB_INTERFACE_UNBOUND))
                         return -EINTR;
         }
-        return 1;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(usb_lock_device_for_reset);
 
@@ -962,8 +954,12 @@ void usb_buffer_unmap_sg(const struct usb_device *dev, int is_in,
 }
 EXPORT_SYMBOL_GPL(usb_buffer_unmap_sg);
 
-/* format to disable USB on kernel command line is: nousb */
-__module_param_call("", nousb, param_set_bool, param_get_bool, &nousb, 0444);
+/* To disable USB, kernel command line is 'nousb' not 'usbcore.nousb' */
+#ifdef MODULE
+module_param(nousb, bool, 0444);
+#else
+core_param(nousb, nousb, bool, 0444);
+#endif
 
 /*
  * for external read access to <nousb>
@@ -975,6 +971,37 @@ int usb_disabled(void)
 EXPORT_SYMBOL_GPL(usb_disabled);
 
 /*
+ * Notifications of device and interface registration
+ */
+static int usb_bus_notify(struct notifier_block *nb, unsigned long action,
+                void *data)
+{
+        struct device *dev = data;
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (dev->type == &usb_device_type)
+                        (void) usb_create_sysfs_dev_files(to_usb_device(dev));
+                else if (dev->type == &usb_if_device_type)
+                        (void) usb_create_sysfs_intf_files(
+                                        to_usb_interface(dev));
+                break;
+
+        case BUS_NOTIFY_DEL_DEVICE:
+                if (dev->type == &usb_device_type)
+                        usb_remove_sysfs_dev_files(to_usb_device(dev));
+                else if (dev->type == &usb_if_device_type)
+                        usb_remove_sysfs_intf_files(to_usb_interface(dev));
+                break;
+        }
+        return 0;
+}
+
+static struct notifier_block usb_bus_nb = {
+        .notifier_call = usb_bus_notify,
+};
+
+/*
  * Init
  */
 static int __init usb_init(void)
@@ -991,6 +1018,9 @@ static int __init usb_init(void)
         retval = bus_register(&usb_bus_type);
         if (retval)
                 goto bus_register_failed;
+        retval = bus_register_notifier(&usb_bus_type, &usb_bus_nb);
+        if (retval)
+                goto bus_notifier_failed;
         retval = usb_host_init();
         if (retval)
                 goto host_init_failed;
@@ -1025,6 +1055,8 @@ driver_register_failed:
 major_init_failed:
         usb_host_cleanup();
 host_init_failed:
+        bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
+bus_notifier_failed:
         bus_unregister(&usb_bus_type);
 bus_register_failed:
         ksuspend_usb_cleanup();
@@ -1048,6 +1080,7 @@ static void __exit usb_exit(void)
         usb_devio_cleanup();
         usb_hub_cleanup();
         usb_host_cleanup();
+        bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
         bus_unregister(&usb_bus_type);
         ksuspend_usb_cleanup();
 }
diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h
index 9a1a45ac3add..386177867a8a 100644
--- a/drivers/usb/core/usb.h
+++ b/drivers/usb/core/usb.h
@@ -1,16 +1,20 @@
+#include <linux/pm.h>
+
 /* Functions local to drivers/usb/core/ */
 
 extern int usb_create_sysfs_dev_files(struct usb_device *dev);
 extern void usb_remove_sysfs_dev_files(struct usb_device *dev);
 extern int usb_create_sysfs_intf_files(struct usb_interface *intf);
 extern void usb_remove_sysfs_intf_files(struct usb_interface *intf);
-extern int usb_create_ep_files(struct device *parent,
+extern int usb_create_ep_devs(struct device *parent,
                                 struct usb_host_endpoint *endpoint,
                                 struct usb_device *udev);
-extern void usb_remove_ep_files(struct usb_host_endpoint *endpoint);
+extern void usb_remove_ep_devs(struct usb_host_endpoint *endpoint);
 
 extern void usb_enable_endpoint(struct usb_device *dev,
-                struct usb_host_endpoint *ep);
+                struct usb_host_endpoint *ep, bool reset_toggle);
+extern void usb_enable_interface(struct usb_device *dev,
+                struct usb_interface *intf, bool reset_toggles);
 extern void usb_disable_endpoint(struct usb_device *dev, unsigned int epaddr);
 extern void usb_disable_interface(struct usb_device *dev,
                 struct usb_interface *intf);
@@ -42,14 +46,16 @@ extern void usb_host_cleanup(void);
 #ifdef  CONFIG_PM
 
 extern int usb_suspend(struct device *dev, pm_message_t msg);
-extern int usb_resume(struct device *dev);
+extern int usb_resume(struct device *dev, pm_message_t msg);
 
 extern void usb_autosuspend_work(struct work_struct *work);
-extern int usb_port_suspend(struct usb_device *dev);
-extern int usb_port_resume(struct usb_device *dev);
+extern void usb_autoresume_work(struct work_struct *work);
+extern int usb_port_suspend(struct usb_device *dev, pm_message_t msg);
+extern int usb_port_resume(struct usb_device *dev, pm_message_t msg);
 extern int usb_external_suspend_device(struct usb_device *udev,
                 pm_message_t msg);
-extern int usb_external_resume_device(struct usb_device *udev);
+extern int usb_external_resume_device(struct usb_device *udev,
+                pm_message_t msg);
 
 static inline void usb_pm_lock(struct usb_device *udev)
 {
@@ -63,12 +69,12 @@ static inline void usb_pm_unlock(struct usb_device *udev)
 
 #else
 
-static inline int usb_port_suspend(struct usb_device *udev)
+static inline int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
 {
         return 0;
 }
 
-static inline int usb_port_resume(struct usb_device *udev)
+static inline int usb_port_resume(struct usb_device *udev, pm_message_t msg)
 {
         return 0;
 }
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index dd4cd5a51370..3219d137340a 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -297,13 +297,34 @@ config USB_S3C2410_DEBUG
 
 # musb builds in ../musb along with host support
 config USB_GADGET_MUSB_HDRC
-        boolean "Inventra HDRC USB Peripheral (TI, ...)"
+        boolean "Inventra HDRC USB Peripheral (TI, ADI, ...)"
         depends on USB_MUSB_HDRC && (USB_MUSB_PERIPHERAL || USB_MUSB_OTG)
         select USB_GADGET_DUALSPEED
         select USB_GADGET_SELECTED
         help
           This OTG-capable silicon IP is used in dual designs including
-          the TI DaVinci, OMAP 243x, OMAP 343x, and TUSB 6010.
+          the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin
+
+config USB_GADGET_IMX
+        boolean "Freescale IMX USB Peripheral Controller"
+        depends on ARCH_MX1
+        help
+           Freescale's IMX series include an integrated full speed
+           USB 1.1 device controller.  The controller in the IMX series
+           is register-compatible.
+
+           It has Six fixed-function endpoints, as well as endpoint
+           zero (for control transfers).
+
+           Say "y" to link the driver statically, or "m" to build a
+           dynamically linked module called "imx_udc" and force all
+           gadget drivers to also be dynamically linked.
+
+config USB_IMX
+        tristate
+        depends on USB_GADGET_IMX
+        default USB_GADGET
+        select USB_GADGET_SELECTED
 
 config USB_GADGET_M66592
         boolean "Renesas M66592 USB Peripheral Controller"
@@ -377,6 +398,24 @@ config USB_FSL_QE
         default USB_GADGET
         select USB_GADGET_SELECTED
 
+config USB_GADGET_CI13XXX
+        boolean "MIPS USB CI13xxx"
+        depends on PCI
+        select USB_GADGET_DUALSPEED
+        help
+          MIPS USB IP core family device controller
+          Currently it only supports IP part number CI13412
+
+          Say "y" to link the driver statically, or "m" to build a
+          dynamically linked module called "ci13xxx_udc" and force all
+          gadget drivers to also be dynamically linked.
+
+config USB_CI13XXX
+        tristate
+        depends on USB_GADGET_CI13XXX
+        default USB_GADGET
+        select USB_GADGET_SELECTED
+
 config USB_GADGET_NET2280
         boolean "NetChip 228x"
         depends on PCI
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index bd4041b47dce..39a51d746cb7 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_USB_NET2280)	+= net2280.o
 obj-$(CONFIG_USB_AMD5536UDC)    += amd5536udc.o
 obj-$(CONFIG_USB_PXA25X)        += pxa25x_udc.o
 obj-$(CONFIG_USB_PXA27X)        += pxa27x_udc.o
+obj-$(CONFIG_USB_IMX)           += imx_udc.o
 obj-$(CONFIG_USB_GOKU)          += goku_udc.o
 obj-$(CONFIG_USB_OMAP)          += omap_udc.o
 obj-$(CONFIG_USB_LH7A40X)       += lh7a40x_udc.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_USB_ATMEL_USBA)	+= atmel_usba_udc.o
 obj-$(CONFIG_USB_FSL_USB2)      += fsl_usb2_udc.o
 obj-$(CONFIG_USB_M66592)        += m66592-udc.o
 obj-$(CONFIG_USB_FSL_QE)        += fsl_qe_udc.o
+obj-$(CONFIG_USB_CI13XXX)       += ci13xxx_udc.o
 
 #
 # USB gadget drivers
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
new file mode 100644
index 000000000000..bebf911c7e5f
--- /dev/null
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -0,0 +1,2830 @@
+/*
+ * ci13xxx_udc.c - MIPS USB IP core family device controller
+ *
+ * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
+ *
+ * Author: David Lopo
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Description: MIPS USB IP core family device controller
+ *              Currently it only supports IP part number CI13412
+ *
+ * This driver is composed of several blocks:
+ * - HW:     hardware interface
+ * - DBG:    debug facilities (optional)
+ * - UTIL:   utilities
+ * - ISR:    interrupts handling
+ * - ENDPT:  endpoint operations (Gadget API)
+ * - GADGET: gadget operations (Gadget API)
+ * - BUS:    bus glue code, bus abstraction layer
+ * - PCI:    PCI core interface and PCI resources (interrupts, memory...)
+ *
+ * Compile Options
+ * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
+ * - STALL_IN:  non-empty bulk-in pipes cannot be halted
+ *              if defined mass storage compliance succeeds but with warnings
+ *              => case 4: Hi >  Dn
+ *              => case 5: Hi >  Di
+ *              => case 8: Hi <> Do
+ *              if undefined usbtest 13 fails
+ * - TRACE:     enable function tracing (depends on DEBUG)
+ *
+ * Main Features
+ * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
+ * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
+ * - Normal & LPM support
+ *
+ * USBTEST Report
+ * - OK: 0-12, 13 (STALL_IN defined) & 14
+ * - Not Supported: 15 & 16 (ISO)
+ *
+ * TODO List
+ * - OTG
+ * - Isochronous & Interrupt Traffic
+ * - Handle requests which spawns into several TDs
+ * - GET_STATUS(device) - always reports 0
+ * - Gadget API (majority of optional features)
+ * - Suspend & Remote Wakeup
+ */
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include "ci13xxx_udc.h"
+
+
+/******************************************************************************
+ * DEFINE
+ *****************************************************************************/
+/* ctrl register bank access */
+static DEFINE_SPINLOCK(udc_lock);
+
+/* driver name */
+#define UDC_DRIVER_NAME   "ci13xxx_udc"
+
+/* control endpoint description */
+static const struct usb_endpoint_descriptor
+ctrl_endpt_desc = {
+        .bLength         = USB_DT_ENDPOINT_SIZE,
+        .bDescriptorType = USB_DT_ENDPOINT,
+
+        .bmAttributes    = USB_ENDPOINT_XFER_CONTROL,
+        .wMaxPacketSize  = cpu_to_le16(CTRL_PAYLOAD_MAX),
+};
+
+/* UDC descriptor */
+static struct ci13xxx *_udc;
+
+/* Interrupt statistics */
+#define ISR_MASK   0x1F
+static struct {
+        u32 test;
+        u32 ui;
+        u32 uei;
+        u32 pci;
+        u32 uri;
+        u32 sli;
+        u32 none;
+        struct {
+                u32 cnt;
+                u32 buf[ISR_MASK+1];
+                u32 idx;
+        } hndl;
+} isr_statistics;
+
+/**
+ * ffs_nr: find first (least significant) bit set
+ * @x: the word to search
+ *
+ * This function returns bit number (instead of position)
+ */
+static int ffs_nr(u32 x)
+{
+        int n = ffs(x);
+
+        return n ? n-1 : 32;
+}
+
+/******************************************************************************
+ * HW block
+ *****************************************************************************/
+/* register bank descriptor */
+static struct {
+        unsigned      lpm;    /* is LPM? */
+        void __iomem *abs;    /* bus map offset */
+        void __iomem *cap;    /* bus map offset + CAP offset + CAP data */
+        size_t        size;   /* bank size */
+} hw_bank;
+
+/* UDC register map */
+#define ABS_CAPLENGTH       (0x100UL)
+#define ABS_HCCPARAMS       (0x108UL)
+#define ABS_DCCPARAMS       (0x124UL)
+#define ABS_TESTMODE        (hw_bank.lpm ? 0x0FCUL : 0x138UL)
+/* offset to CAPLENTGH (addr + data) */
+#define CAP_USBCMD          (0x000UL)
+#define CAP_USBSTS          (0x004UL)
+#define CAP_USBINTR         (0x008UL)
+#define CAP_DEVICEADDR      (0x014UL)
+#define CAP_ENDPTLISTADDR   (0x018UL)
+#define CAP_PORTSC          (0x044UL)
+#define CAP_DEVLC           (0x0B4UL)
+#define CAP_USBMODE         (hw_bank.lpm ? 0x0C8UL : 0x068UL)
+#define CAP_ENDPTSETUPSTAT  (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
+#define CAP_ENDPTPRIME      (hw_bank.lpm ? 0x0DCUL : 0x070UL)
+#define CAP_ENDPTFLUSH      (hw_bank.lpm ? 0x0E0UL : 0x074UL)
+#define CAP_ENDPTSTAT       (hw_bank.lpm ? 0x0E4UL : 0x078UL)
+#define CAP_ENDPTCOMPLETE   (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
+#define CAP_ENDPTCTRL       (hw_bank.lpm ? 0x0ECUL : 0x080UL)
+#define CAP_LAST            (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
+
+/* maximum number of enpoints: valid only after hw_device_reset() */
+static unsigned hw_ep_max;
+
+/**
+ * hw_ep_bit: calculates the bit number
+ * @num: endpoint number
+ * @dir: endpoint direction
+ *
+ * This function returns bit number
+ */
+static inline int hw_ep_bit(int num, int dir)
+{
+        return num + (dir ? 16 : 0);
+}
+
+/**
+ * hw_aread: reads from register bitfield
+ * @addr: address relative to bus map
+ * @mask: bitfield mask
+ *
+ * This function returns register bitfield data
+ */
+static u32 hw_aread(u32 addr, u32 mask)
+{
+        return ioread32(addr + hw_bank.abs) & mask;
+}
+
+/**
+ * hw_awrite: writes to register bitfield
+ * @addr: address relative to bus map
+ * @mask: bitfield mask
+ * @data: new data
+ */
+static void hw_awrite(u32 addr, u32 mask, u32 data)
+{
+        iowrite32(hw_aread(addr, ~mask) | (data & mask),
+                  addr + hw_bank.abs);
+}
+
+/**
+ * hw_cread: reads from register bitfield
+ * @addr: address relative to CAP offset plus content
+ * @mask: bitfield mask
+ *
+ * This function returns register bitfield data
+ */
+static u32 hw_cread(u32 addr, u32 mask)
+{
+        return ioread32(addr + hw_bank.cap) & mask;
+}
+
+/**
+ * hw_cwrite: writes to register bitfield
+ * @addr: address relative to CAP offset plus content
+ * @mask: bitfield mask
+ * @data: new data
+ */
+static void hw_cwrite(u32 addr, u32 mask, u32 data)
+{
+        iowrite32(hw_cread(addr, ~mask) | (data & mask),
+                  addr + hw_bank.cap);
+}
+
+/**
+ * hw_ctest_and_clear: tests & clears register bitfield
+ * @addr: address relative to CAP offset plus content
+ * @mask: bitfield mask
+ *
+ * This function returns register bitfield data
+ */
+static u32 hw_ctest_and_clear(u32 addr, u32 mask)
+{
+        u32 reg = hw_cread(addr, mask);
+
+        iowrite32(reg, addr + hw_bank.cap);
+        return reg;
+}
+
+/**
+ * hw_ctest_and_write: tests & writes register bitfield
+ * @addr: address relative to CAP offset plus content
+ * @mask: bitfield mask
+ * @data: new data
+ *
+ * This function returns register bitfield data
+ */
+static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
+{
+        u32 reg = hw_cread(addr, ~0);
+
+        iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
+        return (reg & mask) >> ffs_nr(mask);
+}
+
+/**
+ * hw_device_reset: resets chip (execute without interruption)
+ * @base: register base address
+ *
+ * This function returns an error code
+ */
+static int hw_device_reset(void __iomem *base)
+{
+        u32 reg;
+
+        /* bank is a module variable */
+        hw_bank.abs = base;
+
+        hw_bank.cap = hw_bank.abs;
+        hw_bank.cap += ABS_CAPLENGTH;
+        hw_bank.cap += ioread8(hw_bank.cap);
+
+        reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
+        hw_bank.lpm  = reg;
+        hw_bank.size = hw_bank.cap - hw_bank.abs;
+        hw_bank.size += CAP_LAST;
+        hw_bank.size /= sizeof(u32);
+
+        /* should flush & stop before reset */
+        hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
+        hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
+
+        hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
+        while (hw_cread(CAP_USBCMD, USBCMD_RST))
+                udelay(10);             /* not RTOS friendly */
+
+        /* USBMODE should be configured step by step */
+        hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
+        hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
+        hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);  /* HW >= 2.3 */
+
+        if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
+                pr_err("cannot enter in device mode");
+                pr_err("lpm = %i", hw_bank.lpm);
+                return -ENODEV;
+        }
+
+        reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
+        if (reg == 0 || reg > ENDPT_MAX)
+                return -ENODEV;
+
+        hw_ep_max = reg;   /* cache hw ENDPT_MAX */
+
+        /* setup lock mode ? */
+
+        /* ENDPTSETUPSTAT is '0' by default */
+
+        /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
+
+        return 0;
+}
+
+/**
+ * hw_device_state: enables/disables interrupts & starts/stops device (execute
+ *                  without interruption)
+ * @dma: 0 => disable, !0 => enable and set dma engine
+ *
+ * This function returns an error code
+ */
+static int hw_device_state(u32 dma)
+{
+        if (dma) {
+                hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
+                /* interrupt, error, port change, reset, sleep/suspend */
+                hw_cwrite(CAP_USBINTR, ~0,
+                             USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
+                hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
+        } else {
+                hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
+                hw_cwrite(CAP_USBINTR, ~0, 0);
+        }
+        return 0;
+}
+
+/**
+ * hw_ep_flush: flush endpoint fifo (execute without interruption)
+ * @num: endpoint number
+ * @dir: endpoint direction
+ *
+ * This function returns an error code
+ */
+static int hw_ep_flush(int num, int dir)
+{
+        int n = hw_ep_bit(num, dir);
+
+        do {
+                /* flush any pending transfer */
+                hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
+                while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
+                        cpu_relax();
+        } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
+
+        return 0;
+}
+
+/**
+ * hw_ep_disable: disables endpoint (execute without interruption)
+ * @num: endpoint number
+ * @dir: endpoint direction
+ *
+ * This function returns an error code
+ */
+static int hw_ep_disable(int num, int dir)
+{
+        hw_ep_flush(num, dir);
+        hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
+                  dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
+        return 0;
+}
+
+/**
+ * hw_ep_enable: enables endpoint (execute without interruption)
+ * @num:  endpoint number
+ * @dir:  endpoint direction
+ * @type: endpoint type
+ *
+ * This function returns an error code
+ */
+static int hw_ep_enable(int num, int dir, int type)
+{
+        u32 mask, data;
+
+        if (dir) {
+                mask  = ENDPTCTRL_TXT;  /* type    */
+                data  = type << ffs_nr(mask);
+
+                mask |= ENDPTCTRL_TXS;  /* unstall */
+                mask |= ENDPTCTRL_TXR;  /* reset data toggle */
+                data |= ENDPTCTRL_TXR;
+                mask |= ENDPTCTRL_TXE;  /* enable  */
+                data |= ENDPTCTRL_TXE;
+        } else {
+                mask  = ENDPTCTRL_RXT;  /* type    */
+                data  = type << ffs_nr(mask);
+
+                mask |= ENDPTCTRL_RXS;  /* unstall */
+                mask |= ENDPTCTRL_RXR;  /* reset data toggle */
+                data |= ENDPTCTRL_RXR;
+                mask |= ENDPTCTRL_RXE;  /* enable  */
+                data |= ENDPTCTRL_RXE;
+        }
+        hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
+        return 0;
+}
+
+/**
+ * hw_ep_get_halt: return endpoint halt status
+ * @num: endpoint number
+ * @dir: endpoint direction
+ *
+ * This function returns 1 if endpoint halted
+ */
+static int hw_ep_get_halt(int num, int dir)
+{
+        u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
+
+        return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
+}
+
+/**
+ * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
+ * @num:   endpoint number
+ * @dir:   endpoint direction
+ *
+ * This function returns true if endpoint primed
+ */
+static int hw_ep_is_primed(int num, int dir)
+{
+        u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
+
+        return test_bit(hw_ep_bit(num, dir), (void *)&reg);
+}
+
+/**
+ * hw_test_and_clear_setup_status: test & clear setup status (execute without
+ *                                 interruption)
+ * @n: bit number (endpoint)
+ *
+ * This function returns setup status
+ */
+static int hw_test_and_clear_setup_status(int n)
+{
+        return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
+}
+
+/**
+ * hw_ep_prime: primes endpoint (execute without interruption)
+ * @num:     endpoint number
+ * @dir:     endpoint direction
+ * @is_ctrl: true if control endpoint
+ *
+ * This function returns an error code
+ */
+static int hw_ep_prime(int num, int dir, int is_ctrl)
+{
+        int n = hw_ep_bit(num, dir);
+
+        /* the caller should flush first */
+        if (hw_ep_is_primed(num, dir))
+                return -EBUSY;
+
+        if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
+                return -EAGAIN;
+
+        hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
+
+        while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
+                cpu_relax();
+        if (is_ctrl && dir == RX  && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
+                return -EAGAIN;
+
+        /* status shoult be tested according with manual but it doesn't work */
+        return 0;
+}
+
+/**
+ * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
+ *                 without interruption)
+ * @num:   endpoint number
+ * @dir:   endpoint direction
+ * @value: true => stall, false => unstall
+ *
+ * This function returns an error code
+ */
+static int hw_ep_set_halt(int num, int dir, int value)
+{
+        if (value != 0 && value != 1)
+                return -EINVAL;
+
+        do {
+                u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
+                u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
+                u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
+
+                /* data toggle - reserved for EP0 but it's in ESS */
+                hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
+
+        } while (value != hw_ep_get_halt(num, dir));
+
+        return 0;
+}
+
+/**
+ * hw_intr_clear: disables interrupt & clears interrupt status (execute without
+ *                interruption)
+ * @n: interrupt bit
+ *
+ * This function returns an error code
+ */
+static int hw_intr_clear(int n)
+{
+        if (n >= REG_BITS)
+                return -EINVAL;
+
+        hw_cwrite(CAP_USBINTR, BIT(n), 0);
+        hw_cwrite(CAP_USBSTS,  BIT(n), BIT(n));
+        return 0;
+}
+
+/**
+ * hw_intr_force: enables interrupt & forces interrupt status (execute without
+ *                interruption)
+ * @n: interrupt bit
+ *
+ * This function returns an error code
+ */
+static int hw_intr_force(int n)
+{
+        if (n >= REG_BITS)
+                return -EINVAL;
+
+        hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
+        hw_cwrite(CAP_USBINTR,  BIT(n), BIT(n));
+        hw_cwrite(CAP_USBSTS,   BIT(n), BIT(n));
+        hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
+        return 0;
+}
+
+/**
+ * hw_is_port_high_speed: test if port is high speed
+ *
+ * This function returns true if high speed port
+ */
+static int hw_port_is_high_speed(void)
+{
+        return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
+                hw_cread(CAP_PORTSC, PORTSC_HSP);
+}
+
+/**
+ * hw_port_test_get: reads port test mode value
+ *
+ * This function returns port test mode value
+ */
+static u8 hw_port_test_get(void)
+{
+        return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
+}
+
+/**
+ * hw_port_test_set: writes port test mode (execute without interruption)
+ * @mode: new value
+ *
+ * This function returns an error code
+ */
+static int hw_port_test_set(u8 mode)
+{
+        const u8 TEST_MODE_MAX = 7;
+
+        if (mode > TEST_MODE_MAX)
+                return -EINVAL;
+
+        hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
+        return 0;
+}
+
+/**
+ * hw_read_intr_enable: returns interrupt enable register
+ *
+ * This function returns register data
+ */
+static u32 hw_read_intr_enable(void)
+{
+        return hw_cread(CAP_USBINTR, ~0);
+}
+
+/**
+ * hw_read_intr_status: returns interrupt status register
+ *
+ * This function returns register data
+ */
+static u32 hw_read_intr_status(void)
+{
+        return hw_cread(CAP_USBSTS, ~0);
+}
+
+/**
+ * hw_register_read: reads all device registers (execute without interruption)
+ * @buf:  destination buffer
+ * @size: buffer size
+ *
+ * This function returns number of registers read
+ */
+static size_t hw_register_read(u32 *buf, size_t size)
+{
+        unsigned i;
+
+        if (size > hw_bank.size)
+                size = hw_bank.size;
+
+        for (i = 0; i < size; i++)
+                buf[i] = hw_aread(i * sizeof(u32), ~0);
+
+        return size;
+}
+
+/**
+ * hw_register_write: writes to register
+ * @addr: register address
+ * @data: register value
+ *
+ * This function returns an error code
+ */
+static int hw_register_write(u16 addr, u32 data)
+{
+        /* align */
+        addr /= sizeof(u32);
+
+        if (addr >= hw_bank.size)
+                return -EINVAL;
+
+        /* align */
+        addr *= sizeof(u32);
+
+        hw_awrite(addr, ~0, data);
+        return 0;
+}
+
+/**
+ * hw_test_and_clear_complete: test & clear complete status (execute without
+ *                             interruption)
+ * @n: bit number (endpoint)
+ *
+ * This function returns complete status
+ */
+static int hw_test_and_clear_complete(int n)
+{
+        return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
+}
+
+/**
+ * hw_test_and_clear_intr_active: test & clear active interrupts (execute
+ *                                without interruption)
+ *
+ * This function returns active interrutps
+ */
+static u32 hw_test_and_clear_intr_active(void)
+{
+        u32 reg = hw_read_intr_status() & hw_read_intr_enable();
+
+        hw_cwrite(CAP_USBSTS, ~0, reg);
+        return reg;
+}
+
+/**
+ * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
+ *                                interruption)
+ *
+ * This function returns guard value
+ */
+static int hw_test_and_clear_setup_guard(void)
+{
+        return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
+}
+
+/**
+ * hw_test_and_set_setup_guard: test & set setup guard (execute without
+ *                              interruption)
+ *
+ * This function returns guard value
+ */
+static int hw_test_and_set_setup_guard(void)
+{
+        return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
+}
+
+/**
+ * hw_usb_set_address: configures USB address (execute without interruption)
+ * @value: new USB address
+ *
+ * This function returns an error code
+ */
+static int hw_usb_set_address(u8 value)
+{
+        /* advance */
+        hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
+                  value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
+        return 0;
+}
+
+/**
+ * hw_usb_reset: restart device after a bus reset (execute without
+ *               interruption)
+ *
+ * This function returns an error code
+ */
+static int hw_usb_reset(void)
+{
+        hw_usb_set_address(0);
+
+        /* ESS flushes only at end?!? */
+        hw_cwrite(CAP_ENDPTFLUSH,    ~0, ~0);   /* flush all EPs */
+
+        /* clear setup token semaphores */
+        hw_cwrite(CAP_ENDPTSETUPSTAT, 0,  0);   /* writes its content */
+
+        /* clear complete status */
+        hw_cwrite(CAP_ENDPTCOMPLETE,  0,  0);   /* writes its content */
+
+        /* wait until all bits cleared */
+        while (hw_cread(CAP_ENDPTPRIME, ~0))
+                udelay(10);             /* not RTOS friendly */
+
+        /* reset all endpoints ? */
+
+        /* reset internal status and wait for further instructions
+           no need to verify the port reset status (ESS does it) */
+
+        return 0;
+}
+
+/******************************************************************************
+ * DBG block
+ *****************************************************************************/
+/**
+ * show_device: prints information about device capabilities and status
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_device(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        struct usb_gadget *gadget = &udc->gadget;
+        int n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        n += scnprintf(buf + n, PAGE_SIZE - n, "speed             = %d\n",
+                       gadget->speed);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed      = %d\n",
+                       gadget->is_dualspeed);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg            = %d\n",
+                       gadget->is_otg);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral   = %d\n",
+                       gadget->is_a_peripheral);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable      = %d\n",
+                       gadget->b_hnp_enable);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support     = %d\n",
+                       gadget->a_hnp_support);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
+                       gadget->a_alt_hnp_support);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "name              = %s\n",
+                       (gadget->name ? gadget->name : ""));
+
+        return n;
+}
+static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
+
+/**
+ * show_driver: prints information about attached gadget (if any)
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        struct usb_gadget_driver *driver = udc->driver;
+        int n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        if (driver == NULL)
+                return scnprintf(buf, PAGE_SIZE,
+                                 "There is no gadget attached!\n");
+
+        n += scnprintf(buf + n, PAGE_SIZE - n, "function  = %s\n",
+                       (driver->function ? driver->function : ""));
+        n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
+                       driver->speed);
+
+        return n;
+}
+static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
+
+/* Maximum event message length */
+#define DBG_DATA_MSG   64UL
+
+/* Maximum event messages */
+#define DBG_DATA_MAX   128UL
+
+/* Event buffer descriptor */
+static struct {
+        char     (buf[DBG_DATA_MAX])[DBG_DATA_MSG];   /* buffer */
+        unsigned idx;   /* index */
+        unsigned tty;   /* print to console? */
+        rwlock_t lck;   /* lock */
+} dbg_data = {
+        .idx = 0,
+        .tty = 0,
+        .lck = __RW_LOCK_UNLOCKED(lck)
+};
+
+/**
+ * dbg_dec: decrements debug event index
+ * @idx: buffer index
+ */
+static void dbg_dec(unsigned *idx)
+{
+        *idx = (*idx - 1) & (DBG_DATA_MAX-1);
+}
+
+/**
+ * dbg_inc: increments debug event index
+ * @idx: buffer index
+ */
+static void dbg_inc(unsigned *idx)
+{
+        *idx = (*idx + 1) & (DBG_DATA_MAX-1);
+}
+
+/**
+ * dbg_print:  prints the common part of the event
+ * @addr:   endpoint address
+ * @name:   event name
+ * @status: status
+ * @extra:  extra information
+ */
+static void dbg_print(u8 addr, const char *name, int status, const char *extra)
+{
+        struct timeval tval;
+        unsigned int stamp;
+        unsigned long flags;
+
+        write_lock_irqsave(&dbg_data.lck, flags);
+
+        do_gettimeofday(&tval);
+        stamp = tval.tv_sec & 0xFFFF;   /* 2^32 = 4294967296. Limit to 4096s */
+        stamp = stamp * 1000000 + tval.tv_usec;
+
+        scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
+                  "%04X\t» %02X %-7.7s %4i «\t%s\n",
+                  stamp, addr, name, status, extra);
+
+        dbg_inc(&dbg_data.idx);
+
+        write_unlock_irqrestore(&dbg_data.lck, flags);
+
+        if (dbg_data.tty != 0)
+                pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
+                          stamp, addr, name, status, extra);
+}
+
+/**
+ * dbg_done: prints a DONE event
+ * @addr:   endpoint address
+ * @td:     transfer descriptor
+ * @status: status
+ */
+static void dbg_done(u8 addr, const u32 token, int status)
+{
+        char msg[DBG_DATA_MSG];
+
+        scnprintf(msg, sizeof(msg), "%d %02X",
+                  (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
+                  (int)(token & TD_STATUS)      >> ffs_nr(TD_STATUS));
+        dbg_print(addr, "DONE", status, msg);
+}
+
+/**
+ * dbg_event: prints a generic event
+ * @addr:   endpoint address
+ * @name:   event name
+ * @status: status
+ */
+static void dbg_event(u8 addr, const char *name, int status)
+{
+        if (name != NULL)
+                dbg_print(addr, name, status, "");
+}
+
+/*
+ * dbg_queue: prints a QUEUE event
+ * @addr:   endpoint address
+ * @req:    USB request
+ * @status: status
+ */
+static void dbg_queue(u8 addr, const struct usb_request *req, int status)
+{
+        char msg[DBG_DATA_MSG];
+
+        if (req != NULL) {
+                scnprintf(msg, sizeof(msg),
+                          "%d %d", !req->no_interrupt, req->length);
+                dbg_print(addr, "QUEUE", status, msg);
+        }
+}
+
+/**
+ * dbg_setup: prints a SETUP event
+ * @addr: endpoint address
+ * @req:  setup request
+ */
+static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
+{
+        char msg[DBG_DATA_MSG];
+
+        if (req != NULL) {
+                scnprintf(msg, sizeof(msg),
+                          "%02X %02X %04X %04X %d", req->bRequestType,
+                          req->bRequest, le16_to_cpu(req->wValue),
+                          le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
+                dbg_print(addr, "SETUP", 0, msg);
+        }
+}
+
+/**
+ * show_events: displays the event buffer
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_events(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        unsigned long flags;
+        unsigned i, j, n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        read_lock_irqsave(&dbg_data.lck, flags);
+
+        i = dbg_data.idx;
+        for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
+                n += strlen(dbg_data.buf[i]);
+                if (n >= PAGE_SIZE) {
+                        n -= strlen(dbg_data.buf[i]);
+                        break;
+                }
+        }
+        for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
+                j += scnprintf(buf + j, PAGE_SIZE - j,
+                               "%s", dbg_data.buf[i]);
+
+        read_unlock_irqrestore(&dbg_data.lck, flags);
+
+        return n;
+}
+
+/**
+ * store_events: configure if events are going to be also printed to console
+ *
+ * Check "device.h" for details
+ */
+static ssize_t store_events(struct device *dev, struct device_attribute *attr,
+                            const char *buf, size_t count)
+{
+        unsigned tty;
+
+        dbg_trace("[%s] %p, %d\n", __func__, buf, count);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                goto done;
+        }
+
+        if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
+                dev_err(dev, "<1|0>: enable|disable console log\n");
+                goto done;
+        }
+
+        dbg_data.tty = tty;
+        dev_info(dev, "tty = %u", dbg_data.tty);
+
+ done:
+        return count;
+}
+static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
+
+/**
+ * show_inters: interrupt status, enable status and historic
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        u32 intr;
+        unsigned i, j, n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+
+        n += scnprintf(buf + n, PAGE_SIZE - n,
+                       "status = %08x\n", hw_read_intr_status());
+        n += scnprintf(buf + n, PAGE_SIZE - n,
+                       "enable = %08x\n", hw_read_intr_enable());
+
+        n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
+                       isr_statistics.test);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "» ui  = %d\n",
+                       isr_statistics.ui);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
+                       isr_statistics.uei);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
+                       isr_statistics.pci);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
+                       isr_statistics.uri);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
+                       isr_statistics.sli);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
+                       isr_statistics.none);
+        n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
+                       isr_statistics.hndl.cnt);
+
+        for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
+                i   &= ISR_MASK;
+                intr = isr_statistics.hndl.buf[i];
+
+                if (USBi_UI  & intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "ui  ");
+                intr &= ~USBi_UI;
+                if (USBi_UEI & intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
+                intr &= ~USBi_UEI;
+                if (USBi_PCI & intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
+                intr &= ~USBi_PCI;
+                if (USBi_URI & intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
+                intr &= ~USBi_URI;
+                if (USBi_SLI & intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
+                intr &= ~USBi_SLI;
+                if (intr)
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
+                if (isr_statistics.hndl.buf[i])
+                        n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
+        }
+
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        return n;
+}
+
+/**
+ * store_inters: enable & force or disable an individual interrutps
+ *                   (to be used for test purposes only)
+ *
+ * Check "device.h" for details
+ */
+static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
+                            const char *buf, size_t count)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        unsigned en, bit;
+
+        dbg_trace("[%s] %p, %d\n", __func__, buf, count);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                goto done;
+        }
+
+        if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
+                dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
+                goto done;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        if (en) {
+                if (hw_intr_force(bit))
+                        dev_err(dev, "invalid bit number\n");
+                else
+                        isr_statistics.test++;
+        } else {
+                if (hw_intr_clear(bit))
+                        dev_err(dev, "invalid bit number\n");
+        }
+        spin_unlock_irqrestore(udc->lock, flags);
+
+ done:
+        return count;
+}
+static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
+
+/**
+ * show_port_test: reads port test mode
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_port_test(struct device *dev,
+                              struct device_attribute *attr, char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        unsigned mode;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        mode = hw_port_test_get();
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
+}
+
+/**
+ * store_port_test: writes port test mode
+ *
+ * Check "device.h" for details
+ */
+static ssize_t store_port_test(struct device *dev,
+                               struct device_attribute *attr,
+                               const char *buf, size_t count)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        unsigned mode;
+
+        dbg_trace("[%s] %p, %d\n", __func__, buf, count);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                goto done;
+        }
+
+        if (sscanf(buf, "%u", &mode) != 1) {
+                dev_err(dev, "<mode>: set port test mode");
+                goto done;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        if (hw_port_test_set(mode))
+                dev_err(dev, "invalid mode\n");
+        spin_unlock_irqrestore(udc->lock, flags);
+
+ done:
+        return count;
+}
+static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
+                   show_port_test, store_port_test);
+
+/**
+ * show_qheads: DMA contents of all queue heads
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        unsigned i, j, n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        for (i = 0; i < hw_ep_max; i++) {
+                struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
+                n += scnprintf(buf + n, PAGE_SIZE - n,
+                               "EP=%02i: RX=%08X TX=%08X\n",
+                               i, (u32)mEp->qh[RX].dma, (u32)mEp->qh[TX].dma);
+                for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
+                        n += scnprintf(buf + n, PAGE_SIZE - n,
+                                       " %04X:    %08X    %08X\n", j,
+                                       *((u32 *)mEp->qh[RX].ptr + j),
+                                       *((u32 *)mEp->qh[TX].ptr + j));
+                }
+        }
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        return n;
+}
+static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
+
+/**
+ * show_registers: dumps all registers
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_registers(struct device *dev,
+                              struct device_attribute *attr, char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        u32 dump[512];
+        unsigned i, k, n = 0;
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        for (i = 0; i < k; i++) {
+                n += scnprintf(buf + n, PAGE_SIZE - n,
+                               "reg[0x%04X] = 0x%08X\n",
+                               i * (unsigned)sizeof(u32), dump[i]);
+        }
+
+        return n;
+}
+
+/**
+ * store_registers: writes value to register address
+ *
+ * Check "device.h" for details
+ */
+static ssize_t store_registers(struct device *dev,
+                               struct device_attribute *attr,
+                               const char *buf, size_t count)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long addr, data, flags;
+
+        dbg_trace("[%s] %p, %d\n", __func__, buf, count);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                goto done;
+        }
+
+        if (sscanf(buf, "%li %li", &addr, &data) != 2) {
+                dev_err(dev, "<addr> <data>: write data to register address");
+                goto done;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        if (hw_register_write(addr, data))
+                dev_err(dev, "invalid address range\n");
+        spin_unlock_irqrestore(udc->lock, flags);
+
+ done:
+        return count;
+}
+static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
+                   show_registers, store_registers);
+
+/**
+ * show_requests: DMA contents of all requests currently queued (all endpts)
+ *
+ * Check "device.h" for details
+ */
+static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
+                             char *buf)
+{
+        struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
+        unsigned long flags;
+        struct list_head   *ptr = NULL;
+        struct ci13xxx_req *req = NULL;
+        unsigned i, j, k, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
+
+        dbg_trace("[%s] %p\n", __func__, buf);
+        if (attr == NULL || buf == NULL) {
+                dev_err(dev, "[%s] EINVAL\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+        for (i = 0; i < hw_ep_max; i++)
+                for (k = RX; k <= TX; k++)
+                        list_for_each(ptr, &udc->ci13xxx_ep[i].qh[k].queue)
+                        {
+                                req = list_entry(ptr,
+                                                 struct ci13xxx_req, queue);
+
+                                n += scnprintf(buf + n, PAGE_SIZE - n,
+                                               "EP=%02i: TD=%08X %s\n",
+                                               i, (u32)req->dma,
+                                               ((k == RX) ? "RX" : "TX"));
+
+                                for (j = 0; j < qSize; j++)
+                                        n += scnprintf(buf + n, PAGE_SIZE - n,
+                                                       " %04X:    %08X\n", j,
+                                                       *((u32 *)req->ptr + j));
+                        }
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        return n;
+}
+static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
+
+/**
+ * dbg_create_files: initializes the attribute interface
+ * @dev: device
+ *
+ * This function returns an error code
+ */
+__maybe_unused static int dbg_create_files(struct device *dev)
+{
+        int retval = 0;
+
+        if (dev == NULL)
+                return -EINVAL;
+        retval = device_create_file(dev, &dev_attr_device);
+        if (retval)
+                goto done;
+        retval = device_create_file(dev, &dev_attr_driver);
+        if (retval)
+                goto rm_device;
+        retval = device_create_file(dev, &dev_attr_events);
+        if (retval)
+                goto rm_driver;
+        retval = device_create_file(dev, &dev_attr_inters);
+        if (retval)
+                goto rm_events;
+        retval = device_create_file(dev, &dev_attr_port_test);
+        if (retval)
+                goto rm_inters;
+        retval = device_create_file(dev, &dev_attr_qheads);
+        if (retval)
+                goto rm_port_test;
+        retval = device_create_file(dev, &dev_attr_registers);
+        if (retval)
+                goto rm_qheads;
+        retval = device_create_file(dev, &dev_attr_requests);
+        if (retval)
+                goto rm_registers;
+        return 0;
+
+ rm_registers:
+        device_remove_file(dev, &dev_attr_registers);
+ rm_qheads:
+        device_remove_file(dev, &dev_attr_qheads);
+ rm_port_test:
+        device_remove_file(dev, &dev_attr_port_test);
+ rm_inters:
+        device_remove_file(dev, &dev_attr_inters);
+ rm_events:
+        device_remove_file(dev, &dev_attr_events);
+ rm_driver:
+        device_remove_file(dev, &dev_attr_driver);
+ rm_device:
+        device_remove_file(dev, &dev_attr_device);
+ done:
+        return retval;
+}
+
+/**
+ * dbg_remove_files: destroys the attribute interface
+ * @dev: device
+ *
+ * This function returns an error code
+ */
+__maybe_unused static int dbg_remove_files(struct device *dev)
+{
+        if (dev == NULL)
+                return -EINVAL;
+        device_remove_file(dev, &dev_attr_requests);
+        device_remove_file(dev, &dev_attr_registers);
+        device_remove_file(dev, &dev_attr_qheads);
+        device_remove_file(dev, &dev_attr_port_test);
+        device_remove_file(dev, &dev_attr_inters);
+        device_remove_file(dev, &dev_attr_events);
+        device_remove_file(dev, &dev_attr_driver);
+        device_remove_file(dev, &dev_attr_device);
+        return 0;
+}
+
+/******************************************************************************
+ * UTIL block
+ *****************************************************************************/
+/**
+ * _usb_addr: calculates endpoint address from direction & number
+ * @ep:  endpoint
+ */
+static inline u8 _usb_addr(struct ci13xxx_ep *ep)
+{
+        return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
+}
+
+/**
+ * _hardware_queue: configures a request at hardware level
+ * @gadget: gadget
+ * @mEp:    endpoint
+ *
+ * This function returns an error code
+ */
+static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
+{
+        unsigned i;
+
+        trace("%p, %p", mEp, mReq);
+
+        /* don't queue twice */
+        if (mReq->req.status == -EALREADY)
+                return -EALREADY;
+
+        if (hw_ep_is_primed(mEp->num, mEp->dir))
+                return -EBUSY;
+
+        mReq->req.status = -EALREADY;
+
+        if (mReq->req.length && !mReq->req.dma) {
+                mReq->req.dma = \
+                        dma_map_single(mEp->device, mReq->req.buf,
+                                       mReq->req.length, mEp->dir ?
+                                       DMA_TO_DEVICE : DMA_FROM_DEVICE);
+                if (mReq->req.dma == 0)
+                        return -ENOMEM;
+
+                mReq->map = 1;
+        }
+
+        /*
+         * TD configuration
+         * TODO - handle requests which spawns into several TDs
+         */
+        memset(mReq->ptr, 0, sizeof(*mReq->ptr));
+        mReq->ptr->next    |= TD_TERMINATE;
+        mReq->ptr->token    = mReq->req.length << ffs_nr(TD_TOTAL_BYTES);
+        mReq->ptr->token   &= TD_TOTAL_BYTES;
+        mReq->ptr->token   |= TD_IOC;
+        mReq->ptr->token   |= TD_STATUS_ACTIVE;
+        mReq->ptr->page[0]  = mReq->req.dma;
+        for (i = 1; i < 5; i++)
+                mReq->ptr->page[i] =
+                        (mReq->req.dma + i * PAGE_SIZE) & ~TD_RESERVED_MASK;
+
+        /*
+         *  QH configuration
+         *  At this point it's guaranteed exclusive access to qhead
+         *  (endpt is not primed) so it's no need to use tripwire
+         */
+        mEp->qh[mEp->dir].ptr->td.next   = mReq->dma;    /* TERMINATE = 0 */
+        mEp->qh[mEp->dir].ptr->td.token &= ~TD_STATUS;   /* clear status */
+        if (mReq->req.zero == 0)
+                mEp->qh[mEp->dir].ptr->cap |=  QH_ZLT;
+        else
+                mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
+
+        wmb();   /* synchronize before ep prime */
+
+        return hw_ep_prime(mEp->num, mEp->dir,
+                           mEp->type == USB_ENDPOINT_XFER_CONTROL);
+}
+
+/**
+ * _hardware_dequeue: handles a request at hardware level
+ * @gadget: gadget
+ * @mEp:    endpoint
+ *
+ * This function returns an error code
+ */
+static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
+{
+        trace("%p, %p", mEp, mReq);
+
+        if (mReq->req.status != -EALREADY)
+                return -EINVAL;
+
+        if (hw_ep_is_primed(mEp->num, mEp->dir))
+                hw_ep_flush(mEp->num, mEp->dir);
+
+        mReq->req.status = 0;
+
+        if (mReq->map) {
+                dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
+                                 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+                mReq->req.dma = 0;
+                mReq->map     = 0;
+        }
+
+        mReq->req.status = mReq->ptr->token & TD_STATUS;
+        if      ((TD_STATUS_ACTIVE & mReq->req.status) != 0)
+                mReq->req.status = -ECONNRESET;
+        else if ((TD_STATUS_HALTED & mReq->req.status) != 0)
+                mReq->req.status = -1;
+        else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
+                mReq->req.status = -1;
+        else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
+                mReq->req.status = -1;
+
+        mReq->req.actual   = mReq->ptr->token & TD_TOTAL_BYTES;
+        mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
+        mReq->req.actual   = mReq->req.length - mReq->req.actual;
+        mReq->req.actual   = mReq->req.status ? 0 : mReq->req.actual;
+
+        return mReq->req.actual;
+}
+
+/**
+ * _ep_nuke: dequeues all endpoint requests
+ * @mEp: endpoint
+ *
+ * This function returns an error code
+ * Caller must hold lock
+ */
+static int _ep_nuke(struct ci13xxx_ep *mEp)
+__releases(mEp->lock)
+__acquires(mEp->lock)
+{
+        trace("%p", mEp);
+
+        if (mEp == NULL)
+                return -EINVAL;
+
+        hw_ep_flush(mEp->num, mEp->dir);
+
+        while (!list_empty(&mEp->qh[mEp->dir].queue)) {
+
+                /* pop oldest request */
+                struct ci13xxx_req *mReq = \
+                        list_entry(mEp->qh[mEp->dir].queue.next,
+                                   struct ci13xxx_req, queue);
+                list_del_init(&mReq->queue);
+                mReq->req.status = -ESHUTDOWN;
+
+                if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
+                        spin_unlock(mEp->lock);
+                        mReq->req.complete(&mEp->ep, &mReq->req);
+                        spin_lock(mEp->lock);
+                }
+        }
+        return 0;
+}
+
+/**
+ * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
+ * @gadget: gadget
+ *
+ * This function returns an error code
+ * Caller must hold lock
+ */
+static int _gadget_stop_activity(struct usb_gadget *gadget)
+__releases(udc->lock)
+__acquires(udc->lock)
+{
+        struct usb_ep *ep;
+        struct ci13xxx    *udc = container_of(gadget, struct ci13xxx, gadget);
+        struct ci13xxx_ep *mEp = container_of(gadget->ep0,
+                                              struct ci13xxx_ep, ep);
+
+        trace("%p", gadget);
+
+        if (gadget == NULL)
+                return -EINVAL;
+
+        spin_unlock(udc->lock);
+
+        /* flush all endpoints */
+        gadget_for_each_ep(ep, gadget) {
+                usb_ep_fifo_flush(ep);
+        }
+        usb_ep_fifo_flush(gadget->ep0);
+
+        udc->driver->disconnect(gadget);
+
+        /* make sure to disable all endpoints */
+        gadget_for_each_ep(ep, gadget) {
+                usb_ep_disable(ep);
+        }
+        usb_ep_disable(gadget->ep0);
+
+        if (mEp->status != NULL) {
+                usb_ep_free_request(gadget->ep0, mEp->status);
+                mEp->status = NULL;
+        }
+
+        spin_lock(udc->lock);
+
+        return 0;
+}
+
+/******************************************************************************
+ * ISR block
+ *****************************************************************************/
+/**
+ * isr_reset_handler: USB reset interrupt handler
+ * @udc: UDC device
+ *
+ * This function resets USB engine after a bus reset occurred
+ */
+static void isr_reset_handler(struct ci13xxx *udc)
+__releases(udc->lock)
+__acquires(udc->lock)
+{
+        struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[0];
+        int retval;
+
+        trace("%p", udc);
+
+        if (udc == NULL) {
+                err("EINVAL");
+                return;
+        }
+
+        dbg_event(0xFF, "BUS RST", 0);
+
+        retval = _gadget_stop_activity(&udc->gadget);
+        if (retval)
+                goto done;
+
+        retval = hw_usb_reset();
+        if (retval)
+                goto done;
+
+        spin_unlock(udc->lock);
+        retval = usb_ep_enable(&mEp->ep, &ctrl_endpt_desc);
+        if (!retval) {
+                mEp->status = usb_ep_alloc_request(&mEp->ep, GFP_KERNEL);
+                if (mEp->status == NULL) {
+                        usb_ep_disable(&mEp->ep);
+                        retval = -ENOMEM;
+                }
+        }
+        spin_lock(udc->lock);
+
+ done:
+        if (retval)
+                err("error: %i", retval);
+}
+
+/**
+ * isr_get_status_complete: get_status request complete function
+ * @ep:  endpoint
+ * @req: request handled
+ *
+ * Caller must release lock
+ */
+static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
+{
+        trace("%p, %p", ep, req);
+
+        if (ep == NULL || req == NULL) {
+                err("EINVAL");
+                return;
+        }
+
+        kfree(req->buf);
+        usb_ep_free_request(ep, req);
+}
+
+/**
+ * isr_get_status_response: get_status request response
+ * @ep:    endpoint
+ * @setup: setup request packet
+ *
+ * This function returns an error code
+ */
+static int isr_get_status_response(struct ci13xxx_ep *mEp,
+                                   struct usb_ctrlrequest *setup)
+__releases(mEp->lock)
+__acquires(mEp->lock)
+{
+        struct usb_request *req = NULL;
+        gfp_t gfp_flags = GFP_ATOMIC;
+        int dir, num, retval;
+
+        trace("%p, %p", mEp, setup);
+
+        if (mEp == NULL || setup == NULL)
+                return -EINVAL;
+
+        spin_unlock(mEp->lock);
+        req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
+        spin_lock(mEp->lock);
+        if (req == NULL)
+                return -ENOMEM;
+
+        req->complete = isr_get_status_complete;
+        req->length   = 2;
+        req->buf      = kzalloc(req->length, gfp_flags);
+        if (req->buf == NULL) {
+                retval = -ENOMEM;
+                goto err_free_req;
+        }
+
+        if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+                /* TODO: D1 - Remote Wakeup; D0 - Self Powered */
+                retval = 0;
+        } else if ((setup->bRequestType & USB_RECIP_MASK) \
+                   == USB_RECIP_ENDPOINT) {
+                dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
+                        TX : RX;
+                num =  le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
+                *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
+        }
+        /* else do nothing; reserved for future use */
+
+        spin_unlock(mEp->lock);
+        retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
+        spin_lock(mEp->lock);
+        if (retval)
+                goto err_free_buf;
+
+        return 0;
+
+ err_free_buf:
+        kfree(req->buf);
+ err_free_req:
+        spin_unlock(mEp->lock);
+        usb_ep_free_request(&mEp->ep, req);
+        spin_lock(mEp->lock);
+        return retval;
+}
+
+/**
+ * isr_setup_status_phase: queues the status phase of a setup transation
+ * @mEp: endpoint
+ *
+ * This function returns an error code
+ */
+static int isr_setup_status_phase(struct ci13xxx_ep *mEp)
+__releases(mEp->lock)
+__acquires(mEp->lock)
+{
+        int retval;
+
+        trace("%p", mEp);
+
+        /* mEp is always valid & configured */
+
+        if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+                mEp->dir = (mEp->dir == TX) ? RX : TX;
+
+        mEp->status->no_interrupt = 1;
+
+        spin_unlock(mEp->lock);
+        retval = usb_ep_queue(&mEp->ep, mEp->status, GFP_ATOMIC);
+        spin_lock(mEp->lock);
+
+        return retval;
+}
+
+/**
+ * isr_tr_complete_low: transaction complete low level handler
+ * @mEp: endpoint
+ *
+ * This function returns an error code
+ * Caller must hold lock
+ */
+static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
+__releases(mEp->lock)
+__acquires(mEp->lock)
+{
+        struct ci13xxx_req *mReq;
+        int retval;
+
+        trace("%p", mEp);
+
+        if (list_empty(&mEp->qh[mEp->dir].queue))
+                return -EINVAL;
+
+        /* pop oldest request */
+        mReq = list_entry(mEp->qh[mEp->dir].queue.next,
+                          struct ci13xxx_req, queue);
+        list_del_init(&mReq->queue);
+
+        retval = _hardware_dequeue(mEp, mReq);
+        if (retval < 0) {
+                dbg_event(_usb_addr(mEp), "DONE", retval);
+                goto done;
+        }
+
+        dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
+
+        if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
+                spin_unlock(mEp->lock);
+                mReq->req.complete(&mEp->ep, &mReq->req);
+                spin_lock(mEp->lock);
+        }
+
+        if (!list_empty(&mEp->qh[mEp->dir].queue)) {
+                mReq = list_entry(mEp->qh[mEp->dir].queue.next,
+                                  struct ci13xxx_req, queue);
+                _hardware_enqueue(mEp, mReq);
+        }
+
+ done:
+        return retval;
+}
+
+/**
+ * isr_tr_complete_handler: transaction complete interrupt handler
+ * @udc: UDC descriptor
+ *
+ * This function handles traffic events
+ */
+static void isr_tr_complete_handler(struct ci13xxx *udc)
+__releases(udc->lock)
+__acquires(udc->lock)
+{
+        unsigned i;
+
+        trace("%p", udc);
+
+        if (udc == NULL) {
+                err("EINVAL");
+                return;
+        }
+
+        for (i = 0; i < hw_ep_max; i++) {
+                struct ci13xxx_ep *mEp  = &udc->ci13xxx_ep[i];
+                int type, num, err = -EINVAL;
+                struct usb_ctrlrequest req;
+
+
+                if (mEp->desc == NULL)
+                        continue;   /* not configured */
+
+                if ((mEp->dir == RX && hw_test_and_clear_complete(i)) ||
+                    (mEp->dir == TX && hw_test_and_clear_complete(i + 16))) {
+                        err = isr_tr_complete_low(mEp);
+                        if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
+                                if (err > 0)   /* needs status phase */
+                                        err = isr_setup_status_phase(mEp);
+                                if (err < 0) {
+                                        dbg_event(_usb_addr(mEp),
+                                                  "ERROR", err);
+                                        spin_unlock(udc->lock);
+                                        if (usb_ep_set_halt(&mEp->ep))
+                                                err("error: ep_set_halt");
+                                        spin_lock(udc->lock);
+                                }
+                        }
+                }
+
+                if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
+                    !hw_test_and_clear_setup_status(i))
+                        continue;
+
+                if (i != 0) {
+                        warn("ctrl traffic received at endpoint");
+                        continue;
+                }
+
+                /* read_setup_packet */
+                do {
+                        hw_test_and_set_setup_guard();
+                        memcpy(&req, &mEp->qh[RX].ptr->setup, sizeof(req));
+                } while (!hw_test_and_clear_setup_guard());
+
+                type = req.bRequestType;
+
+                mEp->dir = (type & USB_DIR_IN) ? TX : RX;
+
+                dbg_setup(_usb_addr(mEp), &req);
+
+                switch (req.bRequest) {
+                case USB_REQ_CLEAR_FEATURE:
+                        if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
+                            le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
+                                goto delegate;
+                        if (req.wLength != 0)
+                                break;
+                        num  = le16_to_cpu(req.wIndex);
+                        num &= USB_ENDPOINT_NUMBER_MASK;
+                        if (!udc->ci13xxx_ep[num].wedge) {
+                                spin_unlock(udc->lock);
+                                err = usb_ep_clear_halt(
+                                        &udc->ci13xxx_ep[num].ep);
+                                spin_lock(udc->lock);
+                                if (err)
+                                        break;
+                        }
+                        err = isr_setup_status_phase(mEp);
+                        break;
+                case USB_REQ_GET_STATUS:
+                        if (type != (USB_DIR_IN|USB_RECIP_DEVICE)   &&
+                            type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
+                            type != (USB_DIR_IN|USB_RECIP_INTERFACE))
+                                goto delegate;
+                        if (le16_to_cpu(req.wLength) != 2 ||
+                            le16_to_cpu(req.wValue)  != 0)
+                                break;
+                        err = isr_get_status_response(mEp, &req);
+                        break;
+                case USB_REQ_SET_ADDRESS:
+                        if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
+                                goto delegate;
+                        if (le16_to_cpu(req.wLength) != 0 ||
+                            le16_to_cpu(req.wIndex)  != 0)
+                                break;
+                        err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
+                        if (err)
+                                break;
+                        err = isr_setup_status_phase(mEp);
+                        break;
+                case USB_REQ_SET_FEATURE:
+                        if (type != (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
+                            le16_to_cpu(req.wValue) != USB_ENDPOINT_HALT)
+                                goto delegate;
+                        if (req.wLength != 0)
+                                break;
+                        num  = le16_to_cpu(req.wIndex);
+                        num &= USB_ENDPOINT_NUMBER_MASK;
+
+                        spin_unlock(udc->lock);
+                        err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
+                        spin_lock(udc->lock);
+                        if (err)
+                                break;
+                        err = isr_setup_status_phase(mEp);
+                        break;
+                default:
+delegate:
+                        if (req.wLength == 0)   /* no data phase */
+                                mEp->dir = TX;
+
+                        spin_unlock(udc->lock);
+                        err = udc->driver->setup(&udc->gadget, &req);
+                        spin_lock(udc->lock);
+                        break;
+                }
+
+                if (err < 0) {
+                        dbg_event(_usb_addr(mEp), "ERROR", err);
+
+                        spin_unlock(udc->lock);
+                        if (usb_ep_set_halt(&mEp->ep))
+                                err("error: ep_set_halt");
+                        spin_lock(udc->lock);
+                }
+        }
+}
+
+/******************************************************************************
+ * ENDPT block
+ *****************************************************************************/
+/**
+ * ep_enable: configure endpoint, making it usable
+ *
+ * Check usb_ep_enable() at "usb_gadget.h" for details
+ */
+static int ep_enable(struct usb_ep *ep,
+                     const struct usb_endpoint_descriptor *desc)
+{
+        struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+        int direction, retval = 0;
+        unsigned long flags;
+
+        trace("%p, %p", ep, desc);
+
+        if (ep == NULL || desc == NULL)
+                return -EINVAL;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        /* only internal SW should enable ctrl endpts */
+
+        mEp->desc = desc;
+
+        if (!list_empty(&mEp->qh[mEp->dir].queue))
+                warn("enabling a non-empty endpoint!");
+
+        mEp->dir  = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? TX : RX;
+        mEp->num  =  desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+        mEp->type =  desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+
+        mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
+
+        direction = mEp->dir;
+        do {
+                dbg_event(_usb_addr(mEp), "ENABLE", 0);
+
+                if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+                        mEp->qh[mEp->dir].ptr->cap |=  QH_IOS;
+                else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
+                        mEp->qh[mEp->dir].ptr->cap &= ~QH_MULT;
+                else
+                        mEp->qh[mEp->dir].ptr->cap &= ~QH_ZLT;
+
+                mEp->qh[mEp->dir].ptr->cap |=
+                        (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
+                mEp->qh[mEp->dir].ptr->td.next |= TD_TERMINATE;   /* needed? */
+
+                retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
+
+                if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+                        mEp->dir = (mEp->dir == TX) ? RX : TX;
+
+        } while (mEp->dir != direction);
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+        return retval;
+}
+
+/**
+ * ep_disable: endpoint is no longer usable
+ *
+ * Check usb_ep_disable() at "usb_gadget.h" for details
+ */
+static int ep_disable(struct usb_ep *ep)
+{
+        struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+        int direction, retval = 0;
+        unsigned long flags;
+
+        trace("%p", ep);
+
+        if (ep == NULL)
+                return -EINVAL;
+        else if (mEp->desc == NULL)
+                return -EBUSY;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        /* only internal SW should disable ctrl endpts */
+
+        direction = mEp->dir;
+        do {
+                dbg_event(_usb_addr(mEp), "DISABLE", 0);
+
+                retval |= _ep_nuke(mEp);
+                retval |= hw_ep_disable(mEp->num, mEp->dir);
+
+                if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+                        mEp->dir = (mEp->dir == TX) ? RX : TX;
+
+        } while (mEp->dir != direction);
+
+        mEp->desc = NULL;
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+        return retval;
+}
+
+/**
+ * ep_alloc_request: allocate a request object to use with this endpoint
+ *
+ * Check usb_ep_alloc_request() at "usb_gadget.h" for details
+ */
+static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
+{
+        struct ci13xxx_ep  *mEp  = container_of(ep, struct ci13xxx_ep, ep);
+        struct ci13xxx_req *mReq = NULL;
+        unsigned long flags;
+
+        trace("%p, %i", ep, gfp_flags);
+
+        if (ep == NULL) {
+                err("EINVAL");
+                return NULL;
+        }
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
+        if (mReq != NULL) {
+                INIT_LIST_HEAD(&mReq->queue);
+
+                mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
+                                           &mReq->dma);
+                if (mReq->ptr == NULL) {
+                        kfree(mReq);
+                        mReq = NULL;
+                }
+        }
+
+        dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+
+        return (mReq == NULL) ? NULL : &mReq->req;
+}
+
+/**
+ * ep_free_request: frees a request object
+ *
+ * Check usb_ep_free_request() at "usb_gadget.h" for details
+ */
+static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
+{
+        struct ci13xxx_ep  *mEp  = container_of(ep,  struct ci13xxx_ep, ep);
+        struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
+        unsigned long flags;
+
+        trace("%p, %p", ep, req);
+
+        if (ep == NULL || req == NULL) {
+                err("EINVAL");
+                return;
+        } else if (!list_empty(&mReq->queue)) {
+                err("EBUSY");
+                return;
+        }
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        if (mReq->ptr)
+                dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
+        kfree(mReq);
+
+        dbg_event(_usb_addr(mEp), "FREE", 0);
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+}
+
+/**
+ * ep_queue: queues (submits) an I/O request to an endpoint
+ *
+ * Check usb_ep_queue()* at usb_gadget.h" for details
+ */
+static int ep_queue(struct usb_ep *ep, struct usb_request *req,
+                    gfp_t __maybe_unused gfp_flags)
+{
+        struct ci13xxx_ep  *mEp  = container_of(ep,  struct ci13xxx_ep, ep);
+        struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
+        int retval = 0;
+        unsigned long flags;
+
+        trace("%p, %p, %X", ep, req, gfp_flags);
+
+        if (ep == NULL || req == NULL || mEp->desc == NULL)
+                return -EINVAL;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
+            !list_empty(&mEp->qh[mEp->dir].queue)) {
+                _ep_nuke(mEp);
+                retval = -EOVERFLOW;
+                warn("endpoint ctrl %X nuked", _usb_addr(mEp));
+        }
+
+        /* first nuke then test link, e.g. previous status has not sent */
+        if (!list_empty(&mReq->queue)) {
+                retval = -EBUSY;
+                err("request already in queue");
+                goto done;
+        }
+
+        if (req->length > (4 * PAGE_SIZE)) {
+                req->length = (4 * PAGE_SIZE);
+                retval = -EMSGSIZE;
+                warn("request length truncated");
+        }
+
+        dbg_queue(_usb_addr(mEp), req, retval);
+
+        /* push request */
+        mReq->req.status = -EINPROGRESS;
+        mReq->req.actual = 0;
+        list_add_tail(&mReq->queue, &mEp->qh[mEp->dir].queue);
+
+        retval = _hardware_enqueue(mEp, mReq);
+        if (retval == -EALREADY || retval == -EBUSY) {
+                dbg_event(_usb_addr(mEp), "QUEUE", retval);
+                retval = 0;
+        }
+
+ done:
+        spin_unlock_irqrestore(mEp->lock, flags);
+        return retval;
+}
+
+/**
+ * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
+ *
+ * Check usb_ep_dequeue() at "usb_gadget.h" for details
+ */
+static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+        struct ci13xxx_ep  *mEp  = container_of(ep,  struct ci13xxx_ep, ep);
+        struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
+        unsigned long flags;
+
+        trace("%p, %p", ep, req);
+
+        if (ep == NULL || req == NULL || mEp->desc == NULL ||
+            list_empty(&mReq->queue)  || list_empty(&mEp->qh[mEp->dir].queue))
+                return -EINVAL;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
+
+        if (mReq->req.status == -EALREADY)
+                _hardware_dequeue(mEp, mReq);
+
+        /* pop request */
+        list_del_init(&mReq->queue);
+        req->status = -ECONNRESET;
+
+        if (!mReq->req.no_interrupt && mReq->req.complete != NULL) {
+                spin_unlock(mEp->lock);
+                mReq->req.complete(&mEp->ep, &mReq->req);
+                spin_lock(mEp->lock);
+        }
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+        return 0;
+}
+
+/**
+ * ep_set_halt: sets the endpoint halt feature
+ *
+ * Check usb_ep_set_halt() at "usb_gadget.h" for details
+ */
+static int ep_set_halt(struct usb_ep *ep, int value)
+{
+        struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+        int direction, retval = 0;
+        unsigned long flags;
+
+        trace("%p, %i", ep, value);
+
+        if (ep == NULL || mEp->desc == NULL)
+                return -EINVAL;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+#ifndef STALL_IN
+        /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
+        if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
+            !list_empty(&mEp->qh[mEp->dir].queue)) {
+                spin_unlock_irqrestore(mEp->lock, flags);
+                return -EAGAIN;
+        }
+#endif
+
+        direction = mEp->dir;
+        do {
+                dbg_event(_usb_addr(mEp), "HALT", value);
+                retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
+
+                if (!value)
+                        mEp->wedge = 0;
+
+                if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+                        mEp->dir = (mEp->dir == TX) ? RX : TX;
+
+        } while (mEp->dir != direction);
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+        return retval;
+}
+
+/**
+ * ep_set_wedge: sets the halt feature and ignores clear requests
+ *
+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
+ */
+static int ep_set_wedge(struct usb_ep *ep)
+{
+        struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+        unsigned long flags;
+
+        trace("%p", ep);
+
+        if (ep == NULL || mEp->desc == NULL)
+                return -EINVAL;
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        dbg_event(_usb_addr(mEp), "WEDGE", 0);
+        mEp->wedge = 1;
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+
+        return usb_ep_set_halt(ep);
+}
+
+/**
+ * ep_fifo_flush: flushes contents of a fifo
+ *
+ * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
+ */
+static void ep_fifo_flush(struct usb_ep *ep)
+{
+        struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+        unsigned long flags;
+
+        trace("%p", ep);
+
+        if (ep == NULL) {
+                err("%02X: -EINVAL", _usb_addr(mEp));
+                return;
+        }
+
+        spin_lock_irqsave(mEp->lock, flags);
+
+        dbg_event(_usb_addr(mEp), "FFLUSH", 0);
+        hw_ep_flush(mEp->num, mEp->dir);
+
+        spin_unlock_irqrestore(mEp->lock, flags);
+}
+
+/**
+ * Endpoint-specific part of the API to the USB controller hardware
+ * Check "usb_gadget.h" for details
+ */
+static const struct usb_ep_ops usb_ep_ops = {
+        .enable        = ep_enable,
+        .disable       = ep_disable,
+        .alloc_request = ep_alloc_request,
+        .free_request  = ep_free_request,
+        .queue         = ep_queue,
+        .dequeue       = ep_dequeue,
+        .set_halt      = ep_set_halt,
+        .set_wedge     = ep_set_wedge,
+        .fifo_flush    = ep_fifo_flush,
+};
+
+/******************************************************************************
+ * GADGET block
+ *****************************************************************************/
+/**
+ * Device operations part of the API to the USB controller hardware,
+ * which don't involve endpoints (or i/o)
+ * Check  "usb_gadget.h" for details
+ */
+static const struct usb_gadget_ops usb_gadget_ops;
+
+/**
+ * usb_gadget_register_driver: register a gadget driver
+ *
+ * Check usb_gadget_register_driver() at "usb_gadget.h" for details
+ * Interrupts are enabled here
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+        struct ci13xxx *udc = _udc;
+        unsigned long i, k, flags;
+        int retval = -ENOMEM;
+
+        trace("%p", driver);
+
+        if (driver             == NULL ||
+            driver->bind       == NULL ||
+            driver->unbind     == NULL ||
+            driver->setup      == NULL ||
+            driver->disconnect == NULL ||
+            driver->suspend    == NULL ||
+            driver->resume     == NULL)
+                return -EINVAL;
+        else if (udc         == NULL)
+                return -ENODEV;
+        else if (udc->driver != NULL)
+                return -EBUSY;
+
+        /* alloc resources */
+        udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
+                                       sizeof(struct ci13xxx_qh),
+                                       64, PAGE_SIZE);
+        if (udc->qh_pool == NULL)
+                return -ENOMEM;
+
+        udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
+                                       sizeof(struct ci13xxx_td),
+                                       64, PAGE_SIZE);
+        if (udc->td_pool == NULL) {
+                dma_pool_destroy(udc->qh_pool);
+                udc->qh_pool = NULL;
+                return -ENOMEM;
+        }
+
+        spin_lock_irqsave(udc->lock, flags);
+
+        info("hw_ep_max = %d", hw_ep_max);
+
+        udc->driver = driver;
+        udc->gadget.ops        = NULL;
+        udc->gadget.dev.driver = NULL;
+
+        retval = 0;
+        for (i = 0; i < hw_ep_max; i++) {
+                struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
+
+                scnprintf(mEp->name, sizeof(mEp->name), "ep%i", (int)i);
+
+                mEp->lock         = udc->lock;
+                mEp->device       = &udc->gadget.dev;
+                mEp->td_pool      = udc->td_pool;
+
+                mEp->ep.name      = mEp->name;
+                mEp->ep.ops       = &usb_ep_ops;
+                mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
+
+                /* this allocation cannot be random */
+                for (k = RX; k <= TX; k++) {
+                        INIT_LIST_HEAD(&mEp->qh[k].queue);
+                        mEp->qh[k].ptr = dma_pool_alloc(udc->qh_pool,
+                                                        GFP_KERNEL,
+                                                        &mEp->qh[k].dma);
+                        if (mEp->qh[k].ptr == NULL)
+                                retval = -ENOMEM;
+                        else
+                                memset(mEp->qh[k].ptr, 0,
+                                       sizeof(*mEp->qh[k].ptr));
+                }
+                if (i == 0)
+                        udc->gadget.ep0 = &mEp->ep;
+                else
+                        list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
+        }
+        if (retval)
+                goto done;
+
+        /* bind gadget */
+        driver->driver.bus     = NULL;
+        udc->gadget.ops        = &usb_gadget_ops;
+        udc->gadget.dev.driver = &driver->driver;
+
+        spin_unlock_irqrestore(udc->lock, flags);
+        retval = driver->bind(&udc->gadget);                /* MAY SLEEP */
+        spin_lock_irqsave(udc->lock, flags);
+
+        if (retval) {
+                udc->gadget.ops        = NULL;
+                udc->gadget.dev.driver = NULL;
+                goto done;
+        }
+
+        retval = hw_device_state(udc->ci13xxx_ep[0].qh[RX].dma);
+
+ done:
+        spin_unlock_irqrestore(udc->lock, flags);
+        if (retval)
+                usb_gadget_unregister_driver(driver);
+        return retval;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+/**
+ * usb_gadget_unregister_driver: unregister a gadget driver
+ *
+ * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
+ */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+        struct ci13xxx *udc = _udc;
+        unsigned long i, k, flags;
+
+        trace("%p", driver);
+
+        if (driver             == NULL ||
+            driver->bind       == NULL ||
+            driver->unbind     == NULL ||
+            driver->setup      == NULL ||
+            driver->disconnect == NULL ||
+            driver->suspend    == NULL ||
+            driver->resume     == NULL ||
+            driver             != udc->driver)
+                return -EINVAL;
+
+        spin_lock_irqsave(udc->lock, flags);
+
+        hw_device_state(0);
+
+        /* unbind gadget */
+        if (udc->gadget.ops != NULL) {
+                _gadget_stop_activity(&udc->gadget);
+
+                spin_unlock_irqrestore(udc->lock, flags);
+                driver->unbind(&udc->gadget);               /* MAY SLEEP */
+                spin_lock_irqsave(udc->lock, flags);
+
+                udc->gadget.ops        = NULL;
+                udc->gadget.dev.driver = NULL;
+        }
+
+        /* free resources */
+        for (i = 0; i < hw_ep_max; i++) {
+                struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
+
+                if (i == 0)
+                        udc->gadget.ep0 = NULL;
+                else if (!list_empty(&mEp->ep.ep_list))
+                        list_del_init(&mEp->ep.ep_list);
+
+                for (k = RX; k <= TX; k++)
+                        if (mEp->qh[k].ptr != NULL)
+                                dma_pool_free(udc->qh_pool,
+                                              mEp->qh[k].ptr, mEp->qh[k].dma);
+        }
+
+        udc->driver = NULL;
+
+        spin_unlock_irqrestore(udc->lock, flags);
+
+        if (udc->td_pool != NULL) {
+                dma_pool_destroy(udc->td_pool);
+                udc->td_pool = NULL;
+        }
+        if (udc->qh_pool != NULL) {
+                dma_pool_destroy(udc->qh_pool);
+                udc->qh_pool = NULL;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/******************************************************************************
+ * BUS block
+ *****************************************************************************/
+/**
+ * udc_irq: global interrupt handler
+ *
+ * This function returns IRQ_HANDLED if the IRQ has been handled
+ * It locks access to registers
+ */
+static irqreturn_t udc_irq(void)
+{
+        struct ci13xxx *udc = _udc;
+        irqreturn_t retval;
+        u32 intr;
+
+        trace();
+
+        if (udc == NULL) {
+                err("ENODEV");
+                return IRQ_HANDLED;
+        }
+
+        spin_lock(udc->lock);
+        intr = hw_test_and_clear_intr_active();
+        if (intr) {
+                isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
+                isr_statistics.hndl.idx &= ISR_MASK;
+                isr_statistics.hndl.cnt++;
+
+                /* order defines priority - do NOT change it */
+                if (USBi_URI & intr) {
+                        isr_statistics.uri++;
+                        isr_reset_handler(udc);
+                }
+                if (USBi_PCI & intr) {
+                        isr_statistics.pci++;
+                        udc->gadget.speed = hw_port_is_high_speed() ?
+                                USB_SPEED_HIGH : USB_SPEED_FULL;
+                }
+                if (USBi_UEI & intr)
+                        isr_statistics.uei++;
+                if (USBi_UI  & intr) {
+                        isr_statistics.ui++;
+                        isr_tr_complete_handler(udc);
+                }
+                if (USBi_SLI & intr)
+                        isr_statistics.sli++;
+                retval = IRQ_HANDLED;
+        } else {
+                isr_statistics.none++;
+                retval = IRQ_NONE;
+        }
+        spin_unlock(udc->lock);
+
+        return retval;
+}
+
+/**
+ * udc_release: driver release function
+ * @dev: device
+ *
+ * Currently does nothing
+ */
+static void udc_release(struct device *dev)
+{
+        trace("%p", dev);
+
+        if (dev == NULL)
+                err("EINVAL");
+}
+
+/**
+ * udc_probe: parent probe must call this to initialize UDC
+ * @dev:  parent device
+ * @regs: registers base address
+ * @name: driver name
+ *
+ * This function returns an error code
+ * No interrupts active, the IRQ has not been requested yet
+ * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
+ */
+static int udc_probe(struct device *dev, void __iomem *regs, const char *name)
+{
+        struct ci13xxx *udc;
+        int retval = 0;
+
+        trace("%p, %p, %p", dev, regs, name);
+
+        if (dev == NULL || regs == NULL || name == NULL)
+                return -EINVAL;
+
+        udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
+        if (udc == NULL)
+                return -ENOMEM;
+
+        udc->lock = &udc_lock;
+
+        retval = hw_device_reset(regs);
+        if (retval)
+                goto done;
+
+        udc->gadget.ops          = NULL;
+        udc->gadget.speed        = USB_SPEED_UNKNOWN;
+        udc->gadget.is_dualspeed = 1;
+        udc->gadget.is_otg       = 0;
+        udc->gadget.name         = name;
+
+        INIT_LIST_HEAD(&udc->gadget.ep_list);
+        udc->gadget.ep0 = NULL;
+
+        strcpy(udc->gadget.dev.bus_id, "gadget");
+        udc->gadget.dev.dma_mask = dev->dma_mask;
+        udc->gadget.dev.parent   = dev;
+        udc->gadget.dev.release  = udc_release;
+
+        retval = device_register(&udc->gadget.dev);
+        if (retval)
+                goto done;
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+        retval = dbg_create_files(&udc->gadget.dev);
+#endif
+        if (retval) {
+                device_unregister(&udc->gadget.dev);
+                goto done;
+        }
+
+        _udc = udc;
+        return retval;
+
+ done:
+        err("error = %i", retval);
+        kfree(udc);
+        _udc = NULL;
+        return retval;
+}
+
+/**
+ * udc_remove: parent remove must call this to remove UDC
+ *
+ * No interrupts active, the IRQ has been released
+ */
+static void udc_remove(void)
+{
+        struct ci13xxx *udc = _udc;
+
+        if (udc == NULL) {
+                err("EINVAL");
+                return;
+        }
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+        dbg_remove_files(&udc->gadget.dev);
+#endif
+        device_unregister(&udc->gadget.dev);
+
+        kfree(udc);
+        _udc = NULL;
+}
+
+/******************************************************************************
+ * PCI block
+ *****************************************************************************/
+/**
+ * ci13xxx_pci_irq: interrut handler
+ * @irq:  irq number
+ * @pdev: USB Device Controller interrupt source
+ *
+ * This function returns IRQ_HANDLED if the IRQ has been handled
+ * This is an ISR don't trace, use attribute interface instead
+ */
+static irqreturn_t ci13xxx_pci_irq(int irq, void *pdev)
+{
+        if (irq == 0) {
+                dev_err(&((struct pci_dev *)pdev)->dev, "Invalid IRQ0 usage!");
+                return IRQ_HANDLED;
+        }
+        return udc_irq();
+}
+
+/**
+ * ci13xxx_pci_probe: PCI probe
+ * @pdev: USB device controller being probed
+ * @id:   PCI hotplug ID connecting controller to UDC framework
+ *
+ * This function returns an error code
+ * Allocates basic PCI resources for this USB device controller, and then
+ * invokes the udc_probe() method to start the UDC associated with it
+ */
+static int __devinit ci13xxx_pci_probe(struct pci_dev *pdev,
+                                       const struct pci_device_id *id)
+{
+        void __iomem *regs = NULL;
+        int retval = 0;
+
+        if (id == NULL)
+                return -EINVAL;
+
+        retval = pci_enable_device(pdev);
+        if (retval)
+                goto done;
+
+        if (!pdev->irq) {
+                dev_err(&pdev->dev, "No IRQ, check BIOS/PCI setup!");
+                retval = -ENODEV;
+                goto disable_device;
+        }
+
+        retval = pci_request_regions(pdev, UDC_DRIVER_NAME);
+        if (retval)
+                goto disable_device;
+
+        /* BAR 0 holds all the registers */
+        regs = pci_iomap(pdev, 0, 0);
+        if (!regs) {
+                dev_err(&pdev->dev, "Error mapping memory!");
+                retval = -EFAULT;
+                goto release_regions;
+        }
+        pci_set_drvdata(pdev, (__force void *)regs);
+
+        pci_set_master(pdev);
+        pci_try_set_mwi(pdev);
+
+        retval = udc_probe(&pdev->dev, regs, UDC_DRIVER_NAME);
+        if (retval)
+                goto iounmap;
+
+        /* our device does not have MSI capability */
+
+        retval = request_irq(pdev->irq, ci13xxx_pci_irq, IRQF_SHARED,
+                             UDC_DRIVER_NAME, pdev);
+        if (retval)
+                goto gadget_remove;
+
+        return 0;
+
+ gadget_remove:
+        udc_remove();
+ iounmap:
+        pci_iounmap(pdev, regs);
+ release_regions:
+        pci_release_regions(pdev);
+ disable_device:
+        pci_disable_device(pdev);
+ done:
+        return retval;
+}
+
+/**
+ * ci13xxx_pci_remove: PCI remove
+ * @pdev: USB Device Controller being removed
+ *
+ * Reverses the effect of ci13xxx_pci_probe(),
+ * first invoking the udc_remove() and then releases
+ * all PCI resources allocated for this USB device controller
+ */
+static void __devexit ci13xxx_pci_remove(struct pci_dev *pdev)
+{
+        free_irq(pdev->irq, pdev);
+        udc_remove();
+        pci_iounmap(pdev, (__force void __iomem *)pci_get_drvdata(pdev));
+        pci_release_regions(pdev);
+        pci_disable_device(pdev);
+}
+
+/**
+ * PCI device table
+ * PCI device structure
+ *
+ * Check "pci.h" for details
+ */
+static DEFINE_PCI_DEVICE_TABLE(ci13xxx_pci_id_table) = {
+        { PCI_DEVICE(0x153F, 0x1004) },
+        { PCI_DEVICE(0x153F, 0x1006) },
+        { 0, 0, 0, 0, 0, 0, 0 /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, ci13xxx_pci_id_table);
+
+static struct pci_driver ci13xxx_pci_driver = {
+        .name         = UDC_DRIVER_NAME,
+        .id_table     = ci13xxx_pci_id_table,
+        .probe        = ci13xxx_pci_probe,
+        .remove       = __devexit_p(ci13xxx_pci_remove),
+};
+
+/**
+ * ci13xxx_pci_init: module init
+ *
+ * Driver load
+ */
+static int __init ci13xxx_pci_init(void)
+{
+        return pci_register_driver(&ci13xxx_pci_driver);
+}
+module_init(ci13xxx_pci_init);
+
+/**
+ * ci13xxx_pci_exit: module exit
+ *
+ * Driver unload
+ */
+static void __exit ci13xxx_pci_exit(void)
+{
+        pci_unregister_driver(&ci13xxx_pci_driver);
+}
+module_exit(ci13xxx_pci_exit);
+
+MODULE_AUTHOR("MIPS - David Lopo <dlopo@chipidea.mips.com>");
+MODULE_DESCRIPTION("MIPS CI13XXX USB Peripheral Controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("June 2008");
diff --git a/drivers/usb/gadget/ci13xxx_udc.h b/drivers/usb/gadget/ci13xxx_udc.h
new file mode 100644
index 000000000000..4026e9cede34
--- /dev/null
+++ b/drivers/usb/gadget/ci13xxx_udc.h
@@ -0,0 +1,195 @@
+/*
+ * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
+ *
+ * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
+ *
+ * Author: David Lopo
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Description: MIPS USB IP core family device controller
+ *              Structures, registers and logging macros
+ */
+
+#ifndef _CI13XXX_h_
+#define _CI13XXX_h_
+
+/******************************************************************************
+ * DEFINE
+ *****************************************************************************/
+#define ENDPT_MAX          (16)
+#define CTRL_PAYLOAD_MAX   (64)
+#define RX        (0)  /* similar to USB_DIR_OUT but can be used as an index */
+#define TX        (1)  /* similar to USB_DIR_IN  but can be used as an index */
+
+/******************************************************************************
+ * STRUCTURES
+ *****************************************************************************/
+/* DMA layout of transfer descriptors */
+struct ci13xxx_td {
+        /* 0 */
+        u32 next;
+#define TD_TERMINATE          BIT(0)
+        /* 1 */
+        u32 token;
+#define TD_STATUS             (0x00FFUL <<  0)
+#define TD_STATUS_TR_ERR      BIT(3)
+#define TD_STATUS_DT_ERR      BIT(5)
+#define TD_STATUS_HALTED      BIT(6)
+#define TD_STATUS_ACTIVE      BIT(7)
+#define TD_MULTO              (0x0003UL << 10)
+#define TD_IOC                BIT(15)
+#define TD_TOTAL_BYTES        (0x7FFFUL << 16)
+        /* 2 */
+        u32 page[5];
+#define TD_CURR_OFFSET        (0x0FFFUL <<  0)
+#define TD_FRAME_NUM          (0x07FFUL <<  0)
+#define TD_RESERVED_MASK      (0x0FFFUL <<  0)
+} __attribute__ ((packed));
+
+/* DMA layout of queue heads */
+struct ci13xxx_qh {
+        /* 0 */
+        u32 cap;
+#define QH_IOS                BIT(15)
+#define QH_MAX_PKT            (0x07FFUL << 16)
+#define QH_ZLT                BIT(29)
+#define QH_MULT               (0x0003UL << 30)
+        /* 1 */
+        u32 curr;
+        /* 2 - 8 */
+        struct ci13xxx_td        td;
+        /* 9 */
+        u32 RESERVED;
+        struct usb_ctrlrequest   setup;
+} __attribute__ ((packed));
+
+/* Extension of usb_request */
+struct ci13xxx_req {
+        struct usb_request   req;
+        unsigned             map;
+        struct list_head     queue;
+        struct ci13xxx_td   *ptr;
+        dma_addr_t           dma;
+};
+
+/* Extension of usb_ep */
+struct ci13xxx_ep {
+        struct usb_ep                          ep;
+        const struct usb_endpoint_descriptor  *desc;
+        u8                                     dir;
+        u8                                     num;
+        u8                                     type;
+        char                                   name[16];
+        struct {
+                struct list_head   queue;
+                struct ci13xxx_qh *ptr;
+                dma_addr_t         dma;
+        }                                      qh[2];
+        struct usb_request                    *status;
+        int                                    wedge;
+
+        /* global resources */
+        spinlock_t                            *lock;
+        struct device                         *device;
+        struct dma_pool                       *td_pool;
+};
+
+/* CI13XXX UDC descriptor & global resources */
+struct ci13xxx {
+        spinlock_t                *lock;      /* ctrl register bank access */
+
+        struct dma_pool           *qh_pool;   /* DMA pool for queue heads */
+        struct dma_pool           *td_pool;   /* DMA pool for transfer descs */
+
+        struct usb_gadget          gadget;     /* USB slave device */
+        struct ci13xxx_ep          ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
+
+        struct usb_gadget_driver  *driver;     /* 3rd party gadget driver */
+};
+
+/******************************************************************************
+ * REGISTERS
+ *****************************************************************************/
+/* register size */
+#define REG_BITS   (32)
+
+/* HCCPARAMS */
+#define HCCPARAMS_LEN         BIT(17)
+
+/* DCCPARAMS */
+#define DCCPARAMS_DEN         (0x1F << 0)
+#define DCCPARAMS_DC          BIT(7)
+
+/* TESTMODE */
+#define TESTMODE_FORCE        BIT(0)
+
+/* USBCMD */
+#define USBCMD_RS             BIT(0)
+#define USBCMD_RST            BIT(1)
+#define USBCMD_SUTW           BIT(13)
+
+/* USBSTS & USBINTR */
+#define USBi_UI               BIT(0)
+#define USBi_UEI              BIT(1)
+#define USBi_PCI              BIT(2)
+#define USBi_URI              BIT(6)
+#define USBi_SLI              BIT(8)
+
+/* DEVICEADDR */
+#define DEVICEADDR_USBADRA    BIT(24)
+#define DEVICEADDR_USBADR     (0x7FUL << 25)
+
+/* PORTSC */
+#define PORTSC_SUSP           BIT(7)
+#define PORTSC_HSP            BIT(9)
+#define PORTSC_PTC            (0x0FUL << 16)
+
+/* DEVLC */
+#define DEVLC_PSPD            (0x03UL << 25)
+#define    DEVLC_PSPD_HS      (0x02UL << 25)
+
+/* USBMODE */
+#define USBMODE_CM            (0x03UL <<  0)
+#define    USBMODE_CM_IDLE    (0x00UL <<  0)
+#define    USBMODE_CM_DEVICE  (0x02UL <<  0)
+#define    USBMODE_CM_HOST    (0x03UL <<  0)
+#define USBMODE_SLOM          BIT(3)
+
+/* ENDPTCTRL */
+#define ENDPTCTRL_RXS         BIT(0)
+#define ENDPTCTRL_RXT         (0x03UL <<  2)
+#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
+#define ENDPTCTRL_RXE         BIT(7)
+#define ENDPTCTRL_TXS         BIT(16)
+#define ENDPTCTRL_TXT         (0x03UL << 18)
+#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
+#define ENDPTCTRL_TXE         BIT(23)
+
+/******************************************************************************
+ * LOGGING
+ *****************************************************************************/
+#define ci13xxx_printk(level, format, args...) \
+do { \
+        if (_udc == NULL) \
+                printk(level "[%s] " format "\n", __func__, ## args); \
+        else \
+                dev_printk(level, _udc->gadget.dev.parent, \
+                           "[%s] " format "\n", __func__, ## args); \
+} while (0)
+
+#define err(format, args...)    ci13xxx_printk(KERN_ERR, format, ## args)
+#define warn(format, args...)   ci13xxx_printk(KERN_WARNING, format, ## args)
+#define info(format, args...)   ci13xxx_printk(KERN_INFO, format, ## args)
+
+#ifdef TRACE
+#define trace(format, args...)      ci13xxx_printk(KERN_DEBUG, format, ## args)
+#define dbg_trace(format, args...)  dev_dbg(dev, format, ##args)
+#else
+#define trace(format, args...)      do {} while (0)
+#define dbg_trace(format, args...)  do {} while (0)
+#endif
+
+#endif  /* _CI13XXX_h_ */
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 9462e30192d8..a36b1175b18d 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -161,7 +161,7 @@ ep_matches (
         /* report address */
         desc->bEndpointAddress &= USB_DIR_IN;
         if (isdigit (ep->name [2])) {
-                u8      num = simple_strtol (&ep->name [2], NULL, 10);
+                u8      num = simple_strtoul (&ep->name [2], NULL, 10);
                 desc->bEndpointAddress |= num;
 #ifdef  MANY_ENDPOINTS
         } else if (desc->bEndpointAddress & USB_DIR_IN) {
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 2e71368f45b4..b10fa31cc915 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -1,7 +1,7 @@
 /*
  * file_storage.c -- File-backed USB Storage Gadget, for USB development
  *
- * Copyright (C) 2003-2007 Alan Stern
+ * Copyright (C) 2003-2008 Alan Stern
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -38,16 +38,17 @@
 
 /*
  * The File-backed Storage Gadget acts as a USB Mass Storage device,
- * appearing to the host as a disk drive.  In addition to providing an
- * example of a genuinely useful gadget driver for a USB device, it also
- * illustrates a technique of double-buffering for increased throughput.
- * Last but not least, it gives an easy way to probe the behavior of the
- * Mass Storage drivers in a USB host.
+ * appearing to the host as a disk drive or as a CD-ROM drive.  In addition
+ * to providing an example of a genuinely useful gadget driver for a USB
+ * device, it also illustrates a technique of double-buffering for increased
+ * throughput.  Last but not least, it gives an easy way to probe the
+ * behavior of the Mass Storage drivers in a USB host.
  *
  * Backing storage is provided by a regular file or a block device, specified
  * by the "file" module parameter.  Access can be limited to read-only by
- * setting the optional "ro" module parameter.  The gadget will indicate that
- * it has removable media if the optional "removable" module parameter is set.
+ * setting the optional "ro" module parameter.  (For CD-ROM emulation,
+ * access is always read-only.)  The gadget will indicate that it has
+ * removable media if the optional "removable" module parameter is set.
  *
  * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
  * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
@@ -64,7 +65,12 @@
  * The default number of LUNs is taken from the number of "file" elements;
  * it is 1 if "file" is not given.  If "removable" is not set then a backing
  * file must be specified for each LUN.  If it is set, then an unspecified
- * or empty backing filename means the LUN's medium is not loaded.
+ * or empty backing filename means the LUN's medium is not loaded.  Ideally
+ * each LUN would be settable independently as a disk drive or a CD-ROM
+ * drive, but currently all LUNs have to be the same type.  The CD-ROM
+ * emulation includes a single data track and no audio tracks; hence there
+ * need be only one backing file per LUN.  Note also that the CD-ROM block
+ * length is set to 512 rather than the more common value 2048.
  *
  * Requirements are modest; only a bulk-in and a bulk-out endpoint are
  * needed (an interrupt-out endpoint is also needed for CBI).  The memory
@@ -91,6 +97,8 @@
  *                                      USB device controller (usually true),
  *                                      boolean to permit the driver to halt
  *                                      bulk endpoints
+ *      cdrom                   Default false, boolean for whether to emulate
+ *                                      a CD-ROM drive
  *      transport=XXX           Default BBB, transport name (CB, CBI, or BBB)
  *      protocol=YYY            Default SCSI, protocol name (RBC, 8020 or
  *                                      ATAPI, QIC, UFI, 8070, or SCSI;
@@ -103,15 +111,16 @@
  *                                      PAGE_CACHE_SIZE)
  *
  * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "ro",
- * "removable", "luns", and "stall" options are available; default values
- * are used for everything else.
+ * "removable", "luns", "stall", and "cdrom" options are available; default
+ * values are used for everything else.
  *
  * The pathnames of the backing files and the ro settings are available in
  * the attribute files "file" and "ro" in the lun<n> subdirectory of the
  * gadget's sysfs directory.  If the "removable" option is set, writing to
  * these files will simulate ejecting/loading the medium (writing an empty
  * line means eject) and adjusting a write-enable tab.  Changes to the ro
- * setting are not allowed when the medium is loaded.
+ * setting are not allowed when the medium is loaded or if CD-ROM emulation
+ * is being used.
  *
  * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
  * The driver's SCSI command interface was based on the "Information
@@ -261,7 +270,7 @@
 
 #define DRIVER_DESC             "File-backed Storage Gadget"
 #define DRIVER_NAME             "g_file_storage"
-#define DRIVER_VERSION          "7 August 2007"
+#define DRIVER_VERSION          "20 November 2008"
 
 static const char longname[] = DRIVER_DESC;
 static const char shortname[] = DRIVER_NAME;
@@ -341,6 +350,7 @@ static struct {
 
         int             removable;
         int             can_stall;
+        int             cdrom;
 
         char            *transport_parm;
         char            *protocol_parm;
@@ -359,6 +369,7 @@ static struct {
         .protocol_parm          = "SCSI",
         .removable              = 0,
         .can_stall              = 1,
+        .cdrom                  = 0,
         .vendor                 = DRIVER_VENDOR_ID,
         .product                = DRIVER_PRODUCT_ID,
         .release                = 0xffff,       // Use controller chip type
@@ -382,6 +393,9 @@ MODULE_PARM_DESC(removable, "true to simulate removable media");
 module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
 MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
 
+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
+MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
+
 
 /* In the non-TEST version, only the module parameters listed above
  * are available. */
@@ -411,6 +425,10 @@ MODULE_PARM_DESC(buflen, "I/O buffer size");
 
 /*-------------------------------------------------------------------------*/
 
+/* SCSI device types */
+#define TYPE_DISK       0x00
+#define TYPE_CDROM      0x05
+
 /* USB protocol value = the transport method */
 #define USB_PR_CBI      0x00            // Control/Bulk/Interrupt
 #define USB_PR_CB       0x01            // Control/Bulk w/o interrupt
@@ -487,6 +505,8 @@ struct interrupt_data {
 #define SC_READ_12                      0xa8
 #define SC_READ_CAPACITY                0x25
 #define SC_READ_FORMAT_CAPACITIES       0x23
+#define SC_READ_HEADER                  0x44
+#define SC_READ_TOC                     0x43
 #define SC_RELEASE                      0x17
 #define SC_REQUEST_SENSE                0x03
 #define SC_RESERVE                      0x16
@@ -2006,23 +2026,28 @@ static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
         u8      *buf = (u8 *) bh->buf;
 
         static char vendor_id[] = "Linux   ";
-        static char product_id[] = "File-Stor Gadget";
+        static char product_disk_id[] = "File-Stor Gadget";
+        static char product_cdrom_id[] = "File-CD Gadget  ";
 
         if (!fsg->curlun) {             // Unsupported LUNs are okay
                 fsg->bad_lun_okay = 1;
                 memset(buf, 0, 36);
                 buf[0] = 0x7f;          // Unsupported, no device-type
+                buf[4] = 31;            // Additional length
                 return 36;
         }
 
-        memset(buf, 0, 8);      // Non-removable, direct-access device
+        memset(buf, 0, 8);
+        buf[0] = (mod_data.cdrom ? TYPE_CDROM : TYPE_DISK);
         if (mod_data.removable)
                 buf[1] = 0x80;
         buf[2] = 2;             // ANSI SCSI level 2
         buf[3] = 2;             // SCSI-2 INQUIRY data format
         buf[4] = 31;            // Additional length
                                 // No special options
-        sprintf(buf + 8, "%-8s%-16s%04x", vendor_id, product_id,
+        sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
+                        (mod_data.cdrom ? product_cdrom_id :
+                                product_disk_id),
                         mod_data.release);
         return 36;
 }
@@ -2101,6 +2126,75 @@ static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 }
 
 
+static void store_cdrom_address(u8 *dest, int msf, u32 addr)
+{
+        if (msf) {
+                /* Convert to Minutes-Seconds-Frames */
+                addr >>= 2;             /* Convert to 2048-byte frames */
+                addr += 2*75;           /* Lead-in occupies 2 seconds */
+                dest[3] = addr % 75;    /* Frames */
+                addr /= 75;
+                dest[2] = addr % 60;    /* Seconds */
+                addr /= 60;
+                dest[1] = addr;         /* Minutes */
+                dest[0] = 0;            /* Reserved */
+        } else {
+                /* Absolute sector */
+                put_be32(dest, addr);
+        }
+}
+
+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+        struct lun      *curlun = fsg->curlun;
+        int             msf = fsg->cmnd[1] & 0x02;
+        u32             lba = get_be32(&fsg->cmnd[2]);
+        u8              *buf = (u8 *) bh->buf;
+
+        if ((fsg->cmnd[1] & ~0x02) != 0) {              /* Mask away MSF */
+                curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+                return -EINVAL;
+        }
+        if (lba >= curlun->num_sectors) {
+                curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+                return -EINVAL;
+        }
+
+        memset(buf, 0, 8);
+        buf[0] = 0x01;          /* 2048 bytes of user data, rest is EC */
+        store_cdrom_address(&buf[4], msf, lba);
+        return 8;
+}
+
+
+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+        struct lun      *curlun = fsg->curlun;
+        int             msf = fsg->cmnd[1] & 0x02;
+        int             start_track = fsg->cmnd[6];
+        u8              *buf = (u8 *) bh->buf;
+
+        if ((fsg->cmnd[1] & ~0x02) != 0 ||              /* Mask away MSF */
+                        start_track > 1) {
+                curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+                return -EINVAL;
+        }
+
+        memset(buf, 0, 20);
+        buf[1] = (20-2);                /* TOC data length */
+        buf[2] = 1;                     /* First track number */
+        buf[3] = 1;                     /* Last track number */
+        buf[5] = 0x16;                  /* Data track, copying allowed */
+        buf[6] = 0x01;                  /* Only track is number 1 */
+        store_cdrom_address(&buf[8], msf, 0);
+
+        buf[13] = 0x16;                 /* Lead-out track is data */
+        buf[14] = 0xAA;                 /* Lead-out track number */
+        store_cdrom_address(&buf[16], msf, curlun->num_sectors);
+        return 20;
+}
+
+
 static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 {
         struct lun      *curlun = fsg->curlun;
@@ -2848,6 +2942,26 @@ static int do_scsi_command(struct fsg_dev *fsg)
                         reply = do_read_capacity(fsg, bh);
                 break;
 
+        case SC_READ_HEADER:
+                if (!mod_data.cdrom)
+                        goto unknown_cmnd;
+                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+                                (3<<7) | (0x1f<<1), 1,
+                                "READ HEADER")) == 0)
+                        reply = do_read_header(fsg, bh);
+                break;
+
+        case SC_READ_TOC:
+                if (!mod_data.cdrom)
+                        goto unknown_cmnd;
+                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+                                (7<<6) | (1<<1), 1,
+                                "READ TOC")) == 0)
+                        reply = do_read_toc(fsg, bh);
+                break;
+
         case SC_READ_FORMAT_CAPACITIES:
                 fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
@@ -2933,6 +3047,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 // Fall through
 
         default:
+ unknown_cmnd:
                 fsg->data_size_from_cmnd = 0;
                 sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
                 if ((reply = check_command(fsg, fsg->cmnd_size,
@@ -3498,6 +3613,7 @@ static int open_backing_file(struct lun *curlun, const char *filename)
         struct inode                    *inode = NULL;
         loff_t                          size;
         loff_t                          num_sectors;
+        loff_t                          min_sectors;
 
         /* R/W if we can, R/O if we must */
         ro = curlun->ro;
@@ -3541,8 +3657,19 @@ static int open_backing_file(struct lun *curlun, const char *filename)
                 rc = (int) size;
                 goto out;
         }
-        num_sectors = size >> 9;        // File size in 512-byte sectors
-        if (num_sectors == 0) {
+        num_sectors = size >> 9;        // File size in 512-byte blocks
+        min_sectors = 1;
+        if (mod_data.cdrom) {
+                num_sectors &= ~3;      // Reduce to a multiple of 2048
+                min_sectors = 300*4;    // Smallest track is 300 frames
+                if (num_sectors >= 256*60*75*4) {
+                        num_sectors = (256*60*75 - 1) * 4;
+                        LINFO(curlun, "file too big: %s\n", filename);
+                        LINFO(curlun, "using only first %d blocks\n",
+                                        (int) num_sectors);
+                }
+        }
+        if (num_sectors < min_sectors) {
                 LINFO(curlun, "file too small: %s\n", filename);
                 rc = -ETOOSMALL;
                 goto out;
@@ -3845,9 +3972,12 @@ static int __init fsg_bind(struct usb_gadget *gadget)
                 goto out;
 
         if (mod_data.removable) {       // Enable the store_xxx attributes
-                dev_attr_ro.attr.mode = dev_attr_file.attr.mode = 0644;
-                dev_attr_ro.store = store_ro;
+                dev_attr_file.attr.mode = 0644;
                 dev_attr_file.store = store_file;
+                if (!mod_data.cdrom) {
+                        dev_attr_ro.attr.mode = 0644;
+                        dev_attr_ro.store = store_ro;
+                }
         }
 
         /* Find out how many LUNs there should be */
@@ -3872,6 +4002,8 @@ static int __init fsg_bind(struct usb_gadget *gadget)
         for (i = 0; i < fsg->nluns; ++i) {
                 curlun = &fsg->luns[i];
                 curlun->ro = mod_data.ro[i];
+                if (mod_data.cdrom)
+                        curlun->ro = 1;
                 curlun->dev.release = lun_release;
                 curlun->dev.parent = &gadget->dev;
                 curlun->dev.driver = &fsg_driver.driver;
@@ -4031,9 +4163,9 @@ static int __init fsg_bind(struct usb_gadget *gadget)
                         mod_data.protocol_name, mod_data.protocol_type);
         DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
                         mod_data.vendor, mod_data.product, mod_data.release);
-        DBG(fsg, "removable=%d, stall=%d, buflen=%u\n",
+        DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
                         mod_data.removable, mod_data.can_stall,
-                        mod_data.buflen);
+                        mod_data.cdrom, mod_data.buflen);
         DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
 
         set_bit(REGISTERED, &fsg->atomic_bitflags);
@@ -4050,6 +4182,7 @@ out:
         fsg->state = FSG_STATE_TERMINATED;      // The thread is dead
         fsg_unbind(gadget);
         close_all_backing_files(fsg);
+        complete(&fsg->thread_notifier);
         return rc;
 }
 
diff --git a/drivers/usb/gadget/fsl_qe_udc.c b/drivers/usb/gadget/fsl_qe_udc.c
index f40272565098..d6c5bcd40064 100644
--- a/drivers/usb/gadget/fsl_qe_udc.c
+++ b/drivers/usb/gadget/fsl_qe_udc.c
@@ -26,6 +26,7 @@
 #include <linux/ioport.h>
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/list.h>
 #include <linux/interrupt.h>
@@ -370,6 +371,9 @@ static int qe_ep_bd_init(struct qe_udc *udc, unsigned char pipe_num)
         /* alloc multi-ram for BD rings and set the ep parameters */
         tmp_addr = cpm_muram_alloc(sizeof(struct qe_bd) * (bdring_len +
                                 USB_BDRING_LEN_TX), QE_ALIGNMENT_OF_BD);
+        if (IS_ERR_VALUE(tmp_addr))
+                return -ENOMEM;
+
         out_be16(&epparam->rbase, (u16)tmp_addr);
         out_be16(&epparam->tbase, (u16)(tmp_addr +
                                 (sizeof(struct qe_bd) * bdring_len)));
@@ -689,7 +693,7 @@ en_done2:
 en_done1:
         spin_unlock_irqrestore(&udc->lock, flags);
 en_done:
-        dev_dbg(udc->dev, "failed to initialize %s\n", ep->ep.name);
+        dev_err(udc->dev, "failed to initialize %s\n", ep->ep.name);
         return -ENODEV;
 }
 
@@ -2408,6 +2412,8 @@ static struct qe_udc __devinit *qe_udc_config(struct of_device *ofdev)
         tmp_addr = cpm_muram_alloc((USB_MAX_ENDPOINTS *
                                         sizeof(struct usb_ep_para)),
                                            USB_EP_PARA_ALIGNMENT);
+        if (IS_ERR_VALUE(tmp_addr))
+                goto cleanup;
 
         for (i = 0; i < USB_MAX_ENDPOINTS; i++) {
                 out_be16(&usbpram->epptr[i], (u16)tmp_addr);
@@ -2513,7 +2519,7 @@ static int __devinit qe_udc_probe(struct of_device *ofdev,
         /* Initialize the udc structure including QH member and other member */
         udc_controller = qe_udc_config(ofdev);
         if (!udc_controller) {
-                dev_dbg(&ofdev->dev, "udc_controll is NULL\n");
+                dev_err(&ofdev->dev, "failed to initialize\n");
                 return -ENOMEM;
         }
 
@@ -2568,7 +2574,7 @@ static int __devinit qe_udc_probe(struct of_device *ofdev,
         /* create a buf for ZLP send, need to remain zeroed */
         udc_controller->nullbuf = kzalloc(256, GFP_KERNEL);
         if (udc_controller->nullbuf == NULL) {
-                dev_dbg(udc_controller->dev, "cannot alloc nullbuf\n");
+                dev_err(udc_controller->dev, "cannot alloc nullbuf\n");
                 ret = -ENOMEM;
                 goto err3;
         }
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 4e3107dd2f34..ec6d439a2aa5 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -110,7 +110,6 @@
 #define gadget_is_at91(g)       0
 #endif
 
-/* status unclear */
 #ifdef CONFIG_USB_GADGET_IMX
 #define gadget_is_imx(g)        !strcmp("imx_udc", (g)->name)
 #else
@@ -158,6 +157,11 @@
 #define gadget_is_fsl_qe(g)     0
 #endif
 
+#ifdef CONFIG_USB_GADGET_CI13XXX
+#define gadget_is_ci13xxx(g)    (!strcmp("ci13xxx_udc", (g)->name))
+#else
+#define gadget_is_ci13xxx(g)    0
+#endif
 
 // CONFIG_USB_GADGET_SX2
 // CONFIG_USB_GADGET_AU1X00
@@ -225,6 +229,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
                 return 0x21;
         else if (gadget_is_fsl_qe(gadget))
                 return 0x22;
+        else if (gadget_is_ci13xxx(gadget))
+                return 0x23;
         return -ENOENT;
 }
 
diff --git a/drivers/usb/gadget/goku_udc.c b/drivers/usb/gadget/goku_udc.c
index 60aa04847b18..63419c4d503c 100644
--- a/drivers/usb/gadget/goku_udc.c
+++ b/drivers/usb/gadget/goku_udc.c
@@ -1349,7 +1349,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
         int                     retval;
 
         if (!driver
-                        || driver->speed != USB_SPEED_FULL
+                        || driver->speed < USB_SPEED_FULL
                         || !driver->bind
                         || !driver->disconnect
                         || !driver->setup)
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
new file mode 100644
index 000000000000..cde8fdf15d5b
--- /dev/null
+++ b/drivers/usb/gadget/imx_udc.c
@@ -0,0 +1,1516 @@
+/*
+ *      driver/usb/gadget/imx_udc.c
+ *
+ *      Copyright (C) 2005 Mike Lee(eemike@gmail.com)
+ *      Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>
+ *
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *
+ *      This program is distributed in the hope that it will be useful,
+ *      but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *      GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <mach/usb.h>
+#include <mach/hardware.h>
+
+#include "imx_udc.h"
+
+static const char driver_name[] = "imx_udc";
+static const char ep0name[] = "ep0";
+
+void ep0_chg_stat(const char *label, struct imx_udc_struct *imx_usb,
+                                                        enum ep0_state stat);
+
+/*******************************************************************************
+ * IMX UDC hardware related functions
+ *******************************************************************************
+ */
+
+void imx_udc_enable(struct imx_udc_struct *imx_usb)
+{
+        int temp = __raw_readl(imx_usb->base + USB_CTRL);
+        __raw_writel(temp | CTRL_FE_ENA | CTRL_AFE_ENA, imx_usb->base + USB_CTRL);
+        imx_usb->gadget.speed = USB_SPEED_FULL;
+}
+
+void imx_udc_disable(struct imx_udc_struct *imx_usb)
+{
+        int temp = __raw_readl(imx_usb->base + USB_CTRL);
+
+        __raw_writel(temp & ~(CTRL_FE_ENA | CTRL_AFE_ENA),
+                 imx_usb->base + USB_CTRL);
+
+        ep0_chg_stat(__func__, imx_usb, EP0_IDLE);
+        imx_usb->gadget.speed = USB_SPEED_UNKNOWN;
+}
+
+void imx_udc_reset(struct imx_udc_struct *imx_usb)
+{
+        int temp = __raw_readl(imx_usb->base + USB_ENAB);
+
+        /* set RST bit */
+        __raw_writel(temp | ENAB_RST, imx_usb->base + USB_ENAB);
+
+        /* wait RST bit to clear */
+        do {} while (__raw_readl(imx_usb->base + USB_ENAB) & ENAB_RST);
+
+        /* wait CFG bit to assert */
+        do {} while (!(__raw_readl(imx_usb->base + USB_DADR) & DADR_CFG));
+
+        /* udc module is now ready */
+}
+
+void imx_udc_config(struct imx_udc_struct *imx_usb)
+{
+        u8 ep_conf[5];
+        u8 i, j, cfg;
+        struct imx_ep_struct *imx_ep;
+
+        /* wait CFG bit to assert */
+        do {} while (!(__raw_readl(imx_usb->base + USB_DADR) & DADR_CFG));
+
+        /* Download the endpoint buffer for endpoint 0. */
+        for (j = 0; j < 5; j++) {
+                i = (j == 2 ? imx_usb->imx_ep[0].fifosize : 0x00);
+                __raw_writeb(i, imx_usb->base + USB_DDAT);
+                do {} while (__raw_readl(imx_usb->base + USB_DADR) & DADR_BSY);
+        }
+
+        /* Download the endpoint buffers for endpoints 1-5.
+         * We specify two configurations, one interface
+         */
+        for (cfg = 1; cfg < 3; cfg++) {
+                for (i = 1; i < IMX_USB_NB_EP; i++) {
+                        imx_ep = &imx_usb->imx_ep[i];
+                        /* EP no | Config no */
+                        ep_conf[0] = (i << 4) | (cfg << 2);
+                        /* Type | Direction */
+                        ep_conf[1] = (imx_ep->bmAttributes << 3) |
+                                        (EP_DIR(imx_ep) << 2);
+                        /* Max packet size */
+                        ep_conf[2] = imx_ep->fifosize;
+                        /* TRXTYP */
+                        ep_conf[3] = 0xC0;
+                        /* FIFO no */
+                        ep_conf[4] = i;
+
+                        D_INI(imx_usb->dev,
+                                "<%s> ep%d_conf[%d]:"
+                                "[%02x-%02x-%02x-%02x-%02x]\n",
+                                __func__, i, cfg,
+                                ep_conf[0], ep_conf[1], ep_conf[2],
+                                ep_conf[3], ep_conf[4]);
+
+                        for (j = 0; j < 5; j++) {
+                                __raw_writeb(ep_conf[j],
+                                        imx_usb->base + USB_DDAT);
+                                do {} while (__raw_readl(imx_usb->base + USB_DADR)
+                                        & DADR_BSY);
+                        }
+                }
+        }
+
+        /* wait CFG bit to clear */
+        do {} while (__raw_readl(imx_usb->base + USB_DADR) & DADR_CFG);
+}
+
+void imx_udc_init_irq(struct imx_udc_struct *imx_usb)
+{
+        int i;
+
+        /* Mask and clear all irqs */
+        __raw_writel(0xFFFFFFFF, imx_usb->base + USB_MASK);
+        __raw_writel(0xFFFFFFFF, imx_usb->base + USB_INTR);
+        for (i = 0; i < IMX_USB_NB_EP; i++) {
+                __raw_writel(0x1FF, imx_usb->base + USB_EP_MASK(i));
+                __raw_writel(0x1FF, imx_usb->base + USB_EP_INTR(i));
+        }
+
+        /* Enable USB irqs */
+        __raw_writel(INTR_MSOF | INTR_FRAME_MATCH, imx_usb->base + USB_MASK);
+
+        /* Enable EP0 irqs */
+        __raw_writel(0x1FF & ~(EPINTR_DEVREQ | EPINTR_MDEVREQ | EPINTR_EOT
+                | EPINTR_EOF | EPINTR_FIFO_EMPTY | EPINTR_FIFO_FULL),
+                imx_usb->base + USB_EP_MASK(0));
+}
+
+void imx_udc_init_ep(struct imx_udc_struct *imx_usb)
+{
+        int i, max, temp;
+        struct imx_ep_struct *imx_ep;
+        for (i = 0; i < IMX_USB_NB_EP; i++) {
+                imx_ep = &imx_usb->imx_ep[i];
+                switch (imx_ep->fifosize) {
+                case 8:
+                        max = 0;
+                        break;
+                case 16:
+                        max = 1;
+                        break;
+                case 32:
+                        max = 2;
+                        break;
+                case 64:
+                        max = 3;
+                        break;
+                default:
+                        max = 1;
+                        break;
+                }
+                temp = (EP_DIR(imx_ep) << 7) | (max << 5)
+                        | (imx_ep->bmAttributes << 3);
+                __raw_writel(temp, imx_usb->base + USB_EP_STAT(i));
+                __raw_writel(temp | EPSTAT_FLUSH, imx_usb->base + USB_EP_STAT(i));
+                D_INI(imx_usb->dev, "<%s> ep%d_stat %08x\n", __func__, i,
+                        __raw_readl(imx_usb->base + USB_EP_STAT(i)));
+        }
+}
+
+void imx_udc_init_fifo(struct imx_udc_struct *imx_usb)
+{
+        int i, temp;
+        struct imx_ep_struct *imx_ep;
+        for (i = 0; i < IMX_USB_NB_EP; i++) {
+                imx_ep = &imx_usb->imx_ep[i];
+
+                /* Fifo control */
+                temp = EP_DIR(imx_ep) ? 0x0B000000 : 0x0F000000;
+                __raw_writel(temp, imx_usb->base + USB_EP_FCTRL(i));
+                D_INI(imx_usb->dev, "<%s> ep%d_fctrl %08x\n", __func__, i,
+                        __raw_readl(imx_usb->base + USB_EP_FCTRL(i)));
+
+                /* Fifo alarm */
+                temp = (i ? imx_ep->fifosize / 2 : 0);
+                __raw_writel(temp, imx_usb->base + USB_EP_FALRM(i));
+                D_INI(imx_usb->dev, "<%s> ep%d_falrm %08x\n", __func__, i,
+                        __raw_readl(imx_usb->base + USB_EP_FALRM(i)));
+        }
+}
+
+static void imx_udc_init(struct imx_udc_struct *imx_usb)
+{
+        /* Reset UDC */
+        imx_udc_reset(imx_usb);
+
+        /* Download config to enpoint buffer */
+        imx_udc_config(imx_usb);
+
+        /* Setup interrups */
+        imx_udc_init_irq(imx_usb);
+
+        /* Setup endpoints */
+        imx_udc_init_ep(imx_usb);
+
+        /* Setup fifos */
+        imx_udc_init_fifo(imx_usb);
+}
+
+void imx_ep_irq_enable(struct imx_ep_struct *imx_ep)
+{
+
+        int i = EP_NO(imx_ep);
+
+        __raw_writel(0x1FF, imx_ep->imx_usb->base + USB_EP_MASK(i));
+        __raw_writel(0x1FF, imx_ep->imx_usb->base + USB_EP_INTR(i));
+        __raw_writel(0x1FF & ~(EPINTR_EOT | EPINTR_EOF),
+                imx_ep->imx_usb->base + USB_EP_MASK(i));
+}
+
+void imx_ep_irq_disable(struct imx_ep_struct *imx_ep)
+{
+
+        int i = EP_NO(imx_ep);
+
+        __raw_writel(0x1FF, imx_ep->imx_usb->base + USB_EP_MASK(i));
+        __raw_writel(0x1FF, imx_ep->imx_usb->base + USB_EP_INTR(i));
+}
+
+int imx_ep_empty(struct imx_ep_struct *imx_ep)
+{
+        struct imx_udc_struct *imx_usb = imx_ep->imx_usb;
+
+        return __raw_readl(imx_usb->base + USB_EP_FSTAT(EP_NO(imx_ep)))
+                        & FSTAT_EMPTY;
+}
+
+unsigned imx_fifo_bcount(struct imx_ep_struct *imx_ep)
+{
+        struct imx_udc_struct *imx_usb = imx_ep->imx_usb;
+
+        return (__raw_readl(imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)))
+                        & EPSTAT_BCOUNT) >> 16;
+}
+
+void imx_flush(struct imx_ep_struct *imx_ep)
+{
+        struct imx_udc_struct *imx_usb = imx_ep->imx_usb;
+
+        int temp = __raw_readl(imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+        __raw_writel(temp | EPSTAT_FLUSH,
+                imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+}
+
+void imx_ep_stall(struct imx_ep_struct *imx_ep)
+{
+        struct imx_udc_struct *imx_usb = imx_ep->imx_usb;
+        int temp, i;
+
+        D_ERR(imx_usb->dev, "<%s> Forced stall on %s\n", __func__, imx_ep->ep.name);
+
+        imx_flush(imx_ep);
+
+        /* Special care for ep0 */
+        if (EP_NO(imx_ep)) {
+                temp = __raw_readl(imx_usb->base + USB_CTRL);
+                __raw_writel(temp | CTRL_CMDOVER | CTRL_CMDERROR, imx_usb->base + USB_CTRL);
+                do { } while (__raw_readl(imx_usb->base + USB_CTRL) & CTRL_CMDOVER);
+                temp = __raw_readl(imx_usb->base + USB_CTRL);
+                __raw_writel(temp & ~CTRL_CMDERROR, imx_usb->base + USB_CTRL);
+        }
+        else {
+                temp = __raw_readl(imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+                __raw_writel(temp | EPSTAT_STALL,
+                        imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+
+                for (i = 0; i < 100; i ++) {
+                        temp = __raw_readl(imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+                        if (!temp & EPSTAT_STALL)
+                                break;
+                        udelay(20);
+                }
+                if (i == 50)
+                        D_ERR(imx_usb->dev, "<%s> Non finished stall on %s\n",
+                                __func__, imx_ep->ep.name);
+        }
+}
+
+static int imx_udc_get_frame(struct usb_gadget *_gadget)
+{
+        struct imx_udc_struct *imx_usb = container_of(_gadget,
+                        struct imx_udc_struct, gadget);
+
+        return __raw_readl(imx_usb->base + USB_FRAME) & 0x7FF;
+}
+
+static int imx_udc_wakeup(struct usb_gadget *_gadget)
+{
+        return 0;
+}
+
+/*******************************************************************************
+ * USB request control functions
+ *******************************************************************************
+ */
+
+static void ep_add_request(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        if (unlikely(!req))
+                return;
+
+        req->in_use = 1;
+        list_add_tail(&req->queue, &imx_ep->queue);
+}
+
+static void ep_del_request(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        if (unlikely(!req))
+                return;
+
+        list_del_init(&req->queue);
+        req->in_use = 0;
+}
+
+static void done(struct imx_ep_struct *imx_ep, struct imx_request *req, int status)
+{
+        ep_del_request(imx_ep, req);
+
+        if (likely(req->req.status == -EINPROGRESS))
+                req->req.status = status;
+        else
+                status = req->req.status;
+
+        if (status && status != -ESHUTDOWN)
+                D_ERR(imx_ep->imx_usb->dev,
+                        "<%s> complete %s req %p stat %d len %u/%u\n", __func__,
+                        imx_ep->ep.name, &req->req, status,
+                        req->req.actual, req->req.length);
+
+        req->req.complete(&imx_ep->ep, &req->req);
+}
+
+static void nuke(struct imx_ep_struct *imx_ep, int status)
+{
+        struct imx_request *req;
+
+        while (!list_empty(&imx_ep->queue)) {
+                req = list_entry(imx_ep->queue.next, struct imx_request, queue);
+                done(imx_ep, req, status);
+        }
+}
+
+/*******************************************************************************
+ * Data tansfer over USB functions
+ *******************************************************************************
+ */
+static int read_packet(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        u8      *buf;
+        int     bytes_ep, bufferspace, count, i;
+
+        bytes_ep = imx_fifo_bcount(imx_ep);
+        bufferspace = req->req.length - req->req.actual;
+
+        buf = req->req.buf + req->req.actual;
+        prefetchw(buf);
+
+        if (unlikely(imx_ep_empty(imx_ep)))
+                count = 0;      /* zlp */
+        else
+                count = min(bytes_ep, bufferspace);
+
+        for (i = count; i > 0; i--)
+                *buf++ = __raw_readb(imx_ep->imx_usb->base
+                                                + USB_EP_FDAT0(EP_NO(imx_ep)));
+        req->req.actual += count;
+
+        return count;
+}
+
+static int write_packet(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        u8      *buf;
+        int     length, count, temp;
+
+        buf = req->req.buf + req->req.actual;
+        prefetch(buf);
+
+        length = min(req->req.length - req->req.actual, (u32)imx_ep->fifosize);
+
+        if (imx_fifo_bcount(imx_ep) + length > imx_ep->fifosize) {
+                D_TRX(imx_ep->imx_usb->dev, "<%s> packet overfill %s fifo\n",
+                        __func__, imx_ep->ep.name);
+                return -1;
+        }
+
+        req->req.actual += length;
+        count = length;
+
+        if (!count && req->req.zero) {  /* zlp */
+                temp = __raw_readl(imx_ep->imx_usb->base
+                        + USB_EP_STAT(EP_NO(imx_ep)));
+                __raw_writel(temp | EPSTAT_ZLPS, imx_ep->imx_usb->base
+                        + USB_EP_STAT(EP_NO(imx_ep)));
+                D_TRX(imx_ep->imx_usb->dev, "<%s> zero packet\n", __func__);
+                return 0;
+        }
+
+        while (count--) {
+                if (count == 0) {       /* last byte */
+                        temp = __raw_readl(imx_ep->imx_usb->base
+                                + USB_EP_FCTRL(EP_NO(imx_ep)));
+                        __raw_writel(temp | FCTRL_WFR, imx_ep->imx_usb->base
+                                + USB_EP_FCTRL(EP_NO(imx_ep)));
+                }
+                __raw_writeb(*buf++,
+                        imx_ep->imx_usb->base + USB_EP_FDAT0(EP_NO(imx_ep)));
+        }
+
+        return length;
+}
+
+static int read_fifo(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        int     bytes = 0,
+                count,
+                completed = 0;
+
+        while (__raw_readl(imx_ep->imx_usb->base + USB_EP_FSTAT(EP_NO(imx_ep)))
+                & FSTAT_FR) {
+                        count = read_packet(imx_ep, req);
+                        bytes += count;
+
+                        completed = (count != imx_ep->fifosize);
+                        if (completed || req->req.actual == req->req.length) {
+                                completed = 1;
+                                break;
+                        }
+        }
+
+        if (completed || !req->req.length) {
+                done(imx_ep, req, 0);
+                D_REQ(imx_ep->imx_usb->dev, "<%s> %s req<%p> %s\n",
+                        __func__, imx_ep->ep.name, req,
+                        completed ? "completed" : "not completed");
+                if (!EP_NO(imx_ep))
+                        ep0_chg_stat(__func__, imx_ep->imx_usb, EP0_IDLE);
+        }
+
+        D_TRX(imx_ep->imx_usb->dev, "<%s> bytes read: %d\n", __func__, bytes);
+
+        return completed;
+}
+
+static int write_fifo(struct imx_ep_struct *imx_ep, struct imx_request *req)
+{
+        int     bytes = 0,
+                count,
+                completed = 0;
+
+        while (!completed) {
+                count = write_packet(imx_ep, req);
+                if (count < 0)
+                        break; /* busy */
+                bytes += count;
+
+                /* last packet "must be" short (or a zlp) */
+                completed = (count != imx_ep->fifosize);
+
+                if (unlikely(completed)) {
+                        done(imx_ep, req, 0);
+                        D_REQ(imx_ep->imx_usb->dev, "<%s> %s req<%p> %s\n",
+                                __func__, imx_ep->ep.name, req,
+                                completed ? "completed" : "not completed");
+                        if (!EP_NO(imx_ep))
+                                ep0_chg_stat(__func__, imx_ep->imx_usb, EP0_IDLE);
+                }
+        }
+
+        D_TRX(imx_ep->imx_usb->dev, "<%s> bytes sent: %d\n", __func__, bytes);
+
+        return completed;
+}
+
+/*******************************************************************************
+ * Endpoint handlers
+ *******************************************************************************
+ */
+static int handle_ep(struct imx_ep_struct *imx_ep)
+{
+        struct imx_request *req;
+        int completed = 0;
+
+        do {
+                if (!list_empty(&imx_ep->queue))
+                        req = list_entry(imx_ep->queue.next,
+                                struct imx_request, queue);
+                else {
+                        D_REQ(imx_ep->imx_usb->dev, "<%s> no request on %s\n",
+                                __func__, imx_ep->ep.name);
+                        return 0;
+                }
+
+                if (EP_DIR(imx_ep))     /* to host */
+                        completed = write_fifo(imx_ep, req);
+                else                    /* to device */
+                        completed = read_fifo(imx_ep, req);
+
+                dump_ep_stat(__func__, imx_ep);
+
+        } while (completed);
+
+        return 0;
+}
+
+static int handle_ep0(struct imx_ep_struct *imx_ep)
+{
+        struct imx_request *req = NULL;
+        int ret = 0;
+
+        if (!list_empty(&imx_ep->queue))
+                req = list_entry(imx_ep->queue.next, struct imx_request, queue);
+
+        if (req) {
+                switch (imx_ep->imx_usb->ep0state) {
+
+                case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR */
+                        write_fifo(imx_ep, req);
+                        break;
+                case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR */
+                        read_fifo(imx_ep, req);
+                        break;
+                default:
+                        D_EP0(imx_ep->imx_usb->dev,
+                                "<%s> ep0 i/o, odd state %d\n",
+                                __func__, imx_ep->imx_usb->ep0state);
+                        ep_del_request(imx_ep, req);
+                        ret = -EL2HLT;
+                        break;
+                }
+        }
+
+        return ret;
+}
+
+static void handle_ep0_devreq(struct imx_udc_struct *imx_usb)
+{
+        struct imx_ep_struct *imx_ep = &imx_usb->imx_ep[0];
+        union {
+                struct usb_ctrlrequest  r;
+                u8                      raw[8];
+                u32                     word[2];
+        } u;
+        int temp, i;
+
+        nuke(imx_ep, -EPROTO);
+
+        /* read SETUP packet */
+        for (i = 0; i < 2; i++) {
+                if (imx_ep_empty(imx_ep)) {
+                        D_ERR(imx_usb->dev,
+                                "<%s> no setup packet received\n", __func__);
+                        goto stall;
+                }
+                u.word[i] = __raw_readl(imx_usb->base + USB_EP_FDAT(EP_NO(imx_ep)));
+        }
+
+        temp = imx_ep_empty(imx_ep);
+        while (!imx_ep_empty(imx_ep)) {
+                i = __raw_readl(imx_usb->base + USB_EP_FDAT(EP_NO(imx_ep)));
+                D_ERR(imx_usb->dev,
+                        "<%s> wrong to have extra bytes for setup : 0x%08x\n",
+                        __func__, i);
+        }
+        if (!temp)
+                goto stall;
+
+        le16_to_cpus(&u.r.wValue);
+        le16_to_cpus(&u.r.wIndex);
+        le16_to_cpus(&u.r.wLength);
+
+        D_REQ(imx_usb->dev, "<%s> SETUP %02x.%02x v%04x i%04x l%04x\n",
+                __func__, u.r.bRequestType, u.r.bRequest,
+                u.r.wValue, u.r.wIndex, u.r.wLength);
+
+        if (imx_usb->set_config) {
+                /* NACK the host by using CMDOVER */
+                temp = __raw_readl(imx_usb->base + USB_CTRL);
+                __raw_writel(temp | CTRL_CMDOVER, imx_usb->base + USB_CTRL);
+
+                D_ERR(imx_usb->dev,
+                        "<%s> set config req is pending, NACK the host\n",
+                        __func__);
+                return;
+        }
+
+        if (u.r.bRequestType & USB_DIR_IN)
+                ep0_chg_stat(__func__, imx_usb, EP0_IN_DATA_PHASE);
+        else
+                ep0_chg_stat(__func__, imx_usb, EP0_OUT_DATA_PHASE);
+
+        i = imx_usb->driver->setup(&imx_usb->gadget, &u.r);
+        if (i < 0) {
+                D_ERR(imx_usb->dev, "<%s> device setup error %d\n",
+                        __func__, i);
+                goto stall;
+        }
+
+        return;
+stall:
+        D_ERR(imx_usb->dev, "<%s> protocol STALL\n", __func__);
+        imx_ep_stall(imx_ep);
+        ep0_chg_stat(__func__, imx_usb, EP0_STALL);
+        return;
+}
+
+/*******************************************************************************
+ * USB gadget callback functions
+ *******************************************************************************
+ */
+
+static int imx_ep_enable(struct usb_ep *usb_ep,
+                                const struct usb_endpoint_descriptor *desc)
+{
+        struct imx_ep_struct *imx_ep = container_of(usb_ep,
+                                                struct imx_ep_struct, ep);
+        struct imx_udc_struct *imx_usb = imx_ep->imx_usb;
+        unsigned long flags;
+
+        if (!usb_ep
+                || !desc
+                || !EP_NO(imx_ep)
+                || desc->bDescriptorType != USB_DT_ENDPOINT
+                || imx_ep->bEndpointAddress != desc->bEndpointAddress) {
+                        D_ERR(imx_usb->dev,
+                                "<%s> bad ep or descriptor\n", __func__);
+                        return -EINVAL;
+        }
+
+        if (imx_ep->bmAttributes != desc->bmAttributes) {
+                D_ERR(imx_usb->dev,
+                        "<%s> %s type mismatch\n", __func__, usb_ep->name);
+                return -EINVAL;
+        }
+
+        if (imx_ep->fifosize < le16_to_cpu(desc->wMaxPacketSize)) {
+                D_ERR(imx_usb->dev,
+                        "<%s> bad %s maxpacket\n", __func__, usb_ep->name);
+                return -ERANGE;
+        }
+
+        if (!imx_usb->driver || imx_usb->gadget.speed == USB_SPEED_UNKNOWN) {
+                D_ERR(imx_usb->dev, "<%s> bogus device state\n", __func__);
+                return -ESHUTDOWN;
+        }
+
+        local_irq_save(flags);
+
+        imx_ep->stopped = 0;
+        imx_flush(imx_ep);
+        imx_ep_irq_enable(imx_ep);
+
+        local_irq_restore(flags);
+
+        D_EPX(imx_usb->dev, "<%s> ENABLED %s\n", __func__, usb_ep->name);
+        return 0;
+}
+
+static int imx_ep_disable(struct usb_ep *usb_ep)
+{
+        struct imx_ep_struct *imx_ep = container_of(usb_ep,
+                                                struct imx_ep_struct, ep);
+        unsigned long flags;
+
+        if (!usb_ep || !EP_NO(imx_ep) || !list_empty(&imx_ep->queue)) {
+                D_ERR(imx_ep->imx_usb->dev, "<%s> %s can not be disabled\n",
+                        __func__, usb_ep ? imx_ep->ep.name : NULL);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+
+        imx_ep->stopped = 1;
+        nuke(imx_ep, -ESHUTDOWN);
+        imx_flush(imx_ep);
+        imx_ep_irq_disable(imx_ep);
+
+        local_irq_restore(flags);
+
+        D_EPX(imx_ep->imx_usb->dev,
+                "<%s> DISABLED %s\n", __func__, usb_ep->name);
+        return 0;
+}
+
+static struct usb_request *imx_ep_alloc_request
+                                        (struct usb_ep *usb_ep, gfp_t gfp_flags)
+{
+        struct imx_request *req;
+
+        req = kzalloc(sizeof *req, gfp_flags);
+        if (!req || !usb_ep)
+                return 0;
+
+        INIT_LIST_HEAD(&req->queue);
+        req->in_use = 0;
+
+        return &req->req;
+}
+
+static void imx_ep_free_request
+                        (struct usb_ep *usb_ep, struct usb_request *usb_req)
+{
+        struct imx_request *req;
+
+        req = container_of(usb_req, struct imx_request, req);
+        WARN_ON(!list_empty(&req->queue));
+        kfree(req);
+}
+
+static int imx_ep_queue
+        (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)
+{
+        struct imx_ep_struct    *imx_ep;
+        struct imx_udc_struct   *imx_usb;
+        struct imx_request      *req;
+        unsigned long           flags;
+        int                     ret = 0;
+
+        imx_ep = container_of(usb_ep, struct imx_ep_struct, ep);
+        imx_usb = imx_ep->imx_usb;
+        req = container_of(usb_req, struct imx_request, req);
+
+        /*
+          Special care on IMX udc.
+          Ignore enqueue when after set configuration from the
+          host. This assume all gadget drivers reply set
+          configuration with the next ep0 req enqueue.
+        */
+        if (imx_usb->set_config && !EP_NO(imx_ep)) {
+                imx_usb->set_config = 0;
+                D_EPX(imx_usb->dev,
+                        "<%s> gadget reply set config\n", __func__);
+                return 0;
+        }
+
+        if (unlikely(!usb_req || !req || !usb_req->complete || !usb_req->buf)) {
+                D_ERR(imx_usb->dev, "<%s> bad params\n", __func__);
+                return -EINVAL;
+        }
+
+        if (unlikely(!usb_ep || !imx_ep)) {
+                D_ERR(imx_usb->dev, "<%s> bad ep\n", __func__);
+                return -EINVAL;
+        }
+
+        if (!imx_usb->driver || imx_usb->gadget.speed == USB_SPEED_UNKNOWN) {
+                D_ERR(imx_usb->dev, "<%s> bogus device state\n", __func__);
+                return -ESHUTDOWN;
+        }
+
+        local_irq_save(flags);
+
+        /* Debug */
+        D_REQ(imx_usb->dev, "<%s> ep%d %s request for [%d] bytes\n",
+                __func__, EP_NO(imx_ep),
+                ((!EP_NO(imx_ep) && imx_ep->imx_usb->ep0state == EP0_IN_DATA_PHASE)
+                || (EP_NO(imx_ep) && EP_DIR(imx_ep))) ? "IN" : "OUT", usb_req->length);
+        dump_req(__func__, imx_ep, usb_req);
+
+        if (imx_ep->stopped) {
+                usb_req->status = -ESHUTDOWN;
+                ret = -ESHUTDOWN;
+                goto out;
+        }
+
+        if (req->in_use) {
+                D_ERR(imx_usb->dev,
+                        "<%s> refusing to queue req %p (already queued)\n",
+                        __func__, req);
+                goto out;
+        }
+
+        usb_req->status = -EINPROGRESS;
+        usb_req->actual = 0;
+
+        ep_add_request(imx_ep, req);
+
+        if (!EP_NO(imx_ep))
+                ret = handle_ep0(imx_ep);
+        else
+                ret = handle_ep(imx_ep);
+out:
+        local_irq_restore(flags);
+        return ret;
+}
+
+static int imx_ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
+{
+
+        struct imx_ep_struct *imx_ep = container_of
+                                        (usb_ep, struct imx_ep_struct, ep);
+        struct imx_request *req;
+        unsigned long flags;
+
+        if (unlikely(!usb_ep || !EP_NO(imx_ep))) {
+                D_ERR(imx_ep->imx_usb->dev, "<%s> bad ep\n", __func__);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+
+        /* make sure it's actually queued on this endpoint */
+        list_for_each_entry(req, &imx_ep->queue, queue) {
+                if (&req->req == usb_req)
+                        break;
+        }
+        if (&req->req != usb_req) {
+                local_irq_restore(flags);
+                return -EINVAL;
+        }
+
+        done(imx_ep, req, -ECONNRESET);
+
+        local_irq_restore(flags);
+        return 0;
+}
+
+static int imx_ep_set_halt(struct usb_ep *usb_ep, int value)
+{
+        struct imx_ep_struct *imx_ep = container_of
+                                        (usb_ep, struct imx_ep_struct, ep);
+        unsigned long flags;
+
+        if (unlikely(!usb_ep || !EP_NO(imx_ep))) {
+                D_ERR(imx_ep->imx_usb->dev, "<%s> bad ep\n", __func__);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+
+        if ((imx_ep->bEndpointAddress & USB_DIR_IN)
+                && !list_empty(&imx_ep->queue)) {
+                        local_irq_restore(flags);
+                        return -EAGAIN;
+        }
+
+        imx_ep_stall(imx_ep);
+
+        local_irq_restore(flags);
+
+        D_EPX(imx_ep->imx_usb->dev, "<%s> %s halt\n", __func__, usb_ep->name);
+        return 0;
+}
+
+static int imx_ep_fifo_status(struct usb_ep *usb_ep)
+{
+        struct imx_ep_struct *imx_ep = container_of
+                                        (usb_ep, struct imx_ep_struct, ep);
+
+        if (!usb_ep) {
+                D_ERR(imx_ep->imx_usb->dev, "<%s> bad ep\n", __func__);
+                return -ENODEV;
+        }
+
+        if (imx_ep->imx_usb->gadget.speed == USB_SPEED_UNKNOWN)
+                return 0;
+        else
+                return imx_fifo_bcount(imx_ep);
+}
+
+static void imx_ep_fifo_flush(struct usb_ep *usb_ep)
+{
+        struct imx_ep_struct *imx_ep = container_of
+                                        (usb_ep, struct imx_ep_struct, ep);
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        if (!usb_ep || !EP_NO(imx_ep) || !list_empty(&imx_ep->queue)) {
+                D_ERR(imx_ep->imx_usb->dev, "<%s> bad ep\n", __func__);
+                local_irq_restore(flags);
+                return;
+        }
+
+        /* toggle and halt bits stay unchanged */
+        imx_flush(imx_ep);
+
+        local_irq_restore(flags);
+}
+
+static struct usb_ep_ops imx_ep_ops = {
+        .enable         = imx_ep_enable,
+        .disable        = imx_ep_disable,
+
+        .alloc_request  = imx_ep_alloc_request,
+        .free_request   = imx_ep_free_request,
+
+        .queue          = imx_ep_queue,
+        .dequeue        = imx_ep_dequeue,
+
+        .set_halt       = imx_ep_set_halt,
+        .fifo_status    = imx_ep_fifo_status,
+        .fifo_flush     = imx_ep_fifo_flush,
+};
+
+/*******************************************************************************
+ * USB endpoint control functions
+ *******************************************************************************
+ */
+
+void ep0_chg_stat(const char *label,
+                        struct imx_udc_struct *imx_usb, enum ep0_state stat)
+{
+        D_EP0(imx_usb->dev, "<%s> from %15s to %15s\n",
+                label, state_name[imx_usb->ep0state], state_name[stat]);
+
+        if (imx_usb->ep0state == stat)
+                return;
+
+        imx_usb->ep0state = stat;
+}
+
+static void usb_init_data(struct imx_udc_struct *imx_usb)
+{
+        struct imx_ep_struct *imx_ep;
+        u8 i;
+
+        /* device/ep0 records init */
+        INIT_LIST_HEAD(&imx_usb->gadget.ep_list);
+        INIT_LIST_HEAD(&imx_usb->gadget.ep0->ep_list);
+        ep0_chg_stat(__func__, imx_usb, EP0_IDLE);
+
+        /* basic endpoint records init */
+        for (i = 0; i < IMX_USB_NB_EP; i++) {
+                imx_ep = &imx_usb->imx_ep[i];
+
+                if (i) {
+                        list_add_tail(&imx_ep->ep.ep_list,
+                                &imx_usb->gadget.ep_list);
+                        imx_ep->stopped = 1;
+                } else
+                        imx_ep->stopped = 0;
+
+                INIT_LIST_HEAD(&imx_ep->queue);
+        }
+}
+
+static void udc_stop_activity(struct imx_udc_struct *imx_usb,
+                                        struct usb_gadget_driver *driver)
+{
+        struct imx_ep_struct *imx_ep;
+        int i;
+
+        if (imx_usb->gadget.speed == USB_SPEED_UNKNOWN)
+                driver = NULL;
+
+        /* prevent new request submissions, kill any outstanding requests  */
+        for (i = 1; i < IMX_USB_NB_EP; i++) {
+                imx_ep = &imx_usb->imx_ep[i];
+                imx_flush(imx_ep);
+                imx_ep->stopped = 1;
+                imx_ep_irq_disable(imx_ep);
+                nuke(imx_ep, -ESHUTDOWN);
+        }
+
+        imx_usb->cfg = 0;
+        imx_usb->intf = 0;
+        imx_usb->alt = 0;
+
+        if (driver)
+                driver->disconnect(&imx_usb->gadget);
+}
+
+/*******************************************************************************
+ * Interrupt handlers
+ *******************************************************************************
+ */
+
+static irqreturn_t imx_udc_irq(int irq, void *dev)
+{
+        struct imx_udc_struct *imx_usb = dev;
+        struct usb_ctrlrequest u;
+        int temp, cfg, intf, alt;
+        int intr = __raw_readl(imx_usb->base + USB_INTR);
+
+        if (intr & (INTR_WAKEUP | INTR_SUSPEND | INTR_RESUME | INTR_RESET_START
+                        | INTR_RESET_STOP | INTR_CFG_CHG)) {
+                                dump_intr(__func__, intr, imx_usb->dev);
+                                dump_usb_stat(__func__, imx_usb);
+        }
+
+        if (!imx_usb->driver) {
+                /*imx_udc_disable(imx_usb);*/
+                goto end_irq;
+        }
+
+        if (intr & INTR_WAKEUP) {
+                if (imx_usb->gadget.speed == USB_SPEED_UNKNOWN
+                        && imx_usb->driver && imx_usb->driver->resume)
+                                imx_usb->driver->resume(&imx_usb->gadget);
+                imx_usb->set_config = 0;
+                imx_usb->gadget.speed = USB_SPEED_FULL;
+        }
+
+        if (intr & INTR_SUSPEND) {
+                if (imx_usb->gadget.speed != USB_SPEED_UNKNOWN
+                        && imx_usb->driver && imx_usb->driver->suspend)
+                                imx_usb->driver->suspend(&imx_usb->gadget);
+                imx_usb->set_config = 0;
+                imx_usb->gadget.speed = USB_SPEED_UNKNOWN;
+        }
+
+        if (intr & INTR_RESET_START) {
+                __raw_writel(intr, imx_usb->base + USB_INTR);
+                udc_stop_activity(imx_usb, imx_usb->driver);
+                imx_usb->set_config = 0;
+                imx_usb->gadget.speed = USB_SPEED_UNKNOWN;
+        }
+
+        if (intr & INTR_RESET_STOP)
+                imx_usb->gadget.speed = USB_SPEED_FULL;
+
+        if (intr & INTR_CFG_CHG) {
+                __raw_writel(INTR_CFG_CHG, imx_usb->base + USB_INTR);
+                temp = __raw_readl(imx_usb->base + USB_STAT);
+                cfg  = (temp & STAT_CFG) >> 5;
+                intf = (temp & STAT_INTF) >> 3;
+                alt  =  temp & STAT_ALTSET;
+
+                D_REQ(imx_usb->dev,
+                        "<%s> orig config C=%d, I=%d, A=%d / "
+                        "req config C=%d, I=%d, A=%d\n",
+                        __func__, imx_usb->cfg, imx_usb->intf, imx_usb->alt,
+                        cfg, intf, alt);
+
+                if (cfg != 1 && cfg != 2)
+                        goto end_irq;
+
+                imx_usb->set_config = 0;
+
+                /* Config setup */
+                if (imx_usb->cfg != cfg) {
+                        D_REQ(imx_usb->dev, "<%s> Change config start\n",__func__);
+                        u.bRequest = USB_REQ_SET_CONFIGURATION;
+                        u.bRequestType = USB_DIR_OUT |
+                                        USB_TYPE_STANDARD |
+                                        USB_RECIP_DEVICE;
+                        u.wValue = cfg;
+                        u.wIndex = 0;
+                        u.wLength = 0;
+                        imx_usb->cfg = cfg;
+                        imx_usb->set_config = 1;
+                        imx_usb->driver->setup(&imx_usb->gadget, &u);
+                        imx_usb->set_config = 0;
+                        D_REQ(imx_usb->dev, "<%s> Change config done\n",__func__);
+
+                }
+                if (imx_usb->intf != intf || imx_usb->alt != alt) {
+                        D_REQ(imx_usb->dev, "<%s> Change interface start\n",__func__);
+                        u.bRequest = USB_REQ_SET_INTERFACE;
+                        u.bRequestType = USB_DIR_OUT |
+                                          USB_TYPE_STANDARD |
+                                          USB_RECIP_INTERFACE;
+                        u.wValue = alt;
+                        u.wIndex = intf;
+                        u.wLength = 0;
+                        imx_usb->intf = intf;
+                        imx_usb->alt = alt;
+                        imx_usb->set_config = 1;
+                        imx_usb->driver->setup(&imx_usb->gadget, &u);
+                        imx_usb->set_config = 0;
+                        D_REQ(imx_usb->dev, "<%s> Change interface done\n",__func__);
+                }
+        }
+
+        if (intr & INTR_SOF) {
+                if (imx_usb->ep0state == EP0_IDLE) {
+                        temp = __raw_readl(imx_usb->base + USB_CTRL);
+                        __raw_writel(temp | CTRL_CMDOVER, imx_usb->base + USB_CTRL);
+                }
+        }
+
+end_irq:
+        __raw_writel(intr, imx_usb->base + USB_INTR);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t imx_udc_ctrl_irq(int irq, void *dev)
+{
+        struct imx_udc_struct *imx_usb = dev;
+        int intr = __raw_readl(imx_usb->base + USB_EP_INTR(0));
+
+        dump_ep_intr(__func__, 0, intr, imx_usb->dev);
+
+        if (!imx_usb->driver) {
+                __raw_writel(intr, imx_usb->base + USB_EP_INTR(0));
+                return IRQ_HANDLED;
+        }
+
+        /* DEVREQ IRQ has highest priority */
+        if (intr & (EPINTR_DEVREQ | EPINTR_MDEVREQ))
+                handle_ep0_devreq(imx_usb);
+        /* Seem i.MX is missing EOF interrupt sometimes.
+         * Therefore we monitor both EOF and FIFO_EMPTY interrups
+         * when transmiting, and both EOF and FIFO_FULL when
+         * receiving data.
+         */
+        else if (intr & (EPINTR_EOF | EPINTR_FIFO_EMPTY | EPINTR_FIFO_FULL))
+                handle_ep0(&imx_usb->imx_ep[0]);
+
+        __raw_writel(intr, imx_usb->base + USB_EP_INTR(0));
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t imx_udc_bulk_irq(int irq, void *dev)
+{
+        struct imx_udc_struct *imx_usb = dev;
+        struct imx_ep_struct *imx_ep = &imx_usb->imx_ep[irq - USBD_INT0];
+        int intr = __raw_readl(imx_usb->base + USB_EP_INTR(EP_NO(imx_ep)));
+
+        dump_ep_intr(__func__, irq - USBD_INT0, intr, imx_usb->dev);
+
+        if (!imx_usb->driver) {
+                __raw_writel(intr, imx_usb->base + USB_EP_INTR(EP_NO(imx_ep)));
+                return IRQ_HANDLED;
+        }
+
+        handle_ep(imx_ep);
+
+        __raw_writel(intr, imx_usb->base + USB_EP_INTR(EP_NO(imx_ep)));
+
+        return IRQ_HANDLED;
+}
+
+irq_handler_t intr_handler(int i)
+{
+        switch (i) {
+        case 0:
+                return imx_udc_ctrl_irq;
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+                return imx_udc_bulk_irq;
+        default:
+                return imx_udc_irq;
+        }
+}
+
+/*******************************************************************************
+ * Static defined IMX UDC structure
+ *******************************************************************************
+ */
+
+static const struct usb_gadget_ops imx_udc_ops = {
+        .get_frame       = imx_udc_get_frame,
+        .wakeup          = imx_udc_wakeup,
+};
+
+static struct imx_udc_struct controller = {
+        .gadget = {
+                .ops            = &imx_udc_ops,
+                .ep0            = &controller.imx_ep[0].ep,
+                .name           = driver_name,
+                .dev = {
+                         .bus_id        = "gadget",
+                 },
+        },
+
+        .imx_ep[0] = {
+                .ep = {
+                        .name           = ep0name,
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 32,
+                },
+                .imx_usb                = &controller,
+                .fifosize               = 32,
+                .bEndpointAddress       = 0,
+                .bmAttributes           = USB_ENDPOINT_XFER_CONTROL,
+         },
+        .imx_ep[1] = {
+                .ep = {
+                        .name           = "ep1in-bulk",
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 64,
+                },
+                .imx_usb                = &controller,
+                .fifosize               = 64,
+                .bEndpointAddress       = USB_DIR_IN | 1,
+                .bmAttributes           = USB_ENDPOINT_XFER_BULK,
+         },
+        .imx_ep[2] = {
+                .ep = {
+                        .name           = "ep2out-bulk",
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 64,
+                },
+                .imx_usb                = &controller,
+                .fifosize               = 64,
+                .bEndpointAddress       = USB_DIR_OUT | 2,
+                .bmAttributes           = USB_ENDPOINT_XFER_BULK,
+         },
+        .imx_ep[3] = {
+                .ep = {
+                        .name           = "ep3out-bulk",
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 32,
+                },
+                .imx_usb                = &controller,
+                .fifosize               = 32,
+                .bEndpointAddress       = USB_DIR_OUT | 3,
+                .bmAttributes           = USB_ENDPOINT_XFER_BULK,
+         },
+        .imx_ep[4] = {
+                .ep = {
+                        .name           = "ep4in-int",
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 32,
+                 },
+                .imx_usb                = &controller,
+                .fifosize               = 32,
+                .bEndpointAddress       = USB_DIR_IN | 4,
+                .bmAttributes           = USB_ENDPOINT_XFER_INT,
+         },
+        .imx_ep[5] = {
+                .ep = {
+                        .name           = "ep5out-int",
+                        .ops            = &imx_ep_ops,
+                        .maxpacket      = 32,
+                },
+                .imx_usb                = &controller,
+                .fifosize               = 32,
+                .bEndpointAddress       = USB_DIR_OUT | 5,
+                .bmAttributes           = USB_ENDPOINT_XFER_INT,
+         },
+};
+
+/*******************************************************************************
+ * USB gadged driver functions
+ *******************************************************************************
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+        struct imx_udc_struct *imx_usb = &controller;
+        int retval;
+
+        if (!driver
+                || driver->speed < USB_SPEED_FULL
+                || !driver->bind
+                || !driver->disconnect
+                || !driver->setup)
+                        return -EINVAL;
+        if (!imx_usb)
+                return -ENODEV;
+        if (imx_usb->driver)
+                return -EBUSY;
+
+        /* first hook up the driver ... */
+        imx_usb->driver = driver;
+        imx_usb->gadget.dev.driver = &driver->driver;
+
+        retval = device_add(&imx_usb->gadget.dev);
+        if (retval)
+                goto fail;
+        retval = driver->bind(&imx_usb->gadget);
+        if (retval) {
+                D_ERR(imx_usb->dev, "<%s> bind to driver %s --> error %d\n",
+                        __func__, driver->driver.name, retval);
+                device_del(&imx_usb->gadget.dev);
+
+                goto fail;
+        }
+
+        D_INI(imx_usb->dev, "<%s> registered gadget driver '%s'\n",
+                __func__, driver->driver.name);
+
+        imx_udc_enable(imx_usb);
+
+        return 0;
+fail:
+        imx_usb->driver = NULL;
+        imx_usb->gadget.dev.driver = NULL;
+        return retval;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+        struct imx_udc_struct *imx_usb = &controller;
+
+        if (!imx_usb)
+                return -ENODEV;
+        if (!driver || driver != imx_usb->driver || !driver->unbind)
+                return -EINVAL;
+
+        udc_stop_activity(imx_usb, driver);
+        imx_udc_disable(imx_usb);
+
+        driver->unbind(&imx_usb->gadget);
+        imx_usb->gadget.dev.driver = NULL;
+        imx_usb->driver = NULL;
+
+        device_del(&imx_usb->gadget.dev);
+
+        D_INI(imx_usb->dev, "<%s> unregistered gadget driver '%s'\n",
+                __func__, driver->driver.name);
+
+        return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/*******************************************************************************
+ * Module functions
+ *******************************************************************************
+ */
+
+static int __init imx_udc_probe(struct platform_device *pdev)
+{
+        struct imx_udc_struct *imx_usb = &controller;
+        struct resource *res;
+        struct imxusb_platform_data *pdata;
+        struct clk *clk;
+        void __iomem *base;
+        int ret = 0;
+        int i, res_size;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "can't get device resources\n");
+                return -ENODEV;
+        }
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "driver needs platform data\n");
+                return -ENODEV;
+        }
+
+        res_size = res->end - res->start + 1;
+        if (!request_mem_region(res->start, res_size, res->name)) {
+                dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
+                        res_size, res->start);
+                return -ENOMEM;
+        }
+
+        if (pdata->init) {
+                ret = pdata->init(&pdev->dev);
+                if (ret)
+                        goto fail0;
+        }
+
+        base = ioremap(res->start, res_size);
+        if (!base) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -EIO;
+                goto fail1;
+        }
+
+        clk = clk_get(NULL, "usbd_clk");
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
+                dev_err(&pdev->dev, "can't get USB clock\n");
+                goto fail2;
+        }
+        clk_enable(clk);
+
+        if (clk_get_rate(clk) != 48000000) {
+                D_INI(&pdev->dev,
+                        "Bad USB clock (%d Hz), changing to 48000000 Hz\n",
+                        (int)clk_get_rate(clk));
+                if (clk_set_rate(clk, 48000000)) {
+                        dev_err(&pdev->dev,
+                                "Unable to set correct USB clock (48MHz)\n");
+                        ret = -EIO;
+                        goto fail3;
+                }
+        }
+
+        for (i = 0; i < IMX_USB_NB_EP + 1; i++) {
+                imx_usb->usbd_int[i] = platform_get_irq(pdev, i);
+                if (imx_usb->usbd_int[i] < 0) {
+                        dev_err(&pdev->dev, "can't get irq number\n");
+                        ret = -ENODEV;
+                        goto fail3;
+                }
+        }
+
+        for (i = 0; i < IMX_USB_NB_EP + 1; i++) {
+                ret = request_irq(imx_usb->usbd_int[i], intr_handler(i),
+                                     IRQF_DISABLED, driver_name, imx_usb);
+                if (ret) {
+                        dev_err(&pdev->dev, "can't get irq %i, err %d\n",
+                                imx_usb->usbd_int[i], ret);
+                        for (--i; i >= 0; i--)
+                                free_irq(imx_usb->usbd_int[i], imx_usb);
+                        goto fail3;
+                }
+        }
+
+        imx_usb->res = res;
+        imx_usb->base = base;
+        imx_usb->clk = clk;
+        imx_usb->dev = &pdev->dev;
+
+        device_initialize(&imx_usb->gadget.dev);
+
+        imx_usb->gadget.dev.parent = &pdev->dev;
+        imx_usb->gadget.dev.dma_mask = pdev->dev.dma_mask;
+
+        platform_set_drvdata(pdev, imx_usb);
+
+        usb_init_data(imx_usb);
+        imx_udc_init(imx_usb);
+
+        return 0;
+
+fail3:
+        clk_put(clk);
+        clk_disable(clk);
+fail2:
+        iounmap(base);
+fail1:
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+fail0:
+        release_mem_region(res->start, res_size);
+        return ret;
+}
+
+static int __exit imx_udc_remove(struct platform_device *pdev)
+{
+        struct imx_udc_struct *imx_usb = platform_get_drvdata(pdev);
+        struct imxusb_platform_data *pdata = pdev->dev.platform_data;
+        int i;
+
+        imx_udc_disable(imx_usb);
+
+        for (i = 0; i < IMX_USB_NB_EP + 1; i++)
+                free_irq(imx_usb->usbd_int[i], imx_usb);
+
+        clk_put(imx_usb->clk);
+        clk_disable(imx_usb->clk);
+        iounmap(imx_usb->base);
+
+        release_mem_region(imx_usb->res->start,
+                imx_usb->res->end - imx_usb->res->start + 1);
+
+        if (pdata->exit)
+                pdata->exit(&pdev->dev);
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+#ifdef  CONFIG_PM
+#define imx_udc_suspend NULL
+#define imx_udc_resume  NULL
+#else
+#define imx_udc_suspend NULL
+#define imx_udc_resume  NULL
+#endif
+
+/*----------------------------------------------------------------------------*/
+
+static struct platform_driver udc_driver = {
+        .driver         = {
+                .name   = driver_name,
+                .owner  = THIS_MODULE,
+        },
+        .remove         = __exit_p(imx_udc_remove),
+        .suspend        = imx_udc_suspend,
+        .resume         = imx_udc_resume,
+};
+
+static int __init udc_init(void)
+{
+        return platform_driver_probe(&udc_driver, imx_udc_probe);
+}
+module_init(udc_init);
+
+static void __exit udc_exit(void)
+{
+        platform_driver_unregister(&udc_driver);
+}
+module_exit(udc_exit);
+
+MODULE_DESCRIPTION("IMX USB Device Controller driver");
+MODULE_AUTHOR("Darius Augulis <augulis.darius@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:imx_udc");
diff --git a/drivers/usb/gadget/imx_udc.h b/drivers/usb/gadget/imx_udc.h
new file mode 100644
index 000000000000..850076937d8d
--- /dev/null
+++ b/drivers/usb/gadget/imx_udc.h
@@ -0,0 +1,344 @@
+/*
+ *      Copyright (C) 2005 Mike Lee(eemike@gmail.com)
+ *
+ *      This udc driver is now under testing and code is based on pxa2xx_udc.h
+ *      Please use it with your own risk!
+ *
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ *
+ *      This program is distributed in the hope that it will be useful,
+ *      but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *      GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_USB_GADGET_IMX_H
+#define __LINUX_USB_GADGET_IMX_H
+
+#include <linux/types.h>
+
+/* Helper macros */
+#define EP_NO(ep)       ((ep->bEndpointAddress) & ~USB_DIR_IN) /* IN:1, OUT:0 */
+#define EP_DIR(ep)      ((ep->bEndpointAddress) & USB_DIR_IN ? 1 : 0)
+#define irq_to_ep(irq)  (((irq) >= USBD_INT0) || ((irq) <= USBD_INT6) ? ((irq) - USBD_INT0) : (USBD_INT6)) /*should not happen*/
+#define ep_to_irq(ep)   (EP_NO((ep)) + USBD_INT0)
+#define IMX_USB_NB_EP   6
+
+/* Driver structures */
+struct imx_request {
+        struct usb_request                      req;
+        struct list_head                        queue;
+        unsigned int                            in_use;
+};
+
+enum ep0_state {
+        EP0_IDLE,
+        EP0_IN_DATA_PHASE,
+        EP0_OUT_DATA_PHASE,
+        EP0_CONFIG,
+        EP0_STALL,
+};
+
+struct imx_ep_struct {
+        struct usb_ep                           ep;
+        struct imx_udc_struct                   *imx_usb;
+        struct list_head                        queue;
+        unsigned char                           stopped;
+        unsigned char                           fifosize;
+        unsigned char                           bEndpointAddress;
+        unsigned char                           bmAttributes;
+};
+
+struct imx_udc_struct {
+        struct usb_gadget                       gadget;
+        struct usb_gadget_driver                *driver;
+        struct device                           *dev;
+        struct imx_ep_struct                    imx_ep[IMX_USB_NB_EP];
+        struct clk                              *clk;
+        enum ep0_state                          ep0state;
+        struct resource                         *res;
+        void __iomem                            *base;
+        unsigned char                           set_config;
+        int                                     cfg,
+                                                intf,
+                                                alt,
+                                                usbd_int[7];
+};
+
+/* USB registers */
+#define  USB_FRAME              (0x00)  /* USB frame */
+#define  USB_SPEC               (0x04)  /* USB Spec */
+#define  USB_STAT               (0x08)  /* USB Status */
+#define  USB_CTRL               (0x0C)  /* USB Control */
+#define  USB_DADR               (0x10)  /* USB Desc RAM addr */
+#define  USB_DDAT               (0x14)  /* USB Desc RAM/EP buffer data */
+#define  USB_INTR               (0x18)  /* USB interrupt */
+#define  USB_MASK               (0x1C)  /* USB Mask */
+#define  USB_ENAB               (0x24)  /* USB Enable */
+#define  USB_EP_STAT(x)         (0x30 + (x*0x30)) /* USB status/control */
+#define  USB_EP_INTR(x)         (0x34 + (x*0x30)) /* USB interrupt */
+#define  USB_EP_MASK(x)         (0x38 + (x*0x30)) /* USB mask */
+#define  USB_EP_FDAT(x)         (0x3C + (x*0x30)) /* USB FIFO data */
+#define  USB_EP_FDAT0(x)        (0x3C + (x*0x30)) /* USB FIFO data */
+#define  USB_EP_FDAT1(x)        (0x3D + (x*0x30)) /* USB FIFO data */
+#define  USB_EP_FDAT2(x)        (0x3E + (x*0x30)) /* USB FIFO data */
+#define  USB_EP_FDAT3(x)        (0x3F + (x*0x30)) /* USB FIFO data */
+#define  USB_EP_FSTAT(x)        (0x40 + (x*0x30)) /* USB FIFO status */
+#define  USB_EP_FCTRL(x)        (0x44 + (x*0x30)) /* USB FIFO control */
+#define  USB_EP_LRFP(x)         (0x48 + (x*0x30)) /* USB last read frame pointer */
+#define  USB_EP_LWFP(x)         (0x4C + (x*0x30)) /* USB last write frame pointer */
+#define  USB_EP_FALRM(x)        (0x50 + (x*0x30)) /* USB FIFO alarm */
+#define  USB_EP_FRDP(x)         (0x54 + (x*0x30)) /* USB FIFO read pointer */
+#define  USB_EP_FWRP(x)         (0x58 + (x*0x30)) /* USB FIFO write pointer */
+/* USB Control Register Bit Fields.*/
+#define CTRL_CMDOVER            (1<<6)  /* UDC status */
+#define CTRL_CMDERROR           (1<<5)  /* UDC status */
+#define CTRL_FE_ENA             (1<<3)  /* Enable Font End logic */
+#define CTRL_UDC_RST            (1<<2)  /* UDC reset */
+#define CTRL_AFE_ENA            (1<<1)  /* Analog Font end enable */
+#define CTRL_RESUME             (1<<0)  /* UDC resume */
+/* USB Status Register Bit Fields.*/
+#define STAT_RST                (1<<8)
+#define STAT_SUSP               (1<<7)
+#define STAT_CFG                (3<<5)
+#define STAT_INTF               (3<<3)
+#define STAT_ALTSET             (7<<0)
+/* USB Interrupt Status/Mask Registers Bit fields */
+#define INTR_WAKEUP             (1<<31) /* Wake up Interrupt */
+#define INTR_MSOF               (1<<7)  /* Missed Start of Frame */
+#define INTR_SOF                (1<<6)  /* Start of Frame */
+#define INTR_RESET_STOP         (1<<5)  /* Reset Signaling stop */
+#define INTR_RESET_START        (1<<4)  /* Reset Signaling start */
+#define INTR_RESUME             (1<<3)  /* Suspend to resume */
+#define INTR_SUSPEND            (1<<2)  /* Active to suspend */
+#define INTR_FRAME_MATCH        (1<<1)  /* Frame matched */
+#define INTR_CFG_CHG            (1<<0)  /* Configuration change occurred */
+/* USB Enable Register Bit Fields.*/
+#define ENAB_RST                (1<<31) /* Reset USB modules */
+#define ENAB_ENAB               (1<<30) /* Enable USB modules*/
+#define ENAB_SUSPEND            (1<<29) /* Suspend USB modules */
+#define ENAB_ENDIAN             (1<<28) /* Endian of USB modules */
+#define ENAB_PWRMD              (1<<0)  /* Power mode of USB modules */
+/* USB Descriptor Ram Address Register bit fields */
+#define DADR_CFG                (1<<31) /* Configuration */
+#define DADR_BSY                (1<<30) /* Busy status */
+#define DADR_DADR               (0x1FF) /* Descriptor Ram Address */
+/* USB Descriptor RAM/Endpoint Buffer Data Register bit fields */
+#define DDAT_DDAT               (0xFF)  /* Descriptor Endpoint Buffer */
+/* USB Endpoint Status Register bit fields */
+#define EPSTAT_BCOUNT           (0x7F<<16)      /* Endpoint FIFO byte count */
+#define EPSTAT_SIP              (1<<8)  /* Endpoint setup in progress */
+#define EPSTAT_DIR              (1<<7)  /* Endpoint transfer direction */
+#define EPSTAT_MAX              (3<<5)  /* Endpoint Max packet size */
+#define EPSTAT_TYP              (3<<3)  /* Endpoint type */
+#define EPSTAT_ZLPS             (1<<2)  /* Send zero length packet */
+#define EPSTAT_FLUSH            (1<<1)  /* Endpoint FIFO Flush */
+#define EPSTAT_STALL            (1<<0)  /* Force stall */
+/* USB Endpoint FIFO Status Register bit fields */
+#define FSTAT_FRAME_STAT        (0xF<<24)       /* Frame status bit [0-3] */
+#define FSTAT_ERR               (1<<22) /* FIFO error */
+#define FSTAT_UF                (1<<21) /* FIFO underflow */
+#define FSTAT_OF                (1<<20) /* FIFO overflow */
+#define FSTAT_FR                (1<<19) /* FIFO frame ready */
+#define FSTAT_FULL              (1<<18) /* FIFO full */
+#define FSTAT_ALRM              (1<<17) /* FIFO alarm */
+#define FSTAT_EMPTY             (1<<16) /* FIFO empty */
+/* USB Endpoint FIFO Control Register bit fields */
+#define FCTRL_WFR               (1<<29) /* Write frame end */
+/* USB Endpoint Interrupt Status Regsiter bit fields */
+#define EPINTR_FIFO_FULL        (1<<8)  /* fifo full */
+#define EPINTR_FIFO_EMPTY       (1<<7)  /* fifo empty */
+#define EPINTR_FIFO_ERROR       (1<<6)  /* fifo error */
+#define EPINTR_FIFO_HIGH        (1<<5)  /* fifo high */
+#define EPINTR_FIFO_LOW         (1<<4)  /* fifo low */
+#define EPINTR_MDEVREQ          (1<<3)  /* multi Device request */
+#define EPINTR_EOT              (1<<2)  /* fifo end of transfer */
+#define EPINTR_DEVREQ           (1<<1)  /* Device request */
+#define EPINTR_EOF              (1<<0)  /* fifo end of frame */
+
+/* Debug macros */
+#ifdef DEBUG
+
+/* #define DEBUG_REQ */
+/* #define DEBUG_TRX */
+/* #define DEBUG_INIT */
+/* #define DEBUG_EP0 */
+/* #define DEBUG_EPX */
+/* #define DEBUG_IRQ */
+/* #define DEBUG_EPIRQ */
+/* #define DEBUG_DUMP */
+#define DEBUG_ERR
+
+#ifdef DEBUG_REQ
+        #define D_REQ(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_REQ(dev, args...)     do {} while (0)
+#endif /* DEBUG_REQ */
+
+#ifdef DEBUG_TRX
+        #define D_TRX(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_TRX(dev, args...)     do {} while (0)
+#endif /* DEBUG_TRX */
+
+#ifdef DEBUG_INIT
+        #define D_INI(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_INI(dev, args...)     do {} while (0)
+#endif /* DEBUG_INIT */
+
+#ifdef DEBUG_EP0
+        static const char *state_name[] = {
+                "EP0_IDLE",
+                "EP0_IN_DATA_PHASE",
+                "EP0_OUT_DATA_PHASE",
+                "EP0_CONFIG",
+                "EP0_STALL"
+        };
+        #define D_EP0(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_EP0(dev, args...)     do {} while (0)
+#endif /* DEBUG_EP0 */
+
+#ifdef DEBUG_EPX
+        #define D_EPX(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_EPX(dev, args...)     do {} while (0)
+#endif /* DEBUG_EP0 */
+
+#ifdef DEBUG_IRQ
+        static void dump_intr(const char *label, int irqreg, struct device *dev)
+        {
+                dev_dbg(dev, "<%s> USB_INTR=[%s%s%s%s%s%s%s%s%s]\n", label,
+                        (irqreg & INTR_WAKEUP) ? " wake" : "",
+                        (irqreg & INTR_MSOF) ? " msof" : "",
+                        (irqreg & INTR_SOF) ? " sof" : "",
+                        (irqreg & INTR_RESUME) ? " resume" : "",
+                        (irqreg & INTR_SUSPEND) ? " suspend" : "",
+                        (irqreg & INTR_RESET_STOP) ? " noreset" : "",
+                        (irqreg & INTR_RESET_START) ? " reset" : "",
+                        (irqreg & INTR_FRAME_MATCH) ? " fmatch" : "",
+                        (irqreg & INTR_CFG_CHG) ? " config" : "");
+        }
+#else
+        #define dump_intr(x, y, z)              do {} while (0)
+#endif /* DEBUG_IRQ */
+
+#ifdef DEBUG_EPIRQ
+        static void dump_ep_intr(const char *label, int nr, int irqreg, struct device *dev)
+        {
+                dev_dbg(dev, "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n", label, nr,
+                        (irqreg & EPINTR_FIFO_FULL) ? " full" : "",
+                        (irqreg & EPINTR_FIFO_EMPTY) ? " fempty" : "",
+                        (irqreg & EPINTR_FIFO_ERROR) ? " ferr" : "",
+                        (irqreg & EPINTR_FIFO_HIGH) ? " fhigh" : "",
+                        (irqreg & EPINTR_FIFO_LOW) ? " flow" : "",
+                        (irqreg & EPINTR_MDEVREQ) ? " mreq" : "",
+                        (irqreg & EPINTR_EOF) ? " eof" : "",
+                        (irqreg & EPINTR_DEVREQ) ? " devreq" : "",
+                        (irqreg & EPINTR_EOT) ? " eot" : "");
+        }
+#else
+        #define dump_ep_intr(x, y, z, i)        do {} while (0)
+#endif /* DEBUG_IRQ */
+
+#ifdef DEBUG_DUMP
+        static void dump_usb_stat(const char *label, struct imx_udc_struct *imx_usb)
+        {
+                int temp = __raw_readl(imx_usb->base + USB_STAT);
+
+                dev_dbg(imx_usb->dev,
+                        "<%s> USB_STAT=[%s%s CFG=%d, INTF=%d, ALTR=%d]\n", label,
+                        (temp & STAT_RST) ? " reset" : "",
+                        (temp & STAT_SUSP) ? " suspend" : "",
+                        (temp & STAT_CFG) >> 5,
+                        (temp & STAT_INTF) >> 3,
+                        (temp & STAT_ALTSET));
+        }
+
+        static void dump_ep_stat(const char *label, struct imx_ep_struct *imx_ep)
+        {
+                int temp = __raw_readl(imx_ep->imx_usb->base + USB_EP_INTR(EP_NO(imx_ep)));
+
+                dev_dbg(imx_ep->imx_usb->dev,
+                        "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n", label, EP_NO(imx_ep),
+                        (temp & EPINTR_FIFO_FULL) ? " full" : "",
+                        (temp & EPINTR_FIFO_EMPTY) ? " fempty" : "",
+                        (temp & EPINTR_FIFO_ERROR) ? " ferr" : "",
+                        (temp & EPINTR_FIFO_HIGH) ? " fhigh" : "",
+                        (temp & EPINTR_FIFO_LOW) ? " flow" : "",
+                        (temp & EPINTR_MDEVREQ) ? " mreq" : "",
+                        (temp & EPINTR_EOF) ? " eof" : "",
+                        (temp & EPINTR_DEVREQ) ? " devreq" : "",
+                        (temp & EPINTR_EOT) ? " eot" : "");
+
+                temp = __raw_readl(imx_ep->imx_usb->base + USB_EP_STAT(EP_NO(imx_ep)));
+
+                dev_dbg(imx_ep->imx_usb->dev,
+                        "<%s> EP%d_STAT=[%s%s bcount=%d]\n", label, EP_NO(imx_ep),
+                        (temp & EPSTAT_SIP) ? " sip" : "",
+                        (temp & EPSTAT_STALL) ? " stall" : "",
+                        (temp & EPSTAT_BCOUNT) >> 16);
+
+                temp = __raw_readl(imx_ep->imx_usb->base + USB_EP_FSTAT(EP_NO(imx_ep)));
+
+                dev_dbg(imx_ep->imx_usb->dev,
+                        "<%s> EP%d_FSTAT=[%s%s%s%s%s%s%s]\n", label, EP_NO(imx_ep),
+                        (temp & FSTAT_ERR) ? " ferr" : "",
+                        (temp & FSTAT_UF) ? " funder" : "",
+                        (temp & FSTAT_OF) ? " fover" : "",
+                        (temp & FSTAT_FR) ? " fready" : "",
+                        (temp & FSTAT_FULL) ? " ffull" : "",
+                        (temp & FSTAT_ALRM) ? " falarm" : "",
+                        (temp & FSTAT_EMPTY) ? " fempty" : "");
+        }
+
+        static void dump_req(const char *label, struct imx_ep_struct *imx_ep, struct usb_request *req)
+        {
+                int i;
+
+                if (!req || !req->buf) {
+                        dev_dbg(imx_ep->imx_usb->dev, "<%s> req or req buf is free\n", label);
+                        return;
+                }
+
+                if ((!EP_NO(imx_ep) && imx_ep->imx_usb->ep0state == EP0_IN_DATA_PHASE)
+                        || (EP_NO(imx_ep) && EP_DIR(imx_ep))) {
+
+                        dev_dbg(imx_ep->imx_usb->dev, "<%s> request dump <", label);
+                        for (i = 0; i < req->length; i++)
+                                printk("%02x-", *((u8 *)req->buf + i));
+                        printk(">\n");
+                }
+        }
+
+#else
+        #define dump_ep_stat(x, y)              do {} while (0)
+        #define dump_usb_stat(x, y)             do {} while (0)
+        #define dump_req(x, y, z)               do {} while (0)
+#endif /* DEBUG_DUMP */
+
+#ifdef DEBUG_ERR
+        #define D_ERR(dev, args...)     dev_dbg(dev, ## args)
+#else
+        #define D_ERR(dev, args...)     do {} while (0)
+#endif
+
+#else
+        #define D_REQ(dev, args...)             do {} while (0)
+        #define D_TRX(dev, args...)             do {} while (0)
+        #define D_INI(dev, args...)             do {} while (0)
+        #define D_EP0(dev, args...)             do {} while (0)
+        #define D_EPX(dev, args...)             do {} while (0)
+        #define dump_ep_intr(x, y, z, i)        do {} while (0)
+        #define dump_intr(x, y, z)              do {} while (0)
+        #define dump_ep_stat(x, y)              do {} while (0)
+        #define dump_usb_stat(x, y)             do {} while (0)
+        #define dump_req(x, y, z)               do {} while (0)
+        #define D_ERR(dev, args...)             do {} while (0)
+#endif /* DEBUG */
+
+#endif /* __LINUX_USB_GADGET_IMX_H */
diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
index 3a8879ec2061..43dcf9e1af6b 100644
--- a/drivers/usb/gadget/m66592-udc.c
+++ b/drivers/usb/gadget/m66592-udc.c
@@ -1546,8 +1546,6 @@ static void nop_completion(struct usb_ep *ep, struct usb_request *r)
 {
 }
 
-#define resource_len(r) (((r)->end - (r)->start) + 1)
-
 static int __init m66592_probe(struct platform_device *pdev)
 {
         struct resource *res;
@@ -1560,11 +1558,10 @@ static int __init m66592_probe(struct platform_device *pdev)
         int ret = 0;
         int i;
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-                        (char *)udc_name);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res) {
                 ret = -ENODEV;
-                pr_err("platform_get_resource_byname error.\n");
+                pr_err("platform_get_resource error.\n");
                 goto clean_up;
         }
 
@@ -1575,7 +1572,7 @@ static int __init m66592_probe(struct platform_device *pdev)
                 goto clean_up;
         }
 
-        reg = ioremap(res->start, resource_len(res));
+        reg = ioremap(res->start, resource_size(res));
         if (reg == NULL) {
                 ret = -ENOMEM;
                 pr_err("ioremap error.\n");
diff --git a/drivers/usb/gadget/net2280.c b/drivers/usb/gadget/net2280.c
index 8ae70de2c37d..12c6d83b218c 100644
--- a/drivers/usb/gadget/net2280.c
+++ b/drivers/usb/gadget/net2280.c
@@ -669,7 +669,7 @@ fill_dma_desc (struct net2280_ep *ep, struct net2280_request *req, int valid)
 
         /* 2280 may be polling VALID_BIT through ep->dma->dmadesc */
         wmb ();
-        td->dmacount = cpu_to_le32p (&dmacount);
+        td->dmacount = cpu_to_le32(dmacount);
 }
 
 static const u32 dmactl_default =
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 34e9e393f929..57d9641c6bf8 100644
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -3006,7 +3006,7 @@ cleanup1:
 
 cleanup0:
         if (xceiv)
-                put_device(xceiv->dev);
+                otg_put_transceiver(xceiv);
 
         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
                 clk_disable(hhc_clk);
@@ -3034,7 +3034,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev)
 
         pullup_disable(udc);
         if (udc->transceiver) {
-                put_device(udc->transceiver->dev);
+                otg_put_transceiver(udc->transceiver);
                 udc->transceiver = NULL;
         }
         omap_writew(0, UDC_SYSCON1);
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 697a0ca349bf..9b36205c5759 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -2198,7 +2198,7 @@ static int __init pxa25x_udc_probe(struct platform_device *pdev)
         udc_disable(dev);
         udc_reinit(dev);
 
-        dev->vbus = is_vbus_present();
+        dev->vbus = !!is_vbus_present();
 
         /* irq setup after old hardware state is cleaned up */
         retval = request_irq(irq, pxa25x_udc_irq,
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 65110d02a206..990f40f988d4 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -430,7 +430,6 @@ static void pio_irq_enable(struct pxa_ep *ep)
 /**
  * pio_irq_disable - Disables irq generation for one endpoint
  * @ep: udc endpoint
- * @index: endpoint number
  */
 static void pio_irq_disable(struct pxa_ep *ep)
 {
@@ -586,7 +585,6 @@ static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in)
  * inc_ep_stats_bytes - Update ep stats counts
  * @ep: physical endpoint
  * @count: bytes transfered on endpoint
- * @req: usb request
  * @is_in: ep direction (USB_DIR_IN or 0)
  */
 static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in)
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index c7e255636803..9a2b8920532d 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -36,6 +36,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -51,7 +52,6 @@
 #include <mach/irqs.h>
 
 #include <mach/hardware.h>
-#include <mach/regs-gpio.h>
 
 #include <plat/regs-udc.h>
 #include <plat/udc.h>
@@ -1510,11 +1510,7 @@ static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
 
         dprintk(DEBUG_NORMAL, "%s()\n", __func__);
 
-        /* some cpus cannot read from an line configured to IRQ! */
-        s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_INPUT);
-        value = s3c2410_gpio_getpin(udc_info->vbus_pin);
-        s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_SFN2);
-
+        value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
         if (udc_info->vbus_pin_inverted)
                 value = !value;
 
@@ -1802,7 +1798,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
         struct s3c2410_udc *udc = &memory;
         struct device *dev = &pdev->dev;
         int retval;
-        unsigned int irq;
+        int irq;
 
         dev_dbg(dev, "%s()\n", __func__);
 
@@ -1861,7 +1857,7 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
 
         /* irq setup after old hardware state is cleaned up */
         retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
-                        IRQF_DISABLED, gadget_name, udc);
+                             IRQF_DISABLED, gadget_name, udc);
 
         if (retval != 0) {
                 dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
@@ -1872,17 +1868,28 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
         dev_dbg(dev, "got irq %i\n", IRQ_USBD);
 
         if (udc_info && udc_info->vbus_pin > 0) {
-                irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
+                retval = gpio_request(udc_info->vbus_pin, "udc vbus");
+                if (retval < 0) {
+                        dev_err(dev, "cannot claim vbus pin\n");
+                        goto err_int;
+                }
+
+                irq = gpio_to_irq(udc_info->vbus_pin);
+                if (irq < 0) {
+                        dev_err(dev, "no irq for gpio vbus pin\n");
+                        goto err_gpio_claim;
+                }
+
                 retval = request_irq(irq, s3c2410_udc_vbus_irq,
                                      IRQF_DISABLED | IRQF_TRIGGER_RISING
                                      | IRQF_TRIGGER_FALLING | IRQF_SHARED,
                                      gadget_name, udc);
 
                 if (retval != 0) {
-                        dev_err(dev, "can't get vbus irq %i, err %d\n",
+                        dev_err(dev, "can't get vbus irq %d, err %d\n",
                                 irq, retval);
                         retval = -EBUSY;
-                        goto err_int;
+                        goto err_gpio_claim;
                 }
 
                 dev_dbg(dev, "got irq %i\n", irq);
@@ -1902,6 +1909,9 @@ static int s3c2410_udc_probe(struct platform_device *pdev)
 
         return 0;
 
+err_gpio_claim:
+        if (udc_info && udc_info->vbus_pin > 0)
+                gpio_free(udc_info->vbus_pin);
 err_int:
         free_irq(IRQ_USBD, udc);
 err_map:
@@ -1927,7 +1937,7 @@ static int s3c2410_udc_remove(struct platform_device *pdev)
         debugfs_remove(udc->regs_info);
 
         if (udc_info && udc_info->vbus_pin > 0) {
-                irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
+                irq = gpio_to_irq(udc_info->vbus_pin);
                 free_irq(irq, udc);
         }
 
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f3a75a929e0a..2b476b6b3d4d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -96,6 +96,19 @@ config USB_EHCI_HCD_PPC_OF
           Enables support for the USB controller present on the PowerPC
           OpenFirmware platform bus.
 
+config USB_OXU210HP_HCD
+        tristate "OXU210HP HCD support"
+        depends on USB
+        ---help---
+          The OXU210HP is an USB host/OTG/device controller. Enable this
+          option if your board has this chip. If unsure, say N.
+
+          This driver does not support isochronous transfers and doesn't
+          implement OTG nor USB device controllers.
+
+          To compile this driver as a module, choose M here: the
+          module will be called oxu210hp-hcd.
+
 config USB_ISP116X_HCD
         tristate "ISP116X HCD support"
         depends on USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 23be22224044..e5f3f20787e4 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
 obj-$(CONFIG_PCI)               += pci-quirks.o
 
 obj-$(CONFIG_USB_EHCI_HCD)      += ehci-hcd.o
+obj-$(CONFIG_USB_OXU210HP_HCD)  += oxu210hp-hcd.o
 obj-$(CONFIG_USB_ISP116X_HCD)   += isp116x-hcd.o
 obj-$(CONFIG_USB_OHCI_HCD)      += ohci-hcd.o
 obj-$(CONFIG_USB_UHCI_HCD)      += uhci-hcd.o
diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c
index 0cb53ca8d343..7f4ace73d44a 100644
--- a/drivers/usb/host/ehci-dbg.c
+++ b/drivers/usb/host/ehci-dbg.c
@@ -455,9 +455,7 @@ static void qh_lines (
                                 (scratch >> 16) & 0x7fff,
                                 scratch,
                                 td->urb);
-                if (temp < 0)
-                        temp = 0;
-                else if (size < temp)
+                if (size < temp)
                         temp = size;
                 size -= temp;
                 next += temp;
@@ -466,9 +464,7 @@ static void qh_lines (
         }
 
         temp = snprintf (next, size, "\n");
-        if (temp < 0)
-                temp = 0;
-        else if (size < temp)
+        if (size < temp)
                 temp = size;
         size -= temp;
         next += temp;
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 218f9660d7ee..97a53a48a3d8 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -194,6 +194,7 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
         u32                     temp;
         u32                     power_okay;
         int                     i;
+        u8                      resume_needed = 0;
 
         if (time_before (jiffies, ehci->next_statechange))
                 msleep(5);
@@ -228,7 +229,9 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
 
         /* Some controller/firmware combinations need a delay during which
          * they set up the port statuses.  See Bugzilla #8190. */
-        mdelay(8);
+        spin_unlock_irq(&ehci->lock);
+        msleep(8);
+        spin_lock_irq(&ehci->lock);
 
         /* manually resume the ports we suspended during bus_suspend() */
         i = HCS_N_PORTS (ehci->hcs_params);
@@ -236,12 +239,21 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
                 temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
                 if (test_bit(i, &ehci->bus_suspended) &&
-                                (temp & PORT_SUSPEND))
+                                (temp & PORT_SUSPEND)) {
                         temp |= PORT_RESUME;
+                        resume_needed = 1;
+                }
                 ehci_writel(ehci, temp, &ehci->regs->port_status [i]);
         }
+
+        /* msleep for 20ms only if code is trying to resume port */
+        if (resume_needed) {
+                spin_unlock_irq(&ehci->lock);
+                msleep(20);
+                spin_lock_irq(&ehci->lock);
+        }
+
         i = HCS_N_PORTS (ehci->hcs_params);
-        mdelay (20);
         while (i--) {
                 temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
                 if (test_bit(i, &ehci->bus_suspended) &&
@@ -422,8 +434,15 @@ static int check_reset_complete (
                 port_status &= ~PORT_RWC_BITS;
                 ehci_writel(ehci, port_status, status_reg);
 
-        } else
+                /* ensure 440EPX ohci controller state is operational */
+                if (ehci->has_amcc_usb23)
+                        set_ohci_hcfs(ehci, 1);
+        } else {
                 ehci_dbg (ehci, "port %d high speed\n", index + 1);
+                /* ensure 440EPx ohci controller state is suspended */
+                if (ehci->has_amcc_usb23)
+                        set_ohci_hcfs(ehci, 0);
+        }
 
         return port_status;
 }
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 36864f958444..bdc6e86e1f8b 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -219,15 +219,19 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
         /* Serial Bus Release Number is at PCI 0x60 offset */
         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 
-        /* Workaround current PCI init glitch:  wakeup bits aren't
-         * being set from PCI PM capability.
+        /* Keep this around for a while just in case some EHCI
+         * implementation uses legacy PCI PM support.  This test
+         * can be removed on 17 Dec 2009 if the dev_warn() hasn't
+         * been triggered by then.
          */
         if (!device_can_wakeup(&pdev->dev)) {
                 u16     port_wake;
 
                 pci_read_config_word(pdev, 0x62, &port_wake);
-                if (port_wake & 0x0001)
+                if (port_wake & 0x0001) {
+                        dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
                         device_init_wakeup(&pdev->dev, 1);
+                }
         }
 
 #ifdef  CONFIG_USB_SUSPEND
@@ -428,6 +432,8 @@ static struct pci_driver ehci_pci_driver = {
 
 #ifdef  CONFIG_PM
         .suspend =      usb_hcd_pci_suspend,
+        .suspend_late = usb_hcd_pci_suspend_late,
+        .resume_early = usb_hcd_pci_resume_early,
         .resume =       usb_hcd_pci_resume,
 #endif
         .shutdown =     usb_hcd_pci_shutdown,
diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
index b018deed2e8f..ef732b704f53 100644
--- a/drivers/usb/host/ehci-ppc-of.c
+++ b/drivers/usb/host/ehci-ppc-of.c
@@ -107,11 +107,13 @@ ehci_hcd_ppc_of_probe(struct of_device *op, const struct of_device_id *match)
 {
         struct device_node *dn = op->node;
         struct usb_hcd *hcd;
-        struct ehci_hcd *ehci;
+        struct ehci_hcd *ehci = NULL;
         struct resource res;
         int irq;
         int rv;
 
+        struct device_node *np;
+
         if (usb_disabled())
                 return -ENODEV;
 
@@ -149,6 +151,20 @@ ehci_hcd_ppc_of_probe(struct of_device *op, const struct of_device_id *match)
         }
 
         ehci = hcd_to_ehci(hcd);
+        np = of_find_compatible_node(NULL, NULL, "ibm,usb-ohci-440epx");
+        if (np != NULL) {
+                /* claim we really affected by usb23 erratum */
+                if (!of_address_to_resource(np, 0, &res))
+                        ehci->ohci_hcctrl_reg = ioremap(res.start +
+                                        OHCI_HCCTRL_OFFSET, OHCI_HCCTRL_LEN);
+                else
+                        pr_debug(__FILE__ ": no ohci offset in fdt\n");
+                if (!ehci->ohci_hcctrl_reg) {
+                        pr_debug(__FILE__ ": ioremap for ohci hcctrl failed\n");
+                } else {
+                        ehci->has_amcc_usb23 = 1;
+                }
+        }
 
         if (of_get_property(dn, "big-endian", NULL)) {
                 ehci->big_endian_mmio = 1;
@@ -181,6 +197,9 @@ err_ioremap:
         irq_dispose_mapping(irq);
 err_irq:
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+
+        if (ehci->has_amcc_usb23)
+                iounmap(ehci->ohci_hcctrl_reg);
 err_rmr:
         usb_put_hcd(hcd);
 
@@ -191,6 +210,11 @@ err_rmr:
 static int ehci_hcd_ppc_of_remove(struct of_device *op)
 {
         struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+        struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+        struct device_node *np;
+        struct resource res;
+
         dev_set_drvdata(&op->dev, NULL);
 
         dev_dbg(&op->dev, "stopping PPC-OF USB Controller\n");
@@ -201,6 +225,25 @@ static int ehci_hcd_ppc_of_remove(struct of_device *op)
         irq_dispose_mapping(hcd->irq);
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 
+        /* use request_mem_region to test if the ohci driver is loaded.  if so
+         * ensure the ohci core is operational.
+         */
+        if (ehci->has_amcc_usb23) {
+                np = of_find_compatible_node(NULL, NULL, "ibm,usb-ohci-440epx");
+                if (np != NULL) {
+                        if (!of_address_to_resource(np, 0, &res))
+                                if (!request_mem_region(res.start,
+                                                            0x4, hcd_name))
+                                        set_ohci_hcfs(ehci, 1);
+                                else
+                                        release_mem_region(res.start, 0x4);
+                        else
+                                pr_debug(__FILE__ ": no ohci offset in fdt\n");
+                        of_node_put(np);
+                }
+
+                iounmap(ehci->ohci_hcctrl_reg);
+        }
         usb_put_hcd(hcd);
 
         return 0;
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index c7d4b5a06bdb..fb7054ccf4fc 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -120,6 +120,16 @@ struct ehci_hcd {			/* one per controller */
         unsigned                has_fsl_port_bug:1; /* FreeScale */
         unsigned                big_endian_mmio:1;
         unsigned                big_endian_desc:1;
+        unsigned                has_amcc_usb23:1;
+
+        /* required for usb32 quirk */
+        #define OHCI_CTRL_HCFS          (3 << 6)
+        #define OHCI_USB_OPER           (2 << 6)
+        #define OHCI_USB_SUSPEND        (3 << 6)
+
+        #define OHCI_HCCTRL_OFFSET      0x4
+        #define OHCI_HCCTRL_LEN         0x4
+        __hc32                  *ohci_hcctrl_reg;
 
         u8                      sbrn;           /* packed release number */
 
@@ -636,6 +646,30 @@ static inline void ehci_writel(const struct ehci_hcd *ehci,
 #endif
 }
 
+/*
+ * On certain ppc-44x SoC there is a HW issue, that could only worked around with
+ * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
+ * Other common bits are dependant on has_amcc_usb23 quirk flag.
+ */
+#ifdef CONFIG_44x
+static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
+{
+        u32 hc_control;
+
+        hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
+        if (operational)
+                hc_control |= OHCI_USB_OPER;
+        else
+                hc_control |= OHCI_USB_SUSPEND;
+
+        writel_be(hc_control, ehci->ohci_hcctrl_reg);
+        (void) readl_be(ehci->ohci_hcctrl_reg);
+}
+#else
+static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
+{ }
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 /*
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
index 8017f1cf78e2..b899f1a59c26 100644
--- a/drivers/usb/host/isp1760-hcd.c
+++ b/drivers/usb/host/isp1760-hcd.c
@@ -435,14 +435,13 @@ static int isp1760_hc_setup(struct usb_hcd *hcd)
 
         /*
          * PORT 1 Control register of the ISP1760 is the OTG control
-         * register on ISP1761.
+         * register on ISP1761. Since there is no OTG or device controller
+         * support in this driver, we use port 1 as a "normal" USB host port on
+         * both chips.
          */
-        if (!(priv->devflags & ISP1760_FLAG_ISP1761) &&
-            !(priv->devflags & ISP1760_FLAG_PORT1_DIS)) {
-                isp1760_writel(PORT1_POWER | PORT1_INIT2,
-                               hcd->regs + HC_PORT1_CTRL);
-                mdelay(10);
-        }
+        isp1760_writel(PORT1_POWER | PORT1_INIT2,
+                       hcd->regs + HC_PORT1_CTRL);
+        mdelay(10);
 
         priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
 
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 4377277667d9..a9daea587962 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -135,7 +135,6 @@ typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
  * indicate the most "atypical" case, so that a devflags of 0 is
  * a sane default configuration.
  */
-#define ISP1760_FLAG_PORT1_DIS          0x00000001 /* Port 1 disabled */
 #define ISP1760_FLAG_BUS_WIDTH_16       0x00000002 /* 16-bit data bus width */
 #define ISP1760_FLAG_OTG_EN             0x00000004 /* Port 1 supports OTG */
 #define ISP1760_FLAG_ANALOG_OC          0x00000008 /* Analog overcurrent */
diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c
index b87ca7cf4b37..4cf7ca428b33 100644
--- a/drivers/usb/host/isp1760-if.c
+++ b/drivers/usb/host/isp1760-if.c
@@ -60,9 +60,6 @@ static int of_isp1760_probe(struct of_device *dev,
         if (of_device_is_compatible(dp, "nxp,usb-isp1761"))
                 devflags |= ISP1760_FLAG_ISP1761;
 
-        if (of_get_property(dp, "port1-disable", NULL) != NULL)
-                devflags |= ISP1760_FLAG_PORT1_DIS;
-
         /* Some systems wire up only 16 of the 32 data lines */
         prop = of_get_property(dp, "bus-width", NULL);
         if (prop && *prop == 16)
@@ -129,23 +126,23 @@ static struct of_platform_driver isp1760_of_driver = {
 #endif
 
 #ifdef CONFIG_PCI
-static u32 nxp_pci_io_base;
-static u32 iolength;
-static u32 pci_mem_phy0;
-static u32 length;
-static u8 __iomem *chip_addr;
-static u8 __iomem *iobase;
-
 static int __devinit isp1761_pci_probe(struct pci_dev *dev,
                 const struct pci_device_id *id)
 {
         u8 latency, limit;
         __u32 reg_data;
         int retry_count;
-        int length;
-        int status = 1;
         struct usb_hcd *hcd;
         unsigned int devflags = 0;
+        int ret_status = 0;
+
+        resource_size_t pci_mem_phy0;
+        resource_size_t memlength;
+
+        u8 __iomem *chip_addr;
+        u8 __iomem *iobase;
+        resource_size_t nxp_pci_io_base;
+        resource_size_t iolength;
 
         if (usb_disabled())
                 return -ENODEV;
@@ -168,26 +165,30 @@ static int __devinit isp1761_pci_probe(struct pci_dev *dev,
         iobase = ioremap_nocache(nxp_pci_io_base, iolength);
         if (!iobase) {
                 printk(KERN_ERR "ioremap #1\n");
-                release_mem_region(nxp_pci_io_base, iolength);
-                return -ENOMEM;
+                ret_status = -ENOMEM;
+                goto cleanup1;
         }
         /* Grab the PLX PCI shared memory of the ISP 1761 we need  */
         pci_mem_phy0 = pci_resource_start(dev, 3);
-        length = pci_resource_len(dev, 3);
-
-        if (length < 0xffff) {
-                printk(KERN_ERR "memory length for this resource is less than "
-                                "required\n");
-                release_mem_region(nxp_pci_io_base, iolength);
-                iounmap(iobase);
-                return  -ENOMEM;
+        memlength = pci_resource_len(dev, 3);
+        if (memlength < 0xffff) {
+                printk(KERN_ERR "memory length for this resource is wrong\n");
+                ret_status = -ENOMEM;
+                goto cleanup2;
         }
 
-        if (!request_mem_region(pci_mem_phy0, length, "ISP-PCI")) {
+        if (!request_mem_region(pci_mem_phy0, memlength, "ISP-PCI")) {
                 printk(KERN_ERR "host controller already in use\n");
-                release_mem_region(nxp_pci_io_base, iolength);
-                iounmap(iobase);
-                return -EBUSY;
+                ret_status = -EBUSY;
+                goto cleanup2;
+        }
+
+        /* map available memory */
+        chip_addr = ioremap_nocache(pci_mem_phy0,memlength);
+        if (!chip_addr) {
+                printk(KERN_ERR "Error ioremap failed\n");
+                ret_status = -ENOMEM;
+                goto cleanup3;
         }
 
         /* bad pci latencies can contribute to overruns */
@@ -210,39 +211,54 @@ static int __devinit isp1761_pci_probe(struct pci_dev *dev,
                  * */
                 writel(0xface, chip_addr + HC_SCRATCH_REG);
                 udelay(100);
-                reg_data = readl(chip_addr + HC_SCRATCH_REG);
+                reg_data = readl(chip_addr + HC_SCRATCH_REG) & 0x0000ffff;
                 retry_count--;
         }
 
+        iounmap(chip_addr);
+
         /* Host Controller presence is detected by writing to scratch register
          * and reading back and checking the contents are same or not
          */
         if (reg_data != 0xFACE) {
                 dev_err(&dev->dev, "scratch register mismatch %x\n", reg_data);
-                goto clean;
+                ret_status = -ENOMEM;
+                goto cleanup3;
         }
 
         pci_set_master(dev);
 
-        status = readl(iobase + 0x68);
-        status |= 0x900;
-        writel(status, iobase + 0x68);
+        /* configure PLX PCI chip to pass interrupts */
+#define PLX_INT_CSR_REG 0x68
+        reg_data = readl(iobase + PLX_INT_CSR_REG);
+        reg_data |= 0x900;
+        writel(reg_data, iobase + PLX_INT_CSR_REG);
 
         dev->dev.dma_mask = NULL;
-        hcd = isp1760_register(pci_mem_phy0, length, dev->irq,
+        hcd = isp1760_register(pci_mem_phy0, memlength, dev->irq,
                 IRQF_SHARED | IRQF_DISABLED, &dev->dev, dev_name(&dev->dev),
                 devflags);
-        if (!IS_ERR(hcd)) {
-                pci_set_drvdata(dev, hcd);
-                return 0;
+        if (IS_ERR(hcd)) {
+                ret_status = -ENODEV;
+                goto cleanup3;
         }
-clean:
-        status = -ENODEV;
+
+        /* done with PLX IO access */
+        iounmap(iobase);
+        release_mem_region(nxp_pci_io_base, iolength);
+
+        pci_set_drvdata(dev, hcd);
+        return 0;
+
+cleanup3:
+        release_mem_region(pci_mem_phy0, memlength);
+cleanup2:
         iounmap(iobase);
-        release_mem_region(pci_mem_phy0, length);
+cleanup1:
         release_mem_region(nxp_pci_io_base, iolength);
-        return status;
+        return ret_status;
 }
+
 static void isp1761_pci_remove(struct pci_dev *dev)
 {
         struct usb_hcd *hcd;
@@ -255,12 +271,6 @@ static void isp1761_pci_remove(struct pci_dev *dev)
         usb_put_hcd(hcd);
 
         pci_disable_device(dev);
-
-        iounmap(iobase);
-        iounmap(chip_addr);
-
-        release_mem_region(nxp_pci_io_base, iolength);
-        release_mem_region(pci_mem_phy0, length);
 }
 
 static void isp1761_pci_shutdown(struct pci_dev *dev)
@@ -268,12 +278,16 @@ static void isp1761_pci_shutdown(struct pci_dev *dev)
         printk(KERN_ERR "ips1761_pci_shutdown\n");
 }
 
-static const struct pci_device_id isp1760_plx [] = { {
-        /* handle any USB 2.0 EHCI controller */
-        PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_OTHER << 8) | (0x06 << 16)), ~0),
-                .driver_data = 0,
-},
-{ /* end: all zeroes */ }
+static const struct pci_device_id isp1760_plx [] = {
+        {
+                .class          = PCI_CLASS_BRIDGE_OTHER << 8,
+                .class_mask     = ~0,
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = 0x5406,
+                .subvendor      = PCI_VENDOR_ID_PLX,
+                .subdevice      = 0x9054,
+        },
+        { }
 };
 MODULE_DEVICE_TABLE(pci, isp1760_plx);
 
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 8aa3f4556a32..65a9609f4ad6 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -589,13 +589,15 @@ static int ohci_run (struct ohci_hcd *ohci)
                 /* also: power/overcurrent flags in roothub.a */
         }
 
-        /* Reset USB nearly "by the book".  RemoteWakeupConnected was
-         * saved if boot firmware (BIOS/SMM/...) told us it's connected,
-         * or if bus glue did the same (e.g. for PCI add-in cards with
-         * PCI PM support).
+        /* Reset USB nearly "by the book".  RemoteWakeupConnected has
+         * to be checked in case boot firmware (BIOS/SMM/...) has set up
+         * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
+         * If the bus glue detected wakeup capability then it should
+         * already be enabled.  Either way, if wakeup should be enabled
+         * but isn't, we'll enable it now.
          */
         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0
-                        && !device_may_wakeup(hcd->self.controller))
+                        && !device_can_wakeup(hcd->self.controller))
                 device_init_wakeup(hcd->self.controller, 1);
 
         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index a9c2ae36c7ad..8b28ae7865ba 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -355,9 +355,9 @@ static int __devinit ohci_pci_start (struct usb_hcd *hcd)
 
                 /* RWC may not be set for add-in PCI cards, since boot
                  * firmware probably ignored them.  This transfers PCI
-                 * PM wakeup capabilities (once the PCI layer is fixed).
+                 * PM wakeup capabilities.
                  */
-                if (device_may_wakeup(&pdev->dev))
+                if (device_can_wakeup(&pdev->dev))
                         ohci->hc_control |= OHCI_CTRL_RWC;
         }
 #endif /* CONFIG_PM */
@@ -487,6 +487,8 @@ static struct pci_driver ohci_pci_driver = {
 
 #ifdef  CONFIG_PM
         .suspend =      usb_hcd_pci_suspend,
+        .suspend_late = usb_hcd_pci_suspend_late,
+        .resume_early = usb_hcd_pci_resume_early,
         .resume =       usb_hcd_pci_resume,
 #endif
 
diff --git a/drivers/usb/host/ohci-pnx4008.c b/drivers/usb/host/ohci-pnx4008.c
index e306ca6aef3d..100bf3d8437c 100644
--- a/drivers/usb/host/ohci-pnx4008.c
+++ b/drivers/usb/host/ohci-pnx4008.c
@@ -106,65 +106,34 @@ extern int ocpi_enable(void);
 
 static struct clk *usb_clk;
 
-static int isp1301_probe(struct i2c_adapter *adap);
-static int isp1301_detach(struct i2c_client *client);
-
 static const unsigned short normal_i2c[] =
     { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
-static const unsigned short dummy_i2c_addrlist[] = { I2C_CLIENT_END };
-
-static struct i2c_client_address_data addr_data = {
-        .normal_i2c = normal_i2c,
-        .probe = dummy_i2c_addrlist,
-        .ignore = dummy_i2c_addrlist,
-};
-
-struct i2c_driver isp1301_driver = {
-        .driver = {
-                .name = "isp1301_pnx",
-        },
-        .attach_adapter = isp1301_probe,
-        .detach_client = isp1301_detach,
-};
 
-static int isp1301_attach(struct i2c_adapter *adap, int addr, int kind)
+static int isp1301_probe(struct i2c_client *client,
+                         const struct i2c_device_id *id)
 {
-        struct i2c_client *c;
-        int err;
-
-        c = kzalloc(sizeof(*c), GFP_KERNEL);
-        if (!c)
-                return -ENOMEM;
-
-        strlcpy(c->name, "isp1301_pnx", I2C_NAME_SIZE);
-        c->flags = 0;
-        c->addr = addr;
-        c->adapter = adap;
-        c->driver = &isp1301_driver;
-
-        err = i2c_attach_client(c);
-        if (err) {
-                kfree(c);
-                return err;
-        }
-
-        isp1301_i2c_client = c;
-
         return 0;
 }
 
-static int isp1301_probe(struct i2c_adapter *adap)
+static int isp1301_remove(struct i2c_client *client)
 {
-        return i2c_probe(adap, &addr_data, isp1301_attach);
-}
-
-static int isp1301_detach(struct i2c_client *client)
-{
-        i2c_detach_client(client);
-        kfree(isp1301_i2c_client);
         return 0;
 }
 
+const struct i2c_device_id isp1301_id[] = {
+        { "isp1301_pnx", 0 },
+        { }
+};
+
+struct i2c_driver isp1301_driver = {
+        .driver = {
+                .name = "isp1301_pnx",
+        },
+        .probe = isp1301_probe,
+        .remove = isp1301_remove,
+        .id_table = isp1301_id,
+};
+
 static void i2c_write(u8 buf, u8 subaddr)
 {
         char tmpbuf[2];
@@ -328,6 +297,8 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
         struct usb_hcd *hcd = 0;
         struct ohci_hcd *ohci;
         const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+        struct i2c_adapter *i2c_adap;
+        struct i2c_board_info i2c_info;
 
         int ret = 0, irq;
 
@@ -351,9 +322,20 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 
         ret = i2c_add_driver(&isp1301_driver);
         if (ret < 0) {
-                err("failed to connect I2C to ISP1301 USB Transceiver");
+                err("failed to add ISP1301 driver");
                 goto out;
         }
+        i2c_adap = i2c_get_adapter(2);
+        memset(&i2c_info, 0, sizeof(struct i2c_board_info));
+        strlcpy(i2c_info.name, "isp1301_pnx", I2C_NAME_SIZE);
+        isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
+                                                   normal_i2c);
+        i2c_put_adapter(i2c_adap);
+        if (!isp1301_i2c_client) {
+                err("failed to connect I2C to ISP1301 USB Transceiver");
+                ret = -ENODEV;
+                goto out_i2c_driver;
+        }
 
         isp1301_configure();
 
@@ -429,6 +411,9 @@ out3:
 out2:
         clk_put(usb_clk);
 out1:
+        i2c_unregister_client(isp1301_i2c_client);
+        isp1301_i2c_client = NULL;
+out_i2c_driver:
         i2c_del_driver(&isp1301_driver);
 out:
         return ret;
@@ -445,6 +430,8 @@ static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
         pnx4008_unset_usb_bits();
         clk_disable(usb_clk);
         clk_put(usb_clk);
+        i2c_unregister_client(isp1301_i2c_client);
+        isp1301_i2c_client = NULL;
         i2c_del_driver(&isp1301_driver);
 
         platform_set_drvdata(pdev, NULL);
diff --git a/drivers/usb/host/ohci-ppc-of.c b/drivers/usb/host/ohci-ppc-of.c
index 7ac53264ead3..68a301710297 100644
--- a/drivers/usb/host/ohci-ppc-of.c
+++ b/drivers/usb/host/ohci-ppc-of.c
@@ -91,6 +91,7 @@ ohci_hcd_ppc_of_probe(struct of_device *op, const struct of_device_id *match)
 
         int rv;
         int is_bigendian;
+        struct device_node *np;
 
         if (usb_disabled())
                 return -ENODEV;
@@ -147,6 +148,30 @@ ohci_hcd_ppc_of_probe(struct of_device *op, const struct of_device_id *match)
         if (rv == 0)
                 return 0;
 
+        /* by now, 440epx is known to show usb_23 erratum */
+        np = of_find_compatible_node(NULL, NULL, "ibm,usb-ehci-440epx");
+
+        /* Work around - At this point ohci_run has executed, the
+        * controller is running, everything, the root ports, etc., is
+        * set up.  If the ehci driver is loaded, put the ohci core in
+        * the suspended state.  The ehci driver will bring it out of
+        * suspended state when / if a non-high speed USB device is
+        * attached to the USB Host port.  If the ehci driver is not
+        * loaded, do nothing. request_mem_region is used to test if
+        * the ehci driver is loaded.
+        */
+        if (np !=  NULL) {
+                if (!of_address_to_resource(np, 0, &res)) {
+                        if (!request_mem_region(res.start, 0x4, hcd_name)) {
+                                writel_be((readl_be(&ohci->regs->control) |
+                                        OHCI_USB_SUSPEND), &ohci->regs->control);
+                                        (void) readl_be(&ohci->regs->control);
+                        } else
+                                release_mem_region(res.start, 0x4);
+                } else
+                    pr_debug(__FILE__ ": cannot get ehci offset from fdt\n");
+        }
+
         iounmap(hcd->regs);
 err_ioremap:
         irq_dispose_mapping(irq);
diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c
index f9f134af0bd1..8dabe8e31d8c 100644
--- a/drivers/usb/host/ohci-tmio.c
+++ b/drivers/usb/host/ohci-tmio.c
@@ -201,7 +201,7 @@ static int __devinit ohci_hcd_tmio_drv_probe(struct platform_device *dev)
         if (!cell)
                 return -EINVAL;
 
-        hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev->dev.bus_id);
+        hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
         if (!hcd) {
                 ret = -ENOMEM;
                 goto err_usb_create_hcd;
diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
new file mode 100644
index 000000000000..75548f7c716b
--- /dev/null
+++ b/drivers/usb/host/oxu210hp-hcd.c
@@ -0,0 +1,3985 @@
+/*
+ * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
+ *
+ * This code is *strongly* based on EHCI-HCD code by David Brownell since
+ * the chip is a quasi-EHCI compatible.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/dmapool.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/reboot.h>
+#include <linux/usb.h>
+#include <linux/moduleparam.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include "../core/hcd.h"
+
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include "oxu210hp.h"
+
+#define DRIVER_VERSION "0.0.50"
+
+/*
+ * Main defines
+ */
+
+#define oxu_dbg(oxu, fmt, args...) \
+                dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
+#define oxu_err(oxu, fmt, args...) \
+                dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
+#define oxu_info(oxu, fmt, args...) \
+                dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
+
+static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
+{
+        return container_of((void *) oxu, struct usb_hcd, hcd_priv);
+}
+
+static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
+{
+        return (struct oxu_hcd *) (hcd->hcd_priv);
+}
+
+/*
+ * Debug stuff
+ */
+
+#undef OXU_URB_TRACE
+#undef OXU_VERBOSE_DEBUG
+
+#ifdef OXU_VERBOSE_DEBUG
+#define oxu_vdbg                        oxu_dbg
+#else
+#define oxu_vdbg(oxu, fmt, args...)     /* Nop */
+#endif
+
+#ifdef DEBUG
+
+static int __attribute__((__unused__))
+dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
+{
+        return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
+                label, label[0] ? " " : "", status,
+                (status & STS_ASS) ? " Async" : "",
+                (status & STS_PSS) ? " Periodic" : "",
+                (status & STS_RECL) ? " Recl" : "",
+                (status & STS_HALT) ? " Halt" : "",
+                (status & STS_IAA) ? " IAA" : "",
+                (status & STS_FATAL) ? " FATAL" : "",
+                (status & STS_FLR) ? " FLR" : "",
+                (status & STS_PCD) ? " PCD" : "",
+                (status & STS_ERR) ? " ERR" : "",
+                (status & STS_INT) ? " INT" : ""
+                );
+}
+
+static int __attribute__((__unused__))
+dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
+{
+        return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
+                label, label[0] ? " " : "", enable,
+                (enable & STS_IAA) ? " IAA" : "",
+                (enable & STS_FATAL) ? " FATAL" : "",
+                (enable & STS_FLR) ? " FLR" : "",
+                (enable & STS_PCD) ? " PCD" : "",
+                (enable & STS_ERR) ? " ERR" : "",
+                (enable & STS_INT) ? " INT" : ""
+                );
+}
+
+static const char *const fls_strings[] =
+    { "1024", "512", "256", "??" };
+
+static int dbg_command_buf(char *buf, unsigned len,
+                                const char *label, u32 command)
+{
+        return scnprintf(buf, len,
+                "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
+                label, label[0] ? " " : "", command,
+                (command & CMD_PARK) ? "park" : "(park)",
+                CMD_PARK_CNT(command),
+                (command >> 16) & 0x3f,
+                (command & CMD_LRESET) ? " LReset" : "",
+                (command & CMD_IAAD) ? " IAAD" : "",
+                (command & CMD_ASE) ? " Async" : "",
+                (command & CMD_PSE) ? " Periodic" : "",
+                fls_strings[(command >> 2) & 0x3],
+                (command & CMD_RESET) ? " Reset" : "",
+                (command & CMD_RUN) ? "RUN" : "HALT"
+                );
+}
+
+static int dbg_port_buf(char *buf, unsigned len, const char *label,
+                                int port, u32 status)
+{
+        char    *sig;
+
+        /* signaling state */
+        switch (status & (3 << 10)) {
+        case 0 << 10:
+                sig = "se0";
+                break;
+        case 1 << 10:
+                sig = "k";      /* low speed */
+                break;
+        case 2 << 10:
+                sig = "j";
+                break;
+        default:
+                sig = "?";
+                break;
+        }
+
+        return scnprintf(buf, len,
+                "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
+                label, label[0] ? " " : "", port, status,
+                (status & PORT_POWER) ? " POWER" : "",
+                (status & PORT_OWNER) ? " OWNER" : "",
+                sig,
+                (status & PORT_RESET) ? " RESET" : "",
+                (status & PORT_SUSPEND) ? " SUSPEND" : "",
+                (status & PORT_RESUME) ? " RESUME" : "",
+                (status & PORT_OCC) ? " OCC" : "",
+                (status & PORT_OC) ? " OC" : "",
+                (status & PORT_PEC) ? " PEC" : "",
+                (status & PORT_PE) ? " PE" : "",
+                (status & PORT_CSC) ? " CSC" : "",
+                (status & PORT_CONNECT) ? " CONNECT" : ""
+            );
+}
+
+#else
+
+static inline int __attribute__((__unused__))
+dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
+{ return 0; }
+
+static inline int __attribute__((__unused__))
+dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
+{ return 0; }
+
+static inline int __attribute__((__unused__))
+dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
+{ return 0; }
+
+static inline int __attribute__((__unused__))
+dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
+{ return 0; }
+
+#endif /* DEBUG */
+
+/* functions have the "wrong" filename when they're output... */
+#define dbg_status(oxu, label, status) { \
+        char _buf[80]; \
+        dbg_status_buf(_buf, sizeof _buf, label, status); \
+        oxu_dbg(oxu, "%s\n", _buf); \
+}
+
+#define dbg_cmd(oxu, label, command) { \
+        char _buf[80]; \
+        dbg_command_buf(_buf, sizeof _buf, label, command); \
+        oxu_dbg(oxu, "%s\n", _buf); \
+}
+
+#define dbg_port(oxu, label, port, status) { \
+        char _buf[80]; \
+        dbg_port_buf(_buf, sizeof _buf, label, port, status); \
+        oxu_dbg(oxu, "%s\n", _buf); \
+}
+
+/*
+ * Module parameters
+ */
+
+/* Initial IRQ latency: faster than hw default */
+static int log2_irq_thresh;                     /* 0 to 6 */
+module_param(log2_irq_thresh, int, S_IRUGO);
+MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
+
+/* Initial park setting: slower than hw default */
+static unsigned park;
+module_param(park, uint, S_IRUGO);
+MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
+
+/* For flakey hardware, ignore overcurrent indicators */
+static int ignore_oc;
+module_param(ignore_oc, bool, S_IRUGO);
+MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
+
+
+static void ehci_work(struct oxu_hcd *oxu);
+static int oxu_hub_control(struct usb_hcd *hcd,
+                                u16 typeReq, u16 wValue, u16 wIndex,
+                                char *buf, u16 wLength);
+
+/*
+ * Local functions
+ */
+
+/* Low level read/write registers functions */
+static inline u32 oxu_readl(void *base, u32 reg)
+{
+        return readl(base + reg);
+}
+
+static inline void oxu_writel(void *base, u32 reg, u32 val)
+{
+        writel(val, base + reg);
+}
+
+static inline void timer_action_done(struct oxu_hcd *oxu,
+                                        enum ehci_timer_action action)
+{
+        clear_bit(action, &oxu->actions);
+}
+
+static inline void timer_action(struct oxu_hcd *oxu,
+                                        enum ehci_timer_action action)
+{
+        if (!test_and_set_bit(action, &oxu->actions)) {
+                unsigned long t;
+
+                switch (action) {
+                case TIMER_IAA_WATCHDOG:
+                        t = EHCI_IAA_JIFFIES;
+                        break;
+                case TIMER_IO_WATCHDOG:
+                        t = EHCI_IO_JIFFIES;
+                        break;
+                case TIMER_ASYNC_OFF:
+                        t = EHCI_ASYNC_JIFFIES;
+                        break;
+                case TIMER_ASYNC_SHRINK:
+                default:
+                        t = EHCI_SHRINK_JIFFIES;
+                        break;
+                }
+                t += jiffies;
+                /* all timings except IAA watchdog can be overridden.
+                 * async queue SHRINK often precedes IAA.  while it's ready
+                 * to go OFF neither can matter, and afterwards the IO
+                 * watchdog stops unless there's still periodic traffic.
+                 */
+                if (action != TIMER_IAA_WATCHDOG
+                                && t > oxu->watchdog.expires
+                                && timer_pending(&oxu->watchdog))
+                        return;
+                mod_timer(&oxu->watchdog, t);
+        }
+}
+
+/*
+ * handshake - spin reading hc until handshake completes or fails
+ * @ptr: address of hc register to be read
+ * @mask: bits to look at in result of read
+ * @done: value of those bits when handshake succeeds
+ * @usec: timeout in microseconds
+ *
+ * Returns negative errno, or zero on success
+ *
+ * Success happens when the "mask" bits have the specified value (hardware
+ * handshake done).  There are two failure modes:  "usec" have passed (major
+ * hardware flakeout), or the register reads as all-ones (hardware removed).
+ *
+ * That last failure should_only happen in cases like physical cardbus eject
+ * before driver shutdown. But it also seems to be caused by bugs in cardbus
+ * bridge shutdown:  shutting down the bridge before the devices using it.
+ */
+static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
+                                        u32 mask, u32 done, int usec)
+{
+        u32 result;
+
+        do {
+                result = readl(ptr);
+                if (result == ~(u32)0)          /* card removed */
+                        return -ENODEV;
+                result &= mask;
+                if (result == done)
+                        return 0;
+                udelay(1);
+                usec--;
+        } while (usec > 0);
+        return -ETIMEDOUT;
+}
+
+/* Force HC to halt state from unknown (EHCI spec section 2.3) */
+static int ehci_halt(struct oxu_hcd *oxu)
+{
+        u32     temp = readl(&oxu->regs->status);
+
+        /* disable any irqs left enabled by previous code */
+        writel(0, &oxu->regs->intr_enable);
+
+        if ((temp & STS_HALT) != 0)
+                return 0;
+
+        temp = readl(&oxu->regs->command);
+        temp &= ~CMD_RUN;
+        writel(temp, &oxu->regs->command);
+        return handshake(oxu, &oxu->regs->status,
+                          STS_HALT, STS_HALT, 16 * 125);
+}
+
+/* Put TDI/ARC silicon into EHCI mode */
+static void tdi_reset(struct oxu_hcd *oxu)
+{
+        u32 __iomem *reg_ptr;
+        u32 tmp;
+
+        reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
+        tmp = readl(reg_ptr);
+        tmp |= 0x3;
+        writel(tmp, reg_ptr);
+}
+
+/* Reset a non-running (STS_HALT == 1) controller */
+static int ehci_reset(struct oxu_hcd *oxu)
+{
+        int     retval;
+        u32     command = readl(&oxu->regs->command);
+
+        command |= CMD_RESET;
+        dbg_cmd(oxu, "reset", command);
+        writel(command, &oxu->regs->command);
+        oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+        oxu->next_statechange = jiffies;
+        retval = handshake(oxu, &oxu->regs->command,
+                            CMD_RESET, 0, 250 * 1000);
+
+        if (retval)
+                return retval;
+
+        tdi_reset(oxu);
+
+        return retval;
+}
+
+/* Idle the controller (from running) */
+static void ehci_quiesce(struct oxu_hcd *oxu)
+{
+        u32     temp;
+
+#ifdef DEBUG
+        if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
+                BUG();
+#endif
+
+        /* wait for any schedule enables/disables to take effect */
+        temp = readl(&oxu->regs->command) << 10;
+        temp &= STS_ASS | STS_PSS;
+        if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
+                                temp, 16 * 125) != 0) {
+                oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+                return;
+        }
+
+        /* then disable anything that's still active */
+        temp = readl(&oxu->regs->command);
+        temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
+        writel(temp, &oxu->regs->command);
+
+        /* hardware can take 16 microframes to turn off ... */
+        if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
+                                0, 16 * 125) != 0) {
+                oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+                return;
+        }
+}
+
+static int check_reset_complete(struct oxu_hcd *oxu, int index,
+                                u32 __iomem *status_reg, int port_status)
+{
+        if (!(port_status & PORT_CONNECT)) {
+                oxu->reset_done[index] = 0;
+                return port_status;
+        }
+
+        /* if reset finished and it's still not enabled -- handoff */
+        if (!(port_status & PORT_PE)) {
+                oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
+                                index+1);
+                return port_status;
+        } else
+                oxu_dbg(oxu, "port %d high speed\n", index + 1);
+
+        return port_status;
+}
+
+static void ehci_hub_descriptor(struct oxu_hcd *oxu,
+                                struct usb_hub_descriptor *desc)
+{
+        int ports = HCS_N_PORTS(oxu->hcs_params);
+        u16 temp;
+
+        desc->bDescriptorType = 0x29;
+        desc->bPwrOn2PwrGood = 10;      /* oxu 1.0, 2.3.9 says 20ms max */
+        desc->bHubContrCurrent = 0;
+
+        desc->bNbrPorts = ports;
+        temp = 1 + (ports / 8);
+        desc->bDescLength = 7 + 2 * temp;
+
+        /* two bitmaps:  ports removable, and usb 1.0 legacy PortPwrCtrlMask */
+        memset(&desc->bitmap[0], 0, temp);
+        memset(&desc->bitmap[temp], 0xff, temp);
+
+        temp = 0x0008;                  /* per-port overcurrent reporting */
+        if (HCS_PPC(oxu->hcs_params))
+                temp |= 0x0001;         /* per-port power control */
+        else
+                temp |= 0x0002;         /* no power switching */
+        desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
+}
+
+
+/* Allocate an OXU210HP on-chip memory data buffer
+ *
+ * An on-chip memory data buffer is required for each OXU210HP USB transfer.
+ * Each transfer descriptor has one or more on-chip memory data buffers.
+ *
+ * Data buffers are allocated from a fix sized pool of data blocks.
+ * To minimise fragmentation and give reasonable memory utlisation,
+ * data buffers are allocated with sizes the power of 2 multiples of
+ * the block size, starting on an address a multiple of the allocated size.
+ *
+ * FIXME: callers of this function require a buffer to be allocated for
+ * len=0. This is a waste of on-chip memory and should be fix. Then this
+ * function should be changed to not allocate a buffer for len=0.
+ */
+static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
+{
+        int n_blocks;   /* minium blocks needed to hold len */
+        int a_blocks;   /* blocks allocated */
+        int i, j;
+
+        /* Don't allocte bigger than supported */
+        if (len > BUFFER_SIZE * BUFFER_NUM) {
+                oxu_err(oxu, "buffer too big (%d)\n", len);
+                return -ENOMEM;
+        }
+
+        spin_lock(&oxu->mem_lock);
+
+        /* Number of blocks needed to hold len */
+        n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
+
+        /* Round the number of blocks up to the power of 2 */
+        for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
+                ;
+
+        /* Find a suitable available data buffer */
+        for (i = 0; i < BUFFER_NUM;
+                        i += max(a_blocks, (int)oxu->db_used[i])) {
+
+                /* Check all the required blocks are available */
+                for (j = 0; j < a_blocks; j++)
+                        if (oxu->db_used[i + j])
+                                break;
+
+                if (j != a_blocks)
+                        continue;
+
+                /* Allocate blocks found! */
+                qtd->buffer = (void *) &oxu->mem->db_pool[i];
+                qtd->buffer_dma = virt_to_phys(qtd->buffer);
+
+                qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
+                oxu->db_used[i] = a_blocks;
+
+                spin_unlock(&oxu->mem_lock);
+
+                return 0;
+        }
+
+        /* Failed */
+
+        spin_unlock(&oxu->mem_lock);
+
+        return -ENOMEM;
+}
+
+static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
+{
+        int index;
+
+        spin_lock(&oxu->mem_lock);
+
+        index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
+                                                         / BUFFER_SIZE;
+        oxu->db_used[index] = 0;
+        qtd->qtd_buffer_len = 0;
+        qtd->buffer_dma = 0;
+        qtd->buffer = NULL;
+
+        spin_unlock(&oxu->mem_lock);
+
+        return;
+}
+
+static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
+{
+        memset(qtd, 0, sizeof *qtd);
+        qtd->qtd_dma = dma;
+        qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
+        qtd->hw_next = EHCI_LIST_END;
+        qtd->hw_alt_next = EHCI_LIST_END;
+        INIT_LIST_HEAD(&qtd->qtd_list);
+}
+
+static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
+{
+        int index;
+
+        if (qtd->buffer)
+                oxu_buf_free(oxu, qtd);
+
+        spin_lock(&oxu->mem_lock);
+
+        index = qtd - &oxu->mem->qtd_pool[0];
+        oxu->qtd_used[index] = 0;
+
+        spin_unlock(&oxu->mem_lock);
+
+        return;
+}
+
+static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
+{
+        int i;
+        struct ehci_qtd *qtd = NULL;
+
+        spin_lock(&oxu->mem_lock);
+
+        for (i = 0; i < QTD_NUM; i++)
+                if (!oxu->qtd_used[i])
+                        break;
+
+        if (i < QTD_NUM) {
+                qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
+                memset(qtd, 0, sizeof *qtd);
+
+                qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
+                qtd->hw_next = EHCI_LIST_END;
+                qtd->hw_alt_next = EHCI_LIST_END;
+                INIT_LIST_HEAD(&qtd->qtd_list);
+
+                qtd->qtd_dma = virt_to_phys(qtd);
+
+                oxu->qtd_used[i] = 1;
+        }
+
+        spin_unlock(&oxu->mem_lock);
+
+        return qtd;
+}
+
+static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        int index;
+
+        spin_lock(&oxu->mem_lock);
+
+        index = qh - &oxu->mem->qh_pool[0];
+        oxu->qh_used[index] = 0;
+
+        spin_unlock(&oxu->mem_lock);
+
+        return;
+}
+
+static void qh_destroy(struct kref *kref)
+{
+        struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
+        struct oxu_hcd *oxu = qh->oxu;
+
+        /* clean qtds first, and know this is not linked */
+        if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
+                oxu_dbg(oxu, "unused qh not empty!\n");
+                BUG();
+        }
+        if (qh->dummy)
+                oxu_qtd_free(oxu, qh->dummy);
+        oxu_qh_free(oxu, qh);
+}
+
+static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
+{
+        int i;
+        struct ehci_qh *qh = NULL;
+
+        spin_lock(&oxu->mem_lock);
+
+        for (i = 0; i < QHEAD_NUM; i++)
+                if (!oxu->qh_used[i])
+                        break;
+
+        if (i < QHEAD_NUM) {
+                qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
+                memset(qh, 0, sizeof *qh);
+
+                kref_init(&qh->kref);
+                qh->oxu = oxu;
+                qh->qh_dma = virt_to_phys(qh);
+                INIT_LIST_HEAD(&qh->qtd_list);
+
+                /* dummy td enables safe urb queuing */
+                qh->dummy = ehci_qtd_alloc(oxu);
+                if (qh->dummy == NULL) {
+                        oxu_dbg(oxu, "no dummy td\n");
+                        oxu->qh_used[i] = 0;
+
+                        return NULL;
+                }
+
+                oxu->qh_used[i] = 1;
+        }
+
+        spin_unlock(&oxu->mem_lock);
+
+        return qh;
+}
+
+/* to share a qh (cpu threads, or hc) */
+static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
+{
+        kref_get(&qh->kref);
+        return qh;
+}
+
+static inline void qh_put(struct ehci_qh *qh)
+{
+        kref_put(&qh->kref, qh_destroy);
+}
+
+static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
+{
+        int index;
+
+        spin_lock(&oxu->mem_lock);
+
+        index = murb - &oxu->murb_pool[0];
+        oxu->murb_used[index] = 0;
+
+        spin_unlock(&oxu->mem_lock);
+
+        return;
+}
+
+static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
+
+{
+        int i;
+        struct oxu_murb *murb = NULL;
+
+        spin_lock(&oxu->mem_lock);
+
+        for (i = 0; i < MURB_NUM; i++)
+                if (!oxu->murb_used[i])
+                        break;
+
+        if (i < MURB_NUM) {
+                murb = &(oxu->murb_pool)[i];
+
+                oxu->murb_used[i] = 1;
+        }
+
+        spin_unlock(&oxu->mem_lock);
+
+        return murb;
+}
+
+/* The queue heads and transfer descriptors are managed from pools tied
+ * to each of the "per device" structures.
+ * This is the initialisation and cleanup code.
+ */
+static void ehci_mem_cleanup(struct oxu_hcd *oxu)
+{
+        kfree(oxu->murb_pool);
+        oxu->murb_pool = NULL;
+
+        if (oxu->async)
+                qh_put(oxu->async);
+        oxu->async = NULL;
+
+        del_timer(&oxu->urb_timer);
+
+        oxu->periodic = NULL;
+
+        /* shadow periodic table */
+        kfree(oxu->pshadow);
+        oxu->pshadow = NULL;
+}
+
+/* Remember to add cleanup code (above) if you add anything here.
+ */
+static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
+{
+        int i;
+
+        for (i = 0; i < oxu->periodic_size; i++)
+                oxu->mem->frame_list[i] = EHCI_LIST_END;
+        for (i = 0; i < QHEAD_NUM; i++)
+                oxu->qh_used[i] = 0;
+        for (i = 0; i < QTD_NUM; i++)
+                oxu->qtd_used[i] = 0;
+
+        oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
+        if (!oxu->murb_pool)
+                goto fail;
+
+        for (i = 0; i < MURB_NUM; i++)
+                oxu->murb_used[i] = 0;
+
+        oxu->async = oxu_qh_alloc(oxu);
+        if (!oxu->async)
+                goto fail;
+
+        oxu->periodic = (__le32 *) &oxu->mem->frame_list;
+        oxu->periodic_dma = virt_to_phys(oxu->periodic);
+
+        for (i = 0; i < oxu->periodic_size; i++)
+                oxu->periodic[i] = EHCI_LIST_END;
+
+        /* software shadow of hardware table */
+        oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
+        if (oxu->pshadow != NULL)
+                return 0;
+
+fail:
+        oxu_dbg(oxu, "couldn't init memory\n");
+        ehci_mem_cleanup(oxu);
+        return -ENOMEM;
+}
+
+/* Fill a qtd, returning how much of the buffer we were able to queue up.
+ */
+static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
+                                int token, int maxpacket)
+{
+        int i, count;
+        u64 addr = buf;
+
+        /* one buffer entry per 4K ... first might be short or unaligned */
+        qtd->hw_buf[0] = cpu_to_le32((u32)addr);
+        qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
+        count = 0x1000 - (buf & 0x0fff);        /* rest of that page */
+        if (likely(len < count))                /* ... iff needed */
+                count = len;
+        else {
+                buf +=  0x1000;
+                buf &= ~0x0fff;
+
+                /* per-qtd limit: from 16K to 20K (best alignment) */
+                for (i = 1; count < len && i < 5; i++) {
+                        addr = buf;
+                        qtd->hw_buf[i] = cpu_to_le32((u32)addr);
+                        qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
+                        buf += 0x1000;
+                        if ((count + 0x1000) < len)
+                                count += 0x1000;
+                        else
+                                count = len;
+                }
+
+                /* short packets may only terminate transfers */
+                if (count != len)
+                        count -= (count % maxpacket);
+        }
+        qtd->hw_token = cpu_to_le32((count << 16) | token);
+        qtd->length = count;
+
+        return count;
+}
+
+static inline void qh_update(struct oxu_hcd *oxu,
+                                struct ehci_qh *qh, struct ehci_qtd *qtd)
+{
+        /* writes to an active overlay are unsafe */
+        BUG_ON(qh->qh_state != QH_STATE_IDLE);
+
+        qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
+        qh->hw_alt_next = EHCI_LIST_END;
+
+        /* Except for control endpoints, we make hardware maintain data
+         * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
+         * and set the pseudo-toggle in udev. Only usb_clear_halt() will
+         * ever clear it.
+         */
+        if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
+                unsigned        is_out, epnum;
+
+                is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
+                epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
+                if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
+                        qh->hw_token &= ~__constant_cpu_to_le32(QTD_TOGGLE);
+                        usb_settoggle(qh->dev, epnum, is_out, 1);
+                }
+        }
+
+        /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
+        wmb();
+        qh->hw_token &= __constant_cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
+}
+
+/* If it weren't for a common silicon quirk (writing the dummy into the qh
+ * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
+ * recovery (including urb dequeue) would need software changes to a QH...
+ */
+static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        struct ehci_qtd *qtd;
+
+        if (list_empty(&qh->qtd_list))
+                qtd = qh->dummy;
+        else {
+                qtd = list_entry(qh->qtd_list.next,
+                                struct ehci_qtd, qtd_list);
+                /* first qtd may already be partially processed */
+                if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
+                        qtd = NULL;
+        }
+
+        if (qtd)
+                qh_update(oxu, qh, qtd);
+}
+
+static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
+                                size_t length, u32 token)
+{
+        /* count IN/OUT bytes, not SETUP (even short packets) */
+        if (likely(QTD_PID(token) != 2))
+                urb->actual_length += length - QTD_LENGTH(token);
+
+        /* don't modify error codes */
+        if (unlikely(urb->status != -EINPROGRESS))
+                return;
+
+        /* force cleanup after short read; not always an error */
+        if (unlikely(IS_SHORT_READ(token)))
+                urb->status = -EREMOTEIO;
+
+        /* serious "can't proceed" faults reported by the hardware */
+        if (token & QTD_STS_HALT) {
+                if (token & QTD_STS_BABBLE) {
+                        /* FIXME "must" disable babbling device's port too */
+                        urb->status = -EOVERFLOW;
+                } else if (token & QTD_STS_MMF) {
+                        /* fs/ls interrupt xfer missed the complete-split */
+                        urb->status = -EPROTO;
+                } else if (token & QTD_STS_DBE) {
+                        urb->status = (QTD_PID(token) == 1) /* IN ? */
+                                ? -ENOSR  /* hc couldn't read data */
+                                : -ECOMM; /* hc couldn't write data */
+                } else if (token & QTD_STS_XACT) {
+                        /* timeout, bad crc, wrong PID, etc; retried */
+                        if (QTD_CERR(token))
+                                urb->status = -EPIPE;
+                        else {
+                                oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
+                                        urb->dev->devpath,
+                                        usb_pipeendpoint(urb->pipe),
+                                        usb_pipein(urb->pipe) ? "in" : "out");
+                                urb->status = -EPROTO;
+                        }
+                /* CERR nonzero + no errors + halt --> stall */
+                } else if (QTD_CERR(token))
+                        urb->status = -EPIPE;
+                else    /* unknown */
+                        urb->status = -EPROTO;
+
+                oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
+                        usb_pipedevice(urb->pipe),
+                        usb_pipeendpoint(urb->pipe),
+                        usb_pipein(urb->pipe) ? "in" : "out",
+                        token, urb->status);
+        }
+}
+
+static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
+__releases(oxu->lock)
+__acquires(oxu->lock)
+{
+        if (likely(urb->hcpriv != NULL)) {
+                struct ehci_qh  *qh = (struct ehci_qh *) urb->hcpriv;
+
+                /* S-mask in a QH means it's an interrupt urb */
+                if ((qh->hw_info2 & __constant_cpu_to_le32(QH_SMASK)) != 0) {
+
+                        /* ... update hc-wide periodic stats (for usbfs) */
+                        oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
+                }
+                qh_put(qh);
+        }
+
+        urb->hcpriv = NULL;
+        switch (urb->status) {
+        case -EINPROGRESS:              /* success */
+                urb->status = 0;
+        default:                        /* fault */
+                break;
+        case -EREMOTEIO:                /* fault or normal */
+                if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
+                        urb->status = 0;
+                break;
+        case -ECONNRESET:               /* canceled */
+        case -ENOENT:
+                break;
+        }
+
+#ifdef OXU_URB_TRACE
+        oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
+                __func__, urb->dev->devpath, urb,
+                usb_pipeendpoint(urb->pipe),
+                usb_pipein(urb->pipe) ? "in" : "out",
+                urb->status,
+                urb->actual_length, urb->transfer_buffer_length);
+#endif
+
+        /* complete() can reenter this HCD */
+        spin_unlock(&oxu->lock);
+        usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
+        spin_lock(&oxu->lock);
+}
+
+static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
+static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
+
+static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
+static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
+
+#define HALT_BIT __constant_cpu_to_le32(QTD_STS_HALT)
+
+/* Process and free completed qtds for a qh, returning URBs to drivers.
+ * Chases up to qh->hw_current.  Returns number of completions called,
+ * indicating how much "real" work we did.
+ */
+static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        struct ehci_qtd *last = NULL, *end = qh->dummy;
+        struct list_head *entry, *tmp;
+        int stopped;
+        unsigned count = 0;
+        int do_status = 0;
+        u8 state;
+        struct oxu_murb *murb = NULL;
+
+        if (unlikely(list_empty(&qh->qtd_list)))
+                return count;
+
+        /* completions (or tasks on other cpus) must never clobber HALT
+         * till we've gone through and cleaned everything up, even when
+         * they add urbs to this qh's queue or mark them for unlinking.
+         *
+         * NOTE:  unlinking expects to be done in queue order.
+         */
+        state = qh->qh_state;
+        qh->qh_state = QH_STATE_COMPLETING;
+        stopped = (state == QH_STATE_IDLE);
+
+        /* remove de-activated QTDs from front of queue.
+         * after faults (including short reads), cleanup this urb
+         * then let the queue advance.
+         * if queue is stopped, handles unlinks.
+         */
+        list_for_each_safe(entry, tmp, &qh->qtd_list) {
+                struct ehci_qtd *qtd;
+                struct urb *urb;
+                u32 token = 0;
+
+                qtd = list_entry(entry, struct ehci_qtd, qtd_list);
+                urb = qtd->urb;
+
+                /* Clean up any state from previous QTD ...*/
+                if (last) {
+                        if (likely(last->urb != urb)) {
+                                if (last->urb->complete == NULL) {
+                                        murb = (struct oxu_murb *) last->urb;
+                                        last->urb = murb->main;
+                                        if (murb->last) {
+                                                ehci_urb_done(oxu, last->urb);
+                                                count++;
+                                        }
+                                        oxu_murb_free(oxu, murb);
+                                } else {
+                                        ehci_urb_done(oxu, last->urb);
+                                        count++;
+                                }
+                        }
+                        oxu_qtd_free(oxu, last);
+                        last = NULL;
+                }
+
+                /* ignore urbs submitted during completions we reported */
+                if (qtd == end)
+                        break;
+
+                /* hardware copies qtd out of qh overlay */
+                rmb();
+                token = le32_to_cpu(qtd->hw_token);
+
+                /* always clean up qtds the hc de-activated */
+                if ((token & QTD_STS_ACTIVE) == 0) {
+
+                        if ((token & QTD_STS_HALT) != 0) {
+                                stopped = 1;
+
+                        /* magic dummy for some short reads; qh won't advance.
+                         * that silicon quirk can kick in with this dummy too.
+                         */
+                        } else if (IS_SHORT_READ(token) &&
+                                        !(qtd->hw_alt_next & EHCI_LIST_END)) {
+                                stopped = 1;
+                                goto halt;
+                        }
+
+                /* stop scanning when we reach qtds the hc is using */
+                } else if (likely(!stopped &&
+                                HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
+                        break;
+
+                } else {
+                        stopped = 1;
+
+                        if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
+                                urb->status = -ESHUTDOWN;
+
+                        /* ignore active urbs unless some previous qtd
+                         * for the urb faulted (including short read) or
+                         * its urb was canceled.  we may patch qh or qtds.
+                         */
+                        if (likely(urb->status == -EINPROGRESS))
+                                continue;
+
+                        /* issue status after short control reads */
+                        if (unlikely(do_status != 0)
+                                        && QTD_PID(token) == 0 /* OUT */) {
+                                do_status = 0;
+                                continue;
+                        }
+
+                        /* token in overlay may be most current */
+                        if (state == QH_STATE_IDLE
+                                        && cpu_to_le32(qtd->qtd_dma)
+                                                == qh->hw_current)
+                                token = le32_to_cpu(qh->hw_token);
+
+                        /* force halt for unlinked or blocked qh, so we'll
+                         * patch the qh later and so that completions can't
+                         * activate it while we "know" it's stopped.
+                         */
+                        if ((HALT_BIT & qh->hw_token) == 0) {
+halt:
+                                qh->hw_token |= HALT_BIT;
+                                wmb();
+                        }
+                }
+
+                /* Remove it from the queue */
+                qtd_copy_status(oxu, urb->complete ?
+                                        urb : ((struct oxu_murb *) urb)->main,
+                                qtd->length, token);
+                if ((usb_pipein(qtd->urb->pipe)) &&
+                                (NULL != qtd->transfer_buffer))
+                        memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
+                do_status = (urb->status == -EREMOTEIO)
+                                && usb_pipecontrol(urb->pipe);
+
+                if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
+                        last = list_entry(qtd->qtd_list.prev,
+                                        struct ehci_qtd, qtd_list);
+                        last->hw_next = qtd->hw_next;
+                }
+                list_del(&qtd->qtd_list);
+                last = qtd;
+        }
+
+        /* last urb's completion might still need calling */
+        if (likely(last != NULL)) {
+                if (last->urb->complete == NULL) {
+                        murb = (struct oxu_murb *) last->urb;
+                        last->urb = murb->main;
+                        if (murb->last) {
+                                ehci_urb_done(oxu, last->urb);
+                                count++;
+                        }
+                        oxu_murb_free(oxu, murb);
+                } else {
+                        ehci_urb_done(oxu, last->urb);
+                        count++;
+                }
+                oxu_qtd_free(oxu, last);
+        }
+
+        /* restore original state; caller must unlink or relink */
+        qh->qh_state = state;
+
+        /* be sure the hardware's done with the qh before refreshing
+         * it after fault cleanup, or recovering from silicon wrongly
+         * overlaying the dummy qtd (which reduces DMA chatter).
+         */
+        if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
+                switch (state) {
+                case QH_STATE_IDLE:
+                        qh_refresh(oxu, qh);
+                        break;
+                case QH_STATE_LINKED:
+                        /* should be rare for periodic transfers,
+                         * except maybe high bandwidth ...
+                         */
+                        if ((__constant_cpu_to_le32(QH_SMASK)
+                                        & qh->hw_info2) != 0) {
+                                intr_deschedule(oxu, qh);
+                                (void) qh_schedule(oxu, qh);
+                        } else
+                                unlink_async(oxu, qh);
+                        break;
+                /* otherwise, unlink already started */
+                }
+        }
+
+        return count;
+}
+
+/* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
+#define hb_mult(wMaxPacketSize)         (1 + (((wMaxPacketSize) >> 11) & 0x03))
+/* ... and packet size, for any kind of endpoint descriptor */
+#define max_packet(wMaxPacketSize)      ((wMaxPacketSize) & 0x07ff)
+
+/* Reverse of qh_urb_transaction: free a list of TDs.
+ * used for cleanup after errors, before HC sees an URB's TDs.
+ */
+static void qtd_list_free(struct oxu_hcd *oxu,
+                                struct urb *urb, struct list_head *qtd_list)
+{
+        struct list_head *entry, *temp;
+
+        list_for_each_safe(entry, temp, qtd_list) {
+                struct ehci_qtd *qtd;
+
+                qtd = list_entry(entry, struct ehci_qtd, qtd_list);
+                list_del(&qtd->qtd_list);
+                oxu_qtd_free(oxu, qtd);
+        }
+}
+
+/* Create a list of filled qtds for this URB; won't link into qh.
+ */
+static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
+                                                struct urb *urb,
+                                                struct list_head *head,
+                                                gfp_t flags)
+{
+        struct ehci_qtd *qtd, *qtd_prev;
+        dma_addr_t buf;
+        int len, maxpacket;
+        int is_input;
+        u32 token;
+        void *transfer_buf = NULL;
+        int ret;
+
+        /*
+         * URBs map to sequences of QTDs: one logical transaction
+         */
+        qtd = ehci_qtd_alloc(oxu);
+        if (unlikely(!qtd))
+                return NULL;
+        list_add_tail(&qtd->qtd_list, head);
+        qtd->urb = urb;
+
+        token = QTD_STS_ACTIVE;
+        token |= (EHCI_TUNE_CERR << 10);
+        /* for split transactions, SplitXState initialized to zero */
+
+        len = urb->transfer_buffer_length;
+        is_input = usb_pipein(urb->pipe);
+        if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
+                urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
+
+        if (usb_pipecontrol(urb->pipe)) {
+                /* SETUP pid */
+                ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
+                if (ret)
+                        goto cleanup;
+
+                qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
+                                token | (2 /* "setup" */ << 8), 8);
+                memcpy(qtd->buffer, qtd->urb->setup_packet,
+                                sizeof(struct usb_ctrlrequest));
+
+                /* ... and always at least one more pid */
+                token ^= QTD_TOGGLE;
+                qtd_prev = qtd;
+                qtd = ehci_qtd_alloc(oxu);
+                if (unlikely(!qtd))
+                        goto cleanup;
+                qtd->urb = urb;
+                qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
+                list_add_tail(&qtd->qtd_list, head);
+
+                /* for zero length DATA stages, STATUS is always IN */
+                if (len == 0)
+                        token |= (1 /* "in" */ << 8);
+        }
+
+        /*
+         * Data transfer stage: buffer setup
+         */
+
+        ret = oxu_buf_alloc(oxu, qtd, len);
+        if (ret)
+                goto cleanup;
+
+        buf = qtd->buffer_dma;
+        transfer_buf = urb->transfer_buffer;
+
+        if (!is_input)
+                memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
+
+        if (is_input)
+                token |= (1 /* "in" */ << 8);
+        /* else it's already initted to "out" pid (0 << 8) */
+
+        maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
+
+        /*
+         * buffer gets wrapped in one or more qtds;
+         * last one may be "short" (including zero len)
+         * and may serve as a control status ack
+         */
+        for (;;) {
+                int this_qtd_len;
+
+                this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
+                qtd->transfer_buffer = transfer_buf;
+                len -= this_qtd_len;
+                buf += this_qtd_len;
+                transfer_buf += this_qtd_len;
+                if (is_input)
+                        qtd->hw_alt_next = oxu->async->hw_alt_next;
+
+                /* qh makes control packets use qtd toggle; maybe switch it */
+                if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
+                        token ^= QTD_TOGGLE;
+
+                if (likely(len <= 0))
+                        break;
+
+                qtd_prev = qtd;
+                qtd = ehci_qtd_alloc(oxu);
+                if (unlikely(!qtd))
+                        goto cleanup;
+                if (likely(len > 0)) {
+                        ret = oxu_buf_alloc(oxu, qtd, len);
+                        if (ret)
+                                goto cleanup;
+                }
+                qtd->urb = urb;
+                qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
+                list_add_tail(&qtd->qtd_list, head);
+        }
+
+        /* unless the bulk/interrupt caller wants a chance to clean
+         * up after short reads, hc should advance qh past this urb
+         */
+        if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
+                                || usb_pipecontrol(urb->pipe)))
+                qtd->hw_alt_next = EHCI_LIST_END;
+
+        /*
+         * control requests may need a terminating data "status" ack;
+         * bulk ones may need a terminating short packet (zero length).
+         */
+        if (likely(urb->transfer_buffer_length != 0)) {
+                int     one_more = 0;
+
+                if (usb_pipecontrol(urb->pipe)) {
+                        one_more = 1;
+                        token ^= 0x0100;        /* "in" <--> "out"  */
+                        token |= QTD_TOGGLE;    /* force DATA1 */
+                } else if (usb_pipebulk(urb->pipe)
+                                && (urb->transfer_flags & URB_ZERO_PACKET)
+                                && !(urb->transfer_buffer_length % maxpacket)) {
+                        one_more = 1;
+                }
+                if (one_more) {
+                        qtd_prev = qtd;
+                        qtd = ehci_qtd_alloc(oxu);
+                        if (unlikely(!qtd))
+                                goto cleanup;
+                        qtd->urb = urb;
+                        qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
+                        list_add_tail(&qtd->qtd_list, head);
+
+                        /* never any data in such packets */
+                        qtd_fill(qtd, 0, 0, token, 0);
+                }
+        }
+
+        /* by default, enable interrupt on urb completion */
+                qtd->hw_token |= __constant_cpu_to_le32(QTD_IOC);
+        return head;
+
+cleanup:
+        qtd_list_free(oxu, urb, head);
+        return NULL;
+}
+
+/* Each QH holds a qtd list; a QH is used for everything except iso.
+ *
+ * For interrupt urbs, the scheduler must set the microframe scheduling
+ * mask(s) each time the QH gets scheduled.  For highspeed, that's
+ * just one microframe in the s-mask.  For split interrupt transactions
+ * there are additional complications: c-mask, maybe FSTNs.
+ */
+static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
+                                struct urb *urb, gfp_t flags)
+{
+        struct ehci_qh *qh = oxu_qh_alloc(oxu);
+        u32 info1 = 0, info2 = 0;
+        int is_input, type;
+        int maxp = 0;
+
+        if (!qh)
+                return qh;
+
+        /*
+         * init endpoint/device data for this QH
+         */
+        info1 |= usb_pipeendpoint(urb->pipe) << 8;
+        info1 |= usb_pipedevice(urb->pipe) << 0;
+
+        is_input = usb_pipein(urb->pipe);
+        type = usb_pipetype(urb->pipe);
+        maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
+
+        /* Compute interrupt scheduling parameters just once, and save.
+         * - allowing for high bandwidth, how many nsec/uframe are used?
+         * - split transactions need a second CSPLIT uframe; same question
+         * - splits also need a schedule gap (for full/low speed I/O)
+         * - qh has a polling interval
+         *
+         * For control/bulk requests, the HC or TT handles these.
+         */
+        if (type == PIPE_INTERRUPT) {
+                qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
+                                                                is_input, 0,
+                                hb_mult(maxp) * max_packet(maxp)));
+                qh->start = NO_FRAME;
+
+                if (urb->dev->speed == USB_SPEED_HIGH) {
+                        qh->c_usecs = 0;
+                        qh->gap_uf = 0;
+
+                        qh->period = urb->interval >> 3;
+                        if (qh->period == 0 && urb->interval != 1) {
+                                /* NOTE interval 2 or 4 uframes could work.
+                                 * But interval 1 scheduling is simpler, and
+                                 * includes high bandwidth.
+                                 */
+                                dbg("intr period %d uframes, NYET!",
+                                                urb->interval);
+                                goto done;
+                        }
+                } else {
+                        struct usb_tt   *tt = urb->dev->tt;
+                        int             think_time;
+
+                        /* gap is f(FS/LS transfer times) */
+                        qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
+                                        is_input, 0, maxp) / (125 * 1000);
+
+                        /* FIXME this just approximates SPLIT/CSPLIT times */
+                        if (is_input) {         /* SPLIT, gap, CSPLIT+DATA */
+                                qh->c_usecs = qh->usecs + HS_USECS(0);
+                                qh->usecs = HS_USECS(1);
+                        } else {                /* SPLIT+DATA, gap, CSPLIT */
+                                qh->usecs += HS_USECS(1);
+                                qh->c_usecs = HS_USECS(0);
+                        }
+
+                        think_time = tt ? tt->think_time : 0;
+                        qh->tt_usecs = NS_TO_US(think_time +
+                                        usb_calc_bus_time(urb->dev->speed,
+                                        is_input, 0, max_packet(maxp)));
+                        qh->period = urb->interval;
+                }
+        }
+
+        /* support for tt scheduling, and access to toggles */
+        qh->dev = urb->dev;
+
+        /* using TT? */
+        switch (urb->dev->speed) {
+        case USB_SPEED_LOW:
+                info1 |= (1 << 12);     /* EPS "low" */
+                /* FALL THROUGH */
+
+        case USB_SPEED_FULL:
+                /* EPS 0 means "full" */
+                if (type != PIPE_INTERRUPT)
+                        info1 |= (EHCI_TUNE_RL_TT << 28);
+                if (type == PIPE_CONTROL) {
+                        info1 |= (1 << 27);     /* for TT */
+                        info1 |= 1 << 14;       /* toggle from qtd */
+                }
+                info1 |= maxp << 16;
+
+                info2 |= (EHCI_TUNE_MULT_TT << 30);
+                info2 |= urb->dev->ttport << 23;
+
+                /* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
+
+                break;
+
+        case USB_SPEED_HIGH:            /* no TT involved */
+                info1 |= (2 << 12);     /* EPS "high" */
+                if (type == PIPE_CONTROL) {
+                        info1 |= (EHCI_TUNE_RL_HS << 28);
+                        info1 |= 64 << 16;      /* usb2 fixed maxpacket */
+                        info1 |= 1 << 14;       /* toggle from qtd */
+                        info2 |= (EHCI_TUNE_MULT_HS << 30);
+                } else if (type == PIPE_BULK) {
+                        info1 |= (EHCI_TUNE_RL_HS << 28);
+                        info1 |= 512 << 16;     /* usb2 fixed maxpacket */
+                        info2 |= (EHCI_TUNE_MULT_HS << 30);
+                } else {                /* PIPE_INTERRUPT */
+                        info1 |= max_packet(maxp) << 16;
+                        info2 |= hb_mult(maxp) << 30;
+                }
+                break;
+        default:
+                dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed);
+done:
+                qh_put(qh);
+                return NULL;
+        }
+
+        /* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
+
+        /* init as live, toggle clear, advance to dummy */
+        qh->qh_state = QH_STATE_IDLE;
+        qh->hw_info1 = cpu_to_le32(info1);
+        qh->hw_info2 = cpu_to_le32(info2);
+        usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
+        qh_refresh(oxu, qh);
+        return qh;
+}
+
+/* Move qh (and its qtds) onto async queue; maybe enable queue.
+ */
+static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        __le32 dma = QH_NEXT(qh->qh_dma);
+        struct ehci_qh *head;
+
+        /* (re)start the async schedule? */
+        head = oxu->async;
+        timer_action_done(oxu, TIMER_ASYNC_OFF);
+        if (!head->qh_next.qh) {
+                u32     cmd = readl(&oxu->regs->command);
+
+                if (!(cmd & CMD_ASE)) {
+                        /* in case a clear of CMD_ASE didn't take yet */
+                        (void)handshake(oxu, &oxu->regs->status,
+                                        STS_ASS, 0, 150);
+                        cmd |= CMD_ASE | CMD_RUN;
+                        writel(cmd, &oxu->regs->command);
+                        oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
+                        /* posted write need not be known to HC yet ... */
+                }
+        }
+
+        /* clear halt and/or toggle; and maybe recover from silicon quirk */
+        if (qh->qh_state == QH_STATE_IDLE)
+                qh_refresh(oxu, qh);
+
+        /* splice right after start */
+        qh->qh_next = head->qh_next;
+        qh->hw_next = head->hw_next;
+        wmb();
+
+        head->qh_next.qh = qh;
+        head->hw_next = dma;
+
+        qh->qh_state = QH_STATE_LINKED;
+        /* qtd completions reported later by interrupt */
+}
+
+#define QH_ADDR_MASK    __constant_cpu_to_le32(0x7f)
+
+/*
+ * For control/bulk/interrupt, return QH with these TDs appended.
+ * Allocates and initializes the QH if necessary.
+ * Returns null if it can't allocate a QH it needs to.
+ * If the QH has TDs (urbs) already, that's great.
+ */
+static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
+                                struct urb *urb, struct list_head *qtd_list,
+                                int epnum, void **ptr)
+{
+        struct ehci_qh *qh = NULL;
+
+        qh = (struct ehci_qh *) *ptr;
+        if (unlikely(qh == NULL)) {
+                /* can't sleep here, we have oxu->lock... */
+                qh = qh_make(oxu, urb, GFP_ATOMIC);
+                *ptr = qh;
+        }
+        if (likely(qh != NULL)) {
+                struct ehci_qtd *qtd;
+
+                if (unlikely(list_empty(qtd_list)))
+                        qtd = NULL;
+                else
+                        qtd = list_entry(qtd_list->next, struct ehci_qtd,
+                                        qtd_list);
+
+                /* control qh may need patching ... */
+                if (unlikely(epnum == 0)) {
+
+                        /* usb_reset_device() briefly reverts to address 0 */
+                        if (usb_pipedevice(urb->pipe) == 0)
+                                qh->hw_info1 &= ~QH_ADDR_MASK;
+                }
+
+                /* just one way to queue requests: swap with the dummy qtd.
+                 * only hc or qh_refresh() ever modify the overlay.
+                 */
+                if (likely(qtd != NULL)) {
+                        struct ehci_qtd *dummy;
+                        dma_addr_t dma;
+                        __le32 token;
+
+                        /* to avoid racing the HC, use the dummy td instead of
+                         * the first td of our list (becomes new dummy).  both
+                         * tds stay deactivated until we're done, when the
+                         * HC is allowed to fetch the old dummy (4.10.2).
+                         */
+                        token = qtd->hw_token;
+                        qtd->hw_token = HALT_BIT;
+                        wmb();
+                        dummy = qh->dummy;
+
+                        dma = dummy->qtd_dma;
+                        *dummy = *qtd;
+                        dummy->qtd_dma = dma;
+
+                        list_del(&qtd->qtd_list);
+                        list_add(&dummy->qtd_list, qtd_list);
+                        list_splice(qtd_list, qh->qtd_list.prev);
+
+                        ehci_qtd_init(qtd, qtd->qtd_dma);
+                        qh->dummy = qtd;
+
+                        /* hc must see the new dummy at list end */
+                        dma = qtd->qtd_dma;
+                        qtd = list_entry(qh->qtd_list.prev,
+                                        struct ehci_qtd, qtd_list);
+                        qtd->hw_next = QTD_NEXT(dma);
+
+                        /* let the hc process these next qtds */
+                        dummy->hw_token = (token & ~(0x80));
+                        wmb();
+                        dummy->hw_token = token;
+
+                        urb->hcpriv = qh_get(qh);
+                }
+        }
+        return qh;
+}
+
+static int submit_async(struct oxu_hcd  *oxu, struct urb *urb,
+                        struct list_head *qtd_list, gfp_t mem_flags)
+{
+        struct ehci_qtd *qtd;
+        int epnum;
+        unsigned long flags;
+        struct ehci_qh *qh = NULL;
+        int rc = 0;
+
+        qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
+        epnum = urb->ep->desc.bEndpointAddress;
+
+#ifdef OXU_URB_TRACE
+        oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
+                __func__, urb->dev->devpath, urb,
+                epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
+                urb->transfer_buffer_length,
+                qtd, urb->ep->hcpriv);
+#endif
+
+        spin_lock_irqsave(&oxu->lock, flags);
+        if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
+                               &oxu_to_hcd(oxu)->flags))) {
+                rc = -ESHUTDOWN;
+                goto done;
+        }
+
+        qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
+        if (unlikely(qh == NULL)) {
+                rc = -ENOMEM;
+                goto done;
+        }
+
+        /* Control/bulk operations through TTs don't need scheduling,
+         * the HC and TT handle it when the TT has a buffer ready.
+         */
+        if (likely(qh->qh_state == QH_STATE_IDLE))
+                qh_link_async(oxu, qh_get(qh));
+done:
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        if (unlikely(qh == NULL))
+                qtd_list_free(oxu, urb, qtd_list);
+        return rc;
+}
+
+/* The async qh for the qtds being reclaimed are now unlinked from the HC */
+
+static void end_unlink_async(struct oxu_hcd *oxu)
+{
+        struct ehci_qh *qh = oxu->reclaim;
+        struct ehci_qh *next;
+
+        timer_action_done(oxu, TIMER_IAA_WATCHDOG);
+
+        qh->qh_state = QH_STATE_IDLE;
+        qh->qh_next.qh = NULL;
+        qh_put(qh);                     /* refcount from reclaim */
+
+        /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
+        next = qh->reclaim;
+        oxu->reclaim = next;
+        oxu->reclaim_ready = 0;
+        qh->reclaim = NULL;
+
+        qh_completions(oxu, qh);
+
+        if (!list_empty(&qh->qtd_list)
+                        && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
+                qh_link_async(oxu, qh);
+        else {
+                qh_put(qh);             /* refcount from async list */
+
+                /* it's not free to turn the async schedule on/off; leave it
+                 * active but idle for a while once it empties.
+                 */
+                if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
+                                && oxu->async->qh_next.qh == NULL)
+                        timer_action(oxu, TIMER_ASYNC_OFF);
+        }
+
+        if (next) {
+                oxu->reclaim = NULL;
+                start_unlink_async(oxu, next);
+        }
+}
+
+/* makes sure the async qh will become idle */
+/* caller must own oxu->lock */
+
+static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        int cmd = readl(&oxu->regs->command);
+        struct ehci_qh *prev;
+
+#ifdef DEBUG
+        assert_spin_locked(&oxu->lock);
+        if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
+                                && qh->qh_state != QH_STATE_UNLINK_WAIT))
+                BUG();
+#endif
+
+        /* stop async schedule right now? */
+        if (unlikely(qh == oxu->async)) {
+                /* can't get here without STS_ASS set */
+                if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
+                                && !oxu->reclaim) {
+                        /* ... and CMD_IAAD clear */
+                        writel(cmd & ~CMD_ASE, &oxu->regs->command);
+                        wmb();
+                        /* handshake later, if we need to */
+                        timer_action_done(oxu, TIMER_ASYNC_OFF);
+                }
+                return;
+        }
+
+        qh->qh_state = QH_STATE_UNLINK;
+        oxu->reclaim = qh = qh_get(qh);
+
+        prev = oxu->async;
+        while (prev->qh_next.qh != qh)
+                prev = prev->qh_next.qh;
+
+        prev->hw_next = qh->hw_next;
+        prev->qh_next = qh->qh_next;
+        wmb();
+
+        if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
+                /* if (unlikely(qh->reclaim != 0))
+                 *      this will recurse, probably not much
+                 */
+                end_unlink_async(oxu);
+                return;
+        }
+
+        oxu->reclaim_ready = 0;
+        cmd |= CMD_IAAD;
+        writel(cmd, &oxu->regs->command);
+        (void) readl(&oxu->regs->command);
+        timer_action(oxu, TIMER_IAA_WATCHDOG);
+}
+
+static void scan_async(struct oxu_hcd *oxu)
+{
+        struct ehci_qh *qh;
+        enum ehci_timer_action action = TIMER_IO_WATCHDOG;
+
+        if (!++(oxu->stamp))
+                oxu->stamp++;
+        timer_action_done(oxu, TIMER_ASYNC_SHRINK);
+rescan:
+        qh = oxu->async->qh_next.qh;
+        if (likely(qh != NULL)) {
+                do {
+                        /* clean any finished work for this qh */
+                        if (!list_empty(&qh->qtd_list)
+                                        && qh->stamp != oxu->stamp) {
+                                int temp;
+
+                                /* unlinks could happen here; completion
+                                 * reporting drops the lock.  rescan using
+                                 * the latest schedule, but don't rescan
+                                 * qhs we already finished (no looping).
+                                 */
+                                qh = qh_get(qh);
+                                qh->stamp = oxu->stamp;
+                                temp = qh_completions(oxu, qh);
+                                qh_put(qh);
+                                if (temp != 0)
+                                        goto rescan;
+                        }
+
+                        /* unlink idle entries, reducing HC PCI usage as well
+                         * as HCD schedule-scanning costs.  delay for any qh
+                         * we just scanned, there's a not-unusual case that it
+                         * doesn't stay idle for long.
+                         * (plus, avoids some kind of re-activation race.)
+                         */
+                        if (list_empty(&qh->qtd_list)) {
+                                if (qh->stamp == oxu->stamp)
+                                        action = TIMER_ASYNC_SHRINK;
+                                else if (!oxu->reclaim
+                                            && qh->qh_state == QH_STATE_LINKED)
+                                        start_unlink_async(oxu, qh);
+                        }
+
+                        qh = qh->qh_next.qh;
+                } while (qh);
+        }
+        if (action == TIMER_ASYNC_SHRINK)
+                timer_action(oxu, TIMER_ASYNC_SHRINK);
+}
+
+/*
+ * periodic_next_shadow - return "next" pointer on shadow list
+ * @periodic: host pointer to qh/itd/sitd
+ * @tag: hardware tag for type of this record
+ */
+static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
+                                                __le32 tag)
+{
+        switch (tag) {
+        default:
+        case Q_TYPE_QH:
+                return &periodic->qh->qh_next;
+        }
+}
+
+/* caller must hold oxu->lock */
+static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
+{
+        union ehci_shadow *prev_p = &oxu->pshadow[frame];
+        __le32 *hw_p = &oxu->periodic[frame];
+        union ehci_shadow here = *prev_p;
+
+        /* find predecessor of "ptr"; hw and shadow lists are in sync */
+        while (here.ptr && here.ptr != ptr) {
+                prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
+                hw_p = here.hw_next;
+                here = *prev_p;
+        }
+        /* an interrupt entry (at list end) could have been shared */
+        if (!here.ptr)
+                return;
+
+        /* update shadow and hardware lists ... the old "next" pointers
+         * from ptr may still be in use, the caller updates them.
+         */
+        *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
+        *hw_p = *here.hw_next;
+}
+
+/* how many of the uframe's 125 usecs are allocated? */
+static unsigned short periodic_usecs(struct oxu_hcd *oxu,
+                                        unsigned frame, unsigned uframe)
+{
+        __le32 *hw_p = &oxu->periodic[frame];
+        union ehci_shadow *q = &oxu->pshadow[frame];
+        unsigned usecs = 0;
+
+        while (q->ptr) {
+                switch (Q_NEXT_TYPE(*hw_p)) {
+                case Q_TYPE_QH:
+                default:
+                        /* is it in the S-mask? */
+                        if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
+                                usecs += q->qh->usecs;
+                        /* ... or C-mask? */
+                        if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
+                                usecs += q->qh->c_usecs;
+                        hw_p = &q->qh->hw_next;
+                        q = &q->qh->qh_next;
+                        break;
+                }
+        }
+#ifdef DEBUG
+        if (usecs > 100)
+                oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
+                                                frame * 8 + uframe, usecs);
+#endif
+        return usecs;
+}
+
+static int enable_periodic(struct oxu_hcd *oxu)
+{
+        u32 cmd;
+        int status;
+
+        /* did clearing PSE did take effect yet?
+         * takes effect only at frame boundaries...
+         */
+        status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
+        if (status != 0) {
+                oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+                return status;
+        }
+
+        cmd = readl(&oxu->regs->command) | CMD_PSE;
+        writel(cmd, &oxu->regs->command);
+        /* posted write ... PSS happens later */
+        oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
+
+        /* make sure ehci_work scans these */
+        oxu->next_uframe = readl(&oxu->regs->frame_index)
+                % (oxu->periodic_size << 3);
+        return 0;
+}
+
+static int disable_periodic(struct oxu_hcd *oxu)
+{
+        u32 cmd;
+        int status;
+
+        /* did setting PSE not take effect yet?
+         * takes effect only at frame boundaries...
+         */
+        status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
+        if (status != 0) {
+                oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+                return status;
+        }
+
+        cmd = readl(&oxu->regs->command) & ~CMD_PSE;
+        writel(cmd, &oxu->regs->command);
+        /* posted write ... */
+
+        oxu->next_uframe = -1;
+        return 0;
+}
+
+/* periodic schedule slots have iso tds (normal or split) first, then a
+ * sparse tree for active interrupt transfers.
+ *
+ * this just links in a qh; caller guarantees uframe masks are set right.
+ * no FSTN support (yet; oxu 0.96+)
+ */
+static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        unsigned i;
+        unsigned period = qh->period;
+
+        dev_dbg(&qh->dev->dev,
+                "link qh%d-%04x/%p start %d [%d/%d us]\n",
+                period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
+                qh, qh->start, qh->usecs, qh->c_usecs);
+
+        /* high bandwidth, or otherwise every microframe */
+        if (period == 0)
+                period = 1;
+
+        for (i = qh->start; i < oxu->periodic_size; i += period) {
+                union ehci_shadow       *prev = &oxu->pshadow[i];
+                __le32                  *hw_p = &oxu->periodic[i];
+                union ehci_shadow       here = *prev;
+                __le32                  type = 0;
+
+                /* skip the iso nodes at list head */
+                while (here.ptr) {
+                        type = Q_NEXT_TYPE(*hw_p);
+                        if (type == Q_TYPE_QH)
+                                break;
+                        prev = periodic_next_shadow(prev, type);
+                        hw_p = &here.qh->hw_next;
+                        here = *prev;
+                }
+
+                /* sorting each branch by period (slow-->fast)
+                 * enables sharing interior tree nodes
+                 */
+                while (here.ptr && qh != here.qh) {
+                        if (qh->period > here.qh->period)
+                                break;
+                        prev = &here.qh->qh_next;
+                        hw_p = &here.qh->hw_next;
+                        here = *prev;
+                }
+                /* link in this qh, unless some earlier pass did that */
+                if (qh != here.qh) {
+                        qh->qh_next = here;
+                        if (here.qh)
+                                qh->hw_next = *hw_p;
+                        wmb();
+                        prev->qh = qh;
+                        *hw_p = QH_NEXT(qh->qh_dma);
+                }
+        }
+        qh->qh_state = QH_STATE_LINKED;
+        qh_get(qh);
+
+        /* update per-qh bandwidth for usbfs */
+        oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
+                ? ((qh->usecs + qh->c_usecs) / qh->period)
+                : (qh->usecs * 8);
+
+        /* maybe enable periodic schedule processing */
+        if (!oxu->periodic_sched++)
+                return enable_periodic(oxu);
+
+        return 0;
+}
+
+static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        unsigned i;
+        unsigned period;
+
+        /* FIXME:
+         *   IF this isn't high speed
+         *   and this qh is active in the current uframe
+         *   (and overlay token SplitXstate is false?)
+         * THEN
+         *   qh->hw_info1 |= __constant_cpu_to_le32(1 << 7 "ignore");
+         */
+
+        /* high bandwidth, or otherwise part of every microframe */
+        period = qh->period;
+        if (period == 0)
+                period = 1;
+
+        for (i = qh->start; i < oxu->periodic_size; i += period)
+                periodic_unlink(oxu, i, qh);
+
+        /* update per-qh bandwidth for usbfs */
+        oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
+                ? ((qh->usecs + qh->c_usecs) / qh->period)
+                : (qh->usecs * 8);
+
+        dev_dbg(&qh->dev->dev,
+                "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
+                qh->period,
+                le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
+                qh, qh->start, qh->usecs, qh->c_usecs);
+
+        /* qh->qh_next still "live" to HC */
+        qh->qh_state = QH_STATE_UNLINK;
+        qh->qh_next.ptr = NULL;
+        qh_put(qh);
+
+        /* maybe turn off periodic schedule */
+        oxu->periodic_sched--;
+        if (!oxu->periodic_sched)
+                (void) disable_periodic(oxu);
+}
+
+static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        unsigned wait;
+
+        qh_unlink_periodic(oxu, qh);
+
+        /* simple/paranoid:  always delay, expecting the HC needs to read
+         * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
+         * expect khubd to clean up after any CSPLITs we won't issue.
+         * active high speed queues may need bigger delays...
+         */
+        if (list_empty(&qh->qtd_list)
+                || (__constant_cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
+                wait = 2;
+        else
+                wait = 55;      /* worst case: 3 * 1024 */
+
+        udelay(wait);
+        qh->qh_state = QH_STATE_IDLE;
+        qh->hw_next = EHCI_LIST_END;
+        wmb();
+}
+
+static int check_period(struct oxu_hcd *oxu,
+                        unsigned frame, unsigned uframe,
+                        unsigned period, unsigned usecs)
+{
+        int claimed;
+
+        /* complete split running into next frame?
+         * given FSTN support, we could sometimes check...
+         */
+        if (uframe >= 8)
+                return 0;
+
+        /*
+         * 80% periodic == 100 usec/uframe available
+         * convert "usecs we need" to "max already claimed"
+         */
+        usecs = 100 - usecs;
+
+        /* we "know" 2 and 4 uframe intervals were rejected; so
+         * for period 0, check _every_ microframe in the schedule.
+         */
+        if (unlikely(period == 0)) {
+                do {
+                        for (uframe = 0; uframe < 7; uframe++) {
+                                claimed = periodic_usecs(oxu, frame, uframe);
+                                if (claimed > usecs)
+                                        return 0;
+                        }
+                } while ((frame += 1) < oxu->periodic_size);
+
+        /* just check the specified uframe, at that period */
+        } else {
+                do {
+                        claimed = periodic_usecs(oxu, frame, uframe);
+                        if (claimed > usecs)
+                                return 0;
+                } while ((frame += period) < oxu->periodic_size);
+        }
+
+        return 1;
+}
+
+static int check_intr_schedule(struct oxu_hcd   *oxu,
+                                unsigned frame, unsigned uframe,
+                                const struct ehci_qh *qh, __le32 *c_maskp)
+{
+        int retval = -ENOSPC;
+
+        if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
+                goto done;
+
+        if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
+                goto done;
+        if (!qh->c_usecs) {
+                retval = 0;
+                *c_maskp = 0;
+                goto done;
+        }
+
+done:
+        return retval;
+}
+
+/* "first fit" scheduling policy used the first time through,
+ * or when the previous schedule slot can't be re-used.
+ */
+static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        int             status;
+        unsigned        uframe;
+        __le32          c_mask;
+        unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
+
+        qh_refresh(oxu, qh);
+        qh->hw_next = EHCI_LIST_END;
+        frame = qh->start;
+
+        /* reuse the previous schedule slots, if we can */
+        if (frame < qh->period) {
+                uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
+                status = check_intr_schedule(oxu, frame, --uframe,
+                                qh, &c_mask);
+        } else {
+                uframe = 0;
+                c_mask = 0;
+                status = -ENOSPC;
+        }
+
+        /* else scan the schedule to find a group of slots such that all
+         * uframes have enough periodic bandwidth available.
+         */
+        if (status) {
+                /* "normal" case, uframing flexible except with splits */
+                if (qh->period) {
+                        frame = qh->period - 1;
+                        do {
+                                for (uframe = 0; uframe < 8; uframe++) {
+                                        status = check_intr_schedule(oxu,
+                                                        frame, uframe, qh,
+                                                        &c_mask);
+                                        if (status == 0)
+                                                break;
+                                }
+                        } while (status && frame--);
+
+                /* qh->period == 0 means every uframe */
+                } else {
+                        frame = 0;
+                        status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
+                }
+                if (status)
+                        goto done;
+                qh->start = frame;
+
+                /* reset S-frame and (maybe) C-frame masks */
+                qh->hw_info2 &= __constant_cpu_to_le32(~(QH_CMASK | QH_SMASK));
+                qh->hw_info2 |= qh->period
+                        ? cpu_to_le32(1 << uframe)
+                        : __constant_cpu_to_le32(QH_SMASK);
+                qh->hw_info2 |= c_mask;
+        } else
+                oxu_dbg(oxu, "reused qh %p schedule\n", qh);
+
+        /* stuff into the periodic schedule */
+        status = qh_link_periodic(oxu, qh);
+done:
+        return status;
+}
+
+static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
+                        struct list_head *qtd_list, gfp_t mem_flags)
+{
+        unsigned epnum;
+        unsigned long flags;
+        struct ehci_qh *qh;
+        int status = 0;
+        struct list_head        empty;
+
+        /* get endpoint and transfer/schedule data */
+        epnum = urb->ep->desc.bEndpointAddress;
+
+        spin_lock_irqsave(&oxu->lock, flags);
+
+        if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
+                               &oxu_to_hcd(oxu)->flags))) {
+                status = -ESHUTDOWN;
+                goto done;
+        }
+
+        /* get qh and force any scheduling errors */
+        INIT_LIST_HEAD(&empty);
+        qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
+        if (qh == NULL) {
+                status = -ENOMEM;
+                goto done;
+        }
+        if (qh->qh_state == QH_STATE_IDLE) {
+                status = qh_schedule(oxu, qh);
+                if (status != 0)
+                        goto done;
+        }
+
+        /* then queue the urb's tds to the qh */
+        qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
+        BUG_ON(qh == NULL);
+
+        /* ... update usbfs periodic stats */
+        oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
+
+done:
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        if (status)
+                qtd_list_free(oxu, urb, qtd_list);
+
+        return status;
+}
+
+static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
+                                                gfp_t mem_flags)
+{
+        oxu_dbg(oxu, "iso support is missing!\n");
+        return -ENOSYS;
+}
+
+static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
+                                                gfp_t mem_flags)
+{
+        oxu_dbg(oxu, "split iso support is missing!\n");
+        return -ENOSYS;
+}
+
+static void scan_periodic(struct oxu_hcd *oxu)
+{
+        unsigned frame, clock, now_uframe, mod;
+        unsigned modified;
+
+        mod = oxu->periodic_size << 3;
+
+        /*
+         * When running, scan from last scan point up to "now"
+         * else clean up by scanning everything that's left.
+         * Touches as few pages as possible:  cache-friendly.
+         */
+        now_uframe = oxu->next_uframe;
+        if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
+                clock = readl(&oxu->regs->frame_index);
+        else
+                clock = now_uframe + mod - 1;
+        clock %= mod;
+
+        for (;;) {
+                union ehci_shadow       q, *q_p;
+                __le32                  type, *hw_p;
+                unsigned                uframes;
+
+                /* don't scan past the live uframe */
+                frame = now_uframe >> 3;
+                if (frame == (clock >> 3))
+                        uframes = now_uframe & 0x07;
+                else {
+                        /* safe to scan the whole frame at once */
+                        now_uframe |= 0x07;
+                        uframes = 8;
+                }
+
+restart:
+                /* scan each element in frame's queue for completions */
+                q_p = &oxu->pshadow[frame];
+                hw_p = &oxu->periodic[frame];
+                q.ptr = q_p->ptr;
+                type = Q_NEXT_TYPE(*hw_p);
+                modified = 0;
+
+                while (q.ptr != NULL) {
+                        union ehci_shadow temp;
+                        int live;
+
+                        live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state);
+                        switch (type) {
+                        case Q_TYPE_QH:
+                                /* handle any completions */
+                                temp.qh = qh_get(q.qh);
+                                type = Q_NEXT_TYPE(q.qh->hw_next);
+                                q = q.qh->qh_next;
+                                modified = qh_completions(oxu, temp.qh);
+                                if (unlikely(list_empty(&temp.qh->qtd_list)))
+                                        intr_deschedule(oxu, temp.qh);
+                                qh_put(temp.qh);
+                                break;
+                        default:
+                                dbg("corrupt type %d frame %d shadow %p",
+                                        type, frame, q.ptr);
+                                q.ptr = NULL;
+                        }
+
+                        /* assume completion callbacks modify the queue */
+                        if (unlikely(modified))
+                                goto restart;
+                }
+
+                /* Stop when we catch up to the HC */
+
+                /* FIXME:  this assumes we won't get lapped when
+                 * latencies climb; that should be rare, but...
+                 * detect it, and just go all the way around.
+                 * FLR might help detect this case, so long as latencies
+                 * don't exceed periodic_size msec (default 1.024 sec).
+                 */
+
+                /* FIXME: likewise assumes HC doesn't halt mid-scan */
+
+                if (now_uframe == clock) {
+                        unsigned        now;
+
+                        if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
+                                break;
+                        oxu->next_uframe = now_uframe;
+                        now = readl(&oxu->regs->frame_index) % mod;
+                        if (now_uframe == now)
+                                break;
+
+                        /* rescan the rest of this frame, then ... */
+                        clock = now;
+                } else {
+                        now_uframe++;
+                        now_uframe %= mod;
+                }
+        }
+}
+
+/* On some systems, leaving remote wakeup enabled prevents system shutdown.
+ * The firmware seems to think that powering off is a wakeup event!
+ * This routine turns off remote wakeup and everything else, on all ports.
+ */
+static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
+{
+        int port = HCS_N_PORTS(oxu->hcs_params);
+
+        while (port--)
+                writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
+}
+
+static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
+{
+        unsigned port;
+
+        if (!HCS_PPC(oxu->hcs_params))
+                return;
+
+        oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
+        for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
+                (void) oxu_hub_control(oxu_to_hcd(oxu),
+                                is_on ? SetPortFeature : ClearPortFeature,
+                                USB_PORT_FEAT_POWER,
+                                port--, NULL, 0);
+        msleep(20);
+}
+
+/* Called from some interrupts, timers, and so on.
+ * It calls driver completion functions, after dropping oxu->lock.
+ */
+static void ehci_work(struct oxu_hcd *oxu)
+{
+        timer_action_done(oxu, TIMER_IO_WATCHDOG);
+        if (oxu->reclaim_ready)
+                end_unlink_async(oxu);
+
+        /* another CPU may drop oxu->lock during a schedule scan while
+         * it reports urb completions.  this flag guards against bogus
+         * attempts at re-entrant schedule scanning.
+         */
+        if (oxu->scanning)
+                return;
+        oxu->scanning = 1;
+        scan_async(oxu);
+        if (oxu->next_uframe != -1)
+                scan_periodic(oxu);
+        oxu->scanning = 0;
+
+        /* the IO watchdog guards against hardware or driver bugs that
+         * misplace IRQs, and should let us run completely without IRQs.
+         * such lossage has been observed on both VT6202 and VT8235.
+         */
+        if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
+                        (oxu->async->qh_next.ptr != NULL ||
+                         oxu->periodic_sched != 0))
+                timer_action(oxu, TIMER_IO_WATCHDOG);
+}
+
+static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
+{
+        /* if we need to use IAA and it's busy, defer */
+        if (qh->qh_state == QH_STATE_LINKED
+                        && oxu->reclaim
+                        && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
+                struct ehci_qh          *last;
+
+                for (last = oxu->reclaim;
+                                last->reclaim;
+                                last = last->reclaim)
+                        continue;
+                qh->qh_state = QH_STATE_UNLINK_WAIT;
+                last->reclaim = qh;
+
+        /* bypass IAA if the hc can't care */
+        } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
+                end_unlink_async(oxu);
+
+        /* something else might have unlinked the qh by now */
+        if (qh->qh_state == QH_STATE_LINKED)
+                start_unlink_async(oxu, qh);
+}
+
+/*
+ * USB host controller methods
+ */
+
+static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        u32 status, pcd_status = 0;
+        int bh;
+
+        spin_lock(&oxu->lock);
+
+        status = readl(&oxu->regs->status);
+
+        /* e.g. cardbus physical eject */
+        if (status == ~(u32) 0) {
+                oxu_dbg(oxu, "device removed\n");
+                goto dead;
+        }
+
+        status &= INTR_MASK;
+        if (!status) {                  /* irq sharing? */
+                spin_unlock(&oxu->lock);
+                return IRQ_NONE;
+        }
+
+        /* clear (just) interrupts */
+        writel(status, &oxu->regs->status);
+        readl(&oxu->regs->command);     /* unblock posted write */
+        bh = 0;
+
+#ifdef OXU_VERBOSE_DEBUG
+        /* unrequested/ignored: Frame List Rollover */
+        dbg_status(oxu, "irq", status);
+#endif
+
+        /* INT, ERR, and IAA interrupt rates can be throttled */
+
+        /* normal [4.15.1.2] or error [4.15.1.1] completion */
+        if (likely((status & (STS_INT|STS_ERR)) != 0))
+                bh = 1;
+
+        /* complete the unlinking of some qh [4.15.2.3] */
+        if (status & STS_IAA) {
+                oxu->reclaim_ready = 1;
+                bh = 1;
+        }
+
+        /* remote wakeup [4.3.1] */
+        if (status & STS_PCD) {
+                unsigned i = HCS_N_PORTS(oxu->hcs_params);
+                pcd_status = status;
+
+                /* resume root hub? */
+                if (!(readl(&oxu->regs->command) & CMD_RUN))
+                        usb_hcd_resume_root_hub(hcd);
+
+                while (i--) {
+                        int pstatus = readl(&oxu->regs->port_status[i]);
+
+                        if (pstatus & PORT_OWNER)
+                                continue;
+                        if (!(pstatus & PORT_RESUME)
+                                        || oxu->reset_done[i] != 0)
+                                continue;
+
+                        /* start 20 msec resume signaling from this port,
+                         * and make khubd collect PORT_STAT_C_SUSPEND to
+                         * stop that signaling.
+                         */
+                        oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
+                        oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
+                        mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
+                }
+        }
+
+        /* PCI errors [4.15.2.4] */
+        if (unlikely((status & STS_FATAL) != 0)) {
+                /* bogus "fatal" IRQs appear on some chips... why?  */
+                status = readl(&oxu->regs->status);
+                dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
+                dbg_status(oxu, "fatal", status);
+                if (status & STS_HALT) {
+                        oxu_err(oxu, "fatal error\n");
+dead:
+                        ehci_reset(oxu);
+                        writel(0, &oxu->regs->configured_flag);
+                        /* generic layer kills/unlinks all urbs, then
+                         * uses oxu_stop to clean up the rest
+                         */
+                        bh = 1;
+                }
+        }
+
+        if (bh)
+                ehci_work(oxu);
+        spin_unlock(&oxu->lock);
+        if (pcd_status & STS_PCD)
+                usb_hcd_poll_rh_status(hcd);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t oxu_irq(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int ret = IRQ_HANDLED;
+
+        u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
+        u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
+
+        /* Disable all interrupt */
+        oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
+
+        if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
+                (!oxu->is_otg && (status & OXU_USBSPHI)))
+                oxu210_hcd_irq(hcd);
+        else
+                ret = IRQ_NONE;
+
+        /* Enable all interrupt back */
+        oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
+
+        return ret;
+}
+
+static void oxu_watchdog(unsigned long param)
+{
+        struct oxu_hcd  *oxu = (struct oxu_hcd *) param;
+        unsigned long flags;
+
+        spin_lock_irqsave(&oxu->lock, flags);
+
+        /* lost IAA irqs wedge things badly; seen with a vt8235 */
+        if (oxu->reclaim) {
+                u32 status = readl(&oxu->regs->status);
+                if (status & STS_IAA) {
+                        oxu_vdbg(oxu, "lost IAA\n");
+                        writel(STS_IAA, &oxu->regs->status);
+                        oxu->reclaim_ready = 1;
+                }
+        }
+
+        /* stop async processing after it's idled a bit */
+        if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
+                start_unlink_async(oxu, oxu->async);
+
+        /* oxu could run by timer, without IRQs ... */
+        ehci_work(oxu);
+
+        spin_unlock_irqrestore(&oxu->lock, flags);
+}
+
+/* One-time init, only for memory state.
+ */
+static int oxu_hcd_init(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        u32 temp;
+        int retval;
+        u32 hcc_params;
+
+        spin_lock_init(&oxu->lock);
+
+        init_timer(&oxu->watchdog);
+        oxu->watchdog.function = oxu_watchdog;
+        oxu->watchdog.data = (unsigned long) oxu;
+
+        /*
+         * hw default: 1K periodic list heads, one per frame.
+         * periodic_size can shrink by USBCMD update if hcc_params allows.
+         */
+        oxu->periodic_size = DEFAULT_I_TDPS;
+        retval = ehci_mem_init(oxu, GFP_KERNEL);
+        if (retval < 0)
+                return retval;
+
+        /* controllers may cache some of the periodic schedule ... */
+        hcc_params = readl(&oxu->caps->hcc_params);
+        if (HCC_ISOC_CACHE(hcc_params))         /* full frame cache */
+                oxu->i_thresh = 8;
+        else                                    /* N microframes cached */
+                oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
+
+        oxu->reclaim = NULL;
+        oxu->reclaim_ready = 0;
+        oxu->next_uframe = -1;
+
+        /*
+         * dedicate a qh for the async ring head, since we couldn't unlink
+         * a 'real' qh without stopping the async schedule [4.8].  use it
+         * as the 'reclamation list head' too.
+         * its dummy is used in hw_alt_next of many tds, to prevent the qh
+         * from automatically advancing to the next td after short reads.
+         */
+        oxu->async->qh_next.qh = NULL;
+        oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
+        oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
+        oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
+        oxu->async->hw_qtd_next = EHCI_LIST_END;
+        oxu->async->qh_state = QH_STATE_LINKED;
+        oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
+
+        /* clear interrupt enables, set irq latency */
+        if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
+                log2_irq_thresh = 0;
+        temp = 1 << (16 + log2_irq_thresh);
+        if (HCC_CANPARK(hcc_params)) {
+                /* HW default park == 3, on hardware that supports it (like
+                 * NVidia and ALI silicon), maximizes throughput on the async
+                 * schedule by avoiding QH fetches between transfers.
+                 *
+                 * With fast usb storage devices and NForce2, "park" seems to
+                 * make problems:  throughput reduction (!), data errors...
+                 */
+                if (park) {
+                        park = min(park, (unsigned) 3);
+                        temp |= CMD_PARK;
+                        temp |= park << 8;
+                }
+                oxu_dbg(oxu, "park %d\n", park);
+        }
+        if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
+                /* periodic schedule size can be smaller than default */
+                temp &= ~(3 << 2);
+                temp |= (EHCI_TUNE_FLS << 2);
+        }
+        oxu->command = temp;
+
+        return 0;
+}
+
+/* Called during probe() after chip reset completes.
+ */
+static int oxu_reset(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int ret;
+
+        spin_lock_init(&oxu->mem_lock);
+        INIT_LIST_HEAD(&oxu->urb_list);
+        oxu->urb_len = 0;
+
+        /* FIMXE */
+        hcd->self.controller->dma_mask = 0UL;
+
+        if (oxu->is_otg) {
+                oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
+                oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
+                        HC_LENGTH(readl(&oxu->caps->hc_capbase));
+
+                oxu->mem = hcd->regs + OXU_SPH_MEM;
+        } else {
+                oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
+                oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
+                        HC_LENGTH(readl(&oxu->caps->hc_capbase));
+
+                oxu->mem = hcd->regs + OXU_OTG_MEM;
+        }
+
+        oxu->hcs_params = readl(&oxu->caps->hcs_params);
+        oxu->sbrn = 0x20;
+
+        ret = oxu_hcd_init(hcd);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int oxu_run(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int retval;
+        u32 temp, hcc_params;
+
+        hcd->uses_new_polling = 1;
+        hcd->poll_rh = 0;
+
+        /* EHCI spec section 4.1 */
+        retval = ehci_reset(oxu);
+        if (retval != 0) {
+                ehci_mem_cleanup(oxu);
+                return retval;
+        }
+        writel(oxu->periodic_dma, &oxu->regs->frame_list);
+        writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
+
+        /* hcc_params controls whether oxu->regs->segment must (!!!)
+         * be used; it constrains QH/ITD/SITD and QTD locations.
+         * pci_pool consistent memory always uses segment zero.
+         * streaming mappings for I/O buffers, like pci_map_single(),
+         * can return segments above 4GB, if the device allows.
+         *
+         * NOTE:  the dma mask is visible through dma_supported(), so
+         * drivers can pass this info along ... like NETIF_F_HIGHDMA,
+         * Scsi_Host.highmem_io, and so forth.  It's readonly to all
+         * host side drivers though.
+         */
+        hcc_params = readl(&oxu->caps->hcc_params);
+        if (HCC_64BIT_ADDR(hcc_params))
+                writel(0, &oxu->regs->segment);
+
+        oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
+                                CMD_ASE | CMD_RESET);
+        oxu->command |= CMD_RUN;
+        writel(oxu->command, &oxu->regs->command);
+        dbg_cmd(oxu, "init", oxu->command);
+
+        /*
+         * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
+         * are explicitly handed to companion controller(s), so no TT is
+         * involved with the root hub.  (Except where one is integrated,
+         * and there's no companion controller unless maybe for USB OTG.)
+         */
+        hcd->state = HC_STATE_RUNNING;
+        writel(FLAG_CF, &oxu->regs->configured_flag);
+        readl(&oxu->regs->command);     /* unblock posted writes */
+
+        temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
+        oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
+                ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
+                temp >> 8, temp & 0xff, DRIVER_VERSION,
+                ignore_oc ? ", overcurrent ignored" : "");
+
+        writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
+
+        return 0;
+}
+
+static void oxu_stop(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+
+        /* Turn off port power on all root hub ports. */
+        ehci_port_power(oxu, 0);
+
+        /* no more interrupts ... */
+        del_timer_sync(&oxu->watchdog);
+
+        spin_lock_irq(&oxu->lock);
+        if (HC_IS_RUNNING(hcd->state))
+                ehci_quiesce(oxu);
+
+        ehci_reset(oxu);
+        writel(0, &oxu->regs->intr_enable);
+        spin_unlock_irq(&oxu->lock);
+
+        /* let companion controllers work when we aren't */
+        writel(0, &oxu->regs->configured_flag);
+
+        /* root hub is shut down separately (first, when possible) */
+        spin_lock_irq(&oxu->lock);
+        if (oxu->async)
+                ehci_work(oxu);
+        spin_unlock_irq(&oxu->lock);
+        ehci_mem_cleanup(oxu);
+
+        dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
+}
+
+/* Kick in for silicon on any bus (not just pci, etc).
+ * This forcibly disables dma and IRQs, helping kexec and other cases
+ * where the next system software may expect clean state.
+ */
+static void oxu_shutdown(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+
+        (void) ehci_halt(oxu);
+        ehci_turn_off_all_ports(oxu);
+
+        /* make BIOS/etc use companion controller during reboot */
+        writel(0, &oxu->regs->configured_flag);
+
+        /* unblock posted writes */
+        readl(&oxu->regs->configured_flag);
+}
+
+/* Non-error returns are a promise to giveback() the urb later
+ * we drop ownership so next owner (or urb unlink) can get it
+ *
+ * urb + dev is in hcd.self.controller.urb_list
+ * we're queueing TDs onto software and hardware lists
+ *
+ * hcd-specific init for hcpriv hasn't been done yet
+ *
+ * NOTE:  control, bulk, and interrupt share the same code to append TDs
+ * to a (possibly active) QH, and the same QH scanning code.
+ */
+static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+                                gfp_t mem_flags)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        struct list_head qtd_list;
+
+        INIT_LIST_HEAD(&qtd_list);
+
+        switch (usb_pipetype(urb->pipe)) {
+        case PIPE_CONTROL:
+        case PIPE_BULK:
+        default:
+                if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
+                        return -ENOMEM;
+                return submit_async(oxu, urb, &qtd_list, mem_flags);
+
+        case PIPE_INTERRUPT:
+                if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
+                        return -ENOMEM;
+                return intr_submit(oxu, urb, &qtd_list, mem_flags);
+
+        case PIPE_ISOCHRONOUS:
+                if (urb->dev->speed == USB_SPEED_HIGH)
+                        return itd_submit(oxu, urb, mem_flags);
+                else
+                        return sitd_submit(oxu, urb, mem_flags);
+        }
+}
+
+/* This function is responsible for breaking URBs with big data size
+ * into smaller size and processing small urbs in sequence.
+ */
+static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+                                gfp_t mem_flags)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int num, rem;
+        int transfer_buffer_length;
+        void *transfer_buffer;
+        struct urb *murb;
+        int i, ret;
+
+        /* If not bulk pipe just enqueue the URB */
+        if (!usb_pipebulk(urb->pipe))
+                return __oxu_urb_enqueue(hcd, urb, mem_flags);
+
+        /* Otherwise we should verify the USB transfer buffer size! */
+        transfer_buffer = urb->transfer_buffer;
+        transfer_buffer_length = urb->transfer_buffer_length;
+
+        num = urb->transfer_buffer_length / 4096;
+        rem = urb->transfer_buffer_length % 4096;
+        if (rem != 0)
+                num++;
+
+        /* If URB is smaller than 4096 bytes just enqueue it! */
+        if (num == 1)
+                return __oxu_urb_enqueue(hcd, urb, mem_flags);
+
+        /* Ok, we have more job to do! :) */
+
+        for (i = 0; i < num - 1; i++) {
+                /* Get free micro URB poll till a free urb is recieved */
+
+                do {
+                        murb = (struct urb *) oxu_murb_alloc(oxu);
+                        if (!murb)
+                                schedule();
+                } while (!murb);
+
+                /* Coping the urb */
+                memcpy(murb, urb, sizeof(struct urb));
+
+                murb->transfer_buffer_length = 4096;
+                murb->transfer_buffer = transfer_buffer + i * 4096;
+
+                /* Null pointer for the encodes that this is a micro urb */
+                murb->complete = NULL;
+
+                ((struct oxu_murb *) murb)->main = urb;
+                ((struct oxu_murb *) murb)->last = 0;
+
+                /* This loop is to guarantee urb to be processed when there's
+                 * not enough resources at a particular time by retrying.
+                 */
+                do {
+                        ret  = __oxu_urb_enqueue(hcd, murb, mem_flags);
+                        if (ret)
+                                schedule();
+                } while (ret);
+        }
+
+        /* Last urb requires special handling  */
+
+        /* Get free micro URB poll till a free urb is recieved */
+        do {
+                murb = (struct urb *) oxu_murb_alloc(oxu);
+                if (!murb)
+                        schedule();
+        } while (!murb);
+
+        /* Coping the urb */
+        memcpy(murb, urb, sizeof(struct urb));
+
+        murb->transfer_buffer_length = rem > 0 ? rem : 4096;
+        murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
+
+        /* Null pointer for the encodes that this is a micro urb */
+        murb->complete = NULL;
+
+        ((struct oxu_murb *) murb)->main = urb;
+        ((struct oxu_murb *) murb)->last = 1;
+
+        do {
+                ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
+                if (ret)
+                        schedule();
+        } while (ret);
+
+        return ret;
+}
+
+/* Remove from hardware lists.
+ * Completions normally happen asynchronously
+ */
+static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        struct ehci_qh *qh;
+        unsigned long flags;
+
+        spin_lock_irqsave(&oxu->lock, flags);
+        switch (usb_pipetype(urb->pipe)) {
+        case PIPE_CONTROL:
+        case PIPE_BULK:
+        default:
+                qh = (struct ehci_qh *) urb->hcpriv;
+                if (!qh)
+                        break;
+                unlink_async(oxu, qh);
+                break;
+
+        case PIPE_INTERRUPT:
+                qh = (struct ehci_qh *) urb->hcpriv;
+                if (!qh)
+                        break;
+                switch (qh->qh_state) {
+                case QH_STATE_LINKED:
+                        intr_deschedule(oxu, qh);
+                        /* FALL THROUGH */
+                case QH_STATE_IDLE:
+                        qh_completions(oxu, qh);
+                        break;
+                default:
+                        oxu_dbg(oxu, "bogus qh %p state %d\n",
+                                        qh, qh->qh_state);
+                        goto done;
+                }
+
+                /* reschedule QH iff another request is queued */
+                if (!list_empty(&qh->qtd_list)
+                                && HC_IS_RUNNING(hcd->state)) {
+                        int status;
+
+                        status = qh_schedule(oxu, qh);
+                        spin_unlock_irqrestore(&oxu->lock, flags);
+
+                        if (status != 0) {
+                                /* shouldn't happen often, but ...
+                                 * FIXME kill those tds' urbs
+                                 */
+                                err("can't reschedule qh %p, err %d",
+                                        qh, status);
+                        }
+                        return status;
+                }
+                break;
+        }
+done:
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        return 0;
+}
+
+/* Bulk qh holds the data toggle */
+static void oxu_endpoint_disable(struct usb_hcd *hcd,
+                                        struct usb_host_endpoint *ep)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        unsigned long           flags;
+        struct ehci_qh          *qh, *tmp;
+
+        /* ASSERT:  any requests/urbs are being unlinked */
+        /* ASSERT:  nobody can be submitting urbs for this any more */
+
+rescan:
+        spin_lock_irqsave(&oxu->lock, flags);
+        qh = ep->hcpriv;
+        if (!qh)
+                goto done;
+
+        /* endpoints can be iso streams.  for now, we don't
+         * accelerate iso completions ... so spin a while.
+         */
+        if (qh->hw_info1 == 0) {
+                oxu_vdbg(oxu, "iso delay\n");
+                goto idle_timeout;
+        }
+
+        if (!HC_IS_RUNNING(hcd->state))
+                qh->qh_state = QH_STATE_IDLE;
+        switch (qh->qh_state) {
+        case QH_STATE_LINKED:
+                for (tmp = oxu->async->qh_next.qh;
+                                tmp && tmp != qh;
+                                tmp = tmp->qh_next.qh)
+                        continue;
+                /* periodic qh self-unlinks on empty */
+                if (!tmp)
+                        goto nogood;
+                unlink_async(oxu, qh);
+                /* FALL THROUGH */
+        case QH_STATE_UNLINK:           /* wait for hw to finish? */
+idle_timeout:
+                spin_unlock_irqrestore(&oxu->lock, flags);
+                schedule_timeout_uninterruptible(1);
+                goto rescan;
+        case QH_STATE_IDLE:             /* fully unlinked */
+                if (list_empty(&qh->qtd_list)) {
+                        qh_put(qh);
+                        break;
+                }
+                /* else FALL THROUGH */
+        default:
+nogood:
+                /* caller was supposed to have unlinked any requests;
+                 * that's not our job.  just leak this memory.
+                 */
+                oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
+                        qh, ep->desc.bEndpointAddress, qh->qh_state,
+                        list_empty(&qh->qtd_list) ? "" : "(has tds)");
+                break;
+        }
+        ep->hcpriv = NULL;
+done:
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        return;
+}
+
+static int oxu_get_frame(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+
+        return (readl(&oxu->regs->frame_index) >> 3) %
+                oxu->periodic_size;
+}
+
+/* Build "status change" packet (one or two bytes) from HC registers */
+static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        u32 temp, mask, status = 0;
+        int ports, i, retval = 1;
+        unsigned long flags;
+
+        /* if !USB_SUSPEND, root hub timers won't get shut down ... */
+        if (!HC_IS_RUNNING(hcd->state))
+                return 0;
+
+        /* init status to no-changes */
+        buf[0] = 0;
+        ports = HCS_N_PORTS(oxu->hcs_params);
+        if (ports > 7) {
+                buf[1] = 0;
+                retval++;
+        }
+
+        /* Some boards (mostly VIA?) report bogus overcurrent indications,
+         * causing massive log spam unless we completely ignore them.  It
+         * may be relevant that VIA VT8235 controlers, where PORT_POWER is
+         * always set, seem to clear PORT_OCC and PORT_CSC when writing to
+         * PORT_POWER; that's surprising, but maybe within-spec.
+         */
+        if (!ignore_oc)
+                mask = PORT_CSC | PORT_PEC | PORT_OCC;
+        else
+                mask = PORT_CSC | PORT_PEC;
+
+        /* no hub change reports (bit 0) for now (power, ...) */
+
+        /* port N changes (bit N)? */
+        spin_lock_irqsave(&oxu->lock, flags);
+        for (i = 0; i < ports; i++) {
+                temp = readl(&oxu->regs->port_status[i]);
+
+                /*
+                 * Return status information even for ports with OWNER set.
+                 * Otherwise khubd wouldn't see the disconnect event when a
+                 * high-speed device is switched over to the companion
+                 * controller by the user.
+                 */
+
+                if (!(temp & PORT_CONNECT))
+                        oxu->reset_done[i] = 0;
+                if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
+                                time_after_eq(jiffies, oxu->reset_done[i]))) {
+                        if (i < 7)
+                                buf[0] |= 1 << (i + 1);
+                        else
+                                buf[1] |= 1 << (i - 7);
+                        status = STS_PCD;
+                }
+        }
+        /* FIXME autosuspend idle root hubs */
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        return status ? retval : 0;
+}
+
+/* Returns the speed of a device attached to a port on the root hub. */
+static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
+                                                unsigned int portsc)
+{
+        switch ((portsc >> 26) & 3) {
+        case 0:
+                return 0;
+        case 1:
+                return 1 << USB_PORT_FEAT_LOWSPEED;
+        case 2:
+        default:
+                return 1 << USB_PORT_FEAT_HIGHSPEED;
+        }
+}
+
+#define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
+static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
+                                u16 wValue, u16 wIndex, char *buf, u16 wLength)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int ports = HCS_N_PORTS(oxu->hcs_params);
+        u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
+        u32 temp, status;
+        unsigned long   flags;
+        int retval = 0;
+        unsigned selector;
+
+        /*
+         * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
+         * HCS_INDICATOR may say we can change LEDs to off/amber/green.
+         * (track current state ourselves) ... blink for diagnostics,
+         * power, "this is the one", etc.  EHCI spec supports this.
+         */
+
+        spin_lock_irqsave(&oxu->lock, flags);
+        switch (typeReq) {
+        case ClearHubFeature:
+                switch (wValue) {
+                case C_HUB_LOCAL_POWER:
+                case C_HUB_OVER_CURRENT:
+                        /* no hub-wide feature/status flags */
+                        break;
+                default:
+                        goto error;
+                }
+                break;
+        case ClearPortFeature:
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                temp = readl(status_reg);
+
+                /*
+                 * Even if OWNER is set, so the port is owned by the
+                 * companion controller, khubd needs to be able to clear
+                 * the port-change status bits (especially
+                 * USB_PORT_FEAT_C_CONNECTION).
+                 */
+
+                switch (wValue) {
+                case USB_PORT_FEAT_ENABLE:
+                        writel(temp & ~PORT_PE, status_reg);
+                        break;
+                case USB_PORT_FEAT_C_ENABLE:
+                        writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
+                        break;
+                case USB_PORT_FEAT_SUSPEND:
+                        if (temp & PORT_RESET)
+                                goto error;
+                        if (temp & PORT_SUSPEND) {
+                                if ((temp & PORT_PE) == 0)
+                                        goto error;
+                                /* resume signaling for 20 msec */
+                                temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
+                                writel(temp | PORT_RESUME, status_reg);
+                                oxu->reset_done[wIndex] = jiffies
+                                                + msecs_to_jiffies(20);
+                        }
+                        break;
+                case USB_PORT_FEAT_C_SUSPEND:
+                        /* we auto-clear this feature */
+                        break;
+                case USB_PORT_FEAT_POWER:
+                        if (HCS_PPC(oxu->hcs_params))
+                                writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
+                                          status_reg);
+                        break;
+                case USB_PORT_FEAT_C_CONNECTION:
+                        writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
+                        break;
+                case USB_PORT_FEAT_C_OVER_CURRENT:
+                        writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
+                        break;
+                case USB_PORT_FEAT_C_RESET:
+                        /* GetPortStatus clears reset */
+                        break;
+                default:
+                        goto error;
+                }
+                readl(&oxu->regs->command);     /* unblock posted write */
+                break;
+        case GetHubDescriptor:
+                ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
+                        buf);
+                break;
+        case GetHubStatus:
+                /* no hub-wide feature/status flags */
+                memset(buf, 0, 4);
+                break;
+        case GetPortStatus:
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                status = 0;
+                temp = readl(status_reg);
+
+                /* wPortChange bits */
+                if (temp & PORT_CSC)
+                        status |= 1 << USB_PORT_FEAT_C_CONNECTION;
+                if (temp & PORT_PEC)
+                        status |= 1 << USB_PORT_FEAT_C_ENABLE;
+                if ((temp & PORT_OCC) && !ignore_oc)
+                        status |= 1 << USB_PORT_FEAT_C_OVER_CURRENT;
+
+                /* whoever resumes must GetPortStatus to complete it!! */
+                if (temp & PORT_RESUME) {
+
+                        /* Remote Wakeup received? */
+                        if (!oxu->reset_done[wIndex]) {
+                                /* resume signaling for 20 msec */
+                                oxu->reset_done[wIndex] = jiffies
+                                                + msecs_to_jiffies(20);
+                                /* check the port again */
+                                mod_timer(&oxu_to_hcd(oxu)->rh_timer,
+                                                oxu->reset_done[wIndex]);
+                        }
+
+                        /* resume completed? */
+                        else if (time_after_eq(jiffies,
+                                        oxu->reset_done[wIndex])) {
+                                status |= 1 << USB_PORT_FEAT_C_SUSPEND;
+                                oxu->reset_done[wIndex] = 0;
+
+                                /* stop resume signaling */
+                                temp = readl(status_reg);
+                                writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
+                                        status_reg);
+                                retval = handshake(oxu, status_reg,
+                                           PORT_RESUME, 0, 2000 /* 2msec */);
+                                if (retval != 0) {
+                                        oxu_err(oxu,
+                                                "port %d resume error %d\n",
+                                                wIndex + 1, retval);
+                                        goto error;
+                                }
+                                temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
+                        }
+                }
+
+                /* whoever resets must GetPortStatus to complete it!! */
+                if ((temp & PORT_RESET)
+                                && time_after_eq(jiffies,
+                                        oxu->reset_done[wIndex])) {
+                        status |= 1 << USB_PORT_FEAT_C_RESET;
+                        oxu->reset_done[wIndex] = 0;
+
+                        /* force reset to complete */
+                        writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
+                                        status_reg);
+                        /* REVISIT:  some hardware needs 550+ usec to clear
+                         * this bit; seems too long to spin routinely...
+                         */
+                        retval = handshake(oxu, status_reg,
+                                        PORT_RESET, 0, 750);
+                        if (retval != 0) {
+                                oxu_err(oxu, "port %d reset error %d\n",
+                                        wIndex + 1, retval);
+                                goto error;
+                        }
+
+                        /* see what we found out */
+                        temp = check_reset_complete(oxu, wIndex, status_reg,
+                                        readl(status_reg));
+                }
+
+                /* transfer dedicated ports to the companion hc */
+                if ((temp & PORT_CONNECT) &&
+                                test_bit(wIndex, &oxu->companion_ports)) {
+                        temp &= ~PORT_RWC_BITS;
+                        temp |= PORT_OWNER;
+                        writel(temp, status_reg);
+                        oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
+                        temp = readl(status_reg);
+                }
+
+                /*
+                 * Even if OWNER is set, there's no harm letting khubd
+                 * see the wPortStatus values (they should all be 0 except
+                 * for PORT_POWER anyway).
+                 */
+
+                if (temp & PORT_CONNECT) {
+                        status |= 1 << USB_PORT_FEAT_CONNECTION;
+                        /* status may be from integrated TT */
+                        status |= oxu_port_speed(oxu, temp);
+                }
+                if (temp & PORT_PE)
+                        status |= 1 << USB_PORT_FEAT_ENABLE;
+                if (temp & (PORT_SUSPEND|PORT_RESUME))
+                        status |= 1 << USB_PORT_FEAT_SUSPEND;
+                if (temp & PORT_OC)
+                        status |= 1 << USB_PORT_FEAT_OVER_CURRENT;
+                if (temp & PORT_RESET)
+                        status |= 1 << USB_PORT_FEAT_RESET;
+                if (temp & PORT_POWER)
+                        status |= 1 << USB_PORT_FEAT_POWER;
+
+#ifndef OXU_VERBOSE_DEBUG
+        if (status & ~0xffff)   /* only if wPortChange is interesting */
+#endif
+                dbg_port(oxu, "GetStatus", wIndex + 1, temp);
+                put_unaligned(cpu_to_le32(status), (__le32 *) buf);
+                break;
+        case SetHubFeature:
+                switch (wValue) {
+                case C_HUB_LOCAL_POWER:
+                case C_HUB_OVER_CURRENT:
+                        /* no hub-wide feature/status flags */
+                        break;
+                default:
+                        goto error;
+                }
+                break;
+        case SetPortFeature:
+                selector = wIndex >> 8;
+                wIndex &= 0xff;
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                temp = readl(status_reg);
+                if (temp & PORT_OWNER)
+                        break;
+
+                temp &= ~PORT_RWC_BITS;
+                switch (wValue) {
+                case USB_PORT_FEAT_SUSPEND:
+                        if ((temp & PORT_PE) == 0
+                                        || (temp & PORT_RESET) != 0)
+                                goto error;
+                        if (device_may_wakeup(&hcd->self.root_hub->dev))
+                                temp |= PORT_WAKE_BITS;
+                        writel(temp | PORT_SUSPEND, status_reg);
+                        break;
+                case USB_PORT_FEAT_POWER:
+                        if (HCS_PPC(oxu->hcs_params))
+                                writel(temp | PORT_POWER, status_reg);
+                        break;
+                case USB_PORT_FEAT_RESET:
+                        if (temp & PORT_RESUME)
+                                goto error;
+                        /* line status bits may report this as low speed,
+                         * which can be fine if this root hub has a
+                         * transaction translator built in.
+                         */
+                        oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
+                        temp |= PORT_RESET;
+                        temp &= ~PORT_PE;
+
+                        /*
+                         * caller must wait, then call GetPortStatus
+                         * usb 2.0 spec says 50 ms resets on root
+                         */
+                        oxu->reset_done[wIndex] = jiffies
+                                        + msecs_to_jiffies(50);
+                        writel(temp, status_reg);
+                        break;
+
+                /* For downstream facing ports (these):  one hub port is put
+                 * into test mode according to USB2 11.24.2.13, then the hub
+                 * must be reset (which for root hub now means rmmod+modprobe,
+                 * or else system reboot).  See EHCI 2.3.9 and 4.14 for info
+                 * about the EHCI-specific stuff.
+                 */
+                case USB_PORT_FEAT_TEST:
+                        if (!selector || selector > 5)
+                                goto error;
+                        ehci_quiesce(oxu);
+                        ehci_halt(oxu);
+                        temp |= selector << 16;
+                        writel(temp, status_reg);
+                        break;
+
+                default:
+                        goto error;
+                }
+                readl(&oxu->regs->command);     /* unblock posted writes */
+                break;
+
+        default:
+error:
+                /* "stall" on error */
+                retval = -EPIPE;
+        }
+        spin_unlock_irqrestore(&oxu->lock, flags);
+        return retval;
+}
+
+#ifdef CONFIG_PM
+
+static int oxu_bus_suspend(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        int port;
+        int mask;
+
+        oxu_dbg(oxu, "suspend root hub\n");
+
+        if (time_before(jiffies, oxu->next_statechange))
+                msleep(5);
+
+        port = HCS_N_PORTS(oxu->hcs_params);
+        spin_lock_irq(&oxu->lock);
+
+        /* stop schedules, clean any completed work */
+        if (HC_IS_RUNNING(hcd->state)) {
+                ehci_quiesce(oxu);
+                hcd->state = HC_STATE_QUIESCING;
+        }
+        oxu->command = readl(&oxu->regs->command);
+        if (oxu->reclaim)
+                oxu->reclaim_ready = 1;
+        ehci_work(oxu);
+
+        /* Unlike other USB host controller types, EHCI doesn't have
+         * any notion of "global" or bus-wide suspend.  The driver has
+         * to manually suspend all the active unsuspended ports, and
+         * then manually resume them in the bus_resume() routine.
+         */
+        oxu->bus_suspended = 0;
+        while (port--) {
+                u32 __iomem *reg = &oxu->regs->port_status[port];
+                u32 t1 = readl(reg) & ~PORT_RWC_BITS;
+                u32 t2 = t1;
+
+                /* keep track of which ports we suspend */
+                if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
+                                !(t1 & PORT_SUSPEND)) {
+                        t2 |= PORT_SUSPEND;
+                        set_bit(port, &oxu->bus_suspended);
+                }
+
+                /* enable remote wakeup on all ports */
+                if (device_may_wakeup(&hcd->self.root_hub->dev))
+                        t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
+                else
+                        t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
+
+                if (t1 != t2) {
+                        oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
+                                port + 1, t1, t2);
+                        writel(t2, reg);
+                }
+        }
+
+        /* turn off now-idle HC */
+        del_timer_sync(&oxu->watchdog);
+        ehci_halt(oxu);
+        hcd->state = HC_STATE_SUSPENDED;
+
+        /* allow remote wakeup */
+        mask = INTR_MASK;
+        if (!device_may_wakeup(&hcd->self.root_hub->dev))
+                mask &= ~STS_PCD;
+        writel(mask, &oxu->regs->intr_enable);
+        readl(&oxu->regs->intr_enable);
+
+        oxu->next_statechange = jiffies + msecs_to_jiffies(10);
+        spin_unlock_irq(&oxu->lock);
+        return 0;
+}
+
+/* Caller has locked the root hub, and should reset/reinit on error */
+static int oxu_bus_resume(struct usb_hcd *hcd)
+{
+        struct oxu_hcd *oxu = hcd_to_oxu(hcd);
+        u32 temp;
+        int i;
+
+        if (time_before(jiffies, oxu->next_statechange))
+                msleep(5);
+        spin_lock_irq(&oxu->lock);
+
+        /* Ideally and we've got a real resume here, and no port's power
+         * was lost.  (For PCI, that means Vaux was maintained.)  But we
+         * could instead be restoring a swsusp snapshot -- so that BIOS was
+         * the last user of the controller, not reset/pm hardware keeping
+         * state we gave to it.
+         */
+        temp = readl(&oxu->regs->intr_enable);
+        oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
+
+        /* at least some APM implementations will try to deliver
+         * IRQs right away, so delay them until we're ready.
+         */
+        writel(0, &oxu->regs->intr_enable);
+
+        /* re-init operational registers */
+        writel(0, &oxu->regs->segment);
+        writel(oxu->periodic_dma, &oxu->regs->frame_list);
+        writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
+
+        /* restore CMD_RUN, framelist size, and irq threshold */
+        writel(oxu->command, &oxu->regs->command);
+
+        /* Some controller/firmware combinations need a delay during which
+         * they set up the port statuses.  See Bugzilla #8190. */
+        mdelay(8);
+
+        /* manually resume the ports we suspended during bus_suspend() */
+        i = HCS_N_PORTS(oxu->hcs_params);
+        while (i--) {
+                temp = readl(&oxu->regs->port_status[i]);
+                temp &= ~(PORT_RWC_BITS
+                        | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
+                if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
+                        oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
+                        temp |= PORT_RESUME;
+                }
+                writel(temp, &oxu->regs->port_status[i]);
+        }
+        i = HCS_N_PORTS(oxu->hcs_params);
+        mdelay(20);
+        while (i--) {
+                temp = readl(&oxu->regs->port_status[i]);
+                if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
+                        temp &= ~(PORT_RWC_BITS | PORT_RESUME);
+                        writel(temp, &oxu->regs->port_status[i]);
+                        oxu_vdbg(oxu, "resumed port %d\n", i + 1);
+                }
+        }
+        (void) readl(&oxu->regs->command);
+
+        /* maybe re-activate the schedule(s) */
+        temp = 0;
+        if (oxu->async->qh_next.qh)
+                temp |= CMD_ASE;
+        if (oxu->periodic_sched)
+                temp |= CMD_PSE;
+        if (temp) {
+                oxu->command |= temp;
+                writel(oxu->command, &oxu->regs->command);
+        }
+
+        oxu->next_statechange = jiffies + msecs_to_jiffies(5);
+        hcd->state = HC_STATE_RUNNING;
+
+        /* Now we can safely re-enable irqs */
+        writel(INTR_MASK, &oxu->regs->intr_enable);
+
+        spin_unlock_irq(&oxu->lock);
+        return 0;
+}
+
+#else
+
+static int oxu_bus_suspend(struct usb_hcd *hcd)
+{
+        return 0;
+}
+
+static int oxu_bus_resume(struct usb_hcd *hcd)
+{
+        return 0;
+}
+
+#endif  /* CONFIG_PM */
+
+static const struct hc_driver oxu_hc_driver = {
+        .description =          "oxu210hp_hcd",
+        .product_desc =         "oxu210hp HCD",
+        .hcd_priv_size =        sizeof(struct oxu_hcd),
+
+        /*
+         * Generic hardware linkage
+         */
+        .irq =                  oxu_irq,
+        .flags =                HCD_MEMORY | HCD_USB2,
+
+        /*
+         * Basic lifecycle operations
+         */
+        .reset =                oxu_reset,
+        .start =                oxu_run,
+        .stop =                 oxu_stop,
+        .shutdown =             oxu_shutdown,
+
+        /*
+         * Managing i/o requests and associated device resources
+         */
+        .urb_enqueue =          oxu_urb_enqueue,
+        .urb_dequeue =          oxu_urb_dequeue,
+        .endpoint_disable =     oxu_endpoint_disable,
+
+        /*
+         * Scheduling support
+         */
+        .get_frame_number =     oxu_get_frame,
+
+        /*
+         * Root hub support
+         */
+        .hub_status_data =      oxu_hub_status_data,
+        .hub_control =          oxu_hub_control,
+        .bus_suspend =          oxu_bus_suspend,
+        .bus_resume =           oxu_bus_resume,
+};
+
+/*
+ * Module stuff
+ */
+
+static void oxu_configuration(struct platform_device *pdev, void *base)
+{
+        u32 tmp;
+
+        /* Initialize top level registers.
+         * First write ever
+         */
+        oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
+        oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
+        oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
+
+        tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
+        oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
+
+        oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
+                                        OXU_COMPARATOR | OXU_ASO_OP);
+
+        tmp = oxu_readl(base, OXU_CLKCTRL_SET);
+        oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
+
+        /* Clear all top interrupt enable */
+        oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
+
+        /* Clear all top interrupt status */
+        oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
+
+        /* Enable all needed top interrupt except OTG SPH core */
+        oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
+}
+
+static int oxu_verify_id(struct platform_device *pdev, void *base)
+{
+        u32 id;
+        char *bo[] = {
+                "reserved",
+                "128-pin LQFP",
+                "84-pin TFBGA",
+                "reserved",
+        };
+
+        /* Read controller signature register to find a match */
+        id = oxu_readl(base, OXU_DEVICEID);
+        dev_info(&pdev->dev, "device ID %x\n", id);
+        if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
+                return -1;
+
+        dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
+                id >> OXU_REV_SHIFT,
+                bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
+                (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
+                (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
+
+        return 0;
+}
+
+static const struct hc_driver oxu_hc_driver;
+static struct usb_hcd *oxu_create(struct platform_device *pdev,
+                                unsigned long memstart, unsigned long memlen,
+                                void *base, int irq, int otg)
+{
+        struct device *dev = &pdev->dev;
+
+        struct usb_hcd *hcd;
+        struct oxu_hcd *oxu;
+        int ret;
+
+        /* Set endian mode and host mode */
+        oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
+                                OXU_USBMODE,
+                                OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
+
+        hcd = usb_create_hcd(&oxu_hc_driver, dev,
+                                otg ? "oxu210hp_otg" : "oxu210hp_sph");
+        if (!hcd)
+                return ERR_PTR(-ENOMEM);
+
+        hcd->rsrc_start = memstart;
+        hcd->rsrc_len = memlen;
+        hcd->regs = base;
+        hcd->irq = irq;
+        hcd->state = HC_STATE_HALT;
+
+        oxu = hcd_to_oxu(hcd);
+        oxu->is_otg = otg;
+
+        ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
+        if (ret < 0)
+                return ERR_PTR(ret);
+
+        return hcd;
+}
+
+static int oxu_init(struct platform_device *pdev,
+                                unsigned long memstart, unsigned long memlen,
+                                void *base, int irq)
+{
+        struct oxu_info *info = platform_get_drvdata(pdev);
+        struct usb_hcd *hcd;
+        int ret;
+
+        /* First time configuration at start up */
+        oxu_configuration(pdev, base);
+
+        ret = oxu_verify_id(pdev, base);
+        if (ret) {
+                dev_err(&pdev->dev, "no devices found!\n");
+                return -ENODEV;
+        }
+
+        /* Create the OTG controller */
+        hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
+        if (IS_ERR(hcd)) {
+                dev_err(&pdev->dev, "cannot create OTG controller!\n");
+                ret = PTR_ERR(hcd);
+                goto error_create_otg;
+        }
+        info->hcd[0] = hcd;
+
+        /* Create the SPH host controller */
+        hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
+        if (IS_ERR(hcd)) {
+                dev_err(&pdev->dev, "cannot create SPH controller!\n");
+                ret = PTR_ERR(hcd);
+                goto error_create_sph;
+        }
+        info->hcd[1] = hcd;
+
+        oxu_writel(base, OXU_CHIPIRQEN_SET,
+                oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
+
+        return 0;
+
+error_create_sph:
+        usb_remove_hcd(info->hcd[0]);
+        usb_put_hcd(info->hcd[0]);
+
+error_create_otg:
+        return ret;
+}
+
+static int oxu_drv_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        void *base;
+        unsigned long memstart, memlen;
+        int irq, ret;
+        struct oxu_info *info;
+
+        if (usb_disabled())
+                return -ENODEV;
+
+        /*
+         * Get the platform resources
+         */
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!res) {
+                dev_err(&pdev->dev,
+                        "no IRQ! Check %s setup!\n", dev_name(&pdev->dev));
+                return -ENODEV;
+        }
+        irq = res->start;
+        dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "no registers address! Check %s setup!\n",
+                        dev_name(&pdev->dev));
+                return -ENODEV;
+        }
+        memstart = res->start;
+        memlen = res->end - res->start + 1;
+        dev_dbg(&pdev->dev, "MEM resource %lx-%lx\n", memstart, memlen);
+        if (!request_mem_region(memstart, memlen,
+                                oxu_hc_driver.description)) {
+                dev_dbg(&pdev->dev, "memory area already in use\n");
+                return -EBUSY;
+        }
+
+        ret = set_irq_type(irq, IRQF_TRIGGER_FALLING);
+        if (ret) {
+                dev_err(&pdev->dev, "error setting irq type\n");
+                ret = -EFAULT;
+                goto error_set_irq_type;
+        }
+
+        base = ioremap(memstart, memlen);
+        if (!base) {
+                dev_dbg(&pdev->dev, "error mapping memory\n");
+                ret = -EFAULT;
+                goto error_ioremap;
+        }
+
+        /* Allocate a driver data struct to hold useful info for both
+         * SPH & OTG devices
+         */
+        info = kzalloc(sizeof(struct oxu_info), GFP_KERNEL);
+        if (!info) {
+                dev_dbg(&pdev->dev, "error allocating memory\n");
+                ret = -EFAULT;
+                goto error_alloc;
+        }
+        platform_set_drvdata(pdev, info);
+
+        ret = oxu_init(pdev, memstart, memlen, base, irq);
+        if (ret < 0) {
+                dev_dbg(&pdev->dev, "cannot init USB devices\n");
+                goto error_init;
+        }
+
+        dev_info(&pdev->dev, "devices enabled and running\n");
+        platform_set_drvdata(pdev, info);
+
+        return 0;
+
+error_init:
+        kfree(info);
+        platform_set_drvdata(pdev, NULL);
+
+error_alloc:
+        iounmap(base);
+
+error_set_irq_type:
+error_ioremap:
+        release_mem_region(memstart, memlen);
+
+        dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
+        return ret;
+}
+
+static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
+{
+        usb_remove_hcd(hcd);
+        usb_put_hcd(hcd);
+}
+
+static int oxu_drv_remove(struct platform_device *pdev)
+{
+        struct oxu_info *info = platform_get_drvdata(pdev);
+        unsigned long memstart = info->hcd[0]->rsrc_start,
+                        memlen = info->hcd[0]->rsrc_len;
+        void *base = info->hcd[0]->regs;
+
+        oxu_remove(pdev, info->hcd[0]);
+        oxu_remove(pdev, info->hcd[1]);
+
+        iounmap(base);
+        release_mem_region(memstart, memlen);
+
+        kfree(info);
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static void oxu_drv_shutdown(struct platform_device *pdev)
+{
+        oxu_drv_remove(pdev);
+}
+
+#if 0
+/* FIXME: TODO */
+static int oxu_drv_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct usb_hcd *hcd = dev_get_drvdata(dev);
+
+        return 0;
+}
+
+static int oxu_drv_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct usb_hcd *hcd = dev_get_drvdata(dev);
+
+        return 0;
+}
+#else
+#define oxu_drv_suspend NULL
+#define oxu_drv_resume  NULL
+#endif
+
+static struct platform_driver oxu_driver = {
+        .probe          = oxu_drv_probe,
+        .remove         = oxu_drv_remove,
+        .shutdown       = oxu_drv_shutdown,
+        .suspend        = oxu_drv_suspend,
+        .resume         = oxu_drv_resume,
+        .driver = {
+                .name = "oxu210hp-hcd",
+                .bus = &platform_bus_type
+        }
+};
+
+static int __init oxu_module_init(void)
+{
+        int retval = 0;
+
+        retval = platform_driver_register(&oxu_driver);
+        if (retval < 0)
+                return retval;
+
+        return retval;
+}
+
+static void __exit oxu_module_cleanup(void)
+{
+        platform_driver_unregister(&oxu_driver);
+}
+
+module_init(oxu_module_init);
+module_exit(oxu_module_cleanup);
+
+MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
+MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/host/oxu210hp.h b/drivers/usb/host/oxu210hp.h
new file mode 100644
index 000000000000..8910e271cc7d
--- /dev/null
+++ b/drivers/usb/host/oxu210hp.h
@@ -0,0 +1,447 @@
+/*
+ * Host interface registers
+ */
+
+#define OXU_DEVICEID                    0x00
+        #define OXU_REV_MASK            0xffff0000
+        #define OXU_REV_SHIFT           16
+        #define OXU_REV_2100            0x2100
+        #define OXU_BO_SHIFT            8
+        #define OXU_BO_MASK             (0x3 << OXU_BO_SHIFT)
+        #define OXU_MAJ_REV_SHIFT       4
+        #define OXU_MAJ_REV_MASK        (0xf << OXU_MAJ_REV_SHIFT)
+        #define OXU_MIN_REV_SHIFT       0
+        #define OXU_MIN_REV_MASK        (0xf << OXU_MIN_REV_SHIFT)
+#define OXU_HOSTIFCONFIG                0x04
+#define OXU_SOFTRESET                   0x08
+        #define OXU_SRESET              (1 << 0)
+
+#define OXU_PIOBURSTREADCTRL            0x0C
+
+#define OXU_CHIPIRQSTATUS               0x10
+#define OXU_CHIPIRQEN_SET               0x14
+#define OXU_CHIPIRQEN_CLR               0x18
+        #define OXU_USBSPHLPWUI         0x00000080
+        #define OXU_USBOTGLPWUI         0x00000040
+        #define OXU_USBSPHI             0x00000002
+        #define OXU_USBOTGI             0x00000001
+
+#define OXU_CLKCTRL_SET                 0x1C
+        #define OXU_SYSCLKEN            0x00000008
+        #define OXU_USBSPHCLKEN         0x00000002
+        #define OXU_USBOTGCLKEN         0x00000001
+
+#define OXU_ASO                         0x68
+        #define OXU_SPHPOEN             0x00000100
+        #define OXU_OVRCCURPUPDEN       0x00000800
+        #define OXU_ASO_OP              (1 << 10)
+        #define OXU_COMPARATOR          0x000004000
+
+#define OXU_USBMODE                     0x1A8
+        #define OXU_VBPS                0x00000020
+        #define OXU_ES_LITTLE           0x00000000
+        #define OXU_CM_HOST_ONLY        0x00000003
+
+/*
+ * Proper EHCI structs & defines
+ */
+
+/* Magic numbers that can affect system performance */
+#define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
+#define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
+#define EHCI_TUNE_RL_TT         0
+#define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
+#define EHCI_TUNE_MULT_TT       1
+#define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
+
+struct oxu_hcd;
+
+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
+
+/* Section 2.2 Host Controller Capability Registers */
+struct ehci_caps {
+        /* these fields are specified as 8 and 16 bit registers,
+         * but some hosts can't perform 8 or 16 bit PCI accesses.
+         */
+        u32             hc_capbase;
+#define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
+#define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
+        u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
+#define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
+#define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
+
+        u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
+#define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
+        u8              portroute[8];    /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+        /* USBCMD: offset 0x00 */
+        u32             command;
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK        (1<<11)         /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
+#define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
+#define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
+#define CMD_ASE         (1<<5)          /* async schedule enable */
+#define CMD_PSE         (1<<4)          /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET       (1<<1)          /* reset HC not bus */
+#define CMD_RUN         (1<<0)          /* start/stop HC */
+
+        /* USBSTS: offset 0x04 */
+        u32             status;
+#define STS_ASS         (1<<15)         /* Async Schedule Status */
+#define STS_PSS         (1<<14)         /* Periodic Schedule Status */
+#define STS_RECL        (1<<13)         /* Reclamation */
+#define STS_HALT        (1<<12)         /* Not running (any reason) */
+/* some bits reserved */
+        /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA         (1<<5)          /* Interrupted on async advance */
+#define STS_FATAL       (1<<4)          /* such as some PCI access errors */
+#define STS_FLR         (1<<3)          /* frame list rolled over */
+#define STS_PCD         (1<<2)          /* port change detect */
+#define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
+#define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
+
+#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
+
+        /* USBINTR: offset 0x08 */
+        u32             intr_enable;
+
+        /* FRINDEX: offset 0x0C */
+        u32             frame_index;    /* current microframe number */
+        /* CTRLDSSEGMENT: offset 0x10 */
+        u32             segment;        /* address bits 63:32 if needed */
+        /* PERIODICLISTBASE: offset 0x14 */
+        u32             frame_list;     /* points to periodic list */
+        /* ASYNCLISTADDR: offset 0x18 */
+        u32             async_next;     /* address of next async queue head */
+
+        u32             reserved[9];
+
+        /* CONFIGFLAG: offset 0x40 */
+        u32             configured_flag;
+#define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
+
+        /* PORTSC: offset 0x44 */
+        u32             port_status[0]; /* up to N_PORTS */
+/* 31:23 reserved */
+#define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
+#define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_LED_OFF    (0<<14)
+#define PORT_LED_AMBER  (1<<14)
+#define PORT_LED_GREEN  (2<<14)
+#define PORT_LED_MASK   (3<<14)
+#define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
+#define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_RESET      (1<<8)          /* reset port */
+#define PORT_SUSPEND    (1<<7)          /* suspend port */
+#define PORT_RESUME     (1<<6)          /* resume it */
+#define PORT_OCC        (1<<5)          /* over current change */
+#define PORT_OC         (1<<4)          /* over current active */
+#define PORT_PEC        (1<<3)          /* port enable change */
+#define PORT_PE         (1<<2)          /* port enable */
+#define PORT_CSC        (1<<1)          /* connect status change */
+#define PORT_CONNECT    (1<<0)          /* device connected */
+#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console.  (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+        u32     control;
+#define DBGP_OWNER      (1<<30)
+#define DBGP_ENABLED    (1<<28)
+#define DBGP_DONE       (1<<16)
+#define DBGP_INUSE      (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+#       define DBGP_ERR_BAD     1
+#       define DBGP_ERR_SIGNAL  2
+#define DBGP_ERROR      (1<<6)
+#define DBGP_GO         (1<<5)
+#define DBGP_OUT        (1<<4)
+#define DBGP_LEN(x)     (((x)>>0)&0x0f)
+        u32     pids;
+#define DBGP_PID_GET(x)         (((x)>>16)&0xff)
+#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
+        u32     data03;
+        u32     data47;
+        u32     address;
+#define DBGP_EPADDR(dev, ep)    (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+
+
+#define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
+
+/*
+ * EHCI Specification 0.95 Section 3.5
+ * QTD: describe data transfer components (buffer, direction, ...)
+ * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
+ *
+ * These are associated only with "QH" (Queue Head) structures,
+ * used with control, bulk, and interrupt transfers.
+ */
+struct ehci_qtd {
+        /* first part defined by EHCI spec */
+        __le32                  hw_next;                /* see EHCI 3.5.1 */
+        __le32                  hw_alt_next;            /* see EHCI 3.5.2 */
+        __le32                  hw_token;               /* see EHCI 3.5.3 */
+#define QTD_TOGGLE      (1 << 31)       /* data toggle */
+#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
+#define QTD_IOC         (1 << 15)       /* interrupt on complete */
+#define QTD_CERR(tok)   (((tok)>>10) & 0x3)
+#define QTD_PID(tok)    (((tok)>>8) & 0x3)
+#define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
+#define QTD_STS_HALT    (1 << 6)        /* halted on error */
+#define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
+#define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
+#define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
+#define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
+#define QTD_STS_STS     (1 << 1)        /* split transaction state */
+#define QTD_STS_PING    (1 << 0)        /* issue PING? */
+        __le32                  hw_buf[5];              /* see EHCI 3.5.4 */
+        __le32                  hw_buf_hi[5];           /* Appendix B */
+
+        /* the rest is HCD-private */
+        dma_addr_t              qtd_dma;                /* qtd address */
+        struct list_head        qtd_list;               /* sw qtd list */
+        struct urb              *urb;                   /* qtd's urb */
+        size_t                  length;                 /* length of buffer */
+
+        u32                     qtd_buffer_len;
+        void                    *buffer;
+        dma_addr_t              buffer_dma;
+        void                    *transfer_buffer;
+        void                    *transfer_dma;
+} __attribute__ ((aligned(32)));
+
+/* mask NakCnt+T in qh->hw_alt_next */
+#define QTD_MASK __constant_cpu_to_le32 (~0x1f)
+
+#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
+
+/* Type tag from {qh, itd, sitd, fstn}->hw_next */
+#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
+
+/* values for that type tag */
+#define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
+
+/* next async queue entry, or pointer to interrupt/periodic QH */
+#define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
+
+/* for periodic/async schedules and qtd lists, mark end of list */
+#define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
+
+/*
+ * Entries in periodic shadow table are pointers to one of four kinds
+ * of data structure.  That's dictated by the hardware; a type tag is
+ * encoded in the low bits of the hardware's periodic schedule.  Use
+ * Q_NEXT_TYPE to get the tag.
+ *
+ * For entries in the async schedule, the type tag always says "qh".
+ */
+union ehci_shadow {
+        struct ehci_qh          *qh;            /* Q_TYPE_QH */
+        __le32                  *hw_next;       /* (all types) */
+        void                    *ptr;
+};
+
+/*
+ * EHCI Specification 0.95 Section 3.6
+ * QH: describes control/bulk/interrupt endpoints
+ * See Fig 3-7 "Queue Head Structure Layout".
+ *
+ * These appear in both the async and (for interrupt) periodic schedules.
+ */
+
+struct ehci_qh {
+        /* first part defined by EHCI spec */
+        __le32                  hw_next;         /* see EHCI 3.6.1 */
+        __le32                  hw_info1;       /* see EHCI 3.6.2 */
+#define QH_HEAD         0x00008000
+        __le32                  hw_info2;       /* see EHCI 3.6.2 */
+#define QH_SMASK        0x000000ff
+#define QH_CMASK        0x0000ff00
+#define QH_HUBADDR      0x007f0000
+#define QH_HUBPORT      0x3f800000
+#define QH_MULT         0xc0000000
+        __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
+
+        /* qtd overlay (hardware parts of a struct ehci_qtd) */
+        __le32                  hw_qtd_next;
+        __le32                  hw_alt_next;
+        __le32                  hw_token;
+        __le32                  hw_buf[5];
+        __le32                  hw_buf_hi[5];
+
+        /* the rest is HCD-private */
+        dma_addr_t              qh_dma;         /* address of qh */
+        union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
+        struct list_head        qtd_list;       /* sw qtd list */
+        struct ehci_qtd         *dummy;
+        struct ehci_qh          *reclaim;       /* next to reclaim */
+
+        struct oxu_hcd          *oxu;
+        struct kref             kref;
+        unsigned                stamp;
+
+        u8                      qh_state;
+#define QH_STATE_LINKED         1               /* HC sees this */
+#define QH_STATE_UNLINK         2               /* HC may still see this */
+#define QH_STATE_IDLE           3               /* HC doesn't see this */
+#define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
+#define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
+
+        /* periodic schedule info */
+        u8                      usecs;          /* intr bandwidth */
+        u8                      gap_uf;         /* uframes split/csplit gap */
+        u8                      c_usecs;        /* ... split completion bw */
+        u16                     tt_usecs;       /* tt downstream bandwidth */
+        unsigned short          period;         /* polling interval */
+        unsigned short          start;          /* where polling starts */
+#define NO_FRAME ((unsigned short)~0)                   /* pick new start */
+        struct usb_device       *dev;           /* access to TT */
+} __attribute__ ((aligned(32)));
+
+/*
+ * Proper OXU210HP structs
+ */
+
+#define OXU_OTG_CORE_OFFSET     0x00400
+#define OXU_OTG_CAP_OFFSET      (OXU_OTG_CORE_OFFSET + 0x100)
+#define OXU_SPH_CORE_OFFSET     0x00800
+#define OXU_SPH_CAP_OFFSET      (OXU_SPH_CORE_OFFSET + 0x100)
+
+#define OXU_OTG_MEM             0xE000
+#define OXU_SPH_MEM             0x16000
+
+/* Only how many elements & element structure are specifies here. */
+/* 2 host controllers are enabled - total size <= 28 kbytes */
+#define DEFAULT_I_TDPS          1024
+#define QHEAD_NUM               16
+#define QTD_NUM                 32
+#define SITD_NUM                8
+#define MURB_NUM                8
+
+#define BUFFER_NUM              8
+#define BUFFER_SIZE             512
+
+struct oxu_info {
+        struct usb_hcd *hcd[2];
+};
+
+struct oxu_buf {
+        u8                      buffer[BUFFER_SIZE];
+} __attribute__ ((aligned(BUFFER_SIZE)));
+
+struct oxu_onchip_mem {
+        struct oxu_buf          db_pool[BUFFER_NUM];
+
+        u32                     frame_list[DEFAULT_I_TDPS];
+        struct ehci_qh          qh_pool[QHEAD_NUM];
+        struct ehci_qtd         qtd_pool[QTD_NUM];
+} __attribute__ ((aligned(4 << 10)));
+
+#define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
+
+struct oxu_murb {
+        struct urb              urb;
+        struct urb              *main;
+        u8                      last;
+};
+
+struct oxu_hcd {                                /* one per controller */
+        unsigned int            is_otg:1;
+
+        u8                      qh_used[QHEAD_NUM];
+        u8                      qtd_used[QTD_NUM];
+        u8                      db_used[BUFFER_NUM];
+        u8                      murb_used[MURB_NUM];
+
+        struct oxu_onchip_mem   __iomem *mem;
+        spinlock_t              mem_lock;
+
+        struct timer_list       urb_timer;
+
+        struct ehci_caps __iomem *caps;
+        struct ehci_regs __iomem *regs;
+
+        __u32                   hcs_params;     /* cached register copy */
+        spinlock_t              lock;
+
+        /* async schedule support */
+        struct ehci_qh          *async;
+        struct ehci_qh          *reclaim;
+        unsigned                reclaim_ready:1;
+        unsigned                scanning:1;
+
+        /* periodic schedule support */
+        unsigned                periodic_size;
+        __le32                  *periodic;      /* hw periodic table */
+        dma_addr_t              periodic_dma;
+        unsigned                i_thresh;       /* uframes HC might cache */
+
+        union ehci_shadow       *pshadow;       /* mirror hw periodic table */
+        int                     next_uframe;    /* scan periodic, start here */
+        unsigned                periodic_sched; /* periodic activity count */
+
+        /* per root hub port */
+        unsigned long           reset_done[EHCI_MAX_ROOT_PORTS];
+        /* bit vectors (one bit per port) */
+        unsigned long           bus_suspended;  /* which ports were
+                                                 * already suspended at the
+                                                 * start of a bus suspend
+                                                 */
+        unsigned long           companion_ports;/* which ports are dedicated
+                                                 * to the companion controller
+                                                 */
+
+        struct timer_list       watchdog;
+        unsigned long           actions;
+        unsigned                stamp;
+        unsigned long           next_statechange;
+        u32                     command;
+
+        /* SILICON QUIRKS */
+        struct list_head        urb_list;       /* this is the head to urb
+                                                 * queue that didn't get enough
+                                                 * resources
+                                                 */
+        struct oxu_murb         *murb_pool;     /* murb per split big urb */
+        unsigned urb_len;
+
+        u8                      sbrn;           /* packed release number */
+};
+
+#define EHCI_IAA_JIFFIES        (HZ/100)        /* arbitrary; ~10 msec */
+#define EHCI_IO_JIFFIES         (HZ/10)         /* io watchdog > irq_thresh */
+#define EHCI_ASYNC_JIFFIES      (HZ/20)         /* async idle timeout */
+#define EHCI_SHRINK_JIFFIES     (HZ/200)        /* async qh unlink delay */
+
+enum ehci_timer_action {
+        TIMER_IO_WATCHDOG,
+        TIMER_IAA_WATCHDOG,
+        TIMER_ASYNC_SHRINK,
+        TIMER_ASYNC_OFF,
+};
+
+#include <linux/oxu210hp.h>
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index ae6e70edd745..75b69847918e 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -172,9 +172,9 @@ static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
         if (!mmio_resource_enabled(pdev, 0))
                 return;
 
-        base = ioremap_nocache(pci_resource_start(pdev, 0),
-                                     pci_resource_len(pdev, 0));
-        if (base == NULL) return;
+        base = pci_ioremap_bar(pdev, 0);
+        if (base == NULL)
+                return;
 
 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 #ifndef __hppa__
@@ -221,9 +221,9 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
         if (!mmio_resource_enabled(pdev, 0))
                 return;
 
-        base = ioremap_nocache(pci_resource_start(pdev, 0),
-                                pci_resource_len(pdev, 0));
-        if (base == NULL) return;
+        base = pci_ioremap_bar(pdev, 0);
+        if (base == NULL)
+                return;
 
         cap_length = readb(base);
         op_reg_base = base + cap_length;
@@ -271,7 +271,7 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
                         /* if boot firmware now owns EHCI, spin till
                          * it hands it over.
                          */
-                        msec = 5000;
+                        msec = 1000;
                         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
                                 tried_handoff = 1;
                                 msleep(10);
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index c21f14e0666a..319041205b57 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -2275,7 +2275,6 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
         return 0;
 }
 
-#define resource_len(r) (((r)->end - (r)->start) + 1)
 static int __init r8a66597_probe(struct platform_device *pdev)
 {
 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
@@ -2296,11 +2295,10 @@ static int __init r8a66597_probe(struct platform_device *pdev)
                 goto clean_up;
         }
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-                                           (char *)hcd_name);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res) {
                 ret = -ENODEV;
-                dev_err(&pdev->dev, "platform_get_resource_byname error.\n");
+                dev_err(&pdev->dev, "platform_get_resource error.\n");
                 goto clean_up;
         }
 
@@ -2315,7 +2313,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
         irq = ires->start;
         irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
 
-        reg = ioremap(res->start, resource_len(res));
+        reg = ioremap(res->start, resource_size(res));
         if (reg == NULL) {
                 ret = -ENOMEM;
                 dev_err(&pdev->dev, "ioremap error.\n");
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index cf5e4cf7ea42..4e221060f58c 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -942,6 +942,8 @@ static struct pci_driver uhci_pci_driver = {
 
 #ifdef  CONFIG_PM
         .suspend =      usb_hcd_pci_suspend,
+        .suspend_late = usb_hcd_pci_suspend_late,
+        .resume_early = usb_hcd_pci_resume_early,
         .resume =       usb_hcd_pci_resume,
 #endif  /* PM */
 };
diff --git a/drivers/usb/image/microtek.c b/drivers/usb/image/microtek.c
index 885867a86de8..4541dfcea88f 100644
--- a/drivers/usb/image/microtek.c
+++ b/drivers/usb/image/microtek.c
@@ -350,17 +350,16 @@ static int mts_scsi_abort(struct scsi_cmnd *srb)
 static int mts_scsi_host_reset(struct scsi_cmnd *srb)
 {
         struct mts_desc* desc = (struct mts_desc*)(srb->device->host->hostdata[0]);
-        int result, rc;
+        int result;
 
         MTS_DEBUG_GOT_HERE();
         mts_debug_dump(desc);
 
-        rc = usb_lock_device_for_reset(desc->usb_dev, desc->usb_intf);
-        if (rc < 0)
-                return FAILED;
-        result = usb_reset_device(desc->usb_dev);
-        if (rc)
+        result = usb_lock_device_for_reset(desc->usb_dev, desc->usb_intf);
+        if (result == 0) {
+                result = usb_reset_device(desc->usb_dev);
                 usb_unlock_device(desc->usb_dev);
+        }
         return result ? FAILED : SUCCESS;
 }
 
diff --git a/drivers/usb/misc/berry_charge.c b/drivers/usb/misc/berry_charge.c
index 24e2dc3148a4..c05a85bc5925 100644
--- a/drivers/usb/misc/berry_charge.c
+++ b/drivers/usb/misc/berry_charge.c
@@ -123,6 +123,11 @@ static int berry_probe(struct usb_interface *intf,
 {
         struct usb_device *udev = interface_to_usbdev(intf);
 
+        if (udev->bus_mA < 500) {
+                dbg(&udev->dev, "Not enough power to charge available\n");
+                return -ENODEV;
+        }
+
         dbg(&udev->dev, "Power is set to %dmA\n",
             udev->actconfig->desc.bMaxPower * 2);
 
diff --git a/drivers/usb/misc/emi26.c b/drivers/usb/misc/emi26.c
index e762beb5f3c6..879a980ca8c4 100644
--- a/drivers/usb/misc/emi26.c
+++ b/drivers/usb/misc/emi26.c
@@ -160,7 +160,7 @@ static int emi26_load_firmware (struct usb_device *dev)
                         err("%s - error loading firmware: error = %d", __func__, err);
                         goto wraperr;
                 }
-        } while (i > 0);
+        } while (rec);
 
         /* Assert reset (stop the CPU in the EMI) */
         err = emi26_set_reset(dev,1);
diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c
index 444c69c447be..5f1a19d1497d 100644
--- a/drivers/usb/misc/usbtest.c
+++ b/drivers/usb/misc/usbtest.c
@@ -192,8 +192,6 @@ static struct urb *simple_alloc_urb (
 {
         struct urb              *urb;
 
-        if (bytes < 0)
-                return NULL;
         urb = usb_alloc_urb (0, GFP_KERNEL);
         if (!urb)
                 return urb;
diff --git a/drivers/usb/mon/Kconfig b/drivers/usb/mon/Kconfig
index deb9ddffa402..f28f350cd96a 100644
--- a/drivers/usb/mon/Kconfig
+++ b/drivers/usb/mon/Kconfig
@@ -3,14 +3,13 @@
 #
 
 config USB_MON
-        bool "USB Monitor"
-        depends on USB!=n
-        default y
+        tristate "USB Monitor"
+        depends on USB
+        default y if USB=y
+        default m if USB=m
         help
-          If you say Y here, a component which captures the USB traffic
+          If you select this option, a component which captures the USB traffic
           between peripheral-specific drivers and HC drivers will be built.
           For more information, see <file:Documentation/usb/usbmon.txt>.
 
-          This is somewhat experimental at this time, but it should be safe.
-
-          If unsure, say Y.
+          If unsure, say Y (if allowed), otherwise M.
diff --git a/drivers/usb/mon/Makefile b/drivers/usb/mon/Makefile
index 0f76ed5e1617..c6516b566731 100644
--- a/drivers/usb/mon/Makefile
+++ b/drivers/usb/mon/Makefile
@@ -4,5 +4,4 @@
 
 usbmon-objs     := mon_main.o mon_stat.o mon_text.o mon_bin.o mon_dma.o
 
-# This does not use CONFIG_USB_MON because we want this to use a tristate.
-obj-$(CONFIG_USB)       += usbmon.o
+obj-$(CONFIG_USB_MON)   += usbmon.o
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 4b9542bbb35c..5af7379cd9a3 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -11,7 +11,7 @@ config USB_MUSB_HDRC
         depends on (USB || USB_GADGET) && HAVE_CLK
         depends on !SUPERH
         select TWL4030_USB if MACH_OMAP_3430SDP
-        tristate 'Inventra Highspeed Dual Role Controller (TI, ...)'
+        tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
         help
           Say Y here if your system has a dual role high speed USB
           controller based on the Mentor Graphics silicon IP.  Then
@@ -22,6 +22,9 @@ config USB_MUSB_HDRC
           Texas Instruments parts using this IP include DaVinci 644x,
           OMAP 243x, OMAP 343x, and TUSB 6010.
 
+          Analog Devices parts using this IP include Blackfin BF54x,
+          BF525 and BF527.
+
           If you do not know what this is, please say N.
 
           To compile this driver as a module, choose M here; the
@@ -33,6 +36,8 @@ config USB_MUSB_SOC
         default y if ARCH_DAVINCI
         default y if ARCH_OMAP2430
         default y if ARCH_OMAP34XX
+        default y if (BF54x && !BF544)
+        default y if (BF52x && !BF522 && !BF523)
 
 comment "DaVinci 644x USB support"
         depends on USB_MUSB_HDRC && ARCH_DAVINCI
@@ -43,6 +48,9 @@ comment "OMAP 243x high speed USB support"
 comment "OMAP 343x high speed USB support"
         depends on USB_MUSB_HDRC && ARCH_OMAP34XX
 
+comment "Blackfin high speed USB Support"
+        depends on USB_MUSB_HDRC && (BF54x && !BF544) || (BF52x && !BF522 && !BF523)
+
 config USB_TUSB6010
         boolean "TUSB 6010 support"
         depends on USB_MUSB_HDRC && !USB_MUSB_SOC
@@ -142,7 +150,7 @@ config MUSB_PIO_ONLY
 config USB_INVENTRA_DMA
         bool
         depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
-        default ARCH_OMAP2430 || ARCH_OMAP34XX
+        default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN
         help
           Enable DMA transfers using Mentor's engine.
 
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index b6af0d687a73..85710ccc1887 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -22,6 +22,14 @@ ifeq ($(CONFIG_ARCH_OMAP3430),y)
         musb_hdrc-objs  += omap2430.o
 endif
 
+ifeq ($(CONFIG_BF54x),y)
+        musb_hdrc-objs  += blackfin.o
+endif
+
+ifeq ($(CONFIG_BF52x),y)
+        musb_hdrc-objs  += blackfin.o
+endif
+
 ifeq ($(CONFIG_USB_GADGET_MUSB_HDRC),y)
         musb_hdrc-objs          += musb_gadget_ep0.o musb_gadget.o
 endif
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
new file mode 100644
index 000000000000..786134852092
--- /dev/null
+++ b/drivers/usb/musb/blackfin.c
@@ -0,0 +1,320 @@
+/*
+ * MUSB OTG controller driver for Blackfin Processors
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#include "musb_core.h"
+#include "blackfin.h"
+
+/*
+ * Load an endpoint's FIFO
+ */
+void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
+{
+        void __iomem *fifo = hw_ep->fifo;
+        void __iomem *epio = hw_ep->regs;
+
+        prefetch((u8 *)src);
+
+        musb_writew(epio, MUSB_TXCOUNT, len);
+
+        DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
+                        hw_ep->epnum, fifo, len, src, epio);
+
+        dump_fifo_data(src, len);
+
+        if (unlikely((unsigned long)src & 0x01))
+                outsw_8((unsigned long)fifo, src,
+                        len & 0x01 ? (len >> 1) + 1 : len >> 1);
+        else
+                outsw((unsigned long)fifo, src,
+                        len & 0x01 ? (len >> 1) + 1 : len >> 1);
+}
+
+/*
+ * Unload an endpoint's FIFO
+ */
+void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
+{
+        void __iomem *fifo = hw_ep->fifo;
+        u8 epnum = hw_ep->epnum;
+        u16 dma_reg = 0;
+
+        DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+                        'R', hw_ep->epnum, fifo, len, dst);
+
+#ifdef CONFIG_BF52x
+        invalidate_dcache_range((unsigned int)dst,
+                (unsigned int)(dst + len));
+
+        /* Setup DMA address register */
+        dma_reg = (u16) ((u32) dst & 0xFFFF);
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
+        SSYNC();
+
+        dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
+        SSYNC();
+
+        /* Setup DMA count register */
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
+        SSYNC();
+
+        /* Enable the DMA */
+        dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
+        SSYNC();
+
+        /* Wait for compelete */
+        while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
+                cpu_relax();
+
+        /* acknowledge dma interrupt */
+        bfin_write_USB_DMA_INTERRUPT(1 << epnum);
+        SSYNC();
+
+        /* Reset DMA */
+        bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
+        SSYNC();
+#else
+        if (unlikely((unsigned long)dst & 0x01))
+                insw_8((unsigned long)fifo, dst,
+                        len & 0x01 ? (len >> 1) + 1 : len >> 1);
+        else
+                insw((unsigned long)fifo, dst,
+                        len & 0x01 ? (len >> 1) + 1 : len >> 1);
+#endif
+
+        dump_fifo_data(dst, len);
+}
+
+static irqreturn_t blackfin_interrupt(int irq, void *__hci)
+{
+        unsigned long   flags;
+        irqreturn_t     retval = IRQ_NONE;
+        struct musb     *musb = __hci;
+
+        spin_lock_irqsave(&musb->lock, flags);
+
+        musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+        musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
+        musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
+
+        if (musb->int_usb || musb->int_tx || musb->int_rx) {
+                musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+                musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+                musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+                retval = musb_interrupt(musb);
+        }
+
+        spin_unlock_irqrestore(&musb->lock, flags);
+
+        /* REVISIT we sometimes get spurious IRQs on g_ep0
+         * not clear why... fall in BF54x too.
+         */
+        if (retval != IRQ_HANDLED)
+                DBG(5, "spurious?\n");
+
+        return IRQ_HANDLED;
+}
+
+static void musb_conn_timer_handler(unsigned long _musb)
+{
+        struct musb *musb = (void *)_musb;
+        unsigned long flags;
+        u16 val;
+
+        spin_lock_irqsave(&musb->lock, flags);
+        switch (musb->xceiv.state) {
+        case OTG_STATE_A_IDLE:
+        case OTG_STATE_A_WAIT_BCON:
+                /* Start a new session */
+                val = musb_readw(musb->mregs, MUSB_DEVCTL);
+                val |= MUSB_DEVCTL_SESSION;
+                musb_writew(musb->mregs, MUSB_DEVCTL, val);
+
+                val = musb_readw(musb->mregs, MUSB_DEVCTL);
+                if (!(val & MUSB_DEVCTL_BDEVICE)) {
+                        gpio_set_value(musb->config->gpio_vrsel, 1);
+                        musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
+                } else {
+                        gpio_set_value(musb->config->gpio_vrsel, 0);
+
+                        /* Ignore VBUSERROR and SUSPEND IRQ */
+                        val = musb_readb(musb->mregs, MUSB_INTRUSBE);
+                        val &= ~MUSB_INTR_VBUSERROR;
+                        musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
+
+                        val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
+                        musb_writeb(musb->mregs, MUSB_INTRUSB, val);
+
+                        val = MUSB_POWER_HSENAB;
+                        musb_writeb(musb->mregs, MUSB_POWER, val);
+                }
+                mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
+                break;
+
+        default:
+                DBG(1, "%s state not handled\n", otg_state_string(musb));
+                break;
+        }
+        spin_unlock_irqrestore(&musb->lock, flags);
+
+        DBG(4, "state is %s\n", otg_state_string(musb));
+}
+
+void musb_platform_enable(struct musb *musb)
+{
+        if (is_host_enabled(musb)) {
+                mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
+                musb->a_wait_bcon = TIMER_DELAY;
+        }
+}
+
+void musb_platform_disable(struct musb *musb)
+{
+}
+
+static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
+{
+}
+
+static void bfin_set_vbus(struct musb *musb, int is_on)
+{
+        if (is_on)
+                gpio_set_value(musb->config->gpio_vrsel, 1);
+        else
+                gpio_set_value(musb->config->gpio_vrsel, 0);
+
+        DBG(1, "VBUS %s, devctl %02x "
+                /* otg %3x conf %08x prcm %08x */ "\n",
+                otg_state_string(musb),
+                musb_readb(musb->mregs, MUSB_DEVCTL));
+}
+
+static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
+{
+        return 0;
+}
+
+void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
+{
+        if (is_host_enabled(musb))
+                mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
+}
+
+int musb_platform_get_vbus_status(struct musb *musb)
+{
+        return 0;
+}
+
+void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+{
+}
+
+int __init musb_platform_init(struct musb *musb)
+{
+
+        /*
+         * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
+         * and OTG HOST modes, while rev 1.1 and greater require PE7 to
+         * be low for DEVICE mode and high for HOST mode. We set it high
+         * here because we are in host mode
+         */
+
+        if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
+                printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
+                        musb->config->gpio_vrsel);
+                return -ENODEV;
+        }
+        gpio_direction_output(musb->config->gpio_vrsel, 0);
+
+        if (ANOMALY_05000346) {
+                bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
+                SSYNC();
+        }
+
+        if (ANOMALY_05000347) {
+                bfin_write_USB_APHY_CNTRL(0x0);
+                SSYNC();
+        }
+
+        /* TODO
+         * Set SIC-IVG register
+         */
+
+        /* Configure PLL oscillator register */
+        bfin_write_USB_PLLOSC_CTRL(0x30a8);
+        SSYNC();
+
+        bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
+        SSYNC();
+
+        bfin_write_USB_EP_NI0_RXMAXP(64);
+        SSYNC();
+
+        bfin_write_USB_EP_NI0_TXMAXP(64);
+        SSYNC();
+
+        /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
+        bfin_write_USB_GLOBINTR(0x7);
+        SSYNC();
+
+        bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
+                                EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
+                                EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
+                                EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
+                                EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
+        SSYNC();
+
+        if (is_host_enabled(musb)) {
+                musb->board_set_vbus = bfin_set_vbus;
+                setup_timer(&musb_conn_timer,
+                        musb_conn_timer_handler, (unsigned long) musb);
+        }
+        if (is_peripheral_enabled(musb))
+                musb->xceiv.set_power = bfin_set_power;
+
+        musb->isr = blackfin_interrupt;
+
+        return 0;
+}
+
+int musb_platform_suspend(struct musb *musb)
+{
+        return 0;
+}
+
+int musb_platform_resume(struct musb *musb)
+{
+        return 0;
+}
+
+
+int musb_platform_exit(struct musb *musb)
+{
+
+        bfin_vbus_power(musb, 0 /*off*/, 1);
+        gpio_free(musb->config->gpio_vrsel);
+        musb_platform_suspend(musb);
+
+        return 0;
+}
diff --git a/drivers/usb/musb/blackfin.h b/drivers/usb/musb/blackfin.h
new file mode 100644
index 000000000000..a240c1e53d16
--- /dev/null
+++ b/drivers/usb/musb/blackfin.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2007 by Analog Devices, Inc.
+ *
+ * The Inventra Controller Driver for Linux is free software; you
+ * can redistribute it and/or modify it under the terms of the GNU
+ * General Public License version 2 as published by the Free Software
+ * Foundation.
+ */
+
+#ifndef __MUSB_BLACKFIN_H__
+#define __MUSB_BLACKFIN_H__
+
+/*
+ * Blackfin specific definitions
+ */
+
+#undef DUMP_FIFO_DATA
+#ifdef DUMP_FIFO_DATA
+static void dump_fifo_data(u8 *buf, u16 len)
+{
+        u8 *tmp = buf;
+        int i;
+
+        for (i = 0; i < len; i++) {
+                if (!(i % 16) && i)
+                        pr_debug("\n");
+                pr_debug("%02x ", *tmp++);
+        }
+        pr_debug("\n");
+}
+#else
+#define dump_fifo_data(buf, len)        do {} while (0)
+#endif
+
+#ifdef CONFIG_BF52x
+
+#define USB_DMA_BASE            USB_DMA_INTERRUPT
+#define USB_DMAx_CTRL           0x04
+#define USB_DMAx_ADDR_LOW       0x08
+#define USB_DMAx_ADDR_HIGH      0x0C
+#define USB_DMAx_COUNT_LOW      0x10
+#define USB_DMAx_COUNT_HIGH     0x14
+
+#define USB_DMA_REG(ep, reg)    (USB_DMA_BASE + 0x20 * ep + reg)
+#endif
+
+/* Almost 1 second */
+#define TIMER_DELAY     (1 * HZ)
+
+static struct timer_list musb_conn_timer;
+
+#endif  /* __MUSB_BLACKFIN_H__ */
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index dfb3bcbe00fc..0d566dc5ce06 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -32,9 +32,9 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/memory.h>
-#include <asm/arch/gpio.h>
+#include <mach/arch/hardware.h>
+#include <mach/arch/memory.h>
+#include <mach/arch/gpio.h>
 #include <asm/mach-types.h>
 
 #include "musb_core.h"
@@ -364,6 +364,18 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
         return IRQ_HANDLED;
 }
 
+int musb_platform_set_mode(struct musb *musb, u8 mode)
+{
+        /* EVM can't do this (right?) */
+        return -EIO;
+}
+
+int musb_platform_set_mode(struct musb *musb, u8 mode)
+{
+       /* EVM can't do this (right?) */
+       return -EIO;
+}
+
 int __init musb_platform_init(struct musb *musb)
 {
         void __iomem    *tibase = musb->ctrl_base;
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 5280dba9b1fb..6c7faacfb535 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -148,7 +148,8 @@ static inline struct musb *dev_to_musb(struct device *dev)
 
 /*-------------------------------------------------------------------------*/
 
-#ifndef CONFIG_USB_TUSB6010
+#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
+
 /*
  * Load an endpoint's FIFO
  */
@@ -1124,25 +1125,25 @@ fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
 #endif
         switch (cfg->style) {
         case FIFO_TX:
-                musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
-                musb_writew(mbase, MUSB_TXFIFOADD, c_off);
+                musb_write_txfifosz(mbase, c_size);
+                musb_write_txfifoadd(mbase, c_off);
                 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
                 hw_ep->max_packet_sz_tx = maxpacket;
                 break;
         case FIFO_RX:
-                musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
-                musb_writew(mbase, MUSB_RXFIFOADD, c_off);
+                musb_write_rxfifosz(mbase, c_size);
+                musb_write_rxfifoadd(mbase, c_off);
                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
                 hw_ep->max_packet_sz_rx = maxpacket;
                 break;
         case FIFO_RXTX:
-                musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
-                musb_writew(mbase, MUSB_TXFIFOADD, c_off);
+                musb_write_txfifosz(mbase, c_size);
+                musb_write_txfifoadd(mbase, c_off);
                 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
                 hw_ep->max_packet_sz_rx = maxpacket;
 
-                musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
-                musb_writew(mbase, MUSB_RXFIFOADD, c_off);
+                musb_write_rxfifosz(mbase, c_size);
+                musb_write_rxfifoadd(mbase, c_off);
                 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
                 hw_ep->max_packet_sz_tx = maxpacket;
 
@@ -1212,7 +1213,7 @@ static int __init ep_config_from_table(struct musb *musb)
                 if (epn >= musb->config->num_eps) {
                         pr_debug("%s: invalid ep %d\n",
                                         musb_driver_name, epn);
-                        continue;
+                        return -EINVAL;
                 }
                 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
                 if (offset < 0) {
@@ -1246,9 +1247,10 @@ static int __init ep_config_from_table(struct musb *musb)
  */
 static int __init ep_config_from_hw(struct musb *musb)
 {
-        u8 epnum = 0, reg;
+        u8 epnum = 0;
         struct musb_hw_ep *hw_ep;
         void *mbase = musb->mregs;
+        int ret = 0;
 
         DBG(2, "<== static silicon ep config\n");
 
@@ -1258,26 +1260,9 @@ static int __init ep_config_from_hw(struct musb *musb)
                 musb_ep_select(mbase, epnum);
                 hw_ep = musb->endpoints + epnum;
 
-                /* read from core using indexed model */
-                reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
-                if (!reg) {
-                        /* 0's returned when no more endpoints */
+                ret = musb_read_fifosize(musb, hw_ep, epnum);
+                if (ret < 0)
                         break;
-                }
-                musb->nr_endpoints++;
-                musb->epmask |= (1 << epnum);
-
-                hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
-
-                /* shared TX/RX FIFO? */
-                if ((reg & 0xf0) == 0xf0) {
-                        hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
-                        hw_ep->is_shared_fifo = true;
-                        continue;
-                } else {
-                        hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
-                        hw_ep->is_shared_fifo = false;
-                }
 
                 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
 
@@ -1326,7 +1311,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 
         /* log core options (read using indexed model) */
         musb_ep_select(mbase, 0);
-        reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
+        reg = musb_read_configdata(mbase);
 
         strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
         if (reg & MUSB_CONFIGDATA_DYNFIFO)
@@ -1391,7 +1376,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
         }
 
         /* log release info */
-        hwvers = musb_readw(mbase, MUSB_HWVERS);
+        hwvers = musb_read_hwvers(mbase);
         rev_major = (hwvers >> 10) & 0x1f;
         rev_minor = hwvers & 0x3ff;
         snprintf(aRevision, 32, "%d.%d%s", rev_major,
@@ -1400,8 +1385,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
                         musb_driver_name, type, aRevision, aDate);
 
         /* configure ep0 */
-        musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
-        musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
+        musb_configure_ep0(musb);
 
         /* discover endpoint configuration */
         musb->nr_endpoints = 1;
@@ -1445,7 +1429,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
 
                 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
-                hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
+                hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
                 hw_ep->rx_reinit = 1;
                 hw_ep->tx_reinit = 1;
 #endif
@@ -1671,17 +1655,20 @@ musb_mode_store(struct device *dev, struct device_attribute *attr,
 {
         struct musb     *musb = dev_to_musb(dev);
         unsigned long   flags;
+        int             status;
 
         spin_lock_irqsave(&musb->lock, flags);
-        if (!strncmp(buf, "host", 4))
-                musb_platform_set_mode(musb, MUSB_HOST);
-        if (!strncmp(buf, "peripheral", 10))
-                musb_platform_set_mode(musb, MUSB_PERIPHERAL);
-        if (!strncmp(buf, "otg", 3))
-                musb_platform_set_mode(musb, MUSB_OTG);
+        if (sysfs_streq(buf, "host"))
+                status = musb_platform_set_mode(musb, MUSB_HOST);
+        else if (sysfs_streq(buf, "peripheral"))
+                status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
+        else if (sysfs_streq(buf, "otg"))
+                status = musb_platform_set_mode(musb, MUSB_OTG);
+        else
+                status = -EINVAL;
         spin_unlock_irqrestore(&musb->lock, flags);
 
-        return n;
+        return (status == 0) ? n : status;
 }
 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
 
@@ -1781,7 +1768,7 @@ allocate_instance(struct device *dev,
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
         struct usb_hcd  *hcd;
 
-        hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
+        hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
         if (!hcd)
                 return NULL;
         /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
@@ -1810,7 +1797,6 @@ allocate_instance(struct device *dev,
         for (epnum = 0, ep = musb->endpoints;
                         epnum < musb->config->num_eps;
                         epnum++, ep++) {
-
                 ep->musb = musb;
                 ep->epnum = epnum;
         }
@@ -1838,7 +1824,7 @@ static void musb_free(struct musb *musb)
         musb_gadget_cleanup(musb);
 #endif
 
-        if (musb->nIrq >= 0) {
+        if (musb->nIrq >= 0 && musb->irq_wake) {
                 disable_irq_wake(musb->nIrq);
                 free_irq(musb->nIrq, musb);
         }
@@ -1984,15 +1970,19 @@ bad_config:
         INIT_WORK(&musb->irq_work, musb_irq_work);
 
         /* attach to the IRQ */
-        if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
+        if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
                 dev_err(dev, "request_irq %d failed!\n", nIrq);
                 status = -ENODEV;
                 goto fail2;
         }
         musb->nIrq = nIrq;
 /* FIXME this handles wakeup irqs wrong */
-        if (enable_irq_wake(nIrq) == 0)
+        if (enable_irq_wake(nIrq) == 0) {
+                musb->irq_wake = 1;
                 device_init_wakeup(dev, 1);
+        } else {
+                musb->irq_wake = 0;
+        }
 
         pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
                         musb_driver_name,
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 82227251931b..630946a2d9fc 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -191,7 +191,7 @@ enum musb_g_ep0_state {
  */
 
 #if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
-                || defined(CONFIG_ARCH_OMAP3430)
+                || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN)
 /* REVISIT indexed access seemed to
  * misbehave (on DaVinci) for at least peripheral IN ...
  */
@@ -359,6 +359,7 @@ struct musb {
         struct otg_transceiver  xceiv;
 
         int nIrq;
+        unsigned                irq_wake:1;
 
         struct musb_hw_ep        endpoints[MUSB_C_NUM_EPS];
 #define control_ep              endpoints
@@ -447,6 +448,70 @@ static inline struct musb *gadget_to_musb(struct usb_gadget *g)
 }
 #endif
 
+#ifdef CONFIG_BLACKFIN
+static inline int musb_read_fifosize(struct musb *musb,
+                struct musb_hw_ep *hw_ep, u8 epnum)
+{
+        musb->nr_endpoints++;
+        musb->epmask |= (1 << epnum);
+
+        if (epnum < 5) {
+                hw_ep->max_packet_sz_tx = 128;
+                hw_ep->max_packet_sz_rx = 128;
+        } else {
+                hw_ep->max_packet_sz_tx = 1024;
+                hw_ep->max_packet_sz_rx = 1024;
+        }
+        hw_ep->is_shared_fifo = false;
+
+        return 0;
+}
+
+static inline void musb_configure_ep0(struct musb *musb)
+{
+        musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
+        musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
+        musb->endpoints[0].is_shared_fifo = true;
+}
+
+#else
+
+static inline int musb_read_fifosize(struct musb *musb,
+                struct musb_hw_ep *hw_ep, u8 epnum)
+{
+        u8 reg = 0;
+
+        /* read from core using indexed model */
+        reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
+        /* 0's returned when no more endpoints */
+        if (!reg)
+                return -ENODEV;
+
+        musb->nr_endpoints++;
+        musb->epmask |= (1 << epnum);
+
+        hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
+
+        /* shared TX/RX FIFO? */
+        if ((reg & 0xf0) == 0xf0) {
+                hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
+                hw_ep->is_shared_fifo = true;
+                return 0;
+        } else {
+                hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
+                hw_ep->is_shared_fifo = false;
+        }
+
+        return 0;
+}
+
+static inline void musb_configure_ep0(struct musb *musb)
+{
+        musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
+        musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
+}
+#endif /* CONFIG_BLACKFIN */
+
 
 /***************************** Glue it together *****************************/
 
@@ -467,16 +532,16 @@ extern void musb_platform_disable(struct musb *musb);
 
 extern void musb_hnp_stop(struct musb *musb);
 
-extern void musb_platform_set_mode(struct musb *musb, u8 musb_mode);
+extern int musb_platform_set_mode(struct musb *musb, u8 musb_mode);
 
-#if defined(CONFIG_USB_TUSB6010) || \
+#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN) || \
         defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
 extern void musb_platform_try_idle(struct musb *musb, unsigned long timeout);
 #else
 #define musb_platform_try_idle(x, y)            do {} while (0)
 #endif
 
-#ifdef CONFIG_USB_TUSB6010
+#if defined(CONFIG_USB_TUSB6010) || defined(CONFIG_BLACKFIN)
 extern int musb_platform_get_vbus_status(struct musb *musb);
 #else
 #define musb_platform_get_vbus_status(x)        0
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index d6a802c224fa..6197daeab8f9 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -1633,7 +1633,7 @@ int __init musb_gadget_setup(struct musb *musb)
         musb->g.speed = USB_SPEED_UNKNOWN;
 
         /* this "gadget" abstracts/virtualizes the controller */
-        strcpy(musb->g.dev.bus_id, "gadget");
+        dev_set_name(&musb->g.dev, "gadget");
         musb->g.dev.parent = musb->controller;
         musb->g.dev.dma_mask = musb->controller->dma_mask;
         musb->g.dev.release = musb_gadget_release;
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index cc64462d4c4e..99fa61234876 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -112,18 +112,21 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
 {
         void __iomem    *epio = ep->regs;
         u16             csr;
+        u16             lastcsr = 0;
         int             retries = 1000;
 
         csr = musb_readw(epio, MUSB_TXCSR);
         while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
-                DBG(5, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+                if (csr != lastcsr)
+                        DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+                lastcsr = csr;
                 csr |= MUSB_TXCSR_FLUSHFIFO;
                 musb_writew(epio, MUSB_TXCSR, csr);
                 csr = musb_readw(epio, MUSB_TXCSR);
-                if (retries-- < 1) {
-                        ERR("Could not flush host TX fifo: csr: %04x\n", csr);
+                if (WARN(retries-- < 1,
+                                "Could not flush host TX%d fifo: csr: %04x\n",
+                                ep->epnum, csr))
                         return;
-                }
                 mdelay(1);
         }
 }
@@ -268,7 +271,7 @@ __musb_giveback(struct musb *musb, struct urb *urb, int status)
 __releases(musb->lock)
 __acquires(musb->lock)
 {
-        DBG(({ int level; switch (urb->status) {
+        DBG(({ int level; switch (status) {
                                 case 0:
                                         level = 4;
                                         break;
@@ -283,8 +286,8 @@ __acquires(musb->lock)
                                         level = 2;
                                         break;
                                 }; level; }),
-                        "complete %p (%d), dev%d ep%d%s, %d/%d\n",
-                        urb, urb->status,
+                        "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
+                        urb, urb->complete, status,
                         usb_pipedevice(urb->pipe),
                         usb_pipeendpoint(urb->pipe),
                         usb_pipein(urb->pipe) ? "in" : "out",
@@ -593,12 +596,10 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
 
         /* target addr and (for multipoint) hub addr/port */
         if (musb->is_multipoint) {
-                musb_writeb(ep->target_regs, MUSB_RXFUNCADDR,
-                        qh->addr_reg);
-                musb_writeb(ep->target_regs, MUSB_RXHUBADDR,
-                        qh->h_addr_reg);
-                musb_writeb(ep->target_regs, MUSB_RXHUBPORT,
-                        qh->h_port_reg);
+                musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
+                musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
+                musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
+
         } else
                 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
 
@@ -712,15 +713,9 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
 
                 /* target addr and (for multipoint) hub addr/port */
                 if (musb->is_multipoint) {
-                        musb_writeb(mbase,
-                                MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
-                                qh->addr_reg);
-                        musb_writeb(mbase,
-                                MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
-                                qh->h_addr_reg);
-                        musb_writeb(mbase,
-                                MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
-                                qh->h_port_reg);
+                        musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
+                        musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
+                        musb_write_txhubport(mbase, epnum, qh->h_port_reg);
 /* FIXME if !epnum, do the same for RX ... */
                 } else
                         musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
@@ -988,8 +983,10 @@ static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
                 if (fifo_count) {
                         fifo_dest = (u8 *) (urb->transfer_buffer
                                         + urb->actual_length);
-                        DBG(3, "Sending %d bytes to %p\n",
-                                        fifo_count, fifo_dest);
+                        DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
+                                        fifo_count,
+                                        (fifo_count == 1) ? "" : "s",
+                                        fifo_dest);
                         musb_write_fifo(hw_ep, fifo_count, fifo_dest);
 
                         urb->actual_length += fifo_count;
diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h
index 223f0a514094..b06e9ef00cfc 100644
--- a/drivers/usb/musb/musb_io.h
+++ b/drivers/usb/musb/musb_io.h
@@ -39,7 +39,7 @@
 
 #if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
         && !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
-        && !defined(CONFIG_PPC64)
+        && !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN)
 static inline void readsl(const void __iomem *addr, void *buf, int len)
         { insl((unsigned long)addr, buf, len); }
 static inline void readsw(const void __iomem *addr, void *buf, int len)
@@ -56,6 +56,8 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
 
 #endif
 
+#ifndef CONFIG_BLACKFIN
+
 /* NOTE:  these offsets are all in bytes */
 
 static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
@@ -114,4 +116,26 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
 
 #endif  /* CONFIG_USB_TUSB6010 */
 
+#else
+
+static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
+        { return (u8) (bfin_read16(addr + offset)); }
+
+static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
+        { return bfin_read16(addr + offset); }
+
+static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
+        { return (u32) (bfin_read16(addr + offset)); }
+
+static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
+        { bfin_write16(addr + offset, (u16) data); }
+
+static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
+        { bfin_write16(addr + offset, data); }
+
+static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
+        { bfin_write16(addr + offset, (u16) data); }
+
+#endif /* CONFIG_BLACKFIN */
+
 #endif
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index 9c228661aa5a..de3b2f18db44 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -38,97 +38,6 @@
 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
 
 /*
- * Common USB registers
- */
-
-#define MUSB_FADDR              0x00    /* 8-bit */
-#define MUSB_POWER              0x01    /* 8-bit */
-
-#define MUSB_INTRTX             0x02    /* 16-bit */
-#define MUSB_INTRRX             0x04
-#define MUSB_INTRTXE            0x06
-#define MUSB_INTRRXE            0x08
-#define MUSB_INTRUSB            0x0A    /* 8 bit */
-#define MUSB_INTRUSBE           0x0B    /* 8 bit */
-#define MUSB_FRAME              0x0C
-#define MUSB_INDEX              0x0E    /* 8 bit */
-#define MUSB_TESTMODE           0x0F    /* 8 bit */
-
-/* Get offset for a given FIFO from musb->mregs */
-#ifdef  CONFIG_USB_TUSB6010
-#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
-#else
-#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
-#endif
-
-/*
- * Additional Control Registers
- */
-
-#define MUSB_DEVCTL             0x60    /* 8 bit */
-
-/* These are always controlled through the INDEX register */
-#define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
-#define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
-#define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
-#define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */
-
-/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
-#define MUSB_HWVERS             0x6C    /* 8 bit */
-
-#define MUSB_EPINFO             0x78    /* 8 bit */
-#define MUSB_RAMINFO            0x79    /* 8 bit */
-#define MUSB_LINKINFO           0x7a    /* 8 bit */
-#define MUSB_VPLEN              0x7b    /* 8 bit */
-#define MUSB_HS_EOF1            0x7c    /* 8 bit */
-#define MUSB_FS_EOF1            0x7d    /* 8 bit */
-#define MUSB_LS_EOF1            0x7e    /* 8 bit */
-
-/* Offsets to endpoint registers */
-#define MUSB_TXMAXP             0x00
-#define MUSB_TXCSR              0x02
-#define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
-#define MUSB_RXMAXP             0x04
-#define MUSB_RXCSR              0x06
-#define MUSB_RXCOUNT            0x08
-#define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
-#define MUSB_TXTYPE             0x0A
-#define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
-#define MUSB_TXINTERVAL         0x0B
-#define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
-#define MUSB_RXTYPE             0x0C
-#define MUSB_RXINTERVAL         0x0D
-#define MUSB_FIFOSIZE           0x0F
-#define MUSB_CONFIGDATA         MUSB_FIFOSIZE   /* Re-used for EP0 */
-
-/* Offsets to endpoint registers in indexed model (using INDEX register) */
-#define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
-        (0x10 + (_offset))
-
-/* Offsets to endpoint registers in flat models */
-#define MUSB_FLAT_OFFSET(_epnum, _offset)       \
-        (0x100 + (0x10*(_epnum)) + (_offset))
-
-#ifdef CONFIG_USB_TUSB6010
-/* TUSB6010 EP0 configuration register is special */
-#define MUSB_TUSB_OFFSET(_epnum, _offset)       \
-        (0x10 + _offset)
-#include "tusb6010.h"           /* Needed "only" for TUSB_EP0_CONF */
-#endif
-
-/* "bus control"/target registers, for host side multipoint (external hubs) */
-#define MUSB_TXFUNCADDR         0x00
-#define MUSB_TXHUBADDR          0x02
-#define MUSB_TXHUBPORT          0x03
-
-#define MUSB_RXFUNCADDR         0x04
-#define MUSB_RXHUBADDR          0x06
-#define MUSB_RXHUBPORT          0x07
-
-#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
-        (0x80 + (8*(_epnum)) + (_offset))
-
-/*
  * MUSB Register bits
  */
 
@@ -228,7 +137,6 @@
 
 /* TXCSR in Peripheral and Host mode */
 #define MUSB_TXCSR_AUTOSET              0x8000
-#define MUSB_TXCSR_MODE                 0x2000
 #define MUSB_TXCSR_DMAENAB              0x1000
 #define MUSB_TXCSR_FRCDATATOG           0x0800
 #define MUSB_TXCSR_DMAMODE              0x0400
@@ -297,4 +205,309 @@
 /* HUBADDR */
 #define MUSB_HUBADDR_MULTI_TT           0x80
 
+
+#ifndef CONFIG_BLACKFIN
+
+/*
+ * Common USB registers
+ */
+
+#define MUSB_FADDR              0x00    /* 8-bit */
+#define MUSB_POWER              0x01    /* 8-bit */
+
+#define MUSB_INTRTX             0x02    /* 16-bit */
+#define MUSB_INTRRX             0x04
+#define MUSB_INTRTXE            0x06
+#define MUSB_INTRRXE            0x08
+#define MUSB_INTRUSB            0x0A    /* 8 bit */
+#define MUSB_INTRUSBE           0x0B    /* 8 bit */
+#define MUSB_FRAME              0x0C
+#define MUSB_INDEX              0x0E    /* 8 bit */
+#define MUSB_TESTMODE           0x0F    /* 8 bit */
+
+/* Get offset for a given FIFO from musb->mregs */
+#ifdef  CONFIG_USB_TUSB6010
+#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
+#else
+#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
+#endif
+
+/*
+ * Additional Control Registers
+ */
+
+#define MUSB_DEVCTL             0x60    /* 8 bit */
+
+/* These are always controlled through the INDEX register */
+#define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
+#define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
+#define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
+#define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */
+
+/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
+#define MUSB_HWVERS             0x6C    /* 8 bit */
+
+#define MUSB_EPINFO             0x78    /* 8 bit */
+#define MUSB_RAMINFO            0x79    /* 8 bit */
+#define MUSB_LINKINFO           0x7a    /* 8 bit */
+#define MUSB_VPLEN              0x7b    /* 8 bit */
+#define MUSB_HS_EOF1            0x7c    /* 8 bit */
+#define MUSB_FS_EOF1            0x7d    /* 8 bit */
+#define MUSB_LS_EOF1            0x7e    /* 8 bit */
+
+/* Offsets to endpoint registers */
+#define MUSB_TXMAXP             0x00
+#define MUSB_TXCSR              0x02
+#define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
+#define MUSB_RXMAXP             0x04
+#define MUSB_RXCSR              0x06
+#define MUSB_RXCOUNT            0x08
+#define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
+#define MUSB_TXTYPE             0x0A
+#define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
+#define MUSB_TXINTERVAL         0x0B
+#define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
+#define MUSB_RXTYPE             0x0C
+#define MUSB_RXINTERVAL         0x0D
+#define MUSB_FIFOSIZE           0x0F
+#define MUSB_CONFIGDATA         MUSB_FIFOSIZE   /* Re-used for EP0 */
+
+/* Offsets to endpoint registers in indexed model (using INDEX register) */
+#define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
+        (0x10 + (_offset))
+
+/* Offsets to endpoint registers in flat models */
+#define MUSB_FLAT_OFFSET(_epnum, _offset)       \
+        (0x100 + (0x10*(_epnum)) + (_offset))
+
+#ifdef CONFIG_USB_TUSB6010
+/* TUSB6010 EP0 configuration register is special */
+#define MUSB_TUSB_OFFSET(_epnum, _offset)       \
+        (0x10 + _offset)
+#include "tusb6010.h"           /* Needed "only" for TUSB_EP0_CONF */
+#endif
+
+#define MUSB_TXCSR_MODE                 0x2000
+
+/* "bus control"/target registers, for host side multipoint (external hubs) */
+#define MUSB_TXFUNCADDR         0x00
+#define MUSB_TXHUBADDR          0x02
+#define MUSB_TXHUBPORT          0x03
+
+#define MUSB_RXFUNCADDR         0x04
+#define MUSB_RXHUBADDR          0x06
+#define MUSB_RXHUBPORT          0x07
+
+#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
+        (0x80 + (8*(_epnum)) + (_offset))
+
+static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
+{
+        musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
+}
+
+static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
+{
+        musb_writew(mbase, MUSB_TXFIFOADD, c_off);
+}
+
+static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
+{
+        musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
+}
+
+static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
+{
+        musb_writew(mbase, MUSB_RXFIFOADD, c_off);
+}
+
+static inline u8 musb_read_configdata(void __iomem *mbase)
+{
+        return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
+}
+
+static inline u16 musb_read_hwvers(void __iomem *mbase)
+{
+        return musb_readw(mbase, MUSB_HWVERS);
+}
+
+static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
+{
+        return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
+}
+
+static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
+                u8 qh_addr_reg)
+{
+        musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
+}
+
+static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
+                u8 qh_h_addr_reg)
+{
+        musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
+}
+
+static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
+                u8 qh_h_port_reg)
+{
+        musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
+}
+
+static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
+                u8 qh_addr_reg)
+{
+        musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
+                        qh_addr_reg);
+}
+
+static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
+                u8 qh_addr_reg)
+{
+        musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
+                        qh_addr_reg);
+}
+
+static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
+                u8 qh_h_port_reg)
+{
+        musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
+                        qh_h_port_reg);
+}
+
+#else /* CONFIG_BLACKFIN */
+
+#define USB_BASE                USB_FADDR
+#define USB_OFFSET(reg)         (reg - USB_BASE)
+
+/*
+ * Common USB registers
+ */
+#define MUSB_FADDR              USB_OFFSET(USB_FADDR)   /* 8-bit */
+#define MUSB_POWER              USB_OFFSET(USB_POWER)   /* 8-bit */
+#define MUSB_INTRTX             USB_OFFSET(USB_INTRTX)  /* 16-bit */
+#define MUSB_INTRRX             USB_OFFSET(USB_INTRRX)
+#define MUSB_INTRTXE            USB_OFFSET(USB_INTRTXE)
+#define MUSB_INTRRXE            USB_OFFSET(USB_INTRRXE)
+#define MUSB_INTRUSB            USB_OFFSET(USB_INTRUSB) /* 8 bit */
+#define MUSB_INTRUSBE           USB_OFFSET(USB_INTRUSBE)/* 8 bit */
+#define MUSB_FRAME              USB_OFFSET(USB_FRAME)
+#define MUSB_INDEX              USB_OFFSET(USB_INDEX)   /* 8 bit */
+#define MUSB_TESTMODE           USB_OFFSET(USB_TESTMODE)/* 8 bit */
+
+/* Get offset for a given FIFO from musb->mregs */
+#define MUSB_FIFO_OFFSET(epnum) \
+        (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
+
+/*
+ * Additional Control Registers
+ */
+
+#define MUSB_DEVCTL             USB_OFFSET(USB_OTG_DEV_CTL)     /* 8 bit */
+
+#define MUSB_LINKINFO           USB_OFFSET(USB_LINKINFO)/* 8 bit */
+#define MUSB_VPLEN              USB_OFFSET(USB_VPLEN)   /* 8 bit */
+#define MUSB_HS_EOF1            USB_OFFSET(USB_HS_EOF1) /* 8 bit */
+#define MUSB_FS_EOF1            USB_OFFSET(USB_FS_EOF1) /* 8 bit */
+#define MUSB_LS_EOF1            USB_OFFSET(USB_LS_EOF1) /* 8 bit */
+
+/* Offsets to endpoint registers */
+#define MUSB_TXMAXP             0x00
+#define MUSB_TXCSR              0x04
+#define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
+#define MUSB_RXMAXP             0x08
+#define MUSB_RXCSR              0x0C
+#define MUSB_RXCOUNT            0x10
+#define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
+#define MUSB_TXTYPE             0x14
+#define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
+#define MUSB_TXINTERVAL         0x18
+#define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
+#define MUSB_RXTYPE             0x1C
+#define MUSB_RXINTERVAL         0x20
+#define MUSB_TXCOUNT            0x28
+
+/* Offsets to endpoint registers in indexed model (using INDEX register) */
+#define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
+        (0x40 + (_offset))
+
+/* Offsets to endpoint registers in flat models */
+#define MUSB_FLAT_OFFSET(_epnum, _offset)       \
+        (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
+
+/* Not implemented - HW has seperate Tx/Rx FIFO */
+#define MUSB_TXCSR_MODE                 0x0000
+
+/*
+ * Dummy stub for clk framework, it will be removed
+ * until Blackfin supports clk framework
+ */
+#define clk_get(dev, id)        NULL
+#define clk_put(clock)          do {} while (0)
+#define clk_enable(clock)       do {} while (0)
+#define clk_disable(clock)      do {} while (0)
+
+static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
+{
+}
+
+static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
+{
+}
+
+static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
+{
+}
+
+static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
+{
+}
+
+static inline u8 musb_read_configdata(void __iomem *mbase)
+{
+        return 0;
+}
+
+static inline u16 musb_read_hwvers(void __iomem *mbase)
+{
+        return 0;
+}
+
+static inline u16 musb_read_target_reg_base(u8 i, void __iomem *mbase)
+{
+        return 0;
+}
+
+static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
+                u8 qh_addr_req)
+{
+}
+
+static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
+                u8 qh_h_addr_reg)
+{
+}
+
+static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
+                u8 qh_h_port_reg)
+{
+}
+
+static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
+                u8 qh_addr_reg)
+{
+}
+
+static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
+                u8 qh_addr_reg)
+{
+}
+
+static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
+                u8 qh_h_port_reg)
+{
+}
+
+#endif /* CONFIG_BLACKFIN */
+
 #endif  /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index 8c734ef2c1ed..8662e9e159c3 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -34,58 +34,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include "musb_core.h"
-
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
-#include "omap2430.h"
-#endif
-
-#define MUSB_HSDMA_BASE         0x200
-#define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
-#define MUSB_HSDMA_CONTROL              0x4
-#define MUSB_HSDMA_ADDRESS              0x8
-#define MUSB_HSDMA_COUNT                0xc
-
-#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
-                (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
-
-/* control register (16-bit): */
-#define MUSB_HSDMA_ENABLE_SHIFT         0
-#define MUSB_HSDMA_TRANSMIT_SHIFT               1
-#define MUSB_HSDMA_MODE1_SHIFT          2
-#define MUSB_HSDMA_IRQENABLE_SHIFT              3
-#define MUSB_HSDMA_ENDPOINT_SHIFT               4
-#define MUSB_HSDMA_BUSERROR_SHIFT               8
-#define MUSB_HSDMA_BURSTMODE_SHIFT              9
-#define MUSB_HSDMA_BURSTMODE            (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
-#define MUSB_HSDMA_BURSTMODE_UNSPEC     0
-#define MUSB_HSDMA_BURSTMODE_INCR4      1
-#define MUSB_HSDMA_BURSTMODE_INCR8      2
-#define MUSB_HSDMA_BURSTMODE_INCR16     3
-
-#define MUSB_HSDMA_CHANNELS             8
-
-struct musb_dma_controller;
-
-struct musb_dma_channel {
-        struct dma_channel              channel;
-        struct musb_dma_controller      *controller;
-        u32                             start_addr;
-        u32                             len;
-        u16                             max_packet_sz;
-        u8                              idx;
-        u8                              epnum;
-        u8                              transmit;
-};
-
-struct musb_dma_controller {
-        struct dma_controller           controller;
-        struct musb_dma_channel         channel[MUSB_HSDMA_CHANNELS];
-        void                            *private_data;
-        void __iomem                    *base;
-        u8                              channel_count;
-        u8                              used_channels;
-        u8                              irq;
-};
+#include "musbhsdma.h"
 
 static int dma_controller_start(struct dma_controller *c)
 {
@@ -203,12 +152,8 @@ static void configure_channel(struct dma_channel *channel,
                                 : 0);
 
         /* address/count */
-        musb_writel(mbase,
-                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
-                dma_addr);
-        musb_writel(mbase,
-                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
-                len);
+        musb_write_hsdma_addr(mbase, bchannel, dma_addr);
+        musb_write_hsdma_count(mbase, bchannel, len);
 
         /* control (this should start things) */
         musb_writew(mbase,
@@ -279,13 +224,8 @@ static int dma_channel_abort(struct dma_channel *channel)
                 musb_writew(mbase,
                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
                         0);
-                musb_writel(mbase,
-                        MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
-                        0);
-                musb_writel(mbase,
-                        MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
-                        0);
-
+                musb_write_hsdma_addr(mbase, bchannel, 0);
+                musb_write_hsdma_count(mbase, bchannel, 0);
                 channel->status = MUSB_DMA_STATUS_FREE;
         }
 
@@ -333,10 +273,8 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
                         } else {
                                 u8 devctl;
 
-                                addr = musb_readl(mbase,
-                                                MUSB_HSDMA_CHANNEL_OFFSET(
-                                                        bchannel,
-                                                        MUSB_HSDMA_ADDRESS));
+                                addr = musb_read_hsdma_addr(mbase,
+                                                bchannel);
                                 channel->actual_len = addr
                                         - musb_channel->start_addr;
 
@@ -375,6 +313,12 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
                         }
                 }
         }
+
+#ifdef CONFIG_BLACKFIN
+        /* Clear DMA interrup flags */
+        musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
+#endif
+
         retval = IRQ_HANDLED;
 done:
         spin_unlock_irqrestore(&musb->lock, flags);
@@ -424,7 +368,7 @@ dma_controller_create(struct musb *musb, void __iomem *base)
         controller->controller.channel_abort = dma_channel_abort;
 
         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
-                        musb->controller->bus_id, &controller->controller)) {
+                        dev_name(musb->controller), &controller->controller)) {
                 dev_err(dev, "request_irq %d failed!\n", irq);
                 dma_controller_destroy(&controller->controller);
 
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
new file mode 100644
index 000000000000..1299d92dc83f
--- /dev/null
+++ b/drivers/usb/musb/musbhsdma.h
@@ -0,0 +1,149 @@
+/*
+ * MUSB OTG driver - support for Mentor's DMA controller
+ *
+ * Copyright 2005 Mentor Graphics Corporation
+ * Copyright (C) 2005-2007 by Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#include "omap2430.h"
+#endif
+
+#ifndef CONFIG_BLACKFIN
+
+#define MUSB_HSDMA_BASE         0x200
+#define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
+#define MUSB_HSDMA_CONTROL              0x4
+#define MUSB_HSDMA_ADDRESS              0x8
+#define MUSB_HSDMA_COUNT                0xc
+
+#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
+                (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
+
+#define musb_read_hsdma_addr(mbase, bchannel)   \
+        musb_readl(mbase,       \
+                   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
+
+#define musb_write_hsdma_addr(mbase, bchannel, addr) \
+        musb_writel(mbase, \
+                    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
+                    addr)
+
+#define musb_write_hsdma_count(mbase, bchannel, len) \
+        musb_writel(mbase, \
+                    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
+                    len)
+#else
+
+#define MUSB_HSDMA_BASE         0x400
+#define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
+#define MUSB_HSDMA_CONTROL              0x04
+#define MUSB_HSDMA_ADDR_LOW             0x08
+#define MUSB_HSDMA_ADDR_HIGH            0x0C
+#define MUSB_HSDMA_COUNT_LOW            0x10
+#define MUSB_HSDMA_COUNT_HIGH           0x14
+
+#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
+                (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
+
+static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
+{
+        u32 addr = musb_readw(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
+
+        addr = addr << 16;
+
+        addr |= musb_readw(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
+
+        return addr;
+}
+
+static inline void musb_write_hsdma_addr(void __iomem *mbase,
+                                u8 bchannel, dma_addr_t dma_addr)
+{
+        musb_writew(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
+                ((u16)((u32) dma_addr & 0xFFFF)));
+        musb_writew(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
+                ((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
+}
+
+static inline void musb_write_hsdma_count(void __iomem *mbase,
+                                u8 bchannel, u32 len)
+{
+        musb_writew(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),
+                ((u16)((u32) len & 0xFFFF)));
+        musb_writew(mbase,
+                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
+                ((u16)(((u32) len >> 16) & 0xFFFF)));
+}
+
+#endif /* CONFIG_BLACKFIN */
+
+/* control register (16-bit): */
+#define MUSB_HSDMA_ENABLE_SHIFT         0
+#define MUSB_HSDMA_TRANSMIT_SHIFT       1
+#define MUSB_HSDMA_MODE1_SHIFT          2
+#define MUSB_HSDMA_IRQENABLE_SHIFT      3
+#define MUSB_HSDMA_ENDPOINT_SHIFT       4
+#define MUSB_HSDMA_BUSERROR_SHIFT       8
+#define MUSB_HSDMA_BURSTMODE_SHIFT      9
+#define MUSB_HSDMA_BURSTMODE            (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
+#define MUSB_HSDMA_BURSTMODE_UNSPEC     0
+#define MUSB_HSDMA_BURSTMODE_INCR4      1
+#define MUSB_HSDMA_BURSTMODE_INCR8      2
+#define MUSB_HSDMA_BURSTMODE_INCR16     3
+
+#define MUSB_HSDMA_CHANNELS             8
+
+struct musb_dma_controller;
+
+struct musb_dma_channel {
+        struct dma_channel              channel;
+        struct musb_dma_controller      *controller;
+        u32                             start_addr;
+        u32                             len;
+        u16                             max_packet_sz;
+        u8                              idx;
+        u8                              epnum;
+        u8                              transmit;
+};
+
+struct musb_dma_controller {
+        struct dma_controller           controller;
+        struct musb_dma_channel         channel[MUSB_HSDMA_CHANNELS];
+        void                            *private_data;
+        void __iomem                    *base;
+        u8                              channel_count;
+        u8                              used_channels;
+        u8                              irq;
+};
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index ce6c162920f7..901dffdf23b1 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -58,10 +58,10 @@ static void musb_do_idle(unsigned long _musb)
 #endif
         u8      devctl;
 
-        devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
-
         spin_lock_irqsave(&musb->lock, flags);
 
+        devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+
         switch (musb->xceiv.state) {
         case OTG_STATE_A_WAIT_BCON:
                 devctl &= ~MUSB_DEVCTL_SESSION;
@@ -196,7 +196,7 @@ static int omap_set_power(struct otg_transceiver *x, unsigned mA)
 
 static int musb_platform_resume(struct musb *musb);
 
-void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 {
         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 
@@ -204,15 +204,24 @@ void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 
         switch (musb_mode) {
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
         case MUSB_HOST:
                 otg_set_host(&musb->xceiv, musb->xceiv.host);
                 break;
+#endif
+#ifdef CONFIG_USB_GADGET_MUSB_HDRC
         case MUSB_PERIPHERAL:
                 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
                 break;
+#endif
+#ifdef CONFIG_USB_MUSB_OTG
         case MUSB_OTG:
                 break;
+#endif
+        default:
+                return -EINVAL;
         }
+        return 0;
 }
 
 int __init musb_platform_init(struct musb *musb)
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index ee8fca92a4ac..9e20fd070d71 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -598,7 +598,7 @@ static void tusb_source_power(struct musb *musb, int is_on)
  * and peripheral modes in non-OTG configurations by reconfiguring hardware
  * and then setting musb->board_mode. For now, only support OTG mode.
  */
-void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
+int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 {
         void __iomem    *tbase = musb->ctrl_base;
         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
@@ -641,7 +641,8 @@ void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 #endif
 
         default:
-                DBG(2, "Trying to set unknown mode %i\n", musb_mode);
+                DBG(2, "Trying to set mode %i\n", musb_mode);
+                return -EINVAL;
         }
 
         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
@@ -655,6 +656,8 @@ void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
                         INFO("Cannot be peripheral with mini-A cable "
                         "otg_stat: %08x\n", otg_stat);
+
+        return 0;
 }
 
 static inline unsigned long
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
new file mode 100644
index 000000000000..8e8dbdb9b39b
--- /dev/null
+++ b/drivers/usb/otg/Kconfig
@@ -0,0 +1,54 @@
+#
+# USB OTG infrastructure may be needed for peripheral-only, host-only,
+# or OTG-capable configurations when OTG transceivers or controllers
+# are used.
+#
+
+comment "OTG and related infrastructure"
+
+if USB || USB_GADGET
+
+config USB_OTG_UTILS
+        bool
+        help
+          Select this to make sure the build includes objects from
+          the OTG infrastructure directory.
+
+#
+# USB Transceiver Drivers
+#
+config USB_GPIO_VBUS
+        tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
+        depends on GENERIC_GPIO
+        select USB_OTG_UTILS
+        help
+          Provides simple GPIO VBUS sensing for controllers with an
+          internal transceiver via the otg_transceiver interface, and
+          optionally control of a D+ pullup GPIO as well as a VBUS
+          current limit regulator.
+
+config ISP1301_OMAP
+        tristate "Philips ISP1301 with OMAP OTG"
+        depends on I2C && ARCH_OMAP_OTG
+        select USB_OTG_UTILS
+        help
+          If you say yes here you get support for the Philips ISP1301
+          USB-On-The-Go transceiver working with the OMAP OTG controller.
+          The ISP1301 is a full speed USB  transceiver which is used in
+          products including H2, H3, and H4 development boards for Texas
+          Instruments OMAP processors.
+
+          This driver can also be built as a module.  If so, the module
+          will be called isp1301_omap.
+
+config TWL4030_USB
+        tristate "TWL4030 USB Transceiver Driver"
+        depends on TWL4030_CORE
+        select USB_OTG_UTILS
+        help
+          Enable this to support the USB OTG transceiver on TWL4030
+          family chips (including the TWL5030 and TPS659x0 devices).
+          This transceiver supports high and full speed devices plus,
+          in host mode, low speed.
+
+endif # USB || OTG
diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
new file mode 100644
index 000000000000..d73c7cf5e2f7
--- /dev/null
+++ b/drivers/usb/otg/Makefile
@@ -0,0 +1,15 @@
+#
+# OTG infrastructure and transceiver drivers
+#
+
+# infrastructure
+obj-$(CONFIG_USB_OTG_UTILS)     += otg.o
+
+# transceiver drivers
+obj-$(CONFIG_USB_GPIO_VBUS)     += gpio_vbus.o
+obj-$(CONFIG_ISP1301_OMAP)      += isp1301_omap.o
+obj-$(CONFIG_TWL4030_USB)       += twl4030-usb.o
+
+ccflags-$(CONFIG_USB_DEBUG)     += -DDEBUG
+ccflags-$(CONFIG_USB_GADGET_DEBUG) += -DDEBUG
+
diff --git a/drivers/usb/otg/gpio_vbus.c b/drivers/usb/otg/gpio_vbus.c
new file mode 100644
index 000000000000..63a6036f04be
--- /dev/null
+++ b/drivers/usb/otg/gpio_vbus.c
@@ -0,0 +1,335 @@
+/*
+ * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
+ *
+ * Copyright (c) 2008 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/usb.h>
+
+#include <linux/regulator/consumer.h>
+
+#include <linux/usb/gadget.h>
+#include <linux/usb/gpio_vbus.h>
+#include <linux/usb/otg.h>
+
+
+/*
+ * A simple GPIO VBUS sensing driver for B peripheral only devices
+ * with internal transceivers. It can control a D+ pullup GPIO and
+ * a regulator to limit the current drawn from VBUS.
+ *
+ * Needs to be loaded before the UDC driver that will use it.
+ */
+struct gpio_vbus_data {
+        struct otg_transceiver otg;
+        struct device          *dev;
+        struct regulator       *vbus_draw;
+        int                     vbus_draw_enabled;
+        unsigned                mA;
+};
+
+
+/*
+ * This driver relies on "both edges" triggering.  VBUS has 100 msec to
+ * stabilize, so the peripheral controller driver may need to cope with
+ * some bouncing due to current surges (e.g. charging local capacitance)
+ * and contact chatter.
+ *
+ * REVISIT in desperate straits, toggling between rising and falling
+ * edges might be workable.
+ */
+#define VBUS_IRQ_FLAGS \
+        ( IRQF_SAMPLE_RANDOM | IRQF_SHARED \
+        | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING )
+
+
+/* interface to regulator framework */
+static void set_vbus_draw(struct gpio_vbus_data *gpio_vbus, unsigned mA)
+{
+        struct regulator *vbus_draw = gpio_vbus->vbus_draw;
+        int enabled;
+
+        if (!vbus_draw)
+                return;
+
+        enabled = gpio_vbus->vbus_draw_enabled;
+        if (mA) {
+                regulator_set_current_limit(vbus_draw, 0, 1000 * mA);
+                if (!enabled) {
+                        regulator_enable(vbus_draw);
+                        gpio_vbus->vbus_draw_enabled = 1;
+                }
+        } else {
+                if (enabled) {
+                        regulator_disable(vbus_draw);
+                        gpio_vbus->vbus_draw_enabled = 0;
+                }
+        }
+        gpio_vbus->mA = mA;
+}
+
+/* VBUS change IRQ handler */
+static irqreturn_t gpio_vbus_irq(int irq, void *data)
+{
+        struct platform_device *pdev = data;
+        struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
+        struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
+        int gpio, vbus;
+
+        vbus = gpio_get_value(pdata->gpio_vbus);
+        if (pdata->gpio_vbus_inverted)
+                vbus = !vbus;
+
+        dev_dbg(&pdev->dev, "VBUS %s (gadget: %s)\n",
+                vbus ? "supplied" : "inactive",
+                gpio_vbus->otg.gadget ? gpio_vbus->otg.gadget->name : "none");
+
+        if (!gpio_vbus->otg.gadget)
+                return IRQ_HANDLED;
+
+        /* Peripheral controllers which manage the pullup themselves won't have
+         * gpio_pullup configured here.  If it's configured here, we'll do what
+         * isp1301_omap::b_peripheral() does and enable the pullup here... although
+         * that may complicate usb_gadget_{,dis}connect() support.
+         */
+        gpio = pdata->gpio_pullup;
+        if (vbus) {
+                gpio_vbus->otg.state = OTG_STATE_B_PERIPHERAL;
+                usb_gadget_vbus_connect(gpio_vbus->otg.gadget);
+
+                /* drawing a "unit load" is *always* OK, except for OTG */
+                set_vbus_draw(gpio_vbus, 100);
+
+                /* optionally enable D+ pullup */
+                if (gpio_is_valid(gpio))
+                        gpio_set_value(gpio, !pdata->gpio_pullup_inverted);
+        } else {
+                /* optionally disable D+ pullup */
+                if (gpio_is_valid(gpio))
+                        gpio_set_value(gpio, pdata->gpio_pullup_inverted);
+
+                set_vbus_draw(gpio_vbus, 0);
+
+                usb_gadget_vbus_disconnect(gpio_vbus->otg.gadget);
+                gpio_vbus->otg.state = OTG_STATE_B_IDLE;
+        }
+
+        return IRQ_HANDLED;
+}
+
+/* OTG transceiver interface */
+
+/* bind/unbind the peripheral controller */
+static int gpio_vbus_set_peripheral(struct otg_transceiver *otg,
+                                struct usb_gadget *gadget)
+{
+        struct gpio_vbus_data *gpio_vbus;
+        struct gpio_vbus_mach_info *pdata;
+        struct platform_device *pdev;
+        int gpio, irq;
+
+        gpio_vbus = container_of(otg, struct gpio_vbus_data, otg);
+        pdev = to_platform_device(gpio_vbus->dev);
+        pdata = gpio_vbus->dev->platform_data;
+        irq = gpio_to_irq(pdata->gpio_vbus);
+        gpio = pdata->gpio_pullup;
+
+        if (!gadget) {
+                dev_dbg(&pdev->dev, "unregistering gadget '%s'\n",
+                        otg->gadget->name);
+
+                /* optionally disable D+ pullup */
+                if (gpio_is_valid(gpio))
+                        gpio_set_value(gpio, pdata->gpio_pullup_inverted);
+
+                set_vbus_draw(gpio_vbus, 0);
+
+                usb_gadget_vbus_disconnect(otg->gadget);
+                otg->state = OTG_STATE_UNDEFINED;
+
+                otg->gadget = NULL;
+                return 0;
+        }
+
+        otg->gadget = gadget;
+        dev_dbg(&pdev->dev, "registered gadget '%s'\n", gadget->name);
+
+        /* initialize connection state */
+        gpio_vbus_irq(irq, pdev);
+        return 0;
+}
+
+/* effective for B devices, ignored for A-peripheral */
+static int gpio_vbus_set_power(struct otg_transceiver *otg, unsigned mA)
+{
+        struct gpio_vbus_data *gpio_vbus;
+
+        gpio_vbus = container_of(otg, struct gpio_vbus_data, otg);
+
+        if (otg->state == OTG_STATE_B_PERIPHERAL)
+                set_vbus_draw(gpio_vbus, mA);
+        return 0;
+}
+
+/* for non-OTG B devices: set/clear transceiver suspend mode */
+static int gpio_vbus_set_suspend(struct otg_transceiver *otg, int suspend)
+{
+        struct gpio_vbus_data *gpio_vbus;
+
+        gpio_vbus = container_of(otg, struct gpio_vbus_data, otg);
+
+        /* draw max 0 mA from vbus in suspend mode; or the previously
+         * recorded amount of current if not suspended
+         *
+         * NOTE: high powered configs (mA > 100) may draw up to 2.5 mA
+         * if they're wake-enabled ... we don't handle that yet.
+         */
+        return gpio_vbus_set_power(otg, suspend ? 0 : gpio_vbus->mA);
+}
+
+/* platform driver interface */
+
+static int __init gpio_vbus_probe(struct platform_device *pdev)
+{
+        struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
+        struct gpio_vbus_data *gpio_vbus;
+        struct resource *res;
+        int err, gpio, irq;
+
+        if (!pdata || !gpio_is_valid(pdata->gpio_vbus))
+                return -EINVAL;
+        gpio = pdata->gpio_vbus;
+
+        gpio_vbus = kzalloc(sizeof(struct gpio_vbus_data), GFP_KERNEL);
+        if (!gpio_vbus)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, gpio_vbus);
+        gpio_vbus->dev = &pdev->dev;
+        gpio_vbus->otg.label = "gpio-vbus";
+        gpio_vbus->otg.state = OTG_STATE_UNDEFINED;
+        gpio_vbus->otg.set_peripheral = gpio_vbus_set_peripheral;
+        gpio_vbus->otg.set_power = gpio_vbus_set_power;
+        gpio_vbus->otg.set_suspend = gpio_vbus_set_suspend;
+
+        err = gpio_request(gpio, "vbus_detect");
+        if (err) {
+                dev_err(&pdev->dev, "can't request vbus gpio %d, err: %d\n",
+                        gpio, err);
+                goto err_gpio;
+        }
+        gpio_direction_input(gpio);
+
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res) {
+                irq = res->start;
+                res->flags &= IRQF_TRIGGER_MASK;
+                res->flags |= IRQF_SAMPLE_RANDOM | IRQF_SHARED;
+        } else
+                irq = gpio_to_irq(gpio);
+
+        /* if data line pullup is in use, initialize it to "not pulling up" */
+        gpio = pdata->gpio_pullup;
+        if (gpio_is_valid(gpio)) {
+                err = gpio_request(gpio, "udc_pullup");
+                if (err) {
+                        dev_err(&pdev->dev,
+                                "can't request pullup gpio %d, err: %d\n",
+                                gpio, err);
+                        gpio_free(pdata->gpio_vbus);
+                        goto err_gpio;
+                }
+                gpio_direction_output(gpio, pdata->gpio_pullup_inverted);
+        }
+
+        err = request_irq(irq, gpio_vbus_irq, VBUS_IRQ_FLAGS,
+                "vbus_detect", pdev);
+        if (err) {
+                dev_err(&pdev->dev, "can't request irq %i, err: %d\n",
+                        irq, err);
+                goto err_irq;
+        }
+
+        /* only active when a gadget is registered */
+        err = otg_set_transceiver(&gpio_vbus->otg);
+        if (err) {
+                dev_err(&pdev->dev, "can't register transceiver, err: %d\n",
+                        err);
+                goto err_otg;
+        }
+
+        gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");
+        if (IS_ERR(gpio_vbus->vbus_draw)) {
+                dev_dbg(&pdev->dev, "can't get vbus_draw regulator, err: %ld\n",
+                        PTR_ERR(gpio_vbus->vbus_draw));
+                gpio_vbus->vbus_draw = NULL;
+        }
+
+        return 0;
+err_otg:
+        free_irq(irq, &pdev->dev);
+err_irq:
+        if (gpio_is_valid(pdata->gpio_pullup))
+                gpio_free(pdata->gpio_pullup);
+        gpio_free(pdata->gpio_vbus);
+err_gpio:
+        platform_set_drvdata(pdev, NULL);
+        kfree(gpio_vbus);
+        return err;
+}
+
+static int __exit gpio_vbus_remove(struct platform_device *pdev)
+{
+        struct gpio_vbus_data *gpio_vbus = platform_get_drvdata(pdev);
+        struct gpio_vbus_mach_info *pdata = pdev->dev.platform_data;
+        int gpio = pdata->gpio_vbus;
+
+        regulator_put(gpio_vbus->vbus_draw);
+
+        otg_set_transceiver(NULL);
+
+        free_irq(gpio_to_irq(gpio), &pdev->dev);
+        if (gpio_is_valid(pdata->gpio_pullup))
+                gpio_free(pdata->gpio_pullup);
+        gpio_free(gpio);
+        platform_set_drvdata(pdev, NULL);
+        kfree(gpio_vbus);
+
+        return 0;
+}
+
+/* NOTE:  the gpio-vbus device may *NOT* be hotplugged */
+
+MODULE_ALIAS("platform:gpio-vbus");
+
+static struct platform_driver gpio_vbus_driver = {
+        .driver = {
+                .name  = "gpio-vbus",
+                .owner = THIS_MODULE,
+        },
+        .remove  = __exit_p(gpio_vbus_remove),
+};
+
+static int __init gpio_vbus_init(void)
+{
+        return platform_driver_probe(&gpio_vbus_driver, gpio_vbus_probe);
+}
+module_init(gpio_vbus_init);
+
+static void __exit gpio_vbus_exit(void)
+{
+        platform_driver_unregister(&gpio_vbus_driver);
+}
+module_exit(gpio_vbus_exit);
+
+MODULE_DESCRIPTION("simple GPIO controlled OTG transceiver driver");
+MODULE_AUTHOR("Philipp Zabel");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index e0d56ef2bcb0..e0d56ef2bcb0 100644
--- a/drivers/i2c/chips/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
new file mode 100644
index 000000000000..ff318fae7d4d
--- /dev/null
+++ b/drivers/usb/otg/otg.c
@@ -0,0 +1,65 @@
+/*
+ * otg.c -- USB OTG utility code
+ *
+ * Copyright (C) 2004 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <linux/usb/otg.h>
+
+static struct otg_transceiver *xceiv;
+
+/**
+ * otg_get_transceiver - find the (single) OTG transceiver
+ *
+ * Returns the transceiver driver, after getting a refcount to it; or
+ * null if there is no such transceiver.  The caller is responsible for
+ * calling otg_put_transceiver() to release that count.
+ *
+ * For use by USB host and peripheral drivers.
+ */
+struct otg_transceiver *otg_get_transceiver(void)
+{
+        if (xceiv)
+                get_device(xceiv->dev);
+        return xceiv;
+}
+EXPORT_SYMBOL(otg_get_transceiver);
+
+/**
+ * otg_put_transceiver - release the (single) OTG transceiver
+ * @x: the transceiver returned by otg_get_transceiver()
+ *
+ * Releases a refcount the caller received from otg_get_transceiver().
+ *
+ * For use by USB host and peripheral drivers.
+ */
+void otg_put_transceiver(struct otg_transceiver *x)
+{
+        put_device(x->dev);
+}
+EXPORT_SYMBOL(otg_put_transceiver);
+
+/**
+ * otg_set_transceiver - declare the (single) OTG transceiver
+ * @x: the USB OTG transceiver to be used; or NULL
+ *
+ * This call is exclusively for use by transceiver drivers, which
+ * coordinate the activities of drivers for host and peripheral
+ * controllers, and in some cases for VBUS current regulation.
+ */
+int otg_set_transceiver(struct otg_transceiver *x)
+{
+        if (xceiv && x)
+                return -EBUSY;
+        xceiv = x;
+        return 0;
+}
+EXPORT_SYMBOL(otg_set_transceiver);
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
new file mode 100644
index 000000000000..416e4410be02
--- /dev/null
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -0,0 +1,721 @@
+/*
+ * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
+ *
+ * Copyright (C) 2004-2007 Texas Instruments
+ * Copyright (C) 2008 Nokia Corporation
+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Current status:
+ *      - HS USB ULPI mode works.
+ *      - 3-pin mode support may be added in future.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/usb/otg.h>
+#include <linux/i2c/twl4030.h>
+
+
+/* Register defines */
+
+#define VENDOR_ID_LO                    0x00
+#define VENDOR_ID_HI                    0x01
+#define PRODUCT_ID_LO                   0x02
+#define PRODUCT_ID_HI                   0x03
+
+#define FUNC_CTRL                       0x04
+#define FUNC_CTRL_SET                   0x05
+#define FUNC_CTRL_CLR                   0x06
+#define FUNC_CTRL_SUSPENDM              (1 << 6)
+#define FUNC_CTRL_RESET                 (1 << 5)
+#define FUNC_CTRL_OPMODE_MASK           (3 << 3) /* bits 3 and 4 */
+#define FUNC_CTRL_OPMODE_NORMAL         (0 << 3)
+#define FUNC_CTRL_OPMODE_NONDRIVING     (1 << 3)
+#define FUNC_CTRL_OPMODE_DISABLE_BIT_NRZI       (2 << 3)
+#define FUNC_CTRL_TERMSELECT            (1 << 2)
+#define FUNC_CTRL_XCVRSELECT_MASK       (3 << 0) /* bits 0 and 1 */
+#define FUNC_CTRL_XCVRSELECT_HS         (0 << 0)
+#define FUNC_CTRL_XCVRSELECT_FS         (1 << 0)
+#define FUNC_CTRL_XCVRSELECT_LS         (2 << 0)
+#define FUNC_CTRL_XCVRSELECT_FS4LS      (3 << 0)
+
+#define IFC_CTRL                        0x07
+#define IFC_CTRL_SET                    0x08
+#define IFC_CTRL_CLR                    0x09
+#define IFC_CTRL_INTERFACE_PROTECT_DISABLE      (1 << 7)
+#define IFC_CTRL_AUTORESUME             (1 << 4)
+#define IFC_CTRL_CLOCKSUSPENDM          (1 << 3)
+#define IFC_CTRL_CARKITMODE             (1 << 2)
+#define IFC_CTRL_FSLSSERIALMODE_3PIN    (1 << 1)
+
+#define TWL4030_OTG_CTRL                0x0A
+#define TWL4030_OTG_CTRL_SET            0x0B
+#define TWL4030_OTG_CTRL_CLR            0x0C
+#define TWL4030_OTG_CTRL_DRVVBUS        (1 << 5)
+#define TWL4030_OTG_CTRL_CHRGVBUS       (1 << 4)
+#define TWL4030_OTG_CTRL_DISCHRGVBUS    (1 << 3)
+#define TWL4030_OTG_CTRL_DMPULLDOWN     (1 << 2)
+#define TWL4030_OTG_CTRL_DPPULLDOWN     (1 << 1)
+#define TWL4030_OTG_CTRL_IDPULLUP       (1 << 0)
+
+#define USB_INT_EN_RISE                 0x0D
+#define USB_INT_EN_RISE_SET             0x0E
+#define USB_INT_EN_RISE_CLR             0x0F
+#define USB_INT_EN_FALL                 0x10
+#define USB_INT_EN_FALL_SET             0x11
+#define USB_INT_EN_FALL_CLR             0x12
+#define USB_INT_STS                     0x13
+#define USB_INT_LATCH                   0x14
+#define USB_INT_IDGND                   (1 << 4)
+#define USB_INT_SESSEND                 (1 << 3)
+#define USB_INT_SESSVALID               (1 << 2)
+#define USB_INT_VBUSVALID               (1 << 1)
+#define USB_INT_HOSTDISCONNECT          (1 << 0)
+
+#define CARKIT_CTRL                     0x19
+#define CARKIT_CTRL_SET                 0x1A
+#define CARKIT_CTRL_CLR                 0x1B
+#define CARKIT_CTRL_MICEN               (1 << 6)
+#define CARKIT_CTRL_SPKRIGHTEN          (1 << 5)
+#define CARKIT_CTRL_SPKLEFTEN           (1 << 4)
+#define CARKIT_CTRL_RXDEN               (1 << 3)
+#define CARKIT_CTRL_TXDEN               (1 << 2)
+#define CARKIT_CTRL_IDGNDDRV            (1 << 1)
+#define CARKIT_CTRL_CARKITPWR           (1 << 0)
+#define CARKIT_PLS_CTRL                 0x22
+#define CARKIT_PLS_CTRL_SET             0x23
+#define CARKIT_PLS_CTRL_CLR             0x24
+#define CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN        (1 << 3)
+#define CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2)
+#define CARKIT_PLS_CTRL_RXPLSEN         (1 << 1)
+#define CARKIT_PLS_CTRL_TXPLSEN         (1 << 0)
+
+#define MCPC_CTRL                       0x30
+#define MCPC_CTRL_SET                   0x31
+#define MCPC_CTRL_CLR                   0x32
+#define MCPC_CTRL_RTSOL                 (1 << 7)
+#define MCPC_CTRL_EXTSWR                (1 << 6)
+#define MCPC_CTRL_EXTSWC                (1 << 5)
+#define MCPC_CTRL_VOICESW               (1 << 4)
+#define MCPC_CTRL_OUT64K                (1 << 3)
+#define MCPC_CTRL_RTSCTSSW              (1 << 2)
+#define MCPC_CTRL_HS_UART               (1 << 0)
+
+#define MCPC_IO_CTRL                    0x33
+#define MCPC_IO_CTRL_SET                0x34
+#define MCPC_IO_CTRL_CLR                0x35
+#define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
+#define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
+#define MCPC_IO_CTRL_RXD_PU             (1 << 3)
+#define MCPC_IO_CTRL_TXDTYP             (1 << 2)
+#define MCPC_IO_CTRL_CTSTYP             (1 << 1)
+#define MCPC_IO_CTRL_RTSTYP             (1 << 0)
+
+#define MCPC_CTRL2                      0x36
+#define MCPC_CTRL2_SET                  0x37
+#define MCPC_CTRL2_CLR                  0x38
+#define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
+
+#define OTHER_FUNC_CTRL                 0x80
+#define OTHER_FUNC_CTRL_SET             0x81
+#define OTHER_FUNC_CTRL_CLR             0x82
+#define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
+#define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
+
+#define OTHER_IFC_CTRL                  0x83
+#define OTHER_IFC_CTRL_SET              0x84
+#define OTHER_IFC_CTRL_CLR              0x85
+#define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
+#define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
+#define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
+#define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
+#define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
+#define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
+
+#define OTHER_INT_EN_RISE               0x86
+#define OTHER_INT_EN_RISE_SET           0x87
+#define OTHER_INT_EN_RISE_CLR           0x88
+#define OTHER_INT_EN_FALL               0x89
+#define OTHER_INT_EN_FALL_SET           0x8A
+#define OTHER_INT_EN_FALL_CLR           0x8B
+#define OTHER_INT_STS                   0x8C
+#define OTHER_INT_LATCH                 0x8D
+#define OTHER_INT_VB_SESS_VLD           (1 << 7)
+#define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
+#define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
+#define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
+#define OTHER_INT_MANU                  (1 << 1)
+#define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
+
+#define ID_STATUS                       0x96
+#define ID_RES_FLOAT                    (1 << 4)
+#define ID_RES_440K                     (1 << 3)
+#define ID_RES_200K                     (1 << 2)
+#define ID_RES_102K                     (1 << 1)
+#define ID_RES_GND                      (1 << 0)
+
+#define POWER_CTRL                      0xAC
+#define POWER_CTRL_SET                  0xAD
+#define POWER_CTRL_CLR                  0xAE
+#define POWER_CTRL_OTG_ENAB             (1 << 5)
+
+#define OTHER_IFC_CTRL2                 0xAF
+#define OTHER_IFC_CTRL2_SET             0xB0
+#define OTHER_IFC_CTRL2_CLR             0xB1
+#define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
+#define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
+#define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
+#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
+#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
+#define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
+
+#define REG_CTRL_EN                     0xB2
+#define REG_CTRL_EN_SET                 0xB3
+#define REG_CTRL_EN_CLR                 0xB4
+#define REG_CTRL_ERROR                  0xB5
+#define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
+
+#define OTHER_FUNC_CTRL2                0xB8
+#define OTHER_FUNC_CTRL2_SET            0xB9
+#define OTHER_FUNC_CTRL2_CLR            0xBA
+#define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
+
+/* following registers do not have separate _clr and _set registers */
+#define VBUS_DEBOUNCE                   0xC0
+#define ID_DEBOUNCE                     0xC1
+#define VBAT_TIMER                      0xD3
+#define PHY_PWR_CTRL                    0xFD
+#define PHY_PWR_PHYPWD                  (1 << 0)
+#define PHY_CLK_CTRL                    0xFE
+#define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
+#define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
+#define REQ_PHY_DPLL_CLK                (1 << 0)
+#define PHY_CLK_CTRL_STS                0xFF
+#define PHY_DPLL_CLK                    (1 << 0)
+
+/* In module TWL4030_MODULE_PM_MASTER */
+#define PROTECT_KEY                     0x0E
+
+/* In module TWL4030_MODULE_PM_RECEIVER */
+#define VUSB_DEDICATED1                 0x7D
+#define VUSB_DEDICATED2                 0x7E
+#define VUSB1V5_DEV_GRP                 0x71
+#define VUSB1V5_TYPE                    0x72
+#define VUSB1V5_REMAP                   0x73
+#define VUSB1V8_DEV_GRP                 0x74
+#define VUSB1V8_TYPE                    0x75
+#define VUSB1V8_REMAP                   0x76
+#define VUSB3V1_DEV_GRP                 0x77
+#define VUSB3V1_TYPE                    0x78
+#define VUSB3V1_REMAP                   0x79
+
+/* In module TWL4030_MODULE_INTBR */
+#define PMBR1                           0x0D
+#define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
+
+
+
+enum linkstat {
+        USB_LINK_UNKNOWN = 0,
+        USB_LINK_NONE,
+        USB_LINK_VBUS,
+        USB_LINK_ID,
+};
+
+struct twl4030_usb {
+        struct otg_transceiver  otg;
+        struct device           *dev;
+
+        /* for vbus reporting with irqs disabled */
+        spinlock_t              lock;
+
+        /* pin configuration */
+        enum twl4030_usb_mode   usb_mode;
+
+        int                     irq;
+        u8                      linkstat;
+        u8                      asleep;
+        bool                    irq_enabled;
+};
+
+/* internal define on top of container_of */
+#define xceiv_to_twl(x)         container_of((x), struct twl4030_usb, otg);
+
+/*-------------------------------------------------------------------------*/
+
+static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
+                u8 module, u8 data, u8 address)
+{
+        u8 check;
+
+        if ((twl4030_i2c_write_u8(module, data, address) >= 0) &&
+            (twl4030_i2c_read_u8(module, &check, address) >= 0) &&
+                                                (check == data))
+                return 0;
+        dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
+                        1, module, address, check, data);
+
+        /* Failed once: Try again */
+        if ((twl4030_i2c_write_u8(module, data, address) >= 0) &&
+            (twl4030_i2c_read_u8(module, &check, address) >= 0) &&
+                                                (check == data))
+                return 0;
+        dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
+                        2, module, address, check, data);
+
+        /* Failed again: Return error */
+        return -EBUSY;
+}
+
+#define twl4030_usb_write_verify(twl, address, data)    \
+        twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
+
+static inline int twl4030_usb_write(struct twl4030_usb *twl,
+                u8 address, u8 data)
+{
+        int ret = 0;
+
+        ret = twl4030_i2c_write_u8(TWL4030_MODULE_USB, data, address);
+        if (ret < 0)
+                dev_dbg(twl->dev,
+                        "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
+        return ret;
+}
+
+static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
+{
+        u8 data;
+        int ret = 0;
+
+        ret = twl4030_i2c_read_u8(module, &data, address);
+        if (ret >= 0)
+                ret = data;
+        else
+                dev_dbg(twl->dev,
+                        "TWL4030:readb[0x%x,0x%x] Error %d\n",
+                                        module, address, ret);
+
+        return ret;
+}
+
+static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
+{
+        return twl4030_readb(twl, TWL4030_MODULE_USB, address);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static inline int
+twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
+{
+        return twl4030_usb_write(twl, reg + 1, bits);
+}
+
+static inline int
+twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
+{
+        return twl4030_usb_write(twl, reg + 2, bits);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static enum linkstat twl4030_usb_linkstat(struct twl4030_usb *twl)
+{
+        int     status;
+        int     linkstat = USB_LINK_UNKNOWN;
+
+        /* STS_HW_CONDITIONS */
+        status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER, 0x0f);
+        if (status < 0)
+                dev_err(twl->dev, "USB link status err %d\n", status);
+        else if (status & BIT(7))
+                linkstat = USB_LINK_VBUS;
+        else if (status & BIT(2))
+                linkstat = USB_LINK_ID;
+        else
+                linkstat = USB_LINK_NONE;
+
+        dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
+                        status, status, linkstat);
+
+        /* REVISIT this assumes host and peripheral controllers
+         * are registered, and that both are active...
+         */
+
+        spin_lock_irq(&twl->lock);
+        twl->linkstat = linkstat;
+        if (linkstat == USB_LINK_ID) {
+                twl->otg.default_a = true;
+                twl->otg.state = OTG_STATE_A_IDLE;
+        } else {
+                twl->otg.default_a = false;
+                twl->otg.state = OTG_STATE_B_IDLE;
+        }
+        spin_unlock_irq(&twl->lock);
+
+        return linkstat;
+}
+
+static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
+{
+        twl->usb_mode = mode;
+
+        switch (mode) {
+        case T2_USB_MODE_ULPI:
+                twl4030_usb_clear_bits(twl, IFC_CTRL, IFC_CTRL_CARKITMODE);
+                twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
+                twl4030_usb_clear_bits(twl, FUNC_CTRL,
+                                        FUNC_CTRL_XCVRSELECT_MASK |
+                                        FUNC_CTRL_OPMODE_MASK);
+                break;
+        case -1:
+                /* FIXME: power on defaults */
+                break;
+        default:
+                dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
+                                mode);
+                break;
+        };
+}
+
+static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
+{
+        unsigned long timeout;
+        int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
+
+        if (val >= 0) {
+                if (on) {
+                        /* enable DPLL to access PHY registers over I2C */
+                        val |= REQ_PHY_DPLL_CLK;
+                        WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
+                                                (u8)val) < 0);
+
+                        timeout = jiffies + HZ;
+                        while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
+                                                        PHY_DPLL_CLK)
+                                && time_before(jiffies, timeout))
+                                        udelay(10);
+                        if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
+                                                        PHY_DPLL_CLK))
+                                dev_err(twl->dev, "Timeout setting T2 HSUSB "
+                                                "PHY DPLL clock\n");
+                } else {
+                        /* let ULPI control the DPLL clock */
+                        val &= ~REQ_PHY_DPLL_CLK;
+                        WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
+                                                (u8)val) < 0);
+                }
+        }
+}
+
+static void twl4030_phy_power(struct twl4030_usb *twl, int on)
+{
+        u8 pwr;
+
+        pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
+        if (on) {
+                pwr &= ~PHY_PWR_PHYPWD;
+                WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
+                twl4030_usb_write(twl, PHY_CLK_CTRL,
+                                  twl4030_usb_read(twl, PHY_CLK_CTRL) |
+                                        (PHY_CLK_CTRL_CLOCKGATING_EN |
+                                                PHY_CLK_CTRL_CLK32K_EN));
+        } else  {
+                pwr |= PHY_PWR_PHYPWD;
+                WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
+        }
+}
+
+static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
+{
+        if (twl->asleep)
+                return;
+
+        twl4030_phy_power(twl, 0);
+        twl->asleep = 1;
+}
+
+static void twl4030_phy_resume(struct twl4030_usb *twl)
+{
+        if (!twl->asleep)
+                return;
+
+        twl4030_phy_power(twl, 1);
+        twl4030_i2c_access(twl, 1);
+        twl4030_usb_set_mode(twl, twl->usb_mode);
+        if (twl->usb_mode == T2_USB_MODE_ULPI)
+                twl4030_i2c_access(twl, 0);
+        twl->asleep = 0;
+}
+
+static void twl4030_usb_ldo_init(struct twl4030_usb *twl)
+{
+        /* Enable writing to power configuration registers */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY);
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x0C, PROTECT_KEY);
+
+        /* put VUSB3V1 LDO in active state */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
+
+        /* input to VUSB3V1 LDO is from VBAT, not VBUS */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
+
+        /* turn on 3.1V regulator */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB3V1_DEV_GRP);
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
+
+        /* turn on 1.5V regulator */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V5_DEV_GRP);
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
+
+        /* turn on 1.8V regulator */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V8_DEV_GRP);
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
+
+        /* disable access to power configuration registers */
+        twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY);
+}
+
+static ssize_t twl4030_usb_vbus_show(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct twl4030_usb *twl = dev_get_drvdata(dev);
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        spin_lock_irqsave(&twl->lock, flags);
+        ret = sprintf(buf, "%s\n",
+                        (twl->linkstat == USB_LINK_VBUS) ? "on" : "off");
+        spin_unlock_irqrestore(&twl->lock, flags);
+
+        return ret;
+}
+static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
+
+static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
+{
+        struct twl4030_usb *twl = _twl;
+        int status;
+
+#ifdef CONFIG_LOCKDEP
+        /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which
+         * we don't want and can't tolerate.  Although it might be
+         * friendlier not to borrow this thread context...
+         */
+        local_irq_enable();
+#endif
+
+        status = twl4030_usb_linkstat(twl);
+        if (status != USB_LINK_UNKNOWN) {
+
+                /* FIXME add a set_power() method so that B-devices can
+                 * configure the charger appropriately.  It's not always
+                 * correct to consume VBUS power, and how much current to
+                 * consume is a function of the USB configuration chosen
+                 * by the host.
+                 *
+                 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
+                 * its disconnect() sibling, when changing to/from the
+                 * USB_LINK_VBUS state.  musb_hdrc won't care until it
+                 * starts to handle softconnect right.
+                 */
+                twl4030charger_usb_en(status == USB_LINK_VBUS);
+
+                if (status == USB_LINK_NONE)
+                        twl4030_phy_suspend(twl, 0);
+                else
+                        twl4030_phy_resume(twl);
+        }
+        sysfs_notify(&twl->dev->kobj, NULL, "vbus");
+
+        return IRQ_HANDLED;
+}
+
+static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
+{
+        struct twl4030_usb *twl = xceiv_to_twl(x);
+
+        if (suspend)
+                twl4030_phy_suspend(twl, 1);
+        else
+                twl4030_phy_resume(twl);
+
+        return 0;
+}
+
+static int twl4030_set_peripheral(struct otg_transceiver *x,
+                struct usb_gadget *gadget)
+{
+        struct twl4030_usb *twl;
+
+        if (!x)
+                return -ENODEV;
+
+        twl = xceiv_to_twl(x);
+        twl->otg.gadget = gadget;
+        if (!gadget)
+                twl->otg.state = OTG_STATE_UNDEFINED;
+
+        return 0;
+}
+
+static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
+{
+        struct twl4030_usb *twl;
+
+        if (!x)
+                return -ENODEV;
+
+        twl = xceiv_to_twl(x);
+        twl->otg.host = host;
+        if (!host)
+                twl->otg.state = OTG_STATE_UNDEFINED;
+
+        return 0;
+}
+
+static int __init twl4030_usb_probe(struct platform_device *pdev)
+{
+        struct twl4030_usb_data *pdata = pdev->dev.platform_data;
+        struct twl4030_usb      *twl;
+        int                     status;
+
+        if (!pdata) {
+                dev_dbg(&pdev->dev, "platform_data not available\n");
+                return -EINVAL;
+        }
+
+        twl = kzalloc(sizeof *twl, GFP_KERNEL);
+        if (!twl)
+                return -ENOMEM;
+
+        twl->dev                = &pdev->dev;
+        twl->irq                = platform_get_irq(pdev, 0);
+        twl->otg.dev            = twl->dev;
+        twl->otg.label          = "twl4030";
+        twl->otg.set_host       = twl4030_set_host;
+        twl->otg.set_peripheral = twl4030_set_peripheral;
+        twl->otg.set_suspend    = twl4030_set_suspend;
+        twl->usb_mode           = pdata->usb_mode;
+        twl->asleep             = 1;
+
+        /* init spinlock for workqueue */
+        spin_lock_init(&twl->lock);
+
+        twl4030_usb_ldo_init(twl);
+        otg_set_transceiver(&twl->otg);
+
+        platform_set_drvdata(pdev, twl);
+        if (device_create_file(&pdev->dev, &dev_attr_vbus))
+                dev_warn(&pdev->dev, "could not create sysfs file\n");
+
+        /* Our job is to use irqs and status from the power module
+         * to keep the transceiver disabled when nothing's connected.
+         *
+         * FIXME we actually shouldn't start enabling it until the
+         * USB controller drivers have said they're ready, by calling
+         * set_host() and/or set_peripheral() ... OTG_capable boards
+         * need both handles, otherwise just one suffices.
+         */
+        twl->irq_enabled = true;
+        status = request_irq(twl->irq, twl4030_usb_irq,
+                        IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                        "twl4030_usb", twl);
+        if (status < 0) {
+                dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
+                        twl->irq, status);
+                kfree(twl);
+                return status;
+        }
+
+        /* The IRQ handler just handles changes from the previous states
+         * of the ID and VBUS pins ... in probe() we must initialize that
+         * previous state.  The easy way:  fake an IRQ.
+         *
+         * REVISIT:  a real IRQ might have happened already, if PREEMPT is
+         * enabled.  Else the IRQ may not yet be configured or enabled,
+         * because of scheduling delays.
+         */
+        twl4030_usb_irq(twl->irq, twl);
+
+        dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
+        return 0;
+}
+
+static int __exit twl4030_usb_remove(struct platform_device *pdev)
+{
+        struct twl4030_usb *twl = platform_get_drvdata(pdev);
+        int val;
+
+        free_irq(twl->irq, twl);
+        device_remove_file(twl->dev, &dev_attr_vbus);
+
+        /* set transceiver mode to power on defaults */
+        twl4030_usb_set_mode(twl, -1);
+
+        /* autogate 60MHz ULPI clock,
+         * clear dpll clock request for i2c access,
+         * disable 32KHz
+         */
+        val = twl4030_usb_read(twl, PHY_CLK_CTRL);
+        if (val >= 0) {
+                val |= PHY_CLK_CTRL_CLOCKGATING_EN;
+                val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
+                twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
+        }
+
+        /* disable complete OTG block */
+        twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
+
+        twl4030_phy_power(twl, 0);
+
+        kfree(twl);
+
+        return 0;
+}
+
+static struct platform_driver twl4030_usb_driver = {
+        .probe          = twl4030_usb_probe,
+        .remove         = __exit_p(twl4030_usb_remove),
+        .driver         = {
+                .name   = "twl4030_usb",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init twl4030_usb_init(void)
+{
+        return platform_driver_register(&twl4030_usb_driver);
+}
+subsys_initcall(twl4030_usb_init);
+
+static void __exit twl4030_usb_exit(void)
+{
+        platform_driver_unregister(&twl4030_usb_driver);
+}
+module_exit(twl4030_usb_exit);
+
+MODULE_ALIAS("platform:twl4030_usb");
+MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
+MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/serial/Kconfig b/drivers/usb/serial/Kconfig
index 70338f4ec918..b361f05cafac 100644
--- a/drivers/usb/serial/Kconfig
+++ b/drivers/usb/serial/Kconfig
@@ -496,6 +496,14 @@ config USB_SERIAL_SAFE_PADDED
         bool "USB Secure Encapsulated Driver - Padded"
         depends on USB_SERIAL_SAFE
 
+config USB_SERIAL_SIEMENS_MPI
+        tristate "USB Siemens MPI driver"
+        help
+          Say M here if you want to use a Siemens USB/MPI adapter.
+
+          To compile this driver as a module, choose M here: the
+          module will be called siemens_mpi.
+
 config USB_SERIAL_SIERRAWIRELESS
         tristate "USB Sierra Wireless Driver"
         help
@@ -565,6 +573,15 @@ config USB_SERIAL_OMNINET
           To compile this driver as a module, choose M here: the
           module will be called omninet.
 
+config USB_SERIAL_OPTICON
+        tristate "USB Opticon Barcode driver (serial mode)"
+        help
+          Say Y here if you want to use a Opticon USB Barcode device
+          in serial emulation mode.
+
+          To compile this driver as a module, choose M here: the
+          module will be called opticon.
+
 config USB_SERIAL_DEBUG
         tristate "USB Debugging Device"
         help
diff --git a/drivers/usb/serial/Makefile b/drivers/usb/serial/Makefile
index 6047f818adfe..b75be91eb8f1 100644
--- a/drivers/usb/serial/Makefile
+++ b/drivers/usb/serial/Makefile
@@ -41,10 +41,12 @@ obj-$(CONFIG_USB_SERIAL_MOS7840)		+= mos7840.o
 obj-$(CONFIG_USB_SERIAL_MOTOROLA)               += moto_modem.o
 obj-$(CONFIG_USB_SERIAL_NAVMAN)                 += navman.o
 obj-$(CONFIG_USB_SERIAL_OMNINET)                += omninet.o
+obj-$(CONFIG_USB_SERIAL_OPTICON)                += opticon.o
 obj-$(CONFIG_USB_SERIAL_OPTION)                 += option.o
 obj-$(CONFIG_USB_SERIAL_OTI6858)                += oti6858.o
 obj-$(CONFIG_USB_SERIAL_PL2303)                 += pl2303.o
 obj-$(CONFIG_USB_SERIAL_SAFE)                   += safe_serial.o
+obj-$(CONFIG_USB_SERIAL_SIEMENS_MPI)            += siemens_mpi.o
 obj-$(CONFIG_USB_SERIAL_SIERRAWIRELESS)         += sierra.o
 obj-$(CONFIG_USB_SERIAL_SPCP8X5)                += spcp8x5.o
 obj-$(CONFIG_USB_SERIAL_TI)                     += ti_usb_3410_5052.o
diff --git a/drivers/usb/serial/digi_acceleport.c b/drivers/usb/serial/digi_acceleport.c
index 69f84f0ea6fe..38ba4ea8b6bf 100644
--- a/drivers/usb/serial/digi_acceleport.c
+++ b/drivers/usb/serial/digi_acceleport.c
@@ -635,8 +635,7 @@ static int digi_write_oob_command(struct usb_serial_port *port,
 
         spin_lock_irqsave(&oob_priv->dp_port_lock, flags);
         while (count > 0) {
-                while (oob_port->write_urb->status == -EINPROGRESS
-                        || oob_priv->dp_write_urb_in_use) {
+                while (oob_priv->dp_write_urb_in_use) {
                         cond_wait_interruptible_timeout_irqrestore(
                                 &oob_port->write_wait, DIGI_RETRY_TIMEOUT,
                                 &oob_priv->dp_port_lock, flags);
@@ -699,9 +698,8 @@ static int digi_write_inb_command(struct usb_serial_port *port,
 
         spin_lock_irqsave(&priv->dp_port_lock, flags);
         while (count > 0 && ret == 0) {
-                while ((port->write_urb->status == -EINPROGRESS
-                                || priv->dp_write_urb_in_use)
-                                        && time_before(jiffies, timeout)) {
+                while (priv->dp_write_urb_in_use &&
+                       time_before(jiffies, timeout)) {
                         cond_wait_interruptible_timeout_irqrestore(
                                 &port->write_wait, DIGI_RETRY_TIMEOUT,
                                 &priv->dp_port_lock, flags);
@@ -779,8 +777,7 @@ static int digi_set_modem_signals(struct usb_serial_port *port,
         spin_lock_irqsave(&oob_priv->dp_port_lock, flags);
         spin_lock(&port_priv->dp_port_lock);
 
-        while (oob_port->write_urb->status == -EINPROGRESS ||
-                                        oob_priv->dp_write_urb_in_use) {
+        while (oob_priv->dp_write_urb_in_use) {
                 spin_unlock(&port_priv->dp_port_lock);
                 cond_wait_interruptible_timeout_irqrestore(
                         &oob_port->write_wait, DIGI_RETRY_TIMEOUT,
@@ -1168,12 +1165,10 @@ static int digi_write(struct tty_struct *tty, struct usb_serial_port *port,
 
         /* be sure only one write proceeds at a time */
         /* there are races on the port private buffer */
-        /* and races to check write_urb->status */
         spin_lock_irqsave(&priv->dp_port_lock, flags);
 
         /* wait for urb status clear to submit another urb */
-        if (port->write_urb->status == -EINPROGRESS ||
-                                        priv->dp_write_urb_in_use) {
+        if (priv->dp_write_urb_in_use) {
                 /* buffer data if count is 1 (probably put_char) if possible */
                 if (count == 1 && priv->dp_out_buf_len < DIGI_OUT_BUF_SIZE) {
                         priv->dp_out_buf[priv->dp_out_buf_len++] = *buf;
@@ -1236,7 +1231,7 @@ static void digi_write_bulk_callback(struct urb *urb)
         int ret = 0;
         int status = urb->status;
 
-        dbg("digi_write_bulk_callback: TOP, urb->status=%d", status);
+        dbg("digi_write_bulk_callback: TOP, status=%d", status);
 
         /* port and serial sanity check */
         if (port == NULL || (priv = usb_get_serial_port_data(port)) == NULL) {
@@ -1266,8 +1261,7 @@ static void digi_write_bulk_callback(struct urb *urb)
         /* try to send any buffered data on this port, if it is open */
         spin_lock(&priv->dp_port_lock);
         priv->dp_write_urb_in_use = 0;
-        if (port->port.count && port->write_urb->status != -EINPROGRESS
-            && priv->dp_out_buf_len > 0) {
+        if (port->port.count && priv->dp_out_buf_len > 0) {
                 *((unsigned char *)(port->write_urb->transfer_buffer))
                         = (unsigned char)DIGI_CMD_SEND_DATA;
                 *((unsigned char *)(port->write_urb->transfer_buffer) + 1)
@@ -1305,8 +1299,7 @@ static int digi_write_room(struct tty_struct *tty)
 
         spin_lock_irqsave(&priv->dp_port_lock, flags);
 
-        if (port->write_urb->status == -EINPROGRESS ||
-                                        priv->dp_write_urb_in_use)
+        if (priv->dp_write_urb_in_use)
                 room = 0;
         else
                 room = port->bulk_out_size - 2 - priv->dp_out_buf_len;
@@ -1322,8 +1315,7 @@ static int digi_chars_in_buffer(struct tty_struct *tty)
         struct usb_serial_port *port = tty->driver_data;
         struct digi_port *priv = usb_get_serial_port_data(port);
 
-        if (port->write_urb->status == -EINPROGRESS
-            || priv->dp_write_urb_in_use) {
+        if (priv->dp_write_urb_in_use) {
                 dbg("digi_chars_in_buffer: port=%d, chars=%d",
                         priv->dp_port_num, port->bulk_out_size - 2);
                 /* return(port->bulk_out_size - 2); */
@@ -1702,7 +1694,7 @@ static int digi_read_inb_callback(struct urb *urb)
         /* short/multiple packet check */
         if (urb->actual_length != len + 2) {
                 dev_err(&port->dev, "%s: INCOMPLETE OR MULTIPLE PACKET, "
-                        "urb->status=%d, port=%d, opcode=%d, len=%d, "
+                        "status=%d, port=%d, opcode=%d, len=%d, "
                         "actual_length=%d, status=%d\n", __func__, status,
                         priv->dp_port_num, opcode, len, urb->actual_length,
                         port_status);
diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
index 8e6a66e38db2..a26a0e2cdb4a 100644
--- a/drivers/usb/serial/garmin_gps.c
+++ b/drivers/usb/serial/garmin_gps.c
@@ -1056,7 +1056,7 @@ static void garmin_write_bulk_callback(struct urb *urb)
 
                 if (status) {
                         dbg("%s - nonzero write bulk status received: %d",
-                            __func__, urb->status);
+                            __func__, status);
                         spin_lock_irqsave(&garmin_data_p->lock, flags);
                         garmin_data_p->flags |= CLEAR_HALT_REQUIRED;
                         spin_unlock_irqrestore(&garmin_data_p->lock, flags);
diff --git a/drivers/usb/serial/ipw.c b/drivers/usb/serial/ipw.c
index 3ac59a8a980f..f530032ed93d 100644
--- a/drivers/usb/serial/ipw.c
+++ b/drivers/usb/serial/ipw.c
@@ -473,7 +473,7 @@ static struct usb_serial_driver ipw_device = {
 
 
 
-static int usb_ipw_init(void)
+static int __init usb_ipw_init(void)
 {
         int retval;
 
@@ -490,7 +490,7 @@ static int usb_ipw_init(void)
         return 0;
 }
 
-static void usb_ipw_exit(void)
+static void __exit usb_ipw_exit(void)
 {
         usb_deregister(&usb_ipw_driver);
         usb_serial_deregister(&ipw_device);
diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
index e320972cb227..2314c6ae4fc2 100644
--- a/drivers/usb/serial/iuu_phoenix.c
+++ b/drivers/usb/serial/iuu_phoenix.c
@@ -190,10 +190,12 @@ static void iuu_rxcmd(struct urb *urb)
 {
         struct usb_serial_port *port = urb->context;
         int result;
+        int status = urb->status;
+
         dbg("%s - enter", __func__);
 
-        if (urb->status) {
-                dbg("%s - urb->status = %d", __func__, urb->status);
+        if (status) {
+                dbg("%s - status = %d", __func__, status);
                 /* error stop all */
                 return;
         }
@@ -245,10 +247,12 @@ static void iuu_update_status_callback(struct urb *urb)
         struct usb_serial_port *port = urb->context;
         struct iuu_private *priv = usb_get_serial_port_data(port);
         u8 *st;
+        int status = urb->status;
+
         dbg("%s - enter", __func__);
 
-        if (urb->status) {
-                dbg("%s - urb->status = %d", __func__, urb->status);
+        if (status) {
+                dbg("%s - status = %d", __func__, status);
                 /* error stop all */
                 return;
         }
@@ -274,9 +278,9 @@ static void iuu_status_callback(struct urb *urb)
 {
         struct usb_serial_port *port = urb->context;
         int result;
-        dbg("%s - enter", __func__);
+        int status = urb->status;
 
-        dbg("%s - urb->status = %d", __func__, urb->status);
+        dbg("%s - status = %d", __func__, status);
         usb_fill_bulk_urb(port->read_urb, port->serial->dev,
                           usb_rcvbulkpipe(port->serial->dev,
                                           port->bulk_in_endpointAddress),
@@ -618,11 +622,12 @@ static void read_buf_callback(struct urb *urb)
         struct usb_serial_port *port = urb->context;
         unsigned char *data = urb->transfer_buffer;
         struct tty_struct *tty;
-        dbg("%s - urb->status = %d", __func__, urb->status);
+        int status = urb->status;
 
-        if (urb->status) {
-                dbg("%s - urb->status = %d", __func__, urb->status);
-                if (urb->status == -EPROTO) {
+        dbg("%s - status = %d", __func__, status);
+
+        if (status) {
+                if (status == -EPROTO) {
                         /* reschedule needed */
                 }
                 return;
@@ -695,7 +700,7 @@ static void iuu_uart_read_callback(struct urb *urb)
         struct usb_serial_port *port = urb->context;
         struct iuu_private *priv = usb_get_serial_port_data(port);
         unsigned long flags;
-        int status;
+        int status = urb->status;
         int error = 0;
         int len = 0;
         unsigned char *data = urb->transfer_buffer;
@@ -703,8 +708,8 @@ static void iuu_uart_read_callback(struct urb *urb)
 
         dbg("%s - enter", __func__);
 
-        if (urb->status) {
-                dbg("%s - urb->status = %d", __func__, urb->status);
+        if (status) {
+                dbg("%s - status = %d", __func__, status);
                 /* error stop all */
                 return;
         }
@@ -782,12 +787,11 @@ static void read_rxcmd_callback(struct urb *urb)
 {
         struct usb_serial_port *port = urb->context;
         int result;
-        dbg("%s - enter", __func__);
+        int status = urb->status;
 
-        dbg("%s - urb->status = %d", __func__, urb->status);
+        dbg("%s - status = %d", __func__, status);
 
-        if (urb->status) {
-                dbg("%s - urb->status = %d", __func__, urb->status);
+        if (status) {
                 /* error stop all */
                 return;
         }
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index 96a8c7713212..2c20e88a91b3 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -214,6 +214,7 @@ struct moschip_port {
         spinlock_t pool_lock;
         struct urb *write_urb_pool[NUM_URBS];
         char busy[NUM_URBS];
+        bool read_urb_busy;
 };
 
 
@@ -679,26 +680,30 @@ static void mos7840_bulk_in_callback(struct urb *urb)
         struct tty_struct *tty;
         int status = urb->status;
 
-        if (status) {
-                dbg("nonzero read bulk status received: %d", status);
-                return;
-        }
-
         mos7840_port = urb->context;
         if (!mos7840_port) {
                 dbg("%s", "NULL mos7840_port pointer \n");
+                mos7840_port->read_urb_busy = false;
+                return;
+        }
+
+        if (status) {
+                dbg("nonzero read bulk status received: %d", status);
+                mos7840_port->read_urb_busy = false;
                 return;
         }
 
         port = (struct usb_serial_port *)mos7840_port->port;
         if (mos7840_port_paranoia_check(port, __func__)) {
                 dbg("%s", "Port Paranoia failed \n");
+                mos7840_port->read_urb_busy = false;
                 return;
         }
 
         serial = mos7840_get_usb_serial(port, __func__);
         if (!serial) {
                 dbg("%s\n", "Bad serial pointer ");
+                mos7840_port->read_urb_busy = false;
                 return;
         }
 
@@ -725,17 +730,19 @@ static void mos7840_bulk_in_callback(struct urb *urb)
 
         if (!mos7840_port->read_urb) {
                 dbg("%s", "URB KILLED !!!\n");
+                mos7840_port->read_urb_busy = false;
                 return;
         }
 
 
         mos7840_port->read_urb->dev = serial->dev;
 
+        mos7840_port->read_urb_busy = true;
         retval = usb_submit_urb(mos7840_port->read_urb, GFP_ATOMIC);
 
         if (retval) {
-                dbg(" usb_submit_urb(read bulk) failed, retval = %d",
-                 retval);
+                dbg("usb_submit_urb(read bulk) failed, retval = %d", retval);
+                mos7840_port->read_urb_busy = false;
         }
 }
 
@@ -1055,10 +1062,12 @@ static int mos7840_open(struct tty_struct *tty,
 
         dbg("mos7840_open: bulkin endpoint is %d\n",
             port->bulk_in_endpointAddress);
+        mos7840_port->read_urb_busy = true;
         response = usb_submit_urb(mos7840_port->read_urb, GFP_KERNEL);
         if (response) {
                 dev_err(&port->dev, "%s - Error %d submitting control urb\n",
                         __func__, response);
+                mos7840_port->read_urb_busy = false;
         }
 
         /* initialize our wait queues */
@@ -1227,6 +1236,7 @@ static void mos7840_close(struct tty_struct *tty,
                 if (mos7840_port->read_urb) {
                         dbg("%s", "Shutdown bulk read\n");
                         usb_kill_urb(mos7840_port->read_urb);
+                        mos7840_port->read_urb_busy = false;
                 }
                 if ((&mos7840_port->control_urb)) {
                         dbg("%s", "Shutdown control read\n");
@@ -2043,14 +2053,14 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
         Data = 0x0c;
         mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
 
-        if (mos7840_port->read_urb->status != -EINPROGRESS) {
+        if (mos7840_port->read_urb_busy == false) {
                 mos7840_port->read_urb->dev = serial->dev;
-
+                mos7840_port->read_urb_busy = true;
                 status = usb_submit_urb(mos7840_port->read_urb, GFP_ATOMIC);
-
                 if (status) {
-                        dbg(" usb_submit_urb(read bulk) failed, status = %d",
+                        dbg("usb_submit_urb(read bulk) failed, status = %d",
                             status);
+                        mos7840_port->read_urb_busy = false;
                 }
         }
         wake_up(&mos7840_port->delta_msr_wait);
@@ -2117,12 +2127,14 @@ static void mos7840_set_termios(struct tty_struct *tty,
                 return;
         }
 
-        if (mos7840_port->read_urb->status != -EINPROGRESS) {
+        if (mos7840_port->read_urb_busy == false) {
                 mos7840_port->read_urb->dev = serial->dev;
+                mos7840_port->read_urb_busy = true;
                 status = usb_submit_urb(mos7840_port->read_urb, GFP_ATOMIC);
                 if (status) {
-                        dbg(" usb_submit_urb(read bulk) failed, status = %d",
+                        dbg("usb_submit_urb(read bulk) failed, status = %d",
                             status);
+                        mos7840_port->read_urb_busy = false;
                 }
         }
         return;
diff --git a/drivers/usb/serial/opticon.c b/drivers/usb/serial/opticon.c
new file mode 100644
index 000000000000..cea326f1f105
--- /dev/null
+++ b/drivers/usb/serial/opticon.c
@@ -0,0 +1,358 @@
+/*
+ * Opticon USB barcode to serial driver
+ *
+ * Copyright (C) 2008 Greg Kroah-Hartman <gregkh@suse.de>
+ * Copyright (C) 2008 Novell Inc.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License version
+ *      2 as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/module.h>
+#include <linux/usb.h>
+#include <linux/usb/serial.h>
+#include <linux/uaccess.h>
+
+static int debug;
+
+static struct usb_device_id id_table[] = {
+        { USB_DEVICE(0x065a, 0x0009) },
+        { },
+};
+MODULE_DEVICE_TABLE(usb, id_table);
+
+/* This structure holds all of the individual device information */
+struct opticon_private {
+        struct usb_device *udev;
+        struct usb_serial *serial;
+        struct usb_serial_port *port;
+        unsigned char *bulk_in_buffer;
+        struct urb *bulk_read_urb;
+        int buffer_size;
+        u8 bulk_address;
+        spinlock_t lock;        /* protects the following flags */
+        bool throttled;
+        bool actually_throttled;
+        bool rts;
+};
+
+static void opticon_bulk_callback(struct urb *urb)
+{
+        struct opticon_private *priv = urb->context;
+        unsigned char *data = urb->transfer_buffer;
+        struct usb_serial_port *port = priv->port;
+        int status = urb->status;
+        struct tty_struct *tty;
+        int result;
+        int available_room = 0;
+        int data_length;
+
+        dbg("%s - port %d", __func__, port->number);
+
+        switch (status) {
+        case 0:
+                /* success */
+                break;
+        case -ECONNRESET:
+        case -ENOENT:
+        case -ESHUTDOWN:
+                /* this urb is terminated, clean up */
+                dbg("%s - urb shutting down with status: %d",
+                    __func__, status);
+                return;
+        default:
+                dbg("%s - nonzero urb status received: %d",
+                    __func__, status);
+                goto exit;
+        }
+
+        usb_serial_debug_data(debug, &port->dev, __func__, urb->actual_length,
+                              data);
+
+        if (urb->actual_length > 2) {
+                data_length = urb->actual_length - 2;
+
+                /*
+                 * Data from the device comes with a 2 byte header:
+                 *
+                 * <0x00><0x00>data...
+                 *      This is real data to be sent to the tty layer
+                 * <0x00><0x01)level
+                 *      This is a RTS level change, the third byte is the RTS
+                 *      value (0 for low, 1 for high).
+                 */
+                if ((data[0] == 0x00) && (data[1] == 0x00)) {
+                        /* real data, send it to the tty layer */
+                        tty = tty_port_tty_get(&port->port);
+                        if (tty) {
+                                available_room = tty_buffer_request_room(tty,
+                                                                data_length);
+                                if (available_room) {
+                                        tty_insert_flip_string(tty, data,
+                                                               available_room);
+                                        tty_flip_buffer_push(tty);
+                                }
+                                tty_kref_put(tty);
+                        }
+                } else {
+                        if ((data[0] == 0x00) && (data[1] == 0x01)) {
+                                if (data[2] == 0x00)
+                                        priv->rts = false;
+                                else
+                                        priv->rts = true;
+                                /* FIXME change the RTS level */
+                        } else {
+                        dev_dbg(&priv->udev->dev,
+                                "Unknown data packet received from the device:"
+                                " %2x %2x\n",
+                                data[0], data[1]);
+                        }
+                }
+        } else {
+                dev_dbg(&priv->udev->dev,
+                        "Improper ammount of data received from the device, "
+                        "%d bytes", urb->actual_length);
+        }
+
+exit:
+        spin_lock(&priv->lock);
+
+        /* Continue trying to always read if we should */
+        if (!priv->throttled) {
+                usb_fill_bulk_urb(priv->bulk_read_urb, priv->udev,
+                                  usb_rcvbulkpipe(priv->udev,
+                                                  priv->bulk_address),
+                                  priv->bulk_in_buffer, priv->buffer_size,
+                                  opticon_bulk_callback, priv);
+                result = usb_submit_urb(port->read_urb, GFP_ATOMIC);
+                if (result)
+                        dev_err(&port->dev,
+                            "%s - failed resubmitting read urb, error %d\n",
+                                                        __func__, result);
+        } else
+                priv->actually_throttled = true;
+        spin_unlock(&priv->lock);
+}
+
+static int opticon_open(struct tty_struct *tty, struct usb_serial_port *port,
+                        struct file *filp)
+{
+        struct opticon_private *priv = usb_get_serial_data(port->serial);
+        unsigned long flags;
+        int result = 0;
+
+        dbg("%s - port %d", __func__, port->number);
+
+        spin_lock_irqsave(&priv->lock, flags);
+        priv->throttled = false;
+        priv->actually_throttled = false;
+        priv->port = port;
+        spin_unlock_irqrestore(&priv->lock, flags);
+
+        /*
+         * Force low_latency on so that our tty_push actually forces the data
+         * through, otherwise it is scheduled, and with high data rates (like
+         * with OHCI) data can get lost.
+         */
+        if (tty)
+                tty->low_latency = 1;
+
+        /* Start reading from the device */
+        usb_fill_bulk_urb(priv->bulk_read_urb, priv->udev,
+                          usb_rcvbulkpipe(priv->udev,
+                                          priv->bulk_address),
+                          priv->bulk_in_buffer, priv->buffer_size,
+                          opticon_bulk_callback, priv);
+        result = usb_submit_urb(priv->bulk_read_urb, GFP_KERNEL);
+        if (result)
+                dev_err(&port->dev,
+                        "%s - failed resubmitting read urb, error %d\n",
+                        __func__, result);
+        return result;
+}
+
+static void opticon_close(struct tty_struct *tty, struct usb_serial_port *port,
+                          struct file *filp)
+{
+        struct opticon_private *priv = usb_get_serial_data(port->serial);
+
+        dbg("%s - port %d", __func__, port->number);
+
+        /* shutdown our urbs */
+        usb_kill_urb(priv->bulk_read_urb);
+}
+
+static void opticon_throttle(struct tty_struct *tty)
+{
+        struct usb_serial_port *port = tty->driver_data;
+        struct opticon_private *priv = usb_get_serial_data(port->serial);
+        unsigned long flags;
+
+        dbg("%s - port %d", __func__, port->number);
+        spin_lock_irqsave(&priv->lock, flags);
+        priv->throttled = true;
+        spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+
+static void opticon_unthrottle(struct tty_struct *tty)
+{
+        struct usb_serial_port *port = tty->driver_data;
+        struct opticon_private *priv = usb_get_serial_data(port->serial);
+        unsigned long flags;
+        int result;
+
+        dbg("%s - port %d", __func__, port->number);
+
+        spin_lock_irqsave(&priv->lock, flags);
+        priv->throttled = false;
+        priv->actually_throttled = false;
+        spin_unlock_irqrestore(&priv->lock, flags);
+
+        priv->bulk_read_urb->dev = port->serial->dev;
+        result = usb_submit_urb(priv->bulk_read_urb, GFP_ATOMIC);
+        if (result)
+                dev_err(&port->dev,
+                        "%s - failed submitting read urb, error %d\n",
+                                                        __func__, result);
+}
+
+static int opticon_startup(struct usb_serial *serial)
+{
+        struct opticon_private *priv;
+        struct usb_host_interface *intf;
+        int i;
+        int retval = -ENOMEM;
+        bool bulk_in_found = false;
+
+        /* create our private serial structure */
+        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+        if (priv == NULL) {
+                dev_err(&serial->dev->dev, "%s - Out of memory\n", __func__);
+                return -ENOMEM;
+        }
+        spin_lock_init(&priv->lock);
+        priv->serial = serial;
+        priv->port = serial->port[0];
+        priv->udev = serial->dev;
+
+        /* find our bulk endpoint */
+        intf = serial->interface->altsetting;
+        for (i = 0; i < intf->desc.bNumEndpoints; ++i) {
+                struct usb_endpoint_descriptor *endpoint;
+
+                endpoint = &intf->endpoint[i].desc;
+                if (!usb_endpoint_is_bulk_in(endpoint))
+                        continue;
+
+                priv->bulk_read_urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (!priv->bulk_read_urb) {
+                        dev_err(&priv->udev->dev, "out of memory\n");
+                        goto error;
+                }
+
+                priv->buffer_size = le16_to_cpu(endpoint->wMaxPacketSize) * 2;
+                priv->bulk_in_buffer = kmalloc(priv->buffer_size, GFP_KERNEL);
+                if (!priv->bulk_in_buffer) {
+                        dev_err(&priv->udev->dev, "out of memory\n");
+                        goto error;
+                }
+
+                priv->bulk_address = endpoint->bEndpointAddress;
+
+                /* set up our bulk urb */
+                usb_fill_bulk_urb(priv->bulk_read_urb, priv->udev,
+                                  usb_rcvbulkpipe(priv->udev,
+                                                  endpoint->bEndpointAddress),
+                                  priv->bulk_in_buffer, priv->buffer_size,
+                                  opticon_bulk_callback, priv);
+
+                bulk_in_found = true;
+                break;
+                }
+
+        if (!bulk_in_found) {
+                dev_err(&priv->udev->dev,
+                        "Error - the proper endpoints were not found!\n");
+                goto error;
+        }
+
+        usb_set_serial_data(serial, priv);
+        return 0;
+
+error:
+        usb_free_urb(priv->bulk_read_urb);
+        kfree(priv->bulk_in_buffer);
+        kfree(priv);
+        return retval;
+}
+
+static void opticon_shutdown(struct usb_serial *serial)
+{
+        struct opticon_private *priv = usb_get_serial_data(serial);
+
+        dbg("%s", __func__);
+
+        usb_kill_urb(priv->bulk_read_urb);
+        usb_free_urb(priv->bulk_read_urb);
+        kfree(priv->bulk_in_buffer);
+        kfree(priv);
+        usb_set_serial_data(serial, NULL);
+}
+
+
+static struct usb_driver opticon_driver = {
+        .name =         "opticon",
+        .probe =        usb_serial_probe,
+        .disconnect =   usb_serial_disconnect,
+        .id_table =     id_table,
+        .no_dynamic_id =        1,
+};
+
+static struct usb_serial_driver opticon_device = {
+        .driver = {
+                .owner =        THIS_MODULE,
+                .name =         "opticon",
+        },
+        .id_table =             id_table,
+        .usb_driver =           &opticon_driver,
+        .num_ports =            1,
+        .attach =               opticon_startup,
+        .open =                 opticon_open,
+        .close =                opticon_close,
+        .shutdown =             opticon_shutdown,
+        .throttle =             opticon_throttle,
+        .unthrottle =           opticon_unthrottle,
+};
+
+static int __init opticon_init(void)
+{
+        int retval;
+
+        retval = usb_serial_register(&opticon_device);
+        if (retval)
+                return retval;
+        retval = usb_register(&opticon_driver);
+        if (retval)
+                usb_serial_deregister(&opticon_device);
+        return retval;
+}
+
+static void __exit opticon_exit(void)
+{
+        usb_deregister(&opticon_driver);
+        usb_serial_deregister(&opticon_device);
+}
+
+module_init(opticon_init);
+module_exit(opticon_exit);
+MODULE_LICENSE("GPL");
+
+module_param(debug, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(debug, "Debug enabled or not");
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 809697b3c7fc..5ed183477aaf 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -522,9 +522,9 @@ static int debug;
 /* per port private data */
 
 #define N_IN_URB 4
-#define N_OUT_URB 1
+#define N_OUT_URB 4
 #define IN_BUFLEN 4096
-#define OUT_BUFLEN 128
+#define OUT_BUFLEN 4096
 
 struct option_port_private {
         /* Input endpoints and buffer for this port */
@@ -654,10 +654,6 @@ static int option_write(struct tty_struct *tty, struct usb_serial_port *port,
                         usb_unlink_urb(this_urb);
                         continue;
                 }
-                if (this_urb->status != 0)
-                        dbg("usb_write %p failed (err=%d)",
-                                this_urb, this_urb->status);
-
                 dbg("%s: endpoint %d buf %d", __func__,
                         usb_pipeendpoint(this_urb->pipe), i);
 
@@ -669,8 +665,7 @@ static int option_write(struct tty_struct *tty, struct usb_serial_port *port,
                 err = usb_submit_urb(this_urb, GFP_ATOMIC);
                 if (err) {
                         dbg("usb_submit_urb %p (write bulk) failed "
-                                "(%d, has %d)", this_urb,
-                                err, this_urb->status);
+                                "(%d)", this_urb, err);
                         clear_bit(i, &portdata->out_busy);
                         continue;
                 }
diff --git a/drivers/usb/serial/siemens_mpi.c b/drivers/usb/serial/siemens_mpi.c
new file mode 100644
index 000000000000..951ea0c6ba77
--- /dev/null
+++ b/drivers/usb/serial/siemens_mpi.c
@@ -0,0 +1,77 @@
+/*
+ * Siemens USB-MPI Serial USB driver
+ *
+ * Copyright (C) 2005 Thomas Hergenhahn <thomas.hergenhahn@suse.de>
+ * Copyright (C) 2005,2008 Greg Kroah-Hartman <gregkh@suse.de>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License version
+ *      2 as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/tty.h>
+#include <linux/module.h>
+#include <linux/usb.h>
+#include <linux/usb/serial.h>
+
+/* Version Information */
+#define DRIVER_VERSION "Version 0.1 09/26/2005"
+#define DRIVER_AUTHOR "Thomas Hergenhahn@web.de http://libnodave.sf.net"
+#define DRIVER_DESC "Driver for Siemens USB/MPI adapter"
+
+
+static struct usb_device_id id_table[] = {
+        /* Vendor and product id for 6ES7-972-0CB20-0XA0 */
+        { USB_DEVICE(0x908, 0x0004) },
+        { },
+};
+MODULE_DEVICE_TABLE(usb, id_table);
+
+static struct usb_driver siemens_usb_mpi_driver = {
+        .name =         "siemens_mpi",
+        .probe =        usb_serial_probe,
+        .disconnect =   usb_serial_disconnect,
+        .id_table =     id_table,
+};
+
+static struct usb_serial_driver siemens_usb_mpi_device = {
+        .driver = {
+                .owner =        THIS_MODULE,
+                .name =         "siemens_mpi",
+        },
+        .id_table =             id_table,
+        .num_ports =            1,
+};
+
+static int __init siemens_usb_mpi_init(void)
+{
+        int retval;
+
+        retval = usb_serial_register(&siemens_usb_mpi_device);
+        if (retval)
+                goto failed_usb_serial_register;
+        retval = usb_register(&siemens_usb_mpi_driver);
+        if (retval)
+                goto failed_usb_register;
+        printk(KERN_INFO DRIVER_DESC "\n");
+        printk(KERN_INFO DRIVER_VERSION " " DRIVER_AUTHOR "\n");
+        return retval;
+failed_usb_register:
+        usb_serial_deregister(&siemens_usb_mpi_device);
+failed_usb_serial_register:
+        return retval;
+}
+
+static void __exit siemens_usb_mpi_exit(void)
+{
+        usb_deregister(&siemens_usb_mpi_driver);
+        usb_serial_deregister(&siemens_usb_mpi_device);
+}
+
+module_init(siemens_usb_mpi_init);
+module_exit(siemens_usb_mpi_exit);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index a65bc2bd8e71..5e7528cc81a8 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -709,21 +709,20 @@ static void spcp8x5_read_bulk_callback(struct urb *urb)
         unsigned char *data = urb->transfer_buffer;
         unsigned long flags;
         int i;
-        int result;
-        u8 status = 0;
+        int result = urb->status;
+        u8 status;
         char tty_flag;
 
-        dev_dbg(&port->dev, "start, urb->status = %d, "
-                "urb->actual_length = %d\n,", urb->status, urb->actual_length);
+        dev_dbg(&port->dev, "start, result = %d, urb->actual_length = %d\n,",
+                result, urb->actual_length);
 
         /* check the urb status */
-        if (urb->status) {
+        if (result) {
                 if (!port->port.count)
                         return;
-                if (urb->status == -EPROTO) {
+                if (result == -EPROTO) {
                         /* spcp8x5 mysteriously fails with -EPROTO */
                         /* reschedule the read */
-                        urb->status = 0;
                         urb->dev = port->serial->dev;
                         result = usb_submit_urb(urb , GFP_ATOMIC);
                         if (result)
@@ -833,8 +832,9 @@ static void spcp8x5_write_bulk_callback(struct urb *urb)
         struct usb_serial_port *port = urb->context;
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         int result;
+        int status = urb->status;
 
-        switch (urb->status) {
+        switch (status) {
         case 0:
                 /* success */
                 break;
@@ -843,14 +843,14 @@ static void spcp8x5_write_bulk_callback(struct urb *urb)
         case -ESHUTDOWN:
                 /* this urb is terminated, clean up */
                 dev_dbg(&port->dev, "urb shutting down with status: %d\n",
-                        urb->status);
+                        status);
                 priv->write_urb_in_use = 0;
                 return;
         default:
                 /* error in the urb, so we have to resubmit it */
                 dbg("%s - Overflow in write", __func__);
                 dbg("%s - nonzero write bulk status received: %d",
-                        __func__, urb->status);
+                        __func__, status);
                 port->write_urb->transfer_buffer_length = 1;
                 port->write_urb->dev = port->serial->dev;
                 result = usb_submit_urb(port->write_urb, GFP_ATOMIC);
diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c
index fc5d9952b03b..6c9cbb59552a 100644
--- a/drivers/usb/serial/usb_debug.c
+++ b/drivers/usb/serial/usb_debug.c
@@ -31,7 +31,7 @@ static struct usb_driver debug_driver = {
         .no_dynamic_id =        1,
 };
 
-int usb_debug_open(struct tty_struct *tty, struct usb_serial_port *port,
+static int usb_debug_open(struct tty_struct *tty, struct usb_serial_port *port,
                                                         struct file *filp)
 {
         port->bulk_out_size = USB_DEBUG_MAX_PACKET_SIZE;
diff --git a/drivers/usb/storage/Kconfig b/drivers/usb/storage/Kconfig
index c68b738900bd..9df6887b91f6 100644
--- a/drivers/usb/storage/Kconfig
+++ b/drivers/usb/storage/Kconfig
@@ -61,13 +61,6 @@ config USB_STORAGE_ISD200
           - CyQ've CQ8060A CDRW drive
           - Planex eXtreme Drive RX-25HU USB-IDE cable (not model RX-25U)
 
-config USB_STORAGE_DPCM
-        bool "Microtech/ZiO! CompactFlash/SmartMedia support"
-        depends on USB_STORAGE
-        help
-          Say Y here to support the Microtech/ZiO! CompactFlash reader.
-          There is a web page at <http://www.ziocorp.com/products/>.
-
 config USB_STORAGE_USBAT
         bool "USBAT/USBAT02-based storage support"
         depends on USB_STORAGE
@@ -90,12 +83,12 @@ config USB_STORAGE_USBAT
           - Sandisk ImageMate SDDR-05b
 
 config USB_STORAGE_SDDR09
-        bool "SanDisk SDDR-09 (and other SmartMedia) support"
+        bool "SanDisk SDDR-09 (and other SmartMedia, including DPCM) support"
         depends on USB_STORAGE
         help
           Say Y here to include additional code to support the Sandisk SDDR-09
           SmartMedia reader in the USB Mass Storage driver.
-          Also works for the Microtech Zio! SmartMedia reader.
+          Also works for the Microtech Zio! CompactFlash/SmartMedia reader.
 
 config USB_STORAGE_SDDR55
         bool "SanDisk SDDR-55 SmartMedia support"
diff --git a/drivers/usb/storage/Makefile b/drivers/usb/storage/Makefile
index 7f8beb5366ae..b32069313390 100644
--- a/drivers/usb/storage/Makefile
+++ b/drivers/usb/storage/Makefile
@@ -14,7 +14,6 @@ usb-storage-obj-$(CONFIG_USB_STORAGE_USBAT)	+= shuttle_usbat.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_SDDR09)    += sddr09.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_SDDR55)    += sddr55.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_FREECOM)   += freecom.o
-usb-storage-obj-$(CONFIG_USB_STORAGE_DPCM)      += dpcm.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_ISD200)    += isd200.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_DATAFAB)   += datafab.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_JUMPSHOT)  += jumpshot.o
@@ -24,7 +23,7 @@ usb-storage-obj-$(CONFIG_USB_STORAGE_KARMA)	+= karma.o
 usb-storage-obj-$(CONFIG_USB_STORAGE_CYPRESS_ATACB) += cypress_atacb.o
 
 usb-storage-objs :=     scsiglue.o protocol.o transport.o usb.o \
-                        initializers.o sierra_ms.o $(usb-storage-obj-y)
+                        initializers.o sierra_ms.o option_ms.o $(usb-storage-obj-y)
 
 ifneq ($(CONFIG_USB_LIBUSUAL),)
         obj-$(CONFIG_USB)       += libusual.o
diff --git a/drivers/usb/storage/dpcm.c b/drivers/usb/storage/dpcm.c
deleted file mode 100644
index 939923471af4..000000000000
--- a/drivers/usb/storage/dpcm.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Driver for Microtech DPCM-USB CompactFlash/SmartMedia reader
- *
- * DPCM driver v0.1:
- *
- * First release
- *
- * Current development and maintenance by:
- *   (c) 2000 Brian Webb (webbb@earthlink.net)
- *
- * This device contains both a CompactFlash card reader, which
- * uses the Control/Bulk w/o Interrupt protocol and
- * a SmartMedia card reader that uses the same protocol
- * as the SDDR09.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <scsi/scsi.h>
-#include <scsi/scsi_cmnd.h>
-#include <scsi/scsi_device.h>
-
-#include "usb.h"
-#include "transport.h"
-#include "protocol.h"
-#include "debug.h"
-#include "dpcm.h"
-#include "sddr09.h"
-
-/*
- * Transport for the Microtech DPCM-USB
- *
- */
-int dpcm_transport(struct scsi_cmnd *srb, struct us_data *us)
-{
-        int ret;
-
-        if (srb == NULL)
-                return USB_STOR_TRANSPORT_ERROR;
-
-        US_DEBUGP("dpcm_transport: LUN=%d\n", srb->device->lun);
-
-        switch (srb->device->lun) {
-                case 0:
-
-                        /*
-                         * LUN 0 corresponds to the CompactFlash card reader.
-                         */
-                        ret = usb_stor_CB_transport(srb, us);
-                        break;
-
-#ifdef CONFIG_USB_STORAGE_SDDR09
-                case 1:
-
-                        /*
-                         * LUN 1 corresponds to the SmartMedia card reader.
-                         */
-
-                        /*
-                         * Set the LUN to 0 (just in case).
-                         */
-                        srb->device->lun = 0; us->srb->device->lun = 0;
-                        ret = sddr09_transport(srb, us);
-                        srb->device->lun = 1; us->srb->device->lun = 1;
-                        break;
-
-#endif
-
-                default:
-                        US_DEBUGP("dpcm_transport: Invalid LUN %d\n", srb->device->lun);
-                        ret = USB_STOR_TRANSPORT_ERROR;
-                        break;
-        }
-        return ret;
-}
diff --git a/drivers/usb/storage/dpcm.h b/drivers/usb/storage/dpcm.h
deleted file mode 100644
index e7b7b0f120d7..000000000000
--- a/drivers/usb/storage/dpcm.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Driver for Microtech DPCM-USB CompactFlash/SmartMedia reader
- *
- * DPCM driver v0.1:
- *
- * First release
- *
- * Current development and maintenance by:
- *   (c) 2000 Brian Webb (webbb@earthlink.net)
- *
- * See dpcm.c for more explanation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _MICROTECH_DPCM_USB_H
-#define _MICROTECH_DPCM_USB_H
-
-extern int dpcm_transport(struct scsi_cmnd *srb, struct us_data *us);
-
-#endif
diff --git a/drivers/usb/storage/libusual.c b/drivers/usb/storage/libusual.c
index d617e8ae6b00..f970b27ba308 100644
--- a/drivers/usb/storage/libusual.c
+++ b/drivers/usb/storage/libusual.c
@@ -46,6 +46,12 @@ static int usu_probe_thread(void *arg);
 { USB_DEVICE_VER(id_vendor, id_product, bcdDeviceMin,bcdDeviceMax), \
   .driver_info = (flags)|(USB_US_TYPE_STOR<<24) }
 
+#define COMPLIANT_DEV(id_vendor, id_product, bcdDeviceMin, bcdDeviceMax, \
+                    vendorName, productName, useProtocol, useTransport, \
+                    initFunction, flags) \
+{ USB_DEVICE_VER(id_vendor, id_product, bcdDeviceMin, bcdDeviceMax), \
+  .driver_info = (flags) }
+
 #define USUAL_DEV(useProto, useTrans, useType) \
 { USB_INTERFACE_INFO(USB_CLASS_MASS_STORAGE, useProto, useTrans), \
   .driver_info = ((useType)<<24) }
@@ -57,6 +63,7 @@ struct usb_device_id storage_usb_ids [] = {
 
 #undef USUAL_DEV
 #undef UNUSUAL_DEV
+#undef COMPLIANT_DEV
 
 MODULE_DEVICE_TABLE(usb, storage_usb_ids);
 EXPORT_SYMBOL_GPL(storage_usb_ids);
diff --git a/drivers/usb/storage/option_ms.c b/drivers/usb/storage/option_ms.c
new file mode 100644
index 000000000000..353f922939a4
--- /dev/null
+++ b/drivers/usb/storage/option_ms.c
@@ -0,0 +1,147 @@
+/*
+ * Driver for Option High Speed Mobile Devices.
+ *
+ *   (c) 2008 Dan Williams <dcbw@redhat.com>
+ *
+ * Inspiration taken from sierra_ms.c by Kevin Lloyd <klloyd@sierrawireless.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/usb.h>
+
+#include "usb.h"
+#include "transport.h"
+#include "option_ms.h"
+#include "debug.h"
+
+#define ZCD_FORCE_MODEM                 0x01
+#define ZCD_ALLOW_MS                    0x02
+
+static unsigned int option_zero_cd = ZCD_FORCE_MODEM;
+module_param(option_zero_cd, uint, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(option_zero_cd, "ZeroCD mode (1=Force Modem (default),"
+                 " 2=Allow CD-Rom");
+
+#define RESPONSE_LEN 1024
+
+static int option_rezero(struct us_data *us, int ep_in, int ep_out)
+{
+        const unsigned char rezero_msg[] = {
+          0x55, 0x53, 0x42, 0x43, 0x78, 0x56, 0x34, 0x12,
+          0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x06, 0x01,
+          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        };
+        char *buffer;
+        int result;
+
+        US_DEBUGP("Option MS: %s", "DEVICE MODE SWITCH\n");
+
+        buffer = kzalloc(RESPONSE_LEN, GFP_KERNEL);
+        if (buffer == NULL)
+                return USB_STOR_TRANSPORT_ERROR;
+
+        memcpy(buffer, rezero_msg, sizeof (rezero_msg));
+        result = usb_stor_bulk_transfer_buf(us,
+                        usb_sndbulkpipe(us->pusb_dev, ep_out),
+                        buffer, sizeof (rezero_msg), NULL);
+        if (result != USB_STOR_XFER_GOOD) {
+                result = USB_STOR_XFER_ERROR;
+                goto out;
+        }
+
+        /* Some of the devices need to be asked for a response, but we don't
+         * care what that response is.
+         */
+        result = usb_stor_bulk_transfer_buf(us,
+                        usb_sndbulkpipe(us->pusb_dev, ep_out),
+                        buffer, RESPONSE_LEN, NULL);
+        result = USB_STOR_XFER_GOOD;
+
+out:
+        kfree(buffer);
+        return result;
+}
+
+int option_ms_init(struct us_data *us)
+{
+        struct usb_device *udev;
+        struct usb_interface *intf;
+        struct usb_host_interface *iface_desc;
+        struct usb_endpoint_descriptor *endpoint = NULL;
+        u8 ep_in = 0, ep_out = 0;
+        int ep_in_size = 0, ep_out_size = 0;
+        int i, result;
+
+        udev = us->pusb_dev;
+        intf = us->pusb_intf;
+
+        /* Ensure it's really a ZeroCD device; devices that are already
+         * in modem mode return 0xFF for class, subclass, and protocol.
+         */
+        if (udev->descriptor.bDeviceClass != 0 ||
+            udev->descriptor.bDeviceSubClass != 0 ||
+            udev->descriptor.bDeviceProtocol != 0)
+                return USB_STOR_TRANSPORT_GOOD;
+
+        US_DEBUGP("Option MS: option_ms_init called\n");
+
+        /* Find the right mass storage interface */
+        iface_desc = intf->cur_altsetting;
+        if (iface_desc->desc.bInterfaceClass != 0x8 ||
+            iface_desc->desc.bInterfaceSubClass != 0x6 ||
+            iface_desc->desc.bInterfaceProtocol != 0x50) {
+                US_DEBUGP("Option MS: mass storage interface not found, no action "
+                          "required\n");
+                return USB_STOR_TRANSPORT_GOOD;
+        }
+
+        /* Find the mass storage bulk endpoints */
+        for (i = 0; i < iface_desc->desc.bNumEndpoints && (!ep_in_size || !ep_out_size); ++i) {
+                endpoint = &iface_desc->endpoint[i].desc;
+
+                if (usb_endpoint_is_bulk_in(endpoint)) {
+                        ep_in = usb_endpoint_num(endpoint);
+                        ep_in_size = le16_to_cpu(endpoint->wMaxPacketSize);
+                } else if (usb_endpoint_is_bulk_out(endpoint)) {
+                        ep_out = usb_endpoint_num(endpoint);
+                        ep_out_size = le16_to_cpu(endpoint->wMaxPacketSize);
+                }
+        }
+
+        /* Can't find the mass storage endpoints */
+        if (!ep_in_size || !ep_out_size) {
+                US_DEBUGP("Option MS: mass storage endpoints not found, no action "
+                          "required\n");
+                return USB_STOR_TRANSPORT_GOOD;
+        }
+
+        /* Force Modem mode */
+        if (option_zero_cd == ZCD_FORCE_MODEM) {
+                US_DEBUGP("Option MS: %s", "Forcing Modem Mode\n");
+                result = option_rezero(us, ep_in, ep_out);
+                if (result != USB_STOR_XFER_GOOD)
+                        US_DEBUGP("Option MS: Failed to switch to modem mode.\n");
+                return -EIO;
+        } else if (option_zero_cd == ZCD_ALLOW_MS) {
+                /* Allow Mass Storage mode (keep CD-Rom) */
+                US_DEBUGP("Option MS: %s", "Allowing Mass Storage Mode if device"
+                          " requests it\n");
+        }
+
+        return USB_STOR_TRANSPORT_GOOD;
+}
+
diff --git a/drivers/usb/storage/option_ms.h b/drivers/usb/storage/option_ms.h
new file mode 100644
index 000000000000..b6e448cab039
--- /dev/null
+++ b/drivers/usb/storage/option_ms.h
@@ -0,0 +1,4 @@
+#ifndef _OPTION_MS_H_
+#define _OPTION_MS_H_
+extern int option_ms_init(struct us_data *us);
+#endif
diff --git a/drivers/usb/storage/protocol.c b/drivers/usb/storage/protocol.c
index 3b3357e20ea7..be441d84bc64 100644
--- a/drivers/usb/storage/protocol.c
+++ b/drivers/usb/storage/protocol.c
@@ -56,9 +56,9 @@
  * Protocol routines
  ***********************************************************************/
 
-void usb_stor_qic157_command(struct scsi_cmnd *srb, struct us_data *us)
+void usb_stor_pad12_command(struct scsi_cmnd *srb, struct us_data *us)
 {
-        /* Pad the ATAPI command with zeros 
+        /* Pad the SCSI command with zeros out to 12 bytes
          *
          * NOTE: This only works because a scsi_cmnd struct field contains
          * a unsigned char cmnd[16], so we know we have storage available
@@ -73,26 +73,6 @@ void usb_stor_qic157_command(struct scsi_cmnd *srb, struct us_data *us)
         usb_stor_invoke_transport(srb, us);
 }
 
-void usb_stor_ATAPI_command(struct scsi_cmnd *srb, struct us_data *us)
-{
-        /* Pad the ATAPI command with zeros 
-         *
-         * NOTE: This only works because a scsi_cmnd struct field contains
-         * a unsigned char cmnd[16], so we know we have storage available
-         */
-
-        /* Pad the ATAPI command with zeros */
-        for (; srb->cmd_len<12; srb->cmd_len++)
-                srb->cmnd[srb->cmd_len] = 0;
-
-        /* set command length to 12 bytes */
-        srb->cmd_len = 12;
-
-        /* send the command to the transport layer */
-        usb_stor_invoke_transport(srb, us);
-}
-
-
 void usb_stor_ufi_command(struct scsi_cmnd *srb, struct us_data *us)
 {
         /* fix some commands -- this is a form of mode translation
diff --git a/drivers/usb/storage/protocol.h b/drivers/usb/storage/protocol.h
index 487056ffb516..ffc3e2af0156 100644
--- a/drivers/usb/storage/protocol.h
+++ b/drivers/usb/storage/protocol.h
@@ -40,8 +40,7 @@
 #define _PROTOCOL_H_
 
 /* Protocol handling routines */
-extern void usb_stor_ATAPI_command(struct scsi_cmnd*, struct us_data*);
-extern void usb_stor_qic157_command(struct scsi_cmnd*, struct us_data*);
+extern void usb_stor_pad12_command(struct scsi_cmnd*, struct us_data*);
 extern void usb_stor_ufi_command(struct scsi_cmnd*, struct us_data*);
 extern void usb_stor_transparent_scsi_command(struct scsi_cmnd*,
                 struct us_data*);
diff --git a/drivers/usb/storage/scsiglue.c b/drivers/usb/storage/scsiglue.c
index 09779f6a8179..2a42b862aa9f 100644
--- a/drivers/usb/storage/scsiglue.c
+++ b/drivers/usb/storage/scsiglue.c
@@ -59,6 +59,13 @@
 #include "transport.h"
 #include "protocol.h"
 
+/* Vendor IDs for companies that seem to include the READ CAPACITY bug
+ * in all their devices
+ */
+#define VENDOR_ID_NOKIA         0x0421
+#define VENDOR_ID_NIKON         0x04b0
+#define VENDOR_ID_MOTOROLA      0x22b8
+
 /***********************************************************************
  * Host functions 
  ***********************************************************************/
@@ -129,11 +136,35 @@ static int slave_configure(struct scsi_device *sdev)
                                               max_sectors);
         }
 
+        /* Some USB host controllers can't do DMA; they have to use PIO.
+         * They indicate this by setting their dma_mask to NULL.  For
+         * such controllers we need to make sure the block layer sets
+         * up bounce buffers in addressable memory.
+         */
+        if (!us->pusb_dev->bus->controller->dma_mask)
+                blk_queue_bounce_limit(sdev->request_queue, BLK_BOUNCE_HIGH);
+
         /* We can't put these settings in slave_alloc() because that gets
          * called before the device type is known.  Consequently these
          * settings can't be overridden via the scsi devinfo mechanism. */
         if (sdev->type == TYPE_DISK) {
 
+                /* Some vendors seem to put the READ CAPACITY bug into
+                 * all their devices -- primarily makers of cell phones
+                 * and digital cameras.  Since these devices always use
+                 * flash media and can be expected to have an even number
+                 * of sectors, we will always enable the CAPACITY_HEURISTICS
+                 * flag unless told otherwise. */
+                switch (le16_to_cpu(us->pusb_dev->descriptor.idVendor)) {
+                case VENDOR_ID_NOKIA:
+                case VENDOR_ID_NIKON:
+                case VENDOR_ID_MOTOROLA:
+                        if (!(us->fflags & (US_FL_FIX_CAPACITY |
+                                        US_FL_CAPACITY_OK)))
+                                us->fflags |= US_FL_CAPACITY_HEURISTICS;
+                        break;
+                }
+
                 /* Disk-type devices use MODE SENSE(6) if the protocol
                  * (SubClass) is Transparent SCSI, otherwise they use
                  * MODE SENSE(10). */
@@ -170,6 +201,10 @@ static int slave_configure(struct scsi_device *sdev)
                 if (us->fflags & US_FL_CAPACITY_HEURISTICS)
                         sdev->guess_capacity = 1;
 
+                /* assume SPC3 or latter devices support sense size > 18 */
+                if (sdev->scsi_level > SCSI_SPC_2)
+                        us->fflags |= US_FL_SANE_SENSE;
+
                 /* Some devices report a SCSI revision level above 2 but are
                  * unable to handle the REPORT LUNS command (for which
                  * support is mandatory at level 3).  Since we already have
@@ -196,6 +231,14 @@ static int slave_configure(struct scsi_device *sdev)
                  * sector in a larger then 1 sector read, since the performance
                  * impact is negible we set this flag for all USB disks */
                 sdev->last_sector_bug = 1;
+
+                /* Enable last-sector hacks for single-target devices using
+                 * the Bulk-only transport, unless we already know the
+                 * capacity will be decremented or is correct. */
+                if (!(us->fflags & (US_FL_FIX_CAPACITY | US_FL_CAPACITY_OK |
+                                        US_FL_SCM_MULT_TARG)) &&
+                                us->protocol == US_PR_BULK)
+                        us->use_last_sector_hacks = 1;
         } else {
 
                 /* Non-disk-type devices don't need to blacklist any pages
diff --git a/drivers/usb/storage/sddr09.c b/drivers/usb/storage/sddr09.c
index c5a54b872c24..531ae5c5abf3 100644
--- a/drivers/usb/storage/sddr09.c
+++ b/drivers/usb/storage/sddr09.c
@@ -45,6 +45,7 @@
 
 #include <scsi/scsi.h>
 #include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_device.h>
 
 #include "usb.h"
 #include "transport.h"
@@ -1446,6 +1447,48 @@ usb_stor_sddr09_dpcm_init(struct us_data *us) {
 }
 
 /*
+ * Transport for the Microtech DPCM-USB
+ */
+int dpcm_transport(struct scsi_cmnd *srb, struct us_data *us)
+{
+        int ret;
+
+        US_DEBUGP("dpcm_transport: LUN=%d\n", srb->device->lun);
+
+        switch (srb->device->lun) {
+        case 0:
+
+                /*
+                 * LUN 0 corresponds to the CompactFlash card reader.
+                 */
+                ret = usb_stor_CB_transport(srb, us);
+                break;
+
+        case 1:
+
+                /*
+                 * LUN 1 corresponds to the SmartMedia card reader.
+                 */
+
+                /*
+                 * Set the LUN to 0 (just in case).
+                 */
+                srb->device->lun = 0;
+                ret = sddr09_transport(srb, us);
+                srb->device->lun = 1;
+                break;
+
+        default:
+                US_DEBUGP("dpcm_transport: Invalid LUN %d\n",
+                                srb->device->lun);
+                ret = USB_STOR_TRANSPORT_ERROR;
+                break;
+        }
+        return ret;
+}
+
+
+/*
  * Transport for the Sandisk SDDR-09
  */
 int sddr09_transport(struct scsi_cmnd *srb, struct us_data *us)
diff --git a/drivers/usb/storage/sddr09.h b/drivers/usb/storage/sddr09.h
index e50033ad7b19..b701172e12e3 100644
--- a/drivers/usb/storage/sddr09.h
+++ b/drivers/usb/storage/sddr09.h
@@ -28,8 +28,11 @@
 /* Sandisk SDDR-09 stuff */
 
 extern int sddr09_transport(struct scsi_cmnd *srb, struct us_data *us);
+extern int usb_stor_sddr09_init(struct us_data *us);
+
+/* Microtech DPCM-USB stuff */
 
+extern int dpcm_transport(struct scsi_cmnd *srb, struct us_data *us);
 extern int usb_stor_sddr09_dpcm_init(struct us_data *us);
-extern int usb_stor_sddr09_init(struct us_data *us);
 
 #endif
diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c
index 79108d5d3171..1d5438e6363b 100644
--- a/drivers/usb/storage/transport.c
+++ b/drivers/usb/storage/transport.c
@@ -57,6 +57,9 @@
 #include "scsiglue.h"
 #include "debug.h"
 
+#include <linux/blkdev.h>
+#include "../../scsi/sd.h"
+
 
 /***********************************************************************
  * Data transfer routines
@@ -511,6 +514,110 @@ int usb_stor_bulk_transfer_sg(struct us_data* us, unsigned int pipe,
  * Transport routines
  ***********************************************************************/
 
+/* There are so many devices that report the capacity incorrectly,
+ * this routine was written to counteract some of the resulting
+ * problems.
+ */
+static void last_sector_hacks(struct us_data *us, struct scsi_cmnd *srb)
+{
+        struct gendisk *disk;
+        struct scsi_disk *sdkp;
+        u32 sector;
+
+        /* To Report "Medium Error: Record Not Found */
+        static unsigned char record_not_found[18] = {
+                [0]     = 0x70,                 /* current error */
+                [2]     = MEDIUM_ERROR,         /* = 0x03 */
+                [7]     = 0x0a,                 /* additional length */
+                [12]    = 0x14                  /* Record Not Found */
+        };
+
+        /* If last-sector problems can't occur, whether because the
+         * capacity was already decremented or because the device is
+         * known to report the correct capacity, then we don't need
+         * to do anything.
+         */
+        if (!us->use_last_sector_hacks)
+                return;
+
+        /* Was this command a READ(10) or a WRITE(10)? */
+        if (srb->cmnd[0] != READ_10 && srb->cmnd[0] != WRITE_10)
+                goto done;
+
+        /* Did this command access the last sector? */
+        sector = (srb->cmnd[2] << 24) | (srb->cmnd[3] << 16) |
+                        (srb->cmnd[4] << 8) | (srb->cmnd[5]);
+        disk = srb->request->rq_disk;
+        if (!disk)
+                goto done;
+        sdkp = scsi_disk(disk);
+        if (!sdkp)
+                goto done;
+        if (sector + 1 != sdkp->capacity)
+                goto done;
+
+        if (srb->result == SAM_STAT_GOOD && scsi_get_resid(srb) == 0) {
+
+                /* The command succeeded.  If the capacity is odd
+                 * (i.e., if the sector number is even) then the
+                 * "always-even" heuristic would be wrong for this
+                 * device.  Issue a WARN() so that the kerneloops.org
+                 * project will be notified and we will then know to
+                 * mark the device with a CAPACITY_OK flag.  Hopefully
+                 * this will occur for only a few devices.
+                 *
+                 * Use the sign of us->last_sector_hacks to tell whether
+                 * the warning has already been issued; we don't need
+                 * more than one warning per device.
+                 */
+                if (!(sector & 1) && us->use_last_sector_hacks > 0) {
+                        unsigned vid = le16_to_cpu(
+                                        us->pusb_dev->descriptor.idVendor);
+                        unsigned pid = le16_to_cpu(
+                                        us->pusb_dev->descriptor.idProduct);
+                        unsigned rev = le16_to_cpu(
+                                        us->pusb_dev->descriptor.bcdDevice);
+
+                        WARN(1, "%s: Successful last sector success at %u, "
+                                        "device %04x:%04x:%04x\n",
+                                        sdkp->disk->disk_name, sector,
+                                        vid, pid, rev);
+                        us->use_last_sector_hacks = -1;
+                }
+
+        } else {
+                /* The command failed.  Allow up to 3 retries in case this
+                 * is some normal sort of failure.  After that, assume the
+                 * capacity is wrong and we're trying to access the sector
+                 * beyond the end.  Replace the result code and sense data
+                 * with values that will cause the SCSI core to fail the
+                 * command immediately, instead of going into an infinite
+                 * (or even just a very long) retry loop.
+                 */
+                if (++us->last_sector_retries < 3)
+                        return;
+                srb->result = SAM_STAT_CHECK_CONDITION;
+                memcpy(srb->sense_buffer, record_not_found,
+                                sizeof(record_not_found));
+
+                /* In theory we might want to issue a WARN() here if the
+                 * capacity is even, since it could indicate the device
+                 * has the READ CAPACITY bug _and_ the real capacity is
+                 * odd.  But it could also indicate that the device
+                 * simply can't access its last sector, a failure mode
+                 * which is surprisingly common.  So no warning.
+                 */
+        }
+
+ done:
+        /* Don't reset the retry counter for TEST UNIT READY commands,
+         * because they get issued after device resets which might be
+         * caused by a failed last-sector access.
+         */
+        if (srb->cmnd[0] != TEST_UNIT_READY)
+                us->last_sector_retries = 0;
+}
+
 /* Invoke the transport and basic error-handling/recovery methods
  *
  * This is used by the protocol layers to actually send the message to
@@ -544,6 +651,7 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
         /* if the transport provided its own sense data, don't auto-sense */
         if (result == USB_STOR_TRANSPORT_NO_SENSE) {
                 srb->result = SAM_STAT_CHECK_CONDITION;
+                last_sector_hacks(us, srb);
                 return;
         }
 
@@ -579,6 +687,20 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
         }
 
         /*
+         * Determine if this device is SAT by seeing if the
+         * command executed successfully.  Otherwise we'll have
+         * to wait for at least one CHECK_CONDITION to determine
+         * SANE_SENSE support
+         */
+        if ((srb->cmnd[0] == ATA_16 || srb->cmnd[0] == ATA_12) &&
+            result == USB_STOR_TRANSPORT_GOOD &&
+            !(us->fflags & US_FL_SANE_SENSE) &&
+            !(srb->cmnd[2] & 0x20)) {
+                US_DEBUGP("-- SAT supported, increasing auto-sense\n");
+                us->fflags |= US_FL_SANE_SENSE;
+        }
+
+        /*
          * A short transfer on a command where we don't expect it
          * is unusual, but it doesn't mean we need to auto-sense.
          */
@@ -595,10 +717,15 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
         if (need_auto_sense) {
                 int temp_result;
                 struct scsi_eh_save ses;
+                int sense_size = US_SENSE_SIZE;
+
+                /* device supports and needs bigger sense buffer */
+                if (us->fflags & US_FL_SANE_SENSE)
+                        sense_size = ~0;
 
                 US_DEBUGP("Issuing auto-REQUEST_SENSE\n");
 
-                scsi_eh_prep_cmnd(srb, &ses, NULL, 0, US_SENSE_SIZE);
+                scsi_eh_prep_cmnd(srb, &ses, NULL, 0, sense_size);
 
                 /* FIXME: we must do the protocol translation here */
                 if (us->subclass == US_SC_RBC || us->subclass == US_SC_SCSI ||
@@ -632,6 +759,25 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
                         return;
                 }
 
+                /* If the sense data returned is larger than 18-bytes then we
+                 * assume this device supports requesting more in the future.
+                 * The response code must be 70h through 73h inclusive.
+                 */
+                if (srb->sense_buffer[7] > (US_SENSE_SIZE - 8) &&
+                    !(us->fflags & US_FL_SANE_SENSE) &&
+                    (srb->sense_buffer[0] & 0x7C) == 0x70) {
+                        US_DEBUGP("-- SANE_SENSE support enabled\n");
+                        us->fflags |= US_FL_SANE_SENSE;
+
+                        /* Indicate to the user that we truncated their sense
+                         * because we didn't know it supported larger sense.
+                         */
+                        US_DEBUGP("-- Sense data truncated to %i from %i\n",
+                                  US_SENSE_SIZE,
+                                  srb->sense_buffer[7] + 8);
+                        srb->sense_buffer[7] = (US_SENSE_SIZE - 8);
+                }
+
                 US_DEBUGP("-- Result from auto-sense is %d\n", temp_result);
                 US_DEBUGP("-- code: 0x%x, key: 0x%x, ASC: 0x%x, ASCQ: 0x%x\n",
                           srb->sense_buffer[0],
@@ -667,6 +813,7 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
                         scsi_bufflen(srb) - scsi_get_resid(srb) < srb->underflow)
                 srb->result = (DID_ERROR << 16) | (SUGGEST_RETRY << 24);
 
+        last_sector_hacks(us, srb);
         return;
 
         /* Error and abort processing: try to resynchronize with the device
@@ -694,6 +841,7 @@ void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
                 us->transport_reset(us);
         }
         clear_bit(US_FLIDX_RESETTING, &us->dflags);
+        last_sector_hacks(us, srb);
 }
 
 /* Stop the current URB transfer */
@@ -718,10 +866,10 @@ void usb_stor_stop_transport(struct us_data *us)
 }
 
 /*
- * Control/Bulk/Interrupt transport
+ * Control/Bulk and Control/Bulk/Interrupt transport
  */
 
-int usb_stor_CBI_transport(struct scsi_cmnd *srb, struct us_data *us)
+int usb_stor_CB_transport(struct scsi_cmnd *srb, struct us_data *us)
 {
         unsigned int transfer_length = scsi_bufflen(srb);
         unsigned int pipe = 0;
@@ -763,6 +911,13 @@ int usb_stor_CBI_transport(struct scsi_cmnd *srb, struct us_data *us)
         }
 
         /* STATUS STAGE */
+
+        /* NOTE: CB does not have a status stage.  Silly, I know.  So
+         * we have to catch this at a higher level.
+         */
+        if (us->protocol != US_PR_CBI)
+                return USB_STOR_TRANSPORT_GOOD;
+
         result = usb_stor_intr_transfer(us, us->iobuf, 2);
         US_DEBUGP("Got interrupt data (0x%x, 0x%x)\n", 
                         us->iobuf[0], us->iobuf[1]);
@@ -817,56 +972,6 @@ int usb_stor_CBI_transport(struct scsi_cmnd *srb, struct us_data *us)
 }
 
 /*
- * Control/Bulk transport
- */
-int usb_stor_CB_transport(struct scsi_cmnd *srb, struct us_data *us)
-{
-        unsigned int transfer_length = scsi_bufflen(srb);
-        int result;
-
-        /* COMMAND STAGE */
-        /* let's send the command via the control pipe */
-        result = usb_stor_ctrl_transfer(us, us->send_ctrl_pipe,
-                                      US_CBI_ADSC, 
-                                      USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, 
-                                      us->ifnum, srb->cmnd, srb->cmd_len);
-
-        /* check the return code for the command */
-        US_DEBUGP("Call to usb_stor_ctrl_transfer() returned %d\n", result);
-
-        /* if we stalled the command, it means command failed */
-        if (result == USB_STOR_XFER_STALLED) {
-                return USB_STOR_TRANSPORT_FAILED;
-        }
-
-        /* Uh oh... serious problem here */
-        if (result != USB_STOR_XFER_GOOD) {
-                return USB_STOR_TRANSPORT_ERROR;
-        }
-
-        /* DATA STAGE */
-        /* transfer the data payload for this command, if one exists*/
-        if (transfer_length) {
-                unsigned int pipe = srb->sc_data_direction == DMA_FROM_DEVICE ? 
-                                us->recv_bulk_pipe : us->send_bulk_pipe;
-                result = usb_stor_bulk_srb(us, pipe, srb);
-                US_DEBUGP("CB data stage result is 0x%x\n", result);
-
-                /* if we stalled the data transfer it means command failed */
-                if (result == USB_STOR_XFER_STALLED)
-                        return USB_STOR_TRANSPORT_FAILED;
-                if (result > USB_STOR_XFER_STALLED)
-                        return USB_STOR_TRANSPORT_ERROR;
-        }
-
-        /* STATUS STAGE */
-        /* NOTE: CB does not have a status stage.  Silly, I know.  So
-         * we have to catch this at a higher level.
-         */
-        return USB_STOR_TRANSPORT_GOOD;
-}
-
-/*
  * Bulk only transport
  */
 
@@ -1173,10 +1278,9 @@ int usb_stor_Bulk_reset(struct us_data *us)
  */
 int usb_stor_port_reset(struct us_data *us)
 {
-        int result, rc_lock;
+        int result;
 
-        result = rc_lock =
-                usb_lock_device_for_reset(us->pusb_dev, us->pusb_intf);
+        result = usb_lock_device_for_reset(us->pusb_dev, us->pusb_intf);
         if (result < 0)
                 US_DEBUGP("unable to lock device for reset: %d\n", result);
         else {
@@ -1189,8 +1293,7 @@ int usb_stor_port_reset(struct us_data *us)
                         US_DEBUGP("usb_reset_device returns %d\n",
                                         result);
                 }
-                if (rc_lock)
-                        usb_unlock_device(us->pusb_dev);
+                usb_unlock_device(us->pusb_dev);
         }
         return result;
 }
diff --git a/drivers/usb/storage/transport.h b/drivers/usb/storage/transport.h
index e70b88182f0e..242ff5e791a5 100644
--- a/drivers/usb/storage/transport.h
+++ b/drivers/usb/storage/transport.h
@@ -113,8 +113,6 @@ struct bulk_cs_wrap {
 
 #define US_CBI_ADSC             0
 
-extern int usb_stor_CBI_transport(struct scsi_cmnd *, struct us_data*);
-
 extern int usb_stor_CB_transport(struct scsi_cmnd *, struct us_data*);
 extern int usb_stor_CB_reset(struct us_data*);
 
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
index bfcc1fe82518..a7f9513fa19d 100644
--- a/drivers/usb/storage/unusual_devs.h
+++ b/drivers/usb/storage/unusual_devs.h
@@ -27,7 +27,8 @@
 
 /* IMPORTANT NOTE: This file must be included in another file which does
  * the following thing for it to work:
- * The macro UNUSUAL_DEV() must be defined before this file is included
+ * The UNUSUAL_DEV, COMPLIANT_DEV, and USUAL_DEV macros must be defined
+ * before this file is included.
  */
 
 /* If you edit this file, please try to keep it sorted first by VendorID,
@@ -46,6 +47,12 @@
  * <usb-storage@lists.one-eyed-alien.net>
  */
 
+/* Note: If you add an entry only in order to set the CAPACITY_OK flag,
+ * use the COMPLIANT_DEV macro instead of UNUSUAL_DEV.  This is
+ * because such entries mark devices which actually work correctly,
+ * as opposed to devices that do something strangely or wrongly.
+ */
+
 /* patch submitted by Vivian Bregier <Vivian.Bregier@imag.fr>
  */
 UNUSUAL_DEV(  0x03eb, 0x2002, 0x0100, 0x0100,
@@ -85,6 +92,13 @@ UNUSUAL_DEV(  0x03f0, 0x0307, 0x0001, 0x0001,
                 US_SC_8070, US_PR_USBAT, init_usbat_cd, 0),
 #endif
 
+/* Reported by Ben Efros <ben@pc-doctor.com> */
+UNUSUAL_DEV(  0x03f0, 0x070c, 0x0000, 0x0000,
+                "HP",
+                "Personal Media Drive",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SANE_SENSE ),
+
 /* Reported by Grant Grundler <grundler@parisc-linux.org>
  * HP r707 camera in "Disk" mode with 2.00.23 or 2.00.24 firmware.
  */
@@ -160,34 +174,6 @@ UNUSUAL_DEV(  0x0421, 0x0019, 0x0592, 0x0592,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_MAX_SECTORS_64 ),
 
-/* Reported by Filip Joelsson <filip@blueturtle.nu> */
-UNUSUAL_DEV(  0x0421, 0x005d, 0x0001, 0x0600,
-                "Nokia",
-                "Nokia 3110c",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
-/* Reported by Ozan Sener <themgzzy@gmail.com> */
-UNUSUAL_DEV(  0x0421, 0x0060, 0x0551, 0x0551,
-                "Nokia",
-                "3500c",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
-/* Reported by CSECSY Laszlo <boobaa@frugalware.org> */
-UNUSUAL_DEV(  0x0421, 0x0063, 0x0001, 0x0601,
-                "Nokia",
-                "Nokia 3109c",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
-/* Patch for Nokia 5310 capacity */
-UNUSUAL_DEV(  0x0421, 0x006a, 0x0000, 0x0701,
-                "Nokia",
-                "5310",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
 /* Reported by Mario Rettig <mariorettig@web.de> */
 UNUSUAL_DEV(  0x0421, 0x042e, 0x0100, 0x0100,
                 "Nokia",
@@ -253,35 +239,6 @@ UNUSUAL_DEV(  0x0421, 0x0495, 0x0370, 0x0370,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_MAX_SECTORS_64 ),
 
-/* Reported by Cedric Godin <cedric@belbone.be> */
-UNUSUAL_DEV(  0x0421, 0x04b9, 0x0500, 0x0551,
-                "Nokia",
-                "5300",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
-/* Reported by Richard Nauber <RichardNauber@web.de> */
-UNUSUAL_DEV(  0x0421, 0x04fa, 0x0550, 0x0660,
-                "Nokia",
-                "6300",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY ),
-
-/* Patch for Nokia 5310 capacity */
-UNUSUAL_DEV(  0x0421, 0x006a, 0x0000, 0x0591,
-        "Nokia",
-        "5310",
-        US_SC_DEVICE, US_PR_DEVICE, NULL,
-        US_FL_FIX_CAPACITY ),
-
-/* Submitted by Ricky Wong Yung Fei <evilbladewarrior@gmail.com> */
-/* Nokia 7610 Supernova - Too many sectors reported in usb storage mode */
-UNUSUAL_DEV(  0x0421, 0x00f5, 0x0000, 0x0470,
-        "Nokia",
-        "7610 Supernova",
-        US_SC_DEVICE, US_PR_DEVICE, NULL,
-        US_FL_FIX_CAPACITY ),
-
 /* Reported by Olaf Hering <olh@suse.de> from novell bug #105878 */
 UNUSUAL_DEV(  0x0424, 0x0fdc, 0x0210, 0x0210,
                 "SMSC",
@@ -289,11 +246,17 @@ UNUSUAL_DEV(  0x0424, 0x0fdc, 0x0210, 0x0210,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_SINGLE_LUN ),
 
-#ifdef CONFIG_USB_STORAGE_DPCM
+#ifdef CONFIG_USB_STORAGE_SDDR09
 UNUSUAL_DEV(  0x0436, 0x0005, 0x0100, 0x0100,
                 "Microtech",
                 "CameraMate (DPCM_USB)",
                 US_SC_SCSI, US_PR_DPCM_USB, NULL, 0 ),
+#else
+UNUSUAL_DEV(  0x0436, 0x0005, 0x0100, 0x0100,
+                "Microtech",
+                "CameraMate",
+                US_SC_SCSI, US_PR_CB, NULL,
+                US_FL_SINGLE_LUN ),
 #endif
 
 /* Patch submitted by Daniel Drake <dsd@gentoo.org>
@@ -388,6 +351,15 @@ UNUSUAL_DEV(  0x04a4, 0x0004, 0x0001, 0x0001,
                 "DVD-CAM DZ-MV100A Camcorder",
                 US_SC_SCSI, US_PR_CB, NULL, US_FL_SINGLE_LUN),
 
+/* BENQ DC5330
+ * Reported by Manuel Fombuena <mfombuena@ya.com> and
+ * Frank Copeland <fjc@thingy.apana.org.au> */
+UNUSUAL_DEV(  0x04a5, 0x3010, 0x0100, 0x0100,
+                "Tekom Technologies, Inc",
+                "300_CAMERA",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_IGNORE_RESIDUE ),
+
 /* Patch for Nikon coolpix 2000
  * Submitted by Fabien Cosse <fabien.cosse@wanadoo.fr>*/
 UNUSUAL_DEV(  0x04b0, 0x0301, 0x0010, 0x0010,
@@ -396,83 +368,6 @@ UNUSUAL_DEV(  0x04b0, 0x0301, 0x0010, 0x0010,
                 US_SC_DEVICE, US_PR_DEVICE,NULL,
                 US_FL_NOT_LOCKABLE ),
 
-/* Reported by Stefan de Konink <skinkie@xs4all.nl> */
-UNUSUAL_DEV(  0x04b0, 0x0401, 0x0200, 0x0200,
-                "NIKON",
-                "NIKON DSC D100",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Tobias Kunze Briseno <t-linux@fictive.com> */
-UNUSUAL_DEV(  0x04b0, 0x0403, 0x0200, 0x0200,
-                "NIKON",
-                "NIKON DSC D2H",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Milinevsky Dmitry <niam.niam@gmail.com> */
-UNUSUAL_DEV(  0x04b0, 0x0409, 0x0100, 0x0100,
-                "NIKON",
-                "NIKON DSC D50",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Andreas Bockhold <andreas@bockionline.de> */
-UNUSUAL_DEV(  0x04b0, 0x0405, 0x0100, 0x0100,
-                "NIKON",
-                "NIKON DSC D70",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Jamie Kitson <jamie@staberinde.fsnet.co.uk> */
-UNUSUAL_DEV(  0x04b0, 0x040d, 0x0100, 0x0100,
-                "NIKON",
-                "NIKON DSC D70s",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Graber and Mike Pagano <mpagano-kernel@mpagano.com> */
-UNUSUAL_DEV(  0x04b0, 0x040f, 0x0100, 0x0200,
-                "NIKON",
-                "NIKON DSC D200",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Emil Larsson <emil@swip.net> */
-UNUSUAL_DEV(  0x04b0, 0x0411, 0x0100, 0x0111,
-                "NIKON",
-                "NIKON DSC D80",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Ortwin Glueck <odi@odi.ch> */
-UNUSUAL_DEV(  0x04b0, 0x0413, 0x0110, 0x0111,
-                "NIKON",
-                "NIKON DSC D40",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Paul Check <paul@openstreet.com> */
-UNUSUAL_DEV(  0x04b0, 0x0415, 0x0100, 0x0100,
-                "NIKON",
-                "NIKON DSC D2Xs",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by Shan Destromp (shansan@gmail.com) */
-UNUSUAL_DEV(  0x04b0, 0x0417, 0x0100, 0x0100,
-                "NIKON",
-                "NIKON DSC D40X",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/* Reported by paul ready <lxtwin@homecall.co.uk> */
-UNUSUAL_DEV(  0x04b0, 0x0419, 0x0100, 0x0200,
-                "NIKON",
-                "NIKON DSC D300",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
 /* Reported by Doug Maxey (dwm@austin.ibm.com) */
 UNUSUAL_DEV(  0x04b3, 0x4001, 0x0110, 0x0110,
                 "IBM",
@@ -480,15 +375,6 @@ UNUSUAL_DEV(  0x04b3, 0x4001, 0x0110, 0x0110,
                 US_SC_DEVICE, US_PR_CB, NULL,
                 US_FL_MAX_SECTORS_MIN),
 
-/* BENQ DC5330
- * Reported by Manuel Fombuena <mfombuena@ya.com> and
- * Frank Copeland <fjc@thingy.apana.org.au> */
-UNUSUAL_DEV(  0x04a5, 0x3010, 0x0100, 0x0100,
-                "Tekom Technologies, Inc",
-                "300_CAMERA",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_IGNORE_RESIDUE ),
-
 #ifdef CONFIG_USB_STORAGE_CYPRESS_ATACB
 /* CY7C68300 : support atacb */
 UNUSUAL_DEV(  0x04b4, 0x6830, 0x0000, 0x9999,
@@ -594,6 +480,12 @@ UNUSUAL_DEV(  0x04e6, 0x0005, 0x0100, 0x0208,
                 "eUSB SmartMedia / CompactFlash Adapter",
                 US_SC_SCSI, US_PR_DPCM_USB, usb_stor_sddr09_dpcm_init,
                 0),
+#else
+UNUSUAL_DEV(  0x04e6, 0x0005, 0x0100, 0x0208,
+                "SCM Microsystems",
+                "eUSB CompactFlash Adapter",
+                US_SC_SCSI, US_PR_CB, NULL,
+                US_FL_SINGLE_LUN),
 #endif
 
 /* Reported by Markus Demleitner <msdemlei@cl.uni-heidelberg.de> */
@@ -685,6 +577,13 @@ UNUSUAL_DEV(  0x0525, 0xa140, 0x0100, 0x0100,
                 US_SC_8070, US_PR_DEVICE, NULL,
                 US_FL_FIX_INQUIRY ),
 
+/* Added by Alan Stern <stern@rowland.harvard.edu> */
+COMPLIANT_DEV(0x0525, 0xa4a5, 0x0000, 0x9999,
+                "Linux",
+                "File-backed Storage Gadget",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_CAPACITY_OK ),
+
 /* Yakumo Mega Image 37
  * Submitted by Stephan Fuhrmann <atomenergie@t-online.de> */
 UNUSUAL_DEV(  0x052b, 0x1801, 0x0100, 0x0100,
@@ -807,15 +706,15 @@ UNUSUAL_DEV(  0x054c, 0x006d, 0x0000, 0x9999,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_INQUIRY ),
 
-/* Submitted by Mike Alborn <malborn@deandra.homeip.net> */
-UNUSUAL_DEV(  0x054c, 0x016a, 0x0000, 0x9999,
+/* Submitted by Frank Engel <frankie@cse.unsw.edu.au> */
+UNUSUAL_DEV(  0x054c, 0x0099, 0x0000, 0x9999,
                 "Sony",
                 "PEG Mass Storage",
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_INQUIRY ),
-                
-/* Submitted by Frank Engel <frankie@cse.unsw.edu.au> */
-UNUSUAL_DEV(  0x054c, 0x0099, 0x0000, 0x9999,
+
+/* Submitted by Mike Alborn <malborn@deandra.homeip.net> */
+UNUSUAL_DEV(  0x054c, 0x016a, 0x0000, 0x9999,
                 "Sony",
                 "PEG Mass Storage",
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
@@ -966,6 +865,18 @@ UNUSUAL_DEV( 0x05ac, 0x120a, 0x0000, 0x9999,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_CAPACITY ),
 
+/* Reported by Dan Williams <dcbw@redhat.com>
+ * Option N.V. mobile broadband modems
+ * Ignore driver CD mode and force into modem mode by default.
+ */
+
+/* Globetrotter HSDPA; mass storage shows up as Qualcomm for vendor */
+UNUSUAL_DEV(  0x05c6, 0x1000, 0x0000, 0x9999,
+                "Option N.V.",
+                "Mass Storage",
+                US_SC_DEVICE, US_PR_DEVICE, option_ms_init,
+                0),
+
 #ifdef CONFIG_USB_STORAGE_JUMPSHOT
 UNUSUAL_DEV(  0x05dc, 0x0001, 0x0000, 0x0001,
                 "Lexar",
@@ -1004,6 +915,13 @@ UNUSUAL_DEV(  0x05e3, 0x0702, 0x0000, 0xffff,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_GO_SLOW | US_FL_MAX_SECTORS_64 ),
 
+/* Reported by Ben Efros <ben@pc-doctor.com> */
+UNUSUAL_DEV(  0x05e3, 0x0723, 0x9451, 0x9451,
+                "Genesys Logic",
+                "USB to SATA",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SANE_SENSE ),
+
 /* Reported by Hanno Boeck <hanno@gmx.de>
  * Taken from the Lycoris Kernel */
 UNUSUAL_DEV(  0x0636, 0x0003, 0x0000, 0x9999,
@@ -1040,7 +958,7 @@ UNUSUAL_DEV( 0x067b, 0x2507, 0x0100, 0x0100,
                 US_FL_FIX_CAPACITY | US_FL_GO_SLOW ),
 
 /* Reported by Alex Butcher <alex.butcher@assursys.co.uk> */
-UNUSUAL_DEV( 0x067b, 0x3507, 0x0001, 0x0001,
+UNUSUAL_DEV( 0x067b, 0x3507, 0x0001, 0x0101,
                 "Prolific Technology Inc.",
                 "ATAPI-6 Bridge Controller",
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
@@ -1161,11 +1079,17 @@ UNUSUAL_DEV(  0x07af, 0x0005, 0x0100, 0x0100,
                 US_SC_DEVICE, US_PR_DEVICE, usb_stor_euscsi_init,
                 US_FL_SCM_MULT_TARG ),
 
-#ifdef CONFIG_USB_STORAGE_DPCM
+#ifdef CONFIG_USB_STORAGE_SDDR09
 UNUSUAL_DEV(  0x07af, 0x0006, 0x0100, 0x0100,
                 "Microtech",
                 "CameraMate (DPCM_USB)",
                 US_SC_SCSI, US_PR_DPCM_USB, NULL, 0 ),
+#else
+UNUSUAL_DEV(  0x07af, 0x0006, 0x0100, 0x0100,
+                "Microtech",
+                "CameraMate",
+                US_SC_SCSI, US_PR_CB, NULL,
+                US_FL_SINGLE_LUN ),
 #endif
 
 #ifdef CONFIG_USB_STORAGE_ALAUDA
@@ -1320,6 +1244,13 @@ UNUSUAL_DEV( 0x0840, 0x0082, 0x0001, 0x0001,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_CAPACITY),
 
+/* Reported and patched by Nguyen Anh Quynh <aquynh@gmail.com> */
+UNUSUAL_DEV( 0x0840, 0x0084, 0x0001, 0x0001,
+                "Argosy",
+                "Storage",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_FIX_CAPACITY),
+
 /* Entry and supporting patch by Theodore Kilgore <kilgota@auburn.edu>.
  * Flag will support Bulk devices which use a standards-violating 32-byte
  * Command Block Wrapper. Here, the "DC2MEGA" cameras (several brands) with
@@ -1343,17 +1274,6 @@ UNUSUAL_DEV(  0x0851, 0x1543, 0x0200, 0x0200,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_NOT_LOCKABLE),
 
-/* Andrew Lunn <andrew@lunn.ch>
- * PanDigital Digital Picture Frame. Does not like ALLOW_MEDIUM_REMOVAL
- * on LUN 4.
- * Note: Vend:Prod clash with "Ltd Maxell WS30 Slim Digital Camera"
-*/
-UNUSUAL_DEV(  0x0851, 0x1543, 0x0200, 0x0200,
-                "PanDigital",
-                "Photo Frame",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_NOT_LOCKABLE),
-
 /* Submitted by Jan De Luyck <lkml@kcore.org> */
 UNUSUAL_DEV(  0x08bd, 0x1100, 0x0000, 0x0000,
                 "CITIZEN",
@@ -1425,6 +1345,13 @@ UNUSUAL_DEV( 0x0a17, 0x006, 0x0000, 0xffff,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_INQUIRY ),
 
+/* Reported by Jaak Ristioja <Ristioja@gmail.com> */
+UNUSUAL_DEV( 0x0a17, 0x006e, 0x0100, 0x0100,
+                "Pentax",
+                "K10D",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_FIX_CAPACITY ),
+
 /* These are virtual windows driver CDs, which the zd1211rw driver
  * automatically converts into WLAN devices. */
 UNUSUAL_DEV( 0x0ace, 0x2011, 0x0101, 0x0101,
@@ -1439,6 +1366,18 @@ UNUSUAL_DEV( 0x0ace, 0x20ff, 0x0101, 0x0101,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_IGNORE_DEVICE ),
 
+/* Reported by Dan Williams <dcbw@redhat.com>
+ * Option N.V. mobile broadband modems
+ * Ignore driver CD mode and force into modem mode by default.
+ */
+
+/* iCON 225 */
+UNUSUAL_DEV(  0x0af0, 0x6971, 0x0000, 0x9999,
+                "Option N.V.",
+                "Mass Storage",
+                US_SC_DEVICE, US_PR_DEVICE, option_ms_init,
+                0),
+
 /* Reported by F. Aben <f.aben@option.com>
  * This device (wrongly) has a vendor-specific device descriptor.
  * The entry is needed so usb-storage can bind to it's mass-storage
@@ -1449,6 +1388,13 @@ UNUSUAL_DEV( 0x0af0, 0x7401, 0x0000, 0x0000,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 0 ),
 
+/* Reported by Ben Efros <ben@pc-doctor.com> */
+UNUSUAL_DEV( 0x0bc2, 0x3010, 0x0000, 0x0000,
+                "Seagate",
+                "FreeAgent Pro",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SANE_SENSE ),
+
 #ifdef CONFIG_USB_STORAGE_ISD200
 UNUSUAL_DEV(  0x0bf6, 0xa001, 0x0100, 0x0110,
                 "ATI",
@@ -1472,6 +1418,22 @@ UNUSUAL_DEV( 0x0c0b, 0xa109, 0x0000, 0xffff,
                 US_FL_SINGLE_LUN ),
 #endif
 
+UNUSUAL_DEV(  0x0d49, 0x7310, 0x0000, 0x9999,
+                "Maxtor",
+                "USB to SATA",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SANE_SENSE),
+
+/*
+ * Pete Zaitcev <zaitcev@yahoo.com>, bz#164688.
+ * The device blatantly ignores LUN and returns 1 in GetMaxLUN.
+ */
+UNUSUAL_DEV( 0x0c45, 0x1060, 0x0100, 0x0100,
+                "Unknown",
+                "Unknown",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SINGLE_LUN ),
+
 /* Submitted by: Nick Sillik <n.sillik@temple.edu>
  * Needed for OneTouch extension to usb-storage
  *
@@ -1489,16 +1451,6 @@ UNUSUAL_DEV( 0x0c0b, 0xa109, 0x0000, 0xffff,
                         0),
 #endif
 
-/*
- * Pete Zaitcev <zaitcev@yahoo.com>, bz#164688.
- * The device blatantly ignores LUN and returns 1 in GetMaxLUN.
- */
-UNUSUAL_DEV( 0x0c45, 0x1060, 0x0100, 0x0100,
-                "Unknown",
-                "Unknown",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_SINGLE_LUN ),
-
 /* Submitted by Joris Struyve <joris@struyve.be> */
 UNUSUAL_DEV( 0x0d96, 0x410a, 0x0001, 0xffff,
                 "Medion",
@@ -1516,6 +1468,13 @@ UNUSUAL_DEV(  0x0d96, 0x5200, 0x0001, 0x0200,
                 "JD 5200 z3",
                 US_SC_DEVICE, US_PR_DEVICE, NULL, US_FL_FIX_INQUIRY),
 
+/* Reported by  Jason Johnston <killean@shaw.ca> */
+UNUSUAL_DEV(  0x0dc4, 0x0073, 0x0000, 0x0000,
+                "Macpower Technology Co.LTD.",
+                "USB 2.0 3.5\" DEVICE",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_FIX_CAPACITY),
+
 /* Reported by Lubomir Blaha <tritol@trilogic.cz>
  * I _REALLY_ don't know what 3rd, 4th number and all defines mean, but this
  * works for me. Can anybody correct these values? (I able to test corrected
@@ -1638,13 +1597,6 @@ UNUSUAL_DEV(  0x0fce, 0xe030, 0x0000, 0x0000,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_FIX_CAPACITY | US_FL_IGNORE_RESIDUE ),
 
-/* Reported by Ricardo Barberis <ricardo@dattatec.com> */
-UNUSUAL_DEV(  0x0fce, 0xe092, 0x0000, 0x0000,
-                "Sony Ericsson",
-                "P1i",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_IGNORE_RESIDUE ),
-
 /* Reported by Emmanuel Vasilakis <evas@forthnet.gr> */
 UNUSUAL_DEV(  0x0fce, 0xe031, 0x0000, 0x0000,
                 "Sony Ericsson",
@@ -1652,6 +1604,13 @@ UNUSUAL_DEV(  0x0fce, 0xe031, 0x0000, 0x0000,
                 US_SC_DEVICE, US_PR_DEVICE, NULL,
                 US_FL_IGNORE_RESIDUE | US_FL_FIX_CAPACITY ),
 
+/* Reported by Ricardo Barberis <ricardo@dattatec.com> */
+UNUSUAL_DEV(  0x0fce, 0xe092, 0x0000, 0x0000,
+                "Sony Ericsson",
+                "P1i",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_IGNORE_RESIDUE ),
+
 /* Reported by Kevin Cernekee <kpc-usbdev@gelato.uiuc.edu>
  * Tested on hardware version 1.10.
  * Entry is needed only for the initializer function override.
@@ -1664,6 +1623,12 @@ UNUSUAL_DEV(  0x1019, 0x0c55, 0x0000, 0x0110,
                 US_SC_DEVICE, US_PR_DEVICE, usb_stor_ucr61s2b_init,
                 0 ),
 
+UNUSUAL_DEV(  0x1058, 0x0704, 0x0000, 0x9999,
+                "Western Digital",
+                "External HDD",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_SANE_SENSE),
+
 /* Reported by Fabio Venturi <f.venturi@tdnet.it>
  * The device reports a vendor-specific bDeviceClass.
  */
@@ -2053,10 +2018,10 @@ UNUSUAL_DEV(  0x14cd, 0x6600, 0x0201, 0x0201,
  * JMicron responds to USN and several other SCSI ioctls with a
  * residue that causes subsequent I/O requests to fail.  */
 UNUSUAL_DEV(  0x152d, 0x2329, 0x0100, 0x0100,
-                "JMicron",
-                "USB to ATA/ATAPI Bridge",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_IGNORE_RESIDUE ),
+                "JMicron",
+                "USB to ATA/ATAPI Bridge",
+                US_SC_DEVICE, US_PR_DEVICE, NULL,
+                US_FL_IGNORE_RESIDUE | US_FL_SANE_SENSE ),
 
 /* Reported by Robert Schedel <r.schedel@yahoo.de>
  * Note: this is a 'super top' device like the above 14cd/6600 device */
@@ -2086,27 +2051,6 @@ UNUSUAL_DEV(  0x22b8, 0x3010, 0x0001, 0x0001,
                 US_FL_FIX_CAPACITY | US_FL_IGNORE_RESIDUE ),
 
 /*
- * Patch by Pete Zaitcev <zaitcev@redhat.com>
- * Report by Mark Patton. Red Hat bz#208928.
- * Added support for rev 0x0002 (Motorola ROKR W5)
- * by Javier Smaldone <javier@smaldone.com.ar>
- */
-UNUSUAL_DEV(  0x22b8, 0x4810, 0x0001, 0x0002,
-                "Motorola",
-                "RAZR V3i/ROKR W5",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/*
- * Patch by Jost Diederichs <jost@qdusa.com>
- */
-UNUSUAL_DEV(0x22b8, 0x6410, 0x0001, 0x9999,
-                "Motorola Inc.",
-                "Motorola Phone (RAZRV3xx)",
-                US_SC_DEVICE, US_PR_DEVICE, NULL,
-                US_FL_FIX_CAPACITY),
-
-/*
  * Patch by Constantin Baranov <const@tltsu.ru>
  * Report by Andreas Koenecke.
  * Motorola ROKR Z6.
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index 27016fd2cad1..4becf495ca2d 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -75,9 +75,6 @@
 #ifdef CONFIG_USB_STORAGE_SDDR55
 #include "sddr55.h"
 #endif
-#ifdef CONFIG_USB_STORAGE_DPCM
-#include "dpcm.h"
-#endif
 #ifdef CONFIG_USB_STORAGE_FREECOM
 #include "freecom.h"
 #endif
@@ -103,6 +100,7 @@
 #include "cypress_atacb.h"
 #endif
 #include "sierra_ms.h"
+#include "option_ms.h"
 
 /* Some informational data */
 MODULE_AUTHOR("Matthew Dharm <mdharm-usb@one-eyed-alien.net>");
@@ -113,6 +111,10 @@ static unsigned int delay_use = 5;
 module_param(delay_use, uint, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device");
 
+static char quirks[128];
+module_param_string(quirks, quirks, sizeof(quirks), S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(quirks, "supplemental list of device IDs and their quirks");
+
 
 /*
  * The entries in this table correspond, line for line,
@@ -126,6 +128,8 @@ MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device");
 { USB_DEVICE_VER(id_vendor, id_product, bcdDeviceMin,bcdDeviceMax), \
   .driver_info = (flags)|(USB_US_TYPE_STOR<<24) }
 
+#define COMPLIANT_DEV   UNUSUAL_DEV
+
 #define USUAL_DEV(useProto, useTrans, useType) \
 { USB_INTERFACE_INFO(USB_CLASS_MASS_STORAGE, useProto, useTrans), \
   .driver_info = (USB_US_TYPE_STOR<<24) }
@@ -134,6 +138,7 @@ static struct usb_device_id storage_usb_ids [] = {
 
 #       include "unusual_devs.h"
 #undef UNUSUAL_DEV
+#undef COMPLIANT_DEV
 #undef USUAL_DEV
         /* Terminating entry */
         { }
@@ -164,6 +169,8 @@ MODULE_DEVICE_TABLE (usb, storage_usb_ids);
         .initFunction = init_function,  \
 }
 
+#define COMPLIANT_DEV   UNUSUAL_DEV
+
 #define USUAL_DEV(use_protocol, use_transport, use_type) \
 { \
         .useProtocol = use_protocol,    \
@@ -173,6 +180,7 @@ MODULE_DEVICE_TABLE (usb, storage_usb_ids);
 static struct us_unusual_dev us_unusual_dev_list[] = {
 #       include "unusual_devs.h" 
 #       undef UNUSUAL_DEV
+#       undef COMPLIANT_DEV
 #       undef USUAL_DEV
 
         /* Terminating entry */
@@ -464,13 +472,83 @@ static int associate_dev(struct us_data *us, struct usb_interface *intf)
                 US_DEBUGP("I/O buffer allocation failed\n");
                 return -ENOMEM;
         }
+        return 0;
+}
 
-        us->sensebuf = kmalloc(US_SENSE_SIZE, GFP_KERNEL);
-        if (!us->sensebuf) {
-                US_DEBUGP("Sense buffer allocation failed\n");
-                return -ENOMEM;
+/* Works only for digits and letters, but small and fast */
+#define TOLOWER(x) ((x) | 0x20)
+
+/* Adjust device flags based on the "quirks=" module parameter */
+static void adjust_quirks(struct us_data *us)
+{
+        char *p;
+        u16 vid = le16_to_cpu(us->pusb_dev->descriptor.idVendor);
+        u16 pid = le16_to_cpu(us->pusb_dev->descriptor.idProduct);
+        unsigned f = 0;
+        unsigned int mask = (US_FL_SANE_SENSE | US_FL_FIX_CAPACITY |
+                        US_FL_CAPACITY_HEURISTICS | US_FL_IGNORE_DEVICE |
+                        US_FL_NOT_LOCKABLE | US_FL_MAX_SECTORS_64 |
+                        US_FL_CAPACITY_OK | US_FL_IGNORE_RESIDUE |
+                        US_FL_SINGLE_LUN | US_FL_NO_WP_DETECT);
+
+        p = quirks;
+        while (*p) {
+                /* Each entry consists of VID:PID:flags */
+                if (vid == simple_strtoul(p, &p, 16) &&
+                                *p == ':' &&
+                                pid == simple_strtoul(p+1, &p, 16) &&
+                                *p == ':')
+                        break;
+
+                /* Move forward to the next entry */
+                while (*p) {
+                        if (*p++ == ',')
+                                break;
+                }
         }
-        return 0;
+        if (!*p)        /* No match */
+                return;
+
+        /* Collect the flags */
+        while (*++p && *p != ',') {
+                switch (TOLOWER(*p)) {
+                case 'a':
+                        f |= US_FL_SANE_SENSE;
+                        break;
+                case 'c':
+                        f |= US_FL_FIX_CAPACITY;
+                        break;
+                case 'h':
+                        f |= US_FL_CAPACITY_HEURISTICS;
+                        break;
+                case 'i':
+                        f |= US_FL_IGNORE_DEVICE;
+                        break;
+                case 'l':
+                        f |= US_FL_NOT_LOCKABLE;
+                        break;
+                case 'm':
+                        f |= US_FL_MAX_SECTORS_64;
+                        break;
+                case 'o':
+                        f |= US_FL_CAPACITY_OK;
+                        break;
+                case 'r':
+                        f |= US_FL_IGNORE_RESIDUE;
+                        break;
+                case 's':
+                        f |= US_FL_SINGLE_LUN;
+                        break;
+                case 'w':
+                        f |= US_FL_NO_WP_DETECT;
+                        break;
+                /* Ignore unrecognized flag characters */
+                }
+        }
+        us->fflags = (us->fflags & ~mask) | f;
+        dev_info(&us->pusb_intf->dev, "Quirks match for "
+                        "vid %04x pid %04x: %x\n",
+                        vid, pid, f);
 }
 
 /* Find an unusual_dev descriptor (always succeeds in the current code) */
@@ -497,6 +575,7 @@ static int get_device_info(struct us_data *us, const struct usb_device_id *id)
                         idesc->bInterfaceProtocol :
                         unusual_dev->useTransport;
         us->fflags = USB_US_ORIG_FLAGS(id->driver_info);
+        adjust_quirks(us);
 
         if (us->fflags & US_FL_IGNORE_DEVICE) {
                 printk(KERN_INFO USB_STORAGE "device ignored\n");
@@ -562,7 +641,7 @@ static int get_transport(struct us_data *us)
 
         case US_PR_CBI:
                 us->transport_name = "Control/Bulk/Interrupt";
-                us->transport = usb_stor_CBI_transport;
+                us->transport = usb_stor_CB_transport;
                 us->transport_reset = usb_stor_CB_reset;
                 us->max_lun = 7;
                 break;
@@ -675,19 +754,19 @@ static int get_protocol(struct us_data *us)
 
         case US_SC_8020:
                 us->protocol_name = "8020i";
-                us->proto_handler = usb_stor_ATAPI_command;
+                us->proto_handler = usb_stor_pad12_command;
                 us->max_lun = 0;
                 break;
 
         case US_SC_QIC:
                 us->protocol_name = "QIC-157";
-                us->proto_handler = usb_stor_qic157_command;
+                us->proto_handler = usb_stor_pad12_command;
                 us->max_lun = 0;
                 break;
 
         case US_SC_8070:
                 us->protocol_name = "8070i";
-                us->proto_handler = usb_stor_ATAPI_command;
+                us->proto_handler = usb_stor_pad12_command;
                 us->max_lun = 0;
                 break;
 
@@ -840,8 +919,6 @@ static void dissociate_dev(struct us_data *us)
 {
         US_DEBUGP("-- %s\n", __func__);
 
-        kfree(us->sensebuf);
-
         /* Free the device-related DMA-mapped buffers */
         if (us->cr)
                 usb_buffer_free(us->pusb_dev, sizeof(*us->cr), us->cr,
@@ -1064,6 +1141,7 @@ static struct usb_driver usb_storage_driver = {
 static int __init usb_stor_init(void)
 {
         int retval;
+
         printk(KERN_INFO "Initializing USB Mass Storage driver...\n");
 
         /* register the driver, return usb_register return code if error */
diff --git a/drivers/usb/storage/usb.h b/drivers/usb/storage/usb.h
index a4ad73bd832d..65e674e4be99 100644
--- a/drivers/usb/storage/usb.h
+++ b/drivers/usb/storage/usb.h
@@ -138,7 +138,6 @@ struct us_data {
         struct usb_ctrlrequest  *cr;             /* control requests     */
         struct usb_sg_request   current_sg;      /* scatter-gather req.  */
         unsigned char           *iobuf;          /* I/O buffer           */
-        unsigned char           *sensebuf;       /* sense data buffer    */
         dma_addr_t              cr_dma;          /* buffer DMA addresses */
         dma_addr_t              iobuf_dma;
         struct task_struct      *ctl_thread;     /* the control thread   */
@@ -155,6 +154,10 @@ struct us_data {
 #ifdef CONFIG_PM
         pm_hook                 suspend_resume_hook;
 #endif
+
+        /* hacks for READ CAPACITY bug handling */
+        int                     use_last_sector_hacks;
+        int                     last_sector_retries;
 };
 
 /* Convert between us_data and the corresponding Scsi_Host */
diff --git a/drivers/usb/wusbcore/rh.c b/drivers/usb/wusbcore/rh.c
index 95c6fa3bf6b2..3937bf6f8cef 100644
--- a/drivers/usb/wusbcore/rh.c
+++ b/drivers/usb/wusbcore/rh.c
@@ -326,7 +326,7 @@ static int wusbhc_rh_clear_port_feat(struct wusbhc *wusbhc, u16 feature,
 static int wusbhc_rh_get_port_status(struct wusbhc *wusbhc, u16 port_idx,
                                      u32 *_buf, u16 wLength)
 {
-        u16 *buf = (u16 *) _buf;
+        __le16 *buf = (__le16 *)_buf;
 
         if (port_idx > wusbhc->ports_max)
                 return -EINVAL;
diff --git a/drivers/uwb/i1480/dfu/usb.c b/drivers/uwb/i1480/dfu/usb.c
index 686795e97195..c7080d497311 100644
--- a/drivers/uwb/i1480/dfu/usb.c
+++ b/drivers/uwb/i1480/dfu/usb.c
@@ -387,7 +387,7 @@ int i1480_usb_probe(struct usb_interface *iface, const struct usb_device_id *id)
                 goto error_create;
         }
 
-        /* setup the fops and upload the firmare */
+        /* setup the fops and upload the firmware */
         i1480->pre_fw_name = "i1480-pre-phy-0.0.bin";
         i1480->mac_fw_name = "i1480-usb-0.0.bin";
         i1480->mac_fw_name_deprecate = "ptc-0.0.bin";
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index e6210725b9ab..d012edda6d11 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -1332,7 +1332,7 @@ static void vgacon_save_screen(struct vc_data *c)
                 c->vc_y = screen_info.orig_y;
         }
 
-        /* We can't copy in more then the size of the video buffer,
+        /* We can't copy in more than the size of the video buffer,
          * or we'll be copying in VGA BIOS */
 
         if (!vga_is_gfx)
diff --git a/firmware/.gitignore b/firmware/.gitignore
index d9c69017bc9a..f89a21fffbf1 100644
--- a/firmware/.gitignore
+++ b/firmware/.gitignore
@@ -3,4 +3,3 @@
 *.bin
 *.csp
 *.dsp
-ihex2fw
diff --git a/firmware/Makefile b/firmware/Makefile
index d872b7942a30..55d3082ea13e 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -99,10 +99,10 @@ quiet_cmd_ihex  = IHEX    $@
       cmd_ihex  = $(OBJCOPY) -Iihex -Obinary $< $@
 
 quiet_cmd_ihex2fw  = IHEX2FW $@
-      cmd_ihex2fw  = $(objtree)/$(obj)/ihex2fw $< $@
+      cmd_ihex2fw  = $(objtree)/scripts/ihex2fw $< $@
 
 quiet_cmd_h16tofw  = H16TOFW $@
-      cmd_h16tofw  = $(objtree)/$(obj)/ihex2fw -w $< $@
+      cmd_h16tofw  = $(objtree)/scripts/ihex2fw -w $< $@
 
 quiet_cmd_fwbin = MK_FW   $@
       cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)";                \
@@ -165,11 +165,11 @@ $(obj)/%: $(obj)/%.ihex | $(objtree)/$(obj)/$$(dir %)
 # is actually meaningful, because the firmware has to be loaded in a certain
 # order rather than as a single binary blob. Thus, we convert them into our
 # more compact binary representation of ihex records (<linux/ihex.h>)
-$(obj)/%.fw: $(obj)/%.HEX $(obj)/ihex2fw | $(objtree)/$(obj)/$$(dir %)
+$(obj)/%.fw: $(obj)/%.HEX  | $(objtree)/$(obj)/$$(dir %)
         $(call cmd,ihex2fw)
 
 # .H16 is our own modified form of Intel HEX, with 16-bit length for records.
-$(obj)/%.fw: $(obj)/%.H16 $(obj)/ihex2fw | $(objtree)/$(obj)/$$(dir %)
+$(obj)/%.fw: $(obj)/%.H16 | $(objtree)/$(obj)/$$(dir %)
         $(call cmd,h16tofw)
 
 $(firmware-dirs):
@@ -186,5 +186,3 @@ targets := $(fw-shipped-) $(patsubst $(obj)/%,%, \
 # Without this, built-in.o won't be created when it's empty, and the
 # final vmlinux link will fail.
 obj-n := dummy
-
-hostprogs-y := ihex2fw
diff --git a/fs/debugfs/file.c b/fs/debugfs/file.c
index 159a5efd6a8a..33a90120f6ad 100644
--- a/fs/debugfs/file.c
+++ b/fs/debugfs/file.c
@@ -294,6 +294,38 @@ struct dentry *debugfs_create_x32(const char *name, mode_t mode,
 }
 EXPORT_SYMBOL_GPL(debugfs_create_x32);
 
+
+static int debugfs_size_t_set(void *data, u64 val)
+{
+        *(size_t *)data = val;
+        return 0;
+}
+static int debugfs_size_t_get(void *data, u64 *val)
+{
+        *val = *(size_t *)data;
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_size_t, debugfs_size_t_get, debugfs_size_t_set,
+                        "%llu\n");      /* %llu and %zu are more or less the same */
+
+/**
+ * debugfs_create_size_t - create a debugfs file that is used to read and write an size_t value
+ * @name: a pointer to a string containing the name of the file to create.
+ * @mode: the permission that the file should have
+ * @parent: a pointer to the parent dentry for this file.  This should be a
+ *          directory dentry if set.  If this parameter is %NULL, then the
+ *          file will be created in the root of the debugfs filesystem.
+ * @value: a pointer to the variable that the file should read to and write
+ *         from.
+ */
+struct dentry *debugfs_create_size_t(const char *name, mode_t mode,
+                                     struct dentry *parent, size_t *value)
+{
+        return debugfs_create_file(name, mode, parent, value, &fops_size_t);
+}
+EXPORT_SYMBOL_GPL(debugfs_create_size_t);
+
+
 static ssize_t read_file_bool(struct file *file, char __user *user_buf,
                               size_t count, loff_t *ppos)
 {
diff --git a/fs/gfs2/Kconfig b/fs/gfs2/Kconfig
index ab2f57e3fb87..e563a6449811 100644
--- a/fs/gfs2/Kconfig
+++ b/fs/gfs2/Kconfig
@@ -1,6 +1,6 @@
 config GFS2_FS
         tristate "GFS2 file system support"
-        depends on EXPERIMENTAL && (64BIT || (LSF && LBD))
+        depends on EXPERIMENTAL && (64BIT || LBD)
         select FS_POSIX_ACL
         select CRC32
         help
diff --git a/fs/gfs2/ops_address.c b/fs/gfs2/ops_address.c
index 6e4ea36c6605..4ddab67867eb 100644
--- a/fs/gfs2/ops_address.c
+++ b/fs/gfs2/ops_address.c
@@ -675,6 +675,7 @@ static int gfs2_write_begin(struct file *file, struct address_space *mapping,
                 goto out_trans_fail;
 
         error = -ENOMEM;
+        flags |= AOP_FLAG_NOFS;
         page = grab_cache_page_write_begin(mapping, index, flags);
         *pagep = page;
         if (unlikely(!page))
diff --git a/fs/gfs2/ops_file.c b/fs/gfs2/ops_file.c
index 289c5f54ba53..93fe41b67f97 100644
--- a/fs/gfs2/ops_file.c
+++ b/fs/gfs2/ops_file.c
@@ -342,7 +342,7 @@ static int gfs2_page_mkwrite(struct vm_area_struct *vma, struct page *page)
         struct gfs2_inode *ip = GFS2_I(inode);
         struct gfs2_sbd *sdp = GFS2_SB(inode);
         unsigned long last_index;
-        u64 pos = page->index << (PAGE_CACHE_SIZE - inode->i_blkbits);
+        u64 pos = page->index << PAGE_CACHE_SHIFT;
         unsigned int data_blocks, ind_blocks, rblocks;
         int alloc_required = 0;
         struct gfs2_holder gh;
diff --git a/fs/inode.c b/fs/inode.c
index 7a6e8c2ff7b1..0013ac1af8e7 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/inotify.h>
 #include <linux/mount.h>
+#include <linux/async.h>
 
 /*
  * This is needed for the following functions:
@@ -1138,16 +1139,11 @@ EXPORT_SYMBOL(remove_inode_hash);
  * I_FREEING is set so that no-one will take a new reference to the inode while
  * it is being deleted.
  */
-void generic_delete_inode(struct inode *inode)
+static void generic_delete_inode_async(void *data, async_cookie_t cookie)
 {
+        struct inode *inode = data;
         const struct super_operations *op = inode->i_sb->s_op;
 
-        list_del_init(&inode->i_list);
-        list_del_init(&inode->i_sb_list);
-        inode->i_state |= I_FREEING;
-        inodes_stat.nr_inodes--;
-        spin_unlock(&inode_lock);
-
         security_inode_delete(inode);
 
         if (op->delete_inode) {
@@ -1171,6 +1167,16 @@ void generic_delete_inode(struct inode *inode)
         destroy_inode(inode);
 }
 
+void generic_delete_inode(struct inode *inode)
+{
+        list_del_init(&inode->i_list);
+        list_del_init(&inode->i_sb_list);
+        inode->i_state |= I_FREEING;
+        inodes_stat.nr_inodes--;
+        spin_unlock(&inode_lock);
+        async_schedule_special(generic_delete_inode_async, inode, &inode->i_sb->s_async_list);
+}
+
 EXPORT_SYMBOL(generic_delete_inode);
 
 static void generic_forget_inode(struct inode *inode)
diff --git a/fs/ncpfs/ioctl.c b/fs/ncpfs/ioctl.c
index 6d04e050c74e..f54360f50a9c 100644
--- a/fs/ncpfs/ioctl.c
+++ b/fs/ncpfs/ioctl.c
@@ -98,7 +98,7 @@ struct compat_ncp_objectname_ioctl
 {
         s32             auth_type;
         u32             object_name_len;
-        compat_caddr_t  object_name;    /* an userspace data, in most cases user name */
+        compat_caddr_t  object_name;    /* a userspace data, in most cases user name */
 };
 
 struct compat_ncp_fs_info_v2 {
diff --git a/fs/ocfs2/cluster/heartbeat.c b/fs/ocfs2/cluster/heartbeat.c
index 6ebaa58e2c03..04697ba7f73e 100644
--- a/fs/ocfs2/cluster/heartbeat.c
+++ b/fs/ocfs2/cluster/heartbeat.c
@@ -854,7 +854,7 @@ static int o2hb_thread(void *data)
 
         while (!kthread_should_stop() && !reg->hr_unclean_stop) {
                 /* We track the time spent inside
-                 * o2hb_do_disk_heartbeat so that we avoid more then
+                 * o2hb_do_disk_heartbeat so that we avoid more than
                  * hr_timeout_ms between disk writes. On busy systems
                  * this should result in a heartbeat which is less
                  * likely to time itself out. */
diff --git a/fs/proc/base.c b/fs/proc/base.c
index 10fd5223d600..0c9de19a1633 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -65,6 +65,7 @@
 #include <linux/mm.h>
 #include <linux/rcupdate.h>
 #include <linux/kallsyms.h>
+#include <linux/stacktrace.h>
 #include <linux/resource.h>
 #include <linux/module.h>
 #include <linux/mount.h>
@@ -109,25 +110,22 @@ struct pid_entry {
         .op   = OP,                                     \
 }
 
-#define DIR(NAME, MODE, OTYPE)                                                  \
-        NOD(NAME, (S_IFDIR|(MODE)),                                             \
-                &proc_##OTYPE##_inode_operations, &proc_##OTYPE##_operations,   \
-                {} )
-#define LNK(NAME, OTYPE)                                        \
+#define DIR(NAME, MODE, iops, fops)     \
+        NOD(NAME, (S_IFDIR|(MODE)), &iops, &fops, {} )
+#define LNK(NAME, get_link)                                     \
         NOD(NAME, (S_IFLNK|S_IRWXUGO),                          \
                 &proc_pid_link_inode_operations, NULL,          \
-                { .proc_get_link = &proc_##OTYPE##_link } )
-#define REG(NAME, MODE, OTYPE)                          \
-        NOD(NAME, (S_IFREG|(MODE)), NULL,               \
-                &proc_##OTYPE##_operations, {})
-#define INF(NAME, MODE, OTYPE)                          \
+                { .proc_get_link = get_link } )
+#define REG(NAME, MODE, fops)                           \
+        NOD(NAME, (S_IFREG|(MODE)), NULL, &fops, {})
+#define INF(NAME, MODE, read)                           \
         NOD(NAME, (S_IFREG|(MODE)),                     \
                 NULL, &proc_info_file_operations,       \
-                { .proc_read = &proc_##OTYPE } )
-#define ONE(NAME, MODE, OTYPE)                          \
+                { .proc_read = read } )
+#define ONE(NAME, MODE, show)                           \
         NOD(NAME, (S_IFREG|(MODE)),                     \
                 NULL, &proc_single_file_operations,     \
-                { .proc_show = &proc_##OTYPE } )
+                { .proc_show = show } )
 
 /*
  * Count the number of hardlinks for the pid_entry table, excluding the .
@@ -308,9 +306,9 @@ static int proc_pid_auxv(struct task_struct *task, char *buffer)
         struct mm_struct *mm = get_task_mm(task);
         if (mm) {
                 unsigned int nwords = 0;
-                do
+                do {
                         nwords += 2;
-                while (mm->saved_auxv[nwords - 2] != 0); /* AT_NULL */
+                } while (mm->saved_auxv[nwords - 2] != 0); /* AT_NULL */
                 res = nwords * sizeof(mm->saved_auxv[0]);
                 if (res > PAGE_SIZE)
                         res = PAGE_SIZE;
@@ -340,6 +338,37 @@ static int proc_pid_wchan(struct task_struct *task, char *buffer)
 }
 #endif /* CONFIG_KALLSYMS */
 
+#ifdef CONFIG_STACKTRACE
+
+#define MAX_STACK_TRACE_DEPTH   64
+
+static int proc_pid_stack(struct seq_file *m, struct pid_namespace *ns,
+                          struct pid *pid, struct task_struct *task)
+{
+        struct stack_trace trace;
+        unsigned long *entries;
+        int i;
+
+        entries = kmalloc(MAX_STACK_TRACE_DEPTH * sizeof(*entries), GFP_KERNEL);
+        if (!entries)
+                return -ENOMEM;
+
+        trace.nr_entries        = 0;
+        trace.max_entries       = MAX_STACK_TRACE_DEPTH;
+        trace.entries           = entries;
+        trace.skip              = 0;
+        save_stack_trace_tsk(task, &trace);
+
+        for (i = 0; i < trace.nr_entries; i++) {
+                seq_printf(m, "[<%p>] %pS\n",
+                           (void *)entries[i], (void *)entries[i]);
+        }
+        kfree(entries);
+
+        return 0;
+}
+#endif
+
 #ifdef CONFIG_SCHEDSTATS
 /*
  * Provides /proc/PID/schedstat
@@ -1186,8 +1215,6 @@ static int sched_show(struct seq_file *m, void *v)
         struct inode *inode = m->private;
         struct task_struct *p;
 
-        WARN_ON(!inode);
-
         p = get_proc_task(inode);
         if (!p)
                 return -ESRCH;
@@ -1205,8 +1232,6 @@ sched_write(struct file *file, const char __user *buf,
         struct inode *inode = file->f_path.dentry->d_inode;
         struct task_struct *p;
 
-        WARN_ON(!inode);
-
         p = get_proc_task(inode);
         if (!p)
                 return -ESRCH;
@@ -1974,13 +1999,11 @@ static struct dentry *proc_pident_lookup(struct inode *dir,
                                          const struct pid_entry *ents,
                                          unsigned int nents)
 {
-        struct inode *inode;
         struct dentry *error;
         struct task_struct *task = get_proc_task(dir);
         const struct pid_entry *p, *last;
 
         error = ERR_PTR(-ENOENT);
-        inode = NULL;
 
         if (!task)
                 goto out_no_task;
@@ -2136,12 +2159,12 @@ static const struct file_operations proc_pid_attr_operations = {
 };
 
 static const struct pid_entry attr_dir_stuff[] = {
-        REG("current",    S_IRUGO|S_IWUGO, pid_attr),
-        REG("prev",       S_IRUGO,         pid_attr),
-        REG("exec",       S_IRUGO|S_IWUGO, pid_attr),
-        REG("fscreate",   S_IRUGO|S_IWUGO, pid_attr),
-        REG("keycreate",  S_IRUGO|S_IWUGO, pid_attr),
-        REG("sockcreate", S_IRUGO|S_IWUGO, pid_attr),
+        REG("current",    S_IRUGO|S_IWUGO, proc_pid_attr_operations),
+        REG("prev",       S_IRUGO,         proc_pid_attr_operations),
+        REG("exec",       S_IRUGO|S_IWUGO, proc_pid_attr_operations),
+        REG("fscreate",   S_IRUGO|S_IWUGO, proc_pid_attr_operations),
+        REG("keycreate",  S_IRUGO|S_IWUGO, proc_pid_attr_operations),
+        REG("sockcreate", S_IRUGO|S_IWUGO, proc_pid_attr_operations),
 };
 
 static int proc_attr_dir_readdir(struct file * filp,
@@ -2461,74 +2484,77 @@ static const struct file_operations proc_task_operations;
 static const struct inode_operations proc_task_inode_operations;
 
 static const struct pid_entry tgid_base_stuff[] = {
-        DIR("task",       S_IRUGO|S_IXUGO, task),
-        DIR("fd",         S_IRUSR|S_IXUSR, fd),
-        DIR("fdinfo",     S_IRUSR|S_IXUSR, fdinfo),
+        DIR("task",       S_IRUGO|S_IXUGO, proc_task_inode_operations, proc_task_operations),
+        DIR("fd",         S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations),
+        DIR("fdinfo",     S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fdinfo_operations),
 #ifdef CONFIG_NET
-        DIR("net",        S_IRUGO|S_IXUGO, net),
+        DIR("net",        S_IRUGO|S_IXUGO, proc_net_inode_operations, proc_net_operations),
 #endif
-        REG("environ",    S_IRUSR, environ),
-        INF("auxv",       S_IRUSR, pid_auxv),
-        ONE("status",     S_IRUGO, pid_status),
-        ONE("personality", S_IRUSR, pid_personality),
-        INF("limits",     S_IRUSR, pid_limits),
+        REG("environ",    S_IRUSR, proc_environ_operations),
+        INF("auxv",       S_IRUSR, proc_pid_auxv),
+        ONE("status",     S_IRUGO, proc_pid_status),
+        ONE("personality", S_IRUSR, proc_pid_personality),
+        INF("limits",     S_IRUSR, proc_pid_limits),
 #ifdef CONFIG_SCHED_DEBUG
-        REG("sched",      S_IRUGO|S_IWUSR, pid_sched),
+        REG("sched",      S_IRUGO|S_IWUSR, proc_pid_sched_operations),
 #endif
 #ifdef CONFIG_HAVE_ARCH_TRACEHOOK
-        INF("syscall",    S_IRUSR, pid_syscall),
+        INF("syscall",    S_IRUSR, proc_pid_syscall),
 #endif
-        INF("cmdline",    S_IRUGO, pid_cmdline),
-        ONE("stat",       S_IRUGO, tgid_stat),
-        ONE("statm",      S_IRUGO, pid_statm),
-        REG("maps",       S_IRUGO, maps),
+        INF("cmdline",    S_IRUGO, proc_pid_cmdline),
+        ONE("stat",       S_IRUGO, proc_tgid_stat),
+        ONE("statm",      S_IRUGO, proc_pid_statm),
+        REG("maps",       S_IRUGO, proc_maps_operations),
 #ifdef CONFIG_NUMA
-        REG("numa_maps",  S_IRUGO, numa_maps),
+        REG("numa_maps",  S_IRUGO, proc_numa_maps_operations),
 #endif
-        REG("mem",        S_IRUSR|S_IWUSR, mem),
-        LNK("cwd",        cwd),
-        LNK("root",       root),
-        LNK("exe",        exe),
-        REG("mounts",     S_IRUGO, mounts),
-        REG("mountinfo",  S_IRUGO, mountinfo),
-        REG("mountstats", S_IRUSR, mountstats),
+        REG("mem",        S_IRUSR|S_IWUSR, proc_mem_operations),
+        LNK("cwd",        proc_cwd_link),
+        LNK("root",       proc_root_link),
+        LNK("exe",        proc_exe_link),
+        REG("mounts",     S_IRUGO, proc_mounts_operations),
+        REG("mountinfo",  S_IRUGO, proc_mountinfo_operations),
+        REG("mountstats", S_IRUSR, proc_mountstats_operations),
 #ifdef CONFIG_PROC_PAGE_MONITOR
-        REG("clear_refs", S_IWUSR, clear_refs),
-        REG("smaps",      S_IRUGO, smaps),
-        REG("pagemap",    S_IRUSR, pagemap),
+        REG("clear_refs", S_IWUSR, proc_clear_refs_operations),
+        REG("smaps",      S_IRUGO, proc_smaps_operations),
+        REG("pagemap",    S_IRUSR, proc_pagemap_operations),
 #endif
 #ifdef CONFIG_SECURITY
-        DIR("attr",       S_IRUGO|S_IXUGO, attr_dir),
+        DIR("attr",       S_IRUGO|S_IXUGO, proc_attr_dir_inode_operations, proc_attr_dir_operations),
 #endif
 #ifdef CONFIG_KALLSYMS
-        INF("wchan",      S_IRUGO, pid_wchan),
+        INF("wchan",      S_IRUGO, proc_pid_wchan),
+#endif
+#ifdef CONFIG_STACKTRACE
+        ONE("stack",      S_IRUSR, proc_pid_stack),
 #endif
 #ifdef CONFIG_SCHEDSTATS
-        INF("schedstat",  S_IRUGO, pid_schedstat),
+        INF("schedstat",  S_IRUGO, proc_pid_schedstat),
 #endif
 #ifdef CONFIG_LATENCYTOP
-        REG("latency",  S_IRUGO, lstats),
+        REG("latency",  S_IRUGO, proc_lstats_operations),
 #endif
 #ifdef CONFIG_PROC_PID_CPUSET
-        REG("cpuset",     S_IRUGO, cpuset),
+        REG("cpuset",     S_IRUGO, proc_cpuset_operations),
 #endif
 #ifdef CONFIG_CGROUPS
-        REG("cgroup",  S_IRUGO, cgroup),
+        REG("cgroup",  S_IRUGO, proc_cgroup_operations),
 #endif
-        INF("oom_score",  S_IRUGO, oom_score),
-        REG("oom_adj",    S_IRUGO|S_IWUSR, oom_adjust),
+        INF("oom_score",  S_IRUGO, proc_oom_score),
+        REG("oom_adj",    S_IRUGO|S_IWUSR, proc_oom_adjust_operations),
 #ifdef CONFIG_AUDITSYSCALL
-        REG("loginuid",   S_IWUSR|S_IRUGO, loginuid),
-        REG("sessionid",  S_IRUGO, sessionid),
+        REG("loginuid",   S_IWUSR|S_IRUGO, proc_loginuid_operations),
+        REG("sessionid",  S_IRUGO, proc_sessionid_operations),
 #endif
 #ifdef CONFIG_FAULT_INJECTION
-        REG("make-it-fail", S_IRUGO|S_IWUSR, fault_inject),
+        REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations),
 #endif
 #if defined(USE_ELF_CORE_DUMP) && defined(CONFIG_ELF_CORE)
-        REG("coredump_filter", S_IRUGO|S_IWUSR, coredump_filter),
+        REG("coredump_filter", S_IRUGO|S_IWUSR, proc_coredump_filter_operations),
 #endif
 #ifdef CONFIG_TASK_IO_ACCOUNTING
-        INF("io",       S_IRUGO, tgid_io_accounting),
+        INF("io",       S_IRUGO, proc_tgid_io_accounting),
 #endif
 };
 
@@ -2801,66 +2827,69 @@ out_no_task:
  * Tasks
  */
 static const struct pid_entry tid_base_stuff[] = {
-        DIR("fd",        S_IRUSR|S_IXUSR, fd),
-        DIR("fdinfo",    S_IRUSR|S_IXUSR, fdinfo),
-        REG("environ",   S_IRUSR, environ),
-        INF("auxv",      S_IRUSR, pid_auxv),
-        ONE("status",    S_IRUGO, pid_status),
-        ONE("personality", S_IRUSR, pid_personality),
-        INF("limits",    S_IRUSR, pid_limits),
+        DIR("fd",        S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations),
+        DIR("fdinfo",    S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fd_operations),
+        REG("environ",   S_IRUSR, proc_environ_operations),
+        INF("auxv",      S_IRUSR, proc_pid_auxv),
+        ONE("status",    S_IRUGO, proc_pid_status),
+        ONE("personality", S_IRUSR, proc_pid_personality),
+        INF("limits",    S_IRUSR, proc_pid_limits),
 #ifdef CONFIG_SCHED_DEBUG
-        REG("sched",     S_IRUGO|S_IWUSR, pid_sched),
+        REG("sched",     S_IRUGO|S_IWUSR, proc_pid_sched_operations),
 #endif
 #ifdef CONFIG_HAVE_ARCH_TRACEHOOK
-        INF("syscall",   S_IRUSR, pid_syscall),
+        INF("syscall",   S_IRUSR, proc_pid_syscall),
 #endif
-        INF("cmdline",   S_IRUGO, pid_cmdline),
-        ONE("stat",      S_IRUGO, tid_stat),
-        ONE("statm",     S_IRUGO, pid_statm),
-        REG("maps",      S_IRUGO, maps),
+        INF("cmdline",   S_IRUGO, proc_pid_cmdline),
+        ONE("stat",      S_IRUGO, proc_tid_stat),
+        ONE("statm",     S_IRUGO, proc_pid_statm),
+        REG("maps",      S_IRUGO, proc_maps_operations),
 #ifdef CONFIG_NUMA
-        REG("numa_maps", S_IRUGO, numa_maps),
+        REG("numa_maps", S_IRUGO, proc_numa_maps_operations),
 #endif
-        REG("mem",       S_IRUSR|S_IWUSR, mem),
-        LNK("cwd",       cwd),
-        LNK("root",      root),
-        LNK("exe",       exe),
-        REG("mounts",    S_IRUGO, mounts),
-        REG("mountinfo",  S_IRUGO, mountinfo),
+        REG("mem",       S_IRUSR|S_IWUSR, proc_mem_operations),
+        LNK("cwd",       proc_cwd_link),
+        LNK("root",      proc_root_link),
+        LNK("exe",       proc_exe_link),
+        REG("mounts",    S_IRUGO, proc_mounts_operations),
+        REG("mountinfo",  S_IRUGO, proc_mountinfo_operations),
 #ifdef CONFIG_PROC_PAGE_MONITOR
-        REG("clear_refs", S_IWUSR, clear_refs),
-        REG("smaps",     S_IRUGO, smaps),
-        REG("pagemap",    S_IRUSR, pagemap),
+        REG("clear_refs", S_IWUSR, proc_clear_refs_operations),
+        REG("smaps",     S_IRUGO, proc_smaps_operations),
+        REG("pagemap",    S_IRUSR, proc_pagemap_operations),
 #endif
 #ifdef CONFIG_SECURITY
-        DIR("attr",      S_IRUGO|S_IXUGO, attr_dir),
+        DIR("attr",      S_IRUGO|S_IXUGO, proc_attr_dir_inode_operations, proc_attr_dir_operations),
 #endif
 #ifdef CONFIG_KALLSYMS
-        INF("wchan",     S_IRUGO, pid_wchan),
+        INF("wchan",     S_IRUGO, proc_pid_wchan),
+#endif
+#ifdef CONFIG_STACKTRACE
+        ONE("stack",      S_IRUSR, proc_pid_stack),
 #endif
 #ifdef CONFIG_SCHEDSTATS
-        INF("schedstat", S_IRUGO, pid_schedstat),
+        INF("schedstat", S_IRUGO, proc_pid_schedstat),
 #endif
 #ifdef CONFIG_LATENCYTOP
-        REG("latency",  S_IRUGO, lstats),
+        REG("latency",  S_IRUGO, proc_lstats_operations),
 #endif
 #ifdef CONFIG_PROC_PID_CPUSET
-        REG("cpuset",    S_IRUGO, cpuset),
+        REG("cpuset",    S_IRUGO, proc_cpuset_operations),
 #endif
 #ifdef CONFIG_CGROUPS
-        REG("cgroup",  S_IRUGO, cgroup),
+        REG("cgroup",  S_IRUGO, proc_cgroup_operations),
 #endif
-        INF("oom_score", S_IRUGO, oom_score),
-        REG("oom_adj",   S_IRUGO|S_IWUSR, oom_adjust),
+        INF("oom_score", S_IRUGO, proc_oom_score),
+        REG("oom_adj",   S_IRUGO|S_IWUSR, proc_oom_adjust_operations),
 #ifdef CONFIG_AUDITSYSCALL
-        REG("loginuid",  S_IWUSR|S_IRUGO, loginuid),
-        REG("sessionid",  S_IRUSR, sessionid),
+        REG("loginuid",  S_IWUSR|S_IRUGO, proc_loginuid_operations),
+        REG("sessionid",  S_IRUSR, proc_sessionid_operations),
 #endif
 #ifdef CONFIG_FAULT_INJECTION
-        REG("make-it-fail", S_IRUGO|S_IWUSR, fault_inject),
+        REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations),
 #endif
 #ifdef CONFIG_TASK_IO_ACCOUNTING
-        INF("io",       S_IRUGO, tid_io_accounting),
+        INF("io",       S_IRUGO, proc_tid_io_accounting),
 #endif
 };
 
diff --git a/fs/proc/generic.c b/fs/proc/generic.c
index 60a359b35582..db7fa5cab988 100644
--- a/fs/proc/generic.c
+++ b/fs/proc/generic.c
@@ -14,7 +14,6 @@
 #include <linux/stat.h>
 #include <linux/module.h>
 #include <linux/mount.h>
-#include <linux/smp_lock.h>
 #include <linux/init.h>
 #include <linux/idr.h>
 #include <linux/namei.h>
@@ -379,7 +378,6 @@ struct dentry *proc_lookup_de(struct proc_dir_entry *de, struct inode *dir,
         struct inode *inode = NULL;
         int error = -ENOENT;
 
-        lock_kernel();
         spin_lock(&proc_subdir_lock);
         for (de = de->subdir; de ; de = de->next) {
                 if (de->namelen != dentry->d_name.len)
@@ -397,7 +395,6 @@ struct dentry *proc_lookup_de(struct proc_dir_entry *de, struct inode *dir,
         }
         spin_unlock(&proc_subdir_lock);
 out_unlock:
-        unlock_kernel();
 
         if (inode) {
                 dentry->d_op = &proc_dentry_operations;
@@ -432,8 +429,6 @@ int proc_readdir_de(struct proc_dir_entry *de, struct file *filp, void *dirent,
         struct inode *inode = filp->f_path.dentry->d_inode;
         int ret = 0;
 
-        lock_kernel();
-
         ino = inode->i_ino;
         i = filp->f_pos;
         switch (i) {
@@ -487,7 +482,7 @@ int proc_readdir_de(struct proc_dir_entry *de, struct file *filp, void *dirent,
                         spin_unlock(&proc_subdir_lock);
         }
         ret = 1;
-out:    unlock_kernel();
+out:
         return ret;     
 }
 
@@ -504,6 +499,7 @@ int proc_readdir(struct file *filp, void *dirent, filldir_t filldir)
  * the /proc directory.
  */
 static const struct file_operations proc_dir_operations = {
+        .llseek                 = generic_file_llseek,
         .read                   = generic_read_dir,
         .readdir                = proc_readdir,
 };
diff --git a/fs/proc/inode.c b/fs/proc/inode.c
index 2543fd00c658..3e76bb9b3ad6 100644
--- a/fs/proc/inode.c
+++ b/fs/proc/inode.c
@@ -35,16 +35,13 @@ struct proc_dir_entry *de_get(struct proc_dir_entry *de)
  */
 void de_put(struct proc_dir_entry *de)
 {
-        lock_kernel();
         if (!atomic_read(&de->count)) {
                 printk("de_put: entry %s already free!\n", de->name);
-                unlock_kernel();
                 return;
         }
 
         if (atomic_dec_and_test(&de->count))
                 free_proc_entry(de);
-        unlock_kernel();
 }
 
 /*
diff --git a/fs/proc/proc_net.c b/fs/proc/proc_net.c
index 7bc296f424ae..04d1270f1c38 100644
--- a/fs/proc/proc_net.c
+++ b/fs/proc/proc_net.c
@@ -18,7 +18,6 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/bitops.h>
-#include <linux/smp_lock.h>
 #include <linux/mount.h>
 #include <linux/nsproxy.h>
 #include <net/net_namespace.h>
@@ -172,6 +171,7 @@ static int proc_tgid_net_readdir(struct file *filp, void *dirent,
 }
 
 const struct file_operations proc_net_operations = {
+        .llseek         = generic_file_llseek,
         .read           = generic_read_dir,
         .readdir        = proc_tgid_net_readdir,
 };
diff --git a/fs/proc/root.c b/fs/proc/root.c
index 7761602af9de..f6299a25594e 100644
--- a/fs/proc/root.c
+++ b/fs/proc/root.c
@@ -16,7 +16,6 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/bitops.h>
-#include <linux/smp_lock.h>
 #include <linux/mount.h>
 #include <linux/pid_namespace.h>
 
@@ -162,17 +161,12 @@ static int proc_root_readdir(struct file * filp,
         unsigned int nr = filp->f_pos;
         int ret;
 
-        lock_kernel();
-
         if (nr < FIRST_PROCESS_ENTRY) {
                 int error = proc_readdir(filp, dirent, filldir);
-                if (error <= 0) {
-                        unlock_kernel();
+                if (error <= 0)
                         return error;
-                }
                 filp->f_pos = FIRST_PROCESS_ENTRY;
         }
-        unlock_kernel();
 
         ret = proc_pid_readdir(filp, dirent, filldir);
         return ret;
diff --git a/fs/proc/task_nommu.c b/fs/proc/task_nommu.c
index 219bd79ea894..d4a8be32b902 100644
--- a/fs/proc/task_nommu.c
+++ b/fs/proc/task_nommu.c
@@ -9,7 +9,7 @@
 
 /*
  * Logic: we've got two memory sums for each process, "shared", and
- * "non-shared". Shared memory may get counted more then once, for
+ * "non-shared". Shared memory may get counted more than once, for
  * each process that owns it. Non-shared memory is counted
  * accurately.
  */
diff --git a/fs/super.c b/fs/super.c
index ddba069d7a99..cb20744ec789 100644
--- a/fs/super.c
+++ b/fs/super.c
@@ -38,6 +38,7 @@
 #include <linux/kobject.h>
 #include <linux/mutex.h>
 #include <linux/file.h>
+#include <linux/async.h>
 #include <asm/uaccess.h>
 #include "internal.h"
 
@@ -71,6 +72,7 @@ static struct super_block *alloc_super(struct file_system_type *type)
                 INIT_HLIST_HEAD(&s->s_anon);
                 INIT_LIST_HEAD(&s->s_inodes);
                 INIT_LIST_HEAD(&s->s_dentry_lru);
+                INIT_LIST_HEAD(&s->s_async_list);
                 init_rwsem(&s->s_umount);
                 mutex_init(&s->s_lock);
                 lockdep_set_class(&s->s_umount, &type->s_umount_key);
@@ -289,11 +291,18 @@ void generic_shutdown_super(struct super_block *sb)
 {
         const struct super_operations *sop = sb->s_op;
 
+
         if (sb->s_root) {
                 shrink_dcache_for_umount(sb);
                 fsync_super(sb);
                 lock_super(sb);
                 sb->s_flags &= ~MS_ACTIVE;
+
+                /*
+                 * wait for asynchronous fs operations to finish before going further
+                 */
+                async_synchronize_full_special(&sb->s_async_list);
+
                 /* bad name - it should be evict_inodes() */
                 invalidate_inodes(sb);
                 lock_kernel();
@@ -449,6 +458,7 @@ void sync_filesystems(int wait)
                 if (sb->s_flags & MS_RDONLY)
                         continue;
                 sb->s_need_sync_fs = 1;
+                async_synchronize_full_special(&sb->s_async_list);
         }
 
 restart:
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index 91ceeda7e5bf..e35b54d5059d 100644
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -40,7 +40,7 @@ config UBIFS_FS_ZLIB
         depends on UBIFS_FS
         default y
         help
-          Zlib copresses better then LZO but it is slower. Say 'Y' if unsure.
+          Zlib compresses better than LZO but it is slower. Say 'Y' if unsure.
 
 # Debugging-related stuff
 config UBIFS_FS_DEBUG
diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c
index 0e5e54d82924..175f9c590b77 100644
--- a/fs/ubifs/budget.c
+++ b/fs/ubifs/budget.c
@@ -142,7 +142,7 @@ static long long get_liability(struct ubifs_info *c)
  *
  * This function is called when an operation cannot be budgeted because there
  * is supposedly no free space. But in most cases there is some free space:
- *   o budgeting is pessimistic, so it always budgets more then it is actually
+ *   o budgeting is pessimistic, so it always budgets more than it is actually
  *     needed, so shrinking the liability is one way to make free space - the
  *     cached data will take less space then it was budgeted for;
  *   o GC may turn some dark space into free space (budgeting treats dark space
@@ -606,7 +606,7 @@ void ubifs_release_budget(struct ubifs_info *c, struct ubifs_budget_req *req)
  * @c: UBIFS file-system description object
  *
  * This function converts budget which was allocated for a new page of data to
- * the budget of changing an existing page of data. The latter is smaller then
+ * the budget of changing an existing page of data. The latter is smaller than
  * the former, so this function only does simple re-calculation and does not
  * involve any write-back.
  */
diff --git a/fs/ubifs/gc.c b/fs/ubifs/gc.c
index 0bef6501d58a..9832f9abe28e 100644
--- a/fs/ubifs/gc.c
+++ b/fs/ubifs/gc.c
@@ -45,7 +45,7 @@
 #define SMALL_NODE_WM  UBIFS_MAX_DENT_NODE_SZ
 
 /*
- * GC may need to move more then one LEB to make progress. The below constants
+ * GC may need to move more than one LEB to make progress. The below constants
  * define "soft" and "hard" limits on the number of LEBs the garbage collector
  * may move.
  */
diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c
index 10ae25b7d1db..9b7c54e0cd2a 100644
--- a/fs/ubifs/journal.c
+++ b/fs/ubifs/journal.c
@@ -191,7 +191,7 @@ again:
         if (wbuf->lnum != -1 && avail >= len) {
                 /*
                  * Someone else has switched the journal head and we have
-                 * enough space now. This happens when more then one process is
+                 * enough space now. This happens when more than one process is
                  * trying to write to the same journal head at the same time.
                  */
                 dbg_jnl("return LEB %d back, already have LEB %d:%d",
diff --git a/fs/ubifs/shrinker.c b/fs/ubifs/shrinker.c
index f248533841a2..e7bab52a1410 100644
--- a/fs/ubifs/shrinker.c
+++ b/fs/ubifs/shrinker.c
@@ -151,7 +151,7 @@ static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention)
  * @contention: if any contention, this is set to %1
  *
  * This function walks the list of mounted UBIFS file-systems and frees clean
- * znodes which are older then @age, until at least @nr znodes are freed.
+ * znodes which are older than @age, until at least @nr znodes are freed.
  * Returns the number of freed znodes.
  */
 static int shrink_tnc_trees(int nr, int age, int *contention)
diff --git a/fs/xfs/linux-2.6/xfs_super.c b/fs/xfs/linux-2.6/xfs_super.c
index 36f6cc703ef2..be846d606ae8 100644
--- a/fs/xfs/linux-2.6/xfs_super.c
+++ b/fs/xfs/linux-2.6/xfs_super.c
@@ -1348,7 +1348,7 @@ xfs_finish_flags(
 {
         int                     ronly = (mp->m_flags & XFS_MOUNT_RDONLY);
 
-        /* Fail a mount where the logbuf is smaller then the log stripe */
+        /* Fail a mount where the logbuf is smaller than the log stripe */
         if (xfs_sb_version_haslogv2(&mp->m_sb)) {
                 if (mp->m_logbsize <= 0 &&
                     mp->m_sb.sb_logsunit > XLOG_BIG_RECORD_BSIZE) {
diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index a597207e2835..1954c9d1d012 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -333,8 +333,8 @@ struct acpi_integer_overlay {
 #define ACPI_INSERT_BITS(target, mask, source)          target = ((target & (~(mask))) | (source & mask))
 
 /*
- * An struct acpi_namespace_node can appear in some contexts
- * where a pointer to an union acpi_operand_object can also
+ * A struct acpi_namespace_node can appear in some contexts
+ * where a pointer to a union acpi_operand_object can also
  * appear. This macro is used to distinguish them.
  *
  * The "Descriptor" field is the first field in both structures.
diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index 7220361790b3..8222e8de0d1c 100644
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -467,7 +467,7 @@ typedef u32 acpi_object_type;
 
 /*
  * These are special object types that never appear in
- * a Namespace node, only in an union acpi_operand_object
+ * a Namespace node, only in a union acpi_operand_object
  */
 #define ACPI_TYPE_LOCAL_EXTRA           0x1C
 #define ACPI_TYPE_LOCAL_DATA            0x1D
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index a3323f337e4d..12e9a2957caf 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -371,3 +371,5 @@ unifdef-y += xattr.h
 unifdef-y += xfrm.h
 
 objhdr-y += version.h
+header-y += wimax.h
+header-y += wimax/
diff --git a/include/linux/async.h b/include/linux/async.h
new file mode 100644
index 000000000000..c4ecacd0b327
--- /dev/null
+++ b/include/linux/async.h
@@ -0,0 +1,25 @@
+/*
+ * async.h: Asynchronous function calls for boot performance
+ *
+ * (C) Copyright 2009 Intel Corporation
+ * Author: Arjan van de Ven <arjan@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+typedef u64 async_cookie_t;
+typedef void (async_func_ptr) (void *data, async_cookie_t cookie);
+
+extern async_cookie_t async_schedule(async_func_ptr *ptr, void *data);
+extern async_cookie_t async_schedule_special(async_func_ptr *ptr, void *data, struct list_head *list);
+extern void async_synchronize_full(void);
+extern void async_synchronize_full_special(struct list_head *list);
+extern void async_synchronize_cookie(async_cookie_t cookie);
+extern void async_synchronize_cookie_special(async_cookie_t cookie, struct list_head *list);
+
diff --git a/arch/avr32/include/asm/atmel-mci.h b/include/linux/atmel-mci.h
index 59f3fadd0b68..2a2213eefd85 100644
--- a/arch/avr32/include/asm/atmel-mci.h
+++ b/include/linux/atmel-mci.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_AVR32_ATMEL_MCI_H
-#define __ASM_AVR32_ATMEL_MCI_H
+#ifndef __LINUX_ATMEL_MCI_H
+#define __LINUX_ATMEL_MCI_H
 
 #define ATMEL_MCI_MAX_NR_SLOTS  2
 
@@ -36,4 +36,4 @@ struct mci_platform_data {
         struct mci_slot_pdata   slot[ATMEL_MCI_MAX_NR_SLOTS];
 };
 
-#endif /* __ASM_AVR32_ATMEL_MCI_H */
+#endif /* __LINUX_ATMEL_MCI_H */
diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h
index e1a6c046cea3..23936b16426b 100644
--- a/include/linux/debugfs.h
+++ b/include/linux/debugfs.h
@@ -63,6 +63,8 @@ struct dentry *debugfs_create_x16(const char *name, mode_t mode,
                                   struct dentry *parent, u16 *value);
 struct dentry *debugfs_create_x32(const char *name, mode_t mode,
                                   struct dentry *parent, u32 *value);
+struct dentry *debugfs_create_size_t(const char *name, mode_t mode,
+                                     struct dentry *parent, size_t *value);
 struct dentry *debugfs_create_bool(const char *name, mode_t mode,
                                   struct dentry *parent, u32 *value);
 
diff --git a/include/linux/fs.h b/include/linux/fs.h
index d7eba77f666e..e38a64d71eff 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1184,6 +1184,11 @@ struct super_block {
          * generic_show_options()
          */
         char *s_options;
+
+        /*
+         * storage for asynchronous operations
+         */
+        struct list_head s_async_list;
 };
 
 extern struct timespec current_fs_time(struct super_block *sb);
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 33a5992d4936..20873d402467 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -393,11 +393,7 @@ static inline void i2c_set_adapdata(struct i2c_adapter *dev, void *data)
 #define I2C_CLASS_TV_ANALOG     (1<<1)  /* bttv + friends */
 #define I2C_CLASS_TV_DIGITAL    (1<<2)  /* dvb cards */
 #define I2C_CLASS_DDC           (1<<3)  /* DDC bus on graphics adapters */
-#define I2C_CLASS_CAM_ANALOG    (1<<4)  /* camera with analog CCD */
-#define I2C_CLASS_CAM_DIGITAL   (1<<5)  /* most webcams */
-#define I2C_CLASS_SOUND         (1<<6)  /* sound devices */
 #define I2C_CLASS_SPD           (1<<7)  /* SPD EEPROMs and similar */
-#define I2C_CLASS_ALL           (UINT_MAX) /* all of the above */
 
 /* i2c_client_address_data is the struct for holding default client
  * addresses for a driver and for the parameters supplied on the
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index eae26bb6430a..64433eb411d7 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -83,7 +83,7 @@ typedef enum {
  * @datbuf:     data buffer - if NULL only oob data are read/written
  * @oobbuf:     oob data buffer
  *
- * Note, it is allowed to read more then one OOB area at one go, but not write.
+ * Note, it is allowed to read more than one OOB area at one go, but not write.
  * The interface assumes that the OOB write requests program only one page's
  * OOB area.
  */
diff --git a/include/linux/ncp_fs.h b/include/linux/ncp_fs.h
index 9f2d76347f19..f69e66d151cc 100644
--- a/include/linux/ncp_fs.h
+++ b/include/linux/ncp_fs.h
@@ -87,7 +87,7 @@ struct ncp_objectname_ioctl
 #define NCP_AUTH_NDS    0x32
         int             auth_type;
         size_t          object_name_len;
-        void __user *   object_name;    /* an userspace data, in most cases user name */
+        void __user *   object_name;    /* a userspace data, in most cases user name */
 };
 
 struct ncp_privatedata_ioctl
diff --git a/include/linux/oxu210hp.h b/include/linux/oxu210hp.h
new file mode 100644
index 000000000000..0bf96eae5389
--- /dev/null
+++ b/include/linux/oxu210hp.h
@@ -0,0 +1,7 @@
+/* platform data for the OXU210HP HCD */
+
+struct oxu210hp_platform_data {
+        unsigned int bus16:1;
+        unsigned int use_hcd_otg:1;
+        unsigned int use_hcd_sph:1;
+};
diff --git a/include/linux/qnx4_fs.h b/include/linux/qnx4_fs.h
index 34a196ee7941..787d19ea9f46 100644
--- a/include/linux/qnx4_fs.h
+++ b/include/linux/qnx4_fs.h
@@ -2,14 +2,12 @@
  *  Name                         : qnx4_fs.h
  *  Author                       : Richard Frowijn
  *  Function                     : qnx4 global filesystem definitions
- *  Version                      : 1.0.2
- *  Last modified                : 2000-01-31
- *
  *  History                      : 23-03-1998 created
  */
 #ifndef _LINUX_QNX4_FS_H
 #define _LINUX_QNX4_FS_H
 
+#include <linux/types.h>
 #include <linux/qnxtypes.h>
 #include <linux/magic.h>
 
diff --git a/include/linux/qnxtypes.h b/include/linux/qnxtypes.h
index a3eb1137857b..bebbe5cc4fb8 100644
--- a/include/linux/qnxtypes.h
+++ b/include/linux/qnxtypes.h
@@ -2,9 +2,6 @@
  *  Name                         : qnxtypes.h
  *  Author                       : Richard Frowijn
  *  Function                     : standard qnx types
- *  Version                      : 1.0.2
- *  Last modified                : 2000-01-06
- *
  *  History                      : 22-03-1998 created
  *
  */
@@ -12,6 +9,8 @@
 #ifndef _QNX4TYPES_H
 #define _QNX4TYPES_H
 
+#include <linux/types.h>
+
 typedef __le16 qnx4_nxtnt_t;
 typedef __u8  qnx4_ftype_t;
 
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 82229317753d..68bb1c501d0d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -327,9 +327,9 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
  * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
  * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
  * @len: size of rx and tx buffers (in bytes)
- * @speed_hz: Select a speed other then the device default for this
+ * @speed_hz: Select a speed other than the device default for this
  *      transfer. If 0 the default (from @spi_device) is used.
- * @bits_per_word: select a bits_per_word other then the device default
+ * @bits_per_word: select a bits_per_word other than the device default
  *      for this transfer. If 0 the default (from @spi_device) is used.
  * @cs_change: affects chipselect after this transfer completes
  * @delay_usecs: microseconds to delay after this transfer before
diff --git a/include/linux/types.h b/include/linux/types.h
index 3b864f2d9560..712ca53bc348 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -176,10 +176,9 @@ typedef __u16 __bitwise __le16;
 typedef __u16 __bitwise __be16;
 typedef __u32 __bitwise __le32;
 typedef __u32 __bitwise __be32;
-#if defined(__GNUC__)
 typedef __u64 __bitwise __le64;
 typedef __u64 __bitwise __be64;
-#endif
+
 typedef __u16 __bitwise __sum16;
 typedef __u32 __bitwise __wsum;
 
diff --git a/include/linux/usb.h b/include/linux/usb.h
index f72aa51f7bcd..85ee9be9361e 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -108,6 +108,7 @@ enum usb_interface_condition {
  *      (in probe()), bound to a driver, or unbinding (in disconnect())
  * @is_active: flag set when the interface is bound and not suspended.
  * @sysfs_files_created: sysfs attributes exist
+ * @ep_devs_created: endpoint child pseudo-devices exist
  * @unregistering: flag set when the interface is being unregistered
  * @needs_remote_wakeup: flag set when the driver requires remote-wakeup
  *      capability during autosuspend.
@@ -120,6 +121,11 @@ enum usb_interface_condition {
  *      to the sysfs representation for that device.
  * @pm_usage_cnt: PM usage counter for this interface; autosuspend is not
  *      allowed unless the counter is 0.
+ * @reset_ws: Used for scheduling resets from atomic context.
+ * @reset_running: set to 1 if the interface is currently running a
+ *      queued reset so that usb_cancel_queued_reset() doesn't try to
+ *      remove from the workqueue when running inside the worker
+ *      thread. See __usb_queue_reset_device().
  *
  * USB device drivers attach to interfaces on a physical device.  Each
  * interface encapsulates a single high level function, such as feeding
@@ -164,14 +170,17 @@ struct usb_interface {
         enum usb_interface_condition condition;         /* state of binding */
         unsigned is_active:1;           /* the interface is not suspended */
         unsigned sysfs_files_created:1; /* the sysfs attributes exist */
+        unsigned ep_devs_created:1;     /* endpoint "devices" exist */
         unsigned unregistering:1;       /* unregistration is in progress */
         unsigned needs_remote_wakeup:1; /* driver requires remote wakeup */
         unsigned needs_altsetting0:1;   /* switch to altsetting 0 is pending */
         unsigned needs_binding:1;       /* needs delayed unbind/rebind */
+        unsigned reset_running:1;
 
         struct device dev;              /* interface specific device info */
         struct device *usb_dev;
         int pm_usage_cnt;               /* usage counter for autosuspend */
+        struct work_struct reset_ws;    /* for resets in atomic context */
 };
 #define to_usb_interface(d) container_of(d, struct usb_interface, dev)
 #define interface_to_usbdev(intf) \
@@ -329,7 +338,7 @@ struct usb_bus {
 #endif
         struct device *dev;             /* device for this bus */
 
-#if defined(CONFIG_USB_MON)
+#if defined(CONFIG_USB_MON) || defined(CONFIG_USB_MON_MODULE)
         struct mon_bus *mon_bus;        /* non-null when associated */
         int monitored;                  /* non-zero when monitored */
 #endif
@@ -398,6 +407,7 @@ struct usb_tt;
  * @urbnum: number of URBs submitted for the whole device
  * @active_duration: total time device is not suspended
  * @autosuspend: for delayed autosuspends
+ * @autoresume: for autoresumes requested while in_interrupt
  * @pm_mutex: protects PM operations
  * @last_busy: time of last use
  * @autosuspend_delay: in jiffies
@@ -476,6 +486,7 @@ struct usb_device {
 
 #ifdef CONFIG_PM
         struct delayed_work autosuspend;
+        struct work_struct autoresume;
         struct mutex pm_mutex;
 
         unsigned long last_busy;
@@ -505,6 +516,7 @@ extern int usb_lock_device_for_reset(struct usb_device *udev,
 
 /* USB port reset for device reinitialization */
 extern int usb_reset_device(struct usb_device *dev);
+extern void usb_queue_reset_device(struct usb_interface *dev);
 
 extern struct usb_device *usb_find_device(u16 vendor_id, u16 product_id);
 
@@ -513,6 +525,8 @@ extern struct usb_device *usb_find_device(u16 vendor_id, u16 product_id);
 extern int usb_autopm_set_interface(struct usb_interface *intf);
 extern int usb_autopm_get_interface(struct usb_interface *intf);
 extern void usb_autopm_put_interface(struct usb_interface *intf);
+extern int usb_autopm_get_interface_async(struct usb_interface *intf);
+extern void usb_autopm_put_interface_async(struct usb_interface *intf);
 
 static inline void usb_autopm_enable(struct usb_interface *intf)
 {
@@ -539,8 +553,13 @@ static inline int usb_autopm_set_interface(struct usb_interface *intf)
 static inline int usb_autopm_get_interface(struct usb_interface *intf)
 { return 0; }
 
+static inline int usb_autopm_get_interface_async(struct usb_interface *intf)
+{ return 0; }
+
 static inline void usb_autopm_put_interface(struct usb_interface *intf)
 { }
+static inline void usb_autopm_put_interface_async(struct usb_interface *intf)
+{ }
 static inline void usb_autopm_enable(struct usb_interface *intf)
 { }
 static inline void usb_autopm_disable(struct usb_interface *intf)
@@ -1050,7 +1069,7 @@ struct usb_device_driver {
         void (*disconnect) (struct usb_device *udev);
 
         int (*suspend) (struct usb_device *udev, pm_message_t message);
-        int (*resume) (struct usb_device *udev);
+        int (*resume) (struct usb_device *udev, pm_message_t message);
         struct usbdrv_wrap drvwrap;
         unsigned int supports_autosuspend:1;
 };
@@ -1321,7 +1340,7 @@ struct urb {
         struct kref kref;               /* reference count of the URB */
         void *hcpriv;                   /* private data for host controller */
         atomic_t use_count;             /* concurrent submissions counter */
-        u8 reject;                      /* submissions will fail */
+        atomic_t reject;                /* submissions will fail */
         int unlinked;                   /* unlink error code */
 
         /* public: documented fields in the urb that can be used by drivers */
@@ -1466,6 +1485,7 @@ extern void usb_poison_urb(struct urb *urb);
 extern void usb_unpoison_urb(struct urb *urb);
 extern void usb_kill_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_poison_anchored_urbs(struct usb_anchor *anchor);
+extern void usb_unpoison_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_unlink_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor);
 extern void usb_unanchor_urb(struct urb *urb);
@@ -1722,10 +1742,6 @@ extern void usb_unregister_notify(struct notifier_block *nb);
 
 #define err(format, arg...) printk(KERN_ERR KBUILD_MODNAME ": " \
         format "\n" , ## arg)
-#define info(format, arg...) printk(KERN_INFO KBUILD_MODNAME ": " \
-        format "\n" , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING KBUILD_MODNAME ": " \
-        format "\n" , ## arg)
 
 #endif  /* __KERNEL__ */
 
diff --git a/include/linux/usb/association.h b/include/linux/usb/association.h
index 07c5e3cf5898..0a4a18b3c1bb 100644
--- a/include/linux/usb/association.h
+++ b/include/linux/usb/association.h
@@ -28,17 +28,17 @@ struct wusb_am_attr {
 };
 
 /* Different fields defined by the spec */
-#define WUSB_AR_AssociationTypeId       { .id = 0x0000, .len =  2 }
-#define WUSB_AR_AssociationSubTypeId    { .id = 0x0001, .len =  2 }
-#define WUSB_AR_Length                  { .id = 0x0002, .len =  4 }
-#define WUSB_AR_AssociationStatus       { .id = 0x0004, .len =  4 }
-#define WUSB_AR_LangID                  { .id = 0x0008, .len =  2 }
-#define WUSB_AR_DeviceFriendlyName      { .id = 0x000b, .len = 64 } /* max */
-#define WUSB_AR_HostFriendlyName        { .id = 0x000c, .len = 64 } /* max */
-#define WUSB_AR_CHID                    { .id = 0x1000, .len = 16 }
-#define WUSB_AR_CDID                    { .id = 0x1001, .len = 16 }
-#define WUSB_AR_ConnectionContext       { .id = 0x1002, .len = 48 }
-#define WUSB_AR_BandGroups              { .id = 0x1004, .len =  2 }
+#define WUSB_AR_AssociationTypeId       { .id = cpu_to_le16(0x0000), .len = cpu_to_le16(2) }
+#define WUSB_AR_AssociationSubTypeId    { .id = cpu_to_le16(0x0001), .len = cpu_to_le16(2) }
+#define WUSB_AR_Length                  { .id = cpu_to_le16(0x0002), .len = cpu_to_le16(4) }
+#define WUSB_AR_AssociationStatus       { .id = cpu_to_le16(0x0004), .len = cpu_to_le16(4) }
+#define WUSB_AR_LangID                  { .id = cpu_to_le16(0x0008), .len = cpu_to_le16(2) }
+#define WUSB_AR_DeviceFriendlyName      { .id = cpu_to_le16(0x000b), .len = cpu_to_le16(64) } /* max */
+#define WUSB_AR_HostFriendlyName        { .id = cpu_to_le16(0x000c), .len = cpu_to_le16(64) } /* max */
+#define WUSB_AR_CHID                    { .id = cpu_to_le16(0x1000), .len = cpu_to_le16(16) }
+#define WUSB_AR_CDID                    { .id = cpu_to_le16(0x1001), .len = cpu_to_le16(16) }
+#define WUSB_AR_ConnectionContext       { .id = cpu_to_le16(0x1002), .len = cpu_to_le16(48) }
+#define WUSB_AR_BandGroups              { .id = cpu_to_le16(0x1004), .len = cpu_to_le16(2) }
 
 /* CBAF Control Requests (AMS1.0[T4-1] */
 enum {
diff --git a/include/linux/usb/gpio_vbus.h b/include/linux/usb/gpio_vbus.h
new file mode 100644
index 000000000000..d9f03ccc2d60
--- /dev/null
+++ b/include/linux/usb/gpio_vbus.h
@@ -0,0 +1,30 @@
+/*
+ * A simple GPIO VBUS sensing driver for B peripheral only devices
+ * with internal transceivers.
+ * Optionally D+ pullup can be controlled by a second GPIO.
+ *
+ * Copyright (c) 2008 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/**
+ * struct gpio_vbus_mach_info - configuration for gpio_vbus
+ * @gpio_vbus: VBUS sensing GPIO
+ * @gpio_pullup: optional D+ or D- pullup GPIO (else negative/invalid)
+ * @gpio_vbus_inverted: true if gpio_vbus is active low
+ * @gpio_pullup_inverted: true if gpio_pullup is active low
+ *
+ * The VBUS sensing GPIO should have a pulldown, which will normally be
+ * part of a resistor ladder turning a 4.0V-5.25V level on VBUS into a
+ * value the GPIO detects as active.  Some systems will use comparators.
+ */
+struct gpio_vbus_mach_info {
+        int gpio_vbus;
+        int gpio_pullup;
+        bool gpio_vbus_inverted;
+        bool gpio_pullup_inverted;
+};
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 630962c04ca4..d6aad0ea6033 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -47,6 +47,11 @@ struct musb_hdrc_config {
         u8              ram_bits;       /* ram address size */
 
         struct musb_hdrc_eps_bits *eps_bits;
+#ifdef CONFIG_BLACKFIN
+        /* A GPIO controlling VRSEL in Blackfin */
+        unsigned int    gpio_vrsel;
+#endif
+
 };
 
 struct musb_hdrc_platform_data {
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 1db25d152ad8..94df4fe6c6c0 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -84,6 +84,7 @@ extern int otg_set_transceiver(struct otg_transceiver *);
 
 /* for usb host and peripheral controller drivers */
 extern struct otg_transceiver *otg_get_transceiver(void);
+extern void otg_put_transceiver(struct otg_transceiver *);
 
 static inline int
 otg_start_hnp(struct otg_transceiver *otg)
diff --git a/include/linux/usb_usual.h b/include/linux/usb_usual.h
index d9a3bbe38e6b..1eea1ab68dc4 100644
--- a/include/linux/usb_usual.h
+++ b/include/linux/usb_usual.h
@@ -52,8 +52,11 @@
         US_FLAG(MAX_SECTORS_MIN,0x00002000)                     \
                 /* Sets max_sectors to arch min */              \
         US_FLAG(BULK_IGNORE_TAG,0x00004000)                     \
-                /* Ignore tag mismatch in bulk operations */
-
+                /* Ignore tag mismatch in bulk operations */    \
+        US_FLAG(SANE_SENSE,     0x00008000)                     \
+                /* Sane Sense (> 18 bytes) */                   \
+        US_FLAG(CAPACITY_OK,    0x00010000)                     \
+                /* READ CAPACITY response is correct */
 
 #define US_FLAG(name, value)    US_FL_##name = value ,
 enum { US_DO_ALL_FLAGS };
diff --git a/include/linux/wimax.h b/include/linux/wimax.h
new file mode 100644
index 000000000000..c89de7f4e5b9
--- /dev/null
+++ b/include/linux/wimax.h
@@ -0,0 +1,234 @@
+/*
+ * Linux WiMax
+ * API for user space
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * This file declares the user/kernel protocol that is spoken over
+ * Generic Netlink, as well as any type declaration that is to be used
+ * by kernel and user space.
+ *
+ * It is intended for user space to clone it verbatim to use it as a
+ * primary reference for definitions.
+ *
+ * Stuff intended for kernel usage as well as full protocol and stack
+ * documentation is rooted in include/net/wimax.h.
+ */
+
+#ifndef __LINUX__WIMAX_H__
+#define __LINUX__WIMAX_H__
+
+#include <linux/types.h>
+
+enum {
+        /**
+         * Version of the interface (unsigned decimal, MMm, max 25.5)
+         * M - Major: change if removing or modifying an existing call.
+         * m - minor: change when adding a new call
+         */
+        WIMAX_GNL_VERSION = 00,
+        /* Generic NetLink attributes */
+        WIMAX_GNL_ATTR_INVALID = 0x00,
+        WIMAX_GNL_ATTR_MAX = 10,
+};
+
+
+/*
+ * Generic NetLink operations
+ *
+ * Most of these map to an API call; _OP_ stands for operation, _RP_
+ * for reply and _RE_ for report (aka: signal).
+ */
+enum {
+        WIMAX_GNL_OP_MSG_FROM_USER,     /* User to kernel message */
+        WIMAX_GNL_OP_MSG_TO_USER,       /* Kernel to user message */
+        WIMAX_GNL_OP_RFKILL,    /* Run wimax_rfkill() */
+        WIMAX_GNL_OP_RESET,     /* Run wimax_rfkill() */
+        WIMAX_GNL_RE_STATE_CHANGE,      /* Report: status change */
+};
+
+
+/* Message from user / to user */
+enum {
+        WIMAX_GNL_MSG_IFIDX = 1,
+        WIMAX_GNL_MSG_PIPE_NAME,
+        WIMAX_GNL_MSG_DATA,
+};
+
+
+/*
+ * wimax_rfkill()
+ *
+ * The state of the radio (ON/OFF) is mapped to the rfkill subsystem's
+ * switch state (DISABLED/ENABLED).
+ */
+enum wimax_rf_state {
+        WIMAX_RF_OFF = 0,       /* Radio is off, rfkill on/enabled */
+        WIMAX_RF_ON = 1,        /* Radio is on, rfkill off/disabled */
+        WIMAX_RF_QUERY = 2,
+};
+
+/* Attributes */
+enum {
+        WIMAX_GNL_RFKILL_IFIDX = 1,
+        WIMAX_GNL_RFKILL_STATE,
+};
+
+
+/* Attributes for wimax_reset() */
+enum {
+        WIMAX_GNL_RESET_IFIDX = 1,
+};
+
+
+/*
+ * Attributes for the Report State Change
+ *
+ * For now we just have the old and new states; new attributes might
+ * be added later on.
+ */
+enum {
+        WIMAX_GNL_STCH_IFIDX = 1,
+        WIMAX_GNL_STCH_STATE_OLD,
+        WIMAX_GNL_STCH_STATE_NEW,
+};
+
+
+/**
+ * enum wimax_st - The different states of a WiMAX device
+ * @__WIMAX_ST_NULL: The device structure has been allocated and zeroed,
+ *     but still wimax_dev_add() hasn't been called. There is no state.
+ *
+ * @WIMAX_ST_DOWN: The device has been registered with the WiMAX and
+ *     networking stacks, but it is not initialized (normally that is
+ *     done with 'ifconfig DEV up' [or equivalent], which can upload
+ *     firmware and enable communications with the device).
+ *     In this state, the device is powered down and using as less
+ *     power as possible.
+ *     This state is the default after a call to wimax_dev_add(). It
+ *     is ok to have drivers move directly to %WIMAX_ST_UNINITIALIZED
+ *     or %WIMAX_ST_RADIO_OFF in _probe() after the call to
+ *     wimax_dev_add().
+ *     It is recommended that the driver leaves this state when
+ *     calling 'ifconfig DEV up' and enters it back on 'ifconfig DEV
+ *     down'.
+ *
+ * @__WIMAX_ST_QUIESCING: The device is being torn down, so no API
+ *     operations are allowed to proceed except the ones needed to
+ *     complete the device clean up process.
+ *
+ * @WIMAX_ST_UNINITIALIZED: [optional] Communication with the device
+ *     is setup, but the device still requires some configuration
+ *     before being operational.
+ *     Some WiMAX API calls might work.
+ *
+ * @WIMAX_ST_RADIO_OFF: The device is fully up; radio is off (wether
+ *     by hardware or software switches).
+ *     It is recommended to always leave the device in this state
+ *     after initialization.
+ *
+ * @WIMAX_ST_READY: The device is fully up and radio is on.
+ *
+ * @WIMAX_ST_SCANNING: [optional] The device has been instructed to
+ *     scan. In this state, the device cannot be actively connected to
+ *     a network.
+ *
+ * @WIMAX_ST_CONNECTING: The device is connecting to a network. This
+ *     state exists because in some devices, the connect process can
+ *     include a number of negotiations between user space, kernel
+ *     space and the device. User space needs to know what the device
+ *     is doing. If the connect sequence in a device is atomic and
+ *     fast, the device can transition directly to CONNECTED
+ *
+ * @WIMAX_ST_CONNECTED: The device is connected to a network.
+ *
+ * @__WIMAX_ST_INVALID: This is an invalid state used to mark the
+ *     maximum numeric value of states.
+ *
+ * Description:
+ *
+ * Transitions from one state to another one are atomic and can only
+ * be caused in kernel space with wimax_state_change(). To read the
+ * state, use wimax_state_get().
+ *
+ * States starting with __ are internal and shall not be used or
+ * referred to by drivers or userspace. They look ugly, but that's the
+ * point -- if any use is made non-internal to the stack, it is easier
+ * to catch on review.
+ *
+ * All API operations [with well defined exceptions] will take the
+ * device mutex before starting and then check the state. If the state
+ * is %__WIMAX_ST_NULL, %WIMAX_ST_DOWN, %WIMAX_ST_UNINITIALIZED or
+ * %__WIMAX_ST_QUIESCING, it will drop the lock and quit with
+ * -%EINVAL, -%ENOMEDIUM, -%ENOTCONN or -%ESHUTDOWN.
+ *
+ * The order of the definitions is important, so we can do numerical
+ * comparisons (eg: < %WIMAX_ST_RADIO_OFF means the device is not ready
+ * to operate).
+ */
+/*
+ * The allowed state transitions are described in the table below
+ * (states in rows can go to states in columns where there is an X):
+ *
+ *                                  UNINI   RADIO READY SCAN CONNEC CONNEC
+ *             NULL DOWN QUIESCING TIALIZED  OFF        NING  TING   TED
+ * NULL         -    x
+ * DOWN              -      x        x       x
+ * QUIESCING         x      -
+ * UNINITIALIZED            x        -       x
+ * RADIO_OFF                x                -     x
+ * READY                    x                x     -     x     x      x
+ * SCANNING                 x                x     x     -     x      x
+ * CONNECTING               x                x     x     x     -      x
+ * CONNECTED                x                x     x                  -
+ *
+ * This table not available in kernel-doc because the formatting messes it up.
+ */
+ enum wimax_st {
+        __WIMAX_ST_NULL = 0,
+        WIMAX_ST_DOWN,
+        __WIMAX_ST_QUIESCING,
+        WIMAX_ST_UNINITIALIZED,
+        WIMAX_ST_RADIO_OFF,
+        WIMAX_ST_READY,
+        WIMAX_ST_SCANNING,
+        WIMAX_ST_CONNECTING,
+        WIMAX_ST_CONNECTED,
+        __WIMAX_ST_INVALID                      /* Always keep last */
+};
+
+
+#endif /* #ifndef __LINUX__WIMAX_H__ */
diff --git a/include/linux/wimax/Kbuild b/include/linux/wimax/Kbuild
new file mode 100644
index 000000000000..3cb4f269bb09
--- /dev/null
+++ b/include/linux/wimax/Kbuild
@@ -0,0 +1 @@
+header-y += i2400m.h
diff --git a/include/linux/wimax/debug.h b/include/linux/wimax/debug.h
new file mode 100644
index 000000000000..ba0c49399a83
--- /dev/null
+++ b/include/linux/wimax/debug.h
@@ -0,0 +1,453 @@
+/*
+ * Linux WiMAX
+ * Collection of tools to manage debug operations.
+ *
+ *
+ * Copyright (C) 2005-2007 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * Don't #include this file directly, read on!
+ *
+ *
+ * EXECUTING DEBUGGING ACTIONS OR NOT
+ *
+ * The main thing this framework provides is decission power to take a
+ * debug action (like printing a message) if the current debug level
+ * allows it.
+ *
+ * The decission power is at two levels: at compile-time (what does
+ * not make it is compiled out) and at run-time. The run-time
+ * selection is done per-submodule (as they are declared by the user
+ * of the framework).
+ *
+ * A call to d_test(L) (L being the target debug level) returns true
+ * if the action should be taken because the current debug levels
+ * allow it (both compile and run time).
+ *
+ * It follows that a call to d_test() that can be determined to be
+ * always false at compile time will get the code depending on it
+ * compiled out by optimization.
+ *
+ *
+ * DEBUG LEVELS
+ *
+ * It is up to the caller to define how much a debugging level is.
+ *
+ * Convention sets 0 as "no debug" (so an action marked as debug level 0
+ * will always be taken). The increasing debug levels are used for
+ * increased verbosity.
+ *
+ *
+ * USAGE
+ *
+ * Group the code in modules and submodules inside each module [which
+ * in most cases maps to Linux modules and .c files that compose
+ * those].
+ *
+ *
+ * For each module, there is:
+ *
+ *  - a MODULENAME (single word, legal C identifier)
+ *
+ *  - a debug-levels.h header file that declares the list of
+ *    submodules and that is included by all .c files that use
+ *    the debugging tools. The file name can be anything.
+ *
+ *  - some (optional) .c code to manipulate the runtime debug levels
+ *    through debugfs.
+ *
+ * The debug-levels.h file would look like:
+ *
+ *     #ifndef __debug_levels__h__
+ *     #define __debug_levels__h__
+ *
+ *     #define D_MODULENAME modulename
+ *     #define D_MASTER 10
+ *
+ *     #include <linux/wimax/debug.h>
+ *
+ *     enum d_module {
+ *             D_SUBMODULE_DECLARE(submodule_1),
+ *             D_SUBMODULE_DECLARE(submodule_2),
+ *             ...
+ *             D_SUBMODULE_DECLARE(submodule_N)
+ *     };
+ *
+ *     #endif
+ *
+ * D_MASTER is the maximum compile-time debug level; any debug actions
+ * above this will be out. D_MODULENAME is the module name (legal C
+ * identifier), which has to be unique for each module (to avoid
+ * namespace collisions during linkage). Note those #defines need to
+ * be done before #including debug.h
+ *
+ * We declare N different submodules whose debug level can be
+ * independently controlled during runtime.
+ *
+ * In a .c file of the module (and only in one of them), define the
+ * following code:
+ *
+ *     struct d_level D_LEVEL[] = {
+ *             D_SUBMODULE_DEFINE(submodule_1),
+ *             D_SUBMODULE_DEFINE(submodule_2),
+ *             ...
+ *             D_SUBMODULE_DEFINE(submodule_N),
+ *     };
+ *     size_t D_LEVEL_SIZE = ARRAY_SIZE(D_LEVEL);
+ *
+ * Externs for d_level_MODULENAME and d_level_size_MODULENAME are used
+ * and declared in this file using the D_LEVEL and D_LEVEL_SIZE macros
+ * #defined also in this file.
+ *
+ * To manipulate from user space the levels, create a debugfs dentry
+ * and then register each submodule with:
+ *
+ *     result = d_level_register_debugfs("PREFIX_", submodule_X, parent);
+ *     if (result < 0)
+ *            goto error;
+ *
+ * Where PREFIX_ is a name of your chosing. This will create debugfs
+ * file with a single numeric value that can be use to tweak it. To
+ * remove the entires, just use debugfs_remove_recursive() on 'parent'.
+ *
+ * NOTE: remember that even if this will show attached to some
+ *     particular instance of a device, the settings are *global*.
+ *
+ *
+ * On each submodule (for example, .c files), the debug infrastructure
+ * should be included like this:
+ *
+ *     #define D_SUBMODULE submodule_x     // matches one in debug-levels.h
+ *     #include "debug-levels.h"
+ *
+ * after #including all your include files.
+ *
+ *
+ * Now you can use the d_*() macros below [d_test(), d_fnstart(),
+ * d_fnend(), d_printf(), d_dump()].
+ *
+ * If their debug level is greater than D_MASTER, they will be
+ * compiled out.
+ *
+ * If their debug level is lower or equal than D_MASTER but greater
+ * than the current debug level of their submodule, they'll be
+ * ignored.
+ *
+ * Otherwise, the action will be performed.
+ */
+#ifndef __debug__h__
+#define __debug__h__
+
+#include <linux/types.h>
+#include <linux/device.h>
+
+
+/* Backend stuff */
+
+/*
+ * Debug backend: generate a message header from a 'struct device'
+ *
+ * @head: buffer where to place the header
+ * @head_size: length of @head
+ * @dev: pointer to device used to generate a header from. If NULL,
+ *     an empty ("") header is generated.
+ */
+static inline
+void __d_head(char *head, size_t head_size,
+              struct device *dev)
+{
+        if (dev == NULL)
+                head[0] = 0;
+        else if ((unsigned long)dev < 4096) {
+                printk(KERN_ERR "E: Corrupt dev %p\n", dev);
+                WARN_ON(1);
+        } else
+                snprintf(head, head_size, "%s %s: ",
+                         dev_driver_string(dev), dev->bus_id);
+}
+
+
+/*
+ * Debug backend: log some message if debugging is enabled
+ *
+ * @l: intended debug level
+ * @tag: tag to prefix the message with
+ * @dev: 'struct device' associated to this message
+ * @f: printf-like format and arguments
+ *
+ * Note this is optimized out if it doesn't pass the compile-time
+ * check; however, it is *always* compiled. This is useful to make
+ * sure the printf-like formats and variables are always checked and
+ * they don't get bit rot if you have all the debugging disabled.
+ */
+#define _d_printf(l, tag, dev, f, a...)                                 \
+do {                                                                    \
+        char head[64];                                                  \
+        if (!d_test(l))                                                 \
+                break;                                                  \
+        __d_head(head, sizeof(head), dev);                              \
+        printk(KERN_ERR "%s%s%s: " f, head, __func__, tag, ##a);        \
+} while (0)
+
+
+/*
+ * CPP sintatic sugar to generate A_B like symbol names when one of
+ * the arguments is a a preprocessor #define.
+ */
+#define __D_PASTE__(varname, modulename) varname##_##modulename
+#define __D_PASTE(varname, modulename) (__D_PASTE__(varname, modulename))
+#define _D_SUBMODULE_INDEX(_name) (D_SUBMODULE_DECLARE(_name))
+
+
+/*
+ * Store a submodule's runtime debug level and name
+ */
+struct d_level {
+        u8 level;
+        const char *name;
+};
+
+
+/*
+ * List of available submodules and their debug levels
+ *
+ * We call them d_level_MODULENAME and d_level_size_MODULENAME; the
+ * macros D_LEVEL and D_LEVEL_SIZE contain the name already for
+ * convenience.
+ *
+ * This array and the size are defined on some .c file that is part of
+ * the current module.
+ */
+#define D_LEVEL __D_PASTE(d_level, D_MODULENAME)
+#define D_LEVEL_SIZE __D_PASTE(d_level_size, D_MODULENAME)
+
+extern struct d_level D_LEVEL[];
+extern size_t D_LEVEL_SIZE;
+
+
+/*
+ * Frontend stuff
+ *
+ *
+ * Stuff you need to declare prior to using the actual "debug" actions
+ * (defined below).
+ */
+
+#ifndef D_MODULENAME
+#error D_MODULENAME is not defined in your debug-levels.h file
+/**
+ * D_MODULE - Name of the current module
+ *
+ * #define in your module's debug-levels.h, making sure it is
+ * unique. This has to be a legal C identifier.
+ */
+#define D_MODULENAME undefined_modulename
+#endif
+
+
+#ifndef D_MASTER
+#warning D_MASTER not defined, but debug.h included! [see docs]
+/**
+ * D_MASTER - Compile time maximum debug level
+ *
+ * #define in your debug-levels.h file to the maximum debug level the
+ * runtime code will be allowed to have. This allows you to provide a
+ * main knob.
+ *
+ * Anything above that level will be optimized out of the compile.
+ *
+ * Defaults to zero (no debug code compiled in).
+ *
+ * Maximum one definition per module (at the debug-levels.h file).
+ */
+#define D_MASTER 0
+#endif
+
+#ifndef D_SUBMODULE
+#error D_SUBMODULE not defined, but debug.h included! [see docs]
+/**
+ * D_SUBMODULE - Name of the current submodule
+ *
+ * #define in your submodule .c file before #including debug-levels.h
+ * to the name of the current submodule as previously declared and
+ * defined with D_SUBMODULE_DECLARE() (in your module's
+ * debug-levels.h) and D_SUBMODULE_DEFINE().
+ *
+ * This is used to provide runtime-control over the debug levels.
+ *
+ * Maximum one per .c file! Can be shared among different .c files
+ * (meaning they belong to the same submodule categorization).
+ */
+#define D_SUBMODULE undefined_module
+#endif
+
+
+/**
+ * D_SUBMODULE_DECLARE - Declare a submodule for runtime debug level control
+ *
+ * @_name: name of the submodule, restricted to the chars that make up a
+ *     valid C identifier ([a-zA-Z0-9_]).
+ *
+ * Declare in the module's debug-levels.h header file as:
+ *
+ * enum d_module {
+ *         D_SUBMODULE_DECLARE(submodule_1),
+ *         D_SUBMODULE_DECLARE(submodule_2),
+ *         D_SUBMODULE_DECLARE(submodule_3),
+ * };
+ *
+ * Some corresponding .c file needs to have a matching
+ * D_SUBMODULE_DEFINE().
+ */
+#define D_SUBMODULE_DECLARE(_name) __D_SUBMODULE_##_name
+
+
+/**
+ * D_SUBMODULE_DEFINE - Define a submodule for runtime debug level control
+ *
+ * @_name: name of the submodule, restricted to the chars that make up a
+ *     valid C identifier ([a-zA-Z0-9_]).
+ *
+ * Use once per module (in some .c file) as:
+ *
+ * static
+ * struct d_level d_level_SUBMODULENAME[] = {
+ *         D_SUBMODULE_DEFINE(submodule_1),
+ *         D_SUBMODULE_DEFINE(submodule_2),
+ *         D_SUBMODULE_DEFINE(submodule_3),
+ * };
+ * size_t d_level_size_SUBDMODULENAME = ARRAY_SIZE(d_level_SUBDMODULENAME);
+ *
+ * Matching D_SUBMODULE_DECLARE()s have to be present in a
+ * debug-levels.h header file.
+ */
+#define D_SUBMODULE_DEFINE(_name)               \
+[__D_SUBMODULE_##_name] = {                     \
+        .level = 0,                             \
+        .name = #_name                          \
+}
+
+
+
+/* The actual "debug" operations */
+
+
+/**
+ * d_test - Returns true if debugging should be enabled
+ *
+ * @l: intended debug level (unsigned)
+ *
+ * If the master debug switch is enabled and the current settings are
+ * higher or equal to the requested level, then debugging
+ * output/actions should be enabled.
+ *
+ * NOTE:
+ *
+ * This needs to be coded so that it can be evaluated in compile
+ * time; this is why the ugly BUG_ON() is placed in there, so the
+ * D_MASTER evaluation compiles all out if it is compile-time false.
+ */
+#define d_test(l)                                                       \
+({                                                                      \
+        unsigned __l = l;       /* type enforcer */                     \
+        (D_MASTER) >= __l                                               \
+        && ({                                                           \
+                BUG_ON(_D_SUBMODULE_INDEX(D_SUBMODULE) >= D_LEVEL_SIZE);\
+                D_LEVEL[_D_SUBMODULE_INDEX(D_SUBMODULE)].level >= __l;  \
+        });                                                             \
+})
+
+
+/**
+ * d_fnstart - log message at function start if debugging enabled
+ *
+ * @l: intended debug level
+ * @_dev: 'struct device' pointer, NULL if none (for context)
+ * @f: printf-like format and arguments
+ */
+#define d_fnstart(l, _dev, f, a...) _d_printf(l, " FNSTART", _dev, f, ## a)
+
+
+/**
+ * d_fnend - log message at function end if debugging enabled
+ *
+ * @l: intended debug level
+ * @_dev: 'struct device' pointer, NULL if none (for context)
+ * @f: printf-like format and arguments
+ */
+#define d_fnend(l, _dev, f, a...) _d_printf(l, " FNEND", _dev, f, ## a)
+
+
+/**
+ * d_printf - log message if debugging enabled
+ *
+ * @l: intended debug level
+ * @_dev: 'struct device' pointer, NULL if none (for context)
+ * @f: printf-like format and arguments
+ */
+#define d_printf(l, _dev, f, a...) _d_printf(l, "", _dev, f, ## a)
+
+
+/**
+ * d_dump - log buffer hex dump if debugging enabled
+ *
+ * @l: intended debug level
+ * @_dev: 'struct device' pointer, NULL if none (for context)
+ * @f: printf-like format and arguments
+ */
+#define d_dump(l, dev, ptr, size)                       \
+do {                                                    \
+        char head[64];                                  \
+        if (!d_test(l))                                 \
+                break;                                  \
+        __d_head(head, sizeof(head), dev);              \
+        print_hex_dump(KERN_ERR, head, 0, 16, 1,        \
+                       ((void *) ptr), (size), 0);      \
+} while (0)
+
+
+/**
+ * Export a submodule's debug level over debugfs as PREFIXSUBMODULE
+ *
+ * @prefix: string to prefix the name with
+ * @submodule: name of submodule (not a string, just the name)
+ * @dentry: debugfs parent dentry
+ *
+ * Returns: 0 if ok, < 0 errno on error.
+ *
+ * For removing, just use debugfs_remove_recursive() on the parent.
+ */
+#define d_level_register_debugfs(prefix, name, parent)                  \
+({                                                                      \
+        int rc;                                                         \
+        struct dentry *fd;                                              \
+        struct dentry *verify_parent_type = parent;                     \
+        fd = debugfs_create_u8(                                         \
+                prefix #name, 0600, verify_parent_type,                 \
+                &(D_LEVEL[__D_SUBMODULE_ ## name].level));              \
+        rc = PTR_ERR(fd);                                               \
+        if (IS_ERR(fd) && rc != -ENODEV)                                \
+                printk(KERN_ERR "%s: Can't create debugfs entry %s: "   \
+                       "%d\n", __func__, prefix #name, rc);             \
+        else                                                            \
+                rc = 0;                                                 \
+        rc;                                                             \
+})
+
+
+#endif /* #ifndef __debug__h__ */
diff --git a/include/linux/wimax/i2400m.h b/include/linux/wimax/i2400m.h
new file mode 100644
index 000000000000..74198f5bb4dc
--- /dev/null
+++ b/include/linux/wimax/i2400m.h
@@ -0,0 +1,512 @@
+/*
+ * Intel Wireless WiMax Connection 2400m
+ * Host-Device protocol interface definitions
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *  - Initial implementation
+ *
+ *
+ * This header defines the data structures and constants used to
+ * communicate with the device.
+ *
+ * BOOTMODE/BOOTROM/FIRMWARE UPLOAD PROTOCOL
+ *
+ * The firmware upload protocol is quite simple and only requires a
+ * handful of commands. See drivers/net/wimax/i2400m/fw.c for more
+ * details.
+ *
+ * The BCF data structure is for the firmware file header.
+ *
+ *
+ * THE DATA / CONTROL PROTOCOL
+ *
+ * This is the normal protocol spoken with the device once the
+ * firmware is uploaded. It transports data payloads and control
+ * messages back and forth.
+ *
+ * It consists 'messages' that pack one or more payloads each. The
+ * format is described in detail in drivers/net/wimax/i2400m/rx.c and
+ * tx.c.
+ *
+ *
+ * THE L3L4 PROTOCOL
+ *
+ * The term L3L4 refers to Layer 3 (the device), Layer 4 (the
+ * driver/host software).
+ *
+ * This is the control protocol used by the host to control the i2400m
+ * device (scan, connect, disconnect...). This is sent to / received
+ * as control frames. These frames consist of a header and zero or
+ * more TLVs with information. We call each control frame a "message".
+ *
+ * Each message is composed of:
+ *
+ * HEADER
+ * [TLV0 + PAYLOAD0]
+ * [TLV1 + PAYLOAD1]
+ * [...]
+ * [TLVN + PAYLOADN]
+ *
+ * The HEADER is defined by 'struct i2400m_l3l4_hdr'. The payloads are
+ * defined by a TLV structure (Type Length Value) which is a 'header'
+ * (struct i2400m_tlv_hdr) and then the payload.
+ *
+ * All integers are represented as Little Endian.
+ *
+ * - REQUESTS AND EVENTS
+ *
+ * The requests can be clasified as follows:
+ *
+ *   COMMAND:  implies a request from the host to the device requesting
+ *             an action being performed. The device will reply with a
+ *             message (with the same type as the command), status and
+ *             no (TLV) payload. Execution of a command might cause
+ *             events (of different type) to be sent later on as
+ *             device's state changes.
+ *
+ *   GET/SET:  similar to COMMAND, but will not cause other
+ *             EVENTs. The reply, in the case of GET, will contain
+ *             TLVs with the requested information.
+ *
+ *   EVENT:    asynchronous messages sent from the device, maybe as a
+ *             consequence of previous COMMANDs but disassociated from
+ *             them.
+ *
+ * Only one request might be pending at the same time (ie: don't
+ * parallelize nor post another GET request before the previous
+ * COMMAND has been acknowledged with it's corresponding reply by the
+ * device).
+ *
+ * The different requests and their formats are described below:
+ *
+ *  I2400M_MT_*   Message types
+ *  I2400M_MS_*   Message status (for replies, events)
+ *  i2400m_tlv_*  TLVs
+ *
+ * data types are named 'struct i2400m_msg_OPNAME', OPNAME matching the
+ * operation.
+ */
+
+#ifndef __LINUX__WIMAX__I2400M_H__
+#define __LINUX__WIMAX__I2400M_H__
+
+#include <linux/types.h>
+
+
+/*
+ * Host Device Interface (HDI) common to all busses
+ */
+
+/* Boot-mode (firmware upload mode) commands */
+
+/* Header for the firmware file */
+struct i2400m_bcf_hdr {
+        __le32 module_type;
+        __le32 header_len;
+        __le32 header_version;
+        __le32 module_id;
+        __le32 module_vendor;
+        __le32 date;            /* BCD YYYMMDD */
+        __le32 size;
+        __le32 key_size;        /* in dwords */
+        __le32 modulus_size;    /* in dwords */
+        __le32 exponent_size;   /* in dwords */
+        __u8 reserved[88];
+} __attribute__ ((packed));
+
+/* Boot mode opcodes */
+enum i2400m_brh_opcode {
+        I2400M_BRH_READ = 1,
+        I2400M_BRH_WRITE = 2,
+        I2400M_BRH_JUMP = 3,
+        I2400M_BRH_SIGNED_JUMP = 8,
+        I2400M_BRH_HASH_PAYLOAD_ONLY = 9,
+};
+
+/* Boot mode command masks and stuff */
+enum i2400m_brh {
+        I2400M_BRH_SIGNATURE = 0xcbbc0000,
+        I2400M_BRH_SIGNATURE_MASK = 0xffff0000,
+        I2400M_BRH_SIGNATURE_SHIFT = 16,
+        I2400M_BRH_OPCODE_MASK = 0x0000000f,
+        I2400M_BRH_RESPONSE_MASK = 0x000000f0,
+        I2400M_BRH_RESPONSE_SHIFT = 4,
+        I2400M_BRH_DIRECT_ACCESS = 0x00000400,
+        I2400M_BRH_RESPONSE_REQUIRED = 0x00000200,
+        I2400M_BRH_USE_CHECKSUM = 0x00000100,
+};
+
+
+/* Constants for bcf->module_id */
+enum i2400m_bcf_mod_id {
+        /* Firmware file carries its own pokes -- pokes are a set of
+         * magical values that have to be written in certain memory
+         * addresses to get the device up and ready for firmware
+         * download when it is in non-signed boot mode. */
+        I2400M_BCF_MOD_ID_POKES = 0x000000001,
+};
+
+
+/**
+ * i2400m_bootrom_header - Header for a boot-mode command
+ *
+ * @cmd: the above command descriptor
+ * @target_addr: where on the device memory should the action be performed.
+ * @data_size: for read/write, amount of data to be read/written
+ * @block_checksum: checksum value (if applicable)
+ * @payload: the beginning of data attached to this header
+ */
+struct i2400m_bootrom_header {
+        __le32 command;         /* Compose with enum i2400_brh */
+        __le32 target_addr;
+        __le32 data_size;
+        __le32 block_checksum;
+        char payload[0];
+} __attribute__ ((packed));
+
+
+/*
+ * Data / control protocol
+ */
+
+/* Packet types for the host-device interface */
+enum i2400m_pt {
+        I2400M_PT_DATA = 0,
+        I2400M_PT_CTRL,
+        I2400M_PT_TRACE,        /* For device debug */
+        I2400M_PT_RESET_WARM,   /* device reset */
+        I2400M_PT_RESET_COLD,   /* USB[transport] reset, like reconnect */
+        I2400M_PT_ILLEGAL
+};
+
+
+/*
+ * Payload for a data packet
+ *
+ * This is prefixed to each and every outgoing DATA type.
+ */
+struct i2400m_pl_data_hdr {
+        __le32 reserved;
+} __attribute__((packed));
+
+
+/* Misc constants */
+enum {
+        I2400M_PL_PAD = 16,     /* Payload data size alignment */
+        I2400M_PL_SIZE_MAX = 0x3EFF,
+        I2400M_MAX_PLS_IN_MSG = 60,
+        /* protocol barkers: sync sequences; for notifications they
+         * are sent in groups of four. */
+        I2400M_H2D_PREVIEW_BARKER = 0xcafe900d,
+        I2400M_COLD_RESET_BARKER = 0xc01dc01d,
+        I2400M_WARM_RESET_BARKER = 0x50f750f7,
+        I2400M_NBOOT_BARKER = 0xdeadbeef,
+        I2400M_SBOOT_BARKER = 0x0ff1c1a1,
+        I2400M_ACK_BARKER = 0xfeedbabe,
+        I2400M_D2H_MSG_BARKER = 0xbeefbabe,
+};
+
+
+/*
+ * Hardware payload descriptor
+ *
+ * Bitfields encoded in a struct to enforce typing semantics.
+ *
+ * Look in rx.c and tx.c for a full description of the format.
+ */
+struct i2400m_pld {
+        __le32 val;
+} __attribute__ ((packed));
+
+#define I2400M_PLD_SIZE_MASK 0x00003fff
+#define I2400M_PLD_TYPE_SHIFT 16
+#define I2400M_PLD_TYPE_MASK 0x000f0000
+
+/*
+ * Header for a TX message or RX message
+ *
+ * @barker: preamble
+ * @size: used for management of the FIFO queue buffer; before
+ *     sending, this is converted to be a real preamble. This
+ *     indicates the real size of the TX message that starts at this
+ *     point. If the highest bit is set, then this message is to be
+ *     skipped.
+ * @sequence: sequence number of this message
+ * @offset: offset where the message itself starts -- see the comments
+ *     in the file header about message header and payload descriptor
+ *     alignment.
+ * @num_pls: number of payloads in this message
+ * @padding: amount of padding bytes at the end of the message to make
+ *           it be of block-size aligned
+ *
+ * Look in rx.c and tx.c for a full description of the format.
+ */
+struct i2400m_msg_hdr {
+        union {
+                __le32 barker;
+                __u32 size;     /* same size type as barker!! */
+        };
+        union {
+                __le32 sequence;
+                __u32 offset;   /* same size type as barker!! */
+        };
+        __le16 num_pls;
+        __le16 rsv1;
+        __le16 padding;
+        __le16 rsv2;
+        struct i2400m_pld pld[0];
+} __attribute__ ((packed));
+
+
+
+/*
+ * L3/L4 control protocol
+ */
+
+enum {
+        /* Interface version */
+        I2400M_L3L4_VERSION             = 0x0100,
+};
+
+/* Message types */
+enum i2400m_mt {
+        I2400M_MT_RESERVED              = 0x0000,
+        I2400M_MT_INVALID               = 0xffff,
+        I2400M_MT_REPORT_MASK           = 0x8000,
+
+        I2400M_MT_GET_SCAN_RESULT       = 0x4202,
+        I2400M_MT_SET_SCAN_PARAM        = 0x4402,
+        I2400M_MT_CMD_RF_CONTROL        = 0x4602,
+        I2400M_MT_CMD_SCAN              = 0x4603,
+        I2400M_MT_CMD_CONNECT           = 0x4604,
+        I2400M_MT_CMD_DISCONNECT        = 0x4605,
+        I2400M_MT_CMD_EXIT_IDLE         = 0x4606,
+        I2400M_MT_GET_LM_VERSION        = 0x5201,
+        I2400M_MT_GET_DEVICE_INFO       = 0x5202,
+        I2400M_MT_GET_LINK_STATUS       = 0x5203,
+        I2400M_MT_GET_STATISTICS        = 0x5204,
+        I2400M_MT_GET_STATE             = 0x5205,
+        I2400M_MT_GET_MEDIA_STATUS      = 0x5206,
+        I2400M_MT_SET_INIT_CONFIG       = 0x5404,
+        I2400M_MT_CMD_INIT              = 0x5601,
+        I2400M_MT_CMD_TERMINATE         = 0x5602,
+        I2400M_MT_CMD_MODE_OF_OP        = 0x5603,
+        I2400M_MT_CMD_RESET_DEVICE      = 0x5604,
+        I2400M_MT_CMD_MONITOR_CONTROL   = 0x5605,
+        I2400M_MT_CMD_ENTER_POWERSAVE   = 0x5606,
+        I2400M_MT_GET_TLS_OPERATION_RESULT = 0x6201,
+        I2400M_MT_SET_EAP_SUCCESS       = 0x6402,
+        I2400M_MT_SET_EAP_FAIL          = 0x6403,
+        I2400M_MT_SET_EAP_KEY           = 0x6404,
+        I2400M_MT_CMD_SEND_EAP_RESPONSE = 0x6602,
+        I2400M_MT_REPORT_SCAN_RESULT    = 0xc002,
+        I2400M_MT_REPORT_STATE          = 0xd002,
+        I2400M_MT_REPORT_POWERSAVE_READY = 0xd005,
+        I2400M_MT_REPORT_EAP_REQUEST    = 0xe002,
+        I2400M_MT_REPORT_EAP_RESTART    = 0xe003,
+        I2400M_MT_REPORT_ALT_ACCEPT     = 0xe004,
+        I2400M_MT_REPORT_KEY_REQUEST    = 0xe005,
+};
+
+
+/*
+ * Message Ack Status codes
+ *
+ * When a message is replied-to, this status is reported.
+ */
+enum i2400m_ms {
+        I2400M_MS_DONE_OK                  = 0,
+        I2400M_MS_DONE_IN_PROGRESS         = 1,
+        I2400M_MS_INVALID_OP               = 2,
+        I2400M_MS_BAD_STATE                = 3,
+        I2400M_MS_ILLEGAL_VALUE            = 4,
+        I2400M_MS_MISSING_PARAMS           = 5,
+        I2400M_MS_VERSION_ERROR            = 6,
+        I2400M_MS_ACCESSIBILITY_ERROR      = 7,
+        I2400M_MS_BUSY                     = 8,
+        I2400M_MS_CORRUPTED_TLV            = 9,
+        I2400M_MS_UNINITIALIZED            = 10,
+        I2400M_MS_UNKNOWN_ERROR            = 11,
+        I2400M_MS_PRODUCTION_ERROR         = 12,
+        I2400M_MS_NO_RF                    = 13,
+        I2400M_MS_NOT_READY_FOR_POWERSAVE  = 14,
+        I2400M_MS_THERMAL_CRITICAL         = 15,
+        I2400M_MS_MAX
+};
+
+
+/**
+ * i2400m_tlv - enumeration of the different types of TLVs
+ *
+ * TLVs stand for type-length-value and are the header for a payload
+ * composed of almost anything. Each payload has a type assigned
+ * and a length.
+ */
+enum i2400m_tlv {
+        I2400M_TLV_L4_MESSAGE_VERSIONS = 129,
+        I2400M_TLV_SYSTEM_STATE = 141,
+        I2400M_TLV_MEDIA_STATUS = 161,
+        I2400M_TLV_RF_OPERATION = 162,
+        I2400M_TLV_RF_STATUS = 163,
+        I2400M_TLV_DEVICE_RESET_TYPE = 132,
+        I2400M_TLV_CONFIG_IDLE_PARAMETERS = 601,
+};
+
+
+struct i2400m_tlv_hdr {
+        __le16 type;
+        __le16 length;          /* payload's */
+        __u8   pl[0];
+} __attribute__((packed));
+
+
+struct i2400m_l3l4_hdr {
+        __le16 type;
+        __le16 length;          /* payload's */
+        __le16 version;
+        __le16 resv1;
+        __le16 status;
+        __le16 resv2;
+        struct i2400m_tlv_hdr pl[0];
+} __attribute__((packed));
+
+
+/**
+ * i2400m_system_state - different states of the device
+ */
+enum i2400m_system_state {
+        I2400M_SS_UNINITIALIZED = 1,
+        I2400M_SS_INIT,
+        I2400M_SS_READY,
+        I2400M_SS_SCAN,
+        I2400M_SS_STANDBY,
+        I2400M_SS_CONNECTING,
+        I2400M_SS_WIMAX_CONNECTED,
+        I2400M_SS_DATA_PATH_CONNECTED,
+        I2400M_SS_IDLE,
+        I2400M_SS_DISCONNECTING,
+        I2400M_SS_OUT_OF_ZONE,
+        I2400M_SS_SLEEPACTIVE,
+        I2400M_SS_PRODUCTION,
+        I2400M_SS_CONFIG,
+        I2400M_SS_RF_OFF,
+        I2400M_SS_RF_SHUTDOWN,
+        I2400M_SS_DEVICE_DISCONNECT,
+        I2400M_SS_MAX,
+};
+
+
+/**
+ * i2400m_tlv_system_state - report on the state of the system
+ *
+ * @state: see enum i2400m_system_state
+ */
+struct i2400m_tlv_system_state {
+        struct i2400m_tlv_hdr hdr;
+        __le32 state;
+} __attribute__((packed));
+
+
+struct i2400m_tlv_l4_message_versions {
+        struct i2400m_tlv_hdr hdr;
+        __le16 major;
+        __le16 minor;
+        __le16 branch;
+        __le16 reserved;
+} __attribute__((packed));
+
+
+struct i2400m_tlv_detailed_device_info {
+        struct i2400m_tlv_hdr hdr;
+        __u8 reserved1[400];
+        __u8 mac_address[6];
+        __u8 reserved2[2];
+} __attribute__((packed));
+
+
+enum i2400m_rf_switch_status {
+        I2400M_RF_SWITCH_ON = 1,
+        I2400M_RF_SWITCH_OFF = 2,
+};
+
+struct i2400m_tlv_rf_switches_status {
+        struct i2400m_tlv_hdr hdr;
+        __u8 sw_rf_switch;      /* 1 ON, 2 OFF */
+        __u8 hw_rf_switch;      /* 1 ON, 2 OFF */
+        __u8 reserved[2];
+} __attribute__((packed));
+
+
+enum {
+        i2400m_rf_operation_on = 1,
+        i2400m_rf_operation_off = 2
+};
+
+struct i2400m_tlv_rf_operation {
+        struct i2400m_tlv_hdr hdr;
+        __le32 status;  /* 1 ON, 2 OFF */
+} __attribute__((packed));
+
+
+enum i2400m_tlv_reset_type {
+        I2400M_RESET_TYPE_COLD = 1,
+        I2400M_RESET_TYPE_WARM
+};
+
+struct i2400m_tlv_device_reset_type {
+        struct i2400m_tlv_hdr hdr;
+        __le32 reset_type;
+} __attribute__((packed));
+
+
+struct i2400m_tlv_config_idle_parameters {
+        struct i2400m_tlv_hdr hdr;
+        __le32 idle_timeout;    /* 100 to 300000 ms [5min], 100 increments
+                                 * 0 disabled */
+        __le32 idle_paging_interval;    /* frames */
+} __attribute__((packed));
+
+
+enum i2400m_media_status {
+        I2400M_MEDIA_STATUS_LINK_UP = 1,
+        I2400M_MEDIA_STATUS_LINK_DOWN,
+        I2400M_MEDIA_STATUS_LINK_RENEW,
+};
+
+struct i2400m_tlv_media_status {
+        struct i2400m_tlv_hdr hdr;
+        __le32 media_status;
+} __attribute__((packed));
+
+#endif /* #ifndef __LINUX__WIMAX__I2400M_H__ */
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
index ccdc562e444e..2dc2eb2b8e22 100644
--- a/include/mtd/ubi-user.h
+++ b/include/mtd/ubi-user.h
@@ -253,7 +253,7 @@ struct ubi_mkvol_req {
  *
  * Re-sizing is possible for both dynamic and static volumes. But while dynamic
  * volumes may be re-sized arbitrarily, static volumes cannot be made to be
- * smaller then the number of bytes they bear. To arbitrarily shrink a static
+ * smaller than the number of bytes they bear. To arbitrarily shrink a static
  * volume, it must be wiped out first (by means of volume update operation with
  * zero number of bytes).
  */
diff --git a/include/net/wimax.h b/include/net/wimax.h
new file mode 100644
index 000000000000..1602614fdaf9
--- /dev/null
+++ b/include/net/wimax.h
@@ -0,0 +1,520 @@
+/*
+ * Linux WiMAX
+ * Kernel space API for accessing WiMAX devices
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * The WiMAX stack provides an API for controlling and managing the
+ * system's WiMAX devices. This API affects the control plane; the
+ * data plane is accessed via the network stack (netdev).
+ *
+ * Parts of the WiMAX stack API and notifications are exported to
+ * user space via Generic Netlink. In user space, libwimax (part of
+ * the wimax-tools package) provides a shim layer for accessing those
+ * calls.
+ *
+ * The API is standarized for all WiMAX devices and different drivers
+ * implement the backend support for it. However, device-specific
+ * messaging pipes are provided that can be used to issue commands and
+ * receive notifications in free form.
+ *
+ * Currently the messaging pipes are the only means of control as it
+ * is not known (due to the lack of more devices in the market) what
+ * will be a good abstraction layer. Expect this to change as more
+ * devices show in the market. This API is designed to be growable in
+ * order to address this problem.
+ *
+ * USAGE
+ *
+ * Embed a `struct wimax_dev` at the beginning of the the device's
+ * private structure, initialize and register it. For details, see
+ * `struct wimax_dev`s documentation.
+ *
+ * Once this is done, wimax-tools's libwimaxll can be used to
+ * communicate with the driver from user space. You user space
+ * application does not have to forcibily use libwimaxll and can talk
+ * the generic netlink protocol directly if desired.
+ *
+ * Remember this is a very low level API that will to provide all of
+ * WiMAX features. Other daemons and services running in user space
+ * are the expected clients of it. They offer a higher level API that
+ * applications should use (an example of this is the Intel's WiMAX
+ * Network Service for the i2400m).
+ *
+ * DESIGN
+ *
+ * Although not set on final stone, this very basic interface is
+ * mostly completed. Remember this is meant to grow as new common
+ * operations are decided upon. New operations will be added to the
+ * interface, intent being on keeping backwards compatibility as much
+ * as possible.
+ *
+ * This layer implements a set of calls to control a WiMAX device,
+ * exposing a frontend to the rest of the kernel and user space (via
+ * generic netlink) and a backend implementation in the driver through
+ * function pointers.
+ *
+ * WiMAX devices have a state, and a kernel-only API allows the
+ * drivers to manipulate that state. State transitions are atomic, and
+ * only some of them are allowed (see `enum wimax_st`).
+ *
+ * Most API calls will set the state automatically; in most cases
+ * drivers have to only report state changes due to external
+ * conditions.
+ *
+ * All API operations are 'atomic', serialized thorough a mutex in the
+ * `struct wimax_dev`.
+ *
+ * EXPORTING TO USER SPACE THROUGH GENERIC NETLINK
+ *
+ * The API is exported to user space using generic netlink (other
+ * methods can be added as needed).
+ *
+ * There is a Generic Netlink Family named "WiMAX", where interfaces
+ * supporting the WiMAX interface receive commands and broadcast their
+ * signals over a multicast group named "msg".
+ *
+ * Mapping to the source/destination interface is done by an interface
+ * index attribute.
+ *
+ * For user-to-kernel traffic (commands) we use a function call
+ * marshalling mechanism, where a message X with attributes A, B, C
+ * sent from user space to kernel space means executing the WiMAX API
+ * call wimax_X(A, B, C), sending the results back as a message.
+ *
+ * Kernel-to-user (notifications or signals) communication is sent
+ * over multicast groups. This allows to have multiple applications
+ * monitoring them.
+ *
+ * Each command/signal gets assigned it's own attribute policy. This
+ * way the validator will verify that all the attributes in there are
+ * only the ones that should be for each command/signal. Thing of an
+ * attribute mapping to a type+argumentname for each command/signal.
+ *
+ * If we had a single policy for *all* commands/signals, after running
+ * the validator we'd have to check "does this attribute belong in
+ * here"?  for each one. It can be done manually, but it's just easier
+ * to have the validator do that job with multiple policies. As well,
+ * it makes it easier to later expand each command/signal signature
+ * without affecting others and keeping the namespace more or less
+ * sane. Not that it is too complicated, but it makes it even easier.
+ *
+ * No state information is maintained in the kernel for each user
+ * space connection (the connection is stateless).
+ *
+ * TESTING FOR THE INTERFACE AND VERSIONING
+ *
+ * If network interface X is a WiMAX device, there will be a Generic
+ * Netlink family named "WiMAX X" and the device will present a
+ * "wimax" directory in it's network sysfs directory
+ * (/sys/class/net/DEVICE/wimax) [used by HAL].
+ *
+ * The inexistence of any of these means the device does not support
+ * this WiMAX API.
+ *
+ * By querying the generic netlink controller, versioning information
+ * and the multicast groups available can be found. Applications using
+ * the interface can either rely on that or use the generic netlink
+ * controller to figure out which generic netlink commands/signals are
+ * supported.
+ *
+ * NOTE: this versioning is a last resort to avoid hard
+ *    incompatibilities. It is the intention of the design of this
+ *    stack not to introduce backward incompatible changes.
+ *
+ * The version code has to fit in one byte (restrictions imposed by
+ * generic netlink); we use `version / 10` for the major version and
+ * `version % 10` for the minor. This gives 9 minors for each major
+ * and 25 majors.
+ *
+ * The version change protocol is as follow:
+ *
+ * - Major versions: needs to be increased if an existing message/API
+ *   call is changed or removed. Doesn't need to be changed if a new
+ *   message is added.
+ *
+ * - Minor version: needs to be increased if new messages/API calls are
+ *   being added or some other consideration that doesn't impact the
+ *   user-kernel interface too much (like some kind of bug fix) and
+ *   that is kind of left up in the air to common sense.
+ *
+ * User space code should not try to work if the major version it was
+ * compiled for differs from what the kernel offers. As well, if the
+ * minor version of the kernel interface is lower than the one user
+ * space is expecting (the one it was compiled for), the kernel
+ * might be missing API calls; user space shall be ready to handle
+ * said condition. Use the generic netlink controller operations to
+ * find which ones are supported and which not.
+ *
+ * libwimaxll:wimaxll_open() takes care of checking versions.
+ *
+ * THE OPERATIONS:
+ *
+ * Each operation is defined in its on file (drivers/net/wimax/op-*.c)
+ * for clarity. The parts needed for an operation are:
+ *
+ *  - a function pointer in `struct wimax_dev`: optional, as the
+ *    operation might be implemented by the stack and not by the
+ *    driver.
+ *
+ *    All function pointers are named wimax_dev->op_*(), and drivers
+ *    must implement them except where noted otherwise.
+ *
+ *  - When exported to user space, a `struct nla_policy` to define the
+ *    attributes of the generic netlink command and a `struct genl_ops`
+ *    to define the operation.
+ *
+ * All the declarations for the operation codes (WIMAX_GNL_OP_<NAME>)
+ * and generic netlink attributes (WIMAX_GNL_<NAME>_*) are declared in
+ * include/linux/wimax.h; this file is intended to be cloned by user
+ * space to gain access to those declarations.
+ *
+ * A few caveats to remember:
+ *
+ *  - Need to define attribute numbers starting in 1; otherwise it
+ *    fails.
+ *
+ *  - the `struct genl_family` requires a maximum attribute id; when
+ *    defining the `struct nla_policy` for each message, it has to have
+ *    an array size of WIMAX_GNL_ATTR_MAX+1.
+ *
+ * THE PIPE INTERFACE:
+ *
+ * This interface is kept intentionally simple. The driver can send
+ * and receive free-form messages to/from user space through a
+ * pipe. See drivers/net/wimax/op-msg.c for details.
+ *
+ * The kernel-to-user messages are sent with
+ * wimax_msg(). user-to-kernel messages are delivered via
+ * wimax_dev->op_msg_from_user().
+ *
+ * RFKILL:
+ *
+ * RFKILL support is built into the wimax_dev layer; the driver just
+ * needs to call wimax_report_rfkill_{hw,sw}() to inform of changes in
+ * the hardware or software RF kill switches. When the stack wants to
+ * turn the radio off, it will call wimax_dev->op_rfkill_sw_toggle(),
+ * which the driver implements.
+ *
+ * User space can set the software RF Kill switch by calling
+ * wimax_rfkill().
+ *
+ * The code for now only supports devices that don't require polling;
+ * If the device needs to be polled, create a self-rearming delayed
+ * work struct for polling or look into adding polled support to the
+ * WiMAX stack.
+ *
+ * When initializing the hardware (_probe), after calling
+ * wimax_dev_add(), query the device for it's RF Kill switches status
+ * and feed it back to the WiMAX stack using
+ * wimax_report_rfkill_{hw,sw}(). If any switch is missing, always
+ * report it as ON.
+ *
+ * NOTE: the wimax stack uses an inverted terminology to that of the
+ * RFKILL subsystem:
+ *
+ *  - ON: radio is ON, RFKILL is DISABLED or OFF.
+ *  - OFF: radio is OFF, RFKILL is ENABLED or ON.
+ *
+ * MISCELLANEOUS OPS:
+ *
+ * wimax_reset() can be used to reset the device to power on state; by
+ * default it issues a warm reset that maintains the same device
+ * node. If that is not possible, it falls back to a cold reset
+ * (device reconnect). The driver implements the backend to this
+ * through wimax_dev->op_reset().
+ */
+
+#ifndef __NET__WIMAX_H__
+#define __NET__WIMAX_H__
+#ifdef __KERNEL__
+
+#include <linux/wimax.h>
+#include <net/genetlink.h>
+#include <linux/netdevice.h>
+
+struct net_device;
+struct genl_info;
+struct wimax_dev;
+struct input_dev;
+
+/**
+ * struct wimax_dev - Generic WiMAX device
+ *
+ * @net_dev: [fill] Pointer to the &struct net_device this WiMAX
+ *     device implements.
+ *
+ * @op_msg_from_user: [fill] Driver-specific operation to
+ *     handle a raw message from user space to the driver. The
+ *     driver can send messages to user space using with
+ *     wimax_msg_to_user().
+ *
+ * @op_rfkill_sw_toggle: [fill] Driver-specific operation to act on
+ *     userspace (or any other agent) requesting the WiMAX device to
+ *     change the RF Kill software switch (WIMAX_RF_ON or
+ *     WIMAX_RF_OFF).
+ *     If such hardware support is not present, it is assumed the
+ *     radio cannot be switched off and it is always on (and the stack
+ *     will error out when trying to switch it off). In such case,
+ *     this function pointer can be left as NULL.
+ *
+ * @op_reset: [fill] Driver specific operation to reset the
+ *     device.
+ *     This operation should always attempt first a warm reset that
+ *     does not disconnect the device from the bus and return 0.
+ *     If that fails, it should resort to some sort of cold or bus
+ *     reset (even if it implies a bus disconnection and device
+ *     dissapearance). In that case, -ENODEV should be returned to
+ *     indicate the device is gone.
+ *     This operation has to be synchronous, and return only when the
+ *     reset is complete. In case of having had to resort to bus/cold
+ *     reset implying a device disconnection, the call is allowed to
+ *     return inmediately.
+ *     NOTE: wimax_dev->mutex is NOT locked when this op is being
+ *     called; however, wimax_dev->mutex_reset IS locked to ensure
+ *     serialization of calls to wimax_reset().
+ *     See wimax_reset()'s documentation.
+ *
+ * @name: [fill] A way to identify this device. We need to register a
+ *     name with many subsystems (input for RFKILL, workqueue
+ *     creation, etc). We can't use the network device name as that
+ *     might change and in some instances we don't know it yet (until
+ *     we don't call register_netdev()). So we generate an unique one
+ *     using the driver name and device bus id, place it here and use
+ *     it across the board. Recommended naming:
+ *     DRIVERNAME-BUSNAME:BUSID (dev->bus->name, dev->bus_id).
+ *
+ * @id_table_node: [private] link to the list of wimax devices kept by
+ *     id-table.c. Protected by it's own spinlock.
+ *
+ * @mutex: [private] Serializes all concurrent access and execution of
+ *     operations.
+ *
+ * @mutex_reset: [private] Serializes reset operations. Needs to be a
+ *     different mutex because as part of the reset operation, the
+ *     driver has to call back into the stack to do things such as
+ *     state change, that require wimax_dev->mutex.
+ *
+ * @state: [private] Current state of the WiMAX device.
+ *
+ * @rfkill: [private] integration into the RF-Kill infrastructure.
+ *
+ * @rfkill_input: [private] virtual input device to process the
+ *     hardware RF Kill switches.
+ *
+ * @rf_sw: [private] State of the software radio switch (OFF/ON)
+ *
+ * @rf_hw: [private] State of the hardware radio switch (OFF/ON)
+ *
+ * Description:
+ * This structure defines a common interface to access all WiMAX
+ * devices from different vendors and provides a common API as well as
+ * a free-form device-specific messaging channel.
+ *
+ * Usage:
+ *  1. Embed a &struct wimax_dev at *the beginning* the network
+ *     device structure so that netdev_priv() points to it.
+ *
+ *  2. memset() it to zero
+ *
+ *  3. Initialize with wimax_dev_init(). This will leave the WiMAX
+ *     device in the %__WIMAX_ST_NULL state.
+ *
+ *  4. Fill all the fields marked with [fill]; once called
+ *     wimax_dev_add(), those fields CANNOT be modified.
+ *
+ *  5. Call wimax_dev_add() *after* registering the network
+ *     device. This will leave the WiMAX device in the %WIMAX_ST_DOWN
+ *     state.
+ *     Protect the driver's net_device->open() against succeeding if
+ *     the wimax device state is lower than %WIMAX_ST_DOWN.
+ *
+ *  6. Select when the device is going to be turned on/initialized;
+ *     for example, it could be initialized on 'ifconfig up' (when the
+ *     netdev op 'open()' is called on the driver).
+ *
+ * When the device is initialized (at `ifconfig up` time, or right
+ * after calling wimax_dev_add() from _probe(), make sure the
+ * following steps are taken
+ *
+ *  a. Move the device to %WIMAX_ST_UNINITIALIZED. This is needed so
+ *     some API calls that shouldn't work until the device is ready
+ *     can be blocked.
+ *
+ *  b. Initialize the device. Make sure to turn the SW radio switch
+ *     off and move the device to state %WIMAX_ST_RADIO_OFF when
+ *     done. When just initialized, a device should be left in RADIO
+ *     OFF state until user space devices to turn it on.
+ *
+ *  c. Query the device for the state of the hardware rfkill switch
+ *     and call wimax_rfkill_report_hw() and wimax_rfkill_report_sw()
+ *     as needed. See below.
+ *
+ * wimax_dev_rm() undoes before unregistering the network device. Once
+ * wimax_dev_add() is called, the driver can get called on the
+ * wimax_dev->op_* function pointers
+ *
+ * CONCURRENCY:
+ *
+ * The stack provides a mutex for each device that will disallow API
+ * calls happening concurrently; thus, op calls into the driver
+ * through the wimax_dev->op*() function pointers will always be
+ * serialized and *never* concurrent.
+ *
+ * For locking, take wimax_dev->mutex is taken; (most) operations in
+ * the API have to check for wimax_dev_is_ready() to return 0 before
+ * continuing (this is done internally).
+ *
+ * REFERENCE COUNTING:
+ *
+ * The WiMAX device is reference counted by the associated network
+ * device. The only operation that can be used to reference the device
+ * is wimax_dev_get_by_genl_info(), and the reference it acquires has
+ * to be released with dev_put(wimax_dev->net_dev).
+ *
+ * RFKILL:
+ *
+ * At startup, both HW and SW radio switchess are assumed to be off.
+ *
+ * At initialization time [after calling wimax_dev_add()], have the
+ * driver query the device for the status of the software and hardware
+ * RF kill switches and call wimax_report_rfkill_hw() and
+ * wimax_rfkill_report_sw() to indicate their state. If any is
+ * missing, just call it to indicate it is ON (radio always on).
+ *
+ * Whenever the driver detects a change in the state of the RF kill
+ * switches, it should call wimax_report_rfkill_hw() or
+ * wimax_report_rfkill_sw() to report it to the stack.
+ */
+struct wimax_dev {
+        struct net_device *net_dev;
+        struct list_head id_table_node;
+        struct mutex mutex;             /* Protects all members and API calls */
+        struct mutex mutex_reset;
+        enum wimax_st state;
+
+        int (*op_msg_from_user)(struct wimax_dev *wimax_dev,
+                                const char *,
+                                const void *, size_t,
+                                const struct genl_info *info);
+        int (*op_rfkill_sw_toggle)(struct wimax_dev *wimax_dev,
+                                   enum wimax_rf_state);
+        int (*op_reset)(struct wimax_dev *wimax_dev);
+
+        struct rfkill *rfkill;
+        struct input_dev *rfkill_input;
+        unsigned rf_hw;
+        unsigned rf_sw;
+        char name[32];
+
+        struct dentry *debugfs_dentry;
+};
+
+
+
+/*
+ * WiMAX stack public API for device drivers
+ * -----------------------------------------
+ *
+ * These functions are not exported to user space.
+ */
+extern void wimax_dev_init(struct wimax_dev *);
+extern int wimax_dev_add(struct wimax_dev *, struct net_device *);
+extern void wimax_dev_rm(struct wimax_dev *);
+
+static inline
+struct wimax_dev *net_dev_to_wimax(struct net_device *net_dev)
+{
+        return netdev_priv(net_dev);
+}
+
+static inline
+struct device *wimax_dev_to_dev(struct wimax_dev *wimax_dev)
+{
+        return wimax_dev->net_dev->dev.parent;
+}
+
+extern void wimax_state_change(struct wimax_dev *, enum wimax_st);
+extern enum wimax_st wimax_state_get(struct wimax_dev *);
+
+/*
+ * Radio Switch state reporting.
+ *
+ * enum wimax_rf_state is declared in linux/wimax.h so the exports
+ * to user space can use it.
+ */
+extern void wimax_report_rfkill_hw(struct wimax_dev *, enum wimax_rf_state);
+extern void wimax_report_rfkill_sw(struct wimax_dev *, enum wimax_rf_state);
+
+
+/*
+ * Free-form messaging to/from user space
+ *
+ * Sending a message:
+ *
+ *   wimax_msg(wimax_dev, pipe_name, buf, buf_size, GFP_KERNEL);
+ *
+ * Broken up:
+ *
+ *   skb = wimax_msg_alloc(wimax_dev, pipe_name, buf_size, GFP_KERNEL);
+ *   ...fill up skb...
+ *   wimax_msg_send(wimax_dev, pipe_name, skb);
+ *
+ * Be sure not to modify skb->data in the middle (ie: don't use
+ * skb_push()/skb_pull()/skb_reserve() on the skb).
+ *
+ * "pipe_name" is any string, than can be interpreted as the name of
+ * the pipe or destinatary; the interpretation of it is driver
+ * specific, so the recipient can multiplex it as wished. It can be
+ * NULL, it won't be used - an example is using a "diagnostics" tag to
+ * send diagnostics information that a device-specific diagnostics
+ * tool would be interested in.
+ */
+extern struct sk_buff *wimax_msg_alloc(struct wimax_dev *, const char *,
+                                       const void *, size_t, gfp_t);
+extern int wimax_msg_send(struct wimax_dev *, struct sk_buff *);
+extern int wimax_msg(struct wimax_dev *, const char *,
+                     const void *, size_t, gfp_t);
+
+extern const void *wimax_msg_data_len(struct sk_buff *, size_t *);
+extern const void *wimax_msg_data(struct sk_buff *);
+extern ssize_t wimax_msg_len(struct sk_buff *);
+
+
+/*
+ * WiMAX stack user space API
+ * --------------------------
+ *
+ * This API is what gets exported to user space for general
+ * operations. As well, they can be called from within the kernel,
+ * (with a properly referenced `struct wimax_dev`).
+ *
+ * Properly referenced means: the 'struct net_device' that embeds the
+ * device's control structure and (as such) the 'struct wimax_dev' is
+ * referenced by the caller.
+ */
+extern int wimax_rfkill(struct wimax_dev *, enum wimax_rf_state);
+extern int wimax_reset(struct wimax_dev *);
+
+#else
+/* You might be looking for linux/wimax.h */
+#error This file should not be included from user space.
+#endif /* #ifdef __KERNEL__ */
+#endif /* #ifndef __NET__WIMAX_H__ */
diff --git a/init/do_mounts.c b/init/do_mounts.c
index 5efca73b39f9..708105e163df 100644
--- a/init/do_mounts.c
+++ b/init/do_mounts.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/initrd.h>
+#include <linux/async.h>
 
 #include <linux/nfs_fs.h>
 #include <linux/nfs_fs_sb.h>
@@ -372,6 +373,7 @@ void __init prepare_namespace(void)
         /* wait for the known devices to complete their probing */
         while (driver_probe_done() != 0)
                 msleep(100);
+        async_synchronize_full();
 
         md_run_setup();
 
diff --git a/init/main.c b/init/main.c
index b5a892c68375..844209453c02 100644
--- a/init/main.c
+++ b/init/main.c
@@ -62,6 +62,7 @@
 #include <linux/signal.h>
 #include <linux/idr.h>
 #include <linux/ftrace.h>
+#include <linux/async.h>
 #include <trace/boot.h>
 
 #include <asm/io.h>
@@ -599,7 +600,8 @@ asmlinkage void __init start_kernel(void)
         sched_clock_init();
         profile_init();
         if (!irqs_disabled())
-                printk("start_kernel(): bug: interrupts were enabled early\n");
+                printk(KERN_CRIT "start_kernel(): bug: interrupts were "
+                                 "enabled early\n");
         early_boot_irqs_on();
         local_irq_enable();
 
@@ -684,7 +686,7 @@ asmlinkage void __init start_kernel(void)
         rest_init();
 }
 
-static int initcall_debug;
+int initcall_debug;
 core_param(initcall_debug, initcall_debug, bool, 0644);
 
 int do_one_initcall(initcall_t fn)
@@ -785,6 +787,8 @@ static void run_init_process(char *init_filename)
  */
 static noinline int init_post(void)
 {
+        /* need to finish all async __init code before freeing the memory */
+        async_synchronize_full();
         free_initmem();
         unlock_kernel();
         mark_rodata_ro();
diff --git a/kernel/Makefile b/kernel/Makefile
index e1c5bf3365c0..2921d90ce32f 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -9,7 +9,8 @@ obj-y     = sched.o fork.o exec_domain.o panic.o printk.o \
             rcupdate.o extable.o params.o posix-timers.o \
             kthread.o wait.o kfifo.o sys_ni.o posix-cpu-timers.o mutex.o \
             hrtimer.o rwsem.o nsproxy.o srcu.o semaphore.o \
-            notifier.o ksysfs.o pm_qos_params.o sched_clock.o cred.o
+            notifier.o ksysfs.o pm_qos_params.o sched_clock.o cred.o \
+            async.o
 
 ifdef CONFIG_FUNCTION_TRACER
 # Do not trace debug files and internal ftrace files
diff --git a/kernel/async.c b/kernel/async.c
new file mode 100644
index 000000000000..97373380c9e7
--- /dev/null
+++ b/kernel/async.c
@@ -0,0 +1,321 @@
+/*
+ * async.c: Asynchronous function calls for boot performance
+ *
+ * (C) Copyright 2009 Intel Corporation
+ * Author: Arjan van de Ven <arjan@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+
+/*
+
+Goals and Theory of Operation
+
+The primary goal of this feature is to reduce the kernel boot time,
+by doing various independent hardware delays and discovery operations
+decoupled and not strictly serialized.
+
+More specifically, the asynchronous function call concept allows
+certain operations (primarily during system boot) to happen
+asynchronously, out of order, while these operations still
+have their externally visible parts happen sequentially and in-order.
+(not unlike how out-of-order CPUs retire their instructions in order)
+
+Key to the asynchronous function call implementation is the concept of
+a "sequence cookie" (which, although it has an abstracted type, can be
+thought of as a monotonically incrementing number).
+
+The async core will assign each scheduled event such a sequence cookie and
+pass this to the called functions.
+
+The asynchronously called function should before doing a globally visible
+operation, such as registering device numbers, call the
+async_synchronize_cookie() function and pass in its own cookie. The
+async_synchronize_cookie() function will make sure that all asynchronous
+operations that were scheduled prior to the operation corresponding with the
+cookie have completed.
+
+Subsystem/driver initialization code that scheduled asynchronous probe
+functions, but which shares global resources with other drivers/subsystems
+that do not use the asynchronous call feature, need to do a full
+synchronization with the async_synchronize_full() function, before returning
+from their init function. This is to maintain strict ordering between the
+asynchronous and synchronous parts of the kernel.
+
+*/
+
+#include <linux/async.h>
+#include <linux/module.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/kthread.h>
+#include <asm/atomic.h>
+
+static async_cookie_t next_cookie = 1;
+
+#define MAX_THREADS     256
+#define MAX_WORK        32768
+
+static LIST_HEAD(async_pending);
+static LIST_HEAD(async_running);
+static DEFINE_SPINLOCK(async_lock);
+
+struct async_entry {
+        struct list_head list;
+        async_cookie_t   cookie;
+        async_func_ptr   *func;
+        void             *data;
+        struct list_head *running;
+};
+
+static DECLARE_WAIT_QUEUE_HEAD(async_done);
+static DECLARE_WAIT_QUEUE_HEAD(async_new);
+
+static atomic_t entry_count;
+static atomic_t thread_count;
+
+extern int initcall_debug;
+
+
+/*
+ * MUST be called with the lock held!
+ */
+static async_cookie_t  __lowest_in_progress(struct list_head *running)
+{
+        struct async_entry *entry;
+        if (!list_empty(&async_pending)) {
+                entry = list_first_entry(&async_pending,
+                        struct async_entry, list);
+                return entry->cookie;
+        } else if (!list_empty(running)) {
+                entry = list_first_entry(running,
+                        struct async_entry, list);
+                return entry->cookie;
+        } else {
+                /* nothing in progress... next_cookie is "infinity" */
+                return next_cookie;
+        }
+
+}
+/*
+ * pick the first pending entry and run it
+ */
+static void run_one_entry(void)
+{
+        unsigned long flags;
+        struct async_entry *entry;
+        ktime_t calltime, delta, rettime;
+
+        /* 1) pick one task from the pending queue */
+
+        spin_lock_irqsave(&async_lock, flags);
+        if (list_empty(&async_pending))
+                goto out;
+        entry = list_first_entry(&async_pending, struct async_entry, list);
+
+        /* 2) move it to the running queue */
+        list_del(&entry->list);
+        list_add_tail(&entry->list, &async_running);
+        spin_unlock_irqrestore(&async_lock, flags);
+
+        /* 3) run it (and print duration)*/
+        if (initcall_debug && system_state == SYSTEM_BOOTING) {
+                printk("calling  %lli_%pF @ %i\n", entry->cookie, entry->func, task_pid_nr(current));
+                calltime = ktime_get();
+        }
+        entry->func(entry->data, entry->cookie);
+        if (initcall_debug && system_state == SYSTEM_BOOTING) {
+                rettime = ktime_get();
+                delta = ktime_sub(rettime, calltime);
+                printk("initcall %lli_%pF returned 0 after %lld usecs\n", entry->cookie,
+                        entry->func, ktime_to_ns(delta) >> 10);
+        }
+
+        /* 4) remove it from the running queue */
+        spin_lock_irqsave(&async_lock, flags);
+        list_del(&entry->list);
+
+        /* 5) free the entry  */
+        kfree(entry);
+        atomic_dec(&entry_count);
+
+        spin_unlock_irqrestore(&async_lock, flags);
+
+        /* 6) wake up any waiters. */
+        wake_up(&async_done);
+        return;
+
+out:
+        spin_unlock_irqrestore(&async_lock, flags);
+}
+
+
+static async_cookie_t __async_schedule(async_func_ptr *ptr, void *data, struct list_head *running)
+{
+        struct async_entry *entry;
+        unsigned long flags;
+        async_cookie_t newcookie;
+        
+
+        /* allow irq-off callers */
+        entry = kzalloc(sizeof(struct async_entry), GFP_ATOMIC);
+
+        /*
+         * If we're out of memory or if there's too much work
+         * pending already, we execute synchronously.
+         */
+        if (!entry || atomic_read(&entry_count) > MAX_WORK) {
+                kfree(entry);
+                spin_lock_irqsave(&async_lock, flags);
+                newcookie = next_cookie++;
+                spin_unlock_irqrestore(&async_lock, flags);
+
+                /* low on memory.. run synchronously */
+                ptr(data, newcookie);
+                return newcookie;
+        }
+        entry->func = ptr;
+        entry->data = data;
+        entry->running = running;
+
+        spin_lock_irqsave(&async_lock, flags);
+        newcookie = entry->cookie = next_cookie++;
+        list_add_tail(&entry->list, &async_pending);
+        atomic_inc(&entry_count);
+        spin_unlock_irqrestore(&async_lock, flags);
+        wake_up(&async_new);
+        return newcookie;
+}
+
+async_cookie_t async_schedule(async_func_ptr *ptr, void *data)
+{
+        return __async_schedule(ptr, data, &async_pending);
+}
+EXPORT_SYMBOL_GPL(async_schedule);
+
+async_cookie_t async_schedule_special(async_func_ptr *ptr, void *data, struct list_head *running)
+{
+        return __async_schedule(ptr, data, running);
+}
+EXPORT_SYMBOL_GPL(async_schedule_special);
+
+void async_synchronize_full(void)
+{
+        async_synchronize_cookie(next_cookie);
+}
+EXPORT_SYMBOL_GPL(async_synchronize_full);
+
+void async_synchronize_full_special(struct list_head *list)
+{
+        async_synchronize_cookie_special(next_cookie, list);
+}
+EXPORT_SYMBOL_GPL(async_synchronize_full_special);
+
+void async_synchronize_cookie_special(async_cookie_t cookie, struct list_head *running)
+{
+        ktime_t starttime, delta, endtime;
+
+        if (initcall_debug && system_state == SYSTEM_BOOTING) {
+                printk("async_waiting @ %i\n", task_pid_nr(current));
+                starttime = ktime_get();
+        }
+
+        wait_event(async_done, __lowest_in_progress(running) >= cookie);
+
+        if (initcall_debug && system_state == SYSTEM_BOOTING) {
+                endtime = ktime_get();
+                delta = ktime_sub(endtime, starttime);
+
+                printk("async_continuing @ %i after %lli usec\n",
+                        task_pid_nr(current), ktime_to_ns(delta) >> 10);
+        }
+}
+EXPORT_SYMBOL_GPL(async_synchronize_cookie_special);
+
+void async_synchronize_cookie(async_cookie_t cookie)
+{
+        async_synchronize_cookie_special(cookie, &async_running);
+}
+EXPORT_SYMBOL_GPL(async_synchronize_cookie);
+
+
+static int async_thread(void *unused)
+{
+        DECLARE_WAITQUEUE(wq, current);
+        add_wait_queue(&async_new, &wq);
+
+        while (!kthread_should_stop()) {
+                int ret = HZ;
+                set_current_state(TASK_INTERRUPTIBLE);
+                /*
+                 * check the list head without lock.. false positives
+                 * are dealt with inside run_one_entry() while holding
+                 * the lock.
+                 */
+                rmb();
+                if (!list_empty(&async_pending))
+                        run_one_entry();
+                else
+                        ret = schedule_timeout(HZ);
+
+                if (ret == 0) {
+                        /*
+                         * we timed out, this means we as thread are redundant.
+                         * we sign off and die, but we to avoid any races there
+                         * is a last-straw check to see if work snuck in.
+                         */
+                        atomic_dec(&thread_count);
+                        wmb(); /* manager must see our departure first */
+                        if (list_empty(&async_pending))
+                                break;
+                        /*
+                         * woops work came in between us timing out and us
+                         * signing off; we need to stay alive and keep working.
+                         */
+                        atomic_inc(&thread_count);
+                }
+        }
+        remove_wait_queue(&async_new, &wq);
+
+        return 0;
+}
+
+static int async_manager_thread(void *unused)
+{
+        DECLARE_WAITQUEUE(wq, current);
+        add_wait_queue(&async_new, &wq);
+
+        while (!kthread_should_stop()) {
+                int tc, ec;
+
+                set_current_state(TASK_INTERRUPTIBLE);
+
+                tc = atomic_read(&thread_count);
+                rmb();
+                ec = atomic_read(&entry_count);
+
+                while (tc < ec && tc < MAX_THREADS) {
+                        kthread_run(async_thread, NULL, "async/%i", tc);
+                        atomic_inc(&thread_count);
+                        tc++;
+                }
+
+                schedule();
+        }
+        remove_wait_queue(&async_new, &wq);
+
+        return 0;
+}
+
+static int __init async_init(void)
+{
+        kthread_run(async_manager_thread, NULL, "async/mgr");
+        return 0;
+}
+
+core_initcall(async_init);
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 30e74dd6d01b..79e40f00dcb8 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -379,8 +379,11 @@ static cpumask_var_t frozen_cpus;
 
 int disable_nonboot_cpus(void)
 {
-        int cpu, first_cpu, error = 0;
+        int cpu, first_cpu, error;
 
+        error = stop_machine_create();
+        if (error)
+                return error;
         cpu_maps_update_begin();
         first_cpu = cpumask_first(cpu_online_mask);
         /* We take down all of the non-boot CPUs in one shot to avoid races
@@ -409,6 +412,7 @@ int disable_nonboot_cpus(void)
                 printk(KERN_ERR "Non-boot CPUs are not disabled\n");
         }
         cpu_maps_update_done();
+        stop_machine_destroy();
         return error;
 }
 
diff --git a/kernel/irq/autoprobe.c b/kernel/irq/autoprobe.c
index cc0f7321b8ce..1de9700f416e 100644
--- a/kernel/irq/autoprobe.c
+++ b/kernel/irq/autoprobe.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
+#include <linux/async.h>
 
 #include "internals.h"
 
@@ -34,6 +35,10 @@ unsigned long probe_irq_on(void)
         unsigned int status;
         int i;
 
+        /*
+         * quiesce the kernel, or at least the asynchronous portion
+         */
+        async_synchronize_full();
         mutex_lock(&probing_active);
         /*
          * something may have generated an irq long ago and we want to
diff --git a/kernel/module.c b/kernel/module.c
index 496dcb57b608..c9332c90d5a0 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -50,6 +50,7 @@
 #include <asm/sections.h>
 #include <linux/tracepoint.h>
 #include <linux/ftrace.h>
+#include <linux/async.h>
 
 #if 0
 #define DEBUGP printk
@@ -816,6 +817,7 @@ sys_delete_module(const char __user *name_user, unsigned int flags)
                 mod->exit();
         blocking_notifier_call_chain(&module_notify_list,
                                      MODULE_STATE_GOING, mod);
+        async_synchronize_full();
         mutex_lock(&module_mutex);
         /* Store the name of the last unloaded module for diagnostic purposes */
         strlcpy(last_unloaded_module, mod->name, sizeof(last_unloaded_module));
diff --git a/kernel/pid.c b/kernel/pid.c
index 064e76afa507..af9224cdd6c0 100644
--- a/kernel/pid.c
+++ b/kernel/pid.c
@@ -475,7 +475,7 @@ pid_t task_session_nr_ns(struct task_struct *tsk, struct pid_namespace *ns)
 EXPORT_SYMBOL(task_session_nr_ns);
 
 /*
- * Used by proc to find the first pid that is greater then or equal to nr.
+ * Used by proc to find the first pid that is greater than or equal to nr.
  *
  * If there is a pid at nr this function is exactly the same as find_pid_ns.
  */
diff --git a/kernel/printk.c b/kernel/printk.c
index e651ab05655f..7015733793e8 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -619,7 +619,7 @@ static int acquire_console_semaphore_for_printk(unsigned int cpu)
 static const char recursion_bug_msg [] =
                 KERN_CRIT "BUG: recent printk recursion!\n";
 static int recursion_bug;
-        static int new_text_line = 1;
+static int new_text_line = 1;
 static char printk_buf[1024];
 
 asmlinkage int vprintk(const char *fmt, va_list args)
diff --git a/kernel/time/jiffies.c b/kernel/time/jiffies.c
index 1ca99557e929..06f197560f3b 100644
--- a/kernel/time/jiffies.c
+++ b/kernel/time/jiffies.c
@@ -45,7 +45,7 @@
  *
  * The value 8 is somewhat carefully chosen, as anything
  * larger can result in overflows. NSEC_PER_JIFFY grows as
- * HZ shrinks, so values greater then 8 overflow 32bits when
+ * HZ shrinks, so values greater than 8 overflow 32bits when
  * HZ=100.
  */
 #define JIFFIES_SHIFT   8
diff --git a/lib/radix-tree.c b/lib/radix-tree.c
index 8d3fb0bd1288..4bb42a0344ec 100644
--- a/lib/radix-tree.c
+++ b/lib/radix-tree.c
@@ -640,13 +640,14 @@ EXPORT_SYMBOL(radix_tree_tag_get);
  *
  *      Returns: the index of the hole if found, otherwise returns an index
  *      outside of the set specified (in which case 'return - index >= max_scan'
- *      will be true).
+ *      will be true). In rare cases of index wrap-around, 0 will be returned.
  *
  *      radix_tree_next_hole may be called under rcu_read_lock. However, like
- *      radix_tree_gang_lookup, this will not atomically search a snapshot of the
- *      tree at a single point in time. For example, if a hole is created at index
- *      5, then subsequently a hole is created at index 10, radix_tree_next_hole
- *      covering both indexes may return 10 if called under rcu_read_lock.
+ *      radix_tree_gang_lookup, this will not atomically search a snapshot of
+ *      the tree at a single point in time. For example, if a hole is created
+ *      at index 5, then subsequently a hole is created at index 10,
+ *      radix_tree_next_hole covering both indexes may return 10 if called
+ *      under rcu_read_lock.
  */
 unsigned long radix_tree_next_hole(struct radix_tree_root *root,
                                 unsigned long index, unsigned long max_scan)
diff --git a/mm/slub.c b/mm/slub.c
index f0e2892fe403..6392ae5cc6b1 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2254,7 +2254,7 @@ static int calculate_sizes(struct kmem_cache *s, int forced_order)
                  * Add some empty padding so that we can catch
                  * overwrites from earlier objects rather than let
                  * tracking information or the free pointer be
-                 * corrupted if an user writes before the start
+                 * corrupted if a user writes before the start
                  * of the object.
                  */
                 size += sizeof(void *);
diff --git a/net/Kconfig b/net/Kconfig
index 6ec2cce7c167..bf2776018f71 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -254,6 +254,8 @@ source "net/mac80211/Kconfig"
 
 endif # WIRELESS
 
+source "net/wimax/Kconfig"
+
 source "net/rfkill/Kconfig"
 source "net/9p/Kconfig"
 
diff --git a/net/Makefile b/net/Makefile
index ba4460432b7c..0fcce89d7169 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -63,3 +63,4 @@ endif
 ifeq ($(CONFIG_NET),y)
 obj-$(CONFIG_SYSCTL)            += sysctl_net.o
 endif
+obj-$(CONFIG_WIMAX)             += wimax/
diff --git a/net/netlink/genetlink.c b/net/netlink/genetlink.c
index 3e1191cecaf0..1d3dd30099df 100644
--- a/net/netlink/genetlink.c
+++ b/net/netlink/genetlink.c
@@ -225,6 +225,7 @@ void genl_unregister_mc_group(struct genl_family *family,
         __genl_unregister_mc_group(family, grp);
         genl_unlock();
 }
+EXPORT_SYMBOL(genl_unregister_mc_group);
 
 static void genl_unregister_mc_groups(struct genl_family *family)
 {
diff --git a/net/sctp/auth.c b/net/sctp/auth.c
index 52db5f60daa0..20c576f530fa 100644
--- a/net/sctp/auth.c
+++ b/net/sctp/auth.c
@@ -141,8 +141,8 @@ void sctp_auth_destroy_keys(struct list_head *keys)
 /* Compare two byte vectors as numbers.  Return values
  * are:
  *        0 - vectors are equal
- *      < 0 - vector 1 is smaller then vector2
- *      > 0 - vector 1 is greater then vector2
+ *      < 0 - vector 1 is smaller than vector2
+ *      > 0 - vector 1 is greater than vector2
  *
  * Algorithm is:
  *      This is performed by selecting the numerically smaller key vector...
diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c
index 1c4e5d6c29c0..3a0cd075914f 100644
--- a/net/sctp/sm_statefuns.c
+++ b/net/sctp/sm_statefuns.c
@@ -4268,9 +4268,9 @@ nomem:
 
 /*
  * Handle a protocol violation when the chunk length is invalid.
- * "Invalid" length is identified as smaller then the minimal length a
+ * "Invalid" length is identified as smaller than the minimal length a
  * given chunk can be.  For example, a SACK chunk has invalid length
- * if it's length is set to be smaller then the size of sctp_sack_chunk_t.
+ * if its length is set to be smaller than the size of sctp_sack_chunk_t.
  *
  * We inform the other end by sending an ABORT with a Protocol Violation
  * error code.
@@ -4300,7 +4300,7 @@ static sctp_disposition_t sctp_sf_violation_chunklen(
 
 /*
  * Handle a protocol violation when the parameter length is invalid.
- * "Invalid" length is identified as smaller then the minimal length a
+ * "Invalid" length is identified as smaller than the minimal length a
  * given parameter can be.
  */
 static sctp_disposition_t sctp_sf_violation_paramlen(
diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index b14a8f33e42d..ff0a8f88de04 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -2717,7 +2717,7 @@ static int sctp_setsockopt_associnfo(struct sock *sk, char __user *optval, int o
                                 paths++;
                         }
 
-                        /* Only validate asocmaxrxt if we have more then
+                        /* Only validate asocmaxrxt if we have more than
                          * one path/transport.  We do this because path
                          * retransmissions are only counted when we have more
                          * then one path.
diff --git a/net/sctp/tsnmap.c b/net/sctp/tsnmap.c
index 35c73e82553a..9bd64565021a 100644
--- a/net/sctp/tsnmap.c
+++ b/net/sctp/tsnmap.c
@@ -227,7 +227,7 @@ void sctp_tsnmap_skip(struct sctp_tsnmap *map, __u32 tsn)
                  */
                 bitmap_zero(map->tsn_map, map->len);
         } else {
-                /* If the gap is smaller then the map size,
+                /* If the gap is smaller than the map size,
                  * shift the map by 'gap' bits and update further.
                  */
                 bitmap_shift_right(map->tsn_map, map->tsn_map, gap, map->len);
diff --git a/net/wimax/Kconfig b/net/wimax/Kconfig
new file mode 100644
index 000000000000..0bdbb6928205
--- /dev/null
+++ b/net/wimax/Kconfig
@@ -0,0 +1,38 @@
+#
+# WiMAX LAN device configuration
+#
+
+menuconfig WIMAX
+        tristate "WiMAX Wireless Broadband support"
+        help
+
+          Select to configure support for devices that provide
+          wireless broadband connectivity using the WiMAX protocol
+          (IEEE 802.16).
+
+          Please note that most of these devices require signing up
+          for a service plan with a provider.
+
+          The different WiMAX drivers can be enabled in the menu entry
+
+          Device Drivers > Network device support > WiMAX Wireless
+          Broadband devices
+
+          If unsure, it is safe to select M (module).
+
+config WIMAX_DEBUG_LEVEL
+        int "WiMAX debug level"
+        depends on WIMAX
+        default 8
+        help
+
+          Select the maximum debug verbosity level to be compiled into
+          the WiMAX stack code.
+
+          By default, debug messages are disabled at runtime and can
+          be selectively enabled for different parts of the code using
+          the sysfs debug-levels file.
+
+          If set at zero, this will compile out all the debug code.
+
+          It is recommended that it is left at 8.
diff --git a/net/wimax/Makefile b/net/wimax/Makefile
new file mode 100644
index 000000000000..5b80b941c2c9
--- /dev/null
+++ b/net/wimax/Makefile
@@ -0,0 +1,13 @@
+
+obj-$(CONFIG_WIMAX)             += wimax.o
+
+wimax-y :=              \
+        id-table.o      \
+        op-msg.o        \
+        op-reset.o      \
+        op-rfkill.o     \
+        stack.o
+
+wimax-$(CONFIG_DEBUG_FS) += debugfs.o
+
+
diff --git a/net/wimax/debug-levels.h b/net/wimax/debug-levels.h
new file mode 100644
index 000000000000..1c29123a3aa9
--- /dev/null
+++ b/net/wimax/debug-levels.h
@@ -0,0 +1,42 @@
+/*
+ * Linux WiMAX Stack
+ * Debug levels control file for the wimax module
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __debug_levels__h__
+#define __debug_levels__h__
+
+/* Maximum compile and run time debug level for all submodules */
+#define D_MODULENAME wimax
+#define D_MASTER CONFIG_WIMAX_DEBUG_LEVEL
+
+#include <linux/wimax/debug.h>
+
+/* List of all the enabled modules */
+enum d_module {
+        D_SUBMODULE_DECLARE(debugfs),
+        D_SUBMODULE_DECLARE(id_table),
+        D_SUBMODULE_DECLARE(op_msg),
+        D_SUBMODULE_DECLARE(op_reset),
+        D_SUBMODULE_DECLARE(op_rfkill),
+        D_SUBMODULE_DECLARE(stack),
+};
+
+#endif /* #ifndef __debug_levels__h__ */
diff --git a/net/wimax/debugfs.c b/net/wimax/debugfs.c
new file mode 100644
index 000000000000..87cf4430079c
--- /dev/null
+++ b/net/wimax/debugfs.c
@@ -0,0 +1,90 @@
+/*
+ * Linux WiMAX
+ * Debugfs support
+ *
+ *
+ * Copyright (C) 2005-2006 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#include <linux/debugfs.h>
+#include <linux/wimax.h>
+#include "wimax-internal.h"
+
+#define D_SUBMODULE debugfs
+#include "debug-levels.h"
+
+
+/* Debug framework control of debug levels */
+struct d_level D_LEVEL[] = {
+        D_SUBMODULE_DEFINE(debugfs),
+        D_SUBMODULE_DEFINE(id_table),
+        D_SUBMODULE_DEFINE(op_msg),
+        D_SUBMODULE_DEFINE(op_reset),
+        D_SUBMODULE_DEFINE(op_rfkill),
+        D_SUBMODULE_DEFINE(stack),
+};
+size_t D_LEVEL_SIZE = ARRAY_SIZE(D_LEVEL);
+
+#define __debugfs_register(prefix, name, parent)                        \
+do {                                                                    \
+        result = d_level_register_debugfs(prefix, name, parent);        \
+        if (result < 0)                                                 \
+                goto error;                                             \
+} while (0)
+
+
+int wimax_debugfs_add(struct wimax_dev *wimax_dev)
+{
+        int result;
+        struct net_device *net_dev = wimax_dev->net_dev;
+        struct device *dev = net_dev->dev.parent;
+        struct dentry *dentry;
+        char buf[128];
+
+        snprintf(buf, sizeof(buf), "wimax:%s", net_dev->name);
+        dentry = debugfs_create_dir(buf, NULL);
+        result = PTR_ERR(dentry);
+        if (IS_ERR(dentry)) {
+                if (result == -ENODEV)
+                        result = 0;     /* No debugfs support */
+                else
+                        dev_err(dev, "Can't create debugfs dentry: %d\n",
+                                result);
+                goto out;
+        }
+        wimax_dev->debugfs_dentry = dentry;
+        __debugfs_register("wimax_dl_", debugfs, dentry);
+        __debugfs_register("wimax_dl_", id_table, dentry);
+        __debugfs_register("wimax_dl_", op_msg, dentry);
+        __debugfs_register("wimax_dl_", op_reset, dentry);
+        __debugfs_register("wimax_dl_", op_rfkill, dentry);
+        __debugfs_register("wimax_dl_", stack, dentry);
+        result = 0;
+out:
+        return result;
+
+error:
+        debugfs_remove_recursive(wimax_dev->debugfs_dentry);
+        return result;
+}
+
+void wimax_debugfs_rm(struct wimax_dev *wimax_dev)
+{
+        debugfs_remove_recursive(wimax_dev->debugfs_dentry);
+}
+
+
diff --git a/net/wimax/id-table.c b/net/wimax/id-table.c
new file mode 100644
index 000000000000..d3b88558682c
--- /dev/null
+++ b/net/wimax/id-table.c
@@ -0,0 +1,142 @@
+/*
+ * Linux WiMAX
+ * Mappping of generic netlink family IDs to net devices
+ *
+ *
+ * Copyright (C) 2005-2006 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * We assign a single generic netlink family ID to each device (to
+ * simplify lookup).
+ *
+ * We need a way to map family ID to a wimax_dev pointer.
+ *
+ * The idea is to use a very simple lookup. Using a netlink attribute
+ * with (for example) the interface name implies a heavier search over
+ * all the network devices; seemed kind of a waste given that we know
+ * we are looking for a WiMAX device and that most systems will have
+ * just a single WiMAX adapter.
+ *
+ * We put all the WiMAX devices in the system in a linked list and
+ * match the generic link family ID against the list.
+ *
+ * By using a linked list, the case of a single adapter in the system
+ * becomes (almost) no overhead, while still working for many more. If
+ * it ever goes beyond two, I'll be surprised.
+ */
+#include <linux/device.h>
+#include <net/genetlink.h>
+#include <linux/netdevice.h>
+#include <linux/list.h>
+#include <linux/wimax.h>
+#include "wimax-internal.h"
+
+
+#define D_SUBMODULE id_table
+#include "debug-levels.h"
+
+
+static DEFINE_SPINLOCK(wimax_id_table_lock);
+static struct list_head wimax_id_table = LIST_HEAD_INIT(wimax_id_table);
+
+
+/*
+ * wimax_id_table_add - add a gennetlink familiy ID / wimax_dev mapping
+ *
+ * @wimax_dev: WiMAX device descriptor to associate to the Generic
+ *     Netlink family ID.
+ *
+ * Look for an empty spot in the ID table; if none found, double the
+ * table's size and get the first spot.
+ */
+void wimax_id_table_add(struct wimax_dev *wimax_dev)
+{
+        d_fnstart(3, NULL, "(wimax_dev %p)\n", wimax_dev);
+        spin_lock(&wimax_id_table_lock);
+        list_add(&wimax_dev->id_table_node, &wimax_id_table);
+        spin_unlock(&wimax_id_table_lock);
+        d_fnend(3, NULL, "(wimax_dev %p)\n", wimax_dev);
+}
+
+
+/*
+ * wimax_get_netdev_by_info - lookup a wimax_dev from the gennetlink info
+ *
+ * The generic netlink family ID has been filled out in the
+ * nlmsghdr->nlmsg_type field, so we pull it from there, look it up in
+ * the mapping table and reference the wimax_dev.
+ *
+ * When done, the reference should be dropped with
+ * 'dev_put(wimax_dev->net_dev)'.
+ */
+struct wimax_dev *wimax_dev_get_by_genl_info(
+        struct genl_info *info, int ifindex)
+{
+        struct wimax_dev *wimax_dev = NULL;
+
+        d_fnstart(3, NULL, "(info %p ifindex %d)\n", info, ifindex);
+        spin_lock(&wimax_id_table_lock);
+        list_for_each_entry(wimax_dev, &wimax_id_table, id_table_node) {
+                if (wimax_dev->net_dev->ifindex == ifindex) {
+                        dev_hold(wimax_dev->net_dev);
+                        break;
+                }
+        }
+        if (wimax_dev == NULL)
+                d_printf(1, NULL, "wimax: no devices found with ifindex %d\n",
+                         ifindex);
+        spin_unlock(&wimax_id_table_lock);
+        d_fnend(3, NULL, "(info %p ifindex %d) = %p\n",
+                info, ifindex, wimax_dev);
+        return wimax_dev;
+}
+
+
+/*
+ * wimax_id_table_rm - Remove a gennetlink familiy ID / wimax_dev mapping
+ *
+ * @id: family ID to remove from the table
+ */
+void wimax_id_table_rm(struct wimax_dev *wimax_dev)
+{
+        spin_lock(&wimax_id_table_lock);
+        list_del_init(&wimax_dev->id_table_node);
+        spin_unlock(&wimax_id_table_lock);
+}
+
+
+/*
+ * Release the gennetlink family id / mapping table
+ *
+ * On debug, verify that the table is empty upon removal.
+ */
+void wimax_id_table_release(void)
+{
+#ifndef CONFIG_BUG
+        return;
+#endif
+        struct wimax_dev *wimax_dev;
+
+        spin_lock(&wimax_id_table_lock);
+        list_for_each_entry(wimax_dev, &wimax_id_table, id_table_node) {
+                printk(KERN_ERR "BUG: %s wimax_dev %p ifindex %d not cleared\n",
+                       __func__, wimax_dev, wimax_dev->net_dev->ifindex);
+                WARN_ON(1);
+        }
+        spin_unlock(&wimax_id_table_lock);
+}
diff --git a/net/wimax/op-msg.c b/net/wimax/op-msg.c
new file mode 100644
index 000000000000..cb3b4ad53683
--- /dev/null
+++ b/net/wimax/op-msg.c
@@ -0,0 +1,421 @@
+/*
+ * Linux WiMAX
+ * Generic messaging interface between userspace and driver/device
+ *
+ *
+ * Copyright (C) 2007-2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This implements a direct communication channel between user space and
+ * the driver/device, by which free form messages can be sent back and
+ * forth.
+ *
+ * This is intended for device-specific features, vendor quirks, etc.
+ *
+ * See include/net/wimax.h
+ *
+ * GENERIC NETLINK ENCODING AND CAPACITY
+ *
+ * A destination "pipe name" is added to each message; it is up to the
+ * drivers to assign or use those names (if using them at all).
+ *
+ * Messages are encoded as a binary netlink attribute using nla_put()
+ * using type NLA_UNSPEC (as some versions of libnl still in
+ * deployment don't yet understand NLA_BINARY).
+ *
+ * The maximum capacity of this transport is PAGESIZE per message (so
+ * the actual payload will be bit smaller depending on the
+ * netlink/generic netlink attributes and headers).
+ *
+ * RECEPTION OF MESSAGES
+ *
+ * When a message is received from user space, it is passed verbatim
+ * to the driver calling wimax_dev->op_msg_from_user(). The return
+ * value from this function is passed back to user space as an ack
+ * over the generic netlink protocol.
+ *
+ * The stack doesn't do any processing or interpretation of these
+ * messages.
+ *
+ * SENDING MESSAGES
+ *
+ * Messages can be sent with wimax_msg().
+ *
+ * If the message delivery needs to happen on a different context to
+ * that of its creation, wimax_msg_alloc() can be used to get a
+ * pointer to the message that can be delivered later on with
+ * wimax_msg_send().
+ *
+ * ROADMAP
+ *
+ * wimax_gnl_doit_msg_from_user()    Process a message from user space
+ *   wimax_dev_get_by_genl_info()
+ *   wimax_dev->op_msg_from_user()   Delivery of message to the driver
+ *
+ * wimax_msg()                       Send a message to user space
+ *   wimax_msg_alloc()
+ *   wimax_msg_send()
+ */
+#include <linux/device.h>
+#include <net/genetlink.h>
+#include <linux/netdevice.h>
+#include <linux/wimax.h>
+#include <linux/security.h>
+#include "wimax-internal.h"
+
+
+#define D_SUBMODULE op_msg
+#include "debug-levels.h"
+
+
+/**
+ * wimax_msg_alloc - Create a new skb for sending a message to userspace
+ *
+ * @wimax_dev: WiMAX device descriptor
+ * @pipe_name: "named pipe" the message will be sent to
+ * @msg: pointer to the message data to send
+ * @size: size of the message to send (in bytes), including the header.
+ * @gfp_flags: flags for memory allocation.
+ *
+ * Returns: %0 if ok, negative errno code on error
+ *
+ * Description:
+ *
+ * Allocates an skb that will contain the message to send to user
+ * space over the messaging pipe and initializes it, copying the
+ * payload.
+ *
+ * Once this call is done, you can deliver it with
+ * wimax_msg_send().
+ *
+ * IMPORTANT:
+ *
+ * Don't use skb_push()/skb_pull()/skb_reserve() on the skb, as
+ * wimax_msg_send() depends on skb->data being placed at the
+ * beginning of the user message.
+ */
+struct sk_buff *wimax_msg_alloc(struct wimax_dev *wimax_dev,
+                                const char *pipe_name,
+                                const void *msg, size_t size,
+                                gfp_t gfp_flags)
+{
+        int result;
+        struct device *dev = wimax_dev->net_dev->dev.parent;
+        size_t msg_size;
+        void *genl_msg;
+        struct sk_buff *skb;
+
+        msg_size = nla_total_size(size)
+                + nla_total_size(sizeof(u32))
+                + (pipe_name ? nla_total_size(strlen(pipe_name)) : 0);
+        result = -ENOMEM;
+        skb = genlmsg_new(msg_size, gfp_flags);
+        if (skb == NULL)
+                goto error_new;
+        genl_msg = genlmsg_put(skb, 0, 0, &wimax_gnl_family,
+                               0, WIMAX_GNL_OP_MSG_TO_USER);
+        if (genl_msg == NULL) {
+                dev_err(dev, "no memory to create generic netlink message\n");
+                goto error_genlmsg_put;
+        }
+        result = nla_put_u32(skb, WIMAX_GNL_MSG_IFIDX,
+                             wimax_dev->net_dev->ifindex);
+        if (result < 0) {
+                dev_err(dev, "no memory to add ifindex attribute\n");
+                goto error_nla_put;
+        }
+        if (pipe_name) {
+                result = nla_put_string(skb, WIMAX_GNL_MSG_PIPE_NAME,
+                                        pipe_name);
+                if (result < 0) {
+                        dev_err(dev, "no memory to add pipe_name attribute\n");
+                        goto error_nla_put;
+                }
+        }
+        result = nla_put(skb, WIMAX_GNL_MSG_DATA, size, msg);
+        if (result < 0) {
+                dev_err(dev, "no memory to add payload in attribute\n");
+                goto error_nla_put;
+        }
+        genlmsg_end(skb, genl_msg);
+        return skb;
+
+error_nla_put:
+error_genlmsg_put:
+error_new:
+        nlmsg_free(skb);
+        return ERR_PTR(result);
+
+}
+EXPORT_SYMBOL_GPL(wimax_msg_alloc);
+
+
+/**
+ * wimax_msg_data_len - Return a pointer and size of a message's payload
+ *
+ * @msg: Pointer to a message created with wimax_msg_alloc()
+ * @size: Pointer to where to store the message's size
+ *
+ * Returns the pointer to the message data.
+ */
+const void *wimax_msg_data_len(struct sk_buff *msg, size_t *size)
+{
+        struct nlmsghdr *nlh = (void *) msg->head;
+        struct nlattr *nla;
+
+        nla = nlmsg_find_attr(nlh, sizeof(struct genlmsghdr),
+                              WIMAX_GNL_MSG_DATA);
+        if (nla == NULL) {
+                printk(KERN_ERR "Cannot find attribute WIMAX_GNL_MSG_DATA\n");
+                return NULL;
+        }
+        *size = nla_len(nla);
+        return nla_data(nla);
+}
+EXPORT_SYMBOL_GPL(wimax_msg_data_len);
+
+
+/**
+ * wimax_msg_data - Return a pointer to a message's payload
+ *
+ * @msg: Pointer to a message created with wimax_msg_alloc()
+ */
+const void *wimax_msg_data(struct sk_buff *msg)
+{
+        struct nlmsghdr *nlh = (void *) msg->head;
+        struct nlattr *nla;
+
+        nla = nlmsg_find_attr(nlh, sizeof(struct genlmsghdr),
+                              WIMAX_GNL_MSG_DATA);
+        if (nla == NULL) {
+                printk(KERN_ERR "Cannot find attribute WIMAX_GNL_MSG_DATA\n");
+                return NULL;
+        }
+        return nla_data(nla);
+}
+EXPORT_SYMBOL_GPL(wimax_msg_data);
+
+
+/**
+ * wimax_msg_len - Return a message's payload length
+ *
+ * @msg: Pointer to a message created with wimax_msg_alloc()
+ */
+ssize_t wimax_msg_len(struct sk_buff *msg)
+{
+        struct nlmsghdr *nlh = (void *) msg->head;
+        struct nlattr *nla;
+
+        nla = nlmsg_find_attr(nlh, sizeof(struct genlmsghdr),
+                              WIMAX_GNL_MSG_DATA);
+        if (nla == NULL) {
+                printk(KERN_ERR "Cannot find attribute WIMAX_GNL_MSG_DATA\n");
+                return -EINVAL;
+        }
+        return nla_len(nla);
+}
+EXPORT_SYMBOL_GPL(wimax_msg_len);
+
+
+/**
+ * wimax_msg_send - Send a pre-allocated message to user space
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * @skb: &struct sk_buff returned by wimax_msg_alloc(). Note the
+ *     ownership of @skb is transferred to this function.
+ *
+ * Returns: 0 if ok, < 0 errno code on error
+ *
+ * Description:
+ *
+ * Sends a free-form message that was preallocated with
+ * wimax_msg_alloc() and filled up.
+ *
+ * Assumes that once you pass an skb to this function for sending, it
+ * owns it and will release it when done (on success).
+ *
+ * IMPORTANT:
+ *
+ * Don't use skb_push()/skb_pull()/skb_reserve() on the skb, as
+ * wimax_msg_send() depends on skb->data being placed at the
+ * beginning of the user message.
+ */
+int wimax_msg_send(struct wimax_dev *wimax_dev, struct sk_buff *skb)
+{
+        int result;
+        struct device *dev = wimax_dev->net_dev->dev.parent;
+        void *msg = skb->data;
+        size_t size = skb->len;
+        might_sleep();
+
+        d_printf(1, dev, "CTX: wimax msg, %zu bytes\n", size);
+        d_dump(2, dev, msg, size);
+        result = genlmsg_multicast(skb, 0, wimax_gnl_mcg.id, GFP_KERNEL);
+        d_printf(1, dev, "CTX: genl multicast result %d\n", result);
+        if (result == -ESRCH)   /* Nobody connected, ignore it */
+                result = 0;     /* btw, the skb is freed already */
+        return result;
+}
+EXPORT_SYMBOL_GPL(wimax_msg_send);
+
+
+/**
+ * wimax_msg - Send a message to user space
+ *
+ * @wimax_dev: WiMAX device descriptor (properly referenced)
+ * @pipe_name: "named pipe" the message will be sent to
+ * @buf: pointer to the message to send.
+ * @size: size of the buffer pointed to by @buf (in bytes).
+ * @gfp_flags: flags for memory allocation.
+ *
+ * Returns: %0 if ok, negative errno code on error.
+ *
+ * Description:
+ *
+ * Sends a free-form message to user space on the device @wimax_dev.
+ *
+ * NOTES:
+ *
+ * Once the @skb is given to this function, who will own it and will
+ * release it when done (unless it returns error).
+ */
+int wimax_msg(struct wimax_dev *wimax_dev, const char *pipe_name,
+              const void *buf, size_t size, gfp_t gfp_flags)
+{
+        int result = -ENOMEM;
+        struct sk_buff *skb;
+
+        skb = wimax_msg_alloc(wimax_dev, pipe_name, buf, size, gfp_flags);
+        if (skb == NULL)
+                goto error_msg_new;
+        result = wimax_msg_send(wimax_dev, skb);
+error_msg_new:
+        return result;
+}
+EXPORT_SYMBOL_GPL(wimax_msg);
+
+
+static const
+struct nla_policy wimax_gnl_msg_policy[WIMAX_GNL_ATTR_MAX + 1] = {
+        [WIMAX_GNL_MSG_IFIDX] = {
+                .type = NLA_U32,
+        },
+        [WIMAX_GNL_MSG_DATA] = {
+                .type = NLA_UNSPEC,     /* libnl doesn't grok BINARY yet */
+        },
+};
+
+
+/*
+ * Relays a message from user space to the driver
+ *
+ * The skb is passed to the driver-specific function with the netlink
+ * and generic netlink headers already stripped.
+ *
+ * This call will block while handling/relaying the message.
+ */
+static
+int wimax_gnl_doit_msg_from_user(struct sk_buff *skb, struct genl_info *info)
+{
+        int result, ifindex;
+        struct wimax_dev *wimax_dev;
+        struct device *dev;
+        struct nlmsghdr *nlh = info->nlhdr;
+        char *pipe_name;
+        void *msg_buf;
+        size_t msg_len;
+
+        might_sleep();
+        d_fnstart(3, NULL, "(skb %p info %p)\n", skb, info);
+        result = -ENODEV;
+        if (info->attrs[WIMAX_GNL_MSG_IFIDX] == NULL) {
+                printk(KERN_ERR "WIMAX_GNL_MSG_FROM_USER: can't find IFIDX "
+                       "attribute\n");
+                goto error_no_wimax_dev;
+        }
+        ifindex = nla_get_u32(info->attrs[WIMAX_GNL_MSG_IFIDX]);
+        wimax_dev = wimax_dev_get_by_genl_info(info, ifindex);
+        if (wimax_dev == NULL)
+                goto error_no_wimax_dev;
+        dev = wimax_dev_to_dev(wimax_dev);
+
+        /* Unpack arguments */
+        result = -EINVAL;
+        if (info->attrs[WIMAX_GNL_MSG_DATA] == NULL) {
+                dev_err(dev, "WIMAX_GNL_MSG_FROM_USER: can't find MSG_DATA "
+                        "attribute\n");
+                goto error_no_data;
+        }
+        msg_buf = nla_data(info->attrs[WIMAX_GNL_MSG_DATA]);
+        msg_len = nla_len(info->attrs[WIMAX_GNL_MSG_DATA]);
+
+        if (info->attrs[WIMAX_GNL_MSG_PIPE_NAME] == NULL)
+                pipe_name = NULL;
+        else {
+                struct nlattr *attr = info->attrs[WIMAX_GNL_MSG_PIPE_NAME];
+                size_t attr_len = nla_len(attr);
+                /* libnl-1.1 does not yet support NLA_NUL_STRING */
+                result = -ENOMEM;
+                pipe_name = kstrndup(nla_data(attr), attr_len + 1, GFP_KERNEL);
+                if (pipe_name == NULL)
+                        goto error_alloc;
+                pipe_name[attr_len] = 0;
+        }
+        mutex_lock(&wimax_dev->mutex);
+        result = wimax_dev_is_ready(wimax_dev);
+        if (result < 0)
+                goto error_not_ready;
+        result = -ENOSYS;
+        if (wimax_dev->op_msg_from_user == NULL)
+                goto error_noop;
+
+        d_printf(1, dev,
+                 "CRX: nlmsghdr len %u type %u flags 0x%04x seq 0x%x pid %u\n",
+                 nlh->nlmsg_len, nlh->nlmsg_type, nlh->nlmsg_flags,
+                 nlh->nlmsg_seq, nlh->nlmsg_pid);
+        d_printf(1, dev, "CRX: wimax message %zu bytes\n", msg_len);
+        d_dump(2, dev, msg_buf, msg_len);
+
+        result = wimax_dev->op_msg_from_user(wimax_dev, pipe_name,
+                                             msg_buf, msg_len, info);
+error_noop:
+error_not_ready:
+        mutex_unlock(&wimax_dev->mutex);
+error_alloc:
+        kfree(pipe_name);
+error_no_data:
+        dev_put(wimax_dev->net_dev);
+error_no_wimax_dev:
+        d_fnend(3, NULL, "(skb %p info %p) = %d\n", skb, info, result);
+        return result;
+}
+
+
+/*
+ * Generic Netlink glue
+ */
+
+struct genl_ops wimax_gnl_msg_from_user = {
+        .cmd = WIMAX_GNL_OP_MSG_FROM_USER,
+        .flags = GENL_ADMIN_PERM,
+        .policy = wimax_gnl_msg_policy,
+        .doit = wimax_gnl_doit_msg_from_user,
+        .dumpit = NULL,
+};
+
diff --git a/net/wimax/op-reset.c b/net/wimax/op-reset.c
new file mode 100644
index 000000000000..ca269178c4d4
--- /dev/null
+++ b/net/wimax/op-reset.c
@@ -0,0 +1,143 @@
+/*
+ * Linux WiMAX
+ * Implement and export a method for resetting a WiMAX device
+ *
+ *
+ * Copyright (C) 2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This implements a simple synchronous call to reset a WiMAX device.
+ *
+ * Resets aim at being warm, keeping the device handles active;
+ * however, when that fails, it falls back to a cold reset (that will
+ * disconnect and reconnect the device).
+ */
+
+#include <net/wimax.h>
+#include <net/genetlink.h>
+#include <linux/wimax.h>
+#include <linux/security.h>
+#include "wimax-internal.h"
+
+#define D_SUBMODULE op_reset
+#include "debug-levels.h"
+
+
+/**
+ * wimax_reset - Reset a WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * Returns:
+ *
+ * %0 if ok and a warm reset was done (the device still exists in
+ * the system).
+ *
+ * -%ENODEV if a cold/bus reset had to be done (device has
+ * disconnected and reconnected, so current handle is not valid
+ * any more).
+ *
+ * -%EINVAL if the device is not even registered.
+ *
+ * Any other negative error code shall be considered as
+ * non-recoverable.
+ *
+ * Description:
+ *
+ * Called when wanting to reset the device for any reason. Device is
+ * taken back to power on status.
+ *
+ * This call blocks; on succesful return, the device has completed the
+ * reset process and is ready to operate.
+ */
+int wimax_reset(struct wimax_dev *wimax_dev)
+{
+        int result = -EINVAL;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_st state;
+
+        might_sleep();
+        d_fnstart(3, dev, "(wimax_dev %p)\n", wimax_dev);
+        mutex_lock(&wimax_dev->mutex);
+        dev_hold(wimax_dev->net_dev);
+        state = wimax_dev->state;
+        mutex_unlock(&wimax_dev->mutex);
+
+        if (state >= WIMAX_ST_DOWN) {
+                mutex_lock(&wimax_dev->mutex_reset);
+                result = wimax_dev->op_reset(wimax_dev);
+                mutex_unlock(&wimax_dev->mutex_reset);
+        }
+        dev_put(wimax_dev->net_dev);
+
+        d_fnend(3, dev, "(wimax_dev %p) = %d\n", wimax_dev, result);
+        return result;
+}
+EXPORT_SYMBOL(wimax_reset);
+
+
+static const
+struct nla_policy wimax_gnl_reset_policy[WIMAX_GNL_ATTR_MAX + 1] = {
+        [WIMAX_GNL_RESET_IFIDX] = {
+                .type = NLA_U32,
+        },
+};
+
+
+/*
+ * Exporting to user space over generic netlink
+ *
+ * Parse the reset command from user space, return error code.
+ *
+ * No attributes.
+ */
+static
+int wimax_gnl_doit_reset(struct sk_buff *skb, struct genl_info *info)
+{
+        int result, ifindex;
+        struct wimax_dev *wimax_dev;
+        struct device *dev;
+
+        d_fnstart(3, NULL, "(skb %p info %p)\n", skb, info);
+        result = -ENODEV;
+        if (info->attrs[WIMAX_GNL_RESET_IFIDX] == NULL) {
+                printk(KERN_ERR "WIMAX_GNL_OP_RFKILL: can't find IFIDX "
+                        "attribute\n");
+                goto error_no_wimax_dev;
+        }
+        ifindex = nla_get_u32(info->attrs[WIMAX_GNL_RESET_IFIDX]);
+        wimax_dev = wimax_dev_get_by_genl_info(info, ifindex);
+        if (wimax_dev == NULL)
+                goto error_no_wimax_dev;
+        dev = wimax_dev_to_dev(wimax_dev);
+        /* Execute the operation and send the result back to user space */
+        result = wimax_reset(wimax_dev);
+        dev_put(wimax_dev->net_dev);
+error_no_wimax_dev:
+        d_fnend(3, NULL, "(skb %p info %p) = %d\n", skb, info, result);
+        return result;
+}
+
+
+struct genl_ops wimax_gnl_reset = {
+        .cmd = WIMAX_GNL_OP_RESET,
+        .flags = GENL_ADMIN_PERM,
+        .policy = wimax_gnl_reset_policy,
+        .doit = wimax_gnl_doit_reset,
+        .dumpit = NULL,
+};
diff --git a/net/wimax/op-rfkill.c b/net/wimax/op-rfkill.c
new file mode 100644
index 000000000000..8745bac173f1
--- /dev/null
+++ b/net/wimax/op-rfkill.c
@@ -0,0 +1,532 @@
+/*
+ * Linux WiMAX
+ * RF-kill framework integration
+ *
+ *
+ * Copyright (C) 2008 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This integrates into the Linux Kernel rfkill susbystem so that the
+ * drivers just have to do the bare minimal work, which is providing a
+ * method to set the software RF-Kill switch and to report changes in
+ * the software and hardware switch status.
+ *
+ * A non-polled generic rfkill device is embedded into the WiMAX
+ * subsystem's representation of a device.
+ *
+ * FIXME: Need polled support? use a timer or add the implementation
+ *     to the stack.
+ *
+ * All device drivers have to do is after wimax_dev_init(), call
+ * wimax_report_rfkill_hw() and wimax_report_rfkill_sw() to update
+ * initial state and then every time it changes. See wimax.h:struct
+ * wimax_dev for more information.
+ *
+ * ROADMAP
+ *
+ * wimax_gnl_doit_rfkill()      User space calling wimax_rfkill()
+ *   wimax_rfkill()             Kernel calling wimax_rfkill()
+ *     __wimax_rf_toggle_radio()
+ *
+ * wimax_rfkill_toggle_radio()  RF-Kill subsytem calling
+ *   __wimax_rf_toggle_radio()
+ *
+ * __wimax_rf_toggle_radio()
+ *   wimax_dev->op_rfkill_sw_toggle() Driver backend
+ *   __wimax_state_change()
+ *
+ * wimax_report_rfkill_sw()     Driver reports state change
+ *   __wimax_state_change()
+ *
+ * wimax_report_rfkill_hw()     Driver reports state change
+ *   __wimax_state_change()
+ *
+ * wimax_rfkill_add()           Initialize/shutdown rfkill support
+ * wimax_rfkill_rm()            [called by wimax_dev_add/rm()]
+ */
+
+#include <net/wimax.h>
+#include <net/genetlink.h>
+#include <linux/wimax.h>
+#include <linux/security.h>
+#include <linux/rfkill.h>
+#include <linux/input.h>
+#include "wimax-internal.h"
+
+#define D_SUBMODULE op_rfkill
+#include "debug-levels.h"
+
+#ifdef CONFIG_RFKILL
+
+
+/**
+ * wimax_report_rfkill_hw - Reports changes in the hardware RF switch
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * @state: New state of the RF Kill switch. %WIMAX_RF_ON radio on,
+ *     %WIMAX_RF_OFF radio off.
+ *
+ * When the device detects a change in the state of thehardware RF
+ * switch, it must call this function to let the WiMAX kernel stack
+ * know that the state has changed so it can be properly propagated.
+ *
+ * The WiMAX stack caches the state (the driver doesn't need to). As
+ * well, as the change is propagated it will come back as a request to
+ * change the software state to mirror the hardware state.
+ *
+ * If the device doesn't have a hardware kill switch, just report
+ * it on initialization as always on (%WIMAX_RF_ON, radio on).
+ */
+void wimax_report_rfkill_hw(struct wimax_dev *wimax_dev,
+                            enum wimax_rf_state state)
+{
+        int result;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_st wimax_state;
+        enum rfkill_state rfkill_state;
+
+        d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state);
+        BUG_ON(state == WIMAX_RF_QUERY);
+        BUG_ON(state != WIMAX_RF_ON && state != WIMAX_RF_OFF);
+
+        mutex_lock(&wimax_dev->mutex);
+        result = wimax_dev_is_ready(wimax_dev);
+        if (result < 0)
+                goto error_not_ready;
+
+        if (state != wimax_dev->rf_hw) {
+                wimax_dev->rf_hw = state;
+                rfkill_state = state == WIMAX_RF_ON ?
+                        RFKILL_STATE_OFF : RFKILL_STATE_ON;
+                if (wimax_dev->rf_hw == WIMAX_RF_ON
+                    && wimax_dev->rf_sw == WIMAX_RF_ON)
+                        wimax_state = WIMAX_ST_READY;
+                else
+                        wimax_state = WIMAX_ST_RADIO_OFF;
+                __wimax_state_change(wimax_dev, wimax_state);
+                input_report_key(wimax_dev->rfkill_input, KEY_WIMAX,
+                                 rfkill_state);
+        }
+error_not_ready:
+        mutex_unlock(&wimax_dev->mutex);
+        d_fnend(3, dev, "(wimax_dev %p state %u) = void [%d]\n",
+                wimax_dev, state, result);
+}
+EXPORT_SYMBOL_GPL(wimax_report_rfkill_hw);
+
+
+/**
+ * wimax_report_rfkill_sw - Reports changes in the software RF switch
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * @state: New state of the RF kill switch. %WIMAX_RF_ON radio on,
+ *     %WIMAX_RF_OFF radio off.
+ *
+ * Reports changes in the software RF switch state to the the WiMAX
+ * stack.
+ *
+ * The main use is during initialization, so the driver can query the
+ * device for its current software radio kill switch state and feed it
+ * to the system.
+ *
+ * On the side, the device does not change the software state by
+ * itself. In practice, this can happen, as the device might decide to
+ * switch (in software) the radio off for different reasons.
+ */
+void wimax_report_rfkill_sw(struct wimax_dev *wimax_dev,
+                            enum wimax_rf_state state)
+{
+        int result;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_st wimax_state;
+
+        d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state);
+        BUG_ON(state == WIMAX_RF_QUERY);
+        BUG_ON(state != WIMAX_RF_ON && state != WIMAX_RF_OFF);
+
+        mutex_lock(&wimax_dev->mutex);
+        result = wimax_dev_is_ready(wimax_dev);
+        if (result < 0)
+                goto error_not_ready;
+
+        if (state != wimax_dev->rf_sw) {
+                wimax_dev->rf_sw = state;
+                if (wimax_dev->rf_hw == WIMAX_RF_ON
+                    && wimax_dev->rf_sw == WIMAX_RF_ON)
+                        wimax_state = WIMAX_ST_READY;
+                else
+                        wimax_state = WIMAX_ST_RADIO_OFF;
+                __wimax_state_change(wimax_dev, wimax_state);
+        }
+error_not_ready:
+        mutex_unlock(&wimax_dev->mutex);
+        d_fnend(3, dev, "(wimax_dev %p state %u) = void [%d]\n",
+                wimax_dev, state, result);
+}
+EXPORT_SYMBOL_GPL(wimax_report_rfkill_sw);
+
+
+/*
+ * Callback for the RF Kill toggle operation
+ *
+ * This function is called by:
+ *
+ * - The rfkill subsystem when the RF-Kill key is pressed in the
+ *   hardware and the driver notifies through
+ *   wimax_report_rfkill_hw(). The rfkill subsystem ends up calling back
+ *   here so the software RF Kill switch state is changed to reflect
+ *   the hardware switch state.
+ *
+ * - When the user sets the state through sysfs' rfkill/state file
+ *
+ * - When the user calls wimax_rfkill().
+ *
+ * This call blocks!
+ *
+ * WARNING! When we call rfkill_unregister(), this will be called with
+ * state 0!
+ *
+ * WARNING: wimax_dev must be locked
+ */
+static
+int __wimax_rf_toggle_radio(struct wimax_dev *wimax_dev,
+                            enum wimax_rf_state state)
+{
+        int result = 0;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_st wimax_state;
+
+        might_sleep();
+        d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state);
+        if (wimax_dev->rf_sw == state)
+                goto out_no_change;
+        if (wimax_dev->op_rfkill_sw_toggle != NULL)
+                result = wimax_dev->op_rfkill_sw_toggle(wimax_dev, state);
+        else if (state == WIMAX_RF_OFF) /* No op? can't turn off */
+                result = -ENXIO;
+        else                            /* No op? can turn on */
+                result = 0;             /* should never happen tho */
+        if (result >= 0) {
+                result = 0;
+                wimax_dev->rf_sw = state;
+                wimax_state = state == WIMAX_RF_ON ?
+                        WIMAX_ST_READY : WIMAX_ST_RADIO_OFF;
+                __wimax_state_change(wimax_dev, wimax_state);
+        }
+out_no_change:
+        d_fnend(3, dev, "(wimax_dev %p state %u) = %d\n",
+                wimax_dev, state, result);
+        return result;
+}
+
+
+/*
+ * Translate from rfkill state to wimax state
+ *
+ * NOTE: Special state handling rules here
+ *
+ *     Just pretend the call didn't happen if we are in a state where
+ *     we know for sure it cannot be handled (WIMAX_ST_DOWN or
+ *     __WIMAX_ST_QUIESCING). rfkill() needs it to register and
+ *     unregister, as it will run this path.
+ *
+ * NOTE: This call will block until the operation is completed.
+ */
+static
+int wimax_rfkill_toggle_radio(void *data, enum rfkill_state state)
+{
+        int result;
+        struct wimax_dev *wimax_dev = data;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_rf_state rf_state;
+
+        d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state);
+        switch (state) {
+        case RFKILL_STATE_ON:
+                rf_state = WIMAX_RF_OFF;
+                break;
+        case RFKILL_STATE_OFF:
+                rf_state = WIMAX_RF_ON;
+                break;
+        default:
+                BUG();
+        }
+        mutex_lock(&wimax_dev->mutex);
+        if (wimax_dev->state <= __WIMAX_ST_QUIESCING)
+                result = 0;     /* just pretend it didn't happen */
+        else
+                result = __wimax_rf_toggle_radio(wimax_dev, rf_state);
+        mutex_unlock(&wimax_dev->mutex);
+        d_fnend(3, dev, "(wimax_dev %p state %u) = %d\n",
+                wimax_dev, state, result);
+        return result;
+}
+
+
+/**
+ * wimax_rfkill - Set the software RF switch state for a WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * @state: New RF state.
+ *
+ * Returns:
+ *
+ * >= 0 toggle state if ok, < 0 errno code on error. The toggle state
+ * is returned as a bitmap, bit 0 being the hardware RF state, bit 1
+ * the software RF state.
+ *
+ * 0 means disabled (%WIMAX_RF_ON, radio on), 1 means enabled radio
+ * off (%WIMAX_RF_OFF).
+ *
+ * Description:
+ *
+ * Called by the user when he wants to request the WiMAX radio to be
+ * switched on (%WIMAX_RF_ON) or off (%WIMAX_RF_OFF). With
+ * %WIMAX_RF_QUERY, just the current state is returned.
+ *
+ * NOTE:
+ *
+ * This call will block until the operation is complete.
+ */
+int wimax_rfkill(struct wimax_dev *wimax_dev, enum wimax_rf_state state)
+{
+        int result;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+
+        d_fnstart(3, dev, "(wimax_dev %p state %u)\n", wimax_dev, state);
+        mutex_lock(&wimax_dev->mutex);
+        result = wimax_dev_is_ready(wimax_dev);
+        if (result < 0)
+                goto error_not_ready;
+        switch (state) {
+        case WIMAX_RF_ON:
+        case WIMAX_RF_OFF:
+                result = __wimax_rf_toggle_radio(wimax_dev, state);
+                if (result < 0)
+                        goto error;
+                break;
+        case WIMAX_RF_QUERY:
+                break;
+        default:
+                result = -EINVAL;
+                goto error;
+        }
+        result = wimax_dev->rf_sw << 1 | wimax_dev->rf_hw;
+error:
+error_not_ready:
+        mutex_unlock(&wimax_dev->mutex);
+        d_fnend(3, dev, "(wimax_dev %p state %u) = %d\n",
+                wimax_dev, state, result);
+        return result;
+}
+EXPORT_SYMBOL(wimax_rfkill);
+
+
+/*
+ * Register a new WiMAX device's RF Kill support
+ *
+ * WARNING: wimax_dev->mutex must be unlocked
+ */
+int wimax_rfkill_add(struct wimax_dev *wimax_dev)
+{
+        int result;
+        struct rfkill *rfkill;
+        struct input_dev *input_dev;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+
+        d_fnstart(3, dev, "(wimax_dev %p)\n", wimax_dev);
+        /* Initialize RF Kill */
+        result = -ENOMEM;
+        rfkill = rfkill_allocate(dev, RFKILL_TYPE_WIMAX);
+        if (rfkill == NULL)
+                goto error_rfkill_allocate;
+        wimax_dev->rfkill = rfkill;
+
+        rfkill->name = wimax_dev->name;
+        rfkill->state = RFKILL_STATE_OFF;
+        rfkill->data = wimax_dev;
+        rfkill->toggle_radio = wimax_rfkill_toggle_radio;
+        rfkill->user_claim_unsupported = 1;
+
+        /* Initialize the input device for the hw key */
+        input_dev = input_allocate_device();
+        if (input_dev == NULL)
+                goto error_input_allocate;
+        wimax_dev->rfkill_input = input_dev;
+        d_printf(1, dev, "rfkill %p input %p\n", rfkill, input_dev);
+
+        input_dev->name = wimax_dev->name;
+        /* FIXME: get a real device bus ID and stuff? do we care? */
+        input_dev->id.bustype = BUS_HOST;
+        input_dev->id.vendor = 0xffff;
+        input_dev->evbit[0] = BIT(EV_KEY);
+        set_bit(KEY_WIMAX, input_dev->keybit);
+
+        /* Register both */
+        result = input_register_device(wimax_dev->rfkill_input);
+        if (result < 0)
+                goto error_input_register;
+        result = rfkill_register(wimax_dev->rfkill);
+        if (result < 0)
+                goto error_rfkill_register;
+
+        /* If there is no SW toggle op, SW RFKill is always on */
+        if (wimax_dev->op_rfkill_sw_toggle == NULL)
+                wimax_dev->rf_sw = WIMAX_RF_ON;
+
+        d_fnend(3, dev, "(wimax_dev %p) = 0\n", wimax_dev);
+        return 0;
+
+        /* if rfkill_register() suceeds, can't use rfkill_free() any
+         * more, only rfkill_unregister() [it owns the refcount]; with
+         * the input device we have the same issue--hence the if. */
+error_rfkill_register:
+        input_unregister_device(wimax_dev->rfkill_input);
+        wimax_dev->rfkill_input = NULL;
+error_input_register:
+        if (wimax_dev->rfkill_input)
+                input_free_device(wimax_dev->rfkill_input);
+error_input_allocate:
+        rfkill_free(wimax_dev->rfkill);
+error_rfkill_allocate:
+        d_fnend(3, dev, "(wimax_dev %p) = %d\n", wimax_dev, result);
+        return result;
+}
+
+
+/*
+ * Deregister a WiMAX device's RF Kill support
+ *
+ * Ick, we can't call rfkill_free() after rfkill_unregister()...oh
+ * well.
+ *
+ * WARNING: wimax_dev->mutex must be unlocked
+ */
+void wimax_rfkill_rm(struct wimax_dev *wimax_dev)
+{
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        d_fnstart(3, dev, "(wimax_dev %p)\n", wimax_dev);
+        rfkill_unregister(wimax_dev->rfkill);   /* frees */
+        input_unregister_device(wimax_dev->rfkill_input);
+        d_fnend(3, dev, "(wimax_dev %p)\n", wimax_dev);
+}
+
+
+#else /* #ifdef CONFIG_RFKILL */
+
+void wimax_report_rfkill_hw(struct wimax_dev *wimax_dev,
+                            enum wimax_rf_state state)
+{
+}
+EXPORT_SYMBOL_GPL(wimax_report_rfkill_hw);
+
+void wimax_report_rfkill_sw(struct wimax_dev *wimax_dev,
+                            enum wimax_rf_state state)
+{
+}
+EXPORT_SYMBOL_GPL(wimax_report_rfkill_sw);
+
+int wimax_rfkill(struct wimax_dev *wimax_dev,
+                 enum wimax_rf_state state)
+{
+        return WIMAX_RF_ON << 1 | WIMAX_RF_ON;
+}
+EXPORT_SYMBOL_GPL(wimax_rfkill);
+
+int wimax_rfkill_add(struct wimax_dev *wimax_dev)
+{
+        return 0;
+}
+
+void wimax_rfkill_rm(struct wimax_dev *wimax_dev)
+{
+}
+
+#endif /* #ifdef CONFIG_RFKILL */
+
+
+/*
+ * Exporting to user space over generic netlink
+ *
+ * Parse the rfkill command from user space, return a combination
+ * value that describe the states of the different toggles.
+ *
+ * Only one attribute: the new state requested (on, off or no change,
+ * just query).
+ */
+
+static const
+struct nla_policy wimax_gnl_rfkill_policy[WIMAX_GNL_ATTR_MAX + 1] = {
+        [WIMAX_GNL_RFKILL_IFIDX] = {
+                .type = NLA_U32,
+        },
+        [WIMAX_GNL_RFKILL_STATE] = {
+                .type = NLA_U32         /* enum wimax_rf_state */
+        },
+};
+
+
+static
+int wimax_gnl_doit_rfkill(struct sk_buff *skb, struct genl_info *info)
+{
+        int result, ifindex;
+        struct wimax_dev *wimax_dev;
+        struct device *dev;
+        enum wimax_rf_state new_state;
+
+        d_fnstart(3, NULL, "(skb %p info %p)\n", skb, info);
+        result = -ENODEV;
+        if (info->attrs[WIMAX_GNL_RFKILL_IFIDX] == NULL) {
+                printk(KERN_ERR "WIMAX_GNL_OP_RFKILL: can't find IFIDX "
+                        "attribute\n");
+                goto error_no_wimax_dev;
+        }
+        ifindex = nla_get_u32(info->attrs[WIMAX_GNL_RFKILL_IFIDX]);
+        wimax_dev = wimax_dev_get_by_genl_info(info, ifindex);
+        if (wimax_dev == NULL)
+                goto error_no_wimax_dev;
+        dev = wimax_dev_to_dev(wimax_dev);
+        result = -EINVAL;
+        if (info->attrs[WIMAX_GNL_RFKILL_STATE] == NULL) {
+                dev_err(dev, "WIMAX_GNL_RFKILL: can't find RFKILL_STATE "
+                        "attribute\n");
+                goto error_no_pid;
+        }
+        new_state = nla_get_u32(info->attrs[WIMAX_GNL_RFKILL_STATE]);
+
+        /* Execute the operation and send the result back to user space */
+        result = wimax_rfkill(wimax_dev, new_state);
+error_no_pid:
+        dev_put(wimax_dev->net_dev);
+error_no_wimax_dev:
+        d_fnend(3, NULL, "(skb %p info %p) = %d\n", skb, info, result);
+        return result;
+}
+
+
+struct genl_ops wimax_gnl_rfkill = {
+        .cmd = WIMAX_GNL_OP_RFKILL,
+        .flags = GENL_ADMIN_PERM,
+        .policy = wimax_gnl_rfkill_policy,
+        .doit = wimax_gnl_doit_rfkill,
+        .dumpit = NULL,
+};
+
diff --git a/net/wimax/stack.c b/net/wimax/stack.c
new file mode 100644
index 000000000000..d4da92f8981a
--- /dev/null
+++ b/net/wimax/stack.c
@@ -0,0 +1,599 @@
+/*
+ * Linux WiMAX
+ * Initialization, addition and removal of wimax devices
+ *
+ *
+ * Copyright (C) 2005-2006 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This implements:
+ *
+ *   - basic life cycle of 'struct wimax_dev' [wimax_dev_*()]; on
+ *     addition/registration initialize all subfields and allocate
+ *     generic netlink resources for user space communication. On
+ *     removal/unregistration, undo all that.
+ *
+ *   - device state machine [wimax_state_change()] and support to send
+ *     reports to user space when the state changes
+ *     [wimax_gnl_re_state_change*()].
+ *
+ * See include/net/wimax.h for rationales and design.
+ *
+ * ROADMAP
+ *
+ * [__]wimax_state_change()     Called by drivers to update device's state
+ *   wimax_gnl_re_state_change_alloc()
+ *   wimax_gnl_re_state_change_send()
+ *
+ * wimax_dev_init()             Init a device
+ * wimax_dev_add()              Register
+ *   wimax_rfkill_add()
+ *   wimax_gnl_add()            Register all the generic netlink resources.
+ *   wimax_id_table_add()
+ * wimax_dev_rm()               Unregister
+ *   wimax_id_table_rm()
+ *   wimax_gnl_rm()
+ *   wimax_rfkill_rm()
+ */
+#include <linux/device.h>
+#include <net/genetlink.h>
+#include <linux/netdevice.h>
+#include <linux/wimax.h>
+#include "wimax-internal.h"
+
+
+#define D_SUBMODULE stack
+#include "debug-levels.h"
+
+/*
+ * Authoritative source for the RE_STATE_CHANGE attribute policy
+ *
+ * We don't really use it here, but /me likes to keep the definition
+ * close to where the data is generated.
+ */
+/*
+static const
+struct nla_policy wimax_gnl_re_status_change[WIMAX_GNL_ATTR_MAX + 1] = {
+        [WIMAX_GNL_STCH_STATE_OLD] = { .type = NLA_U8 },
+        [WIMAX_GNL_STCH_STATE_NEW] = { .type = NLA_U8 },
+};
+*/
+
+
+/*
+ * Allocate a Report State Change message
+ *
+ * @header: save it, you need it for _send()
+ *
+ * Creates and fills a basic state change message; different code
+ * paths can then add more attributes to the message as needed.
+ *
+ * Use wimax_gnl_re_state_change_send() to send the returned skb.
+ *
+ * Returns: skb with the genl message if ok, IS_ERR() ptr on error
+ *     with an errno code.
+ */
+static
+struct sk_buff *wimax_gnl_re_state_change_alloc(
+        struct wimax_dev *wimax_dev,
+        enum wimax_st new_state, enum wimax_st old_state,
+        void **header)
+{
+        int result;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        void *data;
+        struct sk_buff *report_skb;
+
+        d_fnstart(3, dev, "(wimax_dev %p new_state %u old_state %u)\n",
+                  wimax_dev, new_state, old_state);
+        result = -ENOMEM;
+        report_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
+        if (report_skb == NULL) {
+                dev_err(dev, "RE_STCH: can't create message\n");
+                goto error_new;
+        }
+        data = genlmsg_put(report_skb, 0, wimax_gnl_mcg.id, &wimax_gnl_family,
+                           0, WIMAX_GNL_RE_STATE_CHANGE);
+        if (data == NULL) {
+                dev_err(dev, "RE_STCH: can't put data into message\n");
+                goto error_put;
+        }
+        *header = data;
+
+        result = nla_put_u8(report_skb, WIMAX_GNL_STCH_STATE_OLD, old_state);
+        if (result < 0) {
+                dev_err(dev, "RE_STCH: Error adding OLD attr: %d\n", result);
+                goto error_put;
+        }
+        result = nla_put_u8(report_skb, WIMAX_GNL_STCH_STATE_NEW, new_state);
+        if (result < 0) {
+                dev_err(dev, "RE_STCH: Error adding NEW attr: %d\n", result);
+                goto error_put;
+        }
+        result = nla_put_u32(report_skb, WIMAX_GNL_STCH_IFIDX,
+                             wimax_dev->net_dev->ifindex);
+        if (result < 0) {
+                dev_err(dev, "RE_STCH: Error adding IFINDEX attribute\n");
+                goto error_put;
+        }
+        d_fnend(3, dev, "(wimax_dev %p new_state %u old_state %u) = %p\n",
+                wimax_dev, new_state, old_state, report_skb);
+        return report_skb;
+
+error_put:
+        nlmsg_free(report_skb);
+error_new:
+        d_fnend(3, dev, "(wimax_dev %p new_state %u old_state %u) = %d\n",
+                wimax_dev, new_state, old_state, result);
+        return ERR_PTR(result);
+}
+
+
+/*
+ * Send a Report State Change message (as created with _alloc).
+ *
+ * @report_skb: as returned by wimax_gnl_re_state_change_alloc()
+ * @header: as returned by wimax_gnl_re_state_change_alloc()
+ *
+ * Returns: 0 if ok, < 0 errno code on error.
+ *
+ * If the message is  NULL, pretend it didn't happen.
+ */
+static
+int wimax_gnl_re_state_change_send(
+        struct wimax_dev *wimax_dev, struct sk_buff *report_skb,
+        void *header)
+{
+        int result = 0;
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        d_fnstart(3, dev, "(wimax_dev %p report_skb %p)\n",
+                  wimax_dev, report_skb);
+        if (report_skb == NULL)
+                goto out;
+        genlmsg_end(report_skb, header);
+        result = genlmsg_multicast(report_skb, 0, wimax_gnl_mcg.id, GFP_KERNEL);
+        if (result == -ESRCH)   /* Nobody connected, ignore it */
+                result = 0;     /* btw, the skb is freed already */
+        if (result < 0) {
+                dev_err(dev, "RE_STCH: Error sending: %d\n", result);
+                nlmsg_free(report_skb);
+        }
+out:
+        d_fnend(3, dev, "(wimax_dev %p report_skb %p) = %d\n",
+                wimax_dev, report_skb, result);
+        return result;
+}
+
+
+static
+void __check_new_state(enum wimax_st old_state, enum wimax_st new_state,
+                       unsigned allowed_states_bm)
+{
+        if (WARN_ON(((1 << new_state) & allowed_states_bm) == 0)) {
+                printk(KERN_ERR "SW BUG! Forbidden state change %u -> %u\n",
+                        old_state, new_state);
+        }
+}
+
+
+/*
+ * Set the current state of a WiMAX device [unlocking version of
+ * wimax_state_change().
+ */
+void __wimax_state_change(struct wimax_dev *wimax_dev, enum wimax_st new_state)
+{
+        struct device *dev = wimax_dev_to_dev(wimax_dev);
+        enum wimax_st old_state = wimax_dev->state;
+        struct sk_buff *stch_skb;
+        void *header;
+
+        d_fnstart(3, dev, "(wimax_dev %p new_state %u [old %u])\n",
+                  wimax_dev, new_state, old_state);
+
+        if (WARN_ON(new_state >= __WIMAX_ST_INVALID)) {
+                dev_err(dev, "SW BUG: requesting invalid state %u\n",
+                        new_state);
+                goto out;
+        }
+        if (old_state == new_state)
+                goto out;
+        header = NULL;  /* gcc complains? can't grok why */
+        stch_skb = wimax_gnl_re_state_change_alloc(
+                wimax_dev, new_state, old_state, &header);
+
+        /* Verify the state transition and do exit-from-state actions */
+        switch (old_state) {
+        case __WIMAX_ST_NULL:
+                __check_new_state(old_state, new_state,
+                                  1 << WIMAX_ST_DOWN);
+                break;
+        case WIMAX_ST_DOWN:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_UNINITIALIZED
+                                  | 1 << WIMAX_ST_RADIO_OFF);
+                break;
+        case __WIMAX_ST_QUIESCING:
+                __check_new_state(old_state, new_state, 1 << WIMAX_ST_DOWN);
+                break;
+        case WIMAX_ST_UNINITIALIZED:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_RADIO_OFF);
+                break;
+        case WIMAX_ST_RADIO_OFF:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_READY);
+                break;
+        case WIMAX_ST_READY:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_RADIO_OFF
+                                  | 1 << WIMAX_ST_SCANNING
+                                  | 1 << WIMAX_ST_CONNECTING
+                                  | 1 << WIMAX_ST_CONNECTED);
+                break;
+        case WIMAX_ST_SCANNING:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_RADIO_OFF
+                                  | 1 << WIMAX_ST_READY
+                                  | 1 << WIMAX_ST_CONNECTING
+                                  | 1 << WIMAX_ST_CONNECTED);
+                break;
+        case WIMAX_ST_CONNECTING:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_RADIO_OFF
+                                  | 1 << WIMAX_ST_READY
+                                  | 1 << WIMAX_ST_SCANNING
+                                  | 1 << WIMAX_ST_CONNECTED);
+                break;
+        case WIMAX_ST_CONNECTED:
+                __check_new_state(old_state, new_state,
+                                  1 << __WIMAX_ST_QUIESCING
+                                  | 1 << WIMAX_ST_RADIO_OFF
+                                  | 1 << WIMAX_ST_READY);
+                netif_tx_disable(wimax_dev->net_dev);
+                netif_carrier_off(wimax_dev->net_dev);
+                break;
+        case __WIMAX_ST_INVALID:
+        default:
+                dev_err(dev, "SW BUG: wimax_dev %p is in unknown state %u\n",
+                        wimax_dev, wimax_dev->state);
+                WARN_ON(1);
+                goto out;
+        }
+
+        /* Execute the actions of entry to the new state */
+        switch (new_state) {
+        case __WIMAX_ST_NULL:
+                dev_err(dev, "SW BUG: wimax_dev %p entering NULL state "
+                        "from %u\n", wimax_dev, wimax_dev->state);
+                WARN_ON(1);             /* Nobody can enter this state */
+                break;
+        case WIMAX_ST_DOWN:
+                break;
+        case __WIMAX_ST_QUIESCING:
+                break;
+        case WIMAX_ST_UNINITIALIZED:
+                break;
+        case WIMAX_ST_RADIO_OFF:
+                break;
+        case WIMAX_ST_READY:
+                break;
+        case WIMAX_ST_SCANNING:
+                break;
+        case WIMAX_ST_CONNECTING:
+                break;
+        case WIMAX_ST_CONNECTED:
+                netif_carrier_on(wimax_dev->net_dev);
+                netif_wake_queue(wimax_dev->net_dev);
+                break;
+        case __WIMAX_ST_INVALID:
+        default:
+                BUG();
+        }
+        __wimax_state_set(wimax_dev, new_state);
+        if (stch_skb)
+                wimax_gnl_re_state_change_send(wimax_dev, stch_skb, header);
+out:
+        d_fnend(3, dev, "(wimax_dev %p new_state %u [old %u]) = void\n",
+                wimax_dev, new_state, old_state);
+        return;
+}
+
+
+/**
+ * wimax_state_change - Set the current state of a WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor (properly referenced)
+ * @new_state: New state to switch to
+ *
+ * This implements the state changes for the wimax devices. It will
+ *
+ * - verify that the state transition is legal (for now it'll just
+ *   print a warning if not) according to the table in
+ *   linux/wimax.h's documentation for 'enum wimax_st'.
+ *
+ * - perform the actions needed for leaving the current state and
+ *   whichever are needed for entering the new state.
+ *
+ * - issue a report to user space indicating the new state (and an
+ *   optional payload with information about the new state).
+ *
+ * NOTE: @wimax_dev must be locked
+ */
+void wimax_state_change(struct wimax_dev *wimax_dev, enum wimax_st new_state)
+{
+        mutex_lock(&wimax_dev->mutex);
+        __wimax_state_change(wimax_dev, new_state);
+        mutex_unlock(&wimax_dev->mutex);
+        return;
+}
+EXPORT_SYMBOL_GPL(wimax_state_change);
+
+
+/**
+ * wimax_state_get() - Return the current state of a WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * Returns: Current state of the device according to its driver.
+ */
+enum wimax_st wimax_state_get(struct wimax_dev *wimax_dev)
+{
+        enum wimax_st state;
+        mutex_lock(&wimax_dev->mutex);
+        state = wimax_dev->state;
+        mutex_unlock(&wimax_dev->mutex);
+        return state;
+}
+EXPORT_SYMBOL_GPL(wimax_state_get);
+
+
+/**
+ * wimax_dev_init - initialize a newly allocated instance
+ *
+ * @wimax_dev: WiMAX device descriptor to initialize.
+ *
+ * Initializes fields of a freshly allocated @wimax_dev instance. This
+ * function assumes that after allocation, the memory occupied by
+ * @wimax_dev was zeroed.
+ */
+void wimax_dev_init(struct wimax_dev *wimax_dev)
+{
+        INIT_LIST_HEAD(&wimax_dev->id_table_node);
+        __wimax_state_set(wimax_dev, WIMAX_ST_UNINITIALIZED);
+        mutex_init(&wimax_dev->mutex);
+        mutex_init(&wimax_dev->mutex_reset);
+}
+EXPORT_SYMBOL_GPL(wimax_dev_init);
+
+/*
+ * This extern is declared here because it's easier to keep track --
+ * both declarations are a list of the same
+ */
+extern struct genl_ops
+        wimax_gnl_msg_from_user,
+        wimax_gnl_reset,
+        wimax_gnl_rfkill;
+
+static
+struct genl_ops *wimax_gnl_ops[] = {
+        &wimax_gnl_msg_from_user,
+        &wimax_gnl_reset,
+        &wimax_gnl_rfkill,
+};
+
+
+static
+size_t wimax_addr_scnprint(char *addr_str, size_t addr_str_size,
+                           unsigned char *addr, size_t addr_len)
+{
+        unsigned cnt, total;
+        for (total = cnt = 0; cnt < addr_len; cnt++)
+                total += scnprintf(addr_str + total, addr_str_size - total,
+                                   "%02x%c", addr[cnt],
+                                   cnt == addr_len - 1 ? '\0' : ':');
+        return total;
+}
+
+
+/**
+ * wimax_dev_add - Register a new WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor (as embedded in your @net_dev's
+ *     priv data). You must have called wimax_dev_init() on it before.
+ *
+ * @net_dev: net device the @wimax_dev is associated with. The
+ *     function expects SET_NETDEV_DEV() and register_netdev() were
+ *     already called on it.
+ *
+ * Registers the new WiMAX device, sets up the user-kernel control
+ * interface (generic netlink) and common WiMAX infrastructure.
+ *
+ * Note that the parts that will allow interaction with user space are
+ * setup at the very end, when the rest is in place, as once that
+ * happens, the driver might get user space control requests via
+ * netlink or from debugfs that might translate into calls into
+ * wimax_dev->op_*().
+ */
+int wimax_dev_add(struct wimax_dev *wimax_dev, struct net_device *net_dev)
+{
+        int result;
+        struct device *dev = net_dev->dev.parent;
+        char addr_str[32];
+
+        d_fnstart(3, dev, "(wimax_dev %p net_dev %p)\n", wimax_dev, net_dev);
+
+        /* Do the RFKILL setup before locking, as RFKILL will call
+         * into our functions. */
+        wimax_dev->net_dev = net_dev;
+        result = wimax_rfkill_add(wimax_dev);
+        if (result < 0)
+                goto error_rfkill_add;
+
+        /* Set up user-space interaction */
+        mutex_lock(&wimax_dev->mutex);
+        wimax_id_table_add(wimax_dev);
+        result = wimax_debugfs_add(wimax_dev);
+        if (result < 0) {
+                dev_err(dev, "cannot initialize debugfs: %d\n",
+                        result);
+                goto error_debugfs_add;
+        }
+
+        __wimax_state_set(wimax_dev, WIMAX_ST_DOWN);
+        mutex_unlock(&wimax_dev->mutex);
+
+        wimax_addr_scnprint(addr_str, sizeof(addr_str),
+                            net_dev->dev_addr, net_dev->addr_len);
+        dev_err(dev, "WiMAX interface %s (%s) ready\n",
+                net_dev->name, addr_str);
+        d_fnend(3, dev, "(wimax_dev %p net_dev %p) = 0\n", wimax_dev, net_dev);
+        return 0;
+
+error_debugfs_add:
+        wimax_id_table_rm(wimax_dev);
+        mutex_unlock(&wimax_dev->mutex);
+        wimax_rfkill_rm(wimax_dev);
+error_rfkill_add:
+        d_fnend(3, dev, "(wimax_dev %p net_dev %p) = %d\n",
+                wimax_dev, net_dev, result);
+        return result;
+}
+EXPORT_SYMBOL_GPL(wimax_dev_add);
+
+
+/**
+ * wimax_dev_rm - Unregister an existing WiMAX device
+ *
+ * @wimax_dev: WiMAX device descriptor
+ *
+ * Unregisters a WiMAX device previously registered for use with
+ * wimax_add_rm().
+ *
+ * IMPORTANT! Must call before calling unregister_netdev().
+ *
+ * After this function returns, you will not get any more user space
+ * control requests (via netlink or debugfs) and thus to wimax_dev->ops.
+ *
+ * Reentrancy control is ensured by setting the state to
+ * %__WIMAX_ST_QUIESCING. rfkill operations coming through
+ * wimax_*rfkill*() will be stopped by the quiescing state; ops coming
+ * from the rfkill subsystem will be stopped by the support being
+ * removed by wimax_rfkill_rm().
+ */
+void wimax_dev_rm(struct wimax_dev *wimax_dev)
+{
+        d_fnstart(3, NULL, "(wimax_dev %p)\n", wimax_dev);
+
+        mutex_lock(&wimax_dev->mutex);
+        __wimax_state_change(wimax_dev, __WIMAX_ST_QUIESCING);
+        wimax_debugfs_rm(wimax_dev);
+        wimax_id_table_rm(wimax_dev);
+        __wimax_state_change(wimax_dev, WIMAX_ST_DOWN);
+        mutex_unlock(&wimax_dev->mutex);
+        wimax_rfkill_rm(wimax_dev);
+        d_fnend(3, NULL, "(wimax_dev %p) = void\n", wimax_dev);
+}
+EXPORT_SYMBOL_GPL(wimax_dev_rm);
+
+struct genl_family wimax_gnl_family = {
+        .id = GENL_ID_GENERATE,
+        .name = "WiMAX",
+        .version = WIMAX_GNL_VERSION,
+        .hdrsize = 0,
+        .maxattr = WIMAX_GNL_ATTR_MAX,
+};
+
+struct genl_multicast_group wimax_gnl_mcg = {
+        .name = "msg",
+};
+
+
+
+/* Shutdown the wimax stack */
+static
+int __init wimax_subsys_init(void)
+{
+        int result, cnt;
+
+        d_fnstart(4, NULL, "()\n");
+        snprintf(wimax_gnl_family.name, sizeof(wimax_gnl_family.name),
+                 "WiMAX");
+        result = genl_register_family(&wimax_gnl_family);
+        if (unlikely(result < 0)) {
+                printk(KERN_ERR "cannot register generic netlink family: %d\n",
+                       result);
+                goto error_register_family;
+        }
+
+        for (cnt = 0; cnt < ARRAY_SIZE(wimax_gnl_ops); cnt++) {
+                result = genl_register_ops(&wimax_gnl_family,
+                                           wimax_gnl_ops[cnt]);
+                d_printf(4, NULL, "registering generic netlink op code "
+                         "%u: %d\n", wimax_gnl_ops[cnt]->cmd, result);
+                if (unlikely(result < 0)) {
+                        printk(KERN_ERR "cannot register generic netlink op "
+                               "code %u: %d\n",
+                               wimax_gnl_ops[cnt]->cmd, result);
+                        goto error_register_ops;
+                }
+        }
+
+        result = genl_register_mc_group(&wimax_gnl_family, &wimax_gnl_mcg);
+        if (result < 0)
+                goto error_mc_group;
+        d_fnend(4, NULL, "() = 0\n");
+        return 0;
+
+error_mc_group:
+error_register_ops:
+        for (cnt--; cnt >= 0; cnt--)
+                genl_unregister_ops(&wimax_gnl_family,
+                                    wimax_gnl_ops[cnt]);
+        genl_unregister_family(&wimax_gnl_family);
+error_register_family:
+        d_fnend(4, NULL, "() = %d\n", result);
+        return result;
+
+}
+module_init(wimax_subsys_init);
+
+
+/* Shutdown the wimax stack */
+static
+void __exit wimax_subsys_exit(void)
+{
+        int cnt;
+        wimax_id_table_release();
+        genl_unregister_mc_group(&wimax_gnl_family, &wimax_gnl_mcg);
+        for (cnt = ARRAY_SIZE(wimax_gnl_ops) - 1; cnt >= 0; cnt--)
+                genl_unregister_ops(&wimax_gnl_family,
+                                    wimax_gnl_ops[cnt]);
+        genl_unregister_family(&wimax_gnl_family);
+}
+module_exit(wimax_subsys_exit);
+
+MODULE_AUTHOR("Intel Corporation <linux-wimax@intel.com>");
+MODULE_DESCRIPTION("Linux WiMAX stack");
+MODULE_LICENSE("GPL");
+
diff --git a/net/wimax/wimax-internal.h b/net/wimax/wimax-internal.h
new file mode 100644
index 000000000000..1e743d214856
--- /dev/null
+++ b/net/wimax/wimax-internal.h
@@ -0,0 +1,91 @@
+/*
+ * Linux WiMAX
+ * Internal API for kernel space WiMAX stack
+ *
+ *
+ * Copyright (C) 2007 Intel Corporation <linux-wimax@intel.com>
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ *
+ * This header file is for declarations and definitions internal to
+ * the WiMAX stack. For public APIs and documentation, see
+ * include/net/wimax.h and include/linux/wimax.h.
+ */
+
+#ifndef __WIMAX_INTERNAL_H__
+#define __WIMAX_INTERNAL_H__
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <net/wimax.h>
+
+
+/*
+ * Decide if a (locked) device is ready for use
+ *
+ * Before using the device structure, it must be locked
+ * (wimax_dev->mutex). As well, most operations need to call this
+ * function to check if the state is the right one.
+ *
+ * An error value will be returned if the state is not the right
+ * one. In that case, the caller should not attempt to use the device
+ * and just unlock it.
+ */
+static inline __must_check
+int wimax_dev_is_ready(struct wimax_dev *wimax_dev)
+{
+        if (wimax_dev->state == __WIMAX_ST_NULL)
+                return -EINVAL; /* Device is not even registered! */
+        if (wimax_dev->state == WIMAX_ST_DOWN)
+                return -ENOMEDIUM;
+        if (wimax_dev->state == __WIMAX_ST_QUIESCING)
+                return -ESHUTDOWN;
+        return 0;
+}
+
+
+static inline
+void __wimax_state_set(struct wimax_dev *wimax_dev, enum wimax_st state)
+{
+        wimax_dev->state = state;
+}
+extern void __wimax_state_change(struct wimax_dev *, enum wimax_st);
+
+#ifdef CONFIG_DEBUG_FS
+extern int wimax_debugfs_add(struct wimax_dev *);
+extern void wimax_debugfs_rm(struct wimax_dev *);
+#else
+static inline int wimax_debugfs_add(struct wimax_dev *wimax_dev)
+{
+        return 0;
+}
+static inline void wimax_debugfs_rm(struct wimax_dev *wimax_dev) {}
+#endif
+
+extern void wimax_id_table_add(struct wimax_dev *);
+extern struct wimax_dev *wimax_dev_get_by_genl_info(struct genl_info *, int);
+extern void wimax_id_table_rm(struct wimax_dev *);
+extern void wimax_id_table_release(void);
+
+extern int wimax_rfkill_add(struct wimax_dev *);
+extern void wimax_rfkill_rm(struct wimax_dev *);
+
+extern struct genl_family wimax_gnl_family;
+extern struct genl_multicast_group wimax_gnl_mcg;
+
+#endif /* #ifdef __KERNEL__ */
+#endif /* #ifndef __WIMAX_INTERNAL_H__ */
diff --git a/scripts/.gitignore b/scripts/.gitignore
index b939fbd01195..09e2406f3b78 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -1,6 +1,7 @@
 #
 # Generated files
 #
+ihex2fw
 conmakehash
 kallsyms
 pnmtologo
diff --git a/scripts/Makefile b/scripts/Makefile
index aafdf064feef..035182e16afb 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -2,11 +2,12 @@
 # scripts contains sources for various helper programs used throughout
 # the kernel for the build process.
 # ---------------------------------------------------------------------------
+# ihex2fw:       Parser/loader for IHEX formatted data
 # kallsyms:      Find all symbols in vmlinux
 # pnmttologo:    Convert pnm files to logo files
-# conmakehash:   Create chartable
 # conmakehash:   Create arrays for initializing the kernel console tables
 
+hostprogs-y                      := ihex2fw
 hostprogs-$(CONFIG_KALLSYMS)     += kallsyms
 hostprogs-$(CONFIG_LOGO)         += pnmtologo
 hostprogs-$(CONFIG_VT)           += conmakehash
diff --git a/scripts/bootgraph.pl b/scripts/bootgraph.pl
index f0af9aa9b243..0a498e33b30b 100644
--- a/scripts/bootgraph.pl
+++ b/scripts/bootgraph.pl
@@ -88,7 +88,7 @@ END
 }
 
 print "<?xml version=\"1.0\" standalone=\"no\"?> \n";
-print "<svg width=\"1000\" height=\"100%\" version=\"1.1\" xmlns=\"http://www.w3.org/2000/svg\">\n";
+print "<svg width=\"2000\" height=\"100%\" version=\"1.1\" xmlns=\"http://www.w3.org/2000/svg\">\n";
 
 my @styles;
 
@@ -105,8 +105,9 @@ $styles[9] = "fill:rgb(255,255,128);fill-opacity:0.5;stroke-width:1;stroke:rgb(0
 $styles[10] = "fill:rgb(255,128,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)";
 $styles[11] = "fill:rgb(128,255,255);fill-opacity:0.5;stroke-width:1;stroke:rgb(0,0,0)";
 
-my $mult = 950.0 / ($maxtime - $firsttime);
-my $threshold = ($maxtime - $firsttime) / 60.0;
+my $mult = 1950.0 / ($maxtime - $firsttime);
+my $threshold2 = ($maxtime - $firsttime) / 120.0;
+my $threshold = $threshold2/10;
 my $stylecounter = 0;
 my %rows;
 my $rowscount = 1;
@@ -116,7 +117,7 @@ foreach my $key (@initcalls) {
         my $duration = $end{$key} - $start{$key};
 
         if ($duration >= $threshold) {
-                my ($s, $s2, $e, $w, $y, $y2, $style);
+                my ($s, $s2, $s3, $e, $w, $y, $y2, $style);
                 my $pid = $pids{$key};
 
                 if (!defined($rows{$pid})) {
@@ -125,6 +126,7 @@ foreach my $key (@initcalls) {
                 }
                 $s = ($start{$key} - $firsttime) * $mult;
                 $s2 = $s + 6;
+                $s3 = $s + 1;
                 $e = ($end{$key} - $firsttime) * $mult;
                 $w = $e - $s;
 
@@ -138,7 +140,11 @@ foreach my $key (@initcalls) {
                 };
 
                 print "<rect x=\"$s\" width=\"$w\" y=\"$y\" height=\"145\" style=\"$style\"/>\n";
-                print "<text transform=\"translate($s2,$y2) rotate(90)\">$key</text>\n";
+                if ($duration >= $threshold2) {
+                        print "<text transform=\"translate($s2,$y2) rotate(90)\">$key</text>\n";
+                } else {
+                        print "<text transform=\"translate($s3,$y2) rotate(90)\" font-size=\"3pt\">$key</text>\n";
+                }
         }
 }
 
diff --git a/scripts/config b/scripts/config
new file mode 100755
index 000000000000..68b9761cdc38
--- /dev/null
+++ b/scripts/config
@@ -0,0 +1,150 @@
+#!/bin/bash
+# Manipulate options in a .config file from the command line
+
+usage() {
+        cat >&2 <<EOL
+Manipulate options in a .config file from the command line.
+Usage:
+config options command ...
+commands:
+        --enable|-e option   Enable option
+        --disable|-d option  Disable option
+        --module|-m option      Turn option into a module
+        --state|-s option       Print state of option (n,y,m,undef)
+
+        --enable-after|-E beforeopt option
+                             Enable option directly after other option
+        --disable-after|-D beforeopt option
+                             Disable option directly after other option
+        --module-after|-M beforeopt option
+                             Turn option into module directly after other option
+
+        commands can be repeated multiple times
+
+options:
+        --file .config file to change (default .config)
+
+config doesn't check the validity of the .config file. This is done at next
+ make time.
+The options need to be already in the file before they can be changed,
+but sometimes you can cheat with the --*-after options.
+EOL
+        exit 1
+}
+
+checkarg() {
+        ARG="$1"
+        if [ "$ARG" = "" ] ; then
+                usage
+        fi
+        case "$ARG" in
+        CONFIG_*)
+                ARG="${ARG/CONFIG_/}"
+                ;;
+        esac
+        ARG="`echo $ARG | tr a-z A-Z`"
+}
+
+replace() {
+        sed -i -e "$@" $FN
+}
+
+if [ "$1" = "--file" ]; then
+        FN="$2"
+        if [ "$FN" = "" ] ; then
+                usage
+        fi
+        shift
+        shift
+else
+        FN=.config
+fi
+
+while [ "$1" != "" ] ; do
+        CMD="$1"
+        shift
+        case "$CMD" in
+        --enable|-e)
+                checkarg "$1"
+                replace "s/# CONFIG_$ARG is not set/CONFIG_$ARG=y/"
+                shift
+                ;;
+
+        --disable|-d)
+                checkarg "$1"
+                replace "s/CONFIG_$ARG=[my]/# CONFIG_$ARG is not set/"
+                shift
+                ;;
+
+        --module|-m)
+                checkarg "$1"
+                replace "s/CONFIG_$ARG=y/CONFIG_$ARG=m/" \
+                        -e "s/# CONFIG_$ARG is not set/CONFIG_$ARG=m/"
+                shift
+                ;;
+
+        --state|-s)
+                checkarg "$1"
+                if grep -q "# CONFIG_$ARG is not set" $FN ; then
+                        echo n
+                else
+                        V="$(grep "^CONFIG_$ARG=" $FN)"
+                        if [ $? != 0 ] ; then
+                                echo undef
+                        else
+                                V="${V/CONFIG_$ARG=/}"
+                                V="${V/\"/}"
+                                echo "$V"
+                        fi
+                fi
+                shift
+                ;;
+
+        --enable-after|-E)
+                checkarg "$1"
+                A=$ARG
+                checkarg "$2"
+                B=$ARG
+                replace "/CONFIG_$A=[my]/aCONFIG_$B=y" \
+                        -e "/# CONFIG_$ARG is not set/a/CONFIG_$ARG=y" \
+                        -e "s/# CONFIG_$ARG is not set/CONFIG_$ARG=y/"
+                shift
+                shift
+                ;;
+
+        --disable-after|-D)
+                checkarg "$1"
+                A=$ARG
+                checkarg "$2"
+                B=$ARG
+                replace "/CONFIG_$A=[my]/a# CONFIG_$B is not set" \
+                -e "/# CONFIG_$ARG is not set/a/# CONFIG_$ARG is not set" \
+                -e "s/CONFIG_$ARG=[my]/# CONFIG_$ARG is not set/"
+                shift
+                shift
+                ;;
+
+        --module-after|-M)
+                checkarg "$1"
+                A=$ARG
+                checkarg "$2"
+                B=$ARG
+                replace "/CONFIG_$A=[my]/aCONFIG_$B=m" \
+                        -e "/# CONFIG_$ARG is not set/a/CONFIG_$ARG=m" \
+                        -e "s/CONFIG_$ARG=y/CONFIG_$ARG=m/" \
+                        -e "s/# CONFIG_$ARG is not set/CONFIG_$ARG=m/"
+                shift
+                shift
+                ;;
+
+        # undocumented because it ignores --file (fixme)
+        --refresh)
+                yes "" | make oldconfig
+                ;;
+
+        *)
+                usage
+                ;;
+        esac
+done
+
diff --git a/firmware/ihex2fw.c b/scripts/ihex2fw.c
index 8f7fdaa9e010..8f7fdaa9e010 100644
--- a/firmware/ihex2fw.c
+++ b/scripts/ihex2fw.c
diff --git a/scripts/tags.sh b/scripts/tags.sh
index 9e3451d2c3a1..fdbe78bb5e2b 100755
--- a/scripts/tags.sh
+++ b/scripts/tags.sh
@@ -24,6 +24,11 @@ else
         tree=${srctree}/
 fi
 
+# Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH
+if [ "${ALLSOURCE_ARCHS}" = "" ]; then
+        ALLSOURCE_ARCHS=${SRCARCH}
+fi
+
 # find sources in arch/$ARCH
 find_arch_sources()
 {
@@ -54,26 +59,29 @@ find_other_sources()
 find_sources()
 {
         find_arch_sources $1 "$2"
-        find_include_sources "$2"
-        find_other_sources "$2"
 }
 
 all_sources()
 {
-        find_sources $SRCARCH '*.[chS]'
+        for arch in $ALLSOURCE_ARCHS
+        do
+                find_sources $arch '*.[chS]'
+        done
         if [ ! -z "$archinclude" ]; then
                 find_arch_include_sources $archinclude '*.[chS]'
         fi
+        find_include_sources '*.[chS]'
+        find_other_sources '*.[chS]'
 }
 
 all_kconfigs()
 {
-        find_sources $SRCARCH 'Kconfig*'
+        find_sources $ALLSOURCE_ARCHS 'Kconfig*'
 }
 
 all_defconfigs()
 {
-        find_sources $SRCARCH "defconfig"
+        find_sources $ALLSOURCE_ARCHS "defconfig"
 }
 
 docscope()
diff --git a/sound/oss/aedsp16.c b/sound/oss/aedsp16.c
index a0274f3dac08..3ee9900ffd7b 100644
--- a/sound/oss/aedsp16.c
+++ b/sound/oss/aedsp16.c
@@ -157,7 +157,7 @@
 
    Started Fri Mar 17 16:13:18 MET 1995
 
-   v0.1 (ALPHA, was an user-level program called AudioExcelDSP16.c)
+   v0.1 (ALPHA, was a user-level program called AudioExcelDSP16.c)
    - Initial code.
    v0.2 (ALPHA)
    - Cleanups.
diff --git a/sound/usb/usx2y/usbusx2y.c b/sound/usb/usx2y/usbusx2y.c
index ca26c532e77e..11639bd72a51 100644
--- a/sound/usb/usx2y/usbusx2y.c
+++ b/sound/usb/usx2y/usbusx2y.c
@@ -238,7 +238,7 @@ static void i_usX2Y_In04Int(struct urb *urb)
                                         send = 0;
                                 for (j = 0; j < URBS_AsyncSeq  &&  !err; ++j)
                                         if (0 == usX2Y->AS04.urb[j]->status) {
-                                                struct us428_p4out *p4out = us428ctls->p4out + send;    // FIXME if more then 1 p4out is new, 1 gets lost.
+                                                struct us428_p4out *p4out = us428ctls->p4out + send;    // FIXME if more than 1 p4out is new, 1 gets lost.
                                                 usb_fill_bulk_urb(usX2Y->AS04.urb[j], usX2Y->chip.dev,
                                                                   usb_sndbulkpipe(usX2Y->chip.dev, 0x04), &p4out->val.vol, 
                                                                   p4out->type == eLT_Light ? sizeof(struct us428_lights) : 5,