5 files changed, 29 insertions, 74 deletions

diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 78c43b1a3064..20a76f209629 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -136,72 +136,40 @@ void clear_local_APIC(void)
         apic_read(APIC_ESR);
 }
 
-void __init connect_bsp_APIC(void)
-{
-        if (pic_mode) {
-                /*
-                 * Do not trust the local APIC being empty at bootup.
-                 */
-                clear_local_APIC();
-                /*
-                 * PIC mode, enable APIC mode in the IMCR, i.e.
-                 * connect BSP's local APIC to INT and NMI lines.
-                 */
-                apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x01, 0x23);
-        }
-}
-
 void disconnect_bsp_APIC(int virt_wire_setup)
 {
-        if (pic_mode) {
-                /*
-                 * Put the board back into PIC mode (has an effect
-                 * only on certain older boards).  Note that APIC
-                 * interrupts, including IPIs, won't work beyond
-                 * this point!  The only exception are INIT IPIs.
-                 */
-                apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
-                outb(0x70, 0x22);
-                outb(0x00, 0x23);
-        }
-        else {
-                /* Go back to Virtual Wire compatibility mode */
-                unsigned long value;
-
-                /* For the spurious interrupt use vector F, and enable it */
-                value = apic_read(APIC_SPIV);
-                value &= ~APIC_VECTOR_MASK;
-                value |= APIC_SPIV_APIC_ENABLED;
-                value |= 0xf;
-                apic_write(APIC_SPIV, value);
-
-                if (!virt_wire_setup) {
-                        /* For LVT0 make it edge triggered, active high, external and enabled */
-                        value = apic_read(APIC_LVT0);
-                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
-                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
-                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
-                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
-                        apic_write(APIC_LVT0, value);
-                }
-                else {
-                        /* Disable LVT0 */
-                        apic_write(APIC_LVT0, APIC_LVT_MASKED);
-                }
+        /* Go back to Virtual Wire compatibility mode */
+        unsigned long value;
 
-                /* For LVT1 make it edge triggered, active high, nmi and enabled */
-                value = apic_read(APIC_LVT1);
-                value &= ~(
-                        APIC_MODE_MASK | APIC_SEND_PENDING |
+        /* For the spurious interrupt use vector F, and enable it */
+        value = apic_read(APIC_SPIV);
+        value &= ~APIC_VECTOR_MASK;
+        value |= APIC_SPIV_APIC_ENABLED;
+        value |= 0xf;
+        apic_write(APIC_SPIV, value);
+
+        if (!virt_wire_setup) {
+                /* For LVT0 make it edge triggered, active high, external and enabled */
+                value = apic_read(APIC_LVT0);
+                value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
-                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
-                apic_write(APIC_LVT1, value);
+                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+                apic_write(APIC_LVT0, value);
+        } else {
+                /* Disable LVT0 */
+                apic_write(APIC_LVT0, APIC_LVT_MASKED);
         }
+
+        /* For LVT1 make it edge triggered, active high, nmi and enabled */
+        value = apic_read(APIC_LVT1);
+        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+        apic_write(APIC_LVT1, value);
 }
 
 void disable_local_APIC(void)
@@ -418,7 +386,7 @@ void __cpuinit setup_local_APIC (void)
          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
          */
         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
-        if (!smp_processor_id() && (pic_mode || !value)) {
+        if (!smp_processor_id() && !value) {
                 value = APIC_DM_EXTINT;
                 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
         } else {
@@ -1096,8 +1064,6 @@ int __init APIC_init_uniprocessor (void)
 
         verify_local_APIC();
 
-        connect_bsp_APIC();
-
         phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
         apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
 
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index 90e99cf27aa5..022624503552 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -56,7 +56,6 @@ struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 int mp_irq_entries;
 
 int nr_ioapics;
-int pic_mode;
 unsigned long mp_lapic_addr = 0;
 
 
@@ -514,13 +513,6 @@ void __init get_smp_config (void)
                 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
 
         printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
-        if (mpf->mpf_feature2 & (1<<7)) {
-                printk(KERN_INFO "    IMCR and PIC compatibility mode.\n");
-                pic_mode = 1;
-        } else {
-                printk(KERN_INFO "    Virtual Wire compatibility mode.\n");
-                pic_mode = 0;
-        }
 
         /*
          * Now see if we need to read further.
diff --git a/arch/x86_64/kernel/smpboot.c b/arch/x86_64/kernel/smpboot.c
index d29571e24953..ae7d6d84e352 100644
--- a/arch/x86_64/kernel/smpboot.c
+++ b/arch/x86_64/kernel/smpboot.c
@@ -1090,7 +1090,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         /*
          * Switch from PIC to APIC mode.
          */
-        connect_bsp_APIC();
         setup_local_APIC();
 
         if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
diff --git a/include/asm-x86_64/mpspec.h b/include/asm-x86_64/mpspec.h
index 3c7aae9fd157..1dc83436cc91 100644
--- a/include/asm-x86_64/mpspec.h
+++ b/include/asm-x86_64/mpspec.h
@@ -178,7 +178,6 @@ extern int mp_irq_entries;
 extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
 extern int mpc_default_type;
 extern unsigned long mp_lapic_addr;
-extern int pic_mode;
 
 #ifdef CONFIG_ACPI
 extern void mp_register_lapic (u8 id, u8 enabled);
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index 6353fa41bebe..498fbc1fc179 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -33,7 +33,6 @@ extern cpumask_t cpu_initialized;
  
 extern void smp_alloc_memory(void);
 extern volatile unsigned long smp_invalidate_needed;
-extern int pic_mode;
 extern void lock_ipi_call_lock(void);
 extern void unlock_ipi_call_lock(void);
 extern int smp_num_siblings;