diff options
| -rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 6e87ab269ffe..73d4d65249cd 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h | |||
| @@ -83,9 +83,9 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 83 | 83 | ||
| 84 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 84 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
| 85 | #define bfin_read_SWRST() bfin_read_SICA_SWRST() | 85 | #define bfin_read_SWRST() bfin_read_SICA_SWRST() |
| 86 | #define bfin_write_SWRST() bfin_write_SICA_SWRST() | 86 | #define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) |
| 87 | #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() | 87 | #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() |
| 88 | #define bfin_write_SYSCR() bfin_write_SICA_SYSCR() | 88 | #define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) |
| 89 | 89 | ||
| 90 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 90 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
| 91 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) | 91 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) |