15 files changed, 338 insertions, 66 deletions

diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 2e635b814c14..2362c498f52e 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -281,10 +281,14 @@ map_single(struct device *dev, void *ptr, size_t size,
                 ptr = buf->safe;
 
                 dma_addr = buf->safe_dma_addr;
+        } else {
+                /*
+                 * We don't need to sync the DMA buffer since
+                 * it was allocated via the coherent allocators.
+                 */
+                consistent_sync(ptr, size, dir);
         }
 
-        consistent_sync(ptr, size, dir);
-
         return dma_addr;
 }
 
@@ -317,12 +321,12 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                 DO_STATS ( device_info->bounce_count++ );
 
                 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
-                        unsigned long ptr;
+                        void *ptr = buf->ptr;
 
                         dev_dbg(dev,
                                 "%s: copy back safe %p to unsafe %p size %d\n",
-                                __func__, buf->safe, buf->ptr, size);
-                        memcpy(buf->ptr, buf->safe, size);
+                                __func__, buf->safe, ptr, size);
+                        memcpy(ptr, buf->safe, size);
 
                         /*
                          * DMA buffers must have the same cache properties
@@ -332,8 +336,8 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                          * bidirectional case because we know the cache
                          * lines will be coherent with the data written.
                          */
-                        ptr = (unsigned long)buf->ptr;
                         dmac_clean_range(ptr, ptr + size);
+                        outer_clean_range(__pa(ptr), __pa(ptr) + size);
                 }
                 free_safe_buffer(device_info, buf);
         }
@@ -397,7 +401,10 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                 default:
                         BUG();
                 }
-                consistent_sync(buf->safe, size, dir);
+                /*
+                 * No need to sync the safe buffer - it was allocated
+                 * via the coherent allocators.
+                 */
         } else {
                 consistent_sync(dma_to_virt(dev, dma_addr), size, dir);
         }
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bbab134cd82d..243aea458057 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -88,6 +88,9 @@ struct cpu_user_fns cpu_user;
 #ifdef MULTI_CACHE
 struct cpu_cache_fns cpu_cache;
 #endif
+#ifdef CONFIG_OUTER_CACHE
+struct outer_cache_fns outer_cache;
+#endif
 
 struct stack {
         u32 irq[3];
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index aade2f72c920..af3fa9d622ff 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -609,3 +609,10 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
           Forget about fast user space cmpxchg support.
           It is just not possible.
 
+config OUTER_CACHE
+        bool
+        default n
+
+config CACHE_L2X0
+        bool
+        select OUTER_CACHE
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index d2f5672ecf62..2f8b95947774 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -66,3 +66,5 @@ obj-$(CONFIG_CPU_SA1100)	+= proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)        += proc-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += proc-xsc3.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
+
+obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
new file mode 100644
index 000000000000..08a36f1b35d2
--- /dev/null
+++ b/arch/arm/mm/cache-l2x0.c
@@ -0,0 +1,104 @@
+/*
+ * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define CACHE_LINE_SIZE         32
+
+static void __iomem *l2x0_base;
+
+static inline void sync_writel(unsigned long val, unsigned long reg,
+                               unsigned long complete_mask)
+{
+        writel(val, l2x0_base + reg);
+        /* wait for the operation to complete */
+        while (readl(l2x0_base + reg) & complete_mask)
+                ;
+}
+
+static inline void cache_sync(void)
+{
+        sync_writel(0, L2X0_CACHE_SYNC, 1);
+}
+
+static inline void l2x0_inv_all(void)
+{
+        /* invalidate all ways */
+        sync_writel(0xff, L2X0_INV_WAY, 0xff);
+        cache_sync();
+}
+
+static void l2x0_inv_range(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+
+        start &= ~(CACHE_LINE_SIZE - 1);
+        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+                sync_writel(addr, L2X0_INV_LINE_PA, 1);
+        cache_sync();
+}
+
+static void l2x0_clean_range(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+
+        start &= ~(CACHE_LINE_SIZE - 1);
+        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+                sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
+        cache_sync();
+}
+
+static void l2x0_flush_range(unsigned long start, unsigned long end)
+{
+        unsigned long addr;
+
+        start &= ~(CACHE_LINE_SIZE - 1);
+        for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+                sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
+        cache_sync();
+}
+
+void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+{
+        __u32 aux;
+
+        l2x0_base = base;
+
+        /* disable L2X0 */
+        writel(0, l2x0_base + L2X0_CTRL);
+
+        aux = readl(l2x0_base + L2X0_AUX_CTRL);
+        aux &= aux_mask;
+        aux |= aux_val;
+        writel(aux, l2x0_base + L2X0_AUX_CTRL);
+
+        l2x0_inv_all();
+
+        /* enable L2X0 */
+        writel(1, l2x0_base + L2X0_CTRL);
+
+        outer_cache.inv_range = l2x0_inv_range;
+        outer_cache.clean_range = l2x0_clean_range;
+        outer_cache.flush_range = l2x0_flush_range;
+
+        printk(KERN_INFO "L2X0 cache controller enabled\n");
+}
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index 6a9c362fef5e..1f9f94f9af4b 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -205,9 +205,10 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
          * kernel direct-mapped region for device DMA.
          */
         {
-                unsigned long kaddr = (unsigned long)page_address(page);
-                memset(page_address(page), 0, size);
-                dmac_flush_range(kaddr, kaddr + size);
+                void *ptr = page_address(page);
+                memset(ptr, 0, size);
+                dmac_flush_range(ptr, ptr + size);
+                outer_flush_range(__pa(ptr), __pa(ptr) + size);
         }
 
         /*
@@ -480,20 +481,24 @@ core_initcall(consistent_init);
  * platforms with CONFIG_DMABOUNCE.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-void consistent_sync(void *vaddr, size_t size, int direction)
+void consistent_sync(const void *start, size_t size, int direction)
 {
-        unsigned long start = (unsigned long)vaddr;
-        unsigned long end   = start + size;
+        const void *end = start + size;
+
+        BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(end - 1));
 
         switch (direction) {
         case DMA_FROM_DEVICE:           /* invalidate only */
                 dmac_inv_range(start, end);
+                outer_inv_range(__pa(start), __pa(end));
                 break;
         case DMA_TO_DEVICE:             /* writeback only */
                 dmac_clean_range(start, end);
+                outer_clean_range(__pa(start), __pa(end));
                 break;
         case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
                 dmac_flush_range(start, end);
+                outer_flush_range(__pa(start), __pa(end));
                 break;
         default:
                 BUG();
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 79e800202424..9da43a0fdcdf 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -19,7 +19,8 @@ unsigned int cpu_last_asid = { 1 << ASID_BITS };
 /*
  * We fork()ed a process, and we need a new context for the child
  * to run in.  We reserve version 0 for initial tasks so we will
- * always allocate an ASID.
+ * always allocate an ASID. The ASID 0 is reserved for the TTBR
+ * register changing sequence.
  */
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
@@ -38,8 +39,15 @@ void __new_context(struct mm_struct *mm)
          * If we've used up all our ASIDs, we need
          * to start a new version and flush the TLB.
          */
-        if ((asid & ~ASID_MASK) == 0)
+        if ((asid & ~ASID_MASK) == 0) {
+                asid = ++cpu_last_asid;
+                /* set the reserved ASID before flushing the TLB */
+                asm("mcr        p15, 0, %0, c13, c0, 1  @ set reserved context ID\n"
+                    :
+                    : "r" (0));
+                isb();
                 flush_tlb_all();
+        }
 
         mm->context.id = asid;
 }
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index f27d9eb64803..eb42e5b94863 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -33,6 +33,12 @@
 #define TTB_RGN_WT      (2 << 3)
 #define TTB_RGN_WB      (3 << 3)
 
+#ifndef CONFIG_SMP
+#define TTB_FLAGS       TTB_RGN_WBWA
+#else
+#define TTB_FLAGS       TTB_RGN_WBWA|TTB_S
+#endif
+
 ENTRY(cpu_v6_proc_init)
         mov     pc, lr
 
@@ -95,9 +101,7 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
         mov     r2, #0
         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
-#ifdef CONFIG_SMP
-        orr     r0, r0, #TTB_RGN_WBWA|TTB_S     @ mark PTWs shared, outer cacheable
-#endif
+        orr     r0, r0, #TTB_FLAGS
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -206,9 +210,7 @@ __v6_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
-#ifdef CONFIG_SMP
-        orr     r4, r4, #TTB_RGN_WBWA|TTB_S     @ mark PTWs shared, outer cacheable
-#endif
+        orr     r4, r4, #TTB_FLAGS
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 #endif /* CONFIG_MMU */
         adr     r5, v6_crval
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index fd6adde39091..20f84bbaa9bb 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -53,6 +53,8 @@ ENTRY(v6wbi_flush_user_tlb_range)
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
         blo     1b
+        mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
+        mcr     p15, 0, ip, c7, c10, 4          @ data synchronization barrier
         mov     pc, lr
 
 /*
@@ -80,7 +82,9 @@ ENTRY(v6wbi_flush_kern_tlb_range)
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
         blo     1b
+        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ data synchronization barrier
+        mcr     p15, 0, r2, c7, c5, 4           @ prefetch flush
         mov     pc, lr
 
         .section ".text.init", #alloc, #execinstr
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 5f531ea03059..afad32c76e6c 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -185,9 +185,15 @@ struct cpu_cache_fns {
         void (*coherent_user_range)(unsigned long, unsigned long);
         void (*flush_kern_dcache_page)(void *);
 
-        void (*dma_inv_range)(unsigned long, unsigned long);
-        void (*dma_clean_range)(unsigned long, unsigned long);
-        void (*dma_flush_range)(unsigned long, unsigned long);
+        void (*dma_inv_range)(const void *, const void *);
+        void (*dma_clean_range)(const void *, const void *);
+        void (*dma_flush_range)(const void *, const void *);
+};
+
+struct outer_cache_fns {
+        void (*inv_range)(unsigned long, unsigned long);
+        void (*clean_range)(unsigned long, unsigned long);
+        void (*flush_range)(unsigned long, unsigned long);
 };
 
 /*
@@ -240,9 +246,40 @@ extern void __cpuc_flush_dcache_page(void *);
 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 
-extern void dmac_inv_range(unsigned long, unsigned long);
-extern void dmac_clean_range(unsigned long, unsigned long);
-extern void dmac_flush_range(unsigned long, unsigned long);
+extern void dmac_inv_range(const void *, const void *);
+extern void dmac_clean_range(const void *, const void *);
+extern void dmac_flush_range(const void *, const void *);
+
+#endif
+
+#ifdef CONFIG_OUTER_CACHE
+
+extern struct outer_cache_fns outer_cache;
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.inv_range)
+                outer_cache.inv_range(start, end);
+}
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.clean_range)
+                outer_cache.clean_range(start, end);
+}
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.flush_range)
+                outer_cache.flush_range(start, end);
+}
+
+#else
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{ }
 
 #endif
 
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index 9bc46b486afb..a1d574cdcc14 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -17,7 +17,7 @@
  * platforms with CONFIG_DMABOUNCE.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-extern void consistent_sync(void *kaddr, size_t size, int rw);
+extern void consistent_sync(const void *kaddr, size_t size, int rw);
 
 /*
  * Return whether the given device DMA address mask can be supported
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index 4c2885abbe6c..3c12a7625304 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -57,6 +57,7 @@
         __asm__ __volatile__(                           \
         "mcr    p15, 0, %0, c3, c0      @ set domain"   \
           : : "r" (x));                                 \
+        isb();                                          \
         } while (0)
 
 #define modify_domain(dom,type)                                 \
diff --git a/include/asm-arm/hardware/cache-l2x0.h b/include/asm-arm/hardware/cache-l2x0.h
new file mode 100644
index 000000000000..54029a740396
--- /dev/null
+++ b/include/asm-arm/hardware/cache-l2x0.h
@@ -0,0 +1,56 @@
+/*
+ * include/asm-arm/hardware/cache-l2x0.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_L2X0_H
+#define __ASM_ARM_HARDWARE_L2X0_H
+
+#define L2X0_CACHE_ID                   0x000
+#define L2X0_CACHE_TYPE                 0x004
+#define L2X0_CTRL                       0x100
+#define L2X0_AUX_CTRL                   0x104
+#define L2X0_EVENT_CNT_CTRL             0x200
+#define L2X0_EVENT_CNT1_CFG             0x204
+#define L2X0_EVENT_CNT0_CFG             0x208
+#define L2X0_EVENT_CNT1_VAL             0x20C
+#define L2X0_EVENT_CNT0_VAL             0x210
+#define L2X0_INTR_MASK                  0x214
+#define L2X0_MASKED_INTR_STAT           0x218
+#define L2X0_RAW_INTR_STAT              0x21C
+#define L2X0_INTR_CLEAR                 0x220
+#define L2X0_CACHE_SYNC                 0x730
+#define L2X0_INV_LINE_PA                0x770
+#define L2X0_INV_WAY                    0x77C
+#define L2X0_CLEAN_LINE_PA              0x7B0
+#define L2X0_CLEAN_LINE_IDX             0x7B8
+#define L2X0_CLEAN_WAY                  0x7BC
+#define L2X0_CLEAN_INV_LINE_PA          0x7F0
+#define L2X0_CLEAN_INV_LINE_IDX         0x7F8
+#define L2X0_CLEAN_INV_WAY              0x7FC
+#define L2X0_LOCKDOWN_WAY_D             0x900
+#define L2X0_LOCKDOWN_WAY_I             0x904
+#define L2X0_TEST_OPERATION             0xF00
+#define L2X0_LINE_DATA                  0xF10
+#define L2X0_LINE_TAG                   0xF30
+#define L2X0_DEBUG_CTRL                 0xF40
+
+#ifndef __ASSEMBLY__
+extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#endif
+
+#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index aa223fc546af..f4386906b200 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -140,6 +140,40 @@ static inline int cpu_is_xsc3(void)
 #define cpu_is_xscale() 1
 #endif
 
+#define UDBG_UNDEFINED  (1 << 0)
+#define UDBG_SYSCALL    (1 << 1)
+#define UDBG_BADABORT   (1 << 2)
+#define UDBG_SEGV       (1 << 3)
+#define UDBG_BUS        (1 << 4)
+
+extern unsigned int user_debug;
+
+#if __LINUX_ARM_ARCH__ >= 4
+#define vectors_high()  (cr_alignment & CR_V)
+#else
+#define vectors_high()  (0)
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                    : : "r" (0) : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+#define mb() dmb()
+#define rmb() mb()
+#define wmb() mb()
+#define read_barrier_depends() do { } while(0)
+#define set_mb(var, value)  do { var = value; mb(); } while (0)
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 
@@ -154,6 +188,7 @@ static inline void set_cr(unsigned int val)
 {
         asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
           : : "r" (val) : "cc");
+        isb();
 }
 
 #ifndef CONFIG_SMP
@@ -176,34 +211,9 @@ static inline void set_copro_access(unsigned int val)
 {
         asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
           : : "r" (val) : "cc");
+        isb();
 }
 
-#define UDBG_UNDEFINED  (1 << 0)
-#define UDBG_SYSCALL    (1 << 1)
-#define UDBG_BADABORT   (1 << 2)
-#define UDBG_SEGV       (1 << 3)
-#define UDBG_BUS        (1 << 4)
-
-extern unsigned int user_debug;
-
-#if __LINUX_ARM_ARCH__ >= 4
-#define vectors_high()  (cr_alignment & CR_V)
-#else
-#define vectors_high()  (0)
-#endif
-
-#if __LINUX_ARM_ARCH__ >= 6
-#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
-                                   : : "r" (0) : "memory")
-#else
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-#endif
-#define rmb() mb()
-#define wmb() mb()
-#define read_barrier_depends() do { } while(0)
-#define set_mb(var, value)  do { var = value; mb(); } while (0)
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
 /*
  * switch_mm() may do a full cache flush over the context switch,
  * so enable interrupts over the context switch to avoid high
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index cd10a0b5f8ae..08c6991dc9c9 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,7 +247,7 @@ static inline void local_flush_tlb_all(void)
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (tlb_flag(TLB_V3_FULL))
                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
@@ -257,6 +257,15 @@ static inline void local_flush_tlb_all(void)
                 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+                isb();
+        }
 }
 
 static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,7 +275,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
                 if (tlb_flag(TLB_V3_FULL))
@@ -285,6 +294,14 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
                 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
         if (tlb_flag(TLB_V6_I_ASID))
                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+        }
 }
 
 static inline void
@@ -296,7 +313,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
+                dsb();
 
         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
                 if (tlb_flag(TLB_V3_PAGE))
@@ -317,6 +334,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
+
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+        }
 }
 
 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,7 +352,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         kaddr &= PAGE_MASK;
 
         if (tlb_flag(TLB_WB))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+                dsb();
 
         if (tlb_flag(TLB_V3_PAGE))
                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
@@ -347,11 +372,14 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 
-        /* The ARM ARM states that the completion of a TLB maintenance
-         * operation is only guaranteed by a DSB instruction
-         */
-        if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
-                asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
+        if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
+                     TLB_V6_I_PAGE | TLB_V6_D_PAGE |
+                     TLB_V6_I_ASID | TLB_V6_D_ASID)) {
+                /* flush the branch target cache */
+                asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
+                dsb();
+                isb();
+        }
 }
 
 /*
@@ -369,15 +397,13 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
  */
 static inline void flush_pmd_entry(pmd_t *pmd)
 {
-        const unsigned int zero = 0;
         const unsigned int __tlb_flag = __cpu_tlb_flags;
 
         if (tlb_flag(TLB_DCLEAN))
                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
                         : : "r" (pmd) : "cc");
         if (tlb_flag(TLB_WB))
-                asm("mcr        p15, 0, %0, c7, c10, 4  @ flush_pmd"
-                        : : "r" (zero) : "cc");
+                dsb();
 }
 
 static inline void clean_pmd_entry(pmd_t *pmd)