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-rw-r--r--arch/blackfin/Kconfig5
-rw-r--r--arch/blackfin/include/asm/mem_init.h6
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 56ee44d7b2d9..a949c4fbbddd 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -330,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75
330 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) 330 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
331 default y 331 default y
332 332
333config MEM_MT48LC32M8A2_75
334 bool
335 depends on (BFIN518F_EZBRD)
336 default y
337
333source "arch/blackfin/mach-bf518/Kconfig" 338source "arch/blackfin/mach-bf518/Kconfig"
334source "arch/blackfin/mach-bf527/Kconfig" 339source "arch/blackfin/mach-bf527/Kconfig"
335source "arch/blackfin/mach-bf533/Kconfig" 340source "arch/blackfin/mach-bf533/Kconfig"
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 3cbc0f81ebf3..255a9316ad36 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -13,7 +13,8 @@
13 defined(CONFIG_MEM_GENERIC_BOARD) || \ 13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ 15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) 16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
17 defined(CONFIG_MEM_MT48LC32M8A2_75)
17#if (CONFIG_SCLK_HZ > 119402985) 18#if (CONFIG_SCLK_HZ > 119402985)
18#define SDRAM_tRP TRP_2 19#define SDRAM_tRP TRP_2
19#define SDRAM_tRP_num 2 20#define SDRAM_tRP_num 2
@@ -100,7 +101,8 @@
100 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 101 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
101 defined(CONFIG_MEM_GENERIC_BOARD) || \ 102 defined(CONFIG_MEM_GENERIC_BOARD) || \
102 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 103 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
103 defined(CONFIG_MEM_MT48LC16M16A2TG_75) 104 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
105 defined(CONFIG_MEM_MT48LC32M8A2_75)
104 /*SDRAM INFORMATION: */ 106 /*SDRAM INFORMATION: */
105#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 107#define SDRAM_Tref 64 /* Refresh period in milliseconds */
106#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 108#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */