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-rw-r--r--drivers/gpu/drm/drm_crtc.c3
-rw-r--r--drivers/gpu/drm/i915/Makefile1
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7017.c9
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7xxx.c16
-rw-r--r--drivers/gpu/drm/i915/dvo_ivch.c37
-rw-r--r--drivers/gpu/drm/i915/dvo_sil164.c20
-rw-r--r--drivers/gpu/drm/i915/dvo_tfp410.c34
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c117
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c29
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h28
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c45
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c97
-rw-r--r--drivers/gpu/drm/i915/i915_opregion.c90
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h14
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c8
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c135
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h17
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c32
-rw-r--r--drivers/gpu/drm/i915/intel_display.c396
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c64
-rw-r--r--drivers/gpu/drm/i915/intel_dp_i2c.c8
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h37
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c7
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c77
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c105
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c1416
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c10
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c58
-rw-r--r--include/drm/drmP.h15
-rw-r--r--include/drm/drm_crtc.h3
-rw-r--r--include/drm/drm_os_linux.h2
-rw-r--r--include/drm/i915_drm.h71
33 files changed, 2650 insertions, 353 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 32756e67dd56..ac2fa193072b 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -247,7 +247,8 @@ static void drm_mode_object_put(struct drm_device *dev,
247 mutex_unlock(&dev->mode_config.idr_mutex); 247 mutex_unlock(&dev->mode_config.idr_mutex);
248} 248}
249 249
250void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type) 250struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
251 uint32_t id, uint32_t type)
251{ 252{
252 struct drm_mode_object *obj = NULL; 253 struct drm_mode_object *obj = NULL;
253 254
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index fa7b9be096bc..87b21996cd6a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
23 intel_fb.o \ 23 intel_fb.o \
24 intel_tv.o \ 24 intel_tv.o \
25 intel_dvo.o \ 25 intel_dvo.o \
26 intel_overlay.o \
26 dvo_ch7xxx.o \ 27 dvo_ch7xxx.o \
27 dvo_ch7017.o \ 28 dvo_ch7017.o \
28 dvo_ivch.o \ 29 dvo_ivch.o \
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c b/drivers/gpu/drm/i915/dvo_ch7017.c
index 621815b531db..1184c14ba87d 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -249,7 +249,8 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
249 if (val != CH7017_DEVICE_ID_VALUE && 249 if (val != CH7017_DEVICE_ID_VALUE &&
250 val != CH7018_DEVICE_ID_VALUE && 250 val != CH7018_DEVICE_ID_VALUE &&
251 val != CH7019_DEVICE_ID_VALUE) { 251 val != CH7019_DEVICE_ID_VALUE) {
252 DRM_DEBUG("ch701x not detected, got %d: from %s Slave %d.\n", 252 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
253 "Slave %d.\n",
253 val, i2cbus->adapter.name,dvo->slave_addr); 254 val, i2cbus->adapter.name,dvo->slave_addr);
254 goto fail; 255 goto fail;
255 } 256 }
@@ -284,7 +285,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
284 uint8_t horizontal_active_pixel_output, vertical_active_line_output; 285 uint8_t horizontal_active_pixel_output, vertical_active_line_output;
285 uint8_t active_input_line_output; 286 uint8_t active_input_line_output;
286 287
287 DRM_DEBUG("Registers before mode setting\n"); 288 DRM_DEBUG_KMS("Registers before mode setting\n");
288 ch7017_dump_regs(dvo); 289 ch7017_dump_regs(dvo);
289 290
290 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ 291 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
@@ -346,7 +347,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
346 /* Turn the LVDS back on with new settings. */ 347 /* Turn the LVDS back on with new settings. */
347 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); 348 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down);
348 349
349 DRM_DEBUG("Registers after mode setting\n"); 350 DRM_DEBUG_KMS("Registers after mode setting\n");
350 ch7017_dump_regs(dvo); 351 ch7017_dump_regs(dvo);
351} 352}
352 353
@@ -386,7 +387,7 @@ static void ch7017_dump_regs(struct intel_dvo_device *dvo)
386#define DUMP(reg) \ 387#define DUMP(reg) \
387do { \ 388do { \
388 ch7017_read(dvo, reg, &val); \ 389 ch7017_read(dvo, reg, &val); \
389 DRM_DEBUG(#reg ": %02x\n", val); \ 390 DRM_DEBUG_KMS(#reg ": %02x\n", val); \
390} while (0) 391} while (0)
391 392
392 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); 393 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index a9b896289680..d56ff5cc22b2 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -152,7 +152,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
152 }; 152 };
153 153
154 if (!ch7xxx->quiet) { 154 if (!ch7xxx->quiet) {
155 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 155 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
156 addr, i2cbus->adapter.name, dvo->slave_addr); 156 addr, i2cbus->adapter.name, dvo->slave_addr);
157 } 157 }
158 return false; 158 return false;
@@ -179,7 +179,7 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
179 return true; 179 return true;
180 180
181 if (!ch7xxx->quiet) { 181 if (!ch7xxx->quiet) {
182 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 182 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
183 addr, i2cbus->adapter.name, dvo->slave_addr); 183 addr, i2cbus->adapter.name, dvo->slave_addr);
184 } 184 }
185 185
@@ -207,7 +207,8 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
207 207
208 name = ch7xxx_get_id(vendor); 208 name = ch7xxx_get_id(vendor);
209 if (!name) { 209 if (!name) {
210 DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", 210 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
211 "slave %d.\n",
211 vendor, adapter->name, dvo->slave_addr); 212 vendor, adapter->name, dvo->slave_addr);
212 goto out; 213 goto out;
213 } 214 }
@@ -217,13 +218,14 @@ static bool ch7xxx_init(struct intel_dvo_device *dvo,
217 goto out; 218 goto out;
218 219
219 if (device != CH7xxx_DID) { 220 if (device != CH7xxx_DID) {
220 DRM_DEBUG("ch7xxx not detected; got 0x%02x from %s slave %d.\n", 221 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
222 "slave %d.\n",
221 vendor, adapter->name, dvo->slave_addr); 223 vendor, adapter->name, dvo->slave_addr);
222 goto out; 224 goto out;
223 } 225 }
224 226
225 ch7xxx->quiet = false; 227 ch7xxx->quiet = false;
226 DRM_DEBUG("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", 228 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
227 name, vendor, device); 229 name, vendor, device);
228 return true; 230 return true;
229out: 231out:
@@ -315,8 +317,8 @@ static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
315 317
316 for (i = 0; i < CH7xxx_NUM_REGS; i++) { 318 for (i = 0; i < CH7xxx_NUM_REGS; i++) {
317 if ((i % 8) == 0 ) 319 if ((i % 8) == 0 )
318 DRM_DEBUG("\n %02X: ", i); 320 DRM_LOG_KMS("\n %02X: ", i);
319 DRM_DEBUG("%02X ", ch7xxx->mode_reg.regs[i]); 321 DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]);
320 } 322 }
321} 323}
322 324
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index aa176f9921fe..24169e528f0f 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -202,7 +202,8 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
202 }; 202 };
203 203
204 if (!priv->quiet) { 204 if (!priv->quiet) {
205 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 205 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
206 "%s:%02x.\n",
206 addr, i2cbus->adapter.name, dvo->slave_addr); 207 addr, i2cbus->adapter.name, dvo->slave_addr);
207 } 208 }
208 return false; 209 return false;
@@ -230,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
230 return true; 231 return true;
231 232
232 if (!priv->quiet) { 233 if (!priv->quiet) {
233 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 234 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
234 addr, i2cbus->adapter.name, dvo->slave_addr); 235 addr, i2cbus->adapter.name, dvo->slave_addr);
235 } 236 }
236 237
@@ -261,7 +262,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
261 * the address it's responding on. 262 * the address it's responding on.
262 */ 263 */
263 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 264 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
264 DRM_DEBUG("ivch detect failed due to address mismatch " 265 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
265 "(%d vs %d)\n", 266 "(%d vs %d)\n",
266 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 267 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
267 goto out; 268 goto out;
@@ -367,41 +368,41 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
367 uint16_t val; 368 uint16_t val;
368 369
369 ivch_read(dvo, VR00, &val); 370 ivch_read(dvo, VR00, &val);
370 DRM_DEBUG("VR00: 0x%04x\n", val); 371 DRM_LOG_KMS("VR00: 0x%04x\n", val);
371 ivch_read(dvo, VR01, &val); 372 ivch_read(dvo, VR01, &val);
372 DRM_DEBUG("VR01: 0x%04x\n", val); 373 DRM_LOG_KMS("VR01: 0x%04x\n", val);
373 ivch_read(dvo, VR30, &val); 374 ivch_read(dvo, VR30, &val);
374 DRM_DEBUG("VR30: 0x%04x\n", val); 375 DRM_LOG_KMS("VR30: 0x%04x\n", val);
375 ivch_read(dvo, VR40, &val); 376 ivch_read(dvo, VR40, &val);
376 DRM_DEBUG("VR40: 0x%04x\n", val); 377 DRM_LOG_KMS("VR40: 0x%04x\n", val);
377 378
378 /* GPIO registers */ 379 /* GPIO registers */
379 ivch_read(dvo, VR80, &val); 380 ivch_read(dvo, VR80, &val);
380 DRM_DEBUG("VR80: 0x%04x\n", val); 381 DRM_LOG_KMS("VR80: 0x%04x\n", val);
381 ivch_read(dvo, VR81, &val); 382 ivch_read(dvo, VR81, &val);
382 DRM_DEBUG("VR81: 0x%04x\n", val); 383 DRM_LOG_KMS("VR81: 0x%04x\n", val);
383 ivch_read(dvo, VR82, &val); 384 ivch_read(dvo, VR82, &val);
384 DRM_DEBUG("VR82: 0x%04x\n", val); 385 DRM_LOG_KMS("VR82: 0x%04x\n", val);
385 ivch_read(dvo, VR83, &val); 386 ivch_read(dvo, VR83, &val);
386 DRM_DEBUG("VR83: 0x%04x\n", val); 387 DRM_LOG_KMS("VR83: 0x%04x\n", val);
387 ivch_read(dvo, VR84, &val); 388 ivch_read(dvo, VR84, &val);
388 DRM_DEBUG("VR84: 0x%04x\n", val); 389 DRM_LOG_KMS("VR84: 0x%04x\n", val);
389 ivch_read(dvo, VR85, &val); 390 ivch_read(dvo, VR85, &val);
390 DRM_DEBUG("VR85: 0x%04x\n", val); 391 DRM_LOG_KMS("VR85: 0x%04x\n", val);
391 ivch_read(dvo, VR86, &val); 392 ivch_read(dvo, VR86, &val);
392 DRM_DEBUG("VR86: 0x%04x\n", val); 393 DRM_LOG_KMS("VR86: 0x%04x\n", val);
393 ivch_read(dvo, VR87, &val); 394 ivch_read(dvo, VR87, &val);
394 DRM_DEBUG("VR87: 0x%04x\n", val); 395 DRM_LOG_KMS("VR87: 0x%04x\n", val);
395 ivch_read(dvo, VR88, &val); 396 ivch_read(dvo, VR88, &val);
396 DRM_DEBUG("VR88: 0x%04x\n", val); 397 DRM_LOG_KMS("VR88: 0x%04x\n", val);
397 398
398 /* Scratch register 0 - AIM Panel type */ 399 /* Scratch register 0 - AIM Panel type */
399 ivch_read(dvo, VR8E, &val); 400 ivch_read(dvo, VR8E, &val);
400 DRM_DEBUG("VR8E: 0x%04x\n", val); 401 DRM_LOG_KMS("VR8E: 0x%04x\n", val);
401 402
402 /* Scratch register 1 - Status register */ 403 /* Scratch register 1 - Status register */
403 ivch_read(dvo, VR8F, &val); 404 ivch_read(dvo, VR8F, &val);
404 DRM_DEBUG("VR8F: 0x%04x\n", val); 405 DRM_LOG_KMS("VR8F: 0x%04x\n", val);
405} 406}
406 407
407static void ivch_save(struct intel_dvo_device *dvo) 408static void ivch_save(struct intel_dvo_device *dvo)
diff --git a/drivers/gpu/drm/i915/dvo_sil164.c b/drivers/gpu/drm/i915/dvo_sil164.c
index e1c1f7341e5c..0001c13f0a80 100644
--- a/drivers/gpu/drm/i915/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/dvo_sil164.c
@@ -105,7 +105,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
105 }; 105 };
106 106
107 if (!sil->quiet) { 107 if (!sil->quiet) {
108 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 108 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
109 addr, i2cbus->adapter.name, dvo->slave_addr); 109 addr, i2cbus->adapter.name, dvo->slave_addr);
110 } 110 }
111 return false; 111 return false;
@@ -131,7 +131,7 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
131 return true; 131 return true;
132 132
133 if (!sil->quiet) { 133 if (!sil->quiet) {
134 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 134 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
135 addr, i2cbus->adapter.name, dvo->slave_addr); 135 addr, i2cbus->adapter.name, dvo->slave_addr);
136 } 136 }
137 137
@@ -158,7 +158,7 @@ static bool sil164_init(struct intel_dvo_device *dvo,
158 goto out; 158 goto out;
159 159
160 if (ch != (SIL164_VID & 0xff)) { 160 if (ch != (SIL164_VID & 0xff)) {
161 DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", 161 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
162 ch, adapter->name, dvo->slave_addr); 162 ch, adapter->name, dvo->slave_addr);
163 goto out; 163 goto out;
164 } 164 }
@@ -167,13 +167,13 @@ static bool sil164_init(struct intel_dvo_device *dvo,
167 goto out; 167 goto out;
168 168
169 if (ch != (SIL164_DID & 0xff)) { 169 if (ch != (SIL164_DID & 0xff)) {
170 DRM_DEBUG("sil164 not detected got %d: from %s Slave %d.\n", 170 DRM_DEBUG_KMS("sil164 not detected got %d: from %s Slave %d.\n",
171 ch, adapter->name, dvo->slave_addr); 171 ch, adapter->name, dvo->slave_addr);
172 goto out; 172 goto out;
173 } 173 }
174 sil->quiet = false; 174 sil->quiet = false;
175 175
176 DRM_DEBUG("init sil164 dvo controller successfully!\n"); 176 DRM_DEBUG_KMS("init sil164 dvo controller successfully!\n");
177 return true; 177 return true;
178 178
179out: 179out:
@@ -241,15 +241,15 @@ static void sil164_dump_regs(struct intel_dvo_device *dvo)
241 uint8_t val; 241 uint8_t val;
242 242
243 sil164_readb(dvo, SIL164_FREQ_LO, &val); 243 sil164_readb(dvo, SIL164_FREQ_LO, &val);
244 DRM_DEBUG("SIL164_FREQ_LO: 0x%02x\n", val); 244 DRM_LOG_KMS("SIL164_FREQ_LO: 0x%02x\n", val);
245 sil164_readb(dvo, SIL164_FREQ_HI, &val); 245 sil164_readb(dvo, SIL164_FREQ_HI, &val);
246 DRM_DEBUG("SIL164_FREQ_HI: 0x%02x\n", val); 246 DRM_LOG_KMS("SIL164_FREQ_HI: 0x%02x\n", val);
247 sil164_readb(dvo, SIL164_REG8, &val); 247 sil164_readb(dvo, SIL164_REG8, &val);
248 DRM_DEBUG("SIL164_REG8: 0x%02x\n", val); 248 DRM_LOG_KMS("SIL164_REG8: 0x%02x\n", val);
249 sil164_readb(dvo, SIL164_REG9, &val); 249 sil164_readb(dvo, SIL164_REG9, &val);
250 DRM_DEBUG("SIL164_REG9: 0x%02x\n", val); 250 DRM_LOG_KMS("SIL164_REG9: 0x%02x\n", val);
251 sil164_readb(dvo, SIL164_REGC, &val); 251 sil164_readb(dvo, SIL164_REGC, &val);
252 DRM_DEBUG("SIL164_REGC: 0x%02x\n", val); 252 DRM_LOG_KMS("SIL164_REGC: 0x%02x\n", val);
253} 253}
254 254
255static void sil164_save(struct intel_dvo_device *dvo) 255static void sil164_save(struct intel_dvo_device *dvo)
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 9ecc907384ec..c7c391bc116a 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -130,7 +130,7 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
130 }; 130 };
131 131
132 if (!tfp->quiet) { 132 if (!tfp->quiet) {
133 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n", 133 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
134 addr, i2cbus->adapter.name, dvo->slave_addr); 134 addr, i2cbus->adapter.name, dvo->slave_addr);
135 } 135 }
136 return false; 136 return false;
@@ -156,7 +156,7 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
156 return true; 156 return true;
157 157
158 if (!tfp->quiet) { 158 if (!tfp->quiet) {
159 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n", 159 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
160 addr, i2cbus->adapter.name, dvo->slave_addr); 160 addr, i2cbus->adapter.name, dvo->slave_addr);
161 } 161 }
162 162
@@ -191,13 +191,15 @@ static bool tfp410_init(struct intel_dvo_device *dvo,
191 tfp->quiet = true; 191 tfp->quiet = true;
192 192
193 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) { 193 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
194 DRM_DEBUG("tfp410 not detected got VID %X: from %s Slave %d.\n", 194 DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
195 "Slave %d.\n",
195 id, adapter->name, dvo->slave_addr); 196 id, adapter->name, dvo->slave_addr);
196 goto out; 197 goto out;
197 } 198 }
198 199
199 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) { 200 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
200 DRM_DEBUG("tfp410 not detected got DID %X: from %s Slave %d.\n", 201 DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
202 "Slave %d.\n",
201 id, adapter->name, dvo->slave_addr); 203 id, adapter->name, dvo->slave_addr);
202 goto out; 204 goto out;
203 } 205 }
@@ -262,33 +264,33 @@ static void tfp410_dump_regs(struct intel_dvo_device *dvo)
262 uint8_t val, val2; 264 uint8_t val, val2;
263 265
264 tfp410_readb(dvo, TFP410_REV, &val); 266 tfp410_readb(dvo, TFP410_REV, &val);
265 DRM_DEBUG("TFP410_REV: 0x%02X\n", val); 267 DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
266 tfp410_readb(dvo, TFP410_CTL_1, &val); 268 tfp410_readb(dvo, TFP410_CTL_1, &val);
267 DRM_DEBUG("TFP410_CTL1: 0x%02X\n", val); 269 DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
268 tfp410_readb(dvo, TFP410_CTL_2, &val); 270 tfp410_readb(dvo, TFP410_CTL_2, &val);
269 DRM_DEBUG("TFP410_CTL2: 0x%02X\n", val); 271 DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
270 tfp410_readb(dvo, TFP410_CTL_3, &val); 272 tfp410_readb(dvo, TFP410_CTL_3, &val);
271 DRM_DEBUG("TFP410_CTL3: 0x%02X\n", val); 273 DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
272 tfp410_readb(dvo, TFP410_USERCFG, &val); 274 tfp410_readb(dvo, TFP410_USERCFG, &val);
273 DRM_DEBUG("TFP410_USERCFG: 0x%02X\n", val); 275 DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
274 tfp410_readb(dvo, TFP410_DE_DLY, &val); 276 tfp410_readb(dvo, TFP410_DE_DLY, &val);
275 DRM_DEBUG("TFP410_DE_DLY: 0x%02X\n", val); 277 DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
276 tfp410_readb(dvo, TFP410_DE_CTL, &val); 278 tfp410_readb(dvo, TFP410_DE_CTL, &val);
277 DRM_DEBUG("TFP410_DE_CTL: 0x%02X\n", val); 279 DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
278 tfp410_readb(dvo, TFP410_DE_TOP, &val); 280 tfp410_readb(dvo, TFP410_DE_TOP, &val);
279 DRM_DEBUG("TFP410_DE_TOP: 0x%02X\n", val); 281 DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
280 tfp410_readb(dvo, TFP410_DE_CNT_LO, &val); 282 tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
281 tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2); 283 tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
282 DRM_DEBUG("TFP410_DE_CNT: 0x%02X%02X\n", val2, val); 284 DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
283 tfp410_readb(dvo, TFP410_DE_LIN_LO, &val); 285 tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
284 tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2); 286 tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
285 DRM_DEBUG("TFP410_DE_LIN: 0x%02X%02X\n", val2, val); 287 DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
286 tfp410_readb(dvo, TFP410_H_RES_LO, &val); 288 tfp410_readb(dvo, TFP410_H_RES_LO, &val);
287 tfp410_readb(dvo, TFP410_H_RES_HI, &val2); 289 tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
288 DRM_DEBUG("TFP410_H_RES: 0x%02X%02X\n", val2, val); 290 DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
289 tfp410_readb(dvo, TFP410_V_RES_LO, &val); 291 tfp410_readb(dvo, TFP410_V_RES_LO, &val);
290 tfp410_readb(dvo, TFP410_V_RES_HI, &val2); 292 tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
291 DRM_DEBUG("TFP410_V_RES: 0x%02X%02X\n", val2, val); 293 DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
292} 294}
293 295
294static void tfp410_save(struct intel_dvo_device *dvo) 296static void tfp410_save(struct intel_dvo_device *dvo)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f8ce9a3a420d..d7aada51a3be 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -27,6 +27,7 @@
27 */ 27 */
28 28
29#include <linux/seq_file.h> 29#include <linux/seq_file.h>
30#include <linux/debugfs.h>
30#include "drmP.h" 31#include "drmP.h"
31#include "drm.h" 32#include "drm.h"
32#include "i915_drm.h" 33#include "i915_drm.h"
@@ -267,10 +268,10 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
267 uint32_t *mem; 268 uint32_t *mem;
268 269
269 for (page = 0; page < page_count; page++) { 270 for (page = 0; page < page_count; page++) {
270 mem = kmap(pages[page]); 271 mem = kmap_atomic(pages[page], KM_USER0);
271 for (i = 0; i < PAGE_SIZE; i += 4) 272 for (i = 0; i < PAGE_SIZE; i += 4)
272 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); 273 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
273 kunmap(pages[page]); 274 kunmap_atomic(pages[page], KM_USER0);
274 } 275 }
275} 276}
276 277
@@ -412,6 +413,109 @@ static int i915_registers_info(struct seq_file *m, void *data) {
412 return 0; 413 return 0;
413} 414}
414 415
416static int
417i915_wedged_open(struct inode *inode,
418 struct file *filp)
419{
420 filp->private_data = inode->i_private;
421 return 0;
422}
423
424static ssize_t
425i915_wedged_read(struct file *filp,
426 char __user *ubuf,
427 size_t max,
428 loff_t *ppos)
429{
430 struct drm_device *dev = filp->private_data;
431 drm_i915_private_t *dev_priv = dev->dev_private;
432 char buf[80];
433 int len;
434
435 len = snprintf(buf, sizeof (buf),
436 "wedged : %d\n",
437 atomic_read(&dev_priv->mm.wedged));
438
439 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
440}
441
442static ssize_t
443i915_wedged_write(struct file *filp,
444 const char __user *ubuf,
445 size_t cnt,
446 loff_t *ppos)
447{
448 struct drm_device *dev = filp->private_data;
449 drm_i915_private_t *dev_priv = dev->dev_private;
450 char buf[20];
451 int val = 1;
452
453 if (cnt > 0) {
454 if (cnt > sizeof (buf) - 1)
455 return -EINVAL;
456
457 if (copy_from_user(buf, ubuf, cnt))
458 return -EFAULT;
459 buf[cnt] = 0;
460
461 val = simple_strtoul(buf, NULL, 0);
462 }
463
464 DRM_INFO("Manually setting wedged to %d\n", val);
465
466 atomic_set(&dev_priv->mm.wedged, val);
467 if (val) {
468 DRM_WAKEUP(&dev_priv->irq_queue);
469 queue_work(dev_priv->wq, &dev_priv->error_work);
470 }
471
472 return cnt;
473}
474
475static const struct file_operations i915_wedged_fops = {
476 .owner = THIS_MODULE,
477 .open = i915_wedged_open,
478 .read = i915_wedged_read,
479 .write = i915_wedged_write,
480};
481
482/* As the drm_debugfs_init() routines are called before dev->dev_private is
483 * allocated we need to hook into the minor for release. */
484static int
485drm_add_fake_info_node(struct drm_minor *minor,
486 struct dentry *ent,
487 const void *key)
488{
489 struct drm_info_node *node;
490
491 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
492 if (node == NULL) {
493 debugfs_remove(ent);
494 return -ENOMEM;
495 }
496
497 node->minor = minor;
498 node->dent = ent;
499 node->info_ent = (void *) key;
500 list_add(&node->list, &minor->debugfs_nodes.list);
501
502 return 0;
503}
504
505static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
506{
507 struct drm_device *dev = minor->dev;
508 struct dentry *ent;
509
510 ent = debugfs_create_file("i915_wedged",
511 S_IRUGO | S_IWUSR,
512 root, dev,
513 &i915_wedged_fops);
514 if (IS_ERR(ent))
515 return PTR_ERR(ent);
516
517 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
518}
415 519
416static struct drm_info_list i915_debugfs_list[] = { 520static struct drm_info_list i915_debugfs_list[] = {
417 {"i915_regs", i915_registers_info, 0}, 521 {"i915_regs", i915_registers_info, 0},
@@ -432,6 +536,12 @@ static struct drm_info_list i915_debugfs_list[] = {
432 536
433int i915_debugfs_init(struct drm_minor *minor) 537int i915_debugfs_init(struct drm_minor *minor)
434{ 538{
539 int ret;
540
541 ret = i915_wedged_create(minor->debugfs_root, minor);
542 if (ret)
543 return ret;
544
435 return drm_debugfs_create_files(i915_debugfs_list, 545 return drm_debugfs_create_files(i915_debugfs_list,
436 I915_DEBUGFS_ENTRIES, 546 I915_DEBUGFS_ENTRIES,
437 minor->debugfs_root, minor); 547 minor->debugfs_root, minor);
@@ -441,7 +551,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
441{ 551{
442 drm_debugfs_remove_files(i915_debugfs_list, 552 drm_debugfs_remove_files(i915_debugfs_list,
443 I915_DEBUGFS_ENTRIES, minor); 553 I915_DEBUGFS_ENTRIES, minor);
554 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
555 1, minor);
444} 556}
445 557
446#endif /* CONFIG_DEBUG_FS */ 558#endif /* CONFIG_DEBUG_FS */
447
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e5b138be45fa..a8efe78e5c57 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -807,6 +807,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
807 case I915_PARAM_NUM_FENCES_AVAIL: 807 case I915_PARAM_NUM_FENCES_AVAIL:
808 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 808 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
809 break; 809 break;
810 case I915_PARAM_HAS_OVERLAY:
811 value = dev_priv->overlay ? 1 : 0;
812 break;
810 default: 813 default:
811 DRM_DEBUG_DRIVER("Unknown parameter %d\n", 814 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
812 param->param); 815 param->param);
@@ -1070,7 +1073,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1070 1073
1071 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024)); 1074 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1072 1075
1073 DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); 1076 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1074 1077
1075 /* Mask out these reserved bits on this hardware. */ 1078 /* Mask out these reserved bits on this hardware. */
1076 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || 1079 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
@@ -1096,7 +1099,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1096 phys =(entry & PTE_ADDRESS_MASK) | 1099 phys =(entry & PTE_ADDRESS_MASK) |
1097 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4)); 1100 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1098 1101
1099 DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys); 1102 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1100 1103
1101 return phys; 1104 return phys;
1102} 1105}
@@ -1413,7 +1416,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1413 if (ret) 1416 if (ret)
1414 goto out_iomapfree; 1417 goto out_iomapfree;
1415 1418
1416 dev_priv->wq = create_workqueue("i915"); 1419 dev_priv->wq = create_singlethread_workqueue("i915");
1417 if (dev_priv->wq == NULL) { 1420 if (dev_priv->wq == NULL) {
1418 DRM_ERROR("Failed to create our workqueue.\n"); 1421 DRM_ERROR("Failed to create our workqueue.\n");
1419 ret = -ENOMEM; 1422 ret = -ENOMEM;
@@ -1489,9 +1492,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1489 } 1492 }
1490 1493
1491 /* Must be done after probing outputs */ 1494 /* Must be done after probing outputs */
1492 /* FIXME: verify on IGDNG */ 1495 intel_opregion_init(dev, 0);
1493 if (!IS_IGDNG(dev))
1494 intel_opregion_init(dev, 0);
1495 1496
1496 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, 1497 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1497 (unsigned long) dev); 1498 (unsigned long) dev);
@@ -1525,6 +1526,15 @@ int i915_driver_unload(struct drm_device *dev)
1525 } 1526 }
1526 1527
1527 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1528 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1529 /*
1530 * free the memory space allocated for the child device
1531 * config parsed from VBT
1532 */
1533 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1534 kfree(dev_priv->child_dev);
1535 dev_priv->child_dev = NULL;
1536 dev_priv->child_dev_num = 0;
1537 }
1528 drm_irq_uninstall(dev); 1538 drm_irq_uninstall(dev);
1529 vga_client_register(dev->pdev, NULL, NULL, NULL); 1539 vga_client_register(dev->pdev, NULL, NULL, NULL);
1530 } 1540 }
@@ -1535,8 +1545,7 @@ int i915_driver_unload(struct drm_device *dev)
1535 if (dev_priv->regs != NULL) 1545 if (dev_priv->regs != NULL)
1536 iounmap(dev_priv->regs); 1546 iounmap(dev_priv->regs);
1537 1547
1538 if (!IS_IGDNG(dev)) 1548 intel_opregion_free(dev, 0);
1539 intel_opregion_free(dev, 0);
1540 1549
1541 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1550 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1542 intel_modeset_cleanup(dev); 1551 intel_modeset_cleanup(dev);
@@ -1548,6 +1557,8 @@ int i915_driver_unload(struct drm_device *dev)
1548 mutex_unlock(&dev->struct_mutex); 1557 mutex_unlock(&dev->struct_mutex);
1549 drm_mm_takedown(&dev_priv->vram); 1558 drm_mm_takedown(&dev_priv->vram);
1550 i915_gem_lastclose(dev); 1559 i915_gem_lastclose(dev);
1560
1561 intel_cleanup_overlay(dev);
1551 } 1562 }
1552 1563
1553 pci_dev_put(dev_priv->bridge_dev); 1564 pci_dev_put(dev_priv->bridge_dev);
@@ -1656,6 +1667,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
1656 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0), 1667 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1657 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), 1668 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1658 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0), 1669 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1670 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1671 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1659}; 1672};
1660 1673
1661int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1674int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57204e298975..450dcf0d25c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -170,6 +170,8 @@ struct drm_i915_display_funcs {
170 /* clock gating init */ 170 /* clock gating init */
171}; 171};
172 172
173struct intel_overlay;
174
173typedef struct drm_i915_private { 175typedef struct drm_i915_private {
174 struct drm_device *dev; 176 struct drm_device *dev;
175 177
@@ -187,6 +189,7 @@ typedef struct drm_i915_private {
187 unsigned int status_gfx_addr; 189 unsigned int status_gfx_addr;
188 drm_local_map_t hws_map; 190 drm_local_map_t hws_map;
189 struct drm_gem_object *hws_obj; 191 struct drm_gem_object *hws_obj;
192 struct drm_gem_object *pwrctx;
190 193
191 struct resource mch_res; 194 struct resource mch_res;
192 195
@@ -211,6 +214,8 @@ typedef struct drm_i915_private {
211 u32 gt_irq_mask_reg; 214 u32 gt_irq_mask_reg;
212 u32 gt_irq_enable_reg; 215 u32 gt_irq_enable_reg;
213 u32 de_irq_enable_reg; 216 u32 de_irq_enable_reg;
217 u32 pch_irq_mask_reg;
218 u32 pch_irq_enable_reg;
214 219
215 u32 hotplug_supported_mask; 220 u32 hotplug_supported_mask;
216 struct work_struct hotplug_work; 221 struct work_struct hotplug_work;
@@ -240,6 +245,9 @@ typedef struct drm_i915_private {
240 245
241 struct intel_opregion opregion; 246 struct intel_opregion opregion;
242 247
248 /* overlay */
249 struct intel_overlay *overlay;
250
243 /* LVDS info */ 251 /* LVDS info */
244 int backlight_duty_cycle; /* restore backlight to this value */ 252 int backlight_duty_cycle; /* restore backlight to this value */
245 bool panel_wants_dither; 253 bool panel_wants_dither;
@@ -258,7 +266,7 @@ typedef struct drm_i915_private {
258 266
259 struct notifier_block lid_notifier; 267 struct notifier_block lid_notifier;
260 268
261 int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */ 269 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
262 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 270 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
263 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 271 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
264 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 272 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
@@ -280,6 +288,7 @@ typedef struct drm_i915_private {
280 u32 saveDSPBCNTR; 288 u32 saveDSPBCNTR;
281 u32 saveDSPARB; 289 u32 saveDSPARB;
282 u32 saveRENDERSTANDBY; 290 u32 saveRENDERSTANDBY;
291 u32 savePWRCTXA;
283 u32 saveHWS; 292 u32 saveHWS;
284 u32 savePIPEACONF; 293 u32 savePIPEACONF;
285 u32 savePIPEBCONF; 294 u32 savePIPEBCONF;
@@ -530,10 +539,14 @@ typedef struct drm_i915_private {
530 /* Reclocking support */ 539 /* Reclocking support */
531 bool render_reclock_avail; 540 bool render_reclock_avail;
532 bool lvds_downclock_avail; 541 bool lvds_downclock_avail;
542 /* indicates the reduced downclock for LVDS*/
543 int lvds_downclock;
533 struct work_struct idle_work; 544 struct work_struct idle_work;
534 struct timer_list idle_timer; 545 struct timer_list idle_timer;
535 bool busy; 546 bool busy;
536 u16 orig_clock; 547 u16 orig_clock;
548 int child_dev_num;
549 struct child_device_config *child_dev;
537} drm_i915_private_t; 550} drm_i915_private_t;
538 551
539/** driver private structure attached to each drm_gem_object */ 552/** driver private structure attached to each drm_gem_object */
@@ -726,6 +739,8 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
726void 739void
727i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 740i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
728 741
742void intel_enable_asle (struct drm_device *dev);
743
729 744
730/* i915_mem.c */ 745/* i915_mem.c */
731extern int i915_mem_alloc(struct drm_device *dev, void *data, 746extern int i915_mem_alloc(struct drm_device *dev, void *data,
@@ -801,6 +816,9 @@ void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
801int i915_gem_do_init(struct drm_device *dev, unsigned long start, 816int i915_gem_do_init(struct drm_device *dev, unsigned long start,
802 unsigned long end); 817 unsigned long end);
803int i915_gem_idle(struct drm_device *dev); 818int i915_gem_idle(struct drm_device *dev);
819uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
820 uint32_t flush_domains);
821int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
804int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 822int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
805int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 823int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
806 int write); 824 int write);
@@ -851,11 +869,13 @@ extern int i915_restore_state(struct drm_device *dev);
851extern int intel_opregion_init(struct drm_device *dev, int resume); 869extern int intel_opregion_init(struct drm_device *dev, int resume);
852extern void intel_opregion_free(struct drm_device *dev, int suspend); 870extern void intel_opregion_free(struct drm_device *dev, int suspend);
853extern void opregion_asle_intr(struct drm_device *dev); 871extern void opregion_asle_intr(struct drm_device *dev);
872extern void ironlake_opregion_gse_intr(struct drm_device *dev);
854extern void opregion_enable_asle(struct drm_device *dev); 873extern void opregion_enable_asle(struct drm_device *dev);
855#else 874#else
856static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } 875static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
857static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } 876static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
858static inline void opregion_asle_intr(struct drm_device *dev) { return; } 877static inline void opregion_asle_intr(struct drm_device *dev) { return; }
878static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
859static inline void opregion_enable_asle(struct drm_device *dev) { return; } 879static inline void opregion_enable_asle(struct drm_device *dev) { return; }
860#endif 880#endif
861 881
@@ -943,8 +963,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
943#define IS_I830(dev) ((dev)->pci_device == 0x3577) 963#define IS_I830(dev) ((dev)->pci_device == 0x3577)
944#define IS_845G(dev) ((dev)->pci_device == 0x2562) 964#define IS_845G(dev) ((dev)->pci_device == 0x2562)
945#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 965#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
946#define IS_I855(dev) ((dev)->pci_device == 0x3582)
947#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 966#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
967#define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
948 968
949#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 969#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
950#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 970#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
@@ -1006,9 +1026,12 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1006 */ 1026 */
1007#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1027#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1008 IS_I915GM(dev))) 1028 IS_I915GM(dev)))
1029#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_IGD(dev))
1009#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1030#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1010#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1031#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1011#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev)) 1032#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
1033#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1034 !IS_IGDNG(dev) && !IS_IGD(dev))
1012#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev)) 1035#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1013/* dsparb controlled by hw only */ 1036/* dsparb controlled by hw only */
1014#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1037#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
@@ -1019,6 +1042,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1019 (IS_I9XX(dev) || IS_GM45(dev)) && \ 1042 (IS_I9XX(dev) || IS_GM45(dev)) && \
1020 !IS_IGD(dev) && \ 1043 !IS_IGD(dev) && \
1021 !IS_IGDNG(dev)) 1044 !IS_IGDNG(dev))
1045#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IGDNG_M(dev))
1022 1046
1023#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1047#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1024 1048
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index abfc27b0c2ea..481c0ab888c8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1583,7 +1583,7 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1583 * 1583 *
1584 * Returned sequence numbers are nonzero on success. 1584 * Returned sequence numbers are nonzero on success.
1585 */ 1585 */
1586static uint32_t 1586uint32_t
1587i915_add_request(struct drm_device *dev, struct drm_file *file_priv, 1587i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1588 uint32_t flush_domains) 1588 uint32_t flush_domains)
1589{ 1589{
@@ -1617,7 +1617,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1617 OUT_RING(MI_USER_INTERRUPT); 1617 OUT_RING(MI_USER_INTERRUPT);
1618 ADVANCE_LP_RING(); 1618 ADVANCE_LP_RING();
1619 1619
1620 DRM_DEBUG("%d\n", seqno); 1620 DRM_DEBUG_DRIVER("%d\n", seqno);
1621 1621
1622 request->seqno = seqno; 1622 request->seqno = seqno;
1623 request->emitted_jiffies = jiffies; 1623 request->emitted_jiffies = jiffies;
@@ -1820,12 +1820,8 @@ i915_gem_retire_work_handler(struct work_struct *work)
1820 mutex_unlock(&dev->struct_mutex); 1820 mutex_unlock(&dev->struct_mutex);
1821} 1821}
1822 1822
1823/** 1823int
1824 * Waits for a sequence number to be signaled, and cleans up the 1824i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1825 * request and object lists appropriately for that event.
1826 */
1827static int
1828i915_wait_request(struct drm_device *dev, uint32_t seqno)
1829{ 1825{
1830 drm_i915_private_t *dev_priv = dev->dev_private; 1826 drm_i915_private_t *dev_priv = dev->dev_private;
1831 u32 ier; 1827 u32 ier;
@@ -1852,10 +1848,15 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
1852 1848
1853 dev_priv->mm.waiting_gem_seqno = seqno; 1849 dev_priv->mm.waiting_gem_seqno = seqno;
1854 i915_user_irq_get(dev); 1850 i915_user_irq_get(dev);
1855 ret = wait_event_interruptible(dev_priv->irq_queue, 1851 if (interruptible)
1856 i915_seqno_passed(i915_get_gem_seqno(dev), 1852 ret = wait_event_interruptible(dev_priv->irq_queue,
1857 seqno) || 1853 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1858 atomic_read(&dev_priv->mm.wedged)); 1854 atomic_read(&dev_priv->mm.wedged));
1855 else
1856 wait_event(dev_priv->irq_queue,
1857 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1858 atomic_read(&dev_priv->mm.wedged));
1859
1859 i915_user_irq_put(dev); 1860 i915_user_irq_put(dev);
1860 dev_priv->mm.waiting_gem_seqno = 0; 1861 dev_priv->mm.waiting_gem_seqno = 0;
1861 1862
@@ -1879,6 +1880,16 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
1879 return ret; 1880 return ret;
1880} 1881}
1881 1882
1883/**
1884 * Waits for a sequence number to be signaled, and cleans up the
1885 * request and object lists appropriately for that event.
1886 */
1887static int
1888i915_wait_request(struct drm_device *dev, uint32_t seqno)
1889{
1890 return i915_do_wait_request(dev, seqno, 1);
1891}
1892
1882static void 1893static void
1883i915_gem_flush(struct drm_device *dev, 1894i915_gem_flush(struct drm_device *dev,
1884 uint32_t invalidate_domains, 1895 uint32_t invalidate_domains,
@@ -1947,7 +1958,7 @@ i915_gem_flush(struct drm_device *dev,
1947#endif 1958#endif
1948 BEGIN_LP_RING(2); 1959 BEGIN_LP_RING(2);
1949 OUT_RING(cmd); 1960 OUT_RING(cmd);
1950 OUT_RING(0); /* noop */ 1961 OUT_RING(MI_NOOP);
1951 ADVANCE_LP_RING(); 1962 ADVANCE_LP_RING();
1952 } 1963 }
1953} 1964}
@@ -3552,8 +3563,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3552 return -EINVAL; 3563 return -EINVAL;
3553 } 3564 }
3554 /* Copy in the exec list from userland */ 3565 /* Copy in the exec list from userland */
3555 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count); 3566 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3556 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count); 3567 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3557 if (exec_list == NULL || object_list == NULL) { 3568 if (exec_list == NULL || object_list == NULL) {
3558 DRM_ERROR("Failed to allocate exec or object list " 3569 DRM_ERROR("Failed to allocate exec or object list "
3559 "for %d buffers\n", 3570 "for %d buffers\n",
@@ -4356,7 +4367,7 @@ i915_gem_init_hws(struct drm_device *dev)
4356 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 4367 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4357 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 4368 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4358 I915_READ(HWS_PGA); /* posting read */ 4369 I915_READ(HWS_PGA); /* posting read */
4359 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); 4370 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4360 4371
4361 return 0; 4372 return 0;
4362} 4373}
@@ -4790,7 +4801,7 @@ i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4790 user_data = (char __user *) (uintptr_t) args->data_ptr; 4801 user_data = (char __user *) (uintptr_t) args->data_ptr;
4791 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; 4802 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4792 4803
4793 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size); 4804 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4794 ret = copy_from_user(obj_addr, user_data, args->size); 4805 ret = copy_from_user(obj_addr, user_data, args->size);
4795 if (ret) 4806 if (ret)
4796 return -EFAULT; 4807 return -EFAULT;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 200e398453ca..0c8df96a1ef8 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -121,7 +121,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
121 0, pcibios_align_resource, 121 0, pcibios_align_resource,
122 dev_priv->bridge_dev); 122 dev_priv->bridge_dev);
123 if (ret) { 123 if (ret) {
124 DRM_DEBUG("failed bus alloc: %d\n", ret); 124 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
125 dev_priv->mch_res.start = 0; 125 dev_priv->mch_res.start = 0;
126 goto out; 126 goto out;
127 } 127 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c3ceffa46ea0..77bc1d28f744 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -157,6 +157,20 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
157} 157}
158 158
159/** 159/**
160 * intel_enable_asle - enable ASLE interrupt for OpRegion
161 */
162void intel_enable_asle (struct drm_device *dev)
163{
164 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
165
166 if (IS_IGDNG(dev))
167 igdng_enable_display_irq(dev_priv, DE_GSE);
168 else
169 i915_enable_pipestat(dev_priv, 1,
170 I915_LEGACY_BLC_EVENT_ENABLE);
171}
172
173/**
160 * i915_pipe_enabled - check if a pipe is enabled 174 * i915_pipe_enabled - check if a pipe is enabled
161 * @dev: DRM device 175 * @dev: DRM device
162 * @pipe: pipe to check 176 * @pipe: pipe to check
@@ -191,7 +205,8 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
191 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 205 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
192 206
193 if (!i915_pipe_enabled(dev, pipe)) { 207 if (!i915_pipe_enabled(dev, pipe)) {
194 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 208 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
209 "pipe %d\n", pipe);
195 return 0; 210 return 0;
196 } 211 }
197 212
@@ -220,7 +235,8 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
220 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 235 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
221 236
222 if (!i915_pipe_enabled(dev, pipe)) { 237 if (!i915_pipe_enabled(dev, pipe)) {
223 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 238 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
239 "pipe %d\n", pipe);
224 return 0; 240 return 0;
225 } 241 }
226 242
@@ -254,19 +270,24 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
254{ 270{
255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 271 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
256 int ret = IRQ_NONE; 272 int ret = IRQ_NONE;
257 u32 de_iir, gt_iir; 273 u32 de_iir, gt_iir, pch_iir;
258 u32 new_de_iir, new_gt_iir; 274 u32 new_de_iir, new_gt_iir, new_pch_iir;
259 struct drm_i915_master_private *master_priv; 275 struct drm_i915_master_private *master_priv;
260 276
261 de_iir = I915_READ(DEIIR); 277 de_iir = I915_READ(DEIIR);
262 gt_iir = I915_READ(GTIIR); 278 gt_iir = I915_READ(GTIIR);
279 pch_iir = I915_READ(SDEIIR);
263 280
264 for (;;) { 281 for (;;) {
265 if (de_iir == 0 && gt_iir == 0) 282 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
266 break; 283 break;
267 284
268 ret = IRQ_HANDLED; 285 ret = IRQ_HANDLED;
269 286
287 /* should clear PCH hotplug event before clear CPU irq */
288 I915_WRITE(SDEIIR, pch_iir);
289 new_pch_iir = I915_READ(SDEIIR);
290
270 I915_WRITE(DEIIR, de_iir); 291 I915_WRITE(DEIIR, de_iir);
271 new_de_iir = I915_READ(DEIIR); 292 new_de_iir = I915_READ(DEIIR);
272 I915_WRITE(GTIIR, gt_iir); 293 I915_WRITE(GTIIR, gt_iir);
@@ -286,8 +307,18 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
286 DRM_WAKEUP(&dev_priv->irq_queue); 307 DRM_WAKEUP(&dev_priv->irq_queue);
287 } 308 }
288 309
310 if (de_iir & DE_GSE)
311 ironlake_opregion_gse_intr(dev);
312
313 /* check event from PCH */
314 if ((de_iir & DE_PCH_EVENT) &&
315 (pch_iir & SDE_HOTPLUG_MASK)) {
316 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
317 }
318
289 de_iir = new_de_iir; 319 de_iir = new_de_iir;
290 gt_iir = new_gt_iir; 320 gt_iir = new_gt_iir;
321 pch_iir = new_pch_iir;
291 } 322 }
292 323
293 return ret; 324 return ret;
@@ -309,19 +340,19 @@ static void i915_error_work_func(struct work_struct *work)
309 char *reset_event[] = { "RESET=1", NULL }; 340 char *reset_event[] = { "RESET=1", NULL };
310 char *reset_done_event[] = { "ERROR=0", NULL }; 341 char *reset_done_event[] = { "ERROR=0", NULL };
311 342
312 DRM_DEBUG("generating error event\n"); 343 DRM_DEBUG_DRIVER("generating error event\n");
313 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); 344 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
314 345
315 if (atomic_read(&dev_priv->mm.wedged)) { 346 if (atomic_read(&dev_priv->mm.wedged)) {
316 if (IS_I965G(dev)) { 347 if (IS_I965G(dev)) {
317 DRM_DEBUG("resetting chip\n"); 348 DRM_DEBUG_DRIVER("resetting chip\n");
318 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 349 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
319 if (!i965_reset(dev, GDRST_RENDER)) { 350 if (!i965_reset(dev, GDRST_RENDER)) {
320 atomic_set(&dev_priv->mm.wedged, 0); 351 atomic_set(&dev_priv->mm.wedged, 0);
321 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 352 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
322 } 353 }
323 } else { 354 } else {
324 printk("reboot required\n"); 355 DRM_DEBUG_DRIVER("reboot required\n");
325 } 356 }
326 } 357 }
327} 358}
@@ -347,7 +378,7 @@ static void i915_capture_error_state(struct drm_device *dev)
347 378
348 error = kmalloc(sizeof(*error), GFP_ATOMIC); 379 error = kmalloc(sizeof(*error), GFP_ATOMIC);
349 if (!error) { 380 if (!error) {
350 DRM_DEBUG("out ot memory, not capturing error state\n"); 381 DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n");
351 goto out; 382 goto out;
352 } 383 }
353 384
@@ -560,14 +591,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
560 */ 591 */
561 if (pipea_stats & 0x8000ffff) { 592 if (pipea_stats & 0x8000ffff) {
562 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) 593 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
563 DRM_DEBUG("pipe a underrun\n"); 594 DRM_DEBUG_DRIVER("pipe a underrun\n");
564 I915_WRITE(PIPEASTAT, pipea_stats); 595 I915_WRITE(PIPEASTAT, pipea_stats);
565 irq_received = 1; 596 irq_received = 1;
566 } 597 }
567 598
568 if (pipeb_stats & 0x8000ffff) { 599 if (pipeb_stats & 0x8000ffff) {
569 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) 600 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
570 DRM_DEBUG("pipe b underrun\n"); 601 DRM_DEBUG_DRIVER("pipe b underrun\n");
571 I915_WRITE(PIPEBSTAT, pipeb_stats); 602 I915_WRITE(PIPEBSTAT, pipeb_stats);
572 irq_received = 1; 603 irq_received = 1;
573 } 604 }
@@ -583,7 +614,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
583 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 614 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
584 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 615 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
585 616
586 DRM_DEBUG("hotplug event received, stat 0x%08x\n", 617 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
587 hotplug_status); 618 hotplug_status);
588 if (hotplug_status & dev_priv->hotplug_supported_mask) 619 if (hotplug_status & dev_priv->hotplug_supported_mask)
589 queue_work(dev_priv->wq, 620 queue_work(dev_priv->wq,
@@ -591,27 +622,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
591 622
592 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 623 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
593 I915_READ(PORT_HOTPLUG_STAT); 624 I915_READ(PORT_HOTPLUG_STAT);
594
595 /* EOS interrupts occurs */
596 if (IS_IGD(dev) &&
597 (hotplug_status & CRT_EOS_INT_STATUS)) {
598 u32 temp;
599
600 DRM_DEBUG("EOS interrupt occurs\n");
601 /* status is already cleared */
602 temp = I915_READ(ADPA);
603 temp &= ~ADPA_DAC_ENABLE;
604 I915_WRITE(ADPA, temp);
605
606 temp = I915_READ(PORT_HOTPLUG_EN);
607 temp &= ~CRT_EOS_INT_EN;
608 I915_WRITE(PORT_HOTPLUG_EN, temp);
609
610 temp = I915_READ(PORT_HOTPLUG_STAT);
611 if (temp & CRT_EOS_INT_STATUS)
612 I915_WRITE(PORT_HOTPLUG_STAT,
613 CRT_EOS_INT_STATUS);
614 }
615 } 625 }
616 626
617 I915_WRITE(IIR, iir); 627 I915_WRITE(IIR, iir);
@@ -676,7 +686,7 @@ static int i915_emit_irq(struct drm_device * dev)
676 686
677 i915_kernel_lost_context(dev); 687 i915_kernel_lost_context(dev);
678 688
679 DRM_DEBUG("\n"); 689 DRM_DEBUG_DRIVER("\n");
680 690
681 dev_priv->counter++; 691 dev_priv->counter++;
682 if (dev_priv->counter > 0x7FFFFFFFUL) 692 if (dev_priv->counter > 0x7FFFFFFFUL)
@@ -741,7 +751,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
741 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 751 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
742 int ret = 0; 752 int ret = 0;
743 753
744 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, 754 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
745 READ_BREADCRUMB(dev_priv)); 755 READ_BREADCRUMB(dev_priv));
746 756
747 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 757 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
@@ -984,14 +994,21 @@ static void igdng_irq_preinstall(struct drm_device *dev)
984 I915_WRITE(GTIMR, 0xffffffff); 994 I915_WRITE(GTIMR, 0xffffffff);
985 I915_WRITE(GTIER, 0x0); 995 I915_WRITE(GTIER, 0x0);
986 (void) I915_READ(GTIER); 996 (void) I915_READ(GTIER);
997
998 /* south display irq */
999 I915_WRITE(SDEIMR, 0xffffffff);
1000 I915_WRITE(SDEIER, 0x0);
1001 (void) I915_READ(SDEIER);
987} 1002}
988 1003
989static int igdng_irq_postinstall(struct drm_device *dev) 1004static int igdng_irq_postinstall(struct drm_device *dev)
990{ 1005{
991 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1006 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
992 /* enable kind of interrupts always enabled */ 1007 /* enable kind of interrupts always enabled */
993 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; 1008 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
994 u32 render_mask = GT_USER_INTERRUPT; 1009 u32 render_mask = GT_USER_INTERRUPT;
1010 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1011 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
995 1012
996 dev_priv->irq_mask_reg = ~display_mask; 1013 dev_priv->irq_mask_reg = ~display_mask;
997 dev_priv->de_irq_enable_reg = display_mask; 1014 dev_priv->de_irq_enable_reg = display_mask;
@@ -1011,6 +1028,14 @@ static int igdng_irq_postinstall(struct drm_device *dev)
1011 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); 1028 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1012 (void) I915_READ(GTIER); 1029 (void) I915_READ(GTIER);
1013 1030
1031 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1032 dev_priv->pch_irq_enable_reg = hotplug_mask;
1033
1034 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1035 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1036 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1037 (void) I915_READ(SDEIER);
1038
1014 return 0; 1039 return 0;
1015} 1040}
1016 1041
diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
index 2d5193556d3f..313a1a11afab 100644
--- a/drivers/gpu/drm/i915/i915_opregion.c
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -118,6 +118,10 @@ struct opregion_asle {
118#define ASLE_BACKLIGHT_FAIL (2<<12) 118#define ASLE_BACKLIGHT_FAIL (2<<12)
119#define ASLE_PFIT_FAIL (2<<14) 119#define ASLE_PFIT_FAIL (2<<14)
120#define ASLE_PWM_FREQ_FAIL (2<<16) 120#define ASLE_PWM_FREQ_FAIL (2<<16)
121#define ASLE_ALS_ILLUM_FAILED (1<<10)
122#define ASLE_BACKLIGHT_FAILED (1<<12)
123#define ASLE_PFIT_FAILED (1<<14)
124#define ASLE_PWM_FREQ_FAILED (1<<16)
121 125
122/* ASLE backlight brightness to set */ 126/* ASLE backlight brightness to set */
123#define ASLE_BCLP_VALID (1<<31) 127#define ASLE_BCLP_VALID (1<<31)
@@ -224,7 +228,7 @@ void opregion_asle_intr(struct drm_device *dev)
224 asle_req = asle->aslc & ASLE_REQ_MSK; 228 asle_req = asle->aslc & ASLE_REQ_MSK;
225 229
226 if (!asle_req) { 230 if (!asle_req) {
227 DRM_DEBUG("non asle set request??\n"); 231 DRM_DEBUG_DRIVER("non asle set request??\n");
228 return; 232 return;
229 } 233 }
230 234
@@ -243,6 +247,73 @@ void opregion_asle_intr(struct drm_device *dev)
243 asle->aslc = asle_stat; 247 asle->aslc = asle_stat;
244} 248}
245 249
250static u32 asle_set_backlight_ironlake(struct drm_device *dev, u32 bclp)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct opregion_asle *asle = dev_priv->opregion.asle;
254 u32 cpu_pwm_ctl, pch_pwm_ctl2;
255 u32 max_backlight, level;
256
257 if (!(bclp & ASLE_BCLP_VALID))
258 return ASLE_BACKLIGHT_FAILED;
259
260 bclp &= ASLE_BCLP_MSK;
261 if (bclp < 0 || bclp > 255)
262 return ASLE_BACKLIGHT_FAILED;
263
264 cpu_pwm_ctl = I915_READ(BLC_PWM_CPU_CTL);
265 pch_pwm_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
266 /* get the max PWM frequency */
267 max_backlight = (pch_pwm_ctl2 >> 16) & BACKLIGHT_DUTY_CYCLE_MASK;
268 /* calculate the expected PMW frequency */
269 level = (bclp * max_backlight) / 255;
270 /* reserve the high 16 bits */
271 cpu_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK);
272 /* write the updated PWM frequency */
273 I915_WRITE(BLC_PWM_CPU_CTL, cpu_pwm_ctl | level);
274
275 asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
276
277 return 0;
278}
279
280void ironlake_opregion_gse_intr(struct drm_device *dev)
281{
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 struct opregion_asle *asle = dev_priv->opregion.asle;
284 u32 asle_stat = 0;
285 u32 asle_req;
286
287 if (!asle)
288 return;
289
290 asle_req = asle->aslc & ASLE_REQ_MSK;
291
292 if (!asle_req) {
293 DRM_DEBUG_DRIVER("non asle set request??\n");
294 return;
295 }
296
297 if (asle_req & ASLE_SET_ALS_ILLUM) {
298 DRM_DEBUG_DRIVER("Illum is not supported\n");
299 asle_stat |= ASLE_ALS_ILLUM_FAILED;
300 }
301
302 if (asle_req & ASLE_SET_BACKLIGHT)
303 asle_stat |= asle_set_backlight_ironlake(dev, asle->bclp);
304
305 if (asle_req & ASLE_SET_PFIT) {
306 DRM_DEBUG_DRIVER("Pfit is not supported\n");
307 asle_stat |= ASLE_PFIT_FAILED;
308 }
309
310 if (asle_req & ASLE_SET_PWM_FREQ) {
311 DRM_DEBUG_DRIVER("PWM freq is not supported\n");
312 asle_stat |= ASLE_PWM_FREQ_FAILED;
313 }
314
315 asle->aslc = asle_stat;
316}
246#define ASLE_ALS_EN (1<<0) 317#define ASLE_ALS_EN (1<<0)
247#define ASLE_BLC_EN (1<<1) 318#define ASLE_BLC_EN (1<<1)
248#define ASLE_PFIT_EN (1<<2) 319#define ASLE_PFIT_EN (1<<2)
@@ -258,8 +329,7 @@ void opregion_enable_asle(struct drm_device *dev)
258 unsigned long irqflags; 329 unsigned long irqflags;
259 330
260 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 331 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
261 i915_enable_pipestat(dev_priv, 1, 332 intel_enable_asle(dev);
262 I915_LEGACY_BLC_EVENT_ENABLE);
263 spin_unlock_irqrestore(&dev_priv->user_irq_lock, 333 spin_unlock_irqrestore(&dev_priv->user_irq_lock,
264 irqflags); 334 irqflags);
265 } 335 }
@@ -361,9 +431,9 @@ int intel_opregion_init(struct drm_device *dev, int resume)
361 int err = 0; 431 int err = 0;
362 432
363 pci_read_config_dword(dev->pdev, PCI_ASLS, &asls); 433 pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
364 DRM_DEBUG("graphic opregion physical addr: 0x%x\n", asls); 434 DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);
365 if (asls == 0) { 435 if (asls == 0) {
366 DRM_DEBUG("ACPI OpRegion not supported!\n"); 436 DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n");
367 return -ENOTSUPP; 437 return -ENOTSUPP;
368 } 438 }
369 439
@@ -373,30 +443,30 @@ int intel_opregion_init(struct drm_device *dev, int resume)
373 443
374 opregion->header = base; 444 opregion->header = base;
375 if (memcmp(opregion->header->signature, OPREGION_SIGNATURE, 16)) { 445 if (memcmp(opregion->header->signature, OPREGION_SIGNATURE, 16)) {
376 DRM_DEBUG("opregion signature mismatch\n"); 446 DRM_DEBUG_DRIVER("opregion signature mismatch\n");
377 err = -EINVAL; 447 err = -EINVAL;
378 goto err_out; 448 goto err_out;
379 } 449 }
380 450
381 mboxes = opregion->header->mboxes; 451 mboxes = opregion->header->mboxes;
382 if (mboxes & MBOX_ACPI) { 452 if (mboxes & MBOX_ACPI) {
383 DRM_DEBUG("Public ACPI methods supported\n"); 453 DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
384 opregion->acpi = base + OPREGION_ACPI_OFFSET; 454 opregion->acpi = base + OPREGION_ACPI_OFFSET;
385 if (drm_core_check_feature(dev, DRIVER_MODESET)) 455 if (drm_core_check_feature(dev, DRIVER_MODESET))
386 intel_didl_outputs(dev); 456 intel_didl_outputs(dev);
387 } else { 457 } else {
388 DRM_DEBUG("Public ACPI methods not supported\n"); 458 DRM_DEBUG_DRIVER("Public ACPI methods not supported\n");
389 err = -ENOTSUPP; 459 err = -ENOTSUPP;
390 goto err_out; 460 goto err_out;
391 } 461 }
392 opregion->enabled = 1; 462 opregion->enabled = 1;
393 463
394 if (mboxes & MBOX_SWSCI) { 464 if (mboxes & MBOX_SWSCI) {
395 DRM_DEBUG("SWSCI supported\n"); 465 DRM_DEBUG_DRIVER("SWSCI supported\n");
396 opregion->swsci = base + OPREGION_SWSCI_OFFSET; 466 opregion->swsci = base + OPREGION_SWSCI_OFFSET;
397 } 467 }
398 if (mboxes & MBOX_ASLE) { 468 if (mboxes & MBOX_ASLE) {
399 DRM_DEBUG("ASLE supported\n"); 469 DRM_DEBUG_DRIVER("ASLE supported\n");
400 opregion->asle = base + OPREGION_ASLE_OFFSET; 470 opregion->asle = base + OPREGION_ASLE_OFFSET;
401 opregion_enable_asle(dev); 471 opregion_enable_asle(dev);
402 } 472 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1687edf68795..d58f7ad91161 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -140,6 +140,7 @@
140#define MI_NOOP MI_INSTR(0, 0) 140#define MI_NOOP MI_INSTR(0, 0)
141#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 141#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
142#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 142#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
143#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
143#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 144#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
144#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 145#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
145#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 146#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
@@ -151,6 +152,10 @@
151#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 152#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
152#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 153#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
153#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 154#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
155#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
156#define MI_OVERLAY_CONTINUE (0x0<<21)
157#define MI_OVERLAY_ON (0x1<<21)
158#define MI_OVERLAY_OFF (0x2<<21)
154#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 159#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
155#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 160#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
156#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 161#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
@@ -260,6 +265,8 @@
260#define HWS_PGA 0x02080 265#define HWS_PGA 0x02080
261#define HWS_ADDRESS_MASK 0xfffff000 266#define HWS_ADDRESS_MASK 0xfffff000
262#define HWS_START_ADDRESS_SHIFT 4 267#define HWS_START_ADDRESS_SHIFT 4
268#define PWRCTXA 0x2088 /* 965GM+ only */
269#define PWRCTX_EN (1<<0)
263#define IPEIR 0x02088 270#define IPEIR 0x02088
264#define IPEHR 0x0208c 271#define IPEHR 0x0208c
265#define INSTDONE 0x02090 272#define INSTDONE 0x02090
@@ -769,7 +776,8 @@
769 776
770/** GM965 GM45 render standby register */ 777/** GM965 GM45 render standby register */
771#define MCHBAR_RENDER_STANDBY 0x111B8 778#define MCHBAR_RENDER_STANDBY 0x111B8
772 779#define RCX_SW_EXIT (1<<23)
780#define RSX_STATUS_MASK 0x00700000
773#define PEG_BAND_GAP_DATA 0x14d68 781#define PEG_BAND_GAP_DATA 0x14d68
774 782
775/* 783/*
@@ -844,7 +852,6 @@
844#define SDVOB_HOTPLUG_INT_EN (1 << 26) 852#define SDVOB_HOTPLUG_INT_EN (1 << 26)
845#define SDVOC_HOTPLUG_INT_EN (1 << 25) 853#define SDVOC_HOTPLUG_INT_EN (1 << 25)
846#define TV_HOTPLUG_INT_EN (1 << 18) 854#define TV_HOTPLUG_INT_EN (1 << 18)
847#define CRT_EOS_INT_EN (1 << 10)
848#define CRT_HOTPLUG_INT_EN (1 << 9) 855#define CRT_HOTPLUG_INT_EN (1 << 9)
849#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 856#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
850#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 857#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
@@ -879,7 +886,6 @@
879#define DPC_HOTPLUG_INT_STATUS (1 << 28) 886#define DPC_HOTPLUG_INT_STATUS (1 << 28)
880#define HDMID_HOTPLUG_INT_STATUS (1 << 27) 887#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
881#define DPD_HOTPLUG_INT_STATUS (1 << 27) 888#define DPD_HOTPLUG_INT_STATUS (1 << 27)
882#define CRT_EOS_INT_STATUS (1 << 12)
883#define CRT_HOTPLUG_INT_STATUS (1 << 11) 889#define CRT_HOTPLUG_INT_STATUS (1 << 11)
884#define TV_HOTPLUG_INT_STATUS (1 << 10) 890#define TV_HOTPLUG_INT_STATUS (1 << 10)
885#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 891#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
@@ -1907,6 +1913,7 @@
1907#define DISPPLANE_16BPP (0x5<<26) 1913#define DISPPLANE_16BPP (0x5<<26)
1908#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1914#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1909#define DISPPLANE_32BPP (0x7<<26) 1915#define DISPPLANE_32BPP (0x7<<26)
1916#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
1910#define DISPPLANE_STEREO_ENABLE (1<<25) 1917#define DISPPLANE_STEREO_ENABLE (1<<25)
1911#define DISPPLANE_STEREO_DISABLE 0 1918#define DISPPLANE_STEREO_DISABLE 0
1912#define DISPPLANE_SEL_PIPE_MASK (1<<24) 1919#define DISPPLANE_SEL_PIPE_MASK (1<<24)
@@ -2117,6 +2124,7 @@
2117#define SDE_PORTC_HOTPLUG (1 << 9) 2124#define SDE_PORTC_HOTPLUG (1 << 9)
2118#define SDE_PORTB_HOTPLUG (1 << 8) 2125#define SDE_PORTB_HOTPLUG (1 << 8)
2119#define SDE_SDVOB_HOTPLUG (1 << 6) 2126#define SDE_SDVOB_HOTPLUG (1 << 6)
2127#define SDE_HOTPLUG_MASK (0xf << 8)
2120 2128
2121#define SDEISR 0xc4000 2129#define SDEISR 0xc4000
2122#define SDEIMR 0xc4004 2130#define SDEIMR 0xc4004
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 992d5617e798..cd10d9b8181f 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -699,8 +699,10 @@ int i915_save_state(struct drm_device *dev)
699 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 699 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
700 700
701 /* Render Standby */ 701 /* Render Standby */
702 if (IS_I965G(dev) && IS_MOBILE(dev)) 702 if (I915_HAS_RC6(dev)) {
703 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); 703 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
704 dev_priv->savePWRCTXA = I915_READ(PWRCTXA);
705 }
704 706
705 /* Hardware status page */ 707 /* Hardware status page */
706 dev_priv->saveHWS = I915_READ(HWS_PGA); 708 dev_priv->saveHWS = I915_READ(HWS_PGA);
@@ -762,8 +764,10 @@ int i915_restore_state(struct drm_device *dev)
762 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 764 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
763 765
764 /* Render Standby */ 766 /* Render Standby */
765 if (IS_I965G(dev) && IS_MOBILE(dev)) 767 if (I915_HAS_RC6(dev)) {
766 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); 768 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
769 I915_WRITE(PWRCTXA, dev_priv->savePWRCTXA);
770 }
767 771
768 /* Hardware status page */ 772 /* Hardware status page */
769 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 773 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 96cd256e60e6..73ceb36c790e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -114,6 +114,8 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
114 struct lvds_dvo_timing *dvo_timing; 114 struct lvds_dvo_timing *dvo_timing;
115 struct drm_display_mode *panel_fixed_mode; 115 struct drm_display_mode *panel_fixed_mode;
116 int lfp_data_size, dvo_timing_offset; 116 int lfp_data_size, dvo_timing_offset;
117 int i, temp_downclock;
118 struct drm_display_mode *temp_mode;
117 119
118 /* Defaults if we can't find VBT info */ 120 /* Defaults if we can't find VBT info */
119 dev_priv->lvds_dither = 0; 121 dev_priv->lvds_dither = 0;
@@ -159,9 +161,49 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
159 161
160 dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode; 162 dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
161 163
162 DRM_DEBUG("Found panel mode in BIOS VBT tables:\n"); 164 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
163 drm_mode_debug_printmodeline(panel_fixed_mode); 165 drm_mode_debug_printmodeline(panel_fixed_mode);
164 166
167 temp_mode = kzalloc(sizeof(*temp_mode), GFP_KERNEL);
168 temp_downclock = panel_fixed_mode->clock;
169 /*
170 * enumerate the LVDS panel timing info entry in VBT to check whether
171 * the LVDS downclock is found.
172 */
173 for (i = 0; i < 16; i++) {
174 entry = (struct bdb_lvds_lfp_data_entry *)
175 ((uint8_t *)lvds_lfp_data->data + (lfp_data_size * i));
176 dvo_timing = (struct lvds_dvo_timing *)
177 ((unsigned char *)entry + dvo_timing_offset);
178
179 fill_detail_timing_data(temp_mode, dvo_timing);
180
181 if (temp_mode->hdisplay == panel_fixed_mode->hdisplay &&
182 temp_mode->hsync_start == panel_fixed_mode->hsync_start &&
183 temp_mode->hsync_end == panel_fixed_mode->hsync_end &&
184 temp_mode->htotal == panel_fixed_mode->htotal &&
185 temp_mode->vdisplay == panel_fixed_mode->vdisplay &&
186 temp_mode->vsync_start == panel_fixed_mode->vsync_start &&
187 temp_mode->vsync_end == panel_fixed_mode->vsync_end &&
188 temp_mode->vtotal == panel_fixed_mode->vtotal &&
189 temp_mode->clock < temp_downclock) {
190 /*
191 * downclock is already found. But we expect
192 * to find the lower downclock.
193 */
194 temp_downclock = temp_mode->clock;
195 }
196 /* clear it to zero */
197 memset(temp_mode, 0, sizeof(*temp_mode));
198 }
199 kfree(temp_mode);
200 if (temp_downclock < panel_fixed_mode->clock) {
201 dev_priv->lvds_downclock_avail = 1;
202 dev_priv->lvds_downclock = temp_downclock;
203 DRM_DEBUG_KMS("LVDS downclock is found in VBT. ",
204 "Normal Clock %dKHz, downclock %dKHz\n",
205 temp_downclock, panel_fixed_mode->clock);
206 }
165 return; 207 return;
166} 208}
167 209
@@ -241,22 +283,18 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
241 GPIOF, 283 GPIOF,
242 }; 284 };
243 285
244 /* Set sensible defaults in case we can't find the general block
245 or it is the wrong chipset */
246 dev_priv->crt_ddc_bus = -1;
247
248 general = find_section(bdb, BDB_GENERAL_DEFINITIONS); 286 general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
249 if (general) { 287 if (general) {
250 u16 block_size = get_blocksize(general); 288 u16 block_size = get_blocksize(general);
251 if (block_size >= sizeof(*general)) { 289 if (block_size >= sizeof(*general)) {
252 int bus_pin = general->crt_ddc_gmbus_pin; 290 int bus_pin = general->crt_ddc_gmbus_pin;
253 DRM_DEBUG("crt_ddc_bus_pin: %d\n", bus_pin); 291 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
254 if ((bus_pin >= 1) && (bus_pin <= 6)) { 292 if ((bus_pin >= 1) && (bus_pin <= 6)) {
255 dev_priv->crt_ddc_bus = 293 dev_priv->crt_ddc_bus =
256 crt_bus_map_table[bus_pin-1]; 294 crt_bus_map_table[bus_pin-1];
257 } 295 }
258 } else { 296 } else {
259 DRM_DEBUG("BDB_GD too small (%d). Invalid.\n", 297 DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n",
260 block_size); 298 block_size);
261 } 299 }
262 } 300 }
@@ -274,7 +312,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
274 312
275 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 313 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
276 if (!p_defs) { 314 if (!p_defs) {
277 DRM_DEBUG("No general definition block is found\n"); 315 DRM_DEBUG_KMS("No general definition block is found\n");
278 return; 316 return;
279 } 317 }
280 /* judge whether the size of child device meets the requirements. 318 /* judge whether the size of child device meets the requirements.
@@ -284,7 +322,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
284 */ 322 */
285 if (p_defs->child_dev_size != sizeof(*p_child)) { 323 if (p_defs->child_dev_size != sizeof(*p_child)) {
286 /* different child dev size . Ignore it */ 324 /* different child dev size . Ignore it */
287 DRM_DEBUG("different child size is found. Invalid.\n"); 325 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
288 return; 326 return;
289 } 327 }
290 /* get the block size of general definitions */ 328 /* get the block size of general definitions */
@@ -310,11 +348,11 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
310 if (p_child->dvo_port != DEVICE_PORT_DVOB && 348 if (p_child->dvo_port != DEVICE_PORT_DVOB &&
311 p_child->dvo_port != DEVICE_PORT_DVOC) { 349 p_child->dvo_port != DEVICE_PORT_DVOC) {
312 /* skip the incorrect SDVO port */ 350 /* skip the incorrect SDVO port */
313 DRM_DEBUG("Incorrect SDVO port. Skip it \n"); 351 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n");
314 continue; 352 continue;
315 } 353 }
316 DRM_DEBUG("the SDVO device with slave addr %2x is found on " 354 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
317 "%s port\n", 355 " %s port\n",
318 p_child->slave_addr, 356 p_child->slave_addr,
319 (p_child->dvo_port == DEVICE_PORT_DVOB) ? 357 (p_child->dvo_port == DEVICE_PORT_DVOB) ?
320 "SDVOB" : "SDVOC"); 358 "SDVOB" : "SDVOC");
@@ -325,21 +363,21 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
325 p_mapping->dvo_wiring = p_child->dvo_wiring; 363 p_mapping->dvo_wiring = p_child->dvo_wiring;
326 p_mapping->initialized = 1; 364 p_mapping->initialized = 1;
327 } else { 365 } else {
328 DRM_DEBUG("Maybe one SDVO port is shared by " 366 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
329 "two SDVO device.\n"); 367 "two SDVO device.\n");
330 } 368 }
331 if (p_child->slave2_addr) { 369 if (p_child->slave2_addr) {
332 /* Maybe this is a SDVO device with multiple inputs */ 370 /* Maybe this is a SDVO device with multiple inputs */
333 /* And the mapping info is not added */ 371 /* And the mapping info is not added */
334 DRM_DEBUG("there exists the slave2_addr. Maybe this " 372 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
335 "is a SDVO device with multiple inputs.\n"); 373 " is a SDVO device with multiple inputs.\n");
336 } 374 }
337 count++; 375 count++;
338 } 376 }
339 377
340 if (!count) { 378 if (!count) {
341 /* No SDVO device info is found */ 379 /* No SDVO device info is found */
342 DRM_DEBUG("No SDVO device info is found in VBT\n"); 380 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
343 } 381 }
344 return; 382 return;
345} 383}
@@ -366,6 +404,70 @@ parse_driver_features(struct drm_i915_private *dev_priv,
366 dev_priv->render_reclock_avail = true; 404 dev_priv->render_reclock_avail = true;
367} 405}
368 406
407static void
408parse_device_mapping(struct drm_i915_private *dev_priv,
409 struct bdb_header *bdb)
410{
411 struct bdb_general_definitions *p_defs;
412 struct child_device_config *p_child, *child_dev_ptr;
413 int i, child_device_num, count;
414 u16 block_size;
415
416 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
417 if (!p_defs) {
418 DRM_DEBUG_KMS("No general definition block is found\n");
419 return;
420 }
421 /* judge whether the size of child device meets the requirements.
422 * If the child device size obtained from general definition block
423 * is different with sizeof(struct child_device_config), skip the
424 * parsing of sdvo device info
425 */
426 if (p_defs->child_dev_size != sizeof(*p_child)) {
427 /* different child dev size . Ignore it */
428 DRM_DEBUG_KMS("different child size is found. Invalid.\n");
429 return;
430 }
431 /* get the block size of general definitions */
432 block_size = get_blocksize(p_defs);
433 /* get the number of child device */
434 child_device_num = (block_size - sizeof(*p_defs)) /
435 sizeof(*p_child);
436 count = 0;
437 /* get the number of child device that is present */
438 for (i = 0; i < child_device_num; i++) {
439 p_child = &(p_defs->devices[i]);
440 if (!p_child->device_type) {
441 /* skip the device block if device type is invalid */
442 continue;
443 }
444 count++;
445 }
446 if (!count) {
447 DRM_DEBUG_KMS("no child dev is parsed from VBT \n");
448 return;
449 }
450 dev_priv->child_dev = kzalloc(sizeof(*p_child) * count, GFP_KERNEL);
451 if (!dev_priv->child_dev) {
452 DRM_DEBUG_KMS("No memory space for child device\n");
453 return;
454 }
455
456 dev_priv->child_dev_num = count;
457 count = 0;
458 for (i = 0; i < child_device_num; i++) {
459 p_child = &(p_defs->devices[i]);
460 if (!p_child->device_type) {
461 /* skip the device block if device type is invalid */
462 continue;
463 }
464 child_dev_ptr = dev_priv->child_dev + count;
465 count++;
466 memcpy((void *)child_dev_ptr, (void *)p_child,
467 sizeof(*p_child));
468 }
469 return;
470}
369/** 471/**
370 * intel_init_bios - initialize VBIOS settings & find VBT 472 * intel_init_bios - initialize VBIOS settings & find VBT
371 * @dev: DRM device 473 * @dev: DRM device
@@ -417,6 +519,7 @@ intel_init_bios(struct drm_device *dev)
417 parse_lfp_panel_data(dev_priv, bdb); 519 parse_lfp_panel_data(dev_priv, bdb);
418 parse_sdvo_panel_data(dev_priv, bdb); 520 parse_sdvo_panel_data(dev_priv, bdb);
419 parse_sdvo_device_mapping(dev_priv, bdb); 521 parse_sdvo_device_mapping(dev_priv, bdb);
522 parse_device_mapping(dev_priv, bdb);
420 parse_driver_features(dev_priv, bdb); 523 parse_driver_features(dev_priv, bdb);
421 524
422 pci_unmap_rom(pdev, bios); 525 pci_unmap_rom(pdev, bios);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 0f8e5f69ac7a..425ac9d7f724 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -549,4 +549,21 @@ bool intel_init_bios(struct drm_device *dev);
549#define SWF14_APM_STANDBY 0x1 549#define SWF14_APM_STANDBY 0x1
550#define SWF14_APM_RESTORE 0x0 550#define SWF14_APM_RESTORE 0x0
551 551
552/* Add the device class for LFP, TV, HDMI */
553#define DEVICE_TYPE_INT_LFP 0x1022
554#define DEVICE_TYPE_INT_TV 0x1009
555#define DEVICE_TYPE_HDMI 0x60D2
556#define DEVICE_TYPE_DP 0x68C6
557#define DEVICE_TYPE_eDP 0x78C6
558
559/* define the DVO port for HDMI output type */
560#define DVO_B 1
561#define DVO_C 2
562#define DVO_D 3
563
564/* define the PORT for DP output type */
565#define PORT_IDPB 7
566#define PORT_IDPC 8
567#define PORT_IDPD 9
568
552#endif /* _I830_BIOS_H_ */ 569#endif /* _I830_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 212e22740fc1..477a61c5402b 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -64,34 +64,6 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
64 } 64 }
65 65
66 I915_WRITE(reg, temp); 66 I915_WRITE(reg, temp);
67
68 if (IS_IGD(dev)) {
69 if (mode == DRM_MODE_DPMS_OFF) {
70 /* turn off DAC */
71 temp = I915_READ(PORT_HOTPLUG_EN);
72 temp &= ~CRT_EOS_INT_EN;
73 I915_WRITE(PORT_HOTPLUG_EN, temp);
74
75 temp = I915_READ(PORT_HOTPLUG_STAT);
76 if (temp & CRT_EOS_INT_STATUS)
77 I915_WRITE(PORT_HOTPLUG_STAT,
78 CRT_EOS_INT_STATUS);
79 } else {
80 /* turn on DAC. EOS interrupt must be enabled after DAC
81 * is enabled, so it sounds not good to enable it in
82 * i915_driver_irq_postinstall()
83 * wait 12.5ms after DAC is enabled
84 */
85 msleep(13);
86 temp = I915_READ(PORT_HOTPLUG_STAT);
87 if (temp & CRT_EOS_INT_STATUS)
88 I915_WRITE(PORT_HOTPLUG_STAT,
89 CRT_EOS_INT_STATUS);
90 temp = I915_READ(PORT_HOTPLUG_EN);
91 temp |= CRT_EOS_INT_EN;
92 I915_WRITE(PORT_HOTPLUG_EN, temp);
93 }
94 }
95} 67}
96 68
97static int intel_crt_mode_valid(struct drm_connector *connector, 69static int intel_crt_mode_valid(struct drm_connector *connector,
@@ -194,7 +166,7 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
194 ADPA_CRT_HOTPLUG_ENABLE | 166 ADPA_CRT_HOTPLUG_ENABLE |
195 ADPA_CRT_HOTPLUG_FORCE_TRIGGER); 167 ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
196 168
197 DRM_DEBUG("pch crt adpa 0x%x", adpa); 169 DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
198 I915_WRITE(PCH_ADPA, adpa); 170 I915_WRITE(PCH_ADPA, adpa);
199 171
200 while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) 172 while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
@@ -554,7 +526,7 @@ void intel_crt_init(struct drm_device *dev)
554 else { 526 else {
555 i2c_reg = GPIOA; 527 i2c_reg = GPIOA;
556 /* Use VBT information for CRT DDC if available */ 528 /* Use VBT information for CRT DDC if available */
557 if (dev_priv->crt_ddc_bus != -1) 529 if (dev_priv->crt_ddc_bus != 0)
558 i2c_reg = dev_priv->crt_ddc_bus; 530 i2c_reg = dev_priv->crt_ddc_bus;
559 } 531 }
560 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); 532 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ba6546b7c7f..002c07daf9b8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -706,16 +706,17 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
706 706
707 memset (best_clock, 0, sizeof (*best_clock)); 707 memset (best_clock, 0, sizeof (*best_clock));
708 708
709 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 709 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 710 clock.m1++) {
711 clock.m1++) { 711 for (clock.m2 = limit->m2.min;
712 for (clock.m2 = limit->m2.min; 712 clock.m2 <= limit->m2.max; clock.m2++) {
713 clock.m2 <= limit->m2.max; clock.m2++) { 713 /* m1 is always 0 in IGD */
714 /* m1 is always 0 in IGD */ 714 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
715 if (clock.m2 >= clock.m1 && !IS_IGD(dev)) 715 break;
716 break; 716 for (clock.n = limit->n.min;
717 for (clock.n = limit->n.min; 717 clock.n <= limit->n.max; clock.n++) {
718 clock.n <= limit->n.max; clock.n++) { 718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
719 int this_err; 720 int this_err;
720 721
721 intel_clock(dev, refclk, &clock); 722 intel_clock(dev, refclk, &clock);
@@ -863,10 +864,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 struct drm_device *dev = crtc->dev; 864 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private; 865 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock; 866 intel_clock_t clock;
866 int max_n;
867 bool found;
868 int err_most = 47; 867 int err_most = 47;
869 found = false; 868 int err_min = 10000;
870 869
871 /* eDP has only 2 clock choice, no n/m/p setting */ 870 /* eDP has only 2 clock choice, no n/m/p setting */
872 if (HAS_eDP) 871 if (HAS_eDP)
@@ -890,10 +889,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
890 } 889 }
891 890
892 memset(best_clock, 0, sizeof(*best_clock)); 891 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 892 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */ 893 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 894 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */ 895 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max; 896 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) { 897 clock.m1 >= limit->m1.min; clock.m1--) {
@@ -907,18 +905,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
907 this_err = abs((10000 - (target*10000/clock.dot))); 905 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) { 906 if (this_err < err_most) {
909 *best_clock = clock; 907 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 /* found on first matching */ 908 /* found on first matching */
914 goto out; 909 goto out;
910 } else if (this_err < err_min) {
911 *best_clock = clock;
912 err_min = this_err;
915 } 913 }
916 } 914 }
917 } 915 }
918 } 916 }
919 } 917 }
920out: 918out:
921 return found; 919 return true;
922} 920}
923 921
924/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 922/* DisplayPort has only two frequencies, 162MHz and 270MHz */
@@ -952,7 +950,7 @@ void
952intel_wait_for_vblank(struct drm_device *dev) 950intel_wait_for_vblank(struct drm_device *dev)
953{ 951{
954 /* Wait for 20ms, i.e. one cycle at 50hz. */ 952 /* Wait for 20ms, i.e. one cycle at 50hz. */
955 mdelay(20); 953 msleep(20);
956} 954}
957 955
958/* Parameters have changed, update FBC info */ 956/* Parameters have changed, update FBC info */
@@ -997,7 +995,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
997 fbc_ctl |= dev_priv->cfb_fence; 995 fbc_ctl |= dev_priv->cfb_fence;
998 I915_WRITE(FBC_CONTROL, fbc_ctl); 996 I915_WRITE(FBC_CONTROL, fbc_ctl);
999 997
1000 DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ", 998 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1001 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); 999 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1002} 1000}
1003 1001
@@ -1020,7 +1018,7 @@ void i8xx_disable_fbc(struct drm_device *dev)
1020 1018
1021 intel_wait_for_vblank(dev); 1019 intel_wait_for_vblank(dev);
1022 1020
1023 DRM_DEBUG("disabled FBC\n"); 1021 DRM_DEBUG_KMS("disabled FBC\n");
1024} 1022}
1025 1023
1026static bool i8xx_fbc_enabled(struct drm_crtc *crtc) 1024static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
@@ -1065,7 +1063,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1065 /* enable it... */ 1063 /* enable it... */
1066 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 1064 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1067 1065
1068 DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane); 1066 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1069} 1067}
1070 1068
1071void g4x_disable_fbc(struct drm_device *dev) 1069void g4x_disable_fbc(struct drm_device *dev)
@@ -1079,7 +1077,7 @@ void g4x_disable_fbc(struct drm_device *dev)
1079 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1077 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1080 intel_wait_for_vblank(dev); 1078 intel_wait_for_vblank(dev);
1081 1079
1082 DRM_DEBUG("disabled FBC\n"); 1080 DRM_DEBUG_KMS("disabled FBC\n");
1083} 1081}
1084 1082
1085static bool g4x_fbc_enabled(struct drm_crtc *crtc) 1083static bool g4x_fbc_enabled(struct drm_crtc *crtc)
@@ -1144,25 +1142,27 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1144 * - going to an unsupported config (interlace, pixel multiply, etc.) 1142 * - going to an unsupported config (interlace, pixel multiply, etc.)
1145 */ 1143 */
1146 if (intel_fb->obj->size > dev_priv->cfb_size) { 1144 if (intel_fb->obj->size > dev_priv->cfb_size) {
1147 DRM_DEBUG("framebuffer too large, disabling compression\n"); 1145 DRM_DEBUG_KMS("framebuffer too large, disabling "
1146 "compression\n");
1148 goto out_disable; 1147 goto out_disable;
1149 } 1148 }
1150 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 1149 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1151 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) { 1150 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1152 DRM_DEBUG("mode incompatible with compression, disabling\n"); 1151 DRM_DEBUG_KMS("mode incompatible with compression, "
1152 "disabling\n");
1153 goto out_disable; 1153 goto out_disable;
1154 } 1154 }
1155 if ((mode->hdisplay > 2048) || 1155 if ((mode->hdisplay > 2048) ||
1156 (mode->vdisplay > 1536)) { 1156 (mode->vdisplay > 1536)) {
1157 DRM_DEBUG("mode too large for compression, disabling\n"); 1157 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1158 goto out_disable; 1158 goto out_disable;
1159 } 1159 }
1160 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) { 1160 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1161 DRM_DEBUG("plane not 0, disabling compression\n"); 1161 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1162 goto out_disable; 1162 goto out_disable;
1163 } 1163 }
1164 if (obj_priv->tiling_mode != I915_TILING_X) { 1164 if (obj_priv->tiling_mode != I915_TILING_X) {
1165 DRM_DEBUG("framebuffer not tiled, disabling compression\n"); 1165 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1166 goto out_disable; 1166 goto out_disable;
1167 } 1167 }
1168 1168
@@ -1184,7 +1184,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1184 return; 1184 return;
1185 1185
1186out_disable: 1186out_disable:
1187 DRM_DEBUG("unsupported config, disabling FBC\n"); 1187 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1188 /* Multiple disables should be harmless */ 1188 /* Multiple disables should be harmless */
1189 if (dev_priv->display.fbc_enabled(crtc)) 1189 if (dev_priv->display.fbc_enabled(crtc))
1190 dev_priv->display.disable_fbc(dev); 1190 dev_priv->display.disable_fbc(dev);
@@ -1214,7 +1214,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1214 1214
1215 /* no fb bound */ 1215 /* no fb bound */
1216 if (!crtc->fb) { 1216 if (!crtc->fb) {
1217 DRM_DEBUG("No FB bound\n"); 1217 DRM_DEBUG_KMS("No FB bound\n");
1218 return 0; 1218 return 0;
1219 } 1219 }
1220 1220
@@ -1290,7 +1290,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1290 break; 1290 break;
1291 case 24: 1291 case 24:
1292 case 32: 1292 case 32:
1293 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 1293 if (crtc->fb->depth == 30)
1294 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1295 else
1296 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1294 break; 1297 break;
1295 default: 1298 default:
1296 DRM_ERROR("Unknown color depth\n"); 1299 DRM_ERROR("Unknown color depth\n");
@@ -1314,7 +1317,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1314 Start = obj_priv->gtt_offset; 1317 Start = obj_priv->gtt_offset;
1315 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); 1318 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1316 1319
1317 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1320 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1318 I915_WRITE(dspstride, crtc->fb->pitch); 1321 I915_WRITE(dspstride, crtc->fb->pitch);
1319 if (IS_I965G(dev)) { 1322 if (IS_I965G(dev)) {
1320 I915_WRITE(dspbase, Offset); 1323 I915_WRITE(dspbase, Offset);
@@ -1388,7 +1391,7 @@ static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1388 struct drm_i915_private *dev_priv = dev->dev_private; 1391 struct drm_i915_private *dev_priv = dev->dev_private;
1389 u32 dpa_ctl; 1392 u32 dpa_ctl;
1390 1393
1391 DRM_DEBUG("\n"); 1394 DRM_DEBUG_KMS("\n");
1392 dpa_ctl = I915_READ(DP_A); 1395 dpa_ctl = I915_READ(DP_A);
1393 dpa_ctl &= ~DP_PLL_ENABLE; 1396 dpa_ctl &= ~DP_PLL_ENABLE;
1394 I915_WRITE(DP_A, dpa_ctl); 1397 I915_WRITE(DP_A, dpa_ctl);
@@ -1413,7 +1416,7 @@ static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1413 struct drm_i915_private *dev_priv = dev->dev_private; 1416 struct drm_i915_private *dev_priv = dev->dev_private;
1414 u32 dpa_ctl; 1417 u32 dpa_ctl;
1415 1418
1416 DRM_DEBUG("eDP PLL enable for clock %d\n", clock); 1419 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1417 dpa_ctl = I915_READ(DP_A); 1420 dpa_ctl = I915_READ(DP_A);
1418 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1421 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1419 1422
@@ -1484,7 +1487,16 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1484 case DRM_MODE_DPMS_ON: 1487 case DRM_MODE_DPMS_ON:
1485 case DRM_MODE_DPMS_STANDBY: 1488 case DRM_MODE_DPMS_STANDBY:
1486 case DRM_MODE_DPMS_SUSPEND: 1489 case DRM_MODE_DPMS_SUSPEND:
1487 DRM_DEBUG("crtc %d dpms on\n", pipe); 1490 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1491
1492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1493 temp = I915_READ(PCH_LVDS);
1494 if ((temp & LVDS_PORT_EN) == 0) {
1495 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1496 POSTING_READ(PCH_LVDS);
1497 }
1498 }
1499
1488 if (HAS_eDP) { 1500 if (HAS_eDP) {
1489 /* enable eDP PLL */ 1501 /* enable eDP PLL */
1490 igdng_enable_pll_edp(crtc); 1502 igdng_enable_pll_edp(crtc);
@@ -1571,12 +1583,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1571 udelay(150); 1583 udelay(150);
1572 1584
1573 temp = I915_READ(fdi_rx_iir_reg); 1585 temp = I915_READ(fdi_rx_iir_reg);
1574 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1575 1587
1576 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1588 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1577 for (j = 0; j < tries; j++) { 1589 for (j = 0; j < tries; j++) {
1578 temp = I915_READ(fdi_rx_iir_reg); 1590 temp = I915_READ(fdi_rx_iir_reg);
1579 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1591 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1592 temp);
1580 if (temp & FDI_RX_BIT_LOCK) 1593 if (temp & FDI_RX_BIT_LOCK)
1581 break; 1594 break;
1582 udelay(200); 1595 udelay(200);
@@ -1585,11 +1598,11 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1585 I915_WRITE(fdi_rx_iir_reg, 1598 I915_WRITE(fdi_rx_iir_reg,
1586 temp | FDI_RX_BIT_LOCK); 1599 temp | FDI_RX_BIT_LOCK);
1587 else 1600 else
1588 DRM_DEBUG("train 1 fail\n"); 1601 DRM_DEBUG_KMS("train 1 fail\n");
1589 } else { 1602 } else {
1590 I915_WRITE(fdi_rx_iir_reg, 1603 I915_WRITE(fdi_rx_iir_reg,
1591 temp | FDI_RX_BIT_LOCK); 1604 temp | FDI_RX_BIT_LOCK);
1592 DRM_DEBUG("train 1 ok 2!\n"); 1605 DRM_DEBUG_KMS("train 1 ok 2!\n");
1593 } 1606 }
1594 temp = I915_READ(fdi_tx_reg); 1607 temp = I915_READ(fdi_tx_reg);
1595 temp &= ~FDI_LINK_TRAIN_NONE; 1608 temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1604,12 +1617,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1604 udelay(150); 1617 udelay(150);
1605 1618
1606 temp = I915_READ(fdi_rx_iir_reg); 1619 temp = I915_READ(fdi_rx_iir_reg);
1607 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1608 1621
1609 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1622 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1610 for (j = 0; j < tries; j++) { 1623 for (j = 0; j < tries; j++) {
1611 temp = I915_READ(fdi_rx_iir_reg); 1624 temp = I915_READ(fdi_rx_iir_reg);
1612 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1625 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1626 temp);
1613 if (temp & FDI_RX_SYMBOL_LOCK) 1627 if (temp & FDI_RX_SYMBOL_LOCK)
1614 break; 1628 break;
1615 udelay(200); 1629 udelay(200);
@@ -1617,15 +1631,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1617 if (j != tries) { 1631 if (j != tries) {
1618 I915_WRITE(fdi_rx_iir_reg, 1632 I915_WRITE(fdi_rx_iir_reg,
1619 temp | FDI_RX_SYMBOL_LOCK); 1633 temp | FDI_RX_SYMBOL_LOCK);
1620 DRM_DEBUG("train 2 ok 1!\n"); 1634 DRM_DEBUG_KMS("train 2 ok 1!\n");
1621 } else 1635 } else
1622 DRM_DEBUG("train 2 fail\n"); 1636 DRM_DEBUG_KMS("train 2 fail\n");
1623 } else { 1637 } else {
1624 I915_WRITE(fdi_rx_iir_reg, 1638 I915_WRITE(fdi_rx_iir_reg,
1625 temp | FDI_RX_SYMBOL_LOCK); 1639 temp | FDI_RX_SYMBOL_LOCK);
1626 DRM_DEBUG("train 2 ok 2!\n"); 1640 DRM_DEBUG_KMS("train 2 ok 2!\n");
1627 } 1641 }
1628 DRM_DEBUG("train done\n"); 1642 DRM_DEBUG_KMS("train done\n");
1629 1643
1630 /* set transcoder timing */ 1644 /* set transcoder timing */
1631 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1645 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1667,9 +1681,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1667 1681
1668 break; 1682 break;
1669 case DRM_MODE_DPMS_OFF: 1683 case DRM_MODE_DPMS_OFF:
1670 DRM_DEBUG("crtc %d dpms off\n", pipe); 1684 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1671
1672 i915_disable_vga(dev);
1673 1685
1674 /* Disable display plane */ 1686 /* Disable display plane */
1675 temp = I915_READ(dspcntr_reg); 1687 temp = I915_READ(dspcntr_reg);
@@ -1680,6 +1692,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1680 I915_READ(dspbase_reg); 1692 I915_READ(dspbase_reg);
1681 } 1693 }
1682 1694
1695 i915_disable_vga(dev);
1696
1683 /* disable cpu pipe, disable after all planes disabled */ 1697 /* disable cpu pipe, disable after all planes disabled */
1684 temp = I915_READ(pipeconf_reg); 1698 temp = I915_READ(pipeconf_reg);
1685 if ((temp & PIPEACONF_ENABLE) != 0) { 1699 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -1693,16 +1707,23 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1693 udelay(500); 1707 udelay(500);
1694 continue; 1708 continue;
1695 } else { 1709 } else {
1696 DRM_DEBUG("pipe %d off delay\n", pipe); 1710 DRM_DEBUG_KMS("pipe %d off delay\n",
1711 pipe);
1697 break; 1712 break;
1698 } 1713 }
1699 } 1714 }
1700 } else 1715 } else
1701 DRM_DEBUG("crtc %d is disabled\n", pipe); 1716 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1702 1717
1703 if (HAS_eDP) { 1718 udelay(100);
1704 igdng_disable_pll_edp(crtc); 1719
1720 /* Disable PF */
1721 temp = I915_READ(pf_ctl_reg);
1722 if ((temp & PF_ENABLE) != 0) {
1723 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1724 I915_READ(pf_ctl_reg);
1705 } 1725 }
1726 I915_WRITE(pf_win_size, 0);
1706 1727
1707 /* disable CPU FDI tx and PCH FDI rx */ 1728 /* disable CPU FDI tx and PCH FDI rx */
1708 temp = I915_READ(fdi_tx_reg); 1729 temp = I915_READ(fdi_tx_reg);
@@ -1728,6 +1749,13 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1728 1749
1729 udelay(100); 1750 udelay(100);
1730 1751
1752 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1753 temp = I915_READ(PCH_LVDS);
1754 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1755 I915_READ(PCH_LVDS);
1756 udelay(100);
1757 }
1758
1731 /* disable PCH transcoder */ 1759 /* disable PCH transcoder */
1732 temp = I915_READ(transconf_reg); 1760 temp = I915_READ(transconf_reg);
1733 if ((temp & TRANS_ENABLE) != 0) { 1761 if ((temp & TRANS_ENABLE) != 0) {
@@ -1741,12 +1769,15 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1741 udelay(500); 1769 udelay(500);
1742 continue; 1770 continue;
1743 } else { 1771 } else {
1744 DRM_DEBUG("transcoder %d off delay\n", pipe); 1772 DRM_DEBUG_KMS("transcoder %d off "
1773 "delay\n", pipe);
1745 break; 1774 break;
1746 } 1775 }
1747 } 1776 }
1748 } 1777 }
1749 1778
1779 udelay(100);
1780
1750 /* disable PCH DPLL */ 1781 /* disable PCH DPLL */
1751 temp = I915_READ(pch_dpll_reg); 1782 temp = I915_READ(pch_dpll_reg);
1752 if ((temp & DPLL_VCO_ENABLE) != 0) { 1783 if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -1754,14 +1785,20 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1754 I915_READ(pch_dpll_reg); 1785 I915_READ(pch_dpll_reg);
1755 } 1786 }
1756 1787
1757 temp = I915_READ(fdi_rx_reg); 1788 if (HAS_eDP) {
1758 if ((temp & FDI_RX_PLL_ENABLE) != 0) { 1789 igdng_disable_pll_edp(crtc);
1759 temp &= ~FDI_SEL_PCDCLK;
1760 temp &= ~FDI_RX_PLL_ENABLE;
1761 I915_WRITE(fdi_rx_reg, temp);
1762 I915_READ(fdi_rx_reg);
1763 } 1790 }
1764 1791
1792 temp = I915_READ(fdi_rx_reg);
1793 temp &= ~FDI_SEL_PCDCLK;
1794 I915_WRITE(fdi_rx_reg, temp);
1795 I915_READ(fdi_rx_reg);
1796
1797 temp = I915_READ(fdi_rx_reg);
1798 temp &= ~FDI_RX_PLL_ENABLE;
1799 I915_WRITE(fdi_rx_reg, temp);
1800 I915_READ(fdi_rx_reg);
1801
1765 /* Disable CPU FDI TX PLL */ 1802 /* Disable CPU FDI TX PLL */
1766 temp = I915_READ(fdi_tx_reg); 1803 temp = I915_READ(fdi_tx_reg);
1767 if ((temp & FDI_TX_PLL_ENABLE) != 0) { 1804 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
@@ -1770,20 +1807,43 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1770 udelay(100); 1807 udelay(100);
1771 } 1808 }
1772 1809
1773 /* Disable PF */
1774 temp = I915_READ(pf_ctl_reg);
1775 if ((temp & PF_ENABLE) != 0) {
1776 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1777 I915_READ(pf_ctl_reg);
1778 }
1779 I915_WRITE(pf_win_size, 0);
1780
1781 /* Wait for the clocks to turn off. */ 1810 /* Wait for the clocks to turn off. */
1782 udelay(150); 1811 udelay(100);
1783 break; 1812 break;
1784 } 1813 }
1785} 1814}
1786 1815
1816static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1817{
1818 struct intel_overlay *overlay;
1819 int ret;
1820
1821 if (!enable && intel_crtc->overlay) {
1822 overlay = intel_crtc->overlay;
1823 mutex_lock(&overlay->dev->struct_mutex);
1824 for (;;) {
1825 ret = intel_overlay_switch_off(overlay);
1826 if (ret == 0)
1827 break;
1828
1829 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1830 if (ret != 0) {
1831 /* overlay doesn't react anymore. Usually
1832 * results in a black screen and an unkillable
1833 * X server. */
1834 BUG();
1835 overlay->hw_wedged = HW_WEDGED;
1836 break;
1837 }
1838 }
1839 mutex_unlock(&overlay->dev->struct_mutex);
1840 }
1841 /* Let userspace switch the overlay on again. In most cases userspace
1842 * has to recompute where to put it anyway. */
1843
1844 return;
1845}
1846
1787static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 1847static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1788{ 1848{
1789 struct drm_device *dev = crtc->dev; 1849 struct drm_device *dev = crtc->dev;
@@ -1842,12 +1902,13 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1842 intel_update_fbc(crtc, &crtc->mode); 1902 intel_update_fbc(crtc, &crtc->mode);
1843 1903
1844 /* Give the overlay scaler a chance to enable if it's on this pipe */ 1904 /* Give the overlay scaler a chance to enable if it's on this pipe */
1845 //intel_crtc_dpms_video(crtc, true); TODO 1905 intel_crtc_dpms_overlay(intel_crtc, true);
1846 break; 1906 break;
1847 case DRM_MODE_DPMS_OFF: 1907 case DRM_MODE_DPMS_OFF:
1848 intel_update_watermarks(dev); 1908 intel_update_watermarks(dev);
1909
1849 /* Give the overlay scaler a chance to disable if it's on this pipe */ 1910 /* Give the overlay scaler a chance to disable if it's on this pipe */
1850 //intel_crtc_dpms_video(crtc, FALSE); TODO 1911 intel_crtc_dpms_overlay(intel_crtc, false);
1851 1912
1852 if (dev_priv->cfb_plane == plane && 1913 if (dev_priv->cfb_plane == plane &&
1853 dev_priv->display.disable_fbc) 1914 dev_priv->display.disable_fbc)
@@ -2042,7 +2103,7 @@ static int i830_get_display_clock_speed(struct drm_device *dev)
2042 * Return the pipe currently connected to the panel fitter, 2103 * Return the pipe currently connected to the panel fitter,
2043 * or -1 if the panel fitter is not present or not in use 2104 * or -1 if the panel fitter is not present or not in use
2044 */ 2105 */
2045static int intel_panel_fitter_pipe (struct drm_device *dev) 2106int intel_panel_fitter_pipe (struct drm_device *dev)
2046{ 2107{
2047 struct drm_i915_private *dev_priv = dev->dev_private; 2108 struct drm_i915_private *dev_priv = dev->dev_private;
2048 u32 pfit_control; 2109 u32 pfit_control;
@@ -2216,11 +2277,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2216 1000; 2277 1000;
2217 entries_required /= wm->cacheline_size; 2278 entries_required /= wm->cacheline_size;
2218 2279
2219 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required); 2280 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2220 2281
2221 wm_size = wm->fifo_size - (entries_required + wm->guard_size); 2282 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2222 2283
2223 DRM_DEBUG("FIFO watermark level: %d\n", wm_size); 2284 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2224 2285
2225 /* Don't promote wm_size to unsigned... */ 2286 /* Don't promote wm_size to unsigned... */
2226 if (wm_size > (long)wm->max_wm) 2287 if (wm_size > (long)wm->max_wm)
@@ -2282,7 +2343,7 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2282 return latency; 2343 return latency;
2283 } 2344 }
2284 2345
2285 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2346 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2286 2347
2287 return NULL; 2348 return NULL;
2288} 2349}
@@ -2310,7 +2371,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2310 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, 2371 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2311 dev_priv->mem_freq); 2372 dev_priv->mem_freq);
2312 if (!latency) { 2373 if (!latency) {
2313 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); 2374 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2314 igd_disable_cxsr(dev); 2375 igd_disable_cxsr(dev);
2315 return; 2376 return;
2316 } 2377 }
@@ -2322,7 +2383,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2322 reg &= 0x7fffff; 2383 reg &= 0x7fffff;
2323 reg |= wm << 23; 2384 reg |= wm << 23;
2324 I915_WRITE(DSPFW1, reg); 2385 I915_WRITE(DSPFW1, reg);
2325 DRM_DEBUG("DSPFW1 register is %x\n", reg); 2386 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2326 2387
2327 /* cursor SR */ 2388 /* cursor SR */
2328 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, 2389 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
@@ -2347,7 +2408,7 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2347 reg &= ~(0x3f << 16); 2408 reg &= ~(0x3f << 16);
2348 reg |= (wm & 0x3f) << 16; 2409 reg |= (wm & 0x3f) << 16;
2349 I915_WRITE(DSPFW3, reg); 2410 I915_WRITE(DSPFW3, reg);
2350 DRM_DEBUG("DSPFW3 register is %x\n", reg); 2411 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2351 2412
2352 /* activate cxsr */ 2413 /* activate cxsr */
2353 reg = I915_READ(DSPFW3); 2414 reg = I915_READ(DSPFW3);
@@ -2387,8 +2448,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2387 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - 2448 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2388 (dsparb & 0x7f); 2449 (dsparb & 0x7f);
2389 2450
2390 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2451 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2391 size); 2452 plane ? "B" : "A", size);
2392 2453
2393 return size; 2454 return size;
2394} 2455}
@@ -2406,8 +2467,8 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2406 (dsparb & 0x1ff); 2467 (dsparb & 0x1ff);
2407 size >>= 1; /* Convert to cachelines */ 2468 size >>= 1; /* Convert to cachelines */
2408 2469
2409 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2470 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2410 size); 2471 plane ? "B" : "A", size);
2411 2472
2412 return size; 2473 return size;
2413} 2474}
@@ -2421,7 +2482,8 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane)
2421 size = dsparb & 0x7f; 2482 size = dsparb & 0x7f;
2422 size >>= 2; /* Convert to cachelines */ 2483 size >>= 2; /* Convert to cachelines */
2423 2484
2424 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2485 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2486 plane ? "B" : "A",
2425 size); 2487 size);
2426 2488
2427 return size; 2489 return size;
@@ -2436,8 +2498,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2436 size = dsparb & 0x7f; 2498 size = dsparb & 0x7f;
2437 size >>= 1; /* Convert to cachelines */ 2499 size >>= 1; /* Convert to cachelines */
2438 2500
2439 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", 2501 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2440 size); 2502 plane ? "B" : "A", size);
2441 2503
2442 return size; 2504 return size;
2443} 2505}
@@ -2512,15 +2574,39 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2512 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 2574 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2513} 2575}
2514 2576
2515static void i965_update_wm(struct drm_device *dev, int unused, int unused2, 2577static void i965_update_wm(struct drm_device *dev, int planea_clock,
2516 int unused3, int unused4) 2578 int planeb_clock, int sr_hdisplay, int pixel_size)
2517{ 2579{
2518 struct drm_i915_private *dev_priv = dev->dev_private; 2580 struct drm_i915_private *dev_priv = dev->dev_private;
2581 unsigned long line_time_us;
2582 int sr_clock, sr_entries, srwm = 1;
2583
2584 /* Calc sr entries for one plane configs */
2585 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2586 /* self-refresh has much higher latency */
2587 const static int sr_latency_ns = 12000;
2588
2589 sr_clock = planea_clock ? planea_clock : planeb_clock;
2590 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2591
2592 /* Use ns/us then divide to preserve precision */
2593 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2594 pixel_size * sr_hdisplay) / 1000;
2595 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2596 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2597 srwm = I945_FIFO_SIZE - sr_entries;
2598 if (srwm < 0)
2599 srwm = 1;
2600 srwm &= 0x3f;
2601 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2602 }
2519 2603
2520 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); 2604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2605 srwm);
2521 2606
2522 /* 965 has limitations... */ 2607 /* 965 has limitations... */
2523 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); 2608 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2609 (8 << 0));
2524 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 2610 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2525} 2611}
2526 2612
@@ -2556,7 +2642,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2556 pixel_size, latency_ns); 2642 pixel_size, latency_ns);
2557 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, 2643 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2558 pixel_size, latency_ns); 2644 pixel_size, latency_ns);
2559 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 2645 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2560 2646
2561 /* 2647 /*
2562 * Overlay gets an aggressive default since video jitter is bad. 2648 * Overlay gets an aggressive default since video jitter is bad.
@@ -2576,14 +2662,14 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2576 sr_entries = (((sr_latency_ns / line_time_us) + 1) * 2662 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2577 pixel_size * sr_hdisplay) / 1000; 2663 pixel_size * sr_hdisplay) / 1000;
2578 sr_entries = roundup(sr_entries / cacheline_size, 1); 2664 sr_entries = roundup(sr_entries / cacheline_size, 1);
2579 DRM_DEBUG("self-refresh entries: %d\n", sr_entries); 2665 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2580 srwm = total_size - sr_entries; 2666 srwm = total_size - sr_entries;
2581 if (srwm < 0) 2667 if (srwm < 0)
2582 srwm = 1; 2668 srwm = 1;
2583 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); 2669 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2584 } 2670 }
2585 2671
2586 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2672 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2587 planea_wm, planeb_wm, cwm, srwm); 2673 planea_wm, planeb_wm, cwm, srwm);
2588 2674
2589 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 2675 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
@@ -2610,7 +2696,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2610 pixel_size, latency_ns); 2696 pixel_size, latency_ns);
2611 fwater_lo |= (3<<8) | planea_wm; 2697 fwater_lo |= (3<<8) | planea_wm;
2612 2698
2613 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm); 2699 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2614 2700
2615 I915_WRITE(FW_BLC, fwater_lo); 2701 I915_WRITE(FW_BLC, fwater_lo);
2616} 2702}
@@ -2664,11 +2750,11 @@ static void intel_update_watermarks(struct drm_device *dev)
2664 if (crtc->enabled) { 2750 if (crtc->enabled) {
2665 enabled++; 2751 enabled++;
2666 if (intel_crtc->plane == 0) { 2752 if (intel_crtc->plane == 0) {
2667 DRM_DEBUG("plane A (pipe %d) clock: %d\n", 2753 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2668 intel_crtc->pipe, crtc->mode.clock); 2754 intel_crtc->pipe, crtc->mode.clock);
2669 planea_clock = crtc->mode.clock; 2755 planea_clock = crtc->mode.clock;
2670 } else { 2756 } else {
2671 DRM_DEBUG("plane B (pipe %d) clock: %d\n", 2757 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2672 intel_crtc->pipe, crtc->mode.clock); 2758 intel_crtc->pipe, crtc->mode.clock);
2673 planeb_clock = crtc->mode.clock; 2759 planeb_clock = crtc->mode.clock;
2674 } 2760 }
@@ -2782,7 +2868,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2782 2868
2783 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { 2869 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2784 refclk = dev_priv->lvds_ssc_freq * 1000; 2870 refclk = dev_priv->lvds_ssc_freq * 1000;
2785 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); 2871 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2872 refclk / 1000);
2786 } else if (IS_I9XX(dev)) { 2873 } else if (IS_I9XX(dev)) {
2787 refclk = 96000; 2874 refclk = 96000;
2788 if (IS_IGDNG(dev)) 2875 if (IS_IGDNG(dev))
@@ -2805,14 +2892,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2805 return -EINVAL; 2892 return -EINVAL;
2806 } 2893 }
2807 2894
2808 if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) { 2895 if (is_lvds && limit->find_reduced_pll &&
2896 dev_priv->lvds_downclock_avail) {
2809 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t)); 2897 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2810 has_reduced_clock = limit->find_reduced_pll(limit, crtc, 2898 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2811 (adjusted_mode->clock*3/4), 2899 dev_priv->lvds_downclock,
2812 refclk, 2900 refclk,
2813 &reduced_clock); 2901 &reduced_clock);
2902 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2903 /*
2904 * If the different P is found, it means that we can't
2905 * switch the display clock by using the FP0/FP1.
2906 * In such case we will disable the LVDS downclock
2907 * feature.
2908 */
2909 DRM_DEBUG_KMS("Different P is found for "
2910 "LVDS clock/downclock\n");
2911 has_reduced_clock = 0;
2912 }
2814 } 2913 }
2815
2816 /* SDVO TV has fixed PLL values depend on its clock range, 2914 /* SDVO TV has fixed PLL values depend on its clock range,
2817 this mirrors vbios setting. */ 2915 this mirrors vbios setting. */
2818 if (is_sdvo && is_tv) { 2916 if (is_sdvo && is_tv) {
@@ -3040,7 +3138,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3040 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) 3138 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3041 I915_WRITE(PFIT_CONTROL, 0); 3139 I915_WRITE(PFIT_CONTROL, 0);
3042 3140
3043 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3141 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3044 drm_mode_debug_printmodeline(mode); 3142 drm_mode_debug_printmodeline(mode);
3045 3143
3046 /* assign to IGDNG registers */ 3144 /* assign to IGDNG registers */
@@ -3118,14 +3216,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3118 I915_WRITE(fp_reg + 4, fp2); 3216 I915_WRITE(fp_reg + 4, fp2);
3119 intel_crtc->lowfreq_avail = true; 3217 intel_crtc->lowfreq_avail = true;
3120 if (HAS_PIPE_CXSR(dev)) { 3218 if (HAS_PIPE_CXSR(dev)) {
3121 DRM_DEBUG("enabling CxSR downclocking\n"); 3219 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3122 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3220 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3123 } 3221 }
3124 } else { 3222 } else {
3125 I915_WRITE(fp_reg + 4, fp); 3223 I915_WRITE(fp_reg + 4, fp);
3126 intel_crtc->lowfreq_avail = false; 3224 intel_crtc->lowfreq_avail = false;
3127 if (HAS_PIPE_CXSR(dev)) { 3225 if (HAS_PIPE_CXSR(dev)) {
3128 DRM_DEBUG("disabling CxSR downclocking\n"); 3226 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3129 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3227 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3130 } 3228 }
3131 } 3229 }
@@ -3237,11 +3335,11 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3237 size_t addr; 3335 size_t addr;
3238 int ret; 3336 int ret;
3239 3337
3240 DRM_DEBUG("\n"); 3338 DRM_DEBUG_KMS("\n");
3241 3339
3242 /* if we want to turn off the cursor ignore width and height */ 3340 /* if we want to turn off the cursor ignore width and height */
3243 if (!handle) { 3341 if (!handle) {
3244 DRM_DEBUG("cursor off\n"); 3342 DRM_DEBUG_KMS("cursor off\n");
3245 if (IS_MOBILE(dev) || IS_I9XX(dev)) { 3343 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3246 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 3344 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3247 temp |= CURSOR_MODE_DISABLE; 3345 temp |= CURSOR_MODE_DISABLE;
@@ -3575,7 +3673,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3575 7 : 14; 3673 7 : 14;
3576 break; 3674 break;
3577 default: 3675 default:
3578 DRM_DEBUG("Unknown DPLL mode %08x in programmed " 3676 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3579 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 3677 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3580 return 0; 3678 return 0;
3581 } 3679 }
@@ -3661,7 +3759,7 @@ static void intel_gpu_idle_timer(unsigned long arg)
3661 struct drm_device *dev = (struct drm_device *)arg; 3759 struct drm_device *dev = (struct drm_device *)arg;
3662 drm_i915_private_t *dev_priv = dev->dev_private; 3760 drm_i915_private_t *dev_priv = dev->dev_private;
3663 3761
3664 DRM_DEBUG("idle timer fired, downclocking\n"); 3762 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3665 3763
3666 dev_priv->busy = false; 3764 dev_priv->busy = false;
3667 3765
@@ -3676,7 +3774,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3676 return; 3774 return;
3677 3775
3678 if (!dev_priv->render_reclock_avail) { 3776 if (!dev_priv->render_reclock_avail) {
3679 DRM_DEBUG("not reclocking render clock\n"); 3777 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3680 return; 3778 return;
3681 } 3779 }
3682 3780
@@ -3685,7 +3783,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3685 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock); 3783 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3686 else if (IS_I85X(dev)) 3784 else if (IS_I85X(dev))
3687 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock); 3785 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3688 DRM_DEBUG("increasing render clock frequency\n"); 3786 DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3689 3787
3690 /* Schedule downclock */ 3788 /* Schedule downclock */
3691 if (schedule) 3789 if (schedule)
@@ -3701,7 +3799,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3701 return; 3799 return;
3702 3800
3703 if (!dev_priv->render_reclock_avail) { 3801 if (!dev_priv->render_reclock_avail) {
3704 DRM_DEBUG("not reclocking render clock\n"); 3802 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3705 return; 3803 return;
3706 } 3804 }
3707 3805
@@ -3761,7 +3859,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
3761 3859
3762 pci_write_config_word(dev->pdev, HPLLCC, hpllcc); 3860 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3763 } 3861 }
3764 DRM_DEBUG("decreasing render clock frequency\n"); 3862 DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3765} 3863}
3766 3864
3767/* Note that no increase function is needed for this - increase_renderclock() 3865/* Note that no increase function is needed for this - increase_renderclock()
@@ -3795,7 +3893,7 @@ static void intel_crtc_idle_timer(unsigned long arg)
3795 struct drm_crtc *crtc = &intel_crtc->base; 3893 struct drm_crtc *crtc = &intel_crtc->base;
3796 drm_i915_private_t *dev_priv = crtc->dev->dev_private; 3894 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3797 3895
3798 DRM_DEBUG("idle timer fired, downclocking\n"); 3896 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3799 3897
3800 intel_crtc->busy = false; 3898 intel_crtc->busy = false;
3801 3899
@@ -3818,7 +3916,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3818 return; 3916 return;
3819 3917
3820 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 3918 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3821 DRM_DEBUG("upclocking LVDS\n"); 3919 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3822 3920
3823 /* Unlock panel regs */ 3921 /* Unlock panel regs */
3824 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3922 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3829,7 +3927,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3829 intel_wait_for_vblank(dev); 3927 intel_wait_for_vblank(dev);
3830 dpll = I915_READ(dpll_reg); 3928 dpll = I915_READ(dpll_reg);
3831 if (dpll & DISPLAY_RATE_SELECT_FPA1) 3929 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3832 DRM_DEBUG("failed to upclock LVDS!\n"); 3930 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3833 3931
3834 /* ...and lock them again */ 3932 /* ...and lock them again */
3835 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3933 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -3861,7 +3959,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3861 * the manual case. 3959 * the manual case.
3862 */ 3960 */
3863 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 3961 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3864 DRM_DEBUG("downclocking LVDS\n"); 3962 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3865 3963
3866 /* Unlock panel regs */ 3964 /* Unlock panel regs */
3867 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16)); 3965 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
@@ -3872,7 +3970,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
3872 intel_wait_for_vblank(dev); 3970 intel_wait_for_vblank(dev);
3873 dpll = I915_READ(dpll_reg); 3971 dpll = I915_READ(dpll_reg);
3874 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 3972 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3875 DRM_DEBUG("failed to downclock LVDS!\n"); 3973 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3876 3974
3877 /* ...and lock them again */ 3975 /* ...and lock them again */
3878 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); 3976 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
@@ -4013,7 +4111,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
4013 intel_crtc->pipe = pipe; 4111 intel_crtc->pipe = pipe;
4014 intel_crtc->plane = pipe; 4112 intel_crtc->plane = pipe;
4015 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) { 4113 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4016 DRM_DEBUG("swapping pipes & planes for FBC\n"); 4114 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4017 intel_crtc->plane = ((pipe == 0) ? 1 : 0); 4115 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4018 } 4116 }
4019 4117
@@ -4121,7 +4219,7 @@ static void intel_setup_outputs(struct drm_device *dev)
4121 if (I915_READ(PCH_DP_D) & DP_DETECTED) 4219 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4122 intel_dp_init(dev, PCH_DP_D); 4220 intel_dp_init(dev, PCH_DP_D);
4123 4221
4124 } else if (IS_I9XX(dev)) { 4222 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4125 bool found = false; 4223 bool found = false;
4126 4224
4127 if (I915_READ(SDVOB) & SDVO_DETECTED) { 4225 if (I915_READ(SDVOB) & SDVO_DETECTED) {
@@ -4148,10 +4246,10 @@ static void intel_setup_outputs(struct drm_device *dev)
4148 4246
4149 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) 4247 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4150 intel_dp_init(dev, DP_D); 4248 intel_dp_init(dev, DP_D);
4151 } else 4249 } else if (IS_I8XX(dev))
4152 intel_dvo_init(dev); 4250 intel_dvo_init(dev);
4153 4251
4154 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) 4252 if (SUPPORTS_TV(dev))
4155 intel_tv_init(dev); 4253 intel_tv_init(dev);
4156 4254
4157 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4255 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
@@ -4294,11 +4392,47 @@ void intel_init_clock_gating(struct drm_device *dev)
4294 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4392 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4295 DSTATE_DOT_CLOCK_GATING; 4393 DSTATE_DOT_CLOCK_GATING;
4296 I915_WRITE(D_STATE, dstate); 4394 I915_WRITE(D_STATE, dstate);
4297 } else if (IS_I855(dev) || IS_I865G(dev)) { 4395 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4298 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4396 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4299 } else if (IS_I830(dev)) { 4397 } else if (IS_I830(dev)) {
4300 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4398 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4301 } 4399 }
4400
4401 /*
4402 * GPU can automatically power down the render unit if given a page
4403 * to save state.
4404 */
4405 if (I915_HAS_RC6(dev)) {
4406 struct drm_gem_object *pwrctx;
4407 struct drm_i915_gem_object *obj_priv;
4408 int ret;
4409
4410 pwrctx = drm_gem_object_alloc(dev, 4096);
4411 if (!pwrctx) {
4412 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4413 goto out;
4414 }
4415
4416 ret = i915_gem_object_pin(pwrctx, 4096);
4417 if (ret) {
4418 DRM_ERROR("failed to pin power context: %d\n", ret);
4419 drm_gem_object_unreference(pwrctx);
4420 goto out;
4421 }
4422
4423 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4424
4425 obj_priv = pwrctx->driver_private;
4426
4427 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4428 I915_WRITE(MCHBAR_RENDER_STANDBY,
4429 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4430
4431 dev_priv->pwrctx = pwrctx;
4432 }
4433
4434out:
4435 return;
4302} 4436}
4303 4437
4304/* Set up chip specific display functions */ 4438/* Set up chip specific display functions */
@@ -4327,7 +4461,7 @@ static void intel_init_display(struct drm_device *dev)
4327 } 4461 }
4328 4462
4329 /* Returns the core display clock speed */ 4463 /* Returns the core display clock speed */
4330 if (IS_I945G(dev)) 4464 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
4331 dev_priv->display.get_display_clock_speed = 4465 dev_priv->display.get_display_clock_speed =
4332 i945_get_display_clock_speed; 4466 i945_get_display_clock_speed;
4333 else if (IS_I915G(dev)) 4467 else if (IS_I915G(dev))
@@ -4342,7 +4476,7 @@ static void intel_init_display(struct drm_device *dev)
4342 else if (IS_I865G(dev)) 4476 else if (IS_I865G(dev))
4343 dev_priv->display.get_display_clock_speed = 4477 dev_priv->display.get_display_clock_speed =
4344 i865_get_display_clock_speed; 4478 i865_get_display_clock_speed;
4345 else if (IS_I855(dev)) 4479 else if (IS_I85X(dev))
4346 dev_priv->display.get_display_clock_speed = 4480 dev_priv->display.get_display_clock_speed =
4347 i855_get_display_clock_speed; 4481 i855_get_display_clock_speed;
4348 else /* 852, 830 */ 4482 else /* 852, 830 */
@@ -4406,7 +4540,7 @@ void intel_modeset_init(struct drm_device *dev)
4406 num_pipe = 2; 4540 num_pipe = 2;
4407 else 4541 else
4408 num_pipe = 1; 4542 num_pipe = 1;
4409 DRM_DEBUG("%d display pipe%s available.\n", 4543 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4410 num_pipe, num_pipe > 1 ? "s" : ""); 4544 num_pipe, num_pipe > 1 ? "s" : "");
4411 4545
4412 if (IS_I85X(dev)) 4546 if (IS_I85X(dev))
@@ -4425,6 +4559,8 @@ void intel_modeset_init(struct drm_device *dev)
4425 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 4559 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4426 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 4560 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4427 (unsigned long)dev); 4561 (unsigned long)dev);
4562
4563 intel_setup_overlay(dev);
4428} 4564}
4429 4565
4430void intel_modeset_cleanup(struct drm_device *dev) 4566void intel_modeset_cleanup(struct drm_device *dev)
@@ -4448,11 +4584,21 @@ void intel_modeset_cleanup(struct drm_device *dev)
4448 intel_increase_renderclock(dev, false); 4584 intel_increase_renderclock(dev, false);
4449 del_timer_sync(&dev_priv->idle_timer); 4585 del_timer_sync(&dev_priv->idle_timer);
4450 4586
4451 mutex_unlock(&dev->struct_mutex);
4452
4453 if (dev_priv->display.disable_fbc) 4587 if (dev_priv->display.disable_fbc)
4454 dev_priv->display.disable_fbc(dev); 4588 dev_priv->display.disable_fbc(dev);
4455 4589
4590 if (dev_priv->pwrctx) {
4591 struct drm_i915_gem_object *obj_priv;
4592
4593 obj_priv = dev_priv->pwrctx->driver_private;
4594 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4595 I915_READ(PWRCTXA);
4596 i915_gem_object_unpin(dev_priv->pwrctx);
4597 drm_gem_object_unreference(dev_priv->pwrctx);
4598 }
4599
4600 mutex_unlock(&dev->struct_mutex);
4601
4456 drm_mode_config_cleanup(dev); 4602 drm_mode_config_cleanup(dev);
4457} 4603}
4458 4604
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d83447557f9b..a86af0d24fd3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -35,6 +35,7 @@
35#include "i915_drv.h" 35#include "i915_drv.h"
36#include "intel_dp.h" 36#include "intel_dp.h"
37 37
38
38#define DP_LINK_STATUS_SIZE 6 39#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40 41
@@ -282,7 +283,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
282 /* Timeouts occur when the device isn't connected, so they're 283 /* Timeouts occur when the device isn't connected, so they're
283 * "normal" -- don't fill the kernel log with these */ 284 * "normal" -- don't fill the kernel log with these */
284 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 285 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
285 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status); 286 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
286 return -ETIMEDOUT; 287 return -ETIMEDOUT;
287 } 288 }
288 289
@@ -435,7 +436,8 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
435 dp_priv->link_bw = bws[clock]; 436 dp_priv->link_bw = bws[clock];
436 dp_priv->lane_count = lane_count; 437 dp_priv->lane_count = lane_count;
437 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 438 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
438 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n", 439 DRM_DEBUG_KMS("Display port link bw %02x lane "
440 "count %d clock %d\n",
439 dp_priv->link_bw, dp_priv->lane_count, 441 dp_priv->link_bw, dp_priv->lane_count,
440 adjusted_mode->clock); 442 adjusted_mode->clock);
441 return true; 443 return true;
@@ -611,7 +613,7 @@ static void igdng_edp_backlight_on (struct drm_device *dev)
611 struct drm_i915_private *dev_priv = dev->dev_private; 613 struct drm_i915_private *dev_priv = dev->dev_private;
612 u32 pp; 614 u32 pp;
613 615
614 DRM_DEBUG("\n"); 616 DRM_DEBUG_KMS("\n");
615 pp = I915_READ(PCH_PP_CONTROL); 617 pp = I915_READ(PCH_PP_CONTROL);
616 pp |= EDP_BLC_ENABLE; 618 pp |= EDP_BLC_ENABLE;
617 I915_WRITE(PCH_PP_CONTROL, pp); 619 I915_WRITE(PCH_PP_CONTROL, pp);
@@ -622,7 +624,7 @@ static void igdng_edp_backlight_off (struct drm_device *dev)
622 struct drm_i915_private *dev_priv = dev->dev_private; 624 struct drm_i915_private *dev_priv = dev->dev_private;
623 u32 pp; 625 u32 pp;
624 626
625 DRM_DEBUG("\n"); 627 DRM_DEBUG_KMS("\n");
626 pp = I915_READ(PCH_PP_CONTROL); 628 pp = I915_READ(PCH_PP_CONTROL);
627 pp &= ~EDP_BLC_ENABLE; 629 pp &= ~EDP_BLC_ENABLE;
628 I915_WRITE(PCH_PP_CONTROL, pp); 630 I915_WRITE(PCH_PP_CONTROL, pp);
@@ -1010,7 +1012,7 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1010 struct drm_i915_private *dev_priv = dev->dev_private; 1012 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1013 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1012 1014
1013 DRM_DEBUG("\n"); 1015 DRM_DEBUG_KMS("\n");
1014 1016
1015 if (IS_eDP(intel_output)) { 1017 if (IS_eDP(intel_output)) {
1016 DP &= ~DP_PLL_ENABLE; 1018 DP &= ~DP_PLL_ENABLE;
@@ -1227,7 +1229,53 @@ intel_dp_hot_plug(struct intel_output *intel_output)
1227 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1229 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1228 intel_dp_check_link_status(intel_output); 1230 intel_dp_check_link_status(intel_output);
1229} 1231}
1230 1232/*
1233 * Enumerate the child dev array parsed from VBT to check whether
1234 * the given DP is present.
1235 * If it is present, return 1.
1236 * If it is not present, return false.
1237 * If no child dev is parsed from VBT, it is assumed that the given
1238 * DP is present.
1239 */
1240int dp_is_present_in_vbt(struct drm_device *dev, int dp_reg)
1241{
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 struct child_device_config *p_child;
1244 int i, dp_port, ret;
1245
1246 if (!dev_priv->child_dev_num)
1247 return 1;
1248
1249 dp_port = 0;
1250 if (dp_reg == DP_B || PCH_DP_B)
1251 dp_port = PORT_IDPB;
1252 else if (dp_reg == DP_C || PCH_DP_C)
1253 dp_port = PORT_IDPC;
1254 else if (dp_reg == DP_D || PCH_DP_D)
1255 dp_port = PORT_IDPD;
1256
1257 ret = 0;
1258 for (i = 0; i < dev_priv->child_dev_num; i++) {
1259 p_child = dev_priv->child_dev + i;
1260 /*
1261 * If the device type is not DP, continue.
1262 */
1263 if (p_child->device_type != DEVICE_TYPE_DP &&
1264 p_child->device_type != DEVICE_TYPE_eDP)
1265 continue;
1266 /* Find the eDP port */
1267 if (dp_reg == DP_A && p_child->device_type == DEVICE_TYPE_eDP) {
1268 ret = 1;
1269 break;
1270 }
1271 /* Find the DP port */
1272 if (p_child->dvo_port == dp_port) {
1273 ret = 1;
1274 break;
1275 }
1276 }
1277 return ret;
1278}
1231void 1279void
1232intel_dp_init(struct drm_device *dev, int output_reg) 1280intel_dp_init(struct drm_device *dev, int output_reg)
1233{ 1281{
@@ -1237,6 +1285,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1237 struct intel_dp_priv *dp_priv; 1285 struct intel_dp_priv *dp_priv;
1238 const char *name = NULL; 1286 const char *name = NULL;
1239 1287
1288 if (!dp_is_present_in_vbt(dev, output_reg)) {
1289 DRM_DEBUG_KMS("DP is not present. Ignore it\n");
1290 return;
1291 }
1240 intel_output = kcalloc(sizeof(struct intel_output) + 1292 intel_output = kcalloc(sizeof(struct intel_output) +
1241 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1293 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1242 if (!intel_output) 1294 if (!intel_output)
diff --git a/drivers/gpu/drm/i915/intel_dp_i2c.c b/drivers/gpu/drm/i915/intel_dp_i2c.c
index a63b6f57d2d4..a57273ade677 100644
--- a/drivers/gpu/drm/i915/intel_dp_i2c.c
+++ b/drivers/gpu/drm/i915/intel_dp_i2c.c
@@ -85,7 +85,7 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
85 msg, msg_bytes, 85 msg, msg_bytes,
86 reply, reply_bytes); 86 reply, reply_bytes);
87 if (ret < 0) { 87 if (ret < 0) {
88 DRM_DEBUG("aux_ch failed %d\n", ret); 88 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
89 return ret; 89 return ret;
90 } 90 }
91 switch (reply[0] & AUX_I2C_REPLY_MASK) { 91 switch (reply[0] & AUX_I2C_REPLY_MASK) {
@@ -95,10 +95,10 @@ i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
95 } 95 }
96 return reply_bytes - 1; 96 return reply_bytes - 1;
97 case AUX_I2C_REPLY_NACK: 97 case AUX_I2C_REPLY_NACK:
98 DRM_DEBUG("aux_ch nack\n"); 98 DRM_DEBUG_KMS("aux_ch nack\n");
99 return -EREMOTEIO; 99 return -EREMOTEIO;
100 case AUX_I2C_REPLY_DEFER: 100 case AUX_I2C_REPLY_DEFER:
101 DRM_DEBUG("aux_ch defer\n"); 101 DRM_DEBUG_KMS("aux_ch defer\n");
102 udelay(100); 102 udelay(100);
103 break; 103 break;
104 default: 104 default:
@@ -224,7 +224,7 @@ i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
224 if (ret >= 0) 224 if (ret >= 0)
225 ret = num; 225 ret = num;
226 i2c_algo_dp_aux_stop(adapter, reading); 226 i2c_algo_dp_aux_stop(adapter, reading);
227 DRM_DEBUG("dp_aux_xfer return %d\n", ret); 227 DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
228 return ret; 228 return ret;
229} 229}
230 230
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ef61fe9507e2..497240581c6a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -110,6 +110,32 @@ struct intel_output {
110 int clone_mask; 110 int clone_mask;
111}; 111};
112 112
113struct intel_crtc;
114struct intel_overlay {
115 struct drm_device *dev;
116 struct intel_crtc *crtc;
117 struct drm_i915_gem_object *vid_bo;
118 struct drm_i915_gem_object *old_vid_bo;
119 int active;
120 int pfit_active;
121 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
122 u32 color_key;
123 u32 brightness, contrast, saturation;
124 u32 old_xscale, old_yscale;
125 /* register access */
126 u32 flip_addr;
127 struct drm_i915_gem_object *reg_bo;
128 void *virt_addr;
129 /* flip handling */
130 uint32_t last_flip_req;
131 int hw_wedged;
132#define HW_WEDGED 1
133#define NEEDS_WAIT_FOR_FLIP 2
134#define RELEASE_OLD_VID 3
135#define SWITCH_OFF_STAGE_1 4
136#define SWITCH_OFF_STAGE_2 5
137};
138
113struct intel_crtc { 139struct intel_crtc {
114 struct drm_crtc base; 140 struct drm_crtc base;
115 enum pipe pipe; 141 enum pipe pipe;
@@ -121,6 +147,7 @@ struct intel_crtc {
121 bool busy; /* is scanout buffer being updated frequently? */ 147 bool busy; /* is scanout buffer being updated frequently? */
122 struct timer_list idle_timer; 148 struct timer_list idle_timer;
123 bool lowfreq_avail; 149 bool lowfreq_avail;
150 struct intel_overlay *overlay;
124}; 151};
125 152
126#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 153#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -148,6 +175,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
148extern void intel_edp_link_config (struct intel_output *, int *, int *); 175extern void intel_edp_link_config (struct intel_output *, int *, int *);
149 176
150 177
178extern int intel_panel_fitter_pipe (struct drm_device *dev);
151extern void intel_crtc_load_lut(struct drm_crtc *crtc); 179extern void intel_crtc_load_lut(struct drm_crtc *crtc);
152extern void intel_encoder_prepare (struct drm_encoder *encoder); 180extern void intel_encoder_prepare (struct drm_encoder *encoder);
153extern void intel_encoder_commit (struct drm_encoder *encoder); 181extern void intel_encoder_commit (struct drm_encoder *encoder);
@@ -183,4 +211,13 @@ extern int intel_framebuffer_create(struct drm_device *dev,
183 struct drm_framebuffer **fb, 211 struct drm_framebuffer **fb,
184 struct drm_gem_object *obj); 212 struct drm_gem_object *obj);
185 213
214extern void intel_setup_overlay(struct drm_device *dev);
215extern void intel_cleanup_overlay(struct drm_device *dev);
216extern int intel_overlay_switch_off(struct intel_overlay *overlay);
217extern int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
218 int interruptible);
219extern int intel_overlay_put_image(struct drm_device *dev, void *data,
220 struct drm_file *file_priv);
221extern int intel_overlay_attrs(struct drm_device *dev, void *data,
222 struct drm_file *file_priv);
186#endif /* __INTEL_DRV_H__ */ 223#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 2b0fe54cd92c..d4823cc87895 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -230,8 +230,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
230 par->intel_fb = intel_fb; 230 par->intel_fb = intel_fb;
231 231
232 /* To allow resizeing without swapping buffers */ 232 /* To allow resizeing without swapping buffers */
233 DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width, 233 DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n",
234 intel_fb->base.height, obj_priv->gtt_offset, fbo); 234 intel_fb->base.width, intel_fb->base.height,
235 obj_priv->gtt_offset, fbo);
235 236
236 mutex_unlock(&dev->struct_mutex); 237 mutex_unlock(&dev->struct_mutex);
237 return 0; 238 return 0;
@@ -249,7 +250,7 @@ int intelfb_probe(struct drm_device *dev)
249{ 250{
250 int ret; 251 int ret;
251 252
252 DRM_DEBUG("\n"); 253 DRM_DEBUG_KMS("\n");
253 ret = drm_fb_helper_single_fb_probe(dev, 32, intelfb_create); 254 ret = drm_fb_helper_single_fb_probe(dev, 32, intelfb_create);
254 return ret; 255 return ret;
255} 256}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 663ab6de0b58..2ff5d03b44ef 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
77 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 77 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
78 u32 temp; 78 u32 temp;
79 79
80 if (mode != DRM_MODE_DPMS_ON) { 80 temp = I915_READ(hdmi_priv->sdvox_reg);
81 temp = I915_READ(hdmi_priv->sdvox_reg); 81
82 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
83 * we do this anyway which shows more stable in testing.
84 */
85 if (IS_IGDNG(dev)) {
82 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); 86 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
87 POSTING_READ(hdmi_priv->sdvox_reg);
88 }
89
90 if (mode != DRM_MODE_DPMS_ON) {
91 temp &= ~SDVO_ENABLE;
83 } else { 92 } else {
84 temp = I915_READ(hdmi_priv->sdvox_reg); 93 temp |= SDVO_ENABLE;
85 I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE);
86 } 94 }
95
96 I915_WRITE(hdmi_priv->sdvox_reg, temp);
87 POSTING_READ(hdmi_priv->sdvox_reg); 97 POSTING_READ(hdmi_priv->sdvox_reg);
98
99 /* HW workaround, need to write this twice for issue that may result
100 * in first write getting masked.
101 */
102 if (IS_IGDNG(dev)) {
103 I915_WRITE(hdmi_priv->sdvox_reg, temp);
104 POSTING_READ(hdmi_priv->sdvox_reg);
105 }
88} 106}
89 107
90static void intel_hdmi_save(struct drm_connector *connector) 108static void intel_hdmi_save(struct drm_connector *connector)
@@ -207,7 +225,52 @@ static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
207 .destroy = intel_hdmi_enc_destroy, 225 .destroy = intel_hdmi_enc_destroy,
208}; 226};
209 227
210 228/*
229 * Enumerate the child dev array parsed from VBT to check whether
230 * the given HDMI is present.
231 * If it is present, return 1.
232 * If it is not present, return false.
233 * If no child dev is parsed from VBT, it assumes that the given
234 * HDMI is present.
235 */
236int hdmi_is_present_in_vbt(struct drm_device *dev, int hdmi_reg)
237{
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 struct child_device_config *p_child;
240 int i, hdmi_port, ret;
241
242 if (!dev_priv->child_dev_num)
243 return 1;
244
245 if (hdmi_reg == SDVOB)
246 hdmi_port = DVO_B;
247 else if (hdmi_reg == SDVOC)
248 hdmi_port = DVO_C;
249 else if (hdmi_reg == HDMIB)
250 hdmi_port = DVO_B;
251 else if (hdmi_reg == HDMIC)
252 hdmi_port = DVO_C;
253 else if (hdmi_reg == HDMID)
254 hdmi_port = DVO_D;
255 else
256 return 0;
257
258 ret = 0;
259 for (i = 0; i < dev_priv->child_dev_num; i++) {
260 p_child = dev_priv->child_dev + i;
261 /*
262 * If the device type is not HDMI, continue.
263 */
264 if (p_child->device_type != DEVICE_TYPE_HDMI)
265 continue;
266 /* Find the HDMI port */
267 if (p_child->dvo_port == hdmi_port) {
268 ret = 1;
269 break;
270 }
271 }
272 return ret;
273}
211void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 274void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
212{ 275{
213 struct drm_i915_private *dev_priv = dev->dev_private; 276 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -215,6 +278,10 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
215 struct intel_output *intel_output; 278 struct intel_output *intel_output;
216 struct intel_hdmi_priv *hdmi_priv; 279 struct intel_hdmi_priv *hdmi_priv;
217 280
281 if (!hdmi_is_present_in_vbt(dev, sdvox_reg)) {
282 DRM_DEBUG_KMS("HDMI is not present. Ignored it \n");
283 return;
284 }
218 intel_output = kcalloc(sizeof(struct intel_output) + 285 intel_output = kcalloc(sizeof(struct intel_output) +
219 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); 286 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL);
220 if (!intel_output) 287 if (!intel_output)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 05598ae10c4b..7fec70145a3d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -914,6 +914,101 @@ static int intel_lid_present(void)
914#endif 914#endif
915 915
916/** 916/**
917 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
918 * @dev: drm device
919 * @connector: LVDS connector
920 *
921 * Find the reduced downclock for LVDS in EDID.
922 */
923static void intel_find_lvds_downclock(struct drm_device *dev,
924 struct drm_connector *connector)
925{
926 struct drm_i915_private *dev_priv = dev->dev_private;
927 struct drm_display_mode *scan, *panel_fixed_mode;
928 int temp_downclock;
929
930 panel_fixed_mode = dev_priv->panel_fixed_mode;
931 temp_downclock = panel_fixed_mode->clock;
932
933 mutex_lock(&dev->mode_config.mutex);
934 list_for_each_entry(scan, &connector->probed_modes, head) {
935 /*
936 * If one mode has the same resolution with the fixed_panel
937 * mode while they have the different refresh rate, it means
938 * that the reduced downclock is found for the LVDS. In such
939 * case we can set the different FPx0/1 to dynamically select
940 * between low and high frequency.
941 */
942 if (scan->hdisplay == panel_fixed_mode->hdisplay &&
943 scan->hsync_start == panel_fixed_mode->hsync_start &&
944 scan->hsync_end == panel_fixed_mode->hsync_end &&
945 scan->htotal == panel_fixed_mode->htotal &&
946 scan->vdisplay == panel_fixed_mode->vdisplay &&
947 scan->vsync_start == panel_fixed_mode->vsync_start &&
948 scan->vsync_end == panel_fixed_mode->vsync_end &&
949 scan->vtotal == panel_fixed_mode->vtotal) {
950 if (scan->clock < temp_downclock) {
951 /*
952 * The downclock is already found. But we
953 * expect to find the lower downclock.
954 */
955 temp_downclock = scan->clock;
956 }
957 }
958 }
959 mutex_unlock(&dev->mode_config.mutex);
960 if (temp_downclock < panel_fixed_mode->clock) {
961 /* We found the downclock for LVDS. */
962 dev_priv->lvds_downclock_avail = 1;
963 dev_priv->lvds_downclock = temp_downclock;
964 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
965 "Normal clock %dKhz, downclock %dKhz\n",
966 panel_fixed_mode->clock, temp_downclock);
967 }
968 return;
969}
970
971/*
972 * Enumerate the child dev array parsed from VBT to check whether
973 * the LVDS is present.
974 * If it is present, return 1.
975 * If it is not present, return false.
976 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
977 * Note: The addin_offset should also be checked for LVDS panel.
978 * Only when it is non-zero, it is assumed that it is present.
979 */
980int lvds_is_present_in_vbt(struct drm_device *dev)
981{
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct child_device_config *p_child;
984 int i, ret;
985
986 if (!dev_priv->child_dev_num)
987 return 1;
988
989 ret = 0;
990 for (i = 0; i < dev_priv->child_dev_num; i++) {
991 p_child = dev_priv->child_dev + i;
992 /*
993 * If the device type is not LFP, continue.
994 * If the device type is 0x22, it is also regarded as LFP.
995 */
996 if (p_child->device_type != DEVICE_TYPE_INT_LFP &&
997 p_child->device_type != DEVICE_TYPE_LFP)
998 continue;
999
1000 /* The addin_offset should be checked. Only when it is
1001 * non-zero, it is regarded as present.
1002 */
1003 if (p_child->addin_offset) {
1004 ret = 1;
1005 break;
1006 }
1007 }
1008 return ret;
1009}
1010
1011/**
917 * intel_lvds_init - setup LVDS connectors on this device 1012 * intel_lvds_init - setup LVDS connectors on this device
918 * @dev: drm device 1013 * @dev: drm device
919 * 1014 *
@@ -936,6 +1031,10 @@ void intel_lvds_init(struct drm_device *dev)
936 if (dmi_check_system(intel_no_lvds)) 1031 if (dmi_check_system(intel_no_lvds))
937 return; 1032 return;
938 1033
1034 if (!lvds_is_present_in_vbt(dev)) {
1035 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
1036 return;
1037 }
939 /* Assume that any device without an ACPI LID device also doesn't 1038 /* Assume that any device without an ACPI LID device also doesn't
940 * have an integrated LVDS. We would be better off parsing the BIOS 1039 * have an integrated LVDS. We would be better off parsing the BIOS
941 * to get a reliable indicator, but that code isn't written yet. 1040 * to get a reliable indicator, but that code isn't written yet.
@@ -950,7 +1049,7 @@ void intel_lvds_init(struct drm_device *dev)
950 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 1049 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
951 return; 1050 return;
952 if (dev_priv->edp_support) { 1051 if (dev_priv->edp_support) {
953 DRM_DEBUG("disable LVDS for eDP support\n"); 1052 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
954 return; 1053 return;
955 } 1054 }
956 gpio = PCH_GPIOC; 1055 gpio = PCH_GPIOC;
@@ -1023,6 +1122,7 @@ void intel_lvds_init(struct drm_device *dev)
1023 dev_priv->panel_fixed_mode = 1122 dev_priv->panel_fixed_mode =
1024 drm_mode_duplicate(dev, scan); 1123 drm_mode_duplicate(dev, scan);
1025 mutex_unlock(&dev->mode_config.mutex); 1124 mutex_unlock(&dev->mode_config.mutex);
1125 intel_find_lvds_downclock(dev, connector);
1026 goto out; 1126 goto out;
1027 } 1127 }
1028 mutex_unlock(&dev->mode_config.mutex); 1128 mutex_unlock(&dev->mode_config.mutex);
@@ -1082,7 +1182,7 @@ out:
1082 } 1182 }
1083 dev_priv->lid_notifier.notifier_call = intel_lid_notify; 1183 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1084 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { 1184 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
1085 DRM_DEBUG("lid notifier registration failed\n"); 1185 DRM_DEBUG_KMS("lid notifier registration failed\n");
1086 dev_priv->lid_notifier.notifier_call = NULL; 1186 dev_priv->lid_notifier.notifier_call = NULL;
1087 } 1187 }
1088 drm_sysfs_connector_add(connector); 1188 drm_sysfs_connector_add(connector);
@@ -1093,5 +1193,6 @@ failed:
1093 if (intel_output->ddc_bus) 1193 if (intel_output->ddc_bus)
1094 intel_i2c_destroy(intel_output->ddc_bus); 1194 intel_i2c_destroy(intel_output->ddc_bus);
1095 drm_connector_cleanup(connector); 1195 drm_connector_cleanup(connector);
1196 drm_encoder_cleanup(encoder);
1096 kfree(intel_output); 1197 kfree(intel_output);
1097} 1198}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
new file mode 100644
index 000000000000..49110b3aab6a
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -0,0 +1,1416 @@
1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_reg.h"
33#include "intel_drv.h"
34
35/* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39#define IMAGE_MAX_WIDTH 2048
40#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41/* on 830 and 845 these large limits result in the card hanging */
42#define IMAGE_MAX_WIDTH_LEGACY 1024
43#define IMAGE_MAX_HEIGHT_LEGACY 1088
44
45/* overlay register definitions */
46/* OCMD register */
47#define OCMD_TILED_SURFACE (0x1<<19)
48#define OCMD_MIRROR_MASK (0x3<<17)
49#define OCMD_MIRROR_MODE (0x3<<17)
50#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51#define OCMD_MIRROR_VERTICAL (0x2<<17)
52#define OCMD_MIRROR_BOTH (0x3<<17)
53#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61#define OCMD_YUV_422_PACKED (0x8<<10)
62#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_420_PLANAR (0xc<<10)
64#define OCMD_YUV_422_PLANAR (0xd<<10)
65#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68#define OCMD_BUF_TYPE_MASK (Ox1<<5)
69#define OCMD_BUF_TYPE_FRAME (0x0<<5)
70#define OCMD_BUF_TYPE_FIELD (0x1<<5)
71#define OCMD_TEST_MODE (0x1<<4)
72#define OCMD_BUFFER_SELECT (0x3<<2)
73#define OCMD_BUFFER0 (0x0<<2)
74#define OCMD_BUFFER1 (0x1<<2)
75#define OCMD_FIELD_SELECT (0x1<<2)
76#define OCMD_FIELD0 (0x0<<1)
77#define OCMD_FIELD1 (0x1<<1)
78#define OCMD_ENABLE (0x1<<0)
79
80/* OCONFIG register */
81#define OCONF_PIPE_MASK (0x1<<18)
82#define OCONF_PIPE_A (0x0<<18)
83#define OCONF_PIPE_B (0x1<<18)
84#define OCONF_GAMMA2_ENABLE (0x1<<16)
85#define OCONF_CSC_MODE_BT601 (0x0<<5)
86#define OCONF_CSC_MODE_BT709 (0x1<<5)
87#define OCONF_CSC_BYPASS (0x1<<4)
88#define OCONF_CC_OUT_8BIT (0x1<<3)
89#define OCONF_TEST_MODE (0x1<<2)
90#define OCONF_THREE_LINE_BUFFER (0x1<<0)
91#define OCONF_TWO_LINE_BUFFER (0x0<<0)
92
93/* DCLRKM (dst-key) register */
94#define DST_KEY_ENABLE (0x1<<31)
95#define CLK_RGB24_MASK 0x0
96#define CLK_RGB16_MASK 0x070307
97#define CLK_RGB15_MASK 0x070707
98#define CLK_RGB8I_MASK 0xffffff
99
100#define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102#define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104
105/* overlay flip addr flag */
106#define OFC_UPDATE 0x1
107
108/* polyphase filter coefficients */
109#define N_HORIZ_Y_TAPS 5
110#define N_VERT_Y_TAPS 3
111#define N_HORIZ_UV_TAPS 3
112#define N_VERT_UV_TAPS 3
113#define N_PHASES 17
114#define MAX_TAPS 5
115
116/* memory bufferd overlay registers */
117struct overlay_registers {
118 u32 OBUF_0Y;
119 u32 OBUF_1Y;
120 u32 OBUF_0U;
121 u32 OBUF_0V;
122 u32 OBUF_1U;
123 u32 OBUF_1V;
124 u32 OSTRIDE;
125 u32 YRGB_VPH;
126 u32 UV_VPH;
127 u32 HORZ_PH;
128 u32 INIT_PHS;
129 u32 DWINPOS;
130 u32 DWINSZ;
131 u32 SWIDTH;
132 u32 SWIDTHSW;
133 u32 SHEIGHT;
134 u32 YRGBSCALE;
135 u32 UVSCALE;
136 u32 OCLRC0;
137 u32 OCLRC1;
138 u32 DCLRKV;
139 u32 DCLRKM;
140 u32 SCLRKVH;
141 u32 SCLRKVL;
142 u32 SCLRKEN;
143 u32 OCONFIG;
144 u32 OCMD;
145 u32 RESERVED1; /* 0x6C */
146 u32 OSTART_0Y;
147 u32 OSTART_1Y;
148 u32 OSTART_0U;
149 u32 OSTART_0V;
150 u32 OSTART_1U;
151 u32 OSTART_1V;
152 u32 OTILEOFF_0Y;
153 u32 OTILEOFF_1Y;
154 u32 OTILEOFF_0U;
155 u32 OTILEOFF_0V;
156 u32 OTILEOFF_1U;
157 u32 OTILEOFF_1V;
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
169};
170
171/* overlay flip addr flag */
172#define OFC_UPDATE 0x1
173
174#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
175#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IGDNG(dev))
176
177
178static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
179{
180 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
181 struct overlay_registers *regs;
182
183 /* no recursive mappings */
184 BUG_ON(overlay->virt_addr);
185
186 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
187 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
188 overlay->reg_bo->gtt_offset);
189
190 if (!regs) {
191 DRM_ERROR("failed to map overlay regs in GTT\n");
192 return NULL;
193 }
194 } else
195 regs = overlay->reg_bo->phys_obj->handle->vaddr;
196
197 return overlay->virt_addr = regs;
198}
199
200static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
201{
202 struct drm_device *dev = overlay->dev;
203 drm_i915_private_t *dev_priv = dev->dev_private;
204
205 if (OVERLAY_NONPHYSICAL(overlay->dev))
206 io_mapping_unmap_atomic(overlay->virt_addr);
207
208 overlay->virt_addr = NULL;
209
210 I915_READ(OVADD); /* flush wc cashes */
211
212 return;
213}
214
215/* overlay needs to be disable in OCMD reg */
216static int intel_overlay_on(struct intel_overlay *overlay)
217{
218 struct drm_device *dev = overlay->dev;
219 drm_i915_private_t *dev_priv = dev->dev_private;
220 int ret;
221 RING_LOCALS;
222
223 BUG_ON(overlay->active);
224
225 overlay->active = 1;
226 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
227
228 BEGIN_LP_RING(6);
229 OUT_RING(MI_FLUSH);
230 OUT_RING(MI_NOOP);
231 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
232 OUT_RING(overlay->flip_addr | OFC_UPDATE);
233 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
234 OUT_RING(MI_NOOP);
235 ADVANCE_LP_RING();
236
237 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
238 if (overlay->last_flip_req == 0)
239 return -ENOMEM;
240
241 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
242 if (ret != 0)
243 return ret;
244
245 overlay->hw_wedged = 0;
246 overlay->last_flip_req = 0;
247 return 0;
248}
249
250/* overlay needs to be enabled in OCMD reg */
251static void intel_overlay_continue(struct intel_overlay *overlay,
252 bool load_polyphase_filter)
253{
254 struct drm_device *dev = overlay->dev;
255 drm_i915_private_t *dev_priv = dev->dev_private;
256 u32 flip_addr = overlay->flip_addr;
257 u32 tmp;
258 RING_LOCALS;
259
260 BUG_ON(!overlay->active);
261
262 if (load_polyphase_filter)
263 flip_addr |= OFC_UPDATE;
264
265 /* check for underruns */
266 tmp = I915_READ(DOVSTA);
267 if (tmp & (1 << 17))
268 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
269
270 BEGIN_LP_RING(4);
271 OUT_RING(MI_FLUSH);
272 OUT_RING(MI_NOOP);
273 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
274 OUT_RING(flip_addr);
275 ADVANCE_LP_RING();
276
277 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
278}
279
280static int intel_overlay_wait_flip(struct intel_overlay *overlay)
281{
282 struct drm_device *dev = overlay->dev;
283 drm_i915_private_t *dev_priv = dev->dev_private;
284 int ret;
285 u32 tmp;
286 RING_LOCALS;
287
288 if (overlay->last_flip_req != 0) {
289 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
290 if (ret == 0) {
291 overlay->last_flip_req = 0;
292
293 tmp = I915_READ(ISR);
294
295 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
296 return 0;
297 }
298 }
299
300 /* synchronous slowpath */
301 overlay->hw_wedged = RELEASE_OLD_VID;
302
303 BEGIN_LP_RING(2);
304 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
305 OUT_RING(MI_NOOP);
306 ADVANCE_LP_RING();
307
308 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
309 if (overlay->last_flip_req == 0)
310 return -ENOMEM;
311
312 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
313 if (ret != 0)
314 return ret;
315
316 overlay->hw_wedged = 0;
317 overlay->last_flip_req = 0;
318 return 0;
319}
320
321/* overlay needs to be disabled in OCMD reg */
322static int intel_overlay_off(struct intel_overlay *overlay)
323{
324 u32 flip_addr = overlay->flip_addr;
325 struct drm_device *dev = overlay->dev;
326 drm_i915_private_t *dev_priv = dev->dev_private;
327 int ret;
328 RING_LOCALS;
329
330 BUG_ON(!overlay->active);
331
332 /* According to intel docs the overlay hw may hang (when switching
333 * off) without loading the filter coeffs. It is however unclear whether
334 * this applies to the disabling of the overlay or to the switching off
335 * of the hw. Do it in both cases */
336 flip_addr |= OFC_UPDATE;
337
338 /* wait for overlay to go idle */
339 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
340
341 BEGIN_LP_RING(6);
342 OUT_RING(MI_FLUSH);
343 OUT_RING(MI_NOOP);
344 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
345 OUT_RING(flip_addr);
346 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
347 OUT_RING(MI_NOOP);
348 ADVANCE_LP_RING();
349
350 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
351 if (overlay->last_flip_req == 0)
352 return -ENOMEM;
353
354 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
355 if (ret != 0)
356 return ret;
357
358 /* turn overlay off */
359 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
360
361 BEGIN_LP_RING(6);
362 OUT_RING(MI_FLUSH);
363 OUT_RING(MI_NOOP);
364 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
365 OUT_RING(flip_addr);
366 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
367 OUT_RING(MI_NOOP);
368 ADVANCE_LP_RING();
369
370 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
371 if (overlay->last_flip_req == 0)
372 return -ENOMEM;
373
374 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
375 if (ret != 0)
376 return ret;
377
378 overlay->hw_wedged = 0;
379 overlay->last_flip_req = 0;
380 return ret;
381}
382
383static void intel_overlay_off_tail(struct intel_overlay *overlay)
384{
385 struct drm_gem_object *obj;
386
387 /* never have the overlay hw on without showing a frame */
388 BUG_ON(!overlay->vid_bo);
389 obj = overlay->vid_bo->obj;
390
391 i915_gem_object_unpin(obj);
392 drm_gem_object_unreference(obj);
393 overlay->vid_bo = NULL;
394
395 overlay->crtc->overlay = NULL;
396 overlay->crtc = NULL;
397 overlay->active = 0;
398}
399
400/* recover from an interruption due to a signal
401 * We have to be careful not to repeat work forever an make forward progess. */
402int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
403 int interruptible)
404{
405 struct drm_device *dev = overlay->dev;
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 struct drm_gem_object *obj;
408 u32 flip_addr;
409 int ret;
410 RING_LOCALS;
411
412 if (overlay->hw_wedged == HW_WEDGED)
413 return -EIO;
414
415 if (overlay->last_flip_req == 0) {
416 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
417 if (overlay->last_flip_req == 0)
418 return -ENOMEM;
419 }
420
421 ret = i915_do_wait_request(dev, overlay->last_flip_req, interruptible);
422 if (ret != 0)
423 return ret;
424
425 switch (overlay->hw_wedged) {
426 case RELEASE_OLD_VID:
427 obj = overlay->old_vid_bo->obj;
428 i915_gem_object_unpin(obj);
429 drm_gem_object_unreference(obj);
430 overlay->old_vid_bo = NULL;
431 break;
432 case SWITCH_OFF_STAGE_1:
433 flip_addr = overlay->flip_addr;
434 flip_addr |= OFC_UPDATE;
435
436 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
437
438 BEGIN_LP_RING(6);
439 OUT_RING(MI_FLUSH);
440 OUT_RING(MI_NOOP);
441 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
442 OUT_RING(flip_addr);
443 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
444 OUT_RING(MI_NOOP);
445 ADVANCE_LP_RING();
446
447 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
448 if (overlay->last_flip_req == 0)
449 return -ENOMEM;
450
451 ret = i915_do_wait_request(dev, overlay->last_flip_req,
452 interruptible);
453 if (ret != 0)
454 return ret;
455
456 case SWITCH_OFF_STAGE_2:
457 intel_overlay_off_tail(overlay);
458 break;
459 default:
460 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
461 }
462
463 overlay->hw_wedged = 0;
464 overlay->last_flip_req = 0;
465 return 0;
466}
467
468/* Wait for pending overlay flip and release old frame.
469 * Needs to be called before the overlay register are changed
470 * via intel_overlay_(un)map_regs_atomic */
471static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
472{
473 int ret;
474 struct drm_gem_object *obj;
475
476 /* only wait if there is actually an old frame to release to
477 * guarantee forward progress */
478 if (!overlay->old_vid_bo)
479 return 0;
480
481 ret = intel_overlay_wait_flip(overlay);
482 if (ret != 0)
483 return ret;
484
485 obj = overlay->old_vid_bo->obj;
486 i915_gem_object_unpin(obj);
487 drm_gem_object_unreference(obj);
488 overlay->old_vid_bo = NULL;
489
490 return 0;
491}
492
493struct put_image_params {
494 int format;
495 short dst_x;
496 short dst_y;
497 short dst_w;
498 short dst_h;
499 short src_w;
500 short src_scan_h;
501 short src_scan_w;
502 short src_h;
503 short stride_Y;
504 short stride_UV;
505 int offset_Y;
506 int offset_U;
507 int offset_V;
508};
509
510static int packed_depth_bytes(u32 format)
511{
512 switch (format & I915_OVERLAY_DEPTH_MASK) {
513 case I915_OVERLAY_YUV422:
514 return 4;
515 case I915_OVERLAY_YUV411:
516 /* return 6; not implemented */
517 default:
518 return -EINVAL;
519 }
520}
521
522static int packed_width_bytes(u32 format, short width)
523{
524 switch (format & I915_OVERLAY_DEPTH_MASK) {
525 case I915_OVERLAY_YUV422:
526 return width << 1;
527 default:
528 return -EINVAL;
529 }
530}
531
532static int uv_hsubsampling(u32 format)
533{
534 switch (format & I915_OVERLAY_DEPTH_MASK) {
535 case I915_OVERLAY_YUV422:
536 case I915_OVERLAY_YUV420:
537 return 2;
538 case I915_OVERLAY_YUV411:
539 case I915_OVERLAY_YUV410:
540 return 4;
541 default:
542 return -EINVAL;
543 }
544}
545
546static int uv_vsubsampling(u32 format)
547{
548 switch (format & I915_OVERLAY_DEPTH_MASK) {
549 case I915_OVERLAY_YUV420:
550 case I915_OVERLAY_YUV410:
551 return 2;
552 case I915_OVERLAY_YUV422:
553 case I915_OVERLAY_YUV411:
554 return 1;
555 default:
556 return -EINVAL;
557 }
558}
559
560static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
561{
562 u32 mask, shift, ret;
563 if (IS_I9XX(dev)) {
564 mask = 0x3f;
565 shift = 6;
566 } else {
567 mask = 0x1f;
568 shift = 5;
569 }
570 ret = ((offset + width + mask) >> shift) - (offset >> shift);
571 if (IS_I9XX(dev))
572 ret <<= 1;
573 ret -=1;
574 return ret << 2;
575}
576
577static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
578 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
579 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
580 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
581 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
582 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
583 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
584 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
585 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
586 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
587 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
588 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
589 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
590 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
591 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
592 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
593 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
594 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
595static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
596 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
597 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
598 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
599 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
600 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
601 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
602 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
603 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
604 0x3000, 0x0800, 0x3000};
605
606static void update_polyphase_filter(struct overlay_registers *regs)
607{
608 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
609 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
610}
611
612static bool update_scaling_factors(struct intel_overlay *overlay,
613 struct overlay_registers *regs,
614 struct put_image_params *params)
615{
616 /* fixed point with a 12 bit shift */
617 u32 xscale, yscale, xscale_UV, yscale_UV;
618#define FP_SHIFT 12
619#define FRACT_MASK 0xfff
620 bool scale_changed = false;
621 int uv_hscale = uv_hsubsampling(params->format);
622 int uv_vscale = uv_vsubsampling(params->format);
623
624 if (params->dst_w > 1)
625 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
626 /(params->dst_w);
627 else
628 xscale = 1 << FP_SHIFT;
629
630 if (params->dst_h > 1)
631 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
632 /(params->dst_h);
633 else
634 yscale = 1 << FP_SHIFT;
635
636 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
637 xscale_UV = xscale/uv_hscale;
638 yscale_UV = yscale/uv_vscale;
639 /* make the Y scale to UV scale ratio an exact multiply */
640 xscale = xscale_UV * uv_hscale;
641 yscale = yscale_UV * uv_vscale;
642 /*} else {
643 xscale_UV = 0;
644 yscale_UV = 0;
645 }*/
646
647 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
648 scale_changed = true;
649 overlay->old_xscale = xscale;
650 overlay->old_yscale = yscale;
651
652 regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
653 | ((xscale >> FP_SHIFT) << 16)
654 | ((xscale & FRACT_MASK) << 3);
655 regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
656 | ((xscale_UV >> FP_SHIFT) << 16)
657 | ((xscale_UV & FRACT_MASK) << 3);
658 regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
659 | ((yscale_UV >> FP_SHIFT) << 0);
660
661 if (scale_changed)
662 update_polyphase_filter(regs);
663
664 return scale_changed;
665}
666
667static void update_colorkey(struct intel_overlay *overlay,
668 struct overlay_registers *regs)
669{
670 u32 key = overlay->color_key;
671 switch (overlay->crtc->base.fb->bits_per_pixel) {
672 case 8:
673 regs->DCLRKV = 0;
674 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
675 case 16:
676 if (overlay->crtc->base.fb->depth == 15) {
677 regs->DCLRKV = RGB15_TO_COLORKEY(key);
678 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
679 } else {
680 regs->DCLRKV = RGB16_TO_COLORKEY(key);
681 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
682 }
683 case 24:
684 case 32:
685 regs->DCLRKV = key;
686 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
687 }
688}
689
690static u32 overlay_cmd_reg(struct put_image_params *params)
691{
692 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
693
694 if (params->format & I915_OVERLAY_YUV_PLANAR) {
695 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
696 case I915_OVERLAY_YUV422:
697 cmd |= OCMD_YUV_422_PLANAR;
698 break;
699 case I915_OVERLAY_YUV420:
700 cmd |= OCMD_YUV_420_PLANAR;
701 break;
702 case I915_OVERLAY_YUV411:
703 case I915_OVERLAY_YUV410:
704 cmd |= OCMD_YUV_410_PLANAR;
705 break;
706 }
707 } else { /* YUV packed */
708 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
709 case I915_OVERLAY_YUV422:
710 cmd |= OCMD_YUV_422_PACKED;
711 break;
712 case I915_OVERLAY_YUV411:
713 cmd |= OCMD_YUV_411_PACKED;
714 break;
715 }
716
717 switch (params->format & I915_OVERLAY_SWAP_MASK) {
718 case I915_OVERLAY_NO_SWAP:
719 break;
720 case I915_OVERLAY_UV_SWAP:
721 cmd |= OCMD_UV_SWAP;
722 break;
723 case I915_OVERLAY_Y_SWAP:
724 cmd |= OCMD_Y_SWAP;
725 break;
726 case I915_OVERLAY_Y_AND_UV_SWAP:
727 cmd |= OCMD_Y_AND_UV_SWAP;
728 break;
729 }
730 }
731
732 return cmd;
733}
734
735int intel_overlay_do_put_image(struct intel_overlay *overlay,
736 struct drm_gem_object *new_bo,
737 struct put_image_params *params)
738{
739 int ret, tmp_width;
740 struct overlay_registers *regs;
741 bool scale_changed = false;
742 struct drm_i915_gem_object *bo_priv = new_bo->driver_private;
743 struct drm_device *dev = overlay->dev;
744
745 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
746 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
747 BUG_ON(!overlay);
748
749 ret = intel_overlay_release_old_vid(overlay);
750 if (ret != 0)
751 return ret;
752
753 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
754 if (ret != 0)
755 return ret;
756
757 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
758 if (ret != 0)
759 goto out_unpin;
760
761 if (!overlay->active) {
762 regs = intel_overlay_map_regs_atomic(overlay);
763 if (!regs) {
764 ret = -ENOMEM;
765 goto out_unpin;
766 }
767 regs->OCONFIG = OCONF_CC_OUT_8BIT;
768 if (IS_I965GM(overlay->dev))
769 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
770 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
771 OCONF_PIPE_A : OCONF_PIPE_B;
772 intel_overlay_unmap_regs_atomic(overlay);
773
774 ret = intel_overlay_on(overlay);
775 if (ret != 0)
776 goto out_unpin;
777 }
778
779 regs = intel_overlay_map_regs_atomic(overlay);
780 if (!regs) {
781 ret = -ENOMEM;
782 goto out_unpin;
783 }
784
785 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
786 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
787
788 if (params->format & I915_OVERLAY_YUV_PACKED)
789 tmp_width = packed_width_bytes(params->format, params->src_w);
790 else
791 tmp_width = params->src_w;
792
793 regs->SWIDTH = params->src_w;
794 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
795 params->offset_Y, tmp_width);
796 regs->SHEIGHT = params->src_h;
797 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
798 regs->OSTRIDE = params->stride_Y;
799
800 if (params->format & I915_OVERLAY_YUV_PLANAR) {
801 int uv_hscale = uv_hsubsampling(params->format);
802 int uv_vscale = uv_vsubsampling(params->format);
803 u32 tmp_U, tmp_V;
804 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
805 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
806 params->src_w/uv_hscale);
807 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
808 params->src_w/uv_hscale);
809 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
810 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
811 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
812 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
813 regs->OSTRIDE |= params->stride_UV << 16;
814 }
815
816 scale_changed = update_scaling_factors(overlay, regs, params);
817
818 update_colorkey(overlay, regs);
819
820 regs->OCMD = overlay_cmd_reg(params);
821
822 intel_overlay_unmap_regs_atomic(overlay);
823
824 intel_overlay_continue(overlay, scale_changed);
825
826 overlay->old_vid_bo = overlay->vid_bo;
827 overlay->vid_bo = new_bo->driver_private;
828
829 return 0;
830
831out_unpin:
832 i915_gem_object_unpin(new_bo);
833 return ret;
834}
835
836int intel_overlay_switch_off(struct intel_overlay *overlay)
837{
838 int ret;
839 struct overlay_registers *regs;
840 struct drm_device *dev = overlay->dev;
841
842 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
843 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
844
845 if (overlay->hw_wedged) {
846 ret = intel_overlay_recover_from_interrupt(overlay, 1);
847 if (ret != 0)
848 return ret;
849 }
850
851 if (!overlay->active)
852 return 0;
853
854 ret = intel_overlay_release_old_vid(overlay);
855 if (ret != 0)
856 return ret;
857
858 regs = intel_overlay_map_regs_atomic(overlay);
859 regs->OCMD = 0;
860 intel_overlay_unmap_regs_atomic(overlay);
861
862 ret = intel_overlay_off(overlay);
863 if (ret != 0)
864 return ret;
865
866 intel_overlay_off_tail(overlay);
867
868 return 0;
869}
870
871static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
872 struct intel_crtc *crtc)
873{
874 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
875 u32 pipeconf;
876 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
877
878 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
879 return -EINVAL;
880
881 pipeconf = I915_READ(pipeconf_reg);
882
883 /* can't use the overlay with double wide pipe */
884 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
885 return -EINVAL;
886
887 return 0;
888}
889
890static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
891{
892 struct drm_device *dev = overlay->dev;
893 drm_i915_private_t *dev_priv = dev->dev_private;
894 u32 ratio;
895 u32 pfit_control = I915_READ(PFIT_CONTROL);
896
897 /* XXX: This is not the same logic as in the xorg driver, but more in
898 * line with the intel documentation for the i965 */
899 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
900 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
901 } else { /* on i965 use the PGM reg to read out the autoscaler values */
902 ratio = I915_READ(PFIT_PGM_RATIOS);
903 if (IS_I965G(dev))
904 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
905 else
906 ratio >>= PFIT_VERT_SCALE_SHIFT;
907 }
908
909 overlay->pfit_vscale_ratio = ratio;
910}
911
912static int check_overlay_dst(struct intel_overlay *overlay,
913 struct drm_intel_overlay_put_image *rec)
914{
915 struct drm_display_mode *mode = &overlay->crtc->base.mode;
916
917 if ((rec->dst_x < mode->crtc_hdisplay)
918 && (rec->dst_x + rec->dst_width
919 <= mode->crtc_hdisplay)
920 && (rec->dst_y < mode->crtc_vdisplay)
921 && (rec->dst_y + rec->dst_height
922 <= mode->crtc_vdisplay))
923 return 0;
924 else
925 return -EINVAL;
926}
927
928static int check_overlay_scaling(struct put_image_params *rec)
929{
930 u32 tmp;
931
932 /* downscaling limit is 8.0 */
933 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
934 if (tmp > 7)
935 return -EINVAL;
936 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
937 if (tmp > 7)
938 return -EINVAL;
939
940 return 0;
941}
942
943static int check_overlay_src(struct drm_device *dev,
944 struct drm_intel_overlay_put_image *rec,
945 struct drm_gem_object *new_bo)
946{
947 u32 stride_mask;
948 int depth;
949 int uv_hscale = uv_hsubsampling(rec->flags);
950 int uv_vscale = uv_vsubsampling(rec->flags);
951 size_t tmp;
952
953 /* check src dimensions */
954 if (IS_845G(dev) || IS_I830(dev)) {
955 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
956 || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
957 return -EINVAL;
958 } else {
959 if (rec->src_height > IMAGE_MAX_HEIGHT
960 || rec->src_width > IMAGE_MAX_WIDTH)
961 return -EINVAL;
962 }
963 /* better safe than sorry, use 4 as the maximal subsampling ratio */
964 if (rec->src_height < N_VERT_Y_TAPS*4
965 || rec->src_width < N_HORIZ_Y_TAPS*4)
966 return -EINVAL;
967
968 /* check alingment constrains */
969 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
970 case I915_OVERLAY_RGB:
971 /* not implemented */
972 return -EINVAL;
973 case I915_OVERLAY_YUV_PACKED:
974 depth = packed_depth_bytes(rec->flags);
975 if (uv_vscale != 1)
976 return -EINVAL;
977 if (depth < 0)
978 return depth;
979 /* ignore UV planes */
980 rec->stride_UV = 0;
981 rec->offset_U = 0;
982 rec->offset_V = 0;
983 /* check pixel alignment */
984 if (rec->offset_Y % depth)
985 return -EINVAL;
986 break;
987 case I915_OVERLAY_YUV_PLANAR:
988 if (uv_vscale < 0 || uv_hscale < 0)
989 return -EINVAL;
990 /* no offset restrictions for planar formats */
991 break;
992 default:
993 return -EINVAL;
994 }
995
996 if (rec->src_width % uv_hscale)
997 return -EINVAL;
998
999 /* stride checking */
1000 stride_mask = 63;
1001
1002 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1003 return -EINVAL;
1004 if (IS_I965G(dev) && rec->stride_Y < 512)
1005 return -EINVAL;
1006
1007 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1008 4 : 8;
1009 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
1010 return -EINVAL;
1011
1012 /* check buffer dimensions */
1013 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1014 case I915_OVERLAY_RGB:
1015 case I915_OVERLAY_YUV_PACKED:
1016 /* always 4 Y values per depth pixels */
1017 if (packed_width_bytes(rec->flags, rec->src_width)
1018 > rec->stride_Y)
1019 return -EINVAL;
1020
1021 tmp = rec->stride_Y*rec->src_height;
1022 if (rec->offset_Y + tmp > new_bo->size)
1023 return -EINVAL;
1024 break;
1025 case I915_OVERLAY_YUV_PLANAR:
1026 if (rec->src_width > rec->stride_Y)
1027 return -EINVAL;
1028 if (rec->src_width/uv_hscale > rec->stride_UV)
1029 return -EINVAL;
1030
1031 tmp = rec->stride_Y*rec->src_height;
1032 if (rec->offset_Y + tmp > new_bo->size)
1033 return -EINVAL;
1034 tmp = rec->stride_UV*rec->src_height;
1035 tmp /= uv_vscale;
1036 if (rec->offset_U + tmp > new_bo->size
1037 || rec->offset_V + tmp > new_bo->size)
1038 return -EINVAL;
1039 break;
1040 }
1041
1042 return 0;
1043}
1044
1045int intel_overlay_put_image(struct drm_device *dev, void *data,
1046 struct drm_file *file_priv)
1047{
1048 struct drm_intel_overlay_put_image *put_image_rec = data;
1049 drm_i915_private_t *dev_priv = dev->dev_private;
1050 struct intel_overlay *overlay;
1051 struct drm_mode_object *drmmode_obj;
1052 struct intel_crtc *crtc;
1053 struct drm_gem_object *new_bo;
1054 struct put_image_params *params;
1055 int ret;
1056
1057 if (!dev_priv) {
1058 DRM_ERROR("called with no initialization\n");
1059 return -EINVAL;
1060 }
1061
1062 overlay = dev_priv->overlay;
1063 if (!overlay) {
1064 DRM_DEBUG("userspace bug: no overlay\n");
1065 return -ENODEV;
1066 }
1067
1068 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1069 mutex_lock(&dev->mode_config.mutex);
1070 mutex_lock(&dev->struct_mutex);
1071
1072 ret = intel_overlay_switch_off(overlay);
1073
1074 mutex_unlock(&dev->struct_mutex);
1075 mutex_unlock(&dev->mode_config.mutex);
1076
1077 return ret;
1078 }
1079
1080 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1081 if (!params)
1082 return -ENOMEM;
1083
1084 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1085 DRM_MODE_OBJECT_CRTC);
1086 if (!drmmode_obj)
1087 return -ENOENT;
1088 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1089
1090 new_bo = drm_gem_object_lookup(dev, file_priv,
1091 put_image_rec->bo_handle);
1092 if (!new_bo)
1093 return -ENOENT;
1094
1095 mutex_lock(&dev->mode_config.mutex);
1096 mutex_lock(&dev->struct_mutex);
1097
1098 if (overlay->hw_wedged) {
1099 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1100 if (ret != 0)
1101 goto out_unlock;
1102 }
1103
1104 if (overlay->crtc != crtc) {
1105 struct drm_display_mode *mode = &crtc->base.mode;
1106 ret = intel_overlay_switch_off(overlay);
1107 if (ret != 0)
1108 goto out_unlock;
1109
1110 ret = check_overlay_possible_on_crtc(overlay, crtc);
1111 if (ret != 0)
1112 goto out_unlock;
1113
1114 overlay->crtc = crtc;
1115 crtc->overlay = overlay;
1116
1117 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1118 /* and line to wide, i.e. one-line-mode */
1119 && mode->hdisplay > 1024) {
1120 overlay->pfit_active = 1;
1121 update_pfit_vscale_ratio(overlay);
1122 } else
1123 overlay->pfit_active = 0;
1124 }
1125
1126 ret = check_overlay_dst(overlay, put_image_rec);
1127 if (ret != 0)
1128 goto out_unlock;
1129
1130 if (overlay->pfit_active) {
1131 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1132 overlay->pfit_vscale_ratio);
1133 /* shifting right rounds downwards, so add 1 */
1134 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1135 overlay->pfit_vscale_ratio) + 1;
1136 } else {
1137 params->dst_y = put_image_rec->dst_y;
1138 params->dst_h = put_image_rec->dst_height;
1139 }
1140 params->dst_x = put_image_rec->dst_x;
1141 params->dst_w = put_image_rec->dst_width;
1142
1143 params->src_w = put_image_rec->src_width;
1144 params->src_h = put_image_rec->src_height;
1145 params->src_scan_w = put_image_rec->src_scan_width;
1146 params->src_scan_h = put_image_rec->src_scan_height;
1147 if (params->src_scan_h > params->src_h
1148 || params->src_scan_w > params->src_w) {
1149 ret = -EINVAL;
1150 goto out_unlock;
1151 }
1152
1153 ret = check_overlay_src(dev, put_image_rec, new_bo);
1154 if (ret != 0)
1155 goto out_unlock;
1156 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1157 params->stride_Y = put_image_rec->stride_Y;
1158 params->stride_UV = put_image_rec->stride_UV;
1159 params->offset_Y = put_image_rec->offset_Y;
1160 params->offset_U = put_image_rec->offset_U;
1161 params->offset_V = put_image_rec->offset_V;
1162
1163 /* Check scaling after src size to prevent a divide-by-zero. */
1164 ret = check_overlay_scaling(params);
1165 if (ret != 0)
1166 goto out_unlock;
1167
1168 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1169 if (ret != 0)
1170 goto out_unlock;
1171
1172 mutex_unlock(&dev->struct_mutex);
1173 mutex_unlock(&dev->mode_config.mutex);
1174
1175 kfree(params);
1176
1177 return 0;
1178
1179out_unlock:
1180 mutex_unlock(&dev->struct_mutex);
1181 mutex_unlock(&dev->mode_config.mutex);
1182 drm_gem_object_unreference(new_bo);
1183 kfree(params);
1184
1185 return ret;
1186}
1187
1188static void update_reg_attrs(struct intel_overlay *overlay,
1189 struct overlay_registers *regs)
1190{
1191 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1192 regs->OCLRC1 = overlay->saturation;
1193}
1194
1195static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1196{
1197 int i;
1198
1199 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1200 return false;
1201
1202 for (i = 0; i < 3; i++) {
1203 if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1204 return false;
1205 }
1206
1207 return true;
1208}
1209
1210static bool check_gamma5_errata(u32 gamma5)
1211{
1212 int i;
1213
1214 for (i = 0; i < 3; i++) {
1215 if (((gamma5 >> i*8) & 0xff) == 0x80)
1216 return false;
1217 }
1218
1219 return true;
1220}
1221
1222static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1223{
1224 if (!check_gamma_bounds(0, attrs->gamma0)
1225 || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
1226 || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
1227 || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
1228 || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
1229 || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
1230 || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1231 return -EINVAL;
1232 if (!check_gamma5_errata(attrs->gamma5))
1233 return -EINVAL;
1234 return 0;
1235}
1236
1237int intel_overlay_attrs(struct drm_device *dev, void *data,
1238 struct drm_file *file_priv)
1239{
1240 struct drm_intel_overlay_attrs *attrs = data;
1241 drm_i915_private_t *dev_priv = dev->dev_private;
1242 struct intel_overlay *overlay;
1243 struct overlay_registers *regs;
1244 int ret;
1245
1246 if (!dev_priv) {
1247 DRM_ERROR("called with no initialization\n");
1248 return -EINVAL;
1249 }
1250
1251 overlay = dev_priv->overlay;
1252 if (!overlay) {
1253 DRM_DEBUG("userspace bug: no overlay\n");
1254 return -ENODEV;
1255 }
1256
1257 mutex_lock(&dev->mode_config.mutex);
1258 mutex_lock(&dev->struct_mutex);
1259
1260 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1261 attrs->color_key = overlay->color_key;
1262 attrs->brightness = overlay->brightness;
1263 attrs->contrast = overlay->contrast;
1264 attrs->saturation = overlay->saturation;
1265
1266 if (IS_I9XX(dev)) {
1267 attrs->gamma0 = I915_READ(OGAMC0);
1268 attrs->gamma1 = I915_READ(OGAMC1);
1269 attrs->gamma2 = I915_READ(OGAMC2);
1270 attrs->gamma3 = I915_READ(OGAMC3);
1271 attrs->gamma4 = I915_READ(OGAMC4);
1272 attrs->gamma5 = I915_READ(OGAMC5);
1273 }
1274 ret = 0;
1275 } else {
1276 overlay->color_key = attrs->color_key;
1277 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1278 overlay->brightness = attrs->brightness;
1279 } else {
1280 ret = -EINVAL;
1281 goto out_unlock;
1282 }
1283 if (attrs->contrast <= 255) {
1284 overlay->contrast = attrs->contrast;
1285 } else {
1286 ret = -EINVAL;
1287 goto out_unlock;
1288 }
1289 if (attrs->saturation <= 1023) {
1290 overlay->saturation = attrs->saturation;
1291 } else {
1292 ret = -EINVAL;
1293 goto out_unlock;
1294 }
1295
1296 regs = intel_overlay_map_regs_atomic(overlay);
1297 if (!regs) {
1298 ret = -ENOMEM;
1299 goto out_unlock;
1300 }
1301
1302 update_reg_attrs(overlay, regs);
1303
1304 intel_overlay_unmap_regs_atomic(overlay);
1305
1306 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1307 if (!IS_I9XX(dev)) {
1308 ret = -EINVAL;
1309 goto out_unlock;
1310 }
1311
1312 if (overlay->active) {
1313 ret = -EBUSY;
1314 goto out_unlock;
1315 }
1316
1317 ret = check_gamma(attrs);
1318 if (ret != 0)
1319 goto out_unlock;
1320
1321 I915_WRITE(OGAMC0, attrs->gamma0);
1322 I915_WRITE(OGAMC1, attrs->gamma1);
1323 I915_WRITE(OGAMC2, attrs->gamma2);
1324 I915_WRITE(OGAMC3, attrs->gamma3);
1325 I915_WRITE(OGAMC4, attrs->gamma4);
1326 I915_WRITE(OGAMC5, attrs->gamma5);
1327 }
1328 ret = 0;
1329 }
1330
1331out_unlock:
1332 mutex_unlock(&dev->struct_mutex);
1333 mutex_unlock(&dev->mode_config.mutex);
1334
1335 return ret;
1336}
1337
1338void intel_setup_overlay(struct drm_device *dev)
1339{
1340 drm_i915_private_t *dev_priv = dev->dev_private;
1341 struct intel_overlay *overlay;
1342 struct drm_gem_object *reg_bo;
1343 struct overlay_registers *regs;
1344 int ret;
1345
1346 if (!OVERLAY_EXISTS(dev))
1347 return;
1348
1349 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1350 if (!overlay)
1351 return;
1352 overlay->dev = dev;
1353
1354 reg_bo = drm_gem_object_alloc(dev, PAGE_SIZE);
1355 if (!reg_bo)
1356 goto out_free;
1357 overlay->reg_bo = reg_bo->driver_private;
1358
1359 if (OVERLAY_NONPHYSICAL(dev)) {
1360 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1361 if (ret) {
1362 DRM_ERROR("failed to pin overlay register bo\n");
1363 goto out_free_bo;
1364 }
1365 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1366 } else {
1367 ret = i915_gem_attach_phys_object(dev, reg_bo,
1368 I915_GEM_PHYS_OVERLAY_REGS);
1369 if (ret) {
1370 DRM_ERROR("failed to attach phys overlay regs\n");
1371 goto out_free_bo;
1372 }
1373 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1374 }
1375
1376 /* init all values */
1377 overlay->color_key = 0x0101fe;
1378 overlay->brightness = -19;
1379 overlay->contrast = 75;
1380 overlay->saturation = 146;
1381
1382 regs = intel_overlay_map_regs_atomic(overlay);
1383 if (!regs)
1384 goto out_free_bo;
1385
1386 memset(regs, 0, sizeof(struct overlay_registers));
1387 update_polyphase_filter(regs);
1388
1389 update_reg_attrs(overlay, regs);
1390
1391 intel_overlay_unmap_regs_atomic(overlay);
1392
1393 dev_priv->overlay = overlay;
1394 DRM_INFO("initialized overlay support\n");
1395 return;
1396
1397out_free_bo:
1398 drm_gem_object_unreference(reg_bo);
1399out_free:
1400 kfree(overlay);
1401 return;
1402}
1403
1404void intel_cleanup_overlay(struct drm_device *dev)
1405{
1406 drm_i915_private_t *dev_priv = dev->dev_private;
1407
1408 if (dev_priv->overlay) {
1409 /* The bo's should be free'd by the generic code already.
1410 * Furthermore modesetting teardown happens beforehand so the
1411 * hardware should be off already */
1412 BUG_ON(dev_priv->overlay->active);
1413
1414 kfree(dev_priv->overlay);
1415 }
1416}
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 083bec2e50f9..55b8beb0a152 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -36,8 +36,6 @@
36#include "i915_drv.h" 36#include "i915_drv.h"
37#include "intel_sdvo_regs.h" 37#include "intel_sdvo_regs.h"
38 38
39#undef SDVO_DEBUG
40
41static char *tv_format_names[] = { 39static char *tv_format_names[] = {
42 "NTSC_M" , "NTSC_J" , "NTSC_443", 40 "NTSC_M" , "NTSC_J" , "NTSC_443",
43 "PAL_B" , "PAL_D" , "PAL_G" , 41 "PAL_B" , "PAL_D" , "PAL_G" ,
@@ -356,7 +354,6 @@ static const struct _sdvo_cmd_name {
356#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") 354#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
357#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) 355#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
358 356
359#ifdef SDVO_DEBUG
360static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, 357static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
361 void *args, int args_len) 358 void *args, int args_len)
362{ 359{
@@ -379,9 +376,6 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
379 DRM_LOG_KMS("(%02X)", cmd); 376 DRM_LOG_KMS("(%02X)", cmd);
380 DRM_LOG_KMS("\n"); 377 DRM_LOG_KMS("\n");
381} 378}
382#else
383#define intel_sdvo_debug_write(o, c, a, l)
384#endif
385 379
386static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd, 380static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
387 void *args, int args_len) 381 void *args, int args_len)
@@ -398,7 +392,6 @@ static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
398 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd); 392 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
399} 393}
400 394
401#ifdef SDVO_DEBUG
402static const char *cmd_status_names[] = { 395static const char *cmd_status_names[] = {
403 "Power on", 396 "Power on",
404 "Success", 397 "Success",
@@ -427,9 +420,6 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output,
427 DRM_LOG_KMS("(??? %d)", status); 420 DRM_LOG_KMS("(??? %d)", status);
428 DRM_LOG_KMS("\n"); 421 DRM_LOG_KMS("\n");
429} 422}
430#else
431#define intel_sdvo_debug_response(o, r, l, s)
432#endif
433 423
434static u8 intel_sdvo_read_response(struct intel_output *intel_output, 424static u8 intel_sdvo_read_response(struct intel_output *intel_output,
435 void *response, int response_len) 425 void *response, int response_len)
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 9ca917931afb..9325dff21c06 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1213,20 +1213,17 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1213 tv_ctl |= TV_TRILEVEL_SYNC; 1213 tv_ctl |= TV_TRILEVEL_SYNC;
1214 if (tv_mode->pal_burst) 1214 if (tv_mode->pal_burst)
1215 tv_ctl |= TV_PAL_BURST; 1215 tv_ctl |= TV_PAL_BURST;
1216
1216 scctl1 = 0; 1217 scctl1 = 0;
1217 /* dda1 implies valid video levels */ 1218 if (tv_mode->dda1_inc)
1218 if (tv_mode->dda1_inc) {
1219 scctl1 |= TV_SC_DDA1_EN; 1219 scctl1 |= TV_SC_DDA1_EN;
1220 }
1221
1222 if (tv_mode->dda2_inc) 1220 if (tv_mode->dda2_inc)
1223 scctl1 |= TV_SC_DDA2_EN; 1221 scctl1 |= TV_SC_DDA2_EN;
1224
1225 if (tv_mode->dda3_inc) 1222 if (tv_mode->dda3_inc)
1226 scctl1 |= TV_SC_DDA3_EN; 1223 scctl1 |= TV_SC_DDA3_EN;
1227
1228 scctl1 |= tv_mode->sc_reset; 1224 scctl1 |= tv_mode->sc_reset;
1229 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT; 1225 if (video_levels)
1226 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1230 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT; 1227 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1231 1228
1232 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT | 1229 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
@@ -1416,16 +1413,16 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
1416 * 0 0 0 Component 1413 * 0 0 0 Component
1417 */ 1414 */
1418 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1415 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1419 DRM_DEBUG("Detected Composite TV connection\n"); 1416 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1420 type = DRM_MODE_CONNECTOR_Composite; 1417 type = DRM_MODE_CONNECTOR_Composite;
1421 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1418 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1422 DRM_DEBUG("Detected S-Video TV connection\n"); 1419 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1423 type = DRM_MODE_CONNECTOR_SVIDEO; 1420 type = DRM_MODE_CONNECTOR_SVIDEO;
1424 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1421 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1425 DRM_DEBUG("Detected Component TV connection\n"); 1422 DRM_DEBUG_KMS("Detected Component TV connection\n");
1426 type = DRM_MODE_CONNECTOR_Component; 1423 type = DRM_MODE_CONNECTOR_Component;
1427 } else { 1424 } else {
1428 DRM_DEBUG("No TV connection detected\n"); 1425 DRM_DEBUG_KMS("No TV connection detected\n");
1429 type = -1; 1426 type = -1;
1430 } 1427 }
1431 1428
@@ -1702,6 +1699,41 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1702 .destroy = intel_tv_enc_destroy, 1699 .destroy = intel_tv_enc_destroy,
1703}; 1700};
1704 1701
1702/*
1703 * Enumerate the child dev array parsed from VBT to check whether
1704 * the integrated TV is present.
1705 * If it is present, return 1.
1706 * If it is not present, return false.
1707 * If no child dev is parsed from VBT, it assumes that the TV is present.
1708 */
1709int tv_is_present_in_vbt(struct drm_device *dev)
1710{
1711 struct drm_i915_private *dev_priv = dev->dev_private;
1712 struct child_device_config *p_child;
1713 int i, ret;
1714
1715 if (!dev_priv->child_dev_num)
1716 return 1;
1717
1718 ret = 0;
1719 for (i = 0; i < dev_priv->child_dev_num; i++) {
1720 p_child = dev_priv->child_dev + i;
1721 /*
1722 * If the device type is not TV, continue.
1723 */
1724 if (p_child->device_type != DEVICE_TYPE_INT_TV &&
1725 p_child->device_type != DEVICE_TYPE_TV)
1726 continue;
1727 /* Only when the addin_offset is non-zero, it is regarded
1728 * as present.
1729 */
1730 if (p_child->addin_offset) {
1731 ret = 1;
1732 break;
1733 }
1734 }
1735 return ret;
1736}
1705 1737
1706void 1738void
1707intel_tv_init(struct drm_device *dev) 1739intel_tv_init(struct drm_device *dev)
@@ -1717,6 +1749,10 @@ intel_tv_init(struct drm_device *dev)
1717 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1749 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1718 return; 1750 return;
1719 1751
1752 if (!tv_is_present_in_vbt(dev)) {
1753 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1754 return;
1755 }
1720 /* Even if we have an encoder we may not have a connector */ 1756 /* Even if we have an encoder we may not have a connector */
1721 if (!dev_priv->int_tv_support) 1757 if (!dev_priv->int_tv_support)
1722 return; 1758 return;
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 1b72a526ba64..febf6c530c66 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1512,14 +1512,27 @@ static __inline__ void drm_core_dropmap(struct drm_local_map *map)
1512 1512
1513static __inline__ void *drm_calloc_large(size_t nmemb, size_t size) 1513static __inline__ void *drm_calloc_large(size_t nmemb, size_t size)
1514{ 1514{
1515 if (size != 0 && nmemb > ULONG_MAX / size)
1516 return NULL;
1517
1515 if (size * nmemb <= PAGE_SIZE) 1518 if (size * nmemb <= PAGE_SIZE)
1516 return kcalloc(nmemb, size, GFP_KERNEL); 1519 return kcalloc(nmemb, size, GFP_KERNEL);
1517 1520
1521 return __vmalloc(size * nmemb,
1522 GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, PAGE_KERNEL);
1523}
1524
1525/* Modeled after cairo's malloc_ab, it's like calloc but without the zeroing. */
1526static __inline__ void *drm_malloc_ab(size_t nmemb, size_t size)
1527{
1518 if (size != 0 && nmemb > ULONG_MAX / size) 1528 if (size != 0 && nmemb > ULONG_MAX / size)
1519 return NULL; 1529 return NULL;
1520 1530
1531 if (size * nmemb <= PAGE_SIZE)
1532 return kmalloc(nmemb * size, GFP_KERNEL);
1533
1521 return __vmalloc(size * nmemb, 1534 return __vmalloc(size * nmemb,
1522 GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, PAGE_KERNEL); 1535 GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL);
1523} 1536}
1524 1537
1525static __inline void drm_free_large(void *ptr) 1538static __inline void drm_free_large(void *ptr)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 4cc8a32dc4cf..51d613673b2e 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -725,7 +725,8 @@ extern void drm_mode_connector_detach_encoder(struct drm_connector *connector,
725 struct drm_encoder *encoder); 725 struct drm_encoder *encoder);
726extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, 726extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
727 int gamma_size); 727 int gamma_size);
728extern void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type); 728extern struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
729 uint32_t id, uint32_t type);
729/* IOCTLs */ 730/* IOCTLs */
730extern int drm_mode_getresources(struct drm_device *dev, 731extern int drm_mode_getresources(struct drm_device *dev,
731 void *data, struct drm_file *file_priv); 732 void *data, struct drm_file *file_priv);
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
index 26641e95e0a4..393369147a2d 100644
--- a/include/drm/drm_os_linux.h
+++ b/include/drm/drm_os_linux.h
@@ -123,5 +123,5 @@ do { \
123 remove_wait_queue(&(queue), &entry); \ 123 remove_wait_queue(&(queue), &entry); \
124} while (0) 124} while (0)
125 125
126#define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) 126#define DRM_WAKEUP( queue ) wake_up( queue )
127#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) 127#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e0cb1da92e6..c900499f2f63 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -186,6 +186,8 @@ typedef struct _drm_i915_sarea {
186#define DRM_I915_GEM_MMAP_GTT 0x24 186#define DRM_I915_GEM_MMAP_GTT 0x24
187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
188#define DRM_I915_GEM_MADVISE 0x26 188#define DRM_I915_GEM_MADVISE 0x26
189#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
190#define DRM_I915_OVERLAY_ATTRS 0x28
189 191
190#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 192#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
191#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 193#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -223,6 +225,8 @@ typedef struct _drm_i915_sarea {
223#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 225#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
224#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id) 226#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
225#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 227#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
228#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
229#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
226 230
227/* Allow drivers to submit batchbuffers directly to hardware, relying 231/* Allow drivers to submit batchbuffers directly to hardware, relying
228 * on the security mechanisms provided by hardware. 232 * on the security mechanisms provided by hardware.
@@ -266,6 +270,7 @@ typedef struct drm_i915_irq_wait {
266#define I915_PARAM_CHIPSET_ID 4 270#define I915_PARAM_CHIPSET_ID 4
267#define I915_PARAM_HAS_GEM 5 271#define I915_PARAM_HAS_GEM 5
268#define I915_PARAM_NUM_FENCES_AVAIL 6 272#define I915_PARAM_NUM_FENCES_AVAIL 6
273#define I915_PARAM_HAS_OVERLAY 7
269 274
270typedef struct drm_i915_getparam { 275typedef struct drm_i915_getparam {
271 int param; 276 int param;
@@ -686,4 +691,70 @@ struct drm_i915_gem_madvise {
686 __u32 retained; 691 __u32 retained;
687}; 692};
688 693
694/* flags */
695#define I915_OVERLAY_TYPE_MASK 0xff
696#define I915_OVERLAY_YUV_PLANAR 0x01
697#define I915_OVERLAY_YUV_PACKED 0x02
698#define I915_OVERLAY_RGB 0x03
699
700#define I915_OVERLAY_DEPTH_MASK 0xff00
701#define I915_OVERLAY_RGB24 0x1000
702#define I915_OVERLAY_RGB16 0x2000
703#define I915_OVERLAY_RGB15 0x3000
704#define I915_OVERLAY_YUV422 0x0100
705#define I915_OVERLAY_YUV411 0x0200
706#define I915_OVERLAY_YUV420 0x0300
707#define I915_OVERLAY_YUV410 0x0400
708
709#define I915_OVERLAY_SWAP_MASK 0xff0000
710#define I915_OVERLAY_NO_SWAP 0x000000
711#define I915_OVERLAY_UV_SWAP 0x010000
712#define I915_OVERLAY_Y_SWAP 0x020000
713#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
714
715#define I915_OVERLAY_FLAGS_MASK 0xff000000
716#define I915_OVERLAY_ENABLE 0x01000000
717
718struct drm_intel_overlay_put_image {
719 /* various flags and src format description */
720 __u32 flags;
721 /* source picture description */
722 __u32 bo_handle;
723 /* stride values and offsets are in bytes, buffer relative */
724 __u16 stride_Y; /* stride for packed formats */
725 __u16 stride_UV;
726 __u32 offset_Y; /* offset for packet formats */
727 __u32 offset_U;
728 __u32 offset_V;
729 /* in pixels */
730 __u16 src_width;
731 __u16 src_height;
732 /* to compensate the scaling factors for partially covered surfaces */
733 __u16 src_scan_width;
734 __u16 src_scan_height;
735 /* output crtc description */
736 __u32 crtc_id;
737 __u16 dst_x;
738 __u16 dst_y;
739 __u16 dst_width;
740 __u16 dst_height;
741};
742
743/* flags */
744#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
745#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
746struct drm_intel_overlay_attrs {
747 __u32 flags;
748 __u32 color_key;
749 __s32 brightness;
750 __u32 contrast;
751 __u32 saturation;
752 __u32 gamma0;
753 __u32 gamma1;
754 __u32 gamma2;
755 __u32 gamma3;
756 __u32 gamma4;
757 __u32 gamma5;
758};
759
689#endif /* _I915_DRM_H_ */ 760#endif /* _I915_DRM_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 01:52:44 -0400