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-rw-r--r--drivers/video/tgafb.c83
1 files changed, 48 insertions, 35 deletions
diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c
index 9c23a783e713..2f09e796bafb 100644
--- a/drivers/video/tgafb.c
+++ b/drivers/video/tgafb.c
@@ -99,6 +99,12 @@ tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
99 if (var->bits_per_pixel != 32) 99 if (var->bits_per_pixel != 32)
100 return -EINVAL; 100 return -EINVAL;
101 } 101 }
102 var->red.length = var->green.length = var->blue.length = 8;
103 if (var->bits_per_pixel == 32) {
104 var->red.offset = 16;
105 var->green.offset = 8;
106 var->blue.offset = 0;
107 }
102 108
103 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres) 109 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
104 return -EINVAL; 110 return -EINVAL;
@@ -152,7 +158,7 @@ tgafb_set_par(struct fb_info *info)
152 struct tga_par *par = (struct tga_par *) info->par; 158 struct tga_par *par = (struct tga_par *) info->par;
153 u32 htimings, vtimings, pll_freq; 159 u32 htimings, vtimings, pll_freq;
154 u8 tga_type; 160 u8 tga_type;
155 int i, j; 161 int i;
156 162
157 /* Encode video timings. */ 163 /* Encode video timings. */
158 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB) 164 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
@@ -227,8 +233,10 @@ tgafb_set_par(struct fb_info *info)
227 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE); 233 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
228 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); 234 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
229 235
236#ifdef CONFIG_HW_CONSOLE
230 for (i = 0; i < 16; i++) { 237 for (i = 0; i < 16; i++) {
231 j = color_table[i]; 238 int j = color_table[i];
239
232 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8), 240 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
233 TGA_RAMDAC_REG); 241 TGA_RAMDAC_REG);
234 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8), 242 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
@@ -236,14 +244,17 @@ tgafb_set_par(struct fb_info *info)
236 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8), 244 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
237 TGA_RAMDAC_REG); 245 TGA_RAMDAC_REG);
238 } 246 }
239 for (i = 0; i < 240*3; i += 4) { 247 for (i = 0; i < 240 * 3; i += 4) {
240 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8), 248#else
249 for (i = 0; i < 256 * 3; i += 4) {
250#endif
251 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
241 TGA_RAMDAC_REG); 252 TGA_RAMDAC_REG);
242 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), 253 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
243 TGA_RAMDAC_REG); 254 TGA_RAMDAC_REG);
244 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), 255 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
245 TGA_RAMDAC_REG); 256 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8), 257 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
247 TGA_RAMDAC_REG); 258 TGA_RAMDAC_REG);
248 } 259 }
249 260
@@ -267,26 +278,24 @@ tgafb_set_par(struct fb_info *info)
267 278
268 /* Fill the palette. */ 279 /* Fill the palette. */
269 BT463_LOAD_ADDR(par, 0x0000); 280 BT463_LOAD_ADDR(par, 0x0000);
270 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG); 281 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
271 282
283#ifdef CONFIG_HW_CONSOLE
272 for (i = 0; i < 16; i++) { 284 for (i = 0; i < 16; i++) {
273 j = color_table[i]; 285 int j = color_table[i];
274 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10), 286
275 TGA_RAMDAC_REG); 287 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
276 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10), 288 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
277 TGA_RAMDAC_REG); 289 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
278 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
279 TGA_RAMDAC_REG);
280 } 290 }
281 for (i = 0; i < 512*3; i += 4) { 291 for (i = 0; i < 512 * 3; i += 4) {
282 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10), 292#else
283 TGA_RAMDAC_REG); 293 for (i = 0; i < 528 * 3; i += 4) {
284 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), 294#endif
285 TGA_RAMDAC_REG); 295 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
286 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), 296 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
287 TGA_RAMDAC_REG); 297 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10), 298 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
289 TGA_RAMDAC_REG);
290 } 299 }
291 300
292 /* Fill window type table after start of vertical retrace. */ 301 /* Fill window type table after start of vertical retrace. */
@@ -299,15 +308,12 @@ tgafb_set_par(struct fb_info *info)
299 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG); 308 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
300 309
301 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE); 310 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
302 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG); 311 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
303 312
304 for (i = 0; i < 16; i++) { 313 for (i = 0; i < 16; i++) {
305 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10), 314 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
306 TGA_RAMDAC_REG); 315 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
307 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10), 316 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
308 TGA_RAMDAC_REG);
309 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
310 TGA_RAMDAC_REG);
311 } 317 }
312 318
313 } 319 }
@@ -435,9 +441,16 @@ tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
435 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 441 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
436 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 442 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
437 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); 443 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
438 } else if (regno < 16) { 444 } else {
439 u32 value = (red << 16) | (green << 8) | blue; 445 if (regno < 16) {
440 ((u32 *)info->pseudo_palette)[regno] = value; 446 u32 value = (regno << 16) | (regno << 8) | regno;
447 ((u32 *)info->pseudo_palette)[regno] = value;
448 }
449 BT463_LOAD_ADDR(par, regno);
450 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
451 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
452 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
453 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
441 } 454 }
442 455
443 return 0; 456 return 0;
@@ -1317,7 +1330,7 @@ tgafb_init_fix(struct fb_info *info)
1317 info->fix.type_aux = 0; 1330 info->fix.type_aux = 0;
1318 info->fix.visual = (tga_type == TGA_TYPE_8PLANE 1331 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1319 ? FB_VISUAL_PSEUDOCOLOR 1332 ? FB_VISUAL_PSEUDOCOLOR
1320 : FB_VISUAL_TRUECOLOR); 1333 : FB_VISUAL_DIRECTCOLOR);
1321 1334
1322 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3); 1335 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1323 info->fix.smem_start = (size_t) par->tga_fb_base; 1336 info->fix.smem_start = (size_t) par->tga_fb_base;