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-rw-r--r--drivers/char/drm/drm_bufs.c1
-rw-r--r--drivers/char/drm/i915_dma.c113
-rw-r--r--drivers/char/drm/i915_drv.c462
-rw-r--r--drivers/char/drm/i915_drv.h790
4 files changed, 1309 insertions, 57 deletions
diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c
index d65e75d405fa..07b774fa3f38 100644
--- a/drivers/char/drm/drm_bufs.c
+++ b/drivers/char/drm/drm_bufs.c
@@ -429,6 +429,7 @@ int drm_rmmap(struct drm_device *dev, drm_local_map_t *map)
429 429
430 return ret; 430 return ret;
431} 431}
432EXPORT_SYMBOL(drm_rmmap);
432 433
433/* The rmmap ioctl appears to be unnecessary. All mappings are torn down on 434/* The rmmap ioctl appears to be unnecessary. All mappings are torn down on
434 * the last close of the device, and this is necessary for cleanup when things 435 * the last close of the device, and this is necessary for cleanup when things
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index 842db3233e9e..b8db9652e9dd 100644
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -31,17 +31,6 @@
31#include "i915_drm.h" 31#include "i915_drm.h"
32#include "i915_drv.h" 32#include "i915_drv.h"
33 33
34#define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2 || \
38 dev->pci_device == 0x2A02 || \
39 dev->pci_device == 0x2A12)
40
41#define IS_G33(dev) (dev->pci_device == 0x29b2 || \
42 dev->pci_device == 0x29c2 || \
43 dev->pci_device == 0x29d2)
44
45/* Really want an OS-independent resettable timer. Would like to have 34/* Really want an OS-independent resettable timer. Would like to have
46 * this loop run for (eg) 3 sec, but have the timer reset every time 35 * this loop run for (eg) 3 sec, but have the timer reset every time
47 * the head pointer changes, so that EBUSY only happens if the ring 36 * the head pointer changes, so that EBUSY only happens if the ring
@@ -90,6 +79,7 @@ void i915_kernel_lost_context(struct drm_device * dev)
90 79
91static int i915_dma_cleanup(struct drm_device * dev) 80static int i915_dma_cleanup(struct drm_device * dev)
92{ 81{
82 drm_i915_private_t *dev_priv = dev->dev_private;
93 /* Make sure interrupts are disabled here because the uninstall ioctl 83 /* Make sure interrupts are disabled here because the uninstall ioctl
94 * may not have been called from userspace and after dev_private 84 * may not have been called from userspace and after dev_private
95 * is freed, it's too late. 85 * is freed, it's too late.
@@ -97,52 +87,42 @@ static int i915_dma_cleanup(struct drm_device * dev)
97 if (dev->irq) 87 if (dev->irq)
98 drm_irq_uninstall(dev); 88 drm_irq_uninstall(dev);
99 89
100 if (dev->dev_private) { 90 if (dev_priv->ring.virtual_start) {
101 drm_i915_private_t *dev_priv = 91 drm_core_ioremapfree(&dev_priv->ring.map, dev);
102 (drm_i915_private_t *) dev->dev_private; 92 dev_priv->ring.virtual_start = 0;
103 93 dev_priv->ring.map.handle = 0;
104 if (dev_priv->ring.virtual_start) { 94 dev_priv->ring.map.size = 0;
105 drm_core_ioremapfree(&dev_priv->ring.map, dev); 95 }
106 }
107
108 if (dev_priv->status_page_dmah) {
109 drm_pci_free(dev, dev_priv->status_page_dmah);
110 /* Need to rewrite hardware status page */
111 I915_WRITE(0x02080, 0x1ffff000);
112 }
113
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 I915_WRITE(0x2080, 0x1ffff000);
118 }
119 96
120 drm_free(dev->dev_private, sizeof(drm_i915_private_t), 97 if (dev_priv->status_page_dmah) {
121 DRM_MEM_DRIVER); 98 drm_pci_free(dev, dev_priv->status_page_dmah);
99 dev_priv->status_page_dmah = NULL;
100 /* Need to rewrite hardware status page */
101 I915_WRITE(0x02080, 0x1ffff000);
102 }
122 103
123 dev->dev_private = NULL; 104 if (dev_priv->status_gfx_addr) {
105 dev_priv->status_gfx_addr = 0;
106 drm_core_ioremapfree(&dev_priv->hws_map, dev);
107 I915_WRITE(0x2080, 0x1ffff000);
124 } 108 }
125 109
126 return 0; 110 return 0;
127} 111}
128 112
129static int i915_initialize(struct drm_device * dev, 113static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
130 drm_i915_private_t * dev_priv,
131 drm_i915_init_t * init)
132{ 114{
133 memset(dev_priv, 0, sizeof(drm_i915_private_t)); 115 drm_i915_private_t *dev_priv = dev->dev_private;
134 116
135 dev_priv->sarea = drm_getsarea(dev); 117 dev_priv->sarea = drm_getsarea(dev);
136 if (!dev_priv->sarea) { 118 if (!dev_priv->sarea) {
137 DRM_ERROR("can not find sarea!\n"); 119 DRM_ERROR("can not find sarea!\n");
138 dev->dev_private = (void *)dev_priv;
139 i915_dma_cleanup(dev); 120 i915_dma_cleanup(dev);
140 return -EINVAL; 121 return -EINVAL;
141 } 122 }
142 123
143 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); 124 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
144 if (!dev_priv->mmio_map) { 125 if (!dev_priv->mmio_map) {
145 dev->dev_private = (void *)dev_priv;
146 i915_dma_cleanup(dev); 126 i915_dma_cleanup(dev);
147 DRM_ERROR("can not find mmio map!\n"); 127 DRM_ERROR("can not find mmio map!\n");
148 return -EINVAL; 128 return -EINVAL;
@@ -165,7 +145,6 @@ static int i915_initialize(struct drm_device * dev,
165 drm_core_ioremap(&dev_priv->ring.map, dev); 145 drm_core_ioremap(&dev_priv->ring.map, dev);
166 146
167 if (dev_priv->ring.map.handle == NULL) { 147 if (dev_priv->ring.map.handle == NULL) {
168 dev->dev_private = (void *)dev_priv;
169 i915_dma_cleanup(dev); 148 i915_dma_cleanup(dev);
170 DRM_ERROR("can not ioremap virtual address for" 149 DRM_ERROR("can not ioremap virtual address for"
171 " ring buffer\n"); 150 " ring buffer\n");
@@ -197,7 +176,6 @@ static int i915_initialize(struct drm_device * dev,
197 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); 176 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
198 177
199 if (!dev_priv->status_page_dmah) { 178 if (!dev_priv->status_page_dmah) {
200 dev->dev_private = (void *)dev_priv;
201 i915_dma_cleanup(dev); 179 i915_dma_cleanup(dev);
202 DRM_ERROR("Can not allocate hardware status page\n"); 180 DRM_ERROR("Can not allocate hardware status page\n");
203 return -ENOMEM; 181 return -ENOMEM;
@@ -209,7 +187,6 @@ static int i915_initialize(struct drm_device * dev,
209 I915_WRITE(0x02080, dev_priv->dma_status_page); 187 I915_WRITE(0x02080, dev_priv->dma_status_page);
210 } 188 }
211 DRM_DEBUG("Enabled hardware status page\n"); 189 DRM_DEBUG("Enabled hardware status page\n");
212 dev->dev_private = (void *)dev_priv;
213 return 0; 190 return 0;
214} 191}
215 192
@@ -254,17 +231,12 @@ static int i915_dma_resume(struct drm_device * dev)
254static int i915_dma_init(struct drm_device *dev, void *data, 231static int i915_dma_init(struct drm_device *dev, void *data,
255 struct drm_file *file_priv) 232 struct drm_file *file_priv)
256{ 233{
257 drm_i915_private_t *dev_priv;
258 drm_i915_init_t *init = data; 234 drm_i915_init_t *init = data;
259 int retcode = 0; 235 int retcode = 0;
260 236
261 switch (init->func) { 237 switch (init->func) {
262 case I915_INIT_DMA: 238 case I915_INIT_DMA:
263 dev_priv = drm_alloc(sizeof(drm_i915_private_t), 239 retcode = i915_initialize(dev, init);
264 DRM_MEM_DRIVER);
265 if (dev_priv == NULL)
266 return -ENOMEM;
267 retcode = i915_initialize(dev, dev_priv, init);
268 break; 240 break;
269 case I915_CLEANUP_DMA: 241 case I915_CLEANUP_DMA:
270 retcode = i915_dma_cleanup(dev); 242 retcode = i915_dma_cleanup(dev);
@@ -765,7 +737,6 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
765 737
766 drm_core_ioremap(&dev_priv->hws_map, dev); 738 drm_core_ioremap(&dev_priv->hws_map, dev);
767 if (dev_priv->hws_map.handle == NULL) { 739 if (dev_priv->hws_map.handle == NULL) {
768 dev->dev_private = (void *)dev_priv;
769 i915_dma_cleanup(dev); 740 i915_dma_cleanup(dev);
770 dev_priv->status_gfx_addr = 0; 741 dev_priv->status_gfx_addr = 0;
771 DRM_ERROR("can not ioremap virtual address for" 742 DRM_ERROR("can not ioremap virtual address for"
@@ -784,6 +755,10 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
784 755
785int i915_driver_load(struct drm_device *dev, unsigned long flags) 756int i915_driver_load(struct drm_device *dev, unsigned long flags)
786{ 757{
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 unsigned long base, size;
760 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
761
787 /* i915 has 4 more counters */ 762 /* i915 has 4 more counters */
788 dev->counters += 4; 763 dev->counters += 4;
789 dev->types[6] = _DRM_STAT_IRQ; 764 dev->types[6] = _DRM_STAT_IRQ;
@@ -791,24 +766,50 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
791 dev->types[8] = _DRM_STAT_SECONDARY; 766 dev->types[8] = _DRM_STAT_SECONDARY;
792 dev->types[9] = _DRM_STAT_DMA; 767 dev->types[9] = _DRM_STAT_DMA;
793 768
769 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
770 if (dev_priv == NULL)
771 return -ENOMEM;
772
773 memset(dev_priv, 0, sizeof(drm_i915_private_t));
774
775 dev->dev_private = (void *)dev_priv;
776
777 /* Add register map (needed for suspend/resume) */
778 base = drm_get_resource_start(dev, mmio_bar);
779 size = drm_get_resource_len(dev, mmio_bar);
780
781 ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL,
782 &dev_priv->mmio_map);
783 return ret;
784}
785
786int i915_driver_unload(struct drm_device *dev)
787{
788 struct drm_i915_private *dev_priv = dev->dev_private;
789
790 if (dev_priv->mmio_map)
791 drm_rmmap(dev, dev_priv->mmio_map);
792
793 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
794 DRM_MEM_DRIVER);
795
794 return 0; 796 return 0;
795} 797}
796 798
797void i915_driver_lastclose(struct drm_device * dev) 799void i915_driver_lastclose(struct drm_device * dev)
798{ 800{
799 if (dev->dev_private) { 801 drm_i915_private_t *dev_priv = dev->dev_private;
800 drm_i915_private_t *dev_priv = dev->dev_private; 802
803 if (dev_priv->agp_heap)
801 i915_mem_takedown(&(dev_priv->agp_heap)); 804 i915_mem_takedown(&(dev_priv->agp_heap));
802 } 805
803 i915_dma_cleanup(dev); 806 i915_dma_cleanup(dev);
804} 807}
805 808
806void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 809void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
807{ 810{
808 if (dev->dev_private) { 811 drm_i915_private_t *dev_priv = dev->dev_private;
809 drm_i915_private_t *dev_priv = dev->dev_private; 812 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
810 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
811 }
812} 813}
813 814
814struct drm_ioctl_desc i915_ioctls[] = { 815struct drm_ioctl_desc i915_ioctls[] = {
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index 63b667538e08..d745f3fd6fbf 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -38,6 +38,465 @@ static struct pci_device_id pciidlist[] = {
38 i915_PCI_IDS 38 i915_PCI_IDS
39}; 39};
40 40
41enum pipe {
42 PIPE_A = 0,
43 PIPE_B,
44};
45
46static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
47{
48 struct drm_i915_private *dev_priv = dev->dev_private;
49
50 if (pipe == PIPE_A)
51 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
52 else
53 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
54}
55
56static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
57{
58 struct drm_i915_private *dev_priv = dev->dev_private;
59 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
60 u32 *array;
61 int i;
62
63 if (!i915_pipe_enabled(dev, pipe))
64 return;
65
66 if (pipe == PIPE_A)
67 array = dev_priv->save_palette_a;
68 else
69 array = dev_priv->save_palette_b;
70
71 for(i = 0; i < 256; i++)
72 array[i] = I915_READ(reg + (i << 2));
73}
74
75static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76{
77 struct drm_i915_private *dev_priv = dev->dev_private;
78 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
79 u32 *array;
80 int i;
81
82 if (!i915_pipe_enabled(dev, pipe))
83 return;
84
85 if (pipe == PIPE_A)
86 array = dev_priv->save_palette_a;
87 else
88 array = dev_priv->save_palette_b;
89
90 for(i = 0; i < 256; i++)
91 I915_WRITE(reg + (i << 2), array[i]);
92}
93
94static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
95{
96 outb(reg, index_port);
97 return inb(data_port);
98}
99
100static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
101{
102 inb(st01);
103 outb(palette_enable | reg, VGA_AR_INDEX);
104 return inb(VGA_AR_DATA_READ);
105}
106
107static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
108{
109 inb(st01);
110 outb(palette_enable | reg, VGA_AR_INDEX);
111 outb(val, VGA_AR_DATA_WRITE);
112}
113
114static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
115{
116 outb(reg, index_port);
117 outb(val, data_port);
118}
119
120static void i915_save_vga(struct drm_device *dev)
121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 int i;
124 u16 cr_index, cr_data, st01;
125
126 /* VGA color palette registers */
127 dev_priv->saveDACMASK = inb(VGA_DACMASK);
128 /* DACCRX automatically increments during read */
129 outb(0, VGA_DACRX);
130 /* Read 3 bytes of color data from each index */
131 for (i = 0; i < 256 * 3; i++)
132 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
133
134 /* MSR bits */
135 dev_priv->saveMSR = inb(VGA_MSR_READ);
136 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
137 cr_index = VGA_CR_INDEX_CGA;
138 cr_data = VGA_CR_DATA_CGA;
139 st01 = VGA_ST01_CGA;
140 } else {
141 cr_index = VGA_CR_INDEX_MDA;
142 cr_data = VGA_CR_DATA_MDA;
143 st01 = VGA_ST01_MDA;
144 }
145
146 /* CRT controller regs */
147 i915_write_indexed(cr_index, cr_data, 0x11,
148 i915_read_indexed(cr_index, cr_data, 0x11) &
149 (~0x80));
150 for (i = 0; i < 0x24; i++)
151 dev_priv->saveCR[i] =
152 i915_read_indexed(cr_index, cr_data, i);
153 /* Make sure we don't turn off CR group 0 writes */
154 dev_priv->saveCR[0x11] &= ~0x80;
155
156 /* Attribute controller registers */
157 inb(st01);
158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159 for (i = 0; i < 20; i++)
160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161 inb(st01);
162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
163
164 /* Graphics controller registers */
165 for (i = 0; i < 9; i++)
166 dev_priv->saveGR[i] =
167 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
168
169 dev_priv->saveGR[0x10] =
170 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
171 dev_priv->saveGR[0x11] =
172 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
173 dev_priv->saveGR[0x18] =
174 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
175
176 /* Sequencer registers */
177 for (i = 0; i < 8; i++)
178 dev_priv->saveSR[i] =
179 i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
180}
181
182static void i915_restore_vga(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 int i;
186 u16 cr_index, cr_data, st01;
187
188 /* MSR bits */
189 outb(dev_priv->saveMSR, VGA_MSR_WRITE);
190 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
191 cr_index = VGA_CR_INDEX_CGA;
192 cr_data = VGA_CR_DATA_CGA;
193 st01 = VGA_ST01_CGA;
194 } else {
195 cr_index = VGA_CR_INDEX_MDA;
196 cr_data = VGA_CR_DATA_MDA;
197 st01 = VGA_ST01_MDA;
198 }
199
200 /* Sequencer registers, don't write SR07 */
201 for (i = 0; i < 7; i++)
202 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
203 dev_priv->saveSR[i]);
204
205 /* CRT controller regs */
206 /* Enable CR group 0 writes */
207 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
208 for (i = 0; i < 0x24; i++)
209 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
210
211 /* Graphics controller regs */
212 for (i = 0; i < 9; i++)
213 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
214 dev_priv->saveGR[i]);
215
216 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
217 dev_priv->saveGR[0x10]);
218 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
219 dev_priv->saveGR[0x11]);
220 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
221 dev_priv->saveGR[0x18]);
222
223 /* Attribute controller registers */
224 for (i = 0; i < 20; i++)
225 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
226 inb(st01); /* switch back to index mode */
227 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
228
229 /* VGA color palette registers */
230 outb(dev_priv->saveDACMASK, VGA_DACMASK);
231 /* DACCRX automatically increments during read */
232 outb(0, VGA_DACWX);
233 /* Read 3 bytes of color data from each index */
234 for (i = 0; i < 256 * 3; i++)
235 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
236
237}
238
239static int i915_suspend(struct drm_device *dev)
240{
241 struct drm_i915_private *dev_priv = dev->dev_private;
242 int i;
243
244 if (!dev || !dev_priv) {
245 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
246 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
247 return -ENODEV;
248 }
249
250 pci_save_state(dev->pdev);
251 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
252
253 /* Pipe & plane A info */
254 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
255 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
256 dev_priv->saveFPA0 = I915_READ(FPA0);
257 dev_priv->saveFPA1 = I915_READ(FPA1);
258 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
259 if (IS_I965G(dev))
260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
263 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
267 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
268
269 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
270 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
271 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
272 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
273 dev_priv->saveDSPABASE = I915_READ(DSPABASE);
274 if (IS_I965G(dev)) {
275 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
276 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
277 }
278 i915_save_palette(dev, PIPE_A);
279
280 /* Pipe & plane B info */
281 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
282 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
283 dev_priv->saveFPB0 = I915_READ(FPB0);
284 dev_priv->saveFPB1 = I915_READ(FPB1);
285 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
286 if (IS_I965G(dev))
287 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
288 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
289 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
290 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
291 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
292 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
293 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
294 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
295
296 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
297 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
298 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
299 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
300 dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
301 if (IS_I965GM(dev)) {
302 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
303 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
304 }
305 i915_save_palette(dev, PIPE_B);
306
307 /* CRT state */
308 dev_priv->saveADPA = I915_READ(ADPA);
309
310 /* LVDS state */
311 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
312 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
313 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
314 if (IS_I965G(dev))
315 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
316 if (IS_MOBILE(dev) && !IS_I830(dev))
317 dev_priv->saveLVDS = I915_READ(LVDS);
318 if (!IS_I830(dev) && !IS_845G(dev))
319 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
320 dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
321 dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
322 dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
323
324 /* FIXME: save TV & SDVO state */
325
326 /* FBC state */
327 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
328 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
329 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
330 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
331
332 /* VGA state */
333 dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
334 dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
335 dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
336 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
337
338 /* Scratch space */
339 for (i = 0; i < 16; i++) {
340 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
341 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
342 }
343 for (i = 0; i < 3; i++)
344 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
345
346 i915_save_vga(dev);
347
348 /* Shut down the device */
349 pci_disable_device(dev->pdev);
350 pci_set_power_state(dev->pdev, PCI_D3hot);
351
352 return 0;
353}
354
355static int i915_resume(struct drm_device *dev)
356{
357 struct drm_i915_private *dev_priv = dev->dev_private;
358 int i;
359
360 pci_set_power_state(dev->pdev, PCI_D0);
361 pci_restore_state(dev->pdev);
362 if (pci_enable_device(dev->pdev))
363 return -1;
364
365 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
366
367 /* Pipe & plane A info */
368 /* Prime the clock */
369 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
370 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
371 ~DPLL_VCO_ENABLE);
372 udelay(150);
373 }
374 I915_WRITE(FPA0, dev_priv->saveFPA0);
375 I915_WRITE(FPA1, dev_priv->saveFPA1);
376 /* Actually enable it */
377 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
378 udelay(150);
379 if (IS_I965G(dev))
380 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
381 udelay(150);
382
383 /* Restore mode */
384 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
385 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
386 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
387 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
388 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
389 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
390 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
391
392 /* Restore plane info */
393 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
394 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
395 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
396 I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
397 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
398 if (IS_I965G(dev)) {
399 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
400 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
401 }
402
403 if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
404 (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
405 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
406
407 i915_restore_palette(dev, PIPE_A);
408 /* Enable the plane */
409 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
410 I915_WRITE(DSPABASE, I915_READ(DSPABASE));
411
412 /* Pipe & plane B info */
413 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
414 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
415 ~DPLL_VCO_ENABLE);
416 udelay(150);
417 }
418 I915_WRITE(FPB0, dev_priv->saveFPB0);
419 I915_WRITE(FPB1, dev_priv->saveFPB1);
420 /* Actually enable it */
421 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
422 udelay(150);
423 if (IS_I965G(dev))
424 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
425 udelay(150);
426
427 /* Restore mode */
428 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
429 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
430 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
431 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
432 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
433 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
434 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
435
436 /* Restore plane info */
437 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
438 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
439 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
440 I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
441 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
442 if (IS_I965G(dev)) {
443 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
444 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
445 }
446
447 if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
448 (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
449 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
450 i915_restore_palette(dev, PIPE_A);
451 /* Enable the plane */
452 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
453 I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
454
455 /* CRT state */
456 I915_WRITE(ADPA, dev_priv->saveADPA);
457
458 /* LVDS state */
459 if (IS_I965G(dev))
460 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
461 if (IS_MOBILE(dev) && !IS_I830(dev))
462 I915_WRITE(LVDS, dev_priv->saveLVDS);
463 if (!IS_I830(dev) && !IS_845G(dev))
464 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
465
466 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
467 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
468 I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
469 I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
470 I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
471 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
472
473 /* FIXME: restore TV & SDVO state */
474
475 /* FBC info */
476 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
477 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
478 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
479 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
480
481 /* VGA state */
482 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
483 I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
484 I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
485 I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
486 udelay(150);
487
488 for (i = 0; i < 16; i++) {
489 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
490 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
491 }
492 for (i = 0; i < 3; i++)
493 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
494
495 i915_restore_vga(dev);
496
497 return 0;
498}
499
41static struct drm_driver driver = { 500static struct drm_driver driver = {
42 /* don't use mtrr's here, the Xserver or user space app should 501 /* don't use mtrr's here, the Xserver or user space app should
43 * deal with them for intel hardware. 502 * deal with them for intel hardware.
@@ -47,8 +506,11 @@ static struct drm_driver driver = {
47 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL | 506 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
48 DRIVER_IRQ_VBL2, 507 DRIVER_IRQ_VBL2,
49 .load = i915_driver_load, 508 .load = i915_driver_load,
509 .unload = i915_driver_unload,
50 .lastclose = i915_driver_lastclose, 510 .lastclose = i915_driver_lastclose,
51 .preclose = i915_driver_preclose, 511 .preclose = i915_driver_preclose,
512 .suspend = i915_suspend,
513 .resume = i915_resume,
52 .device_is_agp = i915_driver_device_is_agp, 514 .device_is_agp = i915_driver_device_is_agp,
53 .vblank_wait = i915_driver_vblank_wait, 515 .vblank_wait = i915_driver_vblank_wait,
54 .vblank_wait2 = i915_driver_vblank_wait2, 516 .vblank_wait2 = i915_driver_vblank_wait2,
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index f8cc71915c8e..661e2f571195 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -114,6 +114,85 @@ typedef struct drm_i915_private {
114 spinlock_t swaps_lock; 114 spinlock_t swaps_lock;
115 drm_i915_vbl_swap_t vbl_swaps; 115 drm_i915_vbl_swap_t vbl_swaps;
116 unsigned int swaps_pending; 116 unsigned int swaps_pending;
117
118 /* Register state */
119 u8 saveLBB;
120 u32 saveDSPACNTR;
121 u32 saveDSPBCNTR;
122 u32 savePIPEACONF;
123 u32 savePIPEBCONF;
124 u32 savePIPEASRC;
125 u32 savePIPEBSRC;
126 u32 saveFPA0;
127 u32 saveFPA1;
128 u32 saveDPLL_A;
129 u32 saveDPLL_A_MD;
130 u32 saveHTOTAL_A;
131 u32 saveHBLANK_A;
132 u32 saveHSYNC_A;
133 u32 saveVTOTAL_A;
134 u32 saveVBLANK_A;
135 u32 saveVSYNC_A;
136 u32 saveBCLRPAT_A;
137 u32 saveDSPASTRIDE;
138 u32 saveDSPASIZE;
139 u32 saveDSPAPOS;
140 u32 saveDSPABASE;
141 u32 saveDSPASURF;
142 u32 saveDSPATILEOFF;
143 u32 savePFIT_PGM_RATIOS;
144 u32 saveBLC_PWM_CTL;
145 u32 saveBLC_PWM_CTL2;
146 u32 saveFPB0;
147 u32 saveFPB1;
148 u32 saveDPLL_B;
149 u32 saveDPLL_B_MD;
150 u32 saveHTOTAL_B;
151 u32 saveHBLANK_B;
152 u32 saveHSYNC_B;
153 u32 saveVTOTAL_B;
154 u32 saveVBLANK_B;
155 u32 saveVSYNC_B;
156 u32 saveBCLRPAT_B;
157 u32 saveDSPBSTRIDE;
158 u32 saveDSPBSIZE;
159 u32 saveDSPBPOS;
160 u32 saveDSPBBASE;
161 u32 saveDSPBSURF;
162 u32 saveDSPBTILEOFF;
163 u32 saveVCLK_DIVISOR_VGA0;
164 u32 saveVCLK_DIVISOR_VGA1;
165 u32 saveVCLK_POST_DIV;
166 u32 saveVGACNTRL;
167 u32 saveADPA;
168 u32 saveLVDS;
169 u32 saveLVDSPP_ON;
170 u32 saveLVDSPP_OFF;
171 u32 saveDVOA;
172 u32 saveDVOB;
173 u32 saveDVOC;
174 u32 savePP_ON;
175 u32 savePP_OFF;
176 u32 savePP_CONTROL;
177 u32 savePP_CYCLE;
178 u32 savePFIT_CONTROL;
179 u32 save_palette_a[256];
180 u32 save_palette_b[256];
181 u32 saveFBC_CFB_BASE;
182 u32 saveFBC_LL_BASE;
183 u32 saveFBC_CONTROL;
184 u32 saveFBC_CONTROL2;
185 u32 saveSWF0[16];
186 u32 saveSWF1[16];
187 u32 saveSWF2[3];
188 u8 saveMSR;
189 u8 saveSR[8];
190 u8 saveGR[24];
191 u8 saveAR_INDEX;
192 u8 saveAR[20];
193 u8 saveDACMASK;
194 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
195 u8 saveCR[36];
117} drm_i915_private_t; 196} drm_i915_private_t;
118 197
119extern struct drm_ioctl_desc i915_ioctls[]; 198extern struct drm_ioctl_desc i915_ioctls[];
@@ -122,6 +201,7 @@ extern int i915_max_ioctl;
122 /* i915_dma.c */ 201 /* i915_dma.c */
123extern void i915_kernel_lost_context(struct drm_device * dev); 202extern void i915_kernel_lost_context(struct drm_device * dev);
124extern int i915_driver_load(struct drm_device *, unsigned long flags); 203extern int i915_driver_load(struct drm_device *, unsigned long flags);
204extern int i915_driver_unload(struct drm_device *);
125extern void i915_driver_lastclose(struct drm_device * dev); 205extern void i915_driver_lastclose(struct drm_device * dev);
126extern void i915_driver_preclose(struct drm_device *dev, 206extern void i915_driver_preclose(struct drm_device *dev,
127 struct drm_file *file_priv); 207 struct drm_file *file_priv);
@@ -200,6 +280,50 @@ extern void i915_mem_release(struct drm_device * dev,
200 280
201extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 281extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
202 282
283/* Extended config space */
284#define LBB 0xf4
285
286/* VGA stuff */
287
288#define VGA_ST01_MDA 0x3ba
289#define VGA_ST01_CGA 0x3da
290
291#define VGA_MSR_WRITE 0x3c2
292#define VGA_MSR_READ 0x3cc
293#define VGA_MSR_MEM_EN (1<<1)
294#define VGA_MSR_CGA_MODE (1<<0)
295
296#define VGA_SR_INDEX 0x3c4
297#define VGA_SR_DATA 0x3c5
298
299#define VGA_AR_INDEX 0x3c0
300#define VGA_AR_VID_EN (1<<5)
301#define VGA_AR_DATA_WRITE 0x3c0
302#define VGA_AR_DATA_READ 0x3c1
303
304#define VGA_GR_INDEX 0x3ce
305#define VGA_GR_DATA 0x3cf
306/* GR05 */
307#define VGA_GR_MEM_READ_MODE_SHIFT 3
308#define VGA_GR_MEM_READ_MODE_PLANE 1
309/* GR06 */
310#define VGA_GR_MEM_MODE_MASK 0xc
311#define VGA_GR_MEM_MODE_SHIFT 2
312#define VGA_GR_MEM_A0000_AFFFF 0
313#define VGA_GR_MEM_A0000_BFFFF 1
314#define VGA_GR_MEM_B0000_B7FFF 2
315#define VGA_GR_MEM_B0000_BFFFF 3
316
317#define VGA_DACMASK 0x3c6
318#define VGA_DACRX 0x3c7
319#define VGA_DACWX 0x3c8
320#define VGA_DACDATA 0x3c9
321
322#define VGA_CR_INDEX_MDA 0x3b4
323#define VGA_CR_DATA_MDA 0x3b5
324#define VGA_CR_INDEX_CGA 0x3d4
325#define VGA_CR_DATA_CGA 0x3d5
326
203#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 327#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
204#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 328#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
205#define CMD_REPORT_HEAD (7<<23) 329#define CMD_REPORT_HEAD (7<<23)
@@ -215,6 +339,44 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
215#define BB1_UNPROTECTED (0<<0) 339#define BB1_UNPROTECTED (0<<0)
216#define BB2_END_ADDR_MASK (~0x7) 340#define BB2_END_ADDR_MASK (~0x7)
217 341
342/* Framebuffer compression */
343#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
344#define FBC_LL_BASE 0x03204 /* 4k page aligned */
345#define FBC_CONTROL 0x03208
346#define FBC_CTL_EN (1<<31)
347#define FBC_CTL_PERIODIC (1<<30)
348#define FBC_CTL_INTERVAL_SHIFT (16)
349#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
350#define FBC_CTL_STRIDE_SHIFT (5)
351#define FBC_CTL_FENCENO (1<<0)
352#define FBC_COMMAND 0x0320c
353#define FBC_CMD_COMPRESS (1<<0)
354#define FBC_STATUS 0x03210
355#define FBC_STAT_COMPRESSING (1<<31)
356#define FBC_STAT_COMPRESSED (1<<30)
357#define FBC_STAT_MODIFIED (1<<29)
358#define FBC_STAT_CURRENT_LINE (1<<0)
359#define FBC_CONTROL2 0x03214
360#define FBC_CTL_FENCE_DBL (0<<4)
361#define FBC_CTL_IDLE_IMM (0<<2)
362#define FBC_CTL_IDLE_FULL (1<<2)
363#define FBC_CTL_IDLE_LINE (2<<2)
364#define FBC_CTL_IDLE_DEBUG (3<<2)
365#define FBC_CTL_CPU_FENCE (1<<1)
366#define FBC_CTL_PLANEA (0<<0)
367#define FBC_CTL_PLANEB (1<<0)
368#define FBC_FENCE_OFF 0x0321b
369
370#define FBC_LL_SIZE (1536)
371#define FBC_LL_PAD (32)
372
373/* Interrupt bits:
374 */
375#define USER_INT_FLAG (1<<1)
376#define VSYNC_PIPEB_FLAG (1<<5)
377#define VSYNC_PIPEA_FLAG (1<<7)
378#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
379
218#define I915REG_HWSTAM 0x02098 380#define I915REG_HWSTAM 0x02098
219#define I915REG_INT_IDENTITY_R 0x020a4 381#define I915REG_INT_IDENTITY_R 0x020a4
220#define I915REG_INT_MASK_R 0x020a8 382#define I915REG_INT_MASK_R 0x020a8
@@ -251,6 +413,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
251#define NOPID 0x2094 413#define NOPID 0x2094
252#define LP_RING 0x2030 414#define LP_RING 0x2030
253#define HP_RING 0x2040 415#define HP_RING 0x2040
416/* The binner has its own ring buffer:
417 */
418#define HWB_RING 0x2400
419
254#define RING_TAIL 0x00 420#define RING_TAIL 0x00
255#define TAIL_ADDR 0x001FFFF8 421#define TAIL_ADDR 0x001FFFF8
256#define RING_HEAD 0x04 422#define RING_HEAD 0x04
@@ -269,11 +435,105 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
269#define RING_VALID 0x00000001 435#define RING_VALID 0x00000001
270#define RING_INVALID 0x00000000 436#define RING_INVALID 0x00000000
271 437
438/* Instruction parser error reg:
439 */
440#define IPEIR 0x2088
441
442/* Scratch pad debug 0 reg:
443 */
444#define SCPD0 0x209c
445
446/* Error status reg:
447 */
448#define ESR 0x20b8
449
450/* Secondary DMA fetch address debug reg:
451 */
452#define DMA_FADD_S 0x20d4
453
454/* Cache mode 0 reg.
455 * - Manipulating render cache behaviour is central
456 * to the concept of zone rendering, tuning this reg can help avoid
457 * unnecessary render cache reads and even writes (for z/stencil)
458 * at beginning and end of scene.
459 *
460 * - To change a bit, write to this reg with a mask bit set and the
461 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
462 */
463#define Cache_Mode_0 0x2120
464#define CM0_MASK_SHIFT 16
465#define CM0_IZ_OPT_DISABLE (1<<6)
466#define CM0_ZR_OPT_DISABLE (1<<5)
467#define CM0_DEPTH_EVICT_DISABLE (1<<4)
468#define CM0_COLOR_EVICT_DISABLE (1<<3)
469#define CM0_DEPTH_WRITE_DISABLE (1<<1)
470#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
471
472
473/* Graphics flush control. A CPU write flushes the GWB of all writes.
474 * The data is discarded.
475 */
476#define GFX_FLSH_CNTL 0x2170
477
478/* Binner control. Defines the location of the bin pointer list:
479 */
480#define BINCTL 0x2420
481#define BC_MASK (1 << 9)
482
483/* Binned scene info.
484 */
485#define BINSCENE 0x2428
486#define BS_OP_LOAD (1 << 8)
487#define BS_MASK (1 << 22)
488
489/* Bin command parser debug reg:
490 */
491#define BCPD 0x2480
492
493/* Bin memory control debug reg:
494 */
495#define BMCD 0x2484
496
497/* Bin data cache debug reg:
498 */
499#define BDCD 0x2488
500
501/* Binner pointer cache debug reg:
502 */
503#define BPCD 0x248c
504
505/* Binner scratch pad debug reg:
506 */
507#define BINSKPD 0x24f0
508
509/* HWB scratch pad debug reg:
510 */
511#define HWBSKPD 0x24f4
512
513/* Binner memory pool reg:
514 */
515#define BMP_BUFFER 0x2430
516#define BMP_PAGE_SIZE_4K (0 << 10)
517#define BMP_BUFFER_SIZE_SHIFT 1
518#define BMP_ENABLE (1 << 0)
519
520/* Get/put memory from the binner memory pool:
521 */
522#define BMP_GET 0x2438
523#define BMP_PUT 0x2440
524#define BMP_OFFSET_SHIFT 5
525
526/* 3D state packets:
527 */
528#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
529
272#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 530#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
273#define SC_UPDATE_SCISSOR (0x1<<1) 531#define SC_UPDATE_SCISSOR (0x1<<1)
274#define SC_ENABLE_MASK (0x1<<0) 532#define SC_ENABLE_MASK (0x1<<0)
275#define SC_ENABLE (0x1<<0) 533#define SC_ENABLE (0x1<<0)
276 534
535#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
536
277#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 537#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
278#define SCI_YMIN_MASK (0xffff<<16) 538#define SCI_YMIN_MASK (0xffff<<16)
279#define SCI_XMIN_MASK (0xffff<<0) 539#define SCI_XMIN_MASK (0xffff<<0)
@@ -290,6 +550,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
290 550
291#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 551#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
292 552
553#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
293#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 554#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
294#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 555#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
295#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 556#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
@@ -301,6 +562,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
301#define MI_BATCH_NON_SECURE_I965 (1<<8) 562#define MI_BATCH_NON_SECURE_I965 (1<<8)
302 563
303#define MI_WAIT_FOR_EVENT ((0x3<<23)) 564#define MI_WAIT_FOR_EVENT ((0x3<<23))
565#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
304#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 566#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
305#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 567#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
306 568
@@ -308,9 +570,535 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
308 570
309#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 571#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
310#define ASYNC_FLIP (1<<22) 572#define ASYNC_FLIP (1<<22)
573#define DISPLAY_PLANE_A (0<<20)
574#define DISPLAY_PLANE_B (1<<20)
575
576/* Display regs */
577#define DSPACNTR 0x70180
578#define DSPBCNTR 0x71180
579#define DISPPLANE_SEL_PIPE_MASK (1<<24)
580
581/* Define the region of interest for the binner:
582 */
583#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
311 584
312#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 585#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
313 586
314#define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5]) 587#define CMD_MI_FLUSH (0x04 << 23)
588#define MI_NO_WRITE_FLUSH (1 << 2)
589#define MI_READ_FLUSH (1 << 0)
590#define MI_EXE_FLUSH (1 << 1)
591#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
592#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
593
594#define BREADCRUMB_BITS 31
595#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
596
597#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
598#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
599
600#define BLC_PWM_CTL 0x61254
601#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
602
603#define BLC_PWM_CTL2 0x61250
604/**
605 * This is the most significant 15 bits of the number of backlight cycles in a
606 * complete cycle of the modulated backlight control.
607 *
608 * The actual value is this field multiplied by two.
609 */
610#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
611#define BLM_LEGACY_MODE (1 << 16)
612/**
613 * This is the number of cycles out of the backlight modulation cycle for which
614 * the backlight is on.
615 *
616 * This field must be no greater than the number of cycles in the complete
617 * backlight modulation cycle.
618 */
619#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
620#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
621
622#define I915_GCFGC 0xf0
623#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
624#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
625#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
626#define I915_DISPLAY_CLOCK_MASK (7 << 4)
627
628#define I855_HPLLCC 0xc0
629#define I855_CLOCK_CONTROL_MASK (3 << 0)
630#define I855_CLOCK_133_200 (0 << 0)
631#define I855_CLOCK_100_200 (1 << 0)
632#define I855_CLOCK_100_133 (2 << 0)
633#define I855_CLOCK_166_250 (3 << 0)
634
635/* p317, 319
636 */
637#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
638#define VCLK2_VCO_N 0x600a
639#define VCLK2_VCO_DIV_SEL 0x6012
640
641#define VCLK_DIVISOR_VGA0 0x6000
642#define VCLK_DIVISOR_VGA1 0x6004
643#define VCLK_POST_DIV 0x6010
644/** Selects a post divisor of 4 instead of 2. */
645# define VGA1_PD_P2_DIV_4 (1 << 15)
646/** Overrides the p2 post divisor field */
647# define VGA1_PD_P1_DIV_2 (1 << 13)
648# define VGA1_PD_P1_SHIFT 8
649/** P1 value is 2 greater than this field */
650# define VGA1_PD_P1_MASK (0x1f << 8)
651/** Selects a post divisor of 4 instead of 2. */
652# define VGA0_PD_P2_DIV_4 (1 << 7)
653/** Overrides the p2 post divisor field */
654# define VGA0_PD_P1_DIV_2 (1 << 5)
655# define VGA0_PD_P1_SHIFT 0
656/** P1 value is 2 greater than this field */
657# define VGA0_PD_P1_MASK (0x1f << 0)
658
659/* I830 CRTC registers */
660#define HTOTAL_A 0x60000
661#define HBLANK_A 0x60004
662#define HSYNC_A 0x60008
663#define VTOTAL_A 0x6000c
664#define VBLANK_A 0x60010
665#define VSYNC_A 0x60014
666#define PIPEASRC 0x6001c
667#define BCLRPAT_A 0x60020
668#define VSYNCSHIFT_A 0x60028
669
670#define HTOTAL_B 0x61000
671#define HBLANK_B 0x61004
672#define HSYNC_B 0x61008
673#define VTOTAL_B 0x6100c
674#define VBLANK_B 0x61010
675#define VSYNC_B 0x61014
676#define PIPEBSRC 0x6101c
677#define BCLRPAT_B 0x61020
678#define VSYNCSHIFT_B 0x61028
679
680#define PP_STATUS 0x61200
681# define PP_ON (1 << 31)
682/**
683 * Indicates that all dependencies of the panel are on:
684 *
685 * - PLL enabled
686 * - pipe enabled
687 * - LVDS/DVOB/DVOC on
688 */
689# define PP_READY (1 << 30)
690# define PP_SEQUENCE_NONE (0 << 28)
691# define PP_SEQUENCE_ON (1 << 28)
692# define PP_SEQUENCE_OFF (2 << 28)
693# define PP_SEQUENCE_MASK 0x30000000
694#define PP_CONTROL 0x61204
695# define POWER_TARGET_ON (1 << 0)
696
697#define LVDSPP_ON 0x61208
698#define LVDSPP_OFF 0x6120c
699#define PP_CYCLE 0x61210
700
701#define PFIT_CONTROL 0x61230
702# define PFIT_ENABLE (1 << 31)
703# define PFIT_PIPE_MASK (3 << 29)
704# define PFIT_PIPE_SHIFT 29
705# define VERT_INTERP_DISABLE (0 << 10)
706# define VERT_INTERP_BILINEAR (1 << 10)
707# define VERT_INTERP_MASK (3 << 10)
708# define VERT_AUTO_SCALE (1 << 9)
709# define HORIZ_INTERP_DISABLE (0 << 6)
710# define HORIZ_INTERP_BILINEAR (1 << 6)
711# define HORIZ_INTERP_MASK (3 << 6)
712# define HORIZ_AUTO_SCALE (1 << 5)
713# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
714
715#define PFIT_PGM_RATIOS 0x61234
716# define PFIT_VERT_SCALE_MASK 0xfff00000
717# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
718
719#define PFIT_AUTO_RATIOS 0x61238
720
721
722#define DPLL_A 0x06014
723#define DPLL_B 0x06018
724# define DPLL_VCO_ENABLE (1 << 31)
725# define DPLL_DVO_HIGH_SPEED (1 << 30)
726# define DPLL_SYNCLOCK_ENABLE (1 << 29)
727# define DPLL_VGA_MODE_DIS (1 << 28)
728# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
729# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
730# define DPLL_MODE_MASK (3 << 26)
731# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
732# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
733# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
734# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
735# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
736# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
737/**
738 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
739 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
740 */
741# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
742/**
743 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
744 * this field (only one bit may be set).
745 */
746# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
747# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
748# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
749# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
750# define PLL_REF_INPUT_DREFCLK (0 << 13)
751# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
752# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
753# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
754# define PLL_REF_INPUT_MASK (3 << 13)
755# define PLL_LOAD_PULSE_PHASE_SHIFT 9
756/*
757 * Parallel to Serial Load Pulse phase selection.
758 * Selects the phase for the 10X DPLL clock for the PCIe
759 * digital display port. The range is 4 to 13; 10 or more
760 * is just a flip delay. The default is 6
761 */
762# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
763# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
764
765/**
766 * SDVO multiplier for 945G/GM. Not used on 965.
767 *
768 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
769 */
770# define SDVO_MULTIPLIER_MASK 0x000000ff
771# define SDVO_MULTIPLIER_SHIFT_HIRES 4
772# define SDVO_MULTIPLIER_SHIFT_VGA 0
773
774/** @defgroup DPLL_MD
775 * @{
776 */
777/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
778#define DPLL_A_MD 0x0601c
779/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
780#define DPLL_B_MD 0x06020
781/**
782 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
783 *
784 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
785 */
786# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
787# define DPLL_MD_UDI_DIVIDER_SHIFT 24
788/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
789# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
790# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
791/**
792 * SDVO/UDI pixel multiplier.
793 *
794 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
795 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
796 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
797 * dummy bytes in the datastream at an increased clock rate, with both sides of
798 * the link knowing how many bytes are fill.
799 *
800 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
801 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
802 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
803 * through an SDVO command.
804 *
805 * This register field has values of multiplication factor minus 1, with
806 * a maximum multiplier of 5 for SDVO.
807 */
808# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
809# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
810/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
811 * This best be set to the default value (3) or the CRT won't work. No,
812 * I don't entirely understand what this does...
813 */
814# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
815# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
816/** @} */
817
818#define DPLL_TEST 0x606c
819# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
820# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
821# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
822# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
823# define DPLLB_TEST_N_BYPASS (1 << 19)
824# define DPLLB_TEST_M_BYPASS (1 << 18)
825# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
826# define DPLLA_TEST_N_BYPASS (1 << 3)
827# define DPLLA_TEST_M_BYPASS (1 << 2)
828# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
829
830#define ADPA 0x61100
831#define ADPA_DAC_ENABLE (1<<31)
832#define ADPA_DAC_DISABLE 0
833#define ADPA_PIPE_SELECT_MASK (1<<30)
834#define ADPA_PIPE_A_SELECT 0
835#define ADPA_PIPE_B_SELECT (1<<30)
836#define ADPA_USE_VGA_HVPOLARITY (1<<15)
837#define ADPA_SETS_HVPOLARITY 0
838#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
839#define ADPA_VSYNC_CNTL_ENABLE 0
840#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
841#define ADPA_HSYNC_CNTL_ENABLE 0
842#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
843#define ADPA_VSYNC_ACTIVE_LOW 0
844#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
845#define ADPA_HSYNC_ACTIVE_LOW 0
846
847#define FPA0 0x06040
848#define FPA1 0x06044
849#define FPB0 0x06048
850#define FPB1 0x0604c
851# define FP_N_DIV_MASK 0x003f0000
852# define FP_N_DIV_SHIFT 16
853# define FP_M1_DIV_MASK 0x00003f00
854# define FP_M1_DIV_SHIFT 8
855# define FP_M2_DIV_MASK 0x0000003f
856# define FP_M2_DIV_SHIFT 0
857
858
859#define PORT_HOTPLUG_EN 0x61110
860# define SDVOB_HOTPLUG_INT_EN (1 << 26)
861# define SDVOC_HOTPLUG_INT_EN (1 << 25)
862# define TV_HOTPLUG_INT_EN (1 << 18)
863# define CRT_HOTPLUG_INT_EN (1 << 9)
864# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
865
866#define PORT_HOTPLUG_STAT 0x61114
867# define CRT_HOTPLUG_INT_STATUS (1 << 11)
868# define TV_HOTPLUG_INT_STATUS (1 << 10)
869# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
870# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
871# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
872# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
873# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
874# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
875
876#define SDVOB 0x61140
877#define SDVOC 0x61160
878#define SDVO_ENABLE (1 << 31)
879#define SDVO_PIPE_B_SELECT (1 << 30)
880#define SDVO_STALL_SELECT (1 << 29)
881#define SDVO_INTERRUPT_ENABLE (1 << 26)
882/**
883 * 915G/GM SDVO pixel multiplier.
884 *
885 * Programmed value is multiplier - 1, up to 5x.
886 *
887 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
888 */
889#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
890#define SDVO_PORT_MULTIPLY_SHIFT 23
891#define SDVO_PHASE_SELECT_MASK (15 << 19)
892#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
893#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
894#define SDVOC_GANG_MODE (1 << 16)
895#define SDVO_BORDER_ENABLE (1 << 7)
896#define SDVOB_PCIE_CONCURRENCY (1 << 3)
897#define SDVO_DETECTED (1 << 2)
898/* Bits to be preserved when writing */
899#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
900#define SDVOC_PRESERVE_MASK (1 << 17)
901
902/** @defgroup LVDS
903 * @{
904 */
905/**
906 * This register controls the LVDS output enable, pipe selection, and data
907 * format selection.
908 *
909 * All of the clock/data pairs are force powered down by power sequencing.
910 */
911#define LVDS 0x61180
912/**
913 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
914 * the DPLL semantics change when the LVDS is assigned to that pipe.
915 */
916# define LVDS_PORT_EN (1 << 31)
917/** Selects pipe B for LVDS data. Must be set on pre-965. */
918# define LVDS_PIPEB_SELECT (1 << 30)
919
920/**
921 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
922 * pixel.
923 */
924# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
925# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
926# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
927/**
928 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
929 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
930 * on.
931 */
932# define LVDS_A3_POWER_MASK (3 << 6)
933# define LVDS_A3_POWER_DOWN (0 << 6)
934# define LVDS_A3_POWER_UP (3 << 6)
935/**
936 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
937 * is set.
938 */
939# define LVDS_CLKB_POWER_MASK (3 << 4)
940# define LVDS_CLKB_POWER_DOWN (0 << 4)
941# define LVDS_CLKB_POWER_UP (3 << 4)
942
943/**
944 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
945 * setting for whether we are in dual-channel mode. The B3 pair will
946 * additionally only be powered up when LVDS_A3_POWER_UP is set.
947 */
948# define LVDS_B0B3_POWER_MASK (3 << 2)
949# define LVDS_B0B3_POWER_DOWN (0 << 2)
950# define LVDS_B0B3_POWER_UP (3 << 2)
951
952#define PIPEACONF 0x70008
953#define PIPEACONF_ENABLE (1<<31)
954#define PIPEACONF_DISABLE 0
955#define PIPEACONF_DOUBLE_WIDE (1<<30)
956#define I965_PIPECONF_ACTIVE (1<<30)
957#define PIPEACONF_SINGLE_WIDE 0
958#define PIPEACONF_PIPE_UNLOCKED 0
959#define PIPEACONF_PIPE_LOCKED (1<<25)
960#define PIPEACONF_PALETTE 0
961#define PIPEACONF_GAMMA (1<<24)
962#define PIPECONF_FORCE_BORDER (1<<25)
963#define PIPECONF_PROGRESSIVE (0 << 21)
964#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
965#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
966
967#define PIPEBCONF 0x71008
968#define PIPEBCONF_ENABLE (1<<31)
969#define PIPEBCONF_DISABLE 0
970#define PIPEBCONF_DOUBLE_WIDE (1<<30)
971#define PIPEBCONF_DISABLE 0
972#define PIPEBCONF_GAMMA (1<<24)
973#define PIPEBCONF_PALETTE 0
974
975#define PIPEBGCMAXRED 0x71010
976#define PIPEBGCMAXGREEN 0x71014
977#define PIPEBGCMAXBLUE 0x71018
978#define PIPEBSTAT 0x71024
979#define PIPEBFRAMEHIGH 0x71040
980#define PIPEBFRAMEPIXEL 0x71044
981
982#define DSPACNTR 0x70180
983#define DSPBCNTR 0x71180
984#define DISPLAY_PLANE_ENABLE (1<<31)
985#define DISPLAY_PLANE_DISABLE 0
986#define DISPPLANE_GAMMA_ENABLE (1<<30)
987#define DISPPLANE_GAMMA_DISABLE 0
988#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
989#define DISPPLANE_8BPP (0x2<<26)
990#define DISPPLANE_15_16BPP (0x4<<26)
991#define DISPPLANE_16BPP (0x5<<26)
992#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
993#define DISPPLANE_32BPP (0x7<<26)
994#define DISPPLANE_STEREO_ENABLE (1<<25)
995#define DISPPLANE_STEREO_DISABLE 0
996#define DISPPLANE_SEL_PIPE_MASK (1<<24)
997#define DISPPLANE_SEL_PIPE_A 0
998#define DISPPLANE_SEL_PIPE_B (1<<24)
999#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1000#define DISPPLANE_SRC_KEY_DISABLE 0
1001#define DISPPLANE_LINE_DOUBLE (1<<20)
1002#define DISPPLANE_NO_LINE_DOUBLE 0
1003#define DISPPLANE_STEREO_POLARITY_FIRST 0
1004#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1005/* plane B only */
1006#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1007#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1008#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1009#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1010
1011#define DSPABASE 0x70184
1012#define DSPASTRIDE 0x70188
1013
1014#define DSPBBASE 0x71184
1015#define DSPBADDR DSPBBASE
1016#define DSPBSTRIDE 0x71188
1017
1018#define DSPAKEYVAL 0x70194
1019#define DSPAKEYMASK 0x70198
1020
1021#define DSPAPOS 0x7018C /* reserved */
1022#define DSPASIZE 0x70190
1023#define DSPBPOS 0x7118C
1024#define DSPBSIZE 0x71190
1025
1026#define DSPASURF 0x7019C
1027#define DSPATILEOFF 0x701A4
1028
1029#define DSPBSURF 0x7119C
1030#define DSPBTILEOFF 0x711A4
1031
1032#define VGACNTRL 0x71400
1033# define VGA_DISP_DISABLE (1 << 31)
1034# define VGA_2X_MODE (1 << 30)
1035# define VGA_PIPE_B_SELECT (1 << 29)
1036
1037/*
1038 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1039 * of video memory available to the BIOS in SWF1.
1040 */
1041
1042#define SWF0 0x71410
1043
1044/*
1045 * 855 scratch registers.
1046 */
1047#define SWF10 0x70410
1048
1049#define SWF30 0x72414
1050
1051/*
1052 * Overlay registers. These are overlay registers accessed via MMIO.
1053 * Those loaded via the overlay register page are defined in i830_video.c.
1054 */
1055#define OVADD 0x30000
1056
1057#define DOVSTA 0x30008
1058#define OC_BUF (0x3<<20)
1059
1060#define OGAMC5 0x30010
1061#define OGAMC4 0x30014
1062#define OGAMC3 0x30018
1063#define OGAMC2 0x3001c
1064#define OGAMC1 0x30020
1065#define OGAMC0 0x30024
1066/*
1067 * Palette registers
1068 */
1069#define PALETTE_A 0x0a000
1070#define PALETTE_B 0x0a800
1071
1072#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1073#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1074#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1075#define IS_I855(dev) ((dev)->pci_device == 0x3582)
1076#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1077
1078#define IS_I915G(dev) (dev->pci_device == 0x2582)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
1079#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1080#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1081#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
1082
1083#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1084 (dev)->pci_device == 0x2982 || \
1085 (dev)->pci_device == 0x2992 || \
1086 (dev)->pci_device == 0x29A2 || \
1087 (dev)->pci_device == 0x2A02 || \
1088 (dev)->pci_device == 0x2A12)
1089
1090#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1091
1092#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1093 (dev)->pci_device == 0x29B2 || \
1094 (dev)->pci_device == 0x29D2)
1095
1096#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1097 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1098
1099#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1100 IS_I945GM(dev) || IS_I965GM(dev))
1101
1102#define PRIMARY_RINGBUFFER_SIZE (128*1024)
315 1103
316#endif 1104#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 04:06:49 -0500