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-rw-r--r--arch/powerpc/kernel/cputable.c10
-rw-r--r--arch/ppc/platforms/4xx/Kconfig8
-rw-r--r--arch/ppc/platforms/4xx/Makefile1
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.c148
-rw-r--r--arch/ppc/platforms/4xx/ppc440spe.h66
-rw-r--r--arch/ppc/syslib/Makefile1
-rw-r--r--arch/ppc/syslib/ibm440sp_common.c4
-rw-r--r--arch/ppc/syslib/ibm44x_common.c2
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.c442
-rw-r--r--arch/ppc/syslib/ppc440spe_pcie.h149
-rw-r--r--arch/ppc/syslib/ppc4xx_pic.c37
-rw-r--r--include/asm-ppc/ibm44x.h55
12 files changed, 904 insertions, 19 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 33c63bcf69f8..cc4e9eb1c13f 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -929,6 +929,16 @@ struct cpu_spec cpu_specs[] = {
929 .icache_bsize = 32, 929 .icache_bsize = 32,
930 .dcache_bsize = 32, 930 .dcache_bsize = 32,
931 }, 931 },
932 { /* 440SPe Rev. A */
933 .pvr_mask = 0xff000fff,
934 .pvr_value = 0x53000890,
935 .cpu_name = "440SPe Rev. A",
936 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
937 CPU_FTR_USE_TB,
938 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
939 .icache_bsize = 32,
940 .dcache_bsize = 32,
941 },
932#endif /* CONFIG_44x */ 942#endif /* CONFIG_44x */
933#ifdef CONFIG_FSL_BOOKE 943#ifdef CONFIG_FSL_BOOKE
934 { /* e200z5 */ 944 { /* e200z5 */
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 76f4476cab44..108d5a730f84 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -124,9 +124,13 @@ config 440SP
124 depends on LUAN 124 depends on LUAN
125 default y 125 default y
126 126
127config 440SPE
128 bool
129 default n
130
127config 440 131config 440
128 bool 132 bool
129 depends on 440GP || 440SP || 440EP 133 depends on 440GP || 440SP || 440SPE || 440EP
130 default y 134 default y
131 135
132config 440A 136config 440A
@@ -168,7 +172,7 @@ config XILINX_OCP
168 172
169config IBM_EMAC4 173config IBM_EMAC4
170 bool 174 bool
171 depends on 440GX || 440SP 175 depends on 440GX || 440SP || 440SPE
172 default y 176 default y
173 177
174config BIOS_FIXUP 178config BIOS_FIXUP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 1dd6d7fd6a9a..694accdb59f7 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_440EP) += ibm440ep.o
22obj-$(CONFIG_440GP) += ibm440gp.o 22obj-$(CONFIG_440GP) += ibm440gp.o
23obj-$(CONFIG_440GX) += ibm440gx.o 23obj-$(CONFIG_440GX) += ibm440gx.o
24obj-$(CONFIG_440SP) += ibm440sp.o 24obj-$(CONFIG_440SP) += ibm440sp.o
25obj-$(CONFIG_440SPE) += ppc440spe.o
25obj-$(CONFIG_405EP) += ibm405ep.o 26obj-$(CONFIG_405EP) += ibm405ep.o
26obj-$(CONFIG_405GPR) += ibm405gpr.o 27obj-$(CONFIG_405GPR) += ibm405gpr.o
27obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o 28obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
new file mode 100644
index 000000000000..6139a0b3393e
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.c
@@ -0,0 +1,148 @@
1/*
2 * arch/ppc/platforms/4xx/ppc440spe.c
3 *
4 * PPC440SPe I/O descriptions
5 *
6 * Roland Dreier <rolandd@cisco.com>
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2002-2005 MontaVista Software Inc.
11 *
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 * Copyright (c) 2003, 2004 Zultys Technologies
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21#include <linux/init.h>
22#include <linux/module.h>
23#include <platforms/4xx/ppc440spe.h>
24#include <asm/ocp.h>
25#include <asm/ppc4xx_pic.h>
26
27static struct ocp_func_emac_data ppc440spe_emac0_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = -1, /* No ZMII */
31 .zmii_mux = -1, /* No ZMII */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 0, /* MAL rx channel number */
34 .mal_tx_chan = 0, /* MAL tx channel number */
35 .wol_irq = 61, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39OCP_SYSFS_EMAC_DATA()
40
41static struct ocp_func_mal_data ppc440spe_mal0_def = {
42 .num_tx_chans = 1, /* Number of TX channels */
43 .num_rx_chans = 1, /* Number of RX channels */
44 .txeob_irq = 38, /* TX End Of Buffer IRQ */
45 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
46 .txde_irq = 34, /* TX Descriptor Error IRQ */
47 .rxde_irq = 35, /* RX Descriptor Error IRQ */
48 .serr_irq = 33, /* MAL System Error IRQ */
49 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
50};
51OCP_SYSFS_MAL_DATA()
52
53static struct ocp_func_iic_data ppc440spe_iic0_def = {
54 .fast_mode = 0, /* Use standad mode (100Khz) */
55};
56
57static struct ocp_func_iic_data ppc440spe_iic1_def = {
58 .fast_mode = 0, /* Use standad mode (100Khz) */
59};
60OCP_SYSFS_IIC_DATA()
61
62struct ocp_def core_ocp[] = {
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_16550,
65 .index = 0,
66 .paddr = PPC440SPE_UART0_ADDR,
67 .irq = UART0_INT,
68 .pm = IBM_CPM_UART0,
69 },
70 { .vendor = OCP_VENDOR_IBM,
71 .function = OCP_FUNC_16550,
72 .index = 1,
73 .paddr = PPC440SPE_UART1_ADDR,
74 .irq = UART1_INT,
75 .pm = IBM_CPM_UART1,
76 },
77 { .vendor = OCP_VENDOR_IBM,
78 .function = OCP_FUNC_16550,
79 .index = 2,
80 .paddr = PPC440SPE_UART2_ADDR,
81 .irq = UART2_INT,
82 .pm = IBM_CPM_UART2,
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_IIC,
86 .index = 0,
87 .paddr = 0x00000004f0000400ULL,
88 .irq = 2,
89 .pm = IBM_CPM_IIC0,
90 .additions = &ppc440spe_iic0_def,
91 .show = &ocp_show_iic_data
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .index = 1,
96 .paddr = 0x00000004f0000500ULL,
97 .irq = 3,
98 .pm = IBM_CPM_IIC1,
99 .additions = &ppc440spe_iic1_def,
100 .show = &ocp_show_iic_data
101 },
102 { .vendor = OCP_VENDOR_IBM,
103 .function = OCP_FUNC_GPIO,
104 .index = 0,
105 .paddr = 0x00000004f0000700ULL,
106 .irq = OCP_IRQ_NA,
107 .pm = IBM_CPM_GPIO0,
108 },
109 { .vendor = OCP_VENDOR_IBM,
110 .function = OCP_FUNC_MAL,
111 .paddr = OCP_PADDR_NA,
112 .irq = OCP_IRQ_NA,
113 .pm = OCP_CPM_NA,
114 .additions = &ppc440spe_mal0_def,
115 .show = &ocp_show_mal_data,
116 },
117 { .vendor = OCP_VENDOR_IBM,
118 .function = OCP_FUNC_EMAC,
119 .index = 0,
120 .paddr = 0x00000004f0000800ULL,
121 .irq = 60,
122 .pm = OCP_CPM_NA,
123 .additions = &ppc440spe_emac0_def,
124 .show = &ocp_show_emac_data,
125 },
126 { .vendor = OCP_VENDOR_INVALID
127 }
128};
129
130/* Polarity and triggering settings for internal interrupt sources */
131struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
132 { .polarity = 0xffffffff,
133 .triggering = 0x010f0004,
134 .ext_irq_mask = 0x00000000,
135 },
136 { .polarity = 0xffffffff,
137 .triggering = 0x001f8040,
138 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
139 },
140 { .polarity = 0xffffffff,
141 .triggering = 0x00000000,
142 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
143 },
144 { .polarity = 0xffffffff,
145 .triggering = 0x00000000,
146 .ext_irq_mask = 0x00000000,
147 },
148};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
new file mode 100644
index 000000000000..2216846973b8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.h
@@ -0,0 +1,66 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440spe.h
3 *
4 * PPC440SPe definitions
5 *
6 * Roland Dreier <rolandd@cisco.com>
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2004-2005 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#ifdef __KERNEL__
19#ifndef __PPC_PLATFORMS_PPC440SPE_H
20#define __PPC_PLATFORMS_PPC440SPE_H
21
22#include <linux/config.h>
23
24#include <asm/ibm44x.h>
25
26/* UART */
27#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
28#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
29#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
30#define UART0_INT 0
31#define UART1_INT 1
32#define UART2_INT 37
33
34/* Clock and Power Management */
35#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
36#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
37#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
38#define IBM_CPM_CPU 0x02000000 /* processor core */
39#define IBM_CPM_DMA 0x01000000 /* DMA controller */
40#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
41#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
42#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
43#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
44#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
45#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
46#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
47#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
48#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
49#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
50#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
51#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
52#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
53#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
54#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
55#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
56#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
57
58#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
59 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
60 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
61 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
62 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
63 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
64 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
65#endif /* __PPC_PLATFORMS_PPC440SP_H */
66#endif /* __KERNEL__ */
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 2e58c2105225..13dff1e51f15 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common.o
15obj-$(CONFIG_440GP) += ibm440gp_common.o 15obj-$(CONFIG_440GP) += ibm440gp_common.o
16obj-$(CONFIG_440GX) += ibm440gx_common.o 16obj-$(CONFIG_440GX) += ibm440gx_common.o
17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o 17obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
18obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
18ifeq ($(CONFIG_4xx),y) 19ifeq ($(CONFIG_4xx),y)
19ifeq ($(CONFIG_VIRTEX_II_PRO),y) 20ifeq ($(CONFIG_VIRTEX_II_PRO),y)
20obj-$(CONFIG_40x) += xilinx_pic.o 21obj-$(CONFIG_40x) += xilinx_pic.o
diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c
index 417d4cff77a0..cdafda127d81 100644
--- a/arch/ppc/syslib/ibm440sp_common.c
+++ b/arch/ppc/syslib/ibm440sp_common.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/ppc/syslib/ibm440sp_common.c 2 * arch/ppc/syslib/ibm440sp_common.c
3 * 3 *
4 * PPC440SP system library 4 * PPC440SP/PPC440SPe system library
5 * 5 *
6 * Matt Porter <mporter@kernel.crashing.org> 6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc. 7 * Copyright 2002-2005 MontaVista Software Inc.
@@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_of_memory(void)
35 u32 mem_size = 0; 35 u32 mem_size = 0;
36 36
37 /* Read two bank sizes and sum */ 37 /* Read two bank sizes and sum */
38 for (i=0; i<2; i++) 38 for (i=0; i< MQ0_NUM_BANKS; i++)
39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { 39 switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) {
40 case MQ0_CONFIG_SIZE_8M: 40 case MQ0_CONFIG_SIZE_8M:
41 mem_size += PPC44x_MEM_SIZE_8M; 41 mem_size += PPC44x_MEM_SIZE_8M;
diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c
index ebae2e2fcea6..a5bef9d163ab 100644
--- a/arch/ppc/syslib/ibm44x_common.c
+++ b/arch/ppc/syslib/ibm44x_common.c
@@ -214,7 +214,7 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo
214/* Called from machine_check_exception */ 214/* Called from machine_check_exception */
215void platform_machine_check(struct pt_regs *regs) 215void platform_machine_check(struct pt_regs *regs)
216{ 216{
217#ifdef CONFIG_440SP 217#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
218 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", 218 printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
219 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), 219 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
220 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH), 220 mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c
new file mode 100644
index 000000000000..1509fc1ddfb6
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.c
@@ -0,0 +1,442 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/config.h>
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16
17#include <asm/reg.h>
18#include <asm/io.h>
19#include <asm/ibm44x.h>
20
21#include "ppc440spe_pcie.h"
22
23static int
24pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
25 int len, u32 *val)
26{
27 struct pci_controller *hose = bus->sysdata;
28
29 if (PCI_SLOT(devfn) != 1)
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 offset += devfn << 12;
33
34 /*
35 * Note: the caller has already checked that offset is
36 * suitably aligned and that len is 1, 2 or 4.
37 */
38 switch (len) {
39 case 1:
40 *val = in_8(hose->cfg_data + offset);
41 break;
42 case 2:
43 *val = in_le16(hose->cfg_data + offset);
44 break;
45 default:
46 *val = in_le32(hose->cfg_data + offset);
47 break;
48 }
49
50 if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
51
52 return PCIBIOS_SUCCESSFUL;
53}
54
55static int
56pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
57 int len, u32 val)
58{
59 struct pci_controller *hose = bus->sysdata;
60
61 if (PCI_SLOT(devfn) != 1)
62 return PCIBIOS_DEVICE_NOT_FOUND;
63
64 offset += devfn << 12;
65
66 switch (len) {
67 case 1:
68 out_8(hose->cfg_data + offset, val);
69 break;
70 case 2:
71 out_le16(hose->cfg_data + offset, val);
72 break;
73 default:
74 out_le32(hose->cfg_data + offset, val);
75 break;
76 }
77 return PCIBIOS_SUCCESSFUL;
78}
79
80static struct pci_ops pcie_pci_ops =
81{
82 .read = pcie_read_config,
83 .write = pcie_write_config
84};
85
86enum {
87 PTYPE_ENDPOINT = 0x0,
88 PTYPE_LEGACY_ENDPOINT = 0x1,
89 PTYPE_ROOT_PORT = 0x4,
90
91 LNKW_X1 = 0x1,
92 LNKW_X4 = 0x4,
93 LNKW_X8 = 0x8
94};
95
96static void check_error(void)
97{
98 u32 valPE0, valPE1, valPE2;
99
100 /* SDR0_PEGPLLLCT1 reset */
101 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
102 printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0);
103 }
104
105 valPE0 = SDR_READ(PESDR0_RCSSET);
106 valPE1 = SDR_READ(PESDR1_RCSSET);
107 valPE2 = SDR_READ(PESDR2_RCSSET);
108
109 /* SDR0_PExRCSSET rstgu */
110 if ( !(valPE0 & 0x01000000) ||
111 !(valPE1 & 0x01000000) ||
112 !(valPE2 & 0x01000000)) {
113 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
114 }
115
116 /* SDR0_PExRCSSET rstdl */
117 if ( !(valPE0 & 0x00010000) ||
118 !(valPE1 & 0x00010000) ||
119 !(valPE2 & 0x00010000)) {
120 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
121 }
122
123 /* SDR0_PExRCSSET rstpyn */
124 if ( (valPE0 & 0x00001000) ||
125 (valPE1 & 0x00001000) ||
126 (valPE2 & 0x00001000)) {
127 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
128 }
129
130 /* SDR0_PExRCSSET hldplb */
131 if ( (valPE0 & 0x10000000) ||
132 (valPE1 & 0x10000000) ||
133 (valPE2 & 0x10000000)) {
134 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
135 }
136
137 /* SDR0_PExRCSSET rdy */
138 if ( (valPE0 & 0x00100000) ||
139 (valPE1 & 0x00100000) ||
140 (valPE2 & 0x00100000)) {
141 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
142 }
143
144 /* SDR0_PExRCSSET shutdown */
145 if ( (valPE0 & 0x00000100) ||
146 (valPE1 & 0x00000100) ||
147 (valPE2 & 0x00000100)) {
148 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
149 }
150}
151
152/*
153 * Initialize PCI Express core as described in User Manual section 27.12.1
154 */
155int ppc440spe_init_pcie(void)
156{
157 /* Set PLL clock receiver to LVPECL */
158 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
159
160 check_error();
161
162 printk(KERN_INFO "PCIE initialization OK\n");
163
164 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
165 printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
166 SDR_READ(PESDR0_PLLLCT2));
167
168 /* De-assert reset of PCIe PLL, wait for lock */
169 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
170 udelay(3);
171
172 return 0;
173}
174
175int ppc440spe_init_pcie_rootport(int port)
176{
177 static int core_init;
178 void __iomem *utl_base;
179 u32 val = 0;
180 int i;
181
182 if (!core_init) {
183 ++core_init;
184 i = ppc440spe_init_pcie();
185 if (i)
186 return i;
187 }
188
189 /*
190 * Initialize various parts of the PCI Express core for our port:
191 *
192 * - Set as a root port and enable max width
193 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
194 * - Set up UTL configuration.
195 * - Increase SERDES drive strength to levels suggested by AMCC.
196 * - De-assert RSTPYN, RSTDL and RSTGU.
197 */
198 switch (port) {
199 case 0:
200 SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
201
202 SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
203 SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
204
205 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
206 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
207 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
208 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
209 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
210 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
211 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
212 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
213
214 SDR_WRITE(PESDR0_RCSSET,
215 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
216 break;
217
218 case 1:
219 SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
220
221 SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
222 SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
223
224 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
225 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
226 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
227 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
228
229 SDR_WRITE(PESDR1_RCSSET,
230 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
231 break;
232
233 case 2:
234 SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
235
236 SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
237 SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
238
239 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
240 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
241 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
242 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
243
244 SDR_WRITE(PESDR2_RCSSET,
245 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
246 break;
247 }
248
249 mdelay(1000);
250
251 switch (port) {
252 case 0: val = SDR_READ(PESDR0_RCSSTS); break;
253 case 1: val = SDR_READ(PESDR1_RCSSTS); break;
254 case 2: val = SDR_READ(PESDR2_RCSSTS); break;
255 }
256
257 if (!(val & (1 << 20)))
258 printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
259 else
260 printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
261
262 switch (port) {
263 case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
264 case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
265 case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
266 }
267
268 /*
269 * Map UTL registers at 0xc_1000_0n00
270 */
271 switch (port) {
272 case 0:
273 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
274 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
275 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
276 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
277 break;
278
279 case 1:
280 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
281 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
282 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
283 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
284 break;
285
286 case 2:
287 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
288 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
289 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
290 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
291 }
292
293 utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
294
295 /*
296 * Set buffer allocations and then assert VRB and TXE.
297 */
298 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
299 out_be32(utl_base + PEUTL_INTR, 0x02000000);
300 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
301 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
302 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
303 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
304 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
305 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
306
307 iounmap(utl_base);
308
309 /*
310 * We map PCI Express configuration access into the 512MB regions
311 * PCIE0: 0xc_4000_0000
312 * PCIE1: 0xc_8000_0000
313 * PCIE2: 0xc_c000_0000
314 */
315 switch (port) {
316 case 0:
317 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
318 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
319 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
320 break;
321
322 case 1:
323 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
324 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
325 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
326 break;
327
328 case 2:
329 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
330 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
331 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
332 break;
333 }
334
335 /*
336 * Check for VC0 active and assert RDY.
337 */
338 switch (port) {
339 case 0:
340 if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
341 printk(KERN_WARNING "PCIE0: VC0 not active\n");
342 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
343 break;
344 case 1:
345 if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
346 printk(KERN_WARNING "PCIE0: VC0 not active\n");
347 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
348 break;
349 case 2:
350 if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
351 printk(KERN_WARNING "PCIE0: VC0 not active\n");
352 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
353 break;
354 }
355
356#if 0
357 /* Dump all config regs */
358 for (i = 0x300; i <= 0x320; ++i)
359 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
360 for (i = 0x340; i <= 0x353; ++i)
361 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
362 for (i = 0x370; i <= 0x383; ++i)
363 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
364 for (i = 0x3a0; i <= 0x3a2; ++i)
365 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
366 for (i = 0x3c0; i <= 0x3c3; ++i)
367 printk("[%04x] 0x%08x\n", i, SDR_READ(i));
368#endif
369
370 mdelay(100);
371
372 return 0;
373}
374
375void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
376{
377 void __iomem *mbase;
378
379 /*
380 * Map 16MB, which is enough for 4 bits of bus #
381 */
382 hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000,
383 1 << 24);
384 hose->ops = &pcie_pci_ops;
385
386 /*
387 * Set bus numbers on our root port
388 */
389 mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096);
390 out_8(mbase + PCI_PRIMARY_BUS, 0);
391 out_8(mbase + PCI_SECONDARY_BUS, 0);
392
393 /*
394 * Set up outbound translation to hose->mem_space from PLB
395 * addresses at an offset of 0xd_0000_0000. We set the low
396 * bits of the mask to 11 to turn off splitting into 8
397 * subregions and to enable the outbound translation.
398 */
399 out_le32(mbase + PECFG_POM0LAH, 0);
400 out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start);
401
402 switch (port) {
403 case 0:
404 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
405 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start);
406 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
407 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
408 ~(hose->mem_space.end - hose->mem_space.start) | 3);
409 break;
410 case 1:
411 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
412 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start);
413 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
414 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
415 ~(hose->mem_space.end - hose->mem_space.start) | 3);
416
417 break;
418 case 2:
419 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
420 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start);
421 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
422 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
423 ~(hose->mem_space.end - hose->mem_space.start) | 3);
424 break;
425 }
426
427 /* Set up 16GB inbound memory window at 0 */
428 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
429 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
430 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
431 out_le32(mbase + PECFG_BAR0LMPA, 0);
432 out_le32(mbase + PECFG_PIM0LAL, 0);
433 out_le32(mbase + PECFG_PIM0LAH, 0);
434 out_le32(mbase + PECFG_PIMEN, 0x1);
435
436 /* Enable I/O, Mem, and Busmaster cycles */
437 out_le16(mbase + PCI_COMMAND,
438 in_le16(mbase + PCI_COMMAND) |
439 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
440
441 iounmap(mbase);
442}
diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h
new file mode 100644
index 000000000000..55b765ad3272
--- /dev/null
+++ b/arch/ppc/syslib/ppc440spe_pcie.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2005 Cisco Systems. All rights reserved.
3 * Roland Dreier <rolandd@cisco.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H
12#define __PPC_SYSLIB_PPC440SPE_PCIE_H
13
14#define DCRN_SDR0_CFGADDR 0x00e
15#define DCRN_SDR0_CFGDATA 0x00f
16
17#define DCRN_PCIE0_BASE 0x100
18#define DCRN_PCIE1_BASE 0x120
19#define DCRN_PCIE2_BASE 0x140
20#define PCIE0 DCRN_PCIE0_BASE
21#define PCIE1 DCRN_PCIE1_BASE
22#define PCIE2 DCRN_PCIE2_BASE
23
24#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
25#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
26#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
27#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
28#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
29#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
30#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
31#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
32#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
33#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
34#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
35#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
36#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
37#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
38
39/*
40 * System DCRs (SDRs)
41 */
42#define PESDR0_PLLLCT1 0x03a0
43#define PESDR0_PLLLCT2 0x03a1
44#define PESDR0_PLLLCT3 0x03a2
45
46#define PESDR0_UTLSET1 0x0300
47#define PESDR0_UTLSET2 0x0301
48#define PESDR0_DLPSET 0x0302
49#define PESDR0_LOOP 0x0303
50#define PESDR0_RCSSET 0x0304
51#define PESDR0_RCSSTS 0x0305
52#define PESDR0_HSSL0SET1 0x0306
53#define PESDR0_HSSL0SET2 0x0307
54#define PESDR0_HSSL0STS 0x0308
55#define PESDR0_HSSL1SET1 0x0309
56#define PESDR0_HSSL1SET2 0x030a
57#define PESDR0_HSSL1STS 0x030b
58#define PESDR0_HSSL2SET1 0x030c
59#define PESDR0_HSSL2SET2 0x030d
60#define PESDR0_HSSL2STS 0x030e
61#define PESDR0_HSSL3SET1 0x030f
62#define PESDR0_HSSL3SET2 0x0310
63#define PESDR0_HSSL3STS 0x0311
64#define PESDR0_HSSL4SET1 0x0312
65#define PESDR0_HSSL4SET2 0x0313
66#define PESDR0_HSSL4STS 0x0314
67#define PESDR0_HSSL5SET1 0x0315
68#define PESDR0_HSSL5SET2 0x0316
69#define PESDR0_HSSL5STS 0x0317
70#define PESDR0_HSSL6SET1 0x0318
71#define PESDR0_HSSL6SET2 0x0319
72#define PESDR0_HSSL6STS 0x031a
73#define PESDR0_HSSL7SET1 0x031b
74#define PESDR0_HSSL7SET2 0x031c
75#define PESDR0_HSSL7STS 0x031d
76#define PESDR0_HSSCTLSET 0x031e
77#define PESDR0_LANE_ABCD 0x031f
78#define PESDR0_LANE_EFGH 0x0320
79
80#define PESDR1_UTLSET1 0x0340
81#define PESDR1_UTLSET2 0x0341
82#define PESDR1_DLPSET 0x0342
83#define PESDR1_LOOP 0x0343
84#define PESDR1_RCSSET 0x0344
85#define PESDR1_RCSSTS 0x0345
86#define PESDR1_HSSL0SET1 0x0346
87#define PESDR1_HSSL0SET2 0x0347
88#define PESDR1_HSSL0STS 0x0348
89#define PESDR1_HSSL1SET1 0x0349
90#define PESDR1_HSSL1SET2 0x034a
91#define PESDR1_HSSL1STS 0x034b
92#define PESDR1_HSSL2SET1 0x034c
93#define PESDR1_HSSL2SET2 0x034d
94#define PESDR1_HSSL2STS 0x034e
95#define PESDR1_HSSL3SET1 0x034f
96#define PESDR1_HSSL3SET2 0x0350
97#define PESDR1_HSSL3STS 0x0351
98#define PESDR1_HSSCTLSET 0x0352
99#define PESDR1_LANE_ABCD 0x0353
100
101#define PESDR2_UTLSET1 0x0370
102#define PESDR2_UTLSET2 0x0371
103#define PESDR2_DLPSET 0x0372
104#define PESDR2_LOOP 0x0373
105#define PESDR2_RCSSET 0x0374
106#define PESDR2_RCSSTS 0x0375
107#define PESDR2_HSSL0SET1 0x0376
108#define PESDR2_HSSL0SET2 0x0377
109#define PESDR2_HSSL0STS 0x0378
110#define PESDR2_HSSL1SET1 0x0379
111#define PESDR2_HSSL1SET2 0x037a
112#define PESDR2_HSSL1STS 0x037b
113#define PESDR2_HSSL2SET1 0x037c
114#define PESDR2_HSSL2SET2 0x037d
115#define PESDR2_HSSL2STS 0x037e
116#define PESDR2_HSSL3SET1 0x037f
117#define PESDR2_HSSL3SET2 0x0380
118#define PESDR2_HSSL3STS 0x0381
119#define PESDR2_HSSCTLSET 0x0382
120#define PESDR2_LANE_ABCD 0x0383
121
122/*
123 * UTL register offsets
124 */
125#define PEUTL_PBBSZ 0x20
126#define PEUTL_OPDBSZ 0x68
127#define PEUTL_IPHBSZ 0x70
128#define PEUTL_IPDBSZ 0x78
129#define PEUTL_OUTTR 0x90
130#define PEUTL_INTR 0x98
131#define PEUTL_PCTL 0xa0
132#define PEUTL_RCIRQEN 0xb8
133
134/*
135 * Config space register offsets
136 */
137#define PECFG_BAR0LMPA 0x210
138#define PECFG_BAR0HMPA 0x214
139#define PECFG_PIMEN 0x33c
140#define PECFG_PIM0LAL 0x340
141#define PECFG_PIM0LAH 0x344
142#define PECFG_POM0LAL 0x380
143#define PECFG_POM0LAH 0x384
144
145int ppc440spe_init_pcie(void);
146int ppc440spe_init_pcie_rootport(int port);
147void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
148
149#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */
diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 0b435633a0d1..aa4165144ec2 100644
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -38,6 +38,7 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) 38#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) 39#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) 40#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
41#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq)
41 42
42#define UIC_HANDLERS(n) \ 43#define UIC_HANDLERS(n) \
43static void ppc4xx_uic##n##_enable(unsigned int irq) \ 44static void ppc4xx_uic##n##_enable(unsigned int irq) \
@@ -88,7 +89,38 @@ static void ppc4xx_uic##n##_end(unsigned int irq) \
88 .end = ppc4xx_uic##n##_end, \ 89 .end = ppc4xx_uic##n##_end, \
89} \ 90} \
90 91
91#if NR_UICS == 3 92#if NR_UICS == 4
93#define ACK_UIC0_PARENT
94#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
95#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
96#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
97UIC_HANDLERS(0);
98UIC_HANDLERS(1);
99UIC_HANDLERS(2);
100UIC_HANDLERS(3);
101
102static int ppc4xx_pic_get_irq(struct pt_regs *regs)
103{
104 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
105 if (uic0 & UIC0_UIC1NC)
106 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
107 else if (uic0 & UIC0_UIC2NC)
108 return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
109 else if (uic0 & UIC0_UIC3NC)
110 return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3)));
111 else
112 return uic0 ? 32 - ffs(uic0) : -1;
113}
114
115static void __init ppc4xx_pic_impl_init(void)
116{
117 /* Enable cascade interrupts in UIC0 */
118 ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
119 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
120 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
121}
122
123#elif NR_UICS == 3
92#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); 124#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
93#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); 125#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
94#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); 126#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -170,6 +202,9 @@ static struct ppc4xx_uic_impl {
170 { .decl = DECLARE_UIC(1), .base = UIC1 }, 202 { .decl = DECLARE_UIC(1), .base = UIC1 },
171#if NR_UICS > 2 203#if NR_UICS > 2
172 { .decl = DECLARE_UIC(2), .base = UIC2 }, 204 { .decl = DECLARE_UIC(2), .base = UIC2 },
205#if NR_UICS > 3
206 { .decl = DECLARE_UIC(3), .base = UIC3 },
207#endif
173#endif 208#endif
174#endif 209#endif
175}; 210};
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 0c2ba03a1d49..f835066fb3ca 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -41,6 +41,9 @@
41#if defined(CONFIG_440SP) 41#if defined(CONFIG_440SP)
42#define UART0_PHYS_ERPN 1 42#define UART0_PHYS_ERPN 1
43#define UART0_PHYS_IO_BASE 0xf0000200 43#define UART0_PHYS_IO_BASE 0xf0000200
44#elif defined(CONFIG_440SPE)
45#define UART0_PHYS_ERPN 4
46#define UART0_PHYS_IO_BASE 0xf0000200
44#elif defined(CONFIG_440EP) 47#elif defined(CONFIG_440EP)
45#define UART0_PHYS_IO_BASE 0xe0000000 48#define UART0_PHYS_IO_BASE 0xe0000000
46#else 49#else
@@ -61,6 +64,11 @@
61#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 64#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 65#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 66#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
67#elif defined(CONFIG_440SPE)
68#define PPC44x_IO_PAGE 0x0000000400000000ULL
69#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL
70#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
71#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL
64#elif defined(CONFIG_440EP) 72#elif defined(CONFIG_440EP)
65#define PPC44x_IO_PAGE 0x0000000000000000ULL 73#define PPC44x_IO_PAGE 0x0000000000000000ULL
66#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL 74#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
@@ -76,7 +84,7 @@
76/* 84/*
77 * 36-bit trap ranges 85 * 36-bit trap ranges
78 */ 86 */
79#if defined(CONFIG_440SP) 87#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
80#define PPC44x_IO_LO 0xf0000000UL 88#define PPC44x_IO_LO 0xf0000000UL
81#define PPC44x_IO_HI 0xf0000fffUL 89#define PPC44x_IO_HI 0xf0000fffUL
82#define PPC44x_PCI0CFG_LO 0x0ec00000UL 90#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -114,7 +122,7 @@
114 */ 122 */
115 123
116 124
117/* CPRs (440GX and 440SP) */ 125/* CPRs (440GX and 440SP/440SPe) */
118#define DCRN_CPR_CONFIG_ADDR 0xc 126#define DCRN_CPR_CONFIG_ADDR 0xc
119#define DCRN_CPR_CONFIG_DATA 0xd 127#define DCRN_CPR_CONFIG_DATA 0xd
120 128
@@ -135,7 +143,7 @@
135 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 143 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
136 mtdcr(DCRN_CPR_CONFIG_DATA, data);}) 144 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
137 145
138/* SDRs (440GX and 440SP) */ 146/* SDRs (440GX and 440SP/440SPe) */
139#define DCRN_SDR_CONFIG_ADDR 0xe 147#define DCRN_SDR_CONFIG_ADDR 0xe
140#define DCRN_SDR_CONFIG_DATA 0xf 148#define DCRN_SDR_CONFIG_DATA 0xf
141#define DCRN_SDR_PFC0 0x4100 149#define DCRN_SDR_PFC0 0x4100
@@ -185,7 +193,7 @@
185 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 193 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
186 mtdcr(DCRN_SDR_CONFIG_DATA,data);}) 194 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
187 195
188/* DMA (excluding 440SP) */ 196/* DMA (excluding 440SP/440SPe) */
189#define DCRN_DMA0_BASE 0x100 197#define DCRN_DMA0_BASE 0x100
190#define DCRN_DMA1_BASE 0x108 198#define DCRN_DMA1_BASE 0x108
191#define DCRN_DMA2_BASE 0x110 199#define DCRN_DMA2_BASE 0x110
@@ -205,12 +213,20 @@
205/* UIC */ 213/* UIC */
206#define DCRN_UIC0_BASE 0xc0 214#define DCRN_UIC0_BASE 0xc0
207#define DCRN_UIC1_BASE 0xd0 215#define DCRN_UIC1_BASE 0xd0
208#define DCRN_UIC2_BASE 0x210
209#define DCRN_UICB_BASE 0x200
210#define UIC0 DCRN_UIC0_BASE 216#define UIC0 DCRN_UIC0_BASE
211#define UIC1 DCRN_UIC1_BASE 217#define UIC1 DCRN_UIC1_BASE
218
219#ifdef CONFIG_440SPE
220#define DCRN_UIC2_BASE 0xe0
221#define DCRN_UIC3_BASE 0xf0
222#define UIC2 DCRN_UIC2_BASE
223#define UIC3 DCRN_UIC3_BASE
224#else
225#define DCRN_UIC2_BASE 0x210
226#define DCRN_UICB_BASE 0x200
212#define UIC2 DCRN_UIC2_BASE 227#define UIC2 DCRN_UIC2_BASE
213#define UICB DCRN_UICB_BASE 228#define UICB DCRN_UICB_BASE
229#endif
214 230
215#define DCRN_UIC_SR(base) (base + 0x0) 231#define DCRN_UIC_SR(base) (base + 0x0)
216#define DCRN_UIC_ER(base) (base + 0x2) 232#define DCRN_UIC_ER(base) (base + 0x2)
@@ -223,6 +239,12 @@
223 239
224#define UIC0_UIC1NC 0x00000002 240#define UIC0_UIC1NC 0x00000002
225 241
242#ifdef CONFIG_440SPE
243#define UIC0_UIC1NC 0x00000002
244#define UIC0_UIC2NC 0x00200000
245#define UIC0_UIC3NC 0x00008000
246#endif
247
226#define UICB_UIC0NC 0x40000000 248#define UICB_UIC0NC 0x40000000
227#define UICB_UIC1NC 0x10000000 249#define UICB_UIC1NC 0x10000000
228#define UICB_UIC2NC 0x04000000 250#define UICB_UIC2NC 0x04000000
@@ -302,8 +324,8 @@
302#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ 324#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
303#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ 325#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
304 326
305#if defined(CONFIG_440SP) 327#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
306/* 440SP PLB Arbiter DCRs */ 328/* 440SP/440SPe PLB Arbiter DCRs */
307#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ 329#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
308#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ 330#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
309 331
@@ -430,9 +452,13 @@
430#define PPC44x_MEM_SIZE_1G 0x40000000 452#define PPC44x_MEM_SIZE_1G 0x40000000
431#define PPC44x_MEM_SIZE_2G 0x80000000 453#define PPC44x_MEM_SIZE_2G 0x80000000
432 454
433/* 440SP memory controller DCRs */ 455/* 440SP/440SPe memory controller DCRs */
434#define DCRN_MQ0_BS0BAS 0x40 456#define DCRN_MQ0_BS0BAS 0x40
435#define DCRN_MQ0_BS1BAS 0x41 457#if defined(CONFIG_440SP)
458#define MQ0_NUM_BANKS 2
459#elif defined(CONFIG_440SPE)
460#define MQ0_NUM_BANKS 4
461#endif
436 462
437#define MQ0_CONFIG_SIZE_MASK 0x0000fff0 463#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
438#define MQ0_CONFIG_SIZE_8M 0x0000ffc0 464#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
@@ -444,8 +470,9 @@
444#define MQ0_CONFIG_SIZE_512M 0x0000f000 470#define MQ0_CONFIG_SIZE_512M 0x0000f000
445#define MQ0_CONFIG_SIZE_1G 0x0000e000 471#define MQ0_CONFIG_SIZE_1G 0x0000e000
446#define MQ0_CONFIG_SIZE_2G 0x0000c000 472#define MQ0_CONFIG_SIZE_2G 0x0000c000
473#define MQ0_CONFIG_SIZE_4G 0x00008000
447 474
448/* Internal SRAM Controller 440GX/440SP */ 475/* Internal SRAM Controller 440GX/440SP/440SPe */
449#define DCRN_SRAM0_BASE 0x000 476#define DCRN_SRAM0_BASE 0x000
450 477
451#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) 478#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
@@ -469,7 +496,7 @@
469#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) 496#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
470#define SRAM_DPC_ENABLE 0x80000000 497#define SRAM_DPC_ENABLE 0x80000000
471 498
472/* L2 Cache Controller 440GX/440SP */ 499/* L2 Cache Controller 440GX/440SP/440SPe */
473#define DCRN_L2C0_CFG 0x030 500#define DCRN_L2C0_CFG 0x030
474#define L2C_CFG_L2M 0x80000000 501#define L2C_CFG_L2M 0x80000000
475#define L2C_CFG_ICU 0x40000000 502#define L2C_CFG_ICU 0x40000000
@@ -633,8 +660,10 @@
633#define IIC_CLOCK 50 660#define IIC_CLOCK 50
634 661
635#undef NR_UICS 662#undef NR_UICS
636#ifdef CONFIG_440GX 663#if defined(CONFIG_440GX)
637#define NR_UICS 3 664#define NR_UICS 3
665#elif defined(CONFIG_440SPE)
666#define NR_UICS 4
638#else 667#else
639#define NR_UICS 2 668#define NR_UICS 2
640#endif 669#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 02:19:27 -0500