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-rw-r--r--arch/arm/kernel/entry-header.S18
-rw-r--r--arch/arm/vfp/entry.S1
-rw-r--r--include/asm-arm/assembler.h27
3 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 55c99cdab7d6..f1c2fd5b63e4 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -37,24 +37,6 @@
37#endif 37#endif
38 .endm 38 .endm
39 39
40#if __LINUX_ARM_ARCH__ >= 6
41 .macro disable_irq
42 cpsid i
43 .endm
44
45 .macro enable_irq
46 cpsie i
47 .endm
48#else
49 .macro disable_irq
50 msr cpsr_c, #PSR_I_BIT | SVC_MODE
51 .endm
52
53 .macro enable_irq
54 msr cpsr_c, #SVC_MODE
55 .endm
56#endif
57
58 .macro get_thread_info, rd 40 .macro get_thread_info, rd
59 mov \rd, sp, lsr #13 41 mov \rd, sp, lsr #13
60 mov \rd, \rd, lsl #13 42 mov \rd, \rd, lsl #13
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 9ab1abfbe7ad..7b595547c1c8 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -18,6 +18,7 @@
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/assembler.h>
21#include <asm/vfpmacros.h> 22#include <asm/vfpmacros.h>
22 23
23 .globl do_vfp 24 .globl do_vfp
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index f31ac92b6c7f..d53bafa9bf1c 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -80,16 +80,33 @@
80 instr regs 80 instr regs
81 81
82/* 82/*
83 * Save the current IRQ state and disable IRQs. Note that this macro 83 * Enable and disable interrupts
84 * assumes FIQs are enabled, and that the processor is in SVC mode.
85 */ 84 */
86 .macro save_and_disable_irqs, oldcpsr
87 mrs \oldcpsr, cpsr
88#if __LINUX_ARM_ARCH__ >= 6 85#if __LINUX_ARM_ARCH__ >= 6
86 .macro disable_irq
89 cpsid i 87 cpsid i
88 .endm
89
90 .macro enable_irq
91 cpsie i
92 .endm
90#else 93#else
91 msr cpsr_c, #PSR_I_BIT | MODE_SVC 94 .macro disable_irq
95 msr cpsr_c, #PSR_I_BIT | SVC_MODE
96 .endm
97
98 .macro enable_irq
99 msr cpsr_c, #SVC_MODE
100 .endm
92#endif 101#endif
102
103/*
104 * Save the current IRQ state and disable IRQs. Note that this macro
105 * assumes FIQs are enabled, and that the processor is in SVC mode.
106 */
107 .macro save_and_disable_irqs, oldcpsr
108 mrs \oldcpsr, cpsr
109 disable_irq
93 .endm 110 .endm
94 111
95/* 112/*