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-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head-epxa10db.S5
-rw-r--r--arch/arm/configs/epxa10db_defconfig644
-rw-r--r--arch/arm/mach-epxa10db/Kconfig23
-rw-r--r--arch/arm/mach-epxa10db/Makefile11
-rw-r--r--arch/arm/mach-epxa10db/Makefile.boot2
-rw-r--r--arch/arm/mach-epxa10db/arch.c74
-rw-r--r--arch/arm/mach-epxa10db/irq.c82
-rw-r--r--arch/arm/mach-epxa10db/mm.c71
-rw-r--r--arch/arm/mach-epxa10db/time.c78
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/mtd/maps/Kconfig8
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/epxa10db-flash.c179
-rw-r--r--drivers/net/arm/Kconfig13
-rw-r--r--drivers/net/arm/Makefile1
-rw-r--r--drivers/net/arm/ether00.c1017
-rw-r--r--drivers/serial/Kconfig23
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/uart00.c782
-rw-r--r--include/asm-arm/arch-epxa10db/debug-macro.S41
-rw-r--r--include/asm-arm/arch-epxa10db/dma.h19
-rw-r--r--include/asm-arm/arch-epxa10db/entry-macro.S25
-rw-r--r--include/asm-arm/arch-epxa10db/ether00.h482
-rw-r--r--include/asm-arm/arch-epxa10db/excalibur.h91
-rw-r--r--include/asm-arm/arch-epxa10db/hardware.h64
-rw-r--r--include/asm-arm/arch-epxa10db/int_ctrl00.h288
-rw-r--r--include/asm-arm/arch-epxa10db/io.h41
-rw-r--r--include/asm-arm/arch-epxa10db/irqs.h45
-rw-r--r--include/asm-arm/arch-epxa10db/memory.h38
-rw-r--r--include/asm-arm/arch-epxa10db/mode_ctrl00.h80
-rw-r--r--include/asm-arm/arch-epxa10db/param.h19
-rw-r--r--include/asm-arm/arch-epxa10db/platform.h7
-rw-r--r--include/asm-arm/arch-epxa10db/pld_conf00.h73
-rw-r--r--include/asm-arm/arch-epxa10db/system.h41
-rw-r--r--include/asm-arm/arch-epxa10db/tdkphy.h209
-rw-r--r--include/asm-arm/arch-epxa10db/timer00.h98
-rw-r--r--include/asm-arm/arch-epxa10db/timex.h26
-rw-r--r--include/asm-arm/arch-epxa10db/uart00.h181
-rw-r--r--include/asm-arm/arch-epxa10db/uncompress.h54
-rw-r--r--include/asm-arm/arch-epxa10db/vmalloc.h20
43 files changed, 2 insertions, 4973 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 16a5d522b2f2..70f388d168db 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -103,13 +103,6 @@ config ARCH_EBSA110
103 Ethernet interface, two PCMCIA sockets, two serial ports and a 103 Ethernet interface, two PCMCIA sockets, two serial ports and a
104 parallel port. 104 parallel port.
105 105
106config ARCH_CAMELOT
107 bool "Epxa10db"
108 help
109 This enables support for Altera's Excalibur XA10 development board.
110 If you would like to build your kernel to run on one of these boards
111 then you must say 'Y' here. Otherwise say 'N'
112
113config ARCH_FOOTBRIDGE 106config ARCH_FOOTBRIDGE
114 bool "FootBridge" 107 bool "FootBridge"
115 select FOOTBRIDGE 108 select FOOTBRIDGE
@@ -221,8 +214,6 @@ endchoice
221 214
222source "arch/arm/mach-clps711x/Kconfig" 215source "arch/arm/mach-clps711x/Kconfig"
223 216
224source "arch/arm/mach-epxa10db/Kconfig"
225
226source "arch/arm/mach-footbridge/Kconfig" 217source "arch/arm/mach-footbridge/Kconfig"
227 218
228source "arch/arm/mach-integrator/Kconfig" 219source "arch/arm/mach-integrator/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index afaf3a1e903c..1c056d631153 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -84,7 +84,6 @@ endif
84 machine-$(CONFIG_ARCH_PXA) := pxa 84 machine-$(CONFIG_ARCH_PXA) := pxa
85 machine-$(CONFIG_ARCH_L7200) := l7200 85 machine-$(CONFIG_ARCH_L7200) := l7200
86 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator 86 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
87 machine-$(CONFIG_ARCH_CAMELOT) := epxa10db
88 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 87 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
89 machine-$(CONFIG_ARCH_CLPS711X) := clps711x 88 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
90 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx 89 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 6b505ce41a75..0009a80498cc 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -21,10 +21,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
21OBJS += head-shark.o ofw-shark.o 21OBJS += head-shark.o ofw-shark.o
22endif 22endif
23 23
24ifeq ($(CONFIG_ARCH_CAMELOT),y)
25OBJS += head-epxa10db.o
26endif
27
28ifeq ($(CONFIG_ARCH_L7200),y) 24ifeq ($(CONFIG_ARCH_L7200),y)
29OBJS += head-l7200.o 25OBJS += head-l7200.o
30endif 26endif
diff --git a/arch/arm/boot/compressed/head-epxa10db.S b/arch/arm/boot/compressed/head-epxa10db.S
deleted file mode 100644
index 757681f12a39..000000000000
--- a/arch/arm/boot/compressed/head-epxa10db.S
+++ /dev/null
@@ -1,5 +0,0 @@
1#include <asm/mach-types.h>
2#include <asm/arch/excalibur.h>
3
4 .section ".start", "ax"
5 mov r7, #MACH_TYPE_CAMELOT
diff --git a/arch/arm/configs/epxa10db_defconfig b/arch/arm/configs/epxa10db_defconfig
deleted file mode 100644
index 9fb8b58c4954..000000000000
--- a/arch/arm/configs/epxa10db_defconfig
+++ /dev/null
@@ -1,644 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 22:46:51 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27# CONFIG_BSD_PROCESS_ACCT is not set
28CONFIG_SYSCTL=y
29# CONFIG_AUDIT is not set
30# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y
32# CONFIG_IKCONFIG is not set
33# CONFIG_EMBEDDED is not set
34CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_BASE_FULL=y
37CONFIG_FUTEX=y
38CONFIG_EPOLL=y
39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
40CONFIG_SHMEM=y
41CONFIG_CC_ALIGN_FUNCTIONS=0
42CONFIG_CC_ALIGN_LABELS=0
43CONFIG_CC_ALIGN_LOOPS=0
44CONFIG_CC_ALIGN_JUMPS=0
45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
47
48#
49# Loadable module support
50#
51CONFIG_MODULES=y
52CONFIG_MODULE_UNLOAD=y
53# CONFIG_MODULE_FORCE_UNLOAD is not set
54CONFIG_OBSOLETE_MODPARM=y
55# CONFIG_MODVERSIONS is not set
56# CONFIG_MODULE_SRCVERSION_ALL is not set
57# CONFIG_KMOD is not set
58
59#
60# System Type
61#
62# CONFIG_ARCH_CLPS7500 is not set
63# CONFIG_ARCH_CLPS711X is not set
64# CONFIG_ARCH_CO285 is not set
65# CONFIG_ARCH_EBSA110 is not set
66CONFIG_ARCH_CAMELOT=y
67# CONFIG_ARCH_FOOTBRIDGE is not set
68# CONFIG_ARCH_INTEGRATOR is not set
69# CONFIG_ARCH_IOP3XX is not set
70# CONFIG_ARCH_IXP4XX is not set
71# CONFIG_ARCH_IXP2000 is not set
72# CONFIG_ARCH_L7200 is not set
73# CONFIG_ARCH_PXA is not set
74# CONFIG_ARCH_RPC is not set
75# CONFIG_ARCH_SA1100 is not set
76# CONFIG_ARCH_S3C2410 is not set
77# CONFIG_ARCH_SHARK is not set
78# CONFIG_ARCH_LH7A40X is not set
79# CONFIG_ARCH_OMAP is not set
80# CONFIG_ARCH_VERSATILE is not set
81# CONFIG_ARCH_IMX is not set
82# CONFIG_ARCH_H720X is not set
83
84#
85# Epxa10db
86#
87
88#
89# PLD hotswap support
90#
91CONFIG_PLD=y
92# CONFIG_PLD_HOTSWAP is not set
93
94#
95# Processor Type
96#
97CONFIG_CPU_32=y
98CONFIG_CPU_ARM922T=y
99CONFIG_CPU_32v4=y
100CONFIG_CPU_ABRT_EV4T=y
101CONFIG_CPU_CACHE_V4WT=y
102CONFIG_CPU_CACHE_VIVT=y
103CONFIG_CPU_COPY_V4WB=y
104CONFIG_CPU_TLB_V4WBI=y
105
106#
107# Processor Features
108#
109# CONFIG_ARM_THUMB is not set
110# CONFIG_CPU_ICACHE_DISABLE is not set
111# CONFIG_CPU_DCACHE_DISABLE is not set
112# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
113
114#
115# Bus support
116#
117
118#
119# PCCARD (PCMCIA/CardBus) support
120#
121# CONFIG_PCCARD is not set
122
123#
124# Kernel Features
125#
126# CONFIG_PREEMPT is not set
127CONFIG_ALIGNMENT_TRAP=y
128
129#
130# Boot options
131#
132CONFIG_ZBOOT_ROM_TEXT=0x0
133CONFIG_ZBOOT_ROM_BSS=0x0
134CONFIG_CMDLINE="mem=32M console=ttyUA0,115200 initrd=0x00200000,8M root=/dev/ram0 rw"
135# CONFIG_XIP_KERNEL is not set
136
137#
138# Floating point emulation
139#
140
141#
142# At least one emulation must be selected
143#
144CONFIG_FPE_NWFPE=y
145# CONFIG_FPE_NWFPE_XP is not set
146# CONFIG_FPE_FASTFPE is not set
147
148#
149# Userspace binary formats
150#
151CONFIG_BINFMT_ELF=y
152# CONFIG_BINFMT_AOUT is not set
153# CONFIG_BINFMT_MISC is not set
154# CONFIG_ARTHUR is not set
155
156#
157# Power management options
158#
159# CONFIG_PM is not set
160
161#
162# Device Drivers
163#
164
165#
166# Generic Driver Options
167#
168CONFIG_STANDALONE=y
169CONFIG_PREVENT_FIRMWARE_BUILD=y
170# CONFIG_FW_LOADER is not set
171
172#
173# Memory Technology Devices (MTD)
174#
175# CONFIG_MTD is not set
176
177#
178# Parallel port support
179#
180# CONFIG_PARPORT is not set
181
182#
183# Plug and Play support
184#
185
186#
187# Block devices
188#
189# CONFIG_BLK_DEV_FD is not set
190# CONFIG_BLK_DEV_COW_COMMON is not set
191CONFIG_BLK_DEV_LOOP=y
192# CONFIG_BLK_DEV_CRYPTOLOOP is not set
193# CONFIG_BLK_DEV_NBD is not set
194CONFIG_BLK_DEV_RAM=y
195CONFIG_BLK_DEV_RAM_COUNT=16
196CONFIG_BLK_DEV_RAM_SIZE=8192
197CONFIG_BLK_DEV_INITRD=y
198CONFIG_INITRAMFS_SOURCE=""
199# CONFIG_CDROM_PKTCDVD is not set
200
201#
202# IO Schedulers
203#
204CONFIG_IOSCHED_NOOP=y
205CONFIG_IOSCHED_AS=y
206CONFIG_IOSCHED_DEADLINE=y
207CONFIG_IOSCHED_CFQ=y
208# CONFIG_ATA_OVER_ETH is not set
209
210#
211# SCSI device support
212#
213# CONFIG_SCSI is not set
214
215#
216# Multi-device support (RAID and LVM)
217#
218# CONFIG_MD is not set
219
220#
221# Fusion MPT device support
222#
223
224#
225# IEEE 1394 (FireWire) support
226#
227
228#
229# I2O device support
230#
231
232#
233# Networking support
234#
235CONFIG_NET=y
236
237#
238# Networking options
239#
240CONFIG_PACKET=y
241# CONFIG_PACKET_MMAP is not set
242# CONFIG_NETLINK_DEV is not set
243CONFIG_UNIX=y
244# CONFIG_NET_KEY is not set
245CONFIG_INET=y
246CONFIG_IP_MULTICAST=y
247# CONFIG_IP_ADVANCED_ROUTER is not set
248CONFIG_IP_PNP=y
249# CONFIG_IP_PNP_DHCP is not set
250# CONFIG_IP_PNP_BOOTP is not set
251# CONFIG_IP_PNP_RARP is not set
252# CONFIG_NET_IPIP is not set
253# CONFIG_NET_IPGRE is not set
254# CONFIG_IP_MROUTE is not set
255# CONFIG_ARPD is not set
256# CONFIG_SYN_COOKIES is not set
257# CONFIG_INET_AH is not set
258# CONFIG_INET_ESP is not set
259# CONFIG_INET_IPCOMP is not set
260# CONFIG_INET_TUNNEL is not set
261# CONFIG_IP_TCPDIAG is not set
262# CONFIG_IP_TCPDIAG_IPV6 is not set
263# CONFIG_IPV6 is not set
264# CONFIG_NETFILTER is not set
265
266#
267# SCTP Configuration (EXPERIMENTAL)
268#
269# CONFIG_IP_SCTP is not set
270# CONFIG_ATM is not set
271# CONFIG_BRIDGE is not set
272# CONFIG_VLAN_8021Q is not set
273# CONFIG_DECNET is not set
274# CONFIG_LLC2 is not set
275# CONFIG_IPX is not set
276# CONFIG_ATALK is not set
277# CONFIG_X25 is not set
278# CONFIG_LAPB is not set
279# CONFIG_NET_DIVERT is not set
280# CONFIG_ECONET is not set
281# CONFIG_WAN_ROUTER is not set
282
283#
284# QoS and/or fair queueing
285#
286# CONFIG_NET_SCHED is not set
287# CONFIG_NET_CLS_ROUTE is not set
288
289#
290# Network testing
291#
292# CONFIG_NET_PKTGEN is not set
293# CONFIG_NETPOLL is not set
294# CONFIG_NET_POLL_CONTROLLER is not set
295# CONFIG_HAMRADIO is not set
296# CONFIG_IRDA is not set
297# CONFIG_BT is not set
298CONFIG_NETDEVICES=y
299# CONFIG_DUMMY is not set
300# CONFIG_BONDING is not set
301# CONFIG_EQUALIZER is not set
302# CONFIG_TUN is not set
303
304#
305# Ethernet (10 or 100Mbit)
306#
307# CONFIG_NET_ETHERNET is not set
308
309#
310# Ethernet (1000 Mbit)
311#
312
313#
314# Ethernet (10000 Mbit)
315#
316
317#
318# Token Ring devices
319#
320
321#
322# Wireless LAN (non-hamradio)
323#
324# CONFIG_NET_RADIO is not set
325
326#
327# Wan interfaces
328#
329# CONFIG_WAN is not set
330CONFIG_PPP=y
331CONFIG_PPP_MULTILINK=y
332# CONFIG_PPP_FILTER is not set
333CONFIG_PPP_ASYNC=y
334CONFIG_PPP_SYNC_TTY=y
335CONFIG_PPP_DEFLATE=y
336# CONFIG_PPP_BSDCOMP is not set
337# CONFIG_PPPOE is not set
338# CONFIG_SLIP is not set
339# CONFIG_SHAPER is not set
340# CONFIG_NETCONSOLE is not set
341
342#
343# ISDN subsystem
344#
345# CONFIG_ISDN is not set
346
347#
348# Input device support
349#
350CONFIG_INPUT=y
351
352#
353# Userland interfaces
354#
355CONFIG_INPUT_MOUSEDEV=y
356CONFIG_INPUT_MOUSEDEV_PSAUX=y
357CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
358CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
359# CONFIG_INPUT_JOYDEV is not set
360# CONFIG_INPUT_TSDEV is not set
361# CONFIG_INPUT_EVDEV is not set
362# CONFIG_INPUT_EVBUG is not set
363
364#
365# Input Device Drivers
366#
367# CONFIG_INPUT_KEYBOARD is not set
368# CONFIG_INPUT_MOUSE is not set
369# CONFIG_INPUT_JOYSTICK is not set
370# CONFIG_INPUT_TOUCHSCREEN is not set
371# CONFIG_INPUT_MISC is not set
372
373#
374# Hardware I/O ports
375#
376CONFIG_SERIO=y
377CONFIG_SERIO_SERPORT=y
378# CONFIG_SERIO_RAW is not set
379# CONFIG_GAMEPORT is not set
380CONFIG_SOUND_GAMEPORT=y
381
382#
383# Character devices
384#
385CONFIG_VT=y
386CONFIG_VT_CONSOLE=y
387CONFIG_HW_CONSOLE=y
388# CONFIG_SERIAL_NONSTANDARD is not set
389
390#
391# Serial drivers
392#
393# CONFIG_SERIAL_8250 is not set
394
395#
396# Non-8250 serial port support
397#
398CONFIG_SERIAL_UART00=y
399CONFIG_SERIAL_UART00_CONSOLE=y
400CONFIG_SERIAL_CORE=y
401CONFIG_SERIAL_CORE_CONSOLE=y
402CONFIG_UNIX98_PTYS=y
403CONFIG_LEGACY_PTYS=y
404CONFIG_LEGACY_PTY_COUNT=256
405
406#
407# IPMI
408#
409# CONFIG_IPMI_HANDLER is not set
410
411#
412# Watchdog Cards
413#
414# CONFIG_WATCHDOG is not set
415# CONFIG_NVRAM is not set
416# CONFIG_RTC is not set
417# CONFIG_DTLK is not set
418# CONFIG_R3964 is not set
419
420#
421# Ftape, the floppy tape device driver
422#
423# CONFIG_DRM is not set
424# CONFIG_RAW_DRIVER is not set
425
426#
427# TPM devices
428#
429# CONFIG_TCG_TPM is not set
430
431#
432# I2C support
433#
434# CONFIG_I2C is not set
435
436#
437# Misc devices
438#
439
440#
441# Multimedia devices
442#
443# CONFIG_VIDEO_DEV is not set
444
445#
446# Digital Video Broadcasting Devices
447#
448# CONFIG_DVB is not set
449
450#
451# Graphics support
452#
453# CONFIG_FB is not set
454
455#
456# Console display driver support
457#
458# CONFIG_VGA_CONSOLE is not set
459CONFIG_DUMMY_CONSOLE=y
460
461#
462# Sound
463#
464# CONFIG_SOUND is not set
465
466#
467# USB support
468#
469CONFIG_USB_ARCH_HAS_HCD=y
470# CONFIG_USB_ARCH_HAS_OHCI is not set
471# CONFIG_USB is not set
472
473#
474# USB Gadget Support
475#
476# CONFIG_USB_GADGET is not set
477
478#
479# MMC/SD Card support
480#
481# CONFIG_MMC is not set
482
483#
484# File systems
485#
486CONFIG_EXT2_FS=y
487# CONFIG_EXT2_FS_XATTR is not set
488# CONFIG_EXT3_FS is not set
489# CONFIG_JBD is not set
490# CONFIG_REISERFS_FS is not set
491# CONFIG_JFS_FS is not set
492
493#
494# XFS support
495#
496# CONFIG_XFS_FS is not set
497# CONFIG_MINIX_FS is not set
498# CONFIG_ROMFS_FS is not set
499# CONFIG_QUOTA is not set
500CONFIG_DNOTIFY=y
501CONFIG_AUTOFS_FS=y
502CONFIG_AUTOFS4_FS=y
503
504#
505# CD-ROM/DVD Filesystems
506#
507# CONFIG_ISO9660_FS is not set
508# CONFIG_UDF_FS is not set
509
510#
511# DOS/FAT/NT Filesystems
512#
513# CONFIG_MSDOS_FS is not set
514# CONFIG_VFAT_FS is not set
515# CONFIG_NTFS_FS is not set
516
517#
518# Pseudo filesystems
519#
520CONFIG_PROC_FS=y
521CONFIG_SYSFS=y
522# CONFIG_DEVFS_FS is not set
523# CONFIG_DEVPTS_FS_XATTR is not set
524# CONFIG_TMPFS is not set
525# CONFIG_HUGETLB_PAGE is not set
526CONFIG_RAMFS=y
527
528#
529# Miscellaneous filesystems
530#
531# CONFIG_ADFS_FS is not set
532# CONFIG_AFFS_FS is not set
533# CONFIG_HFS_FS is not set
534# CONFIG_HFSPLUS_FS is not set
535# CONFIG_BEFS_FS is not set
536# CONFIG_BFS_FS is not set
537# CONFIG_EFS_FS is not set
538# CONFIG_CRAMFS is not set
539# CONFIG_VXFS_FS is not set
540# CONFIG_HPFS_FS is not set
541# CONFIG_QNX4FS_FS is not set
542# CONFIG_SYSV_FS is not set
543# CONFIG_UFS_FS is not set
544
545#
546# Network File Systems
547#
548# CONFIG_NFS_FS is not set
549# CONFIG_NFSD is not set
550CONFIG_SMB_FS=y
551# CONFIG_SMB_NLS_DEFAULT is not set
552# CONFIG_CIFS is not set
553# CONFIG_NCP_FS is not set
554# CONFIG_CODA_FS is not set
555# CONFIG_AFS_FS is not set
556
557#
558# Partition Types
559#
560# CONFIG_PARTITION_ADVANCED is not set
561CONFIG_MSDOS_PARTITION=y
562
563#
564# Native Language Support
565#
566CONFIG_NLS=y
567CONFIG_NLS_DEFAULT="iso8859-1"
568# CONFIG_NLS_CODEPAGE_437 is not set
569# CONFIG_NLS_CODEPAGE_737 is not set
570# CONFIG_NLS_CODEPAGE_775 is not set
571# CONFIG_NLS_CODEPAGE_850 is not set
572# CONFIG_NLS_CODEPAGE_852 is not set
573# CONFIG_NLS_CODEPAGE_855 is not set
574# CONFIG_NLS_CODEPAGE_857 is not set
575# CONFIG_NLS_CODEPAGE_860 is not set
576# CONFIG_NLS_CODEPAGE_861 is not set
577# CONFIG_NLS_CODEPAGE_862 is not set
578# CONFIG_NLS_CODEPAGE_863 is not set
579# CONFIG_NLS_CODEPAGE_864 is not set
580# CONFIG_NLS_CODEPAGE_865 is not set
581# CONFIG_NLS_CODEPAGE_866 is not set
582# CONFIG_NLS_CODEPAGE_869 is not set
583# CONFIG_NLS_CODEPAGE_936 is not set
584# CONFIG_NLS_CODEPAGE_950 is not set
585# CONFIG_NLS_CODEPAGE_932 is not set
586# CONFIG_NLS_CODEPAGE_949 is not set
587# CONFIG_NLS_CODEPAGE_874 is not set
588# CONFIG_NLS_ISO8859_8 is not set
589# CONFIG_NLS_CODEPAGE_1250 is not set
590# CONFIG_NLS_CODEPAGE_1251 is not set
591# CONFIG_NLS_ASCII is not set
592# CONFIG_NLS_ISO8859_1 is not set
593# CONFIG_NLS_ISO8859_2 is not set
594# CONFIG_NLS_ISO8859_3 is not set
595# CONFIG_NLS_ISO8859_4 is not set
596# CONFIG_NLS_ISO8859_5 is not set
597# CONFIG_NLS_ISO8859_6 is not set
598# CONFIG_NLS_ISO8859_7 is not set
599# CONFIG_NLS_ISO8859_9 is not set
600# CONFIG_NLS_ISO8859_13 is not set
601# CONFIG_NLS_ISO8859_14 is not set
602# CONFIG_NLS_ISO8859_15 is not set
603# CONFIG_NLS_KOI8_R is not set
604# CONFIG_NLS_KOI8_U is not set
605# CONFIG_NLS_UTF8 is not set
606
607#
608# Profiling support
609#
610# CONFIG_PROFILING is not set
611
612#
613# Kernel hacking
614#
615# CONFIG_PRINTK_TIME is not set
616# CONFIG_DEBUG_KERNEL is not set
617CONFIG_LOG_BUF_SHIFT=14
618CONFIG_DEBUG_BUGVERBOSE=y
619CONFIG_FRAME_POINTER=y
620# CONFIG_DEBUG_USER is not set
621
622#
623# Security options
624#
625# CONFIG_KEYS is not set
626# CONFIG_SECURITY is not set
627
628#
629# Cryptographic options
630#
631# CONFIG_CRYPTO is not set
632
633#
634# Hardware crypto devices
635#
636
637#
638# Library routines
639#
640CONFIG_CRC_CCITT=y
641CONFIG_CRC32=y
642# CONFIG_LIBCRC32C is not set
643CONFIG_ZLIB_INFLATE=y
644CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/mach-epxa10db/Kconfig b/arch/arm/mach-epxa10db/Kconfig
deleted file mode 100644
index 55d896dd4950..000000000000
--- a/arch/arm/mach-epxa10db/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
1if ARCH_CAMELOT
2
3menu "Epxa10db"
4
5comment "PLD hotswap support"
6
7config PLD
8 bool
9 default y
10
11config PLD_HOTSWAP
12 bool "Support for PLD device hotplugging (experimental)"
13 depends on EXPERIMENTAL
14 help
15 This enables support for the dynamic loading and configuration of
16 compatible drivers when the contents of the PLD are changed. This
17 is still experimental and requires configuration tools which are
18 not yet generally available. Say N here. You must enable the kernel
19 module loader for this feature to work.
20
21endmenu
22
23endif
diff --git a/arch/arm/mach-epxa10db/Makefile b/arch/arm/mach-epxa10db/Makefile
deleted file mode 100644
index 24fbd7d3a3c1..000000000000
--- a/arch/arm/mach-epxa10db/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := arch.o irq.o mm.o time.o
8obj-m :=
9obj-n :=
10obj- :=
11
diff --git a/arch/arm/mach-epxa10db/Makefile.boot b/arch/arm/mach-epxa10db/Makefile.boot
deleted file mode 100644
index 28bec7d3fc88..000000000000
--- a/arch/arm/mach-epxa10db/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x00008000
2
diff --git a/arch/arm/mach-epxa10db/arch.c b/arch/arm/mach-epxa10db/arch.c
deleted file mode 100644
index 44c56571d183..000000000000
--- a/arch/arm/mach-epxa10db/arch.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * linux/arch/arm/mach-epxa10db/arch.c
3 *
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 * Copyright (C) 2001 Altera Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/serial_8250.h>
24
25#include <asm/hardware.h>
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28
29#include <asm/mach/arch.h>
30
31static struct plat_serial8250_port serial_platform_data[] = {
32 {
33 .iobase = 0x3f8,
34 .irq = IRQ_UARTINT0,
35#error FIXME
36 .uartclk = 0,
37 .regshift = 0,
38 .iotype = UPIO_PORT,
39 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
40 },
41 {
42 .iobase = 0x2f8,
43 .irq = IRQ_UARTINT1,
44#error FIXME
45 .uartclk = 0,
46 .regshift = 0,
47 .iotype = UPIO_PORT,
48 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
49 },
50 { },
51};
52
53static struct platform_device serial_device = {
54 .name = "serial8250",
55 .id = PLAT8250_DEV_PLATFORM,
56 .dev = {
57 .platform_data = serial_platform_data,
58 },
59};
60
61extern void epxa10db_map_io(void);
62extern void epxa10db_init_irq(void);
63extern struct sys_timer epxa10db_timer;
64
65MACHINE_START(CAMELOT, "Altera Epxa10db")
66 /* Maintainer: Altera Corporation */
67 .phys_ram = 0x00000000,
68 .phys_io = 0x7fffc000,
69 .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
70 .map_io = epxa10db_map_io,
71 .init_irq = epxa10db_init_irq,
72 .timer = &epxa10db_timer,
73MACHINE_END
74
diff --git a/arch/arm/mach-epxa10db/irq.c b/arch/arm/mach-epxa10db/irq.c
deleted file mode 100644
index 9bf927e13309..000000000000
--- a/arch/arm/mach-epxa10db/irq.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * linux/arch/arm/mach-epxa10db/irq.c
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/stddef.h>
23#include <linux/timer.h>
24#include <linux/list.h>
25#include <asm/io.h>
26#include <asm/hardware.h>
27#include <asm/irq.h>
28#include <asm/mach/irq.h>
29#include <asm/arch/platform.h>
30#include <asm/arch/int_ctrl00.h>
31
32
33static void epxa_mask_irq(unsigned int irq)
34{
35 writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
36}
37
38static void epxa_unmask_irq(unsigned int irq)
39{
40 writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
41}
42
43
44static struct irqchip epxa_irq_chip = {
45 .ack = epxa_mask_irq,
46 .mask = epxa_mask_irq,
47 .unmask = epxa_unmask_irq,
48};
49
50static struct resource irq_resource = {
51 .name = "irq_handler",
52 .start = IO_ADDRESS(EXC_INT_CTRL00_BASE),
53 .end = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
54};
55
56void __init epxa10db_init_irq(void)
57{
58 unsigned int i;
59
60 request_resource(&iomem_resource, &irq_resource);
61
62 /*
63 * This bit sets up the interrupt controller using
64 * the 6 PLD interrupts mode (the default) each
65 * irqs is assigned a priority which is the same
66 * as its interrupt number. This scheme is used because
67 * its easy, but you may want to change it depending
68 * on the contents of your PLD
69 */
70
71 writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
72 for (i = 0; i < NR_IRQS; i++){
73 writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
74 set_irq_chip(i,&epxa_irq_chip);
75 set_irq_handler(i,do_level_IRQ);
76 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
77 }
78
79 /* Disable all interrupts */
80 writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
81
82}
diff --git a/arch/arm/mach-epxa10db/mm.c b/arch/arm/mach-epxa10db/mm.c
deleted file mode 100644
index cfd0d2182d44..000000000000
--- a/arch/arm/mach-epxa10db/mm.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * linux/arch/arm/mach-epxa10db/mm.c
3 *
4 * MM routines for Altera'a Epxa10db board
5 *
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/sizes.h>
28#include <asm/page.h>
29
30#include <asm/mach/map.h>
31
32/* Page table mapping for I/O region */
33
34static struct map_desc epxa10db_io_desc[] __initdata = {
35 {
36 .virtual = IO_ADDRESS(EXC_REGISTERS_BASE),
37 .pfn = __phys_to_pfn(EXC_REGISTERS_BASE),
38 .length = SZ_16K,
39 .type = MT_DEVICE
40 }, {
41 .virtual = IO_ADDRESS(EXC_PLD_BLOCK0_BASE),
42 .pfn = __phys_to_pfn(EXC_PLD_BLOCK0_BASE),
43 .length = SZ_16K,
44 .type = MT_DEVICE
45 }, {
46 .virtual = IO_ADDRESS(EXC_PLD_BLOCK1_BASE),
47 .pfn =__phys_to_pfn(EXC_PLD_BLOCK1_BASE),
48 .length = SZ_16K,
49 .type = MT_DEVICE
50 }, {
51 .virtual = IO_ADDRESS(EXC_PLD_BLOCK2_BASE),
52 .physical = __phys_to_pfn(EXC_PLD_BLOCK2_BASE),
53 .length = SZ_16K,
54 .type = MT_DEVICE
55 }, {
56 .virtual = IO_ADDRESS(EXC_PLD_BLOCK3_BASE),
57 .pfn = __phys_to_pfn(EXC_PLD_BLOCK3_BASE),
58 .length = SZ_16K,
59 .type = MT_DEVICE
60 }, {
61 .virtual = FLASH_VADDR(EXC_EBI_BLOCK0_BASE),
62 .pfn = __phys_to_pfn(EXC_EBI_BLOCK0_BASE),
63 .length = SZ_16M,
64 .type = MT_DEVICE
65 }
66};
67
68void __init epxa10db_map_io(void)
69{
70 iotable_init(epxa10db_io_desc, ARRAY_SIZE(epxa10db_io_desc));
71}
diff --git a/arch/arm/mach-epxa10db/time.c b/arch/arm/mach-epxa10db/time.c
deleted file mode 100644
index 4b1084dde8dd..000000000000
--- a/arch/arm/mach-epxa10db/time.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * linux/arch/arm/mach-epxa10db/time.c
3 *
4 * Copyright (C) 2000 Deep Blue Solutions
5 * Copyright (C) 2001 Altera Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/sched.h>
15
16#include <asm/hardware.h>
17#include <asm/system.h>
18#include <asm/leds.h>
19
20#include <asm/mach/time.h>
21
22#define TIMER00_TYPE (volatile unsigned int*)
23#include <asm/arch/timer00.h>
24
25static int epxa10db_set_rtc(void)
26{
27 return 1;
28}
29
30static int epxa10db_rtc_init(void)
31{
32 set_rtc = epxa10db_set_rtc;
33
34 return 0;
35}
36
37__initcall(epxa10db_rtc_init);
38
39
40/*
41 * IRQ handler for the timer
42 */
43static irqreturn_t
44epxa10db_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
45{
46 write_seqlock(&xtime_lock);
47
48 // ...clear the interrupt
49 *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK;
50
51 timer_tick(regs);
52 write_sequnlock(&xtime_lock);
53
54 return IRQ_HANDLED;
55}
56
57static struct irqaction epxa10db_timer_irq = {
58 .name = "Excalibur Timer Tick",
59 .flags = SA_INTERRUPT | SA_TIMER,
60 .handler = epxa10db_timer_interrupt,
61};
62
63/*
64 * Set up timer interrupt, and return the current time in seconds.
65 */
66static void __init epxa10db_timer_init(void)
67{
68 /* Start the timer */
69 *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200);
70 *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1;
71 *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK;
72
73 setup_irq(IRQ_TIMER0, &epxa10db_timer_irq);
74}
75
76struct sys_timer epxa10db_timer = {
77 .init = epxa10db_timer_init,
78};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e84fdde6edf8..04cf0557e54b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -83,8 +83,8 @@ config CPU_ARM920T
83# ARM922T 83# ARM922T
84config CPU_ARM922T 84config CPU_ARM922T
85 bool "Support ARM922T processor" if ARCH_INTEGRATOR 85 bool "Support ARM922T processor" if ARCH_INTEGRATOR
86 depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR 86 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
87 default y if ARCH_CAMELOT || ARCH_LH7A40X 87 default y if ARCH_LH7A40X
88 select CPU_32v4 88 select CPU_32v4
89 select CPU_ABRT_EV4T 89 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT 90 select CPU_CACHE_V4WT
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index b9b77cf39a18..7abd7fee0dda 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -473,14 +473,6 @@ config MTD_IXP2000
473 IXDP425 and Coyote. If you have an IXP2000 based board and 473 IXDP425 and Coyote. If you have an IXP2000 based board and
474 would like to use the flash chips on it, say 'Y'. 474 would like to use the flash chips on it, say 'Y'.
475 475
476config MTD_EPXA10DB
477 tristate "CFI Flash device mapped on Epxa10db"
478 depends on MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT
479 help
480 This enables support for the flash devices on the Altera
481 Excalibur XA10 Development Board. If you are building a kernel
482 for on of these boards then you should say 'Y' otherwise say 'N'.
483
484config MTD_FORTUNET 476config MTD_FORTUNET
485 tristate "CFI Flash device mapped on the FortuNet board" 477 tristate "CFI Flash device mapped on the FortuNet board"
486 depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET 478 depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 2f7e254912f0..ab71f172eb77 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
15obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o 15obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
16obj-$(CONFIG_MTD_DC21285) += dc21285.o 16obj-$(CONFIG_MTD_DC21285) += dc21285.o
17obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o 17obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
18obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o
19obj-$(CONFIG_MTD_IQ80310) += iq80310.o 18obj-$(CONFIG_MTD_IQ80310) += iq80310.o
20obj-$(CONFIG_MTD_L440GX) += l440gx.o 19obj-$(CONFIG_MTD_L440GX) += l440gx.o
21obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o 20obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o
diff --git a/drivers/mtd/maps/epxa10db-flash.c b/drivers/mtd/maps/epxa10db-flash.c
deleted file mode 100644
index 265b079fe934..000000000000
--- a/drivers/mtd/maps/epxa10db-flash.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Flash memory access on EPXA based devices
3 *
4 * (C) 2000 Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 Altera Corporation
6 * Copyright (C) 2001 Red Hat, Inc.
7 *
8 * $Id: epxa10db-flash.c,v 1.15 2005/11/07 11:14:27 gleixner Exp $
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31
32#include <linux/mtd/mtd.h>
33#include <linux/mtd/map.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37#include <asm/hardware.h>
38
39#ifdef CONFIG_EPXA10DB
40#define BOARD_NAME "EPXA10DB"
41#else
42#define BOARD_NAME "EPXA1DB"
43#endif
44
45static int nr_parts = 0;
46static struct mtd_partition *parts;
47
48static struct mtd_info *mymtd;
49
50static int epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts);
51
52
53static struct map_info epxa_map = {
54 .name = "EPXA flash",
55 .size = FLASH_SIZE,
56 .bankwidth = 2,
57 .phys = FLASH_START,
58};
59
60static const char *probes[] = { "RedBoot", "afs", NULL };
61
62static int __init epxa_mtd_init(void)
63{
64 int i;
65
66 printk(KERN_NOTICE "%s flash device: 0x%x at 0x%x\n", BOARD_NAME, FLASH_SIZE, FLASH_START);
67
68 epxa_map.virt = ioremap(FLASH_START, FLASH_SIZE);
69 if (!epxa_map.virt) {
70 printk("Failed to ioremap %s flash\n",BOARD_NAME);
71 return -EIO;
72 }
73 simple_map_init(&epxa_map);
74
75 mymtd = do_map_probe("cfi_probe", &epxa_map);
76 if (!mymtd) {
77 iounmap((void *)epxa_map.virt);
78 return -ENXIO;
79 }
80
81 mymtd->owner = THIS_MODULE;
82
83 /* Unlock the flash device. */
84 if(mymtd->unlock){
85 for (i=0; i<mymtd->numeraseregions;i++){
86 int j;
87 for(j=0;j<mymtd->eraseregions[i].numblocks;j++){
88 mymtd->unlock(mymtd,mymtd->eraseregions[i].offset + j * mymtd->eraseregions[i].erasesize,mymtd->eraseregions[i].erasesize);
89 }
90 }
91 }
92
93#ifdef CONFIG_MTD_PARTITIONS
94 nr_parts = parse_mtd_partitions(mymtd, probes, &parts, 0);
95
96 if (nr_parts > 0) {
97 add_mtd_partitions(mymtd, parts, nr_parts);
98 return 0;
99 }
100#endif
101 /* No recognised partitioning schemes found - use defaults */
102 nr_parts = epxa_default_partitions(mymtd, &parts);
103 if (nr_parts > 0) {
104 add_mtd_partitions(mymtd, parts, nr_parts);
105 return 0;
106 }
107
108 /* If all else fails... */
109 add_mtd_device(mymtd);
110 return 0;
111}
112
113static void __exit epxa_mtd_cleanup(void)
114{
115 if (mymtd) {
116 if (nr_parts)
117 del_mtd_partitions(mymtd);
118 else
119 del_mtd_device(mymtd);
120 map_destroy(mymtd);
121 }
122 if (epxa_map.virt) {
123 iounmap((void *)epxa_map.virt);
124 epxa_map.virt = 0;
125 }
126}
127
128
129/*
130 * This will do for now, once we decide which bootldr we're finally
131 * going to use then we'll remove this function and do it properly
132 *
133 * Partions are currently (as offsets from base of flash):
134 * 0x00000000 - 0x003FFFFF - bootloader (!)
135 * 0x00400000 - 0x00FFFFFF - Flashdisk
136 */
137
138static int __init epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts)
139{
140 struct mtd_partition *parts;
141 int ret, i;
142 int npartitions = 0;
143 char *names;
144 const char *name = "jffs";
145
146 printk("Using default partitions for %s\n",BOARD_NAME);
147 npartitions=1;
148 parts = kmalloc(npartitions*sizeof(*parts)+strlen(name), GFP_KERNEL);
149 memzero(parts,npartitions*sizeof(*parts)+strlen(name));
150 if (!parts) {
151 ret = -ENOMEM;
152 goto out;
153 }
154 i=0;
155 names = (char *)&parts[npartitions];
156 parts[i].name = names;
157 names += strlen(name) + 1;
158 strcpy(parts[i].name, name);
159
160#ifdef CONFIG_EPXA10DB
161 parts[i].size = FLASH_SIZE-0x00400000;
162 parts[i].offset = 0x00400000;
163#else
164 parts[i].size = FLASH_SIZE-0x00180000;
165 parts[i].offset = 0x00180000;
166#endif
167
168 out:
169 *pparts = parts;
170 return npartitions;
171}
172
173
174module_init(epxa_mtd_init);
175module_exit(epxa_mtd_cleanup);
176
177MODULE_AUTHOR("Clive Davies");
178MODULE_DESCRIPTION("Altera epxa mtd flash map");
179MODULE_LICENSE("GPL");
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
index 470364deded0..625184b65e38 100644
--- a/drivers/net/arm/Kconfig
+++ b/drivers/net/arm/Kconfig
@@ -31,16 +31,3 @@ config ARM_ETHERH
31 help 31 help
32 If you have an Acorn system with one of these network cards, you 32 If you have an Acorn system with one of these network cards, you
33 should say Y to this option if you wish to use it with Linux. 33 should say Y to this option if you wish to use it with Linux.
34
35config ARM_ETHER00
36 tristate "Altera Ether00 support"
37 depends on NET_ETHERNET && ARM && ARCH_CAMELOT
38 help
39 This is the driver for Altera's ether00 ethernet mac IP core. Say
40 Y here if you want to build support for this into the kernel. It
41 is also available as a module (say M here) that can be inserted/
42 removed from the kernel at the same time as the PLD is configured.
43 If this driver is running on an epxa10 development board then it
44 will generate a suitable hw address based on the board serial
45 number (MTD support is required for this). Otherwise you will
46 need to set a suitable hw address using ifconfig.
diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
index b0d706834d89..bc263edf06a7 100644
--- a/drivers/net/arm/Makefile
+++ b/drivers/net/arm/Makefile
@@ -4,7 +4,6 @@
4# 4#
5 5
6obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o 6obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
7obj-$(CONFIG_ARM_ETHER00) += ether00.o
8obj-$(CONFIG_ARM_ETHERH) += etherh.o 7obj-$(CONFIG_ARM_ETHERH) += etherh.o
9obj-$(CONFIG_ARM_ETHER3) += ether3.o 8obj-$(CONFIG_ARM_ETHER3) += ether3.o
10obj-$(CONFIG_ARM_ETHER1) += ether1.o 9obj-$(CONFIG_ARM_ETHER1) += ether1.o
diff --git a/drivers/net/arm/ether00.c b/drivers/net/arm/ether00.c
deleted file mode 100644
index 4f1f4e31bda5..000000000000
--- a/drivers/net/arm/ether00.c
+++ /dev/null
@@ -1,1017 +0,0 @@
1/*
2 * drivers/net/ether00.c
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* includes */
22#include <linux/config.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/netdevice.h>
26#include <linux/skbuff.h>
27#include <linux/etherdevice.h>
28#include <linux/module.h>
29#include <linux/tqueue.h>
30#include <linux/mtd/mtd.h>
31#include <linux/pld/pld_hotswap.h>
32#include <asm/arch/excalibur.h>
33#include <asm/arch/hardware.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/sizes.h>
37
38#include <asm/arch/ether00.h>
39#include <asm/arch/tdkphy.h>
40
41
42MODULE_AUTHOR("Clive Davies");
43MODULE_DESCRIPTION("Altera Ether00 IP core driver");
44MODULE_LICENSE("GPL");
45
46#define PKT_BUF_SZ 1540 /* Size of each rx buffer */
47#define ETH_NR 4 /* Number of MACs this driver supports */
48
49#define DEBUG(x)
50
51#define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1)))
52#define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data))
53
54#define ETHER00_BASE 0
55#define ETHER00_TYPE
56#define ETHER00_NAME "ether00"
57#define MAC_REG_SIZE 0x400 /* size of MAC register area */
58
59
60
61/* typedefs */
62
63/* The definition of the driver control structure */
64
65#define RX_NUM_BUFF 10
66#define RX_NUM_FDESC 10
67#define TX_NUM_FDESC 10
68
69struct tx_fda_ent{
70 FDA_DESC fd;
71 BUF_DESC bd;
72 BUF_DESC pad;
73};
74struct rx_fda_ent{
75 FDA_DESC fd;
76 BUF_DESC bd;
77 BUF_DESC pad;
78};
79struct rx_blist_ent{
80 FDA_DESC fd;
81 BUF_DESC bd;
82 BUF_DESC pad;
83};
84struct net_priv
85{
86 struct net_device_stats stats;
87 struct sk_buff* skb;
88 void* dma_data;
89 struct rx_blist_ent* rx_blist_vp;
90 struct rx_fda_ent* rx_fda_ptr;
91 struct tx_fda_ent* tx_fdalist_vp;
92 struct tq_struct tq_memupdate;
93 unsigned char memupdate_scheduled;
94 unsigned char rx_disabled;
95 unsigned char queue_stopped;
96 spinlock_t rx_lock;
97};
98
99static const char vendor_id[2]={0x07,0xed};
100
101#ifdef ETHER00_DEBUG
102
103/* Dump (most) registers for debugging puposes */
104
105static void dump_regs(struct net_device *dev){
106 struct net_priv* priv=dev->priv;
107 unsigned int* i;
108
109 printk("\n RX free descriptor area:\n");
110
111 for(i=(unsigned int*)priv->rx_fda_ptr;
112 i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){
113 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
114 i+=4;
115 }
116
117 printk("\n RX buffer list:\n");
118
119 for(i=(unsigned int*)priv->rx_blist_vp;
120 i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){
121 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
122 i+=4;
123 }
124
125 printk("\n TX frame descriptor list:\n");
126
127 for(i=(unsigned int*)priv->tx_fdalist_vp;
128 i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){
129 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
130 i+=4;
131 }
132
133 printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr)));
134 printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr)));
135 printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr)));
136 printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr)));
137 printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr)));
138 printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr)));
139 printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr)));
140 printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr)));
141 printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr)));
142 printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr)));
143 printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr)));
144 printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr)));
145 printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr)));
146 printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr)));
147 printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr)));
148 printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr)));
149}
150#endif /* ETHER00_DEBUG */
151
152
153static int ether00_write_phy(struct net_device *dev, short address, short value)
154{
155 volatile int count = 1024;
156 writew(value,ETHER_MD_DATA(dev->base_addr));
157 writew( ETHER_MD_CA_BUSY_MSK |
158 ETHER_MD_CA_WR_MSK |
159 (address & ETHER_MD_CA_ADDR_MSK),
160 ETHER_MD_CA(dev->base_addr));
161
162 /* Wait for the command to complete */
163 while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
164 count--;
165 }
166 if (!count){
167 printk("Write to phy failed, addr=%#x, data=%#x\n",address, value);
168 return -EIO;
169 }
170 return 0;
171}
172
173static int ether00_read_phy(struct net_device *dev, short address)
174{
175 volatile int count = 1024;
176 writew( ETHER_MD_CA_BUSY_MSK |
177 (address & ETHER_MD_CA_ADDR_MSK),
178 ETHER_MD_CA(dev->base_addr));
179
180 /* Wait for the command to complete */
181 while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
182 count--;
183 }
184 if (!count){
185 printk(KERN_WARNING "Read from phy timed out\n");
186 return -EIO;
187 }
188 return readw(ETHER_MD_DATA(dev->base_addr));
189}
190
191static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs)
192{
193 struct net_device* dev=dev_id;
194 int irq_status;
195
196 irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL);
197
198 if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){
199 /*
200 * Autonegotiation complete on epxa10db. The mac doesn't
201 * twig if we're in full duplex so we need to check the
202 * phy status register and configure the mac accordingly
203 */
204 if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){
205 int tmp;
206 tmp=readl(ETHER_MAC_CTL(dev->base_addr));
207 writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr));
208 }
209 }
210
211 if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){
212
213 if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){
214 /* Link is up */
215 netif_carrier_on(dev);
216 //printk("Carrier on\n");
217 }else{
218 netif_carrier_off(dev);
219 //printk("Carrier off\n");
220
221 }
222 }
223
224}
225
226static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){
227 /* Make the buffer consistent with the cache as the mac is going to write
228 * directly into it*/
229 blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
230 blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data);
231 consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
232 /* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */
233 skb_reserve(skb,2);
234 blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2;
235 blist_ent_ptr->fd.FDLength=1;
236 blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
237 blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK;
238}
239
240
241static int ether00_mem_init(struct net_device* dev)
242{
243 struct net_priv* priv=dev->priv;
244 struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr;
245 struct rx_blist_ent* blist_ent_ptr;
246 int i;
247
248 /*
249 * Grab a block of on chip SRAM to contain the control stuctures for
250 * the ethernet MAC. This uncached becuase it needs to be accesses by both
251 * bus masters (cpu + mac). However, it shouldn't matter too much in terms
252 * of speed as its on chip memory
253 */
254 priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE );
255 if (!priv->dma_data)
256 return -ENOMEM;
257
258 priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data;
259 /*
260 * Now share it out amongst the Frame descriptors and the buffer list
261 */
262 priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent));
263
264 /*
265 *Initalise the FDA list
266 */
267 /* set ownership to the controller */
268 memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent));
269
270 /*
271 *Initialise the buffer list
272 */
273 blist_ent_ptr=priv->rx_blist_vp;
274 i=0;
275 while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
276 struct sk_buff *skb;
277 blist_ent_ptr->fd.FDLength=1;
278 skb=dev_alloc_skb(PKT_BUF_SZ);
279 if(skb){
280 setup_blist_entry(skb,blist_ent_ptr);
281 blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1);
282 blist_ent_ptr->bd.BDStat=i++;
283 blist_ent_ptr++;
284 }
285 else
286 {
287 printk("Failed to initalise buffer list\n");
288 }
289
290 }
291 blist_ent_ptr--;
292 blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp);
293
294 priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF);
295
296 /* Initialise the buffers to be a circular list. The mac will then go poll
297 * the list until it finds a frame ready to transmit */
298 tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC;
299 for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){
300 tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1));
301 tx_fd_ptr->fd.FDCtl=1;
302 tx_fd_ptr->fd.FDStat=0;
303 tx_fd_ptr->fd.FDLength=1;
304
305 }
306 /* Change the last FDNext pointer to make a circular list */
307 tx_fd_ptr--;
308 tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp);
309
310 /* Point the device at the chain of Rx and Tx Buffers */
311 writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr));
312 writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr));
313 writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr));
314
315 writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr));
316
317 return 0;
318}
319
320
321void ether00_mem_update(void* dev_id)
322{
323 struct net_device* dev=dev_id;
324 struct net_priv* priv=dev->priv;
325 struct sk_buff* skb;
326 struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp;
327 struct rx_blist_ent* blist_ent_ptr;
328 unsigned long flags;
329
330 priv->tq_memupdate.sync=0;
331 //priv->tq_memupdate.list=
332 priv->memupdate_scheduled=0;
333
334 /* Transmit interrupt */
335 while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){
336 if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){
337 priv->stats.tx_packets++;
338 priv->stats.tx_bytes+=fda_ptr->bd.BuffLength;
339 skb=(struct sk_buff*)fda_ptr->fd.FDSystem;
340 //printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb);
341 dev_kfree_skb(skb);
342 fda_ptr->fd.FDSystem=0;
343 fda_ptr->fd.FDStat=0;
344 fda_ptr->fd.FDCtl=0;
345 }
346 fda_ptr++;
347 }
348 /* Fill in any missing buffers from the received queue */
349 spin_lock_irqsave(&priv->rx_lock,flags);
350 blist_ent_ptr=priv->rx_blist_vp;
351 while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
352 /* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */
353 if(!blist_ent_ptr->fd.FDSystem){
354 struct sk_buff *skb;
355 skb=dev_alloc_skb(PKT_BUF_SZ);
356 blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
357 if(skb){
358 setup_blist_entry(skb,blist_ent_ptr);
359 }
360 else
361 {
362 break;
363 }
364 }
365 blist_ent_ptr++;
366 }
367 spin_unlock_irqrestore(&priv->rx_lock,flags);
368 if(priv->queue_stopped){
369 //printk("%d:cln:start q\n",jiffies);
370 netif_start_queue(dev);
371 }
372 if(priv->rx_disabled){
373 //printk("%d:enable_irq\n",jiffies);
374 priv->rx_disabled=0;
375 writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
376
377 }
378}
379
380
381static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs)
382{
383 struct net_device* dev=dev_id;
384 struct net_priv* priv=dev->priv;
385
386 unsigned int interruptValue;
387
388 interruptValue=readl(ETHER_INT_SRC(dev->base_addr));
389
390 //printk("INT_SRC=%x\n",interruptValue);
391
392 if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK))
393 {
394 return; /* Interrupt wasn't caused by us!! */
395 }
396
397 if(readl(ETHER_INT_SRC(dev->base_addr))&
398 (ETHER_INT_SRC_INTMACRX_MSK |
399 ETHER_INT_SRC_FDAEX_MSK |
400 ETHER_INT_SRC_BLEX_MSK)) {
401 struct rx_blist_ent* blist_ent_ptr;
402 struct rx_fda_ent* fda_ent_ptr;
403 struct sk_buff* skb;
404
405 fda_ent_ptr=priv->rx_fda_ptr;
406 spin_lock(&priv->rx_lock);
407 while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){
408 int result;
409
410 if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK))
411 {
412 /* This frame is ready for processing */
413 /*find the corresponding buffer in the bufferlist */
414 blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat;
415 skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem;
416
417 /* Pass this skb up the stack */
418 skb->dev=dev;
419 skb_put(skb,fda_ent_ptr->fd.FDLength);
420 skb->protocol=eth_type_trans(skb,dev);
421 skb->ip_summed=CHECKSUM_UNNECESSARY;
422 result=netif_rx(skb);
423 /* Update statistics */
424 priv->stats.rx_packets++;
425 priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength;
426
427 /* Free the FDA entry */
428 fda_ent_ptr->bd.BDStat=0xff;
429 fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
430
431 /* Allocate a new skb and point the bd entry to it */
432 blist_ent_ptr->fd.FDSystem=0;
433 skb=dev_alloc_skb(PKT_BUF_SZ);
434 //printk("allocskb=%#x\n",skb);
435 if(skb){
436 setup_blist_entry(skb,blist_ent_ptr);
437
438 }
439 else if(!priv->memupdate_scheduled){
440 int tmp;
441 /* There are no buffers at the moment, so schedule */
442 /* the background task to sort this out */
443 schedule_task(&priv->tq_memupdate);
444 priv->memupdate_scheduled=1;
445 printk(KERN_DEBUG "%s:No buffers",dev->name);
446 /* If this interrupt was due to a lack of buffers then
447 * we'd better stop the receiver too */
448 if(interruptValue&ETHER_INT_SRC_BLEX_MSK){
449 priv->rx_disabled=1;
450 tmp=readl(ETHER_INT_SRC(dev->base_addr));
451 writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
452 printk(KERN_DEBUG "%s:Halting rx",dev->name);
453 }
454
455 }
456
457 }
458 fda_ent_ptr++;
459 }
460 spin_unlock(&priv->rx_lock);
461
462 /* Clear the interrupts */
463 writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK
464 | ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr));
465
466 }
467
468 if(readl(ETHER_INT_SRC(dev->base_addr))&ETHER_INT_SRC_INTMACTX_MSK){
469
470 if(!priv->memupdate_scheduled){
471 schedule_task(&priv->tq_memupdate);
472 priv->memupdate_scheduled=1;
473 }
474 /* Clear the interrupt */
475 writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr));
476 }
477
478 if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK|
479 ETHER_INT_SRC_INTEARNOT_MSK|
480 ETHER_INT_SRC_INTLINK_MSK|
481 ETHER_INT_SRC_INTEXBD_MSK|
482 ETHER_INT_SRC_INTTXCTLCMP_MSK))
483 {
484 /*
485 * Not using any of these so they shouldn't happen
486 *
487 * In the cased of INTEXBD - if you allocate more
488 * than 28 decsriptors you may need to think about this
489 */
490 printk("Not using this interrupt\n");
491 }
492
493 if (readl(ETHER_INT_SRC(dev->base_addr)) &
494 (ETHER_INT_SRC_INTSBUS_MSK |
495 ETHER_INT_SRC_INTNRABT_MSK
496 |ETHER_INT_SRC_DMPARERR_MSK))
497 {
498 /*
499 * Hardware errors, we can either ignore them and hope they go away
500 *or reset the device, I'll try the first for now to see if they happen
501 */
502 printk("Hardware error\n");
503 }
504}
505
506static void ether00_setup_ethernet_address(struct net_device* dev)
507{
508 int tmp;
509
510 dev->addr_len=6;
511 writew(0,ETHER_ARC_ADR(dev->base_addr));
512 writel((dev->dev_addr[0]<<24) |
513 (dev->dev_addr[1]<<16) |
514 (dev->dev_addr[2]<<8) |
515 dev->dev_addr[3],
516 ETHER_ARC_DATA(dev->base_addr));
517
518 writew(4,ETHER_ARC_ADR(dev->base_addr));
519 tmp=readl(ETHER_ARC_DATA(dev->base_addr));
520 tmp&=0xffff;
521 tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16);
522 writel(tmp, ETHER_ARC_DATA(dev->base_addr));
523 /* Enable this entry in the ARC */
524
525 writel(1,ETHER_ARC_ENA(dev->base_addr));
526
527 return;
528}
529
530
531static void ether00_reset(struct net_device *dev)
532{
533 /* reset the controller */
534 writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr));
535
536 /*
537 * Make sure we're not going to send anything
538 */
539
540 writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr));
541
542 /*
543 * Make sure we're not going to receive anything
544 */
545 writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
546
547 /*
548 * Disable Interrupts for now, and set the burst size to 8 bytes
549 */
550
551 writel(ETHER_DMA_CTL_INTMASK_MSK |
552 ((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK)
553 |(2<<ETHER_DMA_CTL_RXALIGN_OFST),
554 ETHER_DMA_CTL(dev->base_addr));
555
556
557 /*
558 * Set TxThrsh - start transmitting a packet after 1514
559 * bytes or when a packet is complete, whichever comes first
560 */
561 writew(1514,ETHER_TXTHRSH(dev->base_addr));
562
563 /*
564 * Set TxPollCtr. Each cycle is
565 * 61.44 microseconds with a 33 MHz bus
566 */
567 writew(1,ETHER_TXPOLLCTR(dev->base_addr));
568
569 /*
570 * Set Rx_Ctl - Turn off reception and let RxData turn it
571 * on later
572 */
573 writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
574
575}
576
577
578static void ether00_set_multicast(struct net_device* dev)
579{
580 int count=dev->mc_count;
581
582 /* Set promiscuous mode if it's asked for. */
583
584 if (dev->flags&IFF_PROMISC){
585
586 writew( ETHER_ARC_CTL_COMPEN_MSK |
587 ETHER_ARC_CTL_BROADACC_MSK |
588 ETHER_ARC_CTL_GROUPACC_MSK |
589 ETHER_ARC_CTL_STATIONACC_MSK,
590 ETHER_ARC_CTL(dev->base_addr));
591 return;
592 }
593
594 /*
595 * Get all multicast packets if required, or if there are too
596 * many addresses to fit in hardware
597 */
598 if (dev->flags & IFF_ALLMULTI){
599 writew( ETHER_ARC_CTL_COMPEN_MSK |
600 ETHER_ARC_CTL_GROUPACC_MSK |
601 ETHER_ARC_CTL_BROADACC_MSK,
602 ETHER_ARC_CTL(dev->base_addr));
603 return;
604 }
605 if (dev->mc_count > (ETHER_ARC_SIZE - 1)){
606
607 printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n");
608 writew( ETHER_ARC_CTL_COMPEN_MSK |
609 ETHER_ARC_CTL_GROUPACC_MSK |
610 ETHER_ARC_CTL_BROADACC_MSK,
611 ETHER_ARC_CTL(dev->base_addr));
612 return;
613 }
614
615 if(dev->mc_count){
616 struct dev_mc_list *mc_list_ent=dev->mc_list;
617 unsigned int temp,i;
618 DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list));
619 DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n",
620 mc_list_ent->dmi_addr[5],
621 mc_list_ent->dmi_addr[4],
622 mc_list_ent->dmi_addr[3],
623 mc_list_ent->dmi_addr[2],
624 mc_list_ent->dmi_addr[1],
625 mc_list_ent->dmi_addr[0]);)
626
627 /*
628 * The first 6 bytes are the MAC address, so
629 * don't change them!
630 */
631 writew(4,ETHER_ARC_ADR(dev->base_addr));
632 temp=readl(ETHER_ARC_DATA(dev->base_addr));
633 temp&=0xffff0000;
634
635 /* Disable the current multicast stuff */
636 writel(1,ETHER_ARC_ENA(dev->base_addr));
637
638 for(;;){
639 temp|=mc_list_ent->dmi_addr[1] |
640 mc_list_ent->dmi_addr[0]<<8;
641 writel(temp,ETHER_ARC_DATA(dev->base_addr));
642
643 i=readl(ETHER_ARC_ADR(dev->base_addr));
644 writew(i+4,ETHER_ARC_ADR(dev->base_addr));
645
646 temp=mc_list_ent->dmi_addr[5]|
647 mc_list_ent->dmi_addr[4]<<8 |
648 mc_list_ent->dmi_addr[3]<<16 |
649 mc_list_ent->dmi_addr[2]<<24;
650 writel(temp,ETHER_ARC_DATA(dev->base_addr));
651
652 count--;
653 if(!mc_list_ent->next || !count){
654 break;
655 }
656 DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);)
657 mc_list_ent=mc_list_ent->next;
658
659
660 i=readl(ETHER_ARC_ADR(dev->base_addr));
661 writel(i+4,ETHER_ARC_ADR(dev->base_addr));
662
663 temp=mc_list_ent->dmi_addr[3]|
664 mc_list_ent->dmi_addr[2]<<8 |
665 mc_list_ent->dmi_addr[1]<<16 |
666 mc_list_ent->dmi_addr[0]<<24;
667 writel(temp,ETHER_ARC_DATA(dev->base_addr));
668
669 i=readl(ETHER_ARC_ADR(dev->base_addr));
670 writel(i+4,ETHER_ARC_ADR(dev->base_addr));
671
672 temp=mc_list_ent->dmi_addr[4]<<16 |
673 mc_list_ent->dmi_addr[5]<<24;
674
675 writel(temp,ETHER_ARC_DATA(dev->base_addr));
676
677 count--;
678 if(!mc_list_ent->next || !count){
679 break;
680 }
681 mc_list_ent=mc_list_ent->next;
682 }
683
684
685 if(count)
686 printk(KERN_WARNING "Multicast list size error\n");
687
688
689 writew( ETHER_ARC_CTL_BROADACC_MSK|
690 ETHER_ARC_CTL_COMPEN_MSK,
691 ETHER_ARC_CTL(dev->base_addr));
692
693 }
694
695 /* enable the active ARC enties */
696 writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr));
697}
698
699
700static int ether00_open(struct net_device* dev)
701{
702 int result,tmp;
703 struct net_priv* priv;
704
705 if (!is_valid_ether_addr(dev->dev_addr))
706 return -EINVAL;
707
708 /* Install interrupt handlers */
709 result=request_irq(dev->irq,ether00_int,0,"ether00",dev);
710 if(result)
711 goto open_err1;
712
713 result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev);
714 if(result)
715 goto open_err2;
716
717 ether00_reset(dev);
718 result=ether00_mem_init(dev);
719 if(result)
720 goto open_err3;
721
722
723 ether00_setup_ethernet_address(dev);
724
725 ether00_set_multicast(dev);
726
727 result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK);
728 if(result)
729 goto open_err4;
730 result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK |
731 PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK);
732 if(result)
733 goto open_err4;
734
735 /* Start the device enable interrupts */
736 writew(ETHER_RX_CTL_RXEN_MSK
737// | ETHER_RX_CTL_STRIPCRC_MSK
738 | ETHER_RX_CTL_ENGOOD_MSK
739 | ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK
740 | ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK,
741 ETHER_RX_CTL(dev->base_addr));
742
743 writew(ETHER_TX_CTL_TXEN_MSK|
744 ETHER_TX_CTL_ENEXDEFER_MSK|
745 ETHER_TX_CTL_ENLCARR_MSK|
746 ETHER_TX_CTL_ENEXCOLL_MSK|
747 ETHER_TX_CTL_ENLATECOLL_MSK|
748 ETHER_TX_CTL_ENTXPAR_MSK|
749 ETHER_TX_CTL_ENCOMP_MSK,
750 ETHER_TX_CTL(dev->base_addr));
751
752 tmp=readl(ETHER_DMA_CTL(dev->base_addr));
753 writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr));
754
755 return 0;
756
757 open_err4:
758 ether00_reset(dev);
759 open_err3:
760 free_irq(2,dev);
761 open_err2:
762 free_irq(dev->irq,dev);
763 open_err1:
764 return result;
765
766}
767
768
769static int ether00_tx(struct sk_buff* skb, struct net_device* dev)
770{
771 struct net_priv *priv=dev->priv;
772 struct tx_fda_ent *fda_ptr;
773 int i;
774
775
776 /*
777 * Find an empty slot in which to stick the frame
778 */
779 fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr)));
780 i=0;
781 while(i<TX_NUM_FDESC){
782 if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
783 fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext);
784 }
785 else {
786 break;
787 }
788 i++;
789 }
790
791 /* Write the skb data from the cache*/
792 consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
793 fda_ptr->bd.BuffData=(char*)__pa(skb->data);
794 fda_ptr->bd.BuffLength=(unsigned short)skb->len;
795 /* Save the pointer to the skb for freeing later */
796 fda_ptr->fd.FDSystem=(unsigned int)skb;
797 fda_ptr->fd.FDStat=0;
798 /* Pass ownership of the buffers to the controller */
799 fda_ptr->fd.FDCtl=1;
800 fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK;
801
802 /* If the next buffer in the list is full, stop the queue */
803 fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext);
804 if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
805 netif_stop_queue(dev);
806 priv->queue_stopped=1;
807 }
808
809 return 0;
810}
811
812static struct net_device_stats *ether00_stats(struct net_device* dev)
813{
814 struct net_priv *priv=dev->priv;
815 return &priv->stats;
816}
817
818
819static int ether00_stop(struct net_device* dev)
820{
821 struct net_priv *priv=dev->priv;
822 int tmp;
823
824 /* Stop/disable the device. */
825 tmp=readw(ETHER_RX_CTL(dev->base_addr));
826 tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK);
827 tmp|=ETHER_RX_CTL_RXHALT_MSK;
828 writew(tmp,ETHER_RX_CTL(dev->base_addr));
829
830 tmp=readl(ETHER_TX_CTL(dev->base_addr));
831 tmp&=~ETHER_TX_CTL_TXEN_MSK;
832 tmp|=ETHER_TX_CTL_TXHALT_MSK;
833 writel(tmp,ETHER_TX_CTL(dev->base_addr));
834
835 /* Free up system resources */
836 free_irq(dev->irq,dev);
837 free_irq(2,dev);
838 iounmap(priv->dma_data);
839
840 return 0;
841}
842
843
844static void ether00_get_ethernet_address(struct net_device* dev)
845{
846 struct mtd_info *mymtd=NULL;
847 int i;
848 size_t retlen;
849
850 /*
851 * For the Epxa10 dev board (camelot), the ethernet MAC
852 * address is of the form 00:aa:aa:00:xx:xx where
853 * 00:aa:aa is the Altera vendor ID and xx:xx is the
854 * last 2 bytes of the board serial number, as programmed
855 * into the OTP area of the flash device on EBI1. If this
856 * isn't an expa10 dev board, or there's no mtd support to
857 * read the serial number from flash then we'll force the
858 * use to set their own mac address using ifconfig.
859 */
860
861#ifdef CONFIG_ARCH_CAMELOT
862#ifdef CONFIG_MTD
863 /* get the mtd_info structure for the first mtd device*/
864 for(i=0;i<MAX_MTD_DEVICES;i++){
865 mymtd=get_mtd_device(NULL,i);
866 if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash"))
867 break;
868 }
869
870 if(!mymtd || !mymtd->read_user_prot_reg){
871 printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name);
872 }else{
873 mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]);
874 mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]);
875 dev->dev_addr[3]=0;
876 dev->dev_addr[2]=vendor_id[1];
877 dev->dev_addr[1]=vendor_id[0];
878 dev->dev_addr[0]=0;
879 }
880#else
881 printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name);
882#endif
883#endif
884
885 if (!is_valid_ether_addr(dev->dev_addr))
886 printk("%s: Invalid ethernet MAC address. Please set using "
887 "ifconfig\n", dev->name);
888
889}
890
891/*
892 * Keep a mapping of dev_info addresses -> port lines to use when
893 * removing ports dev==NULL indicates unused entry
894 */
895
896
897static struct net_device* dev_list[ETH_NR];
898
899static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data)
900{
901 struct net_device *dev;
902 struct net_priv *priv;
903 void *map_addr;
904 int result;
905 int i;
906
907 i=0;
908 while(dev_list[i] && i < ETH_NR)
909 i++;
910
911 if(i==ETH_NR){
912 printk(KERN_WARNING "ether00: Maximum number of ports reached\n");
913 return 0;
914 }
915
916
917 if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00"))
918 return -EBUSY;
919
920 dev = alloc_etherdev(sizeof(struct net_priv));
921 if(!dev) {
922 result = -ENOMEM;
923 goto out_release;
924 }
925 priv = dev->priv;
926
927 priv->tq_memupdate.routine=ether00_mem_update;
928 priv->tq_memupdate.data=(void*) dev;
929
930 spin_lock_init(&priv->rx_lock);
931
932 map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K);
933 if(!map_addr){
934 result = -ENOMEM;
935 out_kfree;
936 }
937
938 dev->open=ether00_open;
939 dev->stop=ether00_stop;
940 dev->set_multicast_list=ether00_set_multicast;
941 dev->hard_start_xmit=ether00_tx;
942 dev->get_stats=ether00_stats;
943
944 ether00_get_ethernet_address(dev);
945
946 SET_MODULE_OWNER(dev);
947
948 dev->base_addr=(unsigned int)map_addr;
949 dev->irq=dev_info->irq;
950 dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM;
951
952 result=register_netdev(dev);
953 if(result){
954 printk("Ether00: Error %i registering driver\n",result);
955 goto out_unmap;
956 }
957 printk("registered ether00 device at %#x\n",dev_info->base_addr);
958
959 dev_list[i]=dev;
960
961 return result;
962
963 out_unmap:
964 iounmap(map_addr);
965 out_kfree:
966 free_netdev(dev);
967 out_release:
968 release_mem_region(dev_info->base_addr, MAC_REG_SIZE);
969 return result;
970}
971
972
973static int ether00_remove_devices(void)
974{
975 int i;
976
977 for(i=0;i<ETH_NR;i++){
978 if(dev_list[i]){
979 netif_device_detach(dev_list[i]);
980 unregister_netdev(dev_list[i]);
981 iounmap((void*)dev_list[i]->base_addr);
982 release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE);
983 free_netdev(dev_list[i]);
984 dev_list[i]=0;
985 }
986 }
987 return 0;
988}
989
990static struct pld_hotswap_ops ether00_pldhs_ops={
991 .name = ETHER00_NAME,
992 .add_device = ether00_add_device,
993 .remove_devices = ether00_remove_devices,
994};
995
996
997static void __exit ether00_cleanup_module(void)
998{
999 int result;
1000 result=ether00_remove_devices();
1001 if(result)
1002 printk(KERN_WARNING "ether00: failed to remove all devices\n");
1003
1004 pldhs_unregister_driver(ETHER00_NAME);
1005}
1006module_exit(ether00_cleanup_module);
1007
1008
1009static int __init ether00_mod_init(void)
1010{
1011 printk("mod init\n");
1012 return pldhs_register_driver(&ether00_pldhs_ops);
1013
1014}
1015
1016module_init(ether00_mod_init);
1017
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 812bae62c8ec..47ea8338c03c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -359,29 +359,6 @@ config SERIAL_21285_CONSOLE
359 your boot loader (lilo or loadlin) about how to pass options to the 359 your boot loader (lilo or loadlin) about how to pass options to the
360 kernel at boot time.) 360 kernel at boot time.)
361 361
362config SERIAL_UART00
363 bool "Excalibur serial port (uart00) support"
364 depends on ARM && ARCH_CAMELOT
365 select SERIAL_CORE
366 help
367 Say Y here if you want to use the hard logic uart on Excalibur. This
368 driver also supports soft logic implementations of this uart core.
369
370config SERIAL_UART00_CONSOLE
371 bool "Support for console on Excalibur serial port"
372 depends on SERIAL_UART00
373 select SERIAL_CORE_CONSOLE
374 help
375 Say Y here if you want to support a serial console on an Excalibur
376 hard logic uart or uart00 IP core.
377
378 Even if you say Y here, the currently visible virtual console
379 (/dev/tty0) will still be used as the system console by default, but
380 you can alter that using a kernel command line option such as
381 "console=ttyS1". (Try "man bootparam" or see the documentation of
382 your boot loader (lilo or loadlin) about how to pass options to the
383 kernel at boot time.)
384
385config SERIAL_MPSC 362config SERIAL_MPSC
386 bool "Marvell MPSC serial port support" 363 bool "Marvell MPSC serial port support"
387 depends on PPC32 && MV64X60 364 depends on PPC32 && MV64X60
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d7c7c7180e33..137148bba4fa 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
29obj-$(CONFIG_SERIAL_PXA) += pxa.o 29obj-$(CONFIG_SERIAL_PXA) += pxa.o
30obj-$(CONFIG_SERIAL_SA1100) += sa1100.o 30obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
31obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o 31obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
32obj-$(CONFIG_SERIAL_UART00) += uart00.o
33obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o 32obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
34obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o 33obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
35obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 34obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
diff --git a/drivers/serial/uart00.c b/drivers/serial/uart00.c
deleted file mode 100644
index 47b504ff38b2..000000000000
--- a/drivers/serial/uart00.c
+++ /dev/null
@@ -1,782 +0,0 @@
1/*
2 * linux/drivers/serial/uart00.c
3 *
4 * Driver for UART00 serial ports
5 *
6 * Based on drivers/char/serial_amba.c, by ARM Limited &
7 * Deep Blue Solutions Ltd.
8 * Copyright 2001 Altera Corporation
9 *
10 * Update for 2.6.4 by Dirk Behme <dirk.behme@de.bosch.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * $Id: uart00.c,v 1.35 2002/07/28 10:03:28 rmk Exp $
27 *
28 */
29#include <linux/config.h>
30
31#if defined(CONFIG_SERIAL_UART00_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/module.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
44
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/sizes.h>
48
49#include <asm/arch/excalibur.h>
50#define UART00_TYPE (volatile unsigned int*)
51#include <asm/arch/uart00.h>
52#include <asm/arch/int_ctrl00.h>
53
54#define UART_NR 2
55
56#define SERIAL_UART00_NAME "ttyUA"
57#define SERIAL_UART00_MAJOR 204
58#define SERIAL_UART00_MINOR 16 /* Temporary - will change in future */
59#define SERIAL_UART00_NR UART_NR
60#define UART_PORT_SIZE 0x50
61
62#define UART00_ISR_PASS_LIMIT 256
63
64/*
65 * Access macros for the UART00 UARTs
66 */
67#define UART_GET_INT_STATUS(p) inl(UART_ISR((p)->membase))
68#define UART_PUT_IES(p, c) outl(c,UART_IES((p)->membase))
69#define UART_GET_IES(p) inl(UART_IES((p)->membase))
70#define UART_PUT_IEC(p, c) outl(c,UART_IEC((p)->membase))
71#define UART_GET_IEC(p) inl(UART_IEC((p)->membase))
72#define UART_PUT_CHAR(p, c) outl(c,UART_TD((p)->membase))
73#define UART_GET_CHAR(p) inl(UART_RD((p)->membase))
74#define UART_GET_RSR(p) inl(UART_RSR((p)->membase))
75#define UART_GET_RDS(p) inl(UART_RDS((p)->membase))
76#define UART_GET_MSR(p) inl(UART_MSR((p)->membase))
77#define UART_GET_MCR(p) inl(UART_MCR((p)->membase))
78#define UART_PUT_MCR(p, c) outl(c,UART_MCR((p)->membase))
79#define UART_GET_MC(p) inl(UART_MC((p)->membase))
80#define UART_PUT_MC(p, c) outl(c,UART_MC((p)->membase))
81#define UART_GET_TSR(p) inl(UART_TSR((p)->membase))
82#define UART_GET_DIV_HI(p) inl(UART_DIV_HI((p)->membase))
83#define UART_PUT_DIV_HI(p,c) outl(c,UART_DIV_HI((p)->membase))
84#define UART_GET_DIV_LO(p) inl(UART_DIV_LO((p)->membase))
85#define UART_PUT_DIV_LO(p,c) outl(c,UART_DIV_LO((p)->membase))
86#define UART_RX_DATA(s) ((s) & UART_RSR_RX_LEVEL_MSK)
87#define UART_TX_READY(s) (((s) & UART_TSR_TX_LEVEL_MSK) < 15)
88//#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART00_UARTFR_TMSK) == 0)
89
90static void uart00_stop_tx(struct uart_port *port)
91{
92 UART_PUT_IEC(port, UART_IEC_TIE_MSK);
93}
94
95static void uart00_stop_rx(struct uart_port *port)
96{
97 UART_PUT_IEC(port, UART_IEC_RE_MSK);
98}
99
100static void uart00_enable_ms(struct uart_port *port)
101{
102 UART_PUT_IES(port, UART_IES_ME_MSK);
103}
104
105static void
106uart00_rx_chars(struct uart_port *port, struct pt_regs *regs)
107{
108 struct tty_struct *tty = port->info->tty;
109 unsigned int status, ch, rds, flg, ignored = 0;
110
111 status = UART_GET_RSR(port);
112 while (UART_RX_DATA(status)) {
113 /*
114 * We need to read rds before reading the
115 * character from the fifo
116 */
117 rds = UART_GET_RDS(port);
118 ch = UART_GET_CHAR(port);
119 port->icount.rx++;
120
121 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
122 goto ignore_char;
123
124 flg = TTY_NORMAL;
125
126 /*
127 * Note that the error handling code is
128 * out of the main execution path
129 */
130 if (rds & (UART_RDS_BI_MSK |UART_RDS_FE_MSK|
131 UART_RDS_PE_MSK |UART_RDS_PE_MSK))
132 goto handle_error;
133 if (uart_handle_sysrq_char(port, ch, regs))
134 goto ignore_char;
135
136 error_return:
137 tty_insert_flip_char(tty, ch, flg);
138
139 ignore_char:
140 status = UART_GET_RSR(port);
141 }
142 out:
143 tty_flip_buffer_push(tty);
144 return;
145
146 handle_error:
147 if (rds & UART_RDS_BI_MSK) {
148 status &= ~(UART_RDS_FE_MSK | UART_RDS_PE_MSK);
149 port->icount.brk++;
150 if (uart_handle_break(port))
151 goto ignore_char;
152 } else if (rds & UART_RDS_PE_MSK)
153 port->icount.parity++;
154 else if (rds & UART_RDS_FE_MSK)
155 port->icount.frame++;
156 if (rds & UART_RDS_OE_MSK)
157 port->icount.overrun++;
158
159 if (rds & port->ignore_status_mask) {
160 if (++ignored > 100)
161 goto out;
162 goto ignore_char;
163 }
164 rds &= port->read_status_mask;
165
166 if (rds & UART_RDS_BI_MSK)
167 flg = TTY_BREAK;
168 else if (rds & UART_RDS_PE_MSK)
169 flg = TTY_PARITY;
170 else if (rds & UART_RDS_FE_MSK)
171 flg = TTY_FRAME;
172
173 if (rds & UART_RDS_OE_MSK) {
174 /*
175 * CHECK: does overrun affect the current character?
176 * ASSUMPTION: it does not.
177 */
178 tty_insert_flip_char(tty, ch, flg);
179 ch = 0;
180 flg = TTY_OVERRUN;
181 }
182#ifdef SUPPORT_SYSRQ
183 port->sysrq = 0;
184#endif
185 goto error_return;
186}
187
188static void uart00_tx_chars(struct uart_port *port)
189{
190 struct circ_buf *xmit = &port->info->xmit;
191 int count;
192
193 if (port->x_char) {
194 while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
195 barrier();
196 UART_PUT_CHAR(port, port->x_char);
197 port->icount.tx++;
198 port->x_char = 0;
199 return;
200 }
201 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
202 uart00_stop_tx(port);
203 return;
204 }
205
206 count = port->fifosize >> 1;
207 do {
208 while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
209 barrier();
210 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
211 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
212 port->icount.tx++;
213 if (uart_circ_empty(xmit))
214 break;
215 } while (--count > 0);
216
217 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
218 uart_write_wakeup(port);
219
220 if (uart_circ_empty(xmit))
221 uart00_stop_tx(port);
222}
223
224static void uart00_start_tx(struct uart_port *port)
225{
226 UART_PUT_IES(port, UART_IES_TIE_MSK);
227 uart00_tx_chars(port);
228}
229
230static void uart00_modem_status(struct uart_port *port)
231{
232 unsigned int status;
233
234 status = UART_GET_MSR(port);
235
236 if (!(status & (UART_MSR_DCTS_MSK | UART_MSR_DDSR_MSK |
237 UART_MSR_TERI_MSK | UART_MSR_DDCD_MSK)))
238 return;
239
240 if (status & UART_MSR_DDCD_MSK)
241 uart_handle_dcd_change(port, status & UART_MSR_DCD_MSK);
242
243 if (status & UART_MSR_DDSR_MSK)
244 port->icount.dsr++;
245
246 if (status & UART_MSR_DCTS_MSK)
247 uart_handle_cts_change(port, status & UART_MSR_CTS_MSK);
248
249 wake_up_interruptible(&port->info->delta_msr_wait);
250}
251
252static irqreturn_t uart00_int(int irq, void *dev_id, struct pt_regs *regs)
253{
254 struct uart_port *port = dev_id;
255 unsigned int status, pass_counter = 0;
256
257 status = UART_GET_INT_STATUS(port);
258 do {
259 if (status & UART_ISR_RI_MSK)
260 uart00_rx_chars(port, regs);
261 if (status & UART_ISR_MI_MSK)
262 uart00_modem_status(port);
263 if (status & (UART_ISR_TI_MSK | UART_ISR_TII_MSK))
264 uart00_tx_chars(port);
265 if (pass_counter++ > UART00_ISR_PASS_LIMIT)
266 break;
267
268 status = UART_GET_INT_STATUS(port);
269 } while (status);
270
271 return IRQ_HANDLED;
272}
273
274static unsigned int uart00_tx_empty(struct uart_port *port)
275{
276 return UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK? 0 : TIOCSER_TEMT;
277}
278
279static unsigned int uart00_get_mctrl(struct uart_port *port)
280{
281 unsigned int result = 0;
282 unsigned int status;
283
284 status = UART_GET_MSR(port);
285 if (status & UART_MSR_DCD_MSK)
286 result |= TIOCM_CAR;
287 if (status & UART_MSR_DSR_MSK)
288 result |= TIOCM_DSR;
289 if (status & UART_MSR_CTS_MSK)
290 result |= TIOCM_CTS;
291 if (status & UART_MSR_RI_MSK)
292 result |= TIOCM_RI;
293
294 return result;
295}
296
297static void uart00_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
298{
299}
300
301static void uart00_break_ctl(struct uart_port *port, int break_state)
302{
303 unsigned long flags;
304 unsigned int mcr;
305
306 spin_lock_irqsave(&port->lock, flags);
307 mcr = UART_GET_MCR(port);
308 if (break_state == -1)
309 mcr |= UART_MCR_BR_MSK;
310 else
311 mcr &= ~UART_MCR_BR_MSK;
312 UART_PUT_MCR(port, mcr);
313 spin_unlock_irqrestore(&port->lock, flags);
314}
315
316static void
317uart00_set_termios(struct uart_port *port, struct termios *termios,
318 struct termios *old)
319{
320 unsigned int uart_mc, old_ies, baud, quot;
321 unsigned long flags;
322
323 /*
324 * We don't support CREAD (yet)
325 */
326 termios->c_cflag |= CREAD;
327
328 /*
329 * Ask the core to calculate the divisor for us.
330 */
331 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
332 quot = uart_get_divisor(port, baud);
333
334 /* byte size and parity */
335 switch (termios->c_cflag & CSIZE) {
336 case CS5:
337 uart_mc = UART_MC_CLS_CHARLEN_5;
338 break;
339 case CS6:
340 uart_mc = UART_MC_CLS_CHARLEN_6;
341 break;
342 case CS7:
343 uart_mc = UART_MC_CLS_CHARLEN_7;
344 break;
345 default: // CS8
346 uart_mc = UART_MC_CLS_CHARLEN_8;
347 break;
348 }
349 if (termios->c_cflag & CSTOPB)
350 uart_mc|= UART_MC_ST_TWO;
351 if (termios->c_cflag & PARENB) {
352 uart_mc |= UART_MC_PE_MSK;
353 if (!(termios->c_cflag & PARODD))
354 uart_mc |= UART_MC_EP_MSK;
355 }
356
357 spin_lock_irqsave(&port->lock, flags);
358
359 /*
360 * Update the per-port timeout.
361 */
362 uart_update_timeout(port, termios->c_cflag, baud);
363
364 port->read_status_mask = UART_RDS_OE_MSK;
365 if (termios->c_iflag & INPCK)
366 port->read_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
367 if (termios->c_iflag & (BRKINT | PARMRK))
368 port->read_status_mask |= UART_RDS_BI_MSK;
369
370 /*
371 * Characters to ignore
372 */
373 port->ignore_status_mask = 0;
374 if (termios->c_iflag & IGNPAR)
375 port->ignore_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
376 if (termios->c_iflag & IGNBRK) {
377 port->ignore_status_mask |= UART_RDS_BI_MSK;
378 /*
379 * If we're ignoring parity and break indicators,
380 * ignore overruns to (for real raw support).
381 */
382 if (termios->c_iflag & IGNPAR)
383 port->ignore_status_mask |= UART_RDS_OE_MSK;
384 }
385
386 /* first, disable everything */
387 old_ies = UART_GET_IES(port);
388
389 if (UART_ENABLE_MS(port, termios->c_cflag))
390 old_ies |= UART_IES_ME_MSK;
391
392 /* Set baud rate */
393 UART_PUT_DIV_LO(port, (quot & 0xff));
394 UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
395
396 UART_PUT_MC(port, uart_mc);
397 UART_PUT_IES(port, old_ies);
398
399 spin_unlock_irqrestore(&port->lock, flags);
400}
401
402static int uart00_startup(struct uart_port *port)
403{
404 int result;
405
406 /*
407 * Allocate the IRQ
408 */
409 result = request_irq(port->irq, uart00_int, 0, "uart00", port);
410 if (result) {
411 printk(KERN_ERR "Request of irq %d failed\n", port->irq);
412 return result;
413 }
414
415 /*
416 * Finally, enable interrupts. Use the TII interrupt to minimise
417 * the number of interrupts generated. If higher performance is
418 * needed, consider using the TI interrupt with a suitable FIFO
419 * threshold
420 */
421 UART_PUT_IES(port, UART_IES_RE_MSK | UART_IES_TIE_MSK);
422
423 return 0;
424}
425
426static void uart00_shutdown(struct uart_port *port)
427{
428 /*
429 * disable all interrupts, disable the port
430 */
431 UART_PUT_IEC(port, 0xff);
432
433 /* disable break condition and fifos */
434 UART_PUT_MCR(port, UART_GET_MCR(port) &~UART_MCR_BR_MSK);
435
436 /*
437 * Free the interrupt
438 */
439 free_irq(port->irq, port);
440}
441
442static const char *uart00_type(struct uart_port *port)
443{
444 return port->type == PORT_UART00 ? "Altera UART00" : NULL;
445}
446
447/*
448 * Release the memory region(s) being used by 'port'
449 */
450static void uart00_release_port(struct uart_port *port)
451{
452 release_mem_region(port->mapbase, UART_PORT_SIZE);
453
454#ifdef CONFIG_ARCH_CAMELOT
455 if (port->membase != (void*)IO_ADDRESS(EXC_UART00_BASE)) {
456 iounmap(port->membase);
457 }
458#endif
459}
460
461/*
462 * Request the memory region(s) being used by 'port'
463 */
464static int uart00_request_port(struct uart_port *port)
465{
466 return request_mem_region(port->mapbase, UART_PORT_SIZE, "serial_uart00")
467 != NULL ? 0 : -EBUSY;
468}
469
470/*
471 * Configure/autoconfigure the port.
472 */
473static void uart00_config_port(struct uart_port *port, int flags)
474{
475
476 /*
477 * Map the io memory if this is a soft uart
478 */
479 if (!port->membase)
480 port->membase = ioremap_nocache(port->mapbase,SZ_4K);
481
482 if (!port->membase)
483 printk(KERN_ERR "serial00: cannot map io memory\n");
484 else
485 port->type = PORT_UART00;
486
487}
488
489/*
490 * verify the new serial_struct (for TIOCSSERIAL).
491 */
492static int uart00_verify_port(struct uart_port *port, struct serial_struct *ser)
493{
494 int ret = 0;
495 if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
496 ret = -EINVAL;
497 if (ser->irq < 0 || ser->irq >= NR_IRQS)
498 ret = -EINVAL;
499 if (ser->baud_base < 9600)
500 ret = -EINVAL;
501 return ret;
502}
503
504static struct uart_ops uart00_pops = {
505 .tx_empty = uart00_tx_empty,
506 .set_mctrl = uart00_set_mctrl_null,
507 .get_mctrl = uart00_get_mctrl,
508 .stop_tx = uart00_stop_tx,
509 .start_tx = uart00_start_tx,
510 .stop_rx = uart00_stop_rx,
511 .enable_ms = uart00_enable_ms,
512 .break_ctl = uart00_break_ctl,
513 .startup = uart00_startup,
514 .shutdown = uart00_shutdown,
515 .set_termios = uart00_set_termios,
516 .type = uart00_type,
517 .release_port = uart00_release_port,
518 .request_port = uart00_request_port,
519 .config_port = uart00_config_port,
520 .verify_port = uart00_verify_port,
521};
522
523
524#ifdef CONFIG_ARCH_CAMELOT
525static struct uart_port epxa10db_port = {
526 .membase = (void*)IO_ADDRESS(EXC_UART00_BASE),
527 .mapbase = EXC_UART00_BASE,
528 .iotype = SERIAL_IO_MEM,
529 .irq = IRQ_UART,
530 .uartclk = EXC_AHB2_CLK_FREQUENCY,
531 .fifosize = 16,
532 .ops = &uart00_pops,
533 .flags = ASYNC_BOOT_AUTOCONF,
534};
535#endif
536
537
538#ifdef CONFIG_SERIAL_UART00_CONSOLE
539static void uart00_console_write(struct console *co, const char *s, unsigned count)
540{
541#ifdef CONFIG_ARCH_CAMELOT
542 struct uart_port *port = &epxa10db_port;
543 unsigned int status, old_ies;
544 int i;
545
546 /*
547 * First save the CR then disable the interrupts
548 */
549 old_ies = UART_GET_IES(port);
550 UART_PUT_IEC(port,0xff);
551
552 /*
553 * Now, do each character
554 */
555 for (i = 0; i < count; i++) {
556 do {
557 status = UART_GET_TSR(port);
558 } while (!UART_TX_READY(status));
559 UART_PUT_CHAR(port, s[i]);
560 if (s[i] == '\n') {
561 do {
562 status = UART_GET_TSR(port);
563 } while (!UART_TX_READY(status));
564 UART_PUT_CHAR(port, '\r');
565 }
566 }
567
568 /*
569 * Finally, wait for transmitter to become empty
570 * and restore the IES
571 */
572 do {
573 status = UART_GET_TSR(port);
574 } while (status & UART_TSR_TX_LEVEL_MSK);
575 UART_PUT_IES(port, old_ies);
576#endif
577}
578
579static void __init
580uart00_console_get_options(struct uart_port *port, int *baud,
581 int *parity, int *bits)
582{
583 unsigned int uart_mc, quot;
584
585 uart_mc = UART_GET_MC(port);
586
587 *parity = 'n';
588 if (uart_mc & UART_MC_PE_MSK) {
589 if (uart_mc & UART_MC_EP_MSK)
590 *parity = 'e';
591 else
592 *parity = 'o';
593 }
594
595 switch (uart_mc & UART_MC_CLS_MSK) {
596 case UART_MC_CLS_CHARLEN_5:
597 *bits = 5;
598 break;
599 case UART_MC_CLS_CHARLEN_6:
600 *bits = 6;
601 break;
602 case UART_MC_CLS_CHARLEN_7:
603 *bits = 7;
604 break;
605 case UART_MC_CLS_CHARLEN_8:
606 *bits = 8;
607 break;
608 }
609 quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
610 *baud = port->uartclk / (16 *quot );
611}
612
613static int __init uart00_console_setup(struct console *co, char *options)
614{
615 struct uart_port *port;
616 int baud = 115200;
617 int bits = 8;
618 int parity = 'n';
619 int flow = 'n';
620
621#ifdef CONFIG_ARCH_CAMELOT
622 port = &epxa10db_port; ;
623#else
624 return -ENODEV;
625#endif
626 if (options)
627 uart_parse_options(options, &baud, &parity, &bits, &flow);
628 else
629 uart00_console_get_options(port, &baud, &parity, &bits);
630
631 return uart_set_options(port, co, baud, parity, bits, flow);
632}
633
634extern struct uart_driver uart00_reg;
635static struct console uart00_console = {
636 .name = SERIAL_UART00_NAME,
637 .write = uart00_console_write,
638 .device = uart_console_device,
639 .setup = uart00_console_setup,
640 .flags = CON_PRINTBUFFER,
641 .index = 0,
642 .data = &uart00_reg,
643};
644
645static int __init uart00_console_init(void)
646{
647 register_console(&uart00_console);
648 return 0;
649}
650console_initcall(uart00_console_init);
651
652#define UART00_CONSOLE &uart00_console
653#else
654#define UART00_CONSOLE NULL
655#endif
656
657static struct uart_driver uart00_reg = {
658 .owner = NULL,
659 .driver_name = SERIAL_UART00_NAME,
660 .dev_name = SERIAL_UART00_NAME,
661 .major = SERIAL_UART00_MAJOR,
662 .minor = SERIAL_UART00_MINOR,
663 .nr = UART_NR,
664 .cons = UART00_CONSOLE,
665};
666
667struct dev_port_entry{
668 unsigned int base_addr;
669 struct uart_port *port;
670};
671
672#ifdef CONFIG_PLD_HOTSWAP
673
674static struct dev_port_entry dev_port_map[UART_NR];
675
676/*
677 * Keep a mapping of dev_info addresses -> port lines to use when
678 * removing ports dev==NULL indicates unused entry
679 */
680
681struct uart00_ps_data{
682 unsigned int clk;
683 unsigned int fifosize;
684};
685
686int uart00_add_device(struct pldhs_dev_info* dev_info, void* dev_ps_data)
687{
688 struct uart00_ps_data* dev_ps=dev_ps_data;
689 struct uart_port * port;
690 int i,result;
691
692 i=0;
693 while(dev_port_map[i].port)
694 i++;
695
696 if(i==UART_NR){
697 printk(KERN_WARNING "uart00: Maximum number of ports reached\n");
698 return 0;
699 }
700
701 port=kmalloc(sizeof(struct uart_port),GFP_KERNEL);
702 if(!port)
703 return -ENOMEM;
704
705 printk("clk=%d fifo=%d\n",dev_ps->clk,dev_ps->fifosize);
706 port->membase=0;
707 port->mapbase=dev_info->base_addr;
708 port->iotype=SERIAL_IO_MEM;
709 port->irq=dev_info->irq;
710 port->uartclk=dev_ps->clk;
711 port->fifosize=dev_ps->fifosize;
712 port->ops=&uart00_pops;
713 port->line=i;
714 port->flags=ASYNC_BOOT_AUTOCONF;
715
716 result=uart_add_one_port(&uart00_reg, port);
717 if(result){
718 printk("uart_add_one_port returned %d\n",result);
719 return result;
720 }
721 dev_port_map[i].base_addr=dev_info->base_addr;
722 dev_port_map[i].port=port;
723 printk("uart00: added device at %x as ttyUA%d\n",dev_port_map[i].base_addr,i);
724 return 0;
725
726}
727
728int uart00_remove_devices(void)
729{
730 int i,result;
731
732
733 result=0;
734 for(i=1;i<UART_NR;i++){
735 if(dev_port_map[i].base_addr){
736 result=uart_remove_one_port(&uart00_reg, dev_port_map[i].port);
737 if(result)
738 return result;
739
740 /* port removed sucessfully, so now tidy up */
741 kfree(dev_port_map[i].port);
742 dev_port_map[i].base_addr=0;
743 dev_port_map[i].port=NULL;
744 }
745 }
746 return 0;
747
748}
749
750struct pld_hotswap_ops uart00_pldhs_ops={
751 .name = "uart00",
752 .add_device = uart00_add_device,
753 .remove_devices = uart00_remove_devices,
754};
755
756#endif
757
758static int __init uart00_init(void)
759{
760 int result;
761
762 printk(KERN_INFO "Serial: UART00 driver $Revision: 1.35 $\n");
763
764 printk(KERN_WARNING "serial_uart00:Using temporary major/minor pairs"
765 " - these WILL change in the future\n");
766
767 result = uart_register_driver(&uart00_reg);
768 if (result)
769 return result;
770#ifdef CONFIG_ARCH_CAMELOT
771 result = uart_add_one_port(&uart00_reg,&epxa10db_port);
772#endif
773 if (result)
774 uart_unregister_driver(&uart00_reg);
775
776#ifdef CONFIG_PLD_HOTSWAP
777 pldhs_register_driver(&uart00_pldhs_ops);
778#endif
779 return result;
780}
781
782__initcall(uart00_init);
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S
deleted file mode 100644
index 1d11c51f498f..000000000000
--- a/include/asm-arm/arch-epxa10db/debug-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/include/asm-arm/arch-epxa10db/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <asm/arch/excalibur.h>
15#define UART00_TYPE
16#include <asm/arch/uart00.h>
17
18 .macro addruart,rx
19 mrc p15, 0, \rx, c1, c0
20 tst \rx, #1 @ MMU enabled?
21 ldr \rx, =EXC_UART00_BASE @ physical base address
22 orrne \rx, \rx, #0xff000000 @ virtual base
23 orrne \rx, \rx, #0x00f00000
24 .endm
25
26 .macro senduart,rd,rx
27 str \rd, [\rx, #UART_TD(0)]
28 .endm
29
30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #UART_TSR(0)]
32 and \rd, \rd, #UART_TSR_TX_LEVEL_MSK
33 cmp \rd, #15
34 beq 1001b
35 .endm
36
37 .macro busyuart,rd,rx
381001: ldr \rd, [\rx, #UART_TSR(0)]
39 ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK
40 bne 1001b
41 .endm
diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-epxa10db/dma.h
deleted file mode 100644
index de20ec8e74b1..000000000000
--- a/include/asm-arm/arch-epxa10db/dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-camelot/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S
deleted file mode 100644
index de6ae08334e2..000000000000
--- a/include/asm-arm/arch-epxa10db/entry-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-arm/arch-epxa10db/entry-macro.S
3 *
4 * Low-level IRQ helper macros for epxa10db platform
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <asm/arch/platform.h>
11#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
12#include <asm/arch/int_ctrl00.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
18
19 ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
20 ldr \irqnr,[\irqstat]
21 cmp \irqnr,#0
22 subne \irqnr,\irqnr,#1
23
24 .endm
25
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h
deleted file mode 100644
index b737b8aabe2f..000000000000
--- a/include/asm-arm/arch-epxa10db/ether00.h
+++ /dev/null
@@ -1,482 +0,0 @@
1#ifndef __ETHER00_H
2#define __ETHER00_H
3
4
5
6/*
7 * Register definitions for the Ethernet MAC
8 */
9
10/*
11 * Copyright (c) Altera Corporation 2000.
12 * All rights reserved.
13 */
14
15/*
16* Structures for the DMA controller
17*/
18typedef struct fda_desc
19 {
20 struct fda_desc * FDNext;
21 long FDSystem;
22 long FDStat;
23 short FDLength;
24 short FDCtl;
25 }FDA_DESC;
26
27typedef struct buf_desc
28 {
29 char * BuffData;
30 short BuffLength;
31 char BDStat;
32 char BDCtl;
33 }BUF_DESC;
34
35/*
36* Control masks for the DMA controller
37*/
38#define FDCTL_BDCOUNT_MSK (0x1F)
39#define FDCTL_BDCOUNT_OFST (0)
40#define FDCTL_FRMOPT_MSK (0x7C00)
41#define FDCTL_FRMOPT_OFST (10)
42#define FDCTL_COWNSFD_MSK (0x8000)
43#define FDCTL_COWNSFD_OFST (15)
44
45#define BDCTL_RXBDSEQN_MSK (0x7F)
46#define BDCTL_RXBDSEQN_OFST (0)
47#define BDCTL_COWNSBD_MSK (0x80)
48#define BDCTL_COWNSBD_OFST (7)
49
50#define FDNEXT_EOL_MSK (0x1)
51#define FDNEXT_EOL_OFST (0)
52#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0)
53#define FDNEXT_EOL_POINTER_OFST (4)
54
55#define ETHER_ARC_SIZE (21)
56
57/*
58* Register definitions and masks
59*/
60#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100))
61#define ETHER_DMA_CTL_DMBURST_OFST (2)
62#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC)
63#define ETHER_DMA_CTL_POWRMGMNT_OFST (11)
64#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000)
65#define ETHER_DMA_CTL_TXBIGE_OFST (14)
66#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000)
67#define ETHER_DMA_CTL_RXBIGE_OFST (15)
68#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000)
69#define ETHER_DMA_CTL_TXWAKEUP_OFST (16)
70#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000)
71#define ETHER_DMA_CTL_SWINTREQ_OFST (17)
72#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000)
73#define ETHER_DMA_CTL_INTMASK_OFST (18)
74#define ETHER_DMA_CTL_INTMASK_MSK (0x40000)
75#define ETHER_DMA_CTL_M66ENSTAT_OFST (19)
76#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000)
77#define ETHER_DMA_CTL_RMTXINIT_OFST (20)
78#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000)
79#define ETHER_DMA_CTL_RMRXINIT_OFST (21)
80#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000)
81#define ETHER_DMA_CTL_RXALIGN_OFST (22)
82#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000)
83#define ETHER_DMA_CTL_RMSWRQ_OFST (24)
84#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000)
85#define ETHER_DMA_CTL_RMEMBANK_OFST (25)
86#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000)
87
88#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104))
89
90#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308))
91
92#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c))
93
94#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110))
95#define ETHER_BLFFRMPTR_EOL_OFST (0)
96#define ETHER_BLFFRMPTR_EOL_MSK (0x1)
97#define ETHER_BLFFRMPTR_ADDRESS_OFST (4)
98#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0)
99
100#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114))
101#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2)
102#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC)
103#define ETHER_RXFRAGSIZE_ENPACK_OFST (15)
104#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000)
105
106#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118))
107#define ETHER_INT_EN_FDAEXEN_OFST (0)
108#define ETHER_INT_EN_FDAEXEN_MSK (0x1)
109#define ETHER_INT_EN_BLEXEN_OFST (1)
110#define ETHER_INT_EN_BLEXN_MSK (0x2)
111#define ETHER_INT_EN_STARGABTEN_OFST (2)
112#define ETHER_INT_EN_STARGABTEN_MSK (0x4)
113#define ETHER_INT_EN_RTARGABTEN_OFST (3)
114#define ETHER_INT_EN_RTARGABTEN_MSK (0x8)
115#define ETHER_INT_EN_RMASABTEN_OFST (4)
116#define ETHER_INT_EN_RMASABTEN_MSK (0x10)
117#define ETHER_INT_EN_SSYSERREN_OFST (5)
118#define ETHER_INT_EN_SSYSERREN_MSK (0x20)
119#define ETHER_INT_EN_DPARERREN_OFST (6)
120#define ETHER_INT_EN_DPARERREN_MSK (0x40)
121#define ETHER_INT_EN_EARNOTEN_OFST (7)
122#define ETHER_INT_EN_EARNOTEN_MSK (0x80)
123#define ETHER_INT_EN_DPARDEN_OFST (8)
124#define ETHER_INT_EN_DPARDEN_MSK (0x100)
125#define ETHER_INT_EN_DMPARERREN_OFST (9)
126#define ETHER_INT_EN_DMPARERREN_MSK (0x200)
127#define ETHER_INT_EN_TXCTLCMPEN_OFST (10)
128#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400)
129#define ETHER_INT_EN_NRABTEN_OFST (11)
130#define ETHER_INT_EN_NRABTEN_MSK (0x800)
131
132#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C))
133#define ETHER_FDA_BAS_ADDRESS_OFST (4)
134#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0)
135
136#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120))
137#define ETHER_FDA_LIM_COUNT_OFST (4)
138#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0)
139
140#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124))
141#define ETHER_INT_SRC_INTMACTX_OFST (0)
142#define ETHER_INT_SRC_INTMACTX_MSK (0x1)
143#define ETHER_INT_SRC_INTMACRX_OFST (1)
144#define ETHER_INT_SRC_INTMACRX_MSK (0x2)
145#define ETHER_INT_SRC_INTSBUS_OFST (2)
146#define ETHER_INT_SRC_INTSBUS_MSK (0x4)
147#define ETHER_INT_SRC_INTFDAEX_OFST (3)
148#define ETHER_INT_SRC_INTFDAEX_MSK (0x8)
149#define ETHER_INT_SRC_INTBLEX_OFST (4)
150#define ETHER_INT_SRC_INTBLEX_MSK (0x10)
151#define ETHER_INT_SRC_SWINT_OFST (5)
152#define ETHER_INT_SRC_SWINT_MSK (0x20)
153#define ETHER_INT_SRC_INTEARNOT_OFST (6)
154#define ETHER_INT_SRC_INTEARNOT_MSK (0x40)
155#define ETHER_INT_SRC_DMPARERR_OFST (7)
156#define ETHER_INT_SRC_DMPARERR_MSK (0x80)
157#define ETHER_INT_SRC_INTEXBD_OFST (8)
158#define ETHER_INT_SRC_INTEXBD_MSK (0x100)
159#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9)
160#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200)
161#define ETHER_INT_SRC_INTNRABT_OFST (10)
162#define ETHER_INT_SRC_INTNRABT_MSK (0x400)
163#define ETHER_INT_SRC_FDAEX_OFST (11)
164#define ETHER_INT_SRC_FDAEX_MSK (0x800)
165#define ETHER_INT_SRC_BLEX_OFST (12)
166#define ETHER_INT_SRC_BLEX_MSK (0x1000)
167#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13)
168#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000)
169#define ETHER_INT_SRC_NRABT_OFST (14)
170#define ETHER_INT_SRC_NRABT_MSK (0x4000)
171#define ETHER_INT_SRC_INTLINK_OFST (15)
172#define ETHER_INT_SRC_INTLINK_MSK (0x8000)
173#define ETHER_INT_SRC_INTEXDEFER_OFST (16)
174#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000)
175#define ETHER_INT_SRC_INTRMON_OFST (17)
176#define ETHER_INT_SRC_INTRMON_MSK (0x20000)
177#define ETHER_INT_SRC_IRQ_MSK (0x83FF)
178
179#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40))
180#define ETHER_PAUSECNT_COUNT_OFST (0)
181#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF)
182
183#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44))
184#define ETHER_REMPAUCNT_COUNT_OFST (0)
185#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF)
186
187#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348))
188#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0)
189#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF)
190
191#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0))
192#define ETHER_MAC_CTL_HALTREQ_OFST (0)
193#define ETHER_MAC_CTL_HALTREQ_MSK (0x1)
194#define ETHER_MAC_CTL_HALTIMM_OFST (1)
195#define ETHER_MAC_CTL_HALTIMM_MSK (0x2)
196#define ETHER_MAC_CTL_RESET_OFST (2)
197#define ETHER_MAC_CTL_RESET_MSK (0x4)
198#define ETHER_MAC_CTL_FULLDUP_OFST (3)
199#define ETHER_MAC_CTL_FULLDUP_MSK (0x8)
200#define ETHER_MAC_CTL_MACLOOP_OFST (4)
201#define ETHER_MAC_CTL_MACLOOP_MSK (0x10)
202#define ETHER_MAC_CTL_CONN_OFST (5)
203#define ETHER_MAC_CTL_CONN_MSK (0x60)
204#define ETHER_MAC_CTL_LOOP10_OFST (7)
205#define ETHER_MAC_CTL_LOOP10_MSK (0x80)
206#define ETHER_MAC_CTL_LNKCHG_OFST (8)
207#define ETHER_MAC_CTL_LNKCHG_MSK (0x100)
208#define ETHER_MAC_CTL_MISSROLL_OFST (10)
209#define ETHER_MAC_CTL_MISSROLL_MSK (0x400)
210#define ETHER_MAC_CTL_ENMISSROLL_OFST (13)
211#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000)
212#define ETHER_MAC_CTL_LINK10_OFST (15)
213#define ETHER_MAC_CTL_LINK10_MSK (0x8000)
214
215#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4))
216#define ETHER_ARC_CTL_STATIONACC_OFST (0)
217#define ETHER_ARC_CTL_STATIONACC_MSK (0x1)
218#define ETHER_ARC_CTL_GROUPACC_OFST (1)
219#define ETHER_ARC_CTL_GROUPACC_MSK (0x2)
220#define ETHER_ARC_CTL_BROADACC_OFST (2)
221#define ETHER_ARC_CTL_BROADACC_MSK (0x4)
222#define ETHER_ARC_CTL_NEGARC_OFST (3)
223#define ETHER_ARC_CTL_NEGARC_MSK (0x8)
224#define ETHER_ARC_CTL_COMPEN_OFST (4)
225#define ETHER_ARC_CTL_COMPEN_MSK (0x10)
226
227#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8))
228#define ETHER_TX_CTL_TXEN_OFST (0)
229#define ETHER_TX_CTL_TXEN_MSK (0x1)
230#define ETHER_TX_CTL_TXHALT_OFST (1)
231#define ETHER_TX_CTL_TXHALT_MSK (0x2)
232#define ETHER_TX_CTL_NOPAD_OFST (2)
233#define ETHER_TX_CTL_NOPAD_MSK (0x4)
234#define ETHER_TX_CTL_NOCRC_OFST (3)
235#define ETHER_TX_CTL_NOCRC_MSK (0x8)
236#define ETHER_TX_CTL_FBACK_OFST (4)
237#define ETHER_TX_CTL_FBACK_MSK (0x10)
238#define ETHER_TX_CTL_NOEXDEF_OFST (5)
239#define ETHER_TX_CTL_NOEXDEF_MSK (0x20)
240#define ETHER_TX_CTL_SDPAUSE_OFST (6)
241#define ETHER_TX_CTL_SDPAUSE_MSK (0x40)
242#define ETHER_TX_CTL_MII10_OFST (7)
243#define ETHER_TX_CTL_MII10_MSK (0x80)
244#define ETHER_TX_CTL_ENUNDER_OFST (8)
245#define ETHER_TX_CTL_ENUNDER_MSK (0x100)
246#define ETHER_TX_CTL_ENEXDEFER_OFST (9)
247#define ETHER_TX_CTL_ENEXDEFER_MSK (0x200)
248#define ETHER_TX_CTL_ENLCARR_OFST (10)
249#define ETHER_TX_CTL_ENLCARR_MSK (0x400)
250#define ETHER_TX_CTL_ENEXCOLL_OFST (11)
251#define ETHER_TX_CTL_ENEXCOLL_MSK (0x800)
252#define ETHER_TX_CTL_ENLATECOLL_OFST (12)
253#define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000)
254#define ETHER_TX_CTL_ENTXPAR_OFST (13)
255#define ETHER_TX_CTL_ENTXPAR_MSK (0x2000)
256#define ETHER_TX_CTL_ENCOMP_OFST (14)
257#define ETHER_TX_CTL_ENCOMP_MSK (0x4000)
258
259#define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc))
260#define ETHER_TX_STAT_TXCOLL_OFST (0)
261#define ETHER_TX_STAT_TXCOLL_MSK (0xF)
262#define ETHER_TX_STAT_EXCOLL_OFST (4)
263#define ETHER_TX_STAT_EXCOLL_MSK (0x10)
264#define ETHER_TX_STAT_TXDEFER_OFST (5)
265#define ETHER_TX_STAT_TXDEFER_MSK (0x20)
266#define ETHER_TX_STAT_PAUSED_OFST (6)
267#define ETHER_TX_STAT_PAUSED_MSK (0x40)
268#define ETHER_TX_STAT_INTTX_OFST (7)
269#define ETHER_TX_STAT_INTTX_MSK (0x80)
270#define ETHER_TX_STAT_UNDER_OFST (8)
271#define ETHER_TX_STAT_UNDER_MSK (0x100)
272#define ETHER_TX_STAT_EXDEFER_OFST (9)
273#define ETHER_TX_STAT_EXDEFER_MSK (0x200)
274#define ETHER_TX_STAT_LCARR_OFST (10)
275#define ETHER_TX_STAT_LCARR_MSK (0x400)
276#define ETHER_TX_STAT_TX10STAT_OFST (11)
277#define ETHER_TX_STAT_TX10STAT_MSK (0x800)
278#define ETHER_TX_STAT_LATECOLL_OFST (12)
279#define ETHER_TX_STAT_LATECOLL_MSK (0x1000)
280#define ETHER_TX_STAT_TXPAR_OFST (13)
281#define ETHER_TX_STAT_TXPAR_MSK (0x2000)
282#define ETHER_TX_STAT_COMP_OFST (14)
283#define ETHER_TX_STAT_COMP_MSK (0x4000)
284#define ETHER_TX_STAT_TXHALTED_OFST (15)
285#define ETHER_TX_STAT_TXHALTED_MSK (0x8000)
286#define ETHER_TX_STAT_SQERR_OFST (16)
287#define ETHER_TX_STAT_SQERR_MSK (0x10000)
288#define ETHER_TX_STAT_TXMCAST_OFST (17)
289#define ETHER_TX_STAT_TXMCAST_MSK (0x20000)
290#define ETHER_TX_STAT_TXBCAST_OFST (18)
291#define ETHER_TX_STAT_TXBCAST_MSK (0x40000)
292#define ETHER_TX_STAT_VLAN_OFST (19)
293#define ETHER_TX_STAT_VLAN_MSK (0x80000)
294#define ETHER_TX_STAT_MACC_OFST (20)
295#define ETHER_TX_STAT_MACC_MSK (0x100000)
296#define ETHER_TX_STAT_TXPAUSE_OFST (21)
297#define ETHER_TX_STAT_TXPAUSE_MSK (0x200000)
298
299#define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10))
300#define ETHER_RX_CTL_RXEN_OFST (0)
301#define ETHER_RX_CTL_RXEN_MSK (0x1)
302#define ETHER_RX_CTL_RXHALT_OFST (1)
303#define ETHER_RX_CTL_RXHALT_MSK (0x2)
304#define ETHER_RX_CTL_LONGEN_OFST (2)
305#define ETHER_RX_CTL_LONGEN_MSK (0x4)
306#define ETHER_RX_CTL_SHORTEN_OFST (3)
307#define ETHER_RX_CTL_SHORTEN_MSK (0x8)
308#define ETHER_RX_CTL_STRIPCRC_OFST (4)
309#define ETHER_RX_CTL_STRIPCRC_MSK (0x10)
310#define ETHER_RX_CTL_PASSCTL_OFST (5)
311#define ETHER_RX_CTL_PASSCTL_MSK (0x20)
312#define ETHER_RX_CTL_IGNORECRC_OFST (6)
313#define ETHER_RX_CTL_IGNORECRC_MSK (0x40)
314#define ETHER_RX_CTL_ENALIGN_OFST (8)
315#define ETHER_RX_CTL_ENALIGN_MSK (0x100)
316#define ETHER_RX_CTL_ENCRCERR_OFST (9)
317#define ETHER_RX_CTL_ENCRCERR_MSK (0x200)
318#define ETHER_RX_CTL_ENOVER_OFST (10)
319#define ETHER_RX_CTL_ENOVER_MSK (0x400)
320#define ETHER_RX_CTL_ENLONGERR_OFST (11)
321#define ETHER_RX_CTL_ENLONGERR_MSK (0x800)
322#define ETHER_RX_CTL_ENRXPAR_OFST (13)
323#define ETHER_RX_CTL_ENRXPAR_MSK (0x2000)
324#define ETHER_RX_CTL_ENGOOD_OFST (14)
325#define ETHER_RX_CTL_ENGOOD_MSK (0x4000)
326
327#define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14))
328#define ETHER_RX_STAT_LENERR_OFST (4)
329#define ETHER_RX_STAT_LENERR_MSK (0x10)
330#define ETHER_RX_STAT_CTLRECD_OFST (5)
331#define ETHER_RX_STAT_CTLRECD_MSK (0x20)
332#define ETHER_RX_STAT_INTRX_OFST (6)
333#define ETHER_RX_STAT_INTRX_MSK (0x40)
334#define ETHER_RX_STAT_RX10STAT_OFST (7)
335#define ETHER_RX_STAT_RX10STAT_MSK (0x80)
336#define ETHER_RX_STAT_ALIGNERR_OFST (8)
337#define ETHER_RX_STAT_ALIGNERR_MSK (0x100)
338#define ETHER_RX_STAT_CRCERR_OFST (9)
339#define ETHER_RX_STAT_CRCERR_MSK (0x200)
340#define ETHER_RX_STAT_OVERFLOW_OFST (10)
341#define ETHER_RX_STAT_OVERFLOW_MSK (0x400)
342#define ETHER_RX_STAT_LONGERR_OFST (11)
343#define ETHER_RX_STAT_LONGERR_MSK (0x800)
344#define ETHER_RX_STAT_RXPAR_OFST (13)
345#define ETHER_RX_STAT_RXPAR_MSK (0x2000)
346#define ETHER_RX_STAT_GOOD_OFST (14)
347#define ETHER_RX_STAT_GOOD_MSK (0x4000)
348#define ETHER_RX_STAT_RXHALTED_OFST (15)
349#define ETHER_RX_STAT_RXHALTED_MSK (0x8000)
350#define ETHER_RX_STAT_RXMCAST_OFST (17)
351#define ETHER_RX_STAT_RXMCAST_MSK (0x10000)
352#define ETHER_RX_STAT_RXBCAST_OFST (18)
353#define ETHER_RX_STAT_RXBCAST_MSK (0x20000)
354#define ETHER_RX_STAT_RXVLAN_OFST (19)
355#define ETHER_RX_STAT_RXVLAN_MSK (0x40000)
356#define ETHER_RX_STAT_RXPAUSE_OFST (20)
357#define ETHER_RX_STAT_RXPAUSE_MSK (0x80000)
358#define ETHER_RX_STAT_ARCSTATUS_OFST (21)
359#define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000)
360#define ETHER_RX_STAT_ARCENT_OFST (25)
361#define ETHER_RX_STAT_ARCENT_MSK (0x1F000000)
362
363#define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18))
364
365#define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c))
366#define ETHER_MD_CA_ADDR_OFST (0)
367#define ETHER_MD_CA_ADDR_MSK (0x1F)
368#define ETHER_MD_CA_PHY_OFST (5)
369#define ETHER_MD_CA_PHY_MSK (0x3E0)
370#define ETHER_MD_CA_WR_OFST (10)
371#define ETHER_MD_CA_WR_MSK (0x400)
372#define ETHER_MD_CA_BUSY_OFST (11)
373#define ETHER_MD_CA_BUSY_MSK (0x800)
374#define ETHER_MD_CA_PRESUPP_OFST (12)
375#define ETHER_MD_CA_PRESUPP_MSK (0x1000)
376
377#define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160))
378#define ETHER_ARC_ADR_ARC_LOC_OFST (2)
379#define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC)
380
381#define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364))
382
383#define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28))
384#define ETHER_ARC_ENA_MSK (0x1FFFFF)
385
386#define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c))
387#define ETHER_PROM_CTL_PROM_ADDR_OFST (0)
388#define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F)
389#define ETHER_PROM_CTL_OPCODE_OFST (13)
390#define ETHER_PROM_CTL_OPCODE_MSK (0x6000)
391#define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000)
392#define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000)
393#define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000)
394#define ETHER_PROM_CTL_ENABLE_MSK (0x0030)
395#define ETHER_PROM_CTL_DISABLE_MSK (0x0000)
396#define ETHER_PROM_CTL_BUSY_OFST (15)
397#define ETHER_PROM_CTL_BUSY_MSK (0x8000)
398
399#define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30))
400
401#define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c))
402#define ETHER_MISS_CNT_COUNT_OFST (0)
403#define ETHER_MISS_CNT_COUNT_MSK (0xFFFF)
404
405#define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80))
406
407#define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84))
408#define ETHER_CNTACC_ADDR_OFST (0)
409#define ETHER_CNTACC_ADDR_MSK (0xFF)
410#define ETHER_CNTACC_WRRDN_OFST (8)
411#define ETHER_CNTACC_WRRDN_MSK (0x100)
412#define ETHER_CNTACC_CLEAR_OFST (9)
413#define ETHER_CNTACC_CLEAR_MSK (0x200)
414
415#define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88))
416#define ETHER_TXRMINTEN_MSK (0x3FFFFFFF)
417
418#define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C))
419#define ETHER_RXRMINTEN_MSK (0xFFFFFF)
420
421/*
422* RMON Registers
423*/
424#define RMON_COLLISION0 0x0
425#define RMON_COLLISION1 0x1
426#define RMON_COLLISION2 0x2
427#define RMON_COLLISION3 0x3
428#define RMON_COLLISION4 0x4
429#define RMON_COLLISION5 0x5
430#define RMON_COLLISION6 0x6
431#define RMON_COLLISION7 0x7
432#define RMON_COLLISION8 0x8
433#define RMON_COLLISION9 0x9
434#define RMON_COLLISION10 0xa
435#define RMON_COLLISION11 0xb
436#define RMON_COLLISION12 0xc
437#define RMON_COLLISION13 0xd
438#define RMON_COLLISION14 0xe
439#define RMON_COLLISION15 0xf
440#define RMON_COLLISION16 0x10
441#define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11
442#define RMON_LATE_COLLISIONS 0x12
443#define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13
444#define RMON_CARRIER_SENSE_ERRORS 0x14
445#define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15
446#define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16
447#define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17
448#define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18
449#define RMON_SQE_TEST_ERRORS 0x19
450#define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A
451#define RMON_MACCTRL_FRAMES_XMITTED 0x1B
452#define RMON_VLAN_FRAMES_XMITTED 0x1C
453#define RMON_OCTETS_XMITTED_OK 0x1D
454#define RMON_OCTETS_XMITTED_OK_HI 0x1E
455
456#define RMON_RX_PACKET_SIZES0 0x40
457#define RMON_RX_PACKET_SIZES1 0x41
458#define RMON_RX_PACKET_SIZES2 0x42
459#define RMON_RX_PACKET_SIZES3 0x43
460#define RMON_RX_PACKET_SIZES4 0x44
461#define RMON_RX_PACKET_SIZES5 0x45
462#define RMON_RX_PACKET_SIZES6 0x46
463#define RMON_RX_PACKET_SIZES7 0x47
464#define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48
465#define RMON_ALIGNMENT_ERRORS 0x49
466#define RMON_FRAGMENTS 0x4A
467#define RMON_JABBERS 0x4B
468#define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C
469#define RMON_UNICAST_FRAMES_RCVD_OK 0x4D
470#define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E
471#define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F
472#define RMON_IN_RANGE_LENGTH_ERRORS 0x50
473#define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51
474#define RMON_VLAN_FRAMES_RCVD 0x52
475#define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53
476#define RMON_MAC_CTRL_FRAMES_RCVD 0x54
477#define RMON_OCTETS_RCVD_OK 0x55
478#define RMON_OCTETS_RCVD_OK_HI 0x56
479#define RMON_OCTETS_RCVD_OTHER 0x57
480#define RMON_OCTETS_RCVD_OTHER_HI 0x58
481
482#endif /* __ETHER00_H */
diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h
deleted file mode 100644
index 5c91dd6d7822..000000000000
--- a/include/asm-arm/arch-epxa10db/excalibur.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/* megafunction wizard: %ARM-Based Excalibur%
2 GENERATION: STANDARD
3 VERSION: WM1.0
4 MODULE: ARM-Based Excalibur
5 PROJECT: excalibur
6 ============================================================
7 File Name: v:\embedded\linux\bootldr\excalibur.h
8 Megafunction Name(s): ARM-Based Excalibur
9 ============================================================
10
11 ************************************************************
12 THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 ************************************************************/
14
15#ifndef EXCALIBUR_H_INCLUDED
16#define EXCALIBUR_H_INCLUDED
17
18#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
19#define EXC_DEFINE_BOOT_FROM_FLASH
20
21#define EXC_INPUT_CLK_FREQUENCY (50000000)
22#define EXC_AHB1_CLK_FREQUENCY (150000000)
23#define EXC_AHB2_CLK_FREQUENCY (75000000)
24#define EXC_SDRAM_CLK_FREQUENCY (75000000)
25
26/* Registers Block */
27#define EXC_REGISTERS_BASE (0x7fffc000)
28#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
29#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
30#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
31#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
32#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
33#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
34#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
35#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
36#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
37#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
38#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
39#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
40#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
41#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
42
43#define EXC_REGISTERS_SIZE (0x00004000)
44
45/* EBI Block(s) */
46#define EXC_EBI_BLOCK0_BASE (0x40000000)
47#define EXC_EBI_BLOCK0_SIZE (0x00400000)
48#define EXC_EBI_BLOCK0_WIDTH (8)
49#define EXC_EBI_BLOCK0_NON_CACHEABLE
50#define EXC_EBI_BLOCK1_BASE (0x40400000)
51#define EXC_EBI_BLOCK1_SIZE (0x00400000)
52#define EXC_EBI_BLOCK1_WIDTH (16)
53#define EXC_EBI_BLOCK1_NON_CACHEABLE
54#define EXC_EBI_BLOCK2_BASE (0x40800000)
55#define EXC_EBI_BLOCK2_SIZE (0x00400000)
56#define EXC_EBI_BLOCK2_WIDTH (16)
57#define EXC_EBI_BLOCK2_NON_CACHEABLE
58#define EXC_EBI_BLOCK3_BASE (0x40c00000)
59#define EXC_EBI_BLOCK3_SIZE (0x00400000)
60#define EXC_EBI_BLOCK3_WIDTH (16)
61#define EXC_EBI_BLOCK3_NON_CACHEABLE
62
63/* SDRAM Block(s) */
64#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
65#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
66#define EXC_SDRAM_BLOCK0_WIDTH (32)
67#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
68#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
69#define EXC_SDRAM_BLOCK1_WIDTH (32)
70
71/* Single Port SRAM Block(s) */
72#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
73#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
74#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
75#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
76
77/* PLD Block(s) */
78#define EXC_PLD_BLOCK0_BASE (0x80000000)
79#define EXC_PLD_BLOCK0_SIZE (0x00004000)
80#define EXC_PLD_BLOCK0_NON_CACHEABLE
81#define EXC_PLD_BLOCK1_BASE (0xf000000)
82#define EXC_PLD_BLOCK1_SIZE (0x00004000)
83#define EXC_PLD_BLOCK1_NON_CACHEABLE
84#define EXC_PLD_BLOCK2_BASE (0x80008000)
85#define EXC_PLD_BLOCK2_SIZE (0x00004000)
86#define EXC_PLD_BLOCK2_NON_CACHEABLE
87#define EXC_PLD_BLOCK3_BASE (0x8000c000)
88#define EXC_PLD_BLOCK3_SIZE (0x00004000)
89#define EXC_PLD_BLOCK3_NON_CACHEABLE
90
91#endif
diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h
deleted file mode 100644
index b992c2924a77..000000000000
--- a/include/asm-arm/arch-epxa10db/hardware.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10/hardware.h
3 *
4 * This file contains the hardware definitions of the Integrator.
5 *
6 * Copyright (C) 1999 ARM Limited.
7 * Copyright (C) 2001 Altera Corporation
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_ARCH_HARDWARE_H
24#define __ASM_ARCH_HARDWARE_H
25
26#include <asm/arch/platform.h>
27
28/*
29 * Where in virtual memory the IO devices (timers, system controllers
30 * and so on)
31 */
32#define IO_BASE 0xf0000000 // VA of IO
33#define IO_SIZE 0x10000000 // How much?
34#define IO_START EXC_REGISTERS_BASE // PA of IO
35/* macro to get at IO space when running virtually */
36#define IO_ADDRESS(x) ((x) | 0xf0000000)
37
38#define FLASH_VBASE 0xFE000000
39#define FLASH_SIZE 0x01000000
40#define FLASH_START EXC_EBI_BLOCK0_BASE
41#define FLASH_VADDR(x) ((x)|0xFE000000)
42/*
43 * Similar to above, but for PCI addresses (memory, IO, Config and the
44 * V3 chip itself). WARNING: this has to mirror definitions in platform.h
45 */
46#if 0
47#define PCI_MEMORY_VADDR 0xe8000000
48#define PCI_CONFIG_VADDR 0xec000000
49#define PCI_V3_VADDR 0xed000000
50#define PCI_IO_VADDR 0xee000000
51
52#define PCIO_BASE PCI_IO_VADDR
53#define PCIMEM_BASE PCI_MEMORY_VADDR
54
55
56#define pcibios_assign_all_busses() 1
57
58#define PCIBIOS_MIN_IO 0x6000
59#define PCIBIOS_MIN_MEM 0x00100000
60#endif
61
62
63#endif
64
diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h
deleted file mode 100644
index 23ec864c40bb..000000000000
--- a/include/asm-arm/arch-epxa10db/int_ctrl00.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 *
3 * This file contains the register definitions for the Excalibur
4 * Timer TIMER00.
5 *
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __INT_CTRL00_H
24#define __INT_CTRL00_H
25
26#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 ))
27#define INT_MS_FC_MSK (0x10000)
28#define INT_MS_FC_OFST (16)
29#define INT_MS_M1_MSK (0x8000)
30#define INT_MS_M1_OFST (15)
31#define INT_MS_M0_MSK (0x4000)
32#define INT_MS_M0_OFST (14)
33#define INT_MS_AE_MSK (0x2000)
34#define INT_MS_AE_OFST (13)
35#define INT_MS_PE_MSK (0x1000)
36#define INT_MS_PE_OFST (12)
37#define INT_MS_EE_MSK (0x0800)
38#define INT_MS_EE_OFST (11)
39#define INT_MS_PS_MSK (0x0400)
40#define INT_MS_PS_OFST (10)
41#define INT_MS_T1_MSK (0x0200)
42#define INT_MS_T1_OFST (9)
43#define INT_MS_T0_MSK (0x0100)
44#define INT_MS_T0_OFST (8)
45#define INT_MS_UA_MSK (0x0080)
46#define INT_MS_UA_OFST (7)
47#define INT_MS_IP_MSK (0x0040)
48#define INT_MS_IP_OFST (6)
49#define INT_MS_P5_MSK (0x0020)
50#define INT_MS_P5_OFST (5)
51#define INT_MS_P4_MSK (0x0010)
52#define INT_MS_P4_OFST (4)
53#define INT_MS_P3_MSK (0x0008)
54#define INT_MS_P3_OFST (3)
55#define INT_MS_P2_MSK (0x0004)
56#define INT_MS_P2_OFST (2)
57#define INT_MS_P1_MSK (0x0002)
58#define INT_MS_P1_OFST (1)
59#define INT_MS_P0_MSK (0x0001)
60#define INT_MS_P0_OFST (0)
61
62#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 ))
63#define INT_MC_FC_MSK (0x10000)
64#define INT_MC_FC_OFST (16)
65#define INT_MC_M1_MSK (0x8000)
66#define INT_MC_M1_OFST (15)
67#define INT_MC_M0_MSK (0x4000)
68#define INT_MC_M0_OFST (14)
69#define INT_MC_AE_MSK (0x2000)
70#define INT_MC_AE_OFST (13)
71#define INT_MC_PE_MSK (0x1000)
72#define INT_MC_PE_OFST (12)
73#define INT_MC_EE_MSK (0x0800)
74#define INT_MC_EE_OFST (11)
75#define INT_MC_PS_MSK (0x0400)
76#define INT_MC_PS_OFST (10)
77#define INT_MC_T1_MSK (0x0200)
78#define INT_MC_T1_OFST (9)
79#define INT_MC_T0_MSK (0x0100)
80#define INT_MC_T0_OFST (8)
81#define INT_MC_UA_MSK (0x0080)
82#define INT_MC_UA_OFST (7)
83#define INT_MC_IP_MSK (0x0040)
84#define INT_MC_IP_OFST (6)
85#define INT_MC_P5_MSK (0x0020)
86#define INT_MC_P5_OFST (5)
87#define INT_MC_P4_MSK (0x0010)
88#define INT_MC_P4_OFST (4)
89#define INT_MC_P3_MSK (0x0008)
90#define INT_MC_P3_OFST (3)
91#define INT_MC_P2_MSK (0x0004)
92#define INT_MC_P2_OFST (2)
93#define INT_MC_P1_MSK (0x0002)
94#define INT_MC_P1_OFST (1)
95#define INT_MC_P0_MSK (0x0001)
96#define INT_MC_P0_OFST (0)
97
98#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 ))
99#define INT_SS_FC_SSK (0x8000)
100#define INT_SS_FC_OFST (15)
101#define INT_SS_M1_SSK (0x8000)
102#define INT_SS_M1_OFST (15)
103#define INT_SS_M0_SSK (0x4000)
104#define INT_SS_M0_OFST (14)
105#define INT_SS_AE_SSK (0x2000)
106#define INT_SS_AE_OFST (13)
107#define INT_SS_PE_SSK (0x1000)
108#define INT_SS_PE_OFST (12)
109#define INT_SS_EE_SSK (0x0800)
110#define INT_SS_EE_OFST (11)
111#define INT_SS_PS_SSK (0x0400)
112#define INT_SS_PS_OFST (10)
113#define INT_SS_T1_SSK (0x0200)
114#define INT_SS_T1_OFST (9)
115#define INT_SS_T0_SSK (0x0100)
116#define INT_SS_T0_OFST (8)
117#define INT_SS_UA_SSK (0x0080)
118#define INT_SS_UA_OFST (7)
119#define INT_SS_IP_SSK (0x0040)
120#define INT_SS_IP_OFST (6)
121#define INT_SS_P5_SSK (0x0020)
122#define INT_SS_P5_OFST (5)
123#define INT_SS_P4_SSK (0x0010)
124#define INT_SS_P4_OFST (4)
125#define INT_SS_P3_SSK (0x0008)
126#define INT_SS_P3_OFST (3)
127#define INT_SS_P2_SSK (0x0004)
128#define INT_SS_P2_OFST (2)
129#define INT_SS_P1_SSK (0x0002)
130#define INT_SS_P1_OFST (1)
131#define INT_SS_P0_SSK (0x0001)
132#define INT_SS_P0_OFST (0)
133
134#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C ))
135#define INT_RS_FC_RSK (0x10000)
136#define INT_RS_FC_OFST (16)
137#define INT_RS_M1_RSK (0x8000)
138#define INT_RS_M1_OFST (15)
139#define INT_RS_M0_RSK (0x4000)
140#define INT_RS_M0_OFST (14)
141#define INT_RS_AE_RSK (0x2000)
142#define INT_RS_AE_OFST (13)
143#define INT_RS_PE_RSK (0x1000)
144#define INT_RS_PE_OFST (12)
145#define INT_RS_EE_RSK (0x0800)
146#define INT_RS_EE_OFST (11)
147#define INT_RS_PS_RSK (0x0400)
148#define INT_RS_PS_OFST (10)
149#define INT_RS_T1_RSK (0x0200)
150#define INT_RS_T1_OFST (9)
151#define INT_RS_T0_RSK (0x0100)
152#define INT_RS_T0_OFST (8)
153#define INT_RS_UA_RSK (0x0080)
154#define INT_RS_UA_OFST (7)
155#define INT_RS_IP_RSK (0x0040)
156#define INT_RS_IP_OFST (6)
157#define INT_RS_P5_RSK (0x0020)
158#define INT_RS_P5_OFST (5)
159#define INT_RS_P4_RSK (0x0010)
160#define INT_RS_P4_OFST (4)
161#define INT_RS_P3_RSK (0x0008)
162#define INT_RS_P3_OFST (3)
163#define INT_RS_P2_RSK (0x0004)
164#define INT_RS_P2_OFST (2)
165#define INT_RS_P1_RSK (0x0002)
166#define INT_RS_P1_OFST (1)
167#define INT_RS_P0_RSK (0x0001)
168#define INT_RS_P0_OFST (0)
169
170#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 ))
171#define INT_ID_ID_MSK (0x3F)
172#define INT_ID_ID_OFST (0)
173
174#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 ))
175#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
176#define INT_PLD_PRIORITY_PRI_OFST (0)
177#define INT_PLD_PRIORITY_GA_MSK (0x40)
178#define INT_PLD_PRIORITY_GA_OFST (6)
179
180#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 ))
181#define INT_MODE_MODE_MSK (0x3)
182#define INT_MODE_MODE_OFST (0)
183
184#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 ))
185#define INT_PRIORITY_P0_PRI_MSK (0x3F)
186#define INT_PRIORITY_P0_PRI_OFST (0)
187#define INT_PRIORITY_P0_FQ_MSK (0x40)
188#define INT_PRIORITY_P0_FQ_OFST (6)
189
190#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 ))
191#define INT_PRIORITY_P1_PRI_MSK (0x3F)
192#define INT_PRIORITY_P1_PRI_OFST (0)
193#define INT_PRIORITY_P1_FQ_MSK (0x40)
194#define INT_PRIORITY_P1_FQ_OFST (6)
195
196#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 ))
197#define INT_PRIORITY_P2_PRI_MSK (0x3F)
198#define INT_PRIORITY_P2_PRI_OFST (0)
199#define INT_PRIORITY_P2_FQ_MSK (0x40)
200#define INT_PRIORITY_P2_FQ_OFST (6)
201
202#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C ))
203#define INT_PRIORITY_P3_PRI_MSK (0x3F)
204#define INT_PRIORITY_P3_PRI_OFST (0)
205#define INT_PRIORITY_P3_FQ_MSK (0x40)
206#define INT_PRIORITY_P3_FQ_OFST (6)
207
208#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 ))
209#define INT_PRIORITY_P4_PRI_MSK (0x3F)
210#define INT_PRIORITY_P4_PRI_OFST (0)
211#define INT_PRIORITY_P4_FQ_MSK (0x40)
212#define INT_PRIORITY_P4_FQ_OFST (6)
213
214#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
215#define INT_PRIORITY_P5_PRI_MSK (0x3F)
216#define INT_PRIORITY_P5_PRI_OFST (0)
217#define INT_PRIORITY_P5_FQ_MSK (0x40)
218#define INT_PRIORITY_P5_FQ_OFST (6)
219
220#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
221#define INT_PRIORITY_IP_PRI_MSK (0x3F)
222#define INT_PRIORITY_IP_PRI_OFST (0)
223#define INT_PRIORITY_IP_FQ_MSK (0x40)
224#define INT_PRIORITY_IP_FQ_OFST (6)
225
226#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C ))
227#define INT_PRIORITY_UA_PRI_MSK (0x3F)
228#define INT_PRIORITY_UA_PRI_OFST (0)
229#define INT_PRIORITY_UA_FQ_MSK (0x40)
230#define INT_PRIORITY_UA_FQ_OFST (6)
231
232#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 ))
233#define INT_PRIORITY_T0_PRI_MSK (0x3F)
234#define INT_PRIORITY_T0_PRI_OFST (0)
235#define INT_PRIORITY_T0_FQ_MSK (0x40)
236#define INT_PRIORITY_T0_FQ_OFST (6)
237
238#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 ))
239#define INT_PRIORITY_T1_PRI_MSK (0x3F)
240#define INT_PRIORITY_T1_PRI_OFST (0)
241#define INT_PRIORITY_T1_FQ_MSK (0x40)
242#define INT_PRIORITY_T1_FQ_OFST (6)
243
244#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 ))
245#define INT_PRIORITY_PS_PRI_MSK (0x3F)
246#define INT_PRIORITY_PS_PRI_OFST (0)
247#define INT_PRIORITY_PS_FQ_MSK (0x40)
248#define INT_PRIORITY_PS_FQ_OFST (6)
249
250#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC ))
251#define INT_PRIORITY_EE_PRI_MSK (0x3F)
252#define INT_PRIORITY_EE_PRI_OFST (0)
253#define INT_PRIORITY_EE_FQ_MSK (0x40)
254#define INT_PRIORITY_EE_FQ_OFST (6)
255
256#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 ))
257#define INT_PRIORITY_PE_PRI_MSK (0x3F)
258#define INT_PRIORITY_PE_PRI_OFST (0)
259#define INT_PRIORITY_PE_FQ_MSK (0x40)
260#define INT_PRIORITY_PE_FQ_OFST (6)
261
262#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 ))
263#define INT_PRIORITY_AE_PRI_MSK (0x3F)
264#define INT_PRIORITY_AE_PRI_OFST (0)
265#define INT_PRIORITY_AE_FQ_MSK (0x40)
266#define INT_PRIORITY_AE_FQ_OFST (6)
267
268#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 ))
269#define INT_PRIORITY_M0_PRI_MSK (0x3F)
270#define INT_PRIORITY_M0_PRI_OFST (0)
271#define INT_PRIORITY_M0_FQ_MSK (0x40)
272#define INT_PRIORITY_M0_FQ_OFST (6)
273
274#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC ))
275#define INT_PRIORITY_M1_PRI_MSK (0x3F)
276#define INT_PRIORITY_M1_PRI_OFST (0)
277#define INT_PRIORITY_M1_FQ_MSK (0x40)
278#define INT_PRIORITY_M1_FQ_OFST (6)
279
280#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 ))
281#define INT_PRIORITY_FC_PRI_MSK (0x3F)
282#define INT_PRIORITY_FC_PRI_OFST (0)
283#define INT_PRIORITY_FC_FQ_MSK (0x40)
284#define INT_PRIORITY_FC_FQ_OFST (6)
285
286#endif /* __INT_CTRL00_H */
287
288
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
deleted file mode 100644
index 9fe100c9d6be..000000000000
--- a/include/asm-arm/arch-epxa10db/io.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/io.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#include <asm/hardware.h>
24
25#define IO_SPACE_LIMIT 0xffff
26
27
28/*
29 * Generic virtual read/write
30 */
31/*#define outsw __arch_writesw
32#define outsl __arch_writesl
33#define outsb __arch_writesb
34#define insb __arch_readsb
35#define insw __arch_readsw
36#define insl __arch_readsl*/
37
38#define __io(a) ((void __iomem *)(a))
39#define __mem_pci(a) (a)
40
41#endif
diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h
deleted file mode 100644
index c3758a3b5d9d..000000000000
--- a/include/asm-arm/arch-epxa10db/irqs.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-camelot/irqs.h
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* Use the Excalibur chip definitions */
22#define INT_CTRL00_TYPE
23#include "asm/arch/int_ctrl00.h"
24
25
26#define IRQ_PLD0 INT_MS_P0_OFST
27#define IRQ_PLD1 INT_MS_P1_OFST
28#define IRQ_PLD2 INT_MS_P2_OFST
29#define IRQ_PLD3 INT_MS_P3_OFST
30#define IRQ_PLD4 INT_MS_P4_OFST
31#define IRQ_PLD5 INT_MS_P5_OFST
32#define IRQ_EXT INT_MS_IP_OFST
33#define IRQ_UART INT_MS_UA_OFST
34#define IRQ_TIMER0 INT_MS_T0_OFST
35#define IRQ_TIMER1 INT_MS_T1_OFST
36#define IRQ_PLL INT_MS_PLL_OFST
37#define IRQ_EBI INT_MS_EBI_OFST
38#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST
39#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST
40#define IRQ_COMMRX INT_MS_CR_OFST
41#define IRQ_COMMTX INT_MS_CT_OFST
42#define IRQ_FAST_COMM INT_MS_FC_OFST
43
44#define NR_IRQS (INT_MS_FC_OFST + 1)
45
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
deleted file mode 100644
index 999541b6a9f5..000000000000
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10/memory.h
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PHYS_OFFSET UL(0x00000000)
27
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 */
35#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
36#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
37
38#endif
diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h
deleted file mode 100644
index d8a7efa12e19..000000000000
--- a/include/asm-arm/arch-epxa10db/mode_ctrl00.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef __MODE_CTRL00_H
2#define __MODE_CTRL00_H
3
4/*
5 * Register definitions for the reset and mode control
6 */
7
8/*
9 * Copyright (C) 2001 Altera Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26
27
28#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR ))
29#define BOOT_CR_BF_MSK (0x1)
30#define BOOT_CR_BF_OFST (0)
31#define BOOT_CR_HM_MSK (0x2)
32#define BOOT_CR_HM_OFST (1)
33#define BOOT_CR_RE_MSK (0x4)
34#define BOOT_CR_RE_OFST (2)
35
36#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 ))
37#define RESET_SR_WR_MSK (0x1)
38#define RESET_SR_WR_OFST (0)
39#define RESET_SR_CR_MSK (0x2)
40#define RESET_SR_CR_OFST (1)
41#define RESET_SR_JT_MSK (0x4)
42#define RESET_SR_JT_OFST (2)
43#define RESET_SR_ER_MSK (0x8)
44#define RESET_SR_ER_OFST (3)
45
46#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 ))
47
48#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 ))
49#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
50#define SRAM0_SR_SIZE_OFST (12)
51
52#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 ))
53#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
54#define SRAM1_SR_SIZE_OFST (12)
55
56#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 ))
57
58#define DPSRAM0_SR_MODE_MSK (0xF)
59#define DPSRAM0_SR_MODE_OFST (0)
60#define DPSRAM0_SR_GLBL_MSK (0x30)
61#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
62#define DPSRAM0_SR_SIZE_OFST (12)
63
64#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 ))
65#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
66#define DPSRAM0_LCR_LCKADDR_OFST (4)
67
68#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 ))
69#define DPSRAM1_SR_MODE_MSK (0xF)
70#define DPSRAM1_SR_MODE_OFST (0)
71#define DPSRAM1_SR_GLBL_MSK (0x30)
72#define DPSRAM1_SR_GLBL_OFST (4)
73#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
74#define DPSRAM1_SR_SIZE_OFST (12)
75
76#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C ))
77#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
78#define DPSRAM1_LCR_LCKADDR_OFST (4)
79
80#endif /* __MODE_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-epxa10db/param.h
deleted file mode 100644
index 783dedd71c8f..000000000000
--- a/include/asm-arm/arch-epxa10db/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h
deleted file mode 100644
index 129bb0f212a0..000000000000
--- a/include/asm-arm/arch-epxa10db/platform.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef PLATFORM_H
2#define PLATFORM_H
3#include "excalibur.h"
4
5#define MAXIRQNUM 15
6#endif
7
diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h
deleted file mode 100644
index 7af2c38dacc6..000000000000
--- a/include/asm-arm/arch-epxa10db/pld_conf00.h
+++ /dev/null
@@ -1,73 +0,0 @@
1#ifndef __PLD_CONF00_H
2#define __PLD_CONF00_H
3
4/*
5 * Register definitions for the PLD Configuration Logic
6 */
7
8/*
9 *
10 * This file contains the register definitions for the Excalibur
11 * Interrupt controller INT_CTRL00.
12 *
13 * Copyright (C) 2001 Altera Corporation
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))
31#define CONFIG_CONTROL_LK_MSK (0x1)
32#define CONFIG_CONTROL_LK_OFST (0)
33#define CONFIG_CONTROL_CO_MSK (0x2)
34#define CONFIG_CONTROL_CO_OFST (1)
35#define CONFIG_CONTROL_B_MSK (0x4)
36#define CONFIG_CONTROL_B_OFST (2)
37#define CONFIG_CONTROL_PC_MSK (0x8)
38#define CONFIG_CONTROL_PC_OFST (3)
39#define CONFIG_CONTROL_E_MSK (0x10)
40#define CONFIG_CONTROL_E_OFST (4)
41#define CONFIG_CONTROL_ES_MSK (0xE0)
42#define CONFIG_CONTROL_ES_OFST (5)
43#define CONFIG_CONTROL_ES_0_MSK (0x20)
44#define CONFIG_CONTROL_ES_1_MSK (0x40)
45#define CONFIG_CONTROL_ES_2_MSK (0x80)
46
47#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 ))
48#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
49#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
50
51#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 ))
52#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
53#define CONFIG_CONTROL_DATA_OFST (0)
54
55#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC ))
56#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
57#define CONFIG_UNLOCK_OFST (0)
58
59#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
60
61#endif /* __PLD_CONF00_H */
62
63
64
65
66
67
68
69
70
71
72
73
diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-epxa10db/system.h
deleted file mode 100644
index 345b092a1ed5..000000000000
--- a/include/asm-arm/arch-epxa10db/system.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/system.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __ASM_ARCH_SYSTEM_H
23#define __ASM_ARCH_SYSTEM_H
24
25#include <asm/arch/platform.h>
26
27static inline void arch_idle(void)
28{
29 /*
30 * This should do all the clock switching
31 * and wait for interrupt tricks
32 */
33 cpu_do_idle();
34}
35
36extern __inline__ void arch_reset(char mode)
37{
38 /* Hmm... We can probably do something with the watchdog... */
39}
40
41#endif
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h
deleted file mode 100644
index 5e107bd4e109..000000000000
--- a/include/asm-arm/arch-epxa10db/tdkphy.h
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * linux/drivers/tdkphy.h
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __TDKPHY_H
22#define __TDKPHY_H
23
24/*
25 * Register definitions for the TDK 78Q2120 PHY
26 * which is on the Camelot board
27 */
28
29/*
30 * Copyright (c) Altera Corporation 2000.
31 * All rights reserved.
32 */
33#define PHY_CONTROL (0)
34#define PHY_CONTROL_COLT_MSK (0x80)
35#define PHY_CONTROL_COLT_OFST (7)
36#define PHY_CONTROL_DUPLEX_MSK (0x100)
37#define PHY_CONTROL_DUPLEX_OFST (8)
38#define PHY_CONTROL_RANEG_MSK (0x200)
39#define PHY_CONTROL_RANEG_OFST (9)
40#define PHY_CONTROL_ISO_MSK (0x400)
41#define PHY_CONTROL_ISO_OFST (10)
42#define PHY_CONTROL_PWRDN_MSK (0x800)
43#define PHY_CONTROL_PWRDN_OFST (11)
44#define PHY_CONTROL_ANEGEN_MSK (0x1000)
45#define PHY_CONTROL_ANEGEN_OFST (12)
46#define PHY_CONTROL_SPEEDSL_MSK (0x2000)
47#define PHY_CONTROL_SPEEDSL_OFST (13)
48#define PHY_CONTROL_LOOPBK_MSK (0x4000)
49#define PHY_CONTROL_LOOPBK_OFST (14)
50#define PHY_CONTROL_RESET_MSK (0x8000)
51#define PHY_CONTROL_RESET_OFST (15)
52
53#define PHY_STATUS (1)
54#define PHY_STATUS_ETXD_MSK (0x1)
55#define PHY_STATUS_EXTD_OFST (0)
56#define PHY_STATUS_JAB_MSK (0x2)
57#define PHY_STATUS_JAB_OFST (1)
58#define PHY_STATUS_LINK_MSK (0x4)
59#define PHY_STATUS_LINK_OFST (2)
60#define PHY_STATUS_ANEGA_MSK (0x8)
61#define PHY_STATUS_ANEGA_OFST (3)
62#define PHY_STATUS_RFAULT_MSK (0x10)
63#define PHY_STATUS_RFAULT_OFST (4)
64#define PHY_STATUS_ANEGC_MSK (0x20)
65#define PHY_STATUS_ANEGC_OFST (5)
66#define PHY_STATUS_10T_H_MSK (0x800)
67#define PHY_STATUS_10T_H_OFST (11)
68#define PHY_STATUS_10T_F_MSK (0x1000)
69#define PHY_STATUS_10T_F_OFST (12)
70#define PHY_STATUS_100_X_H_MSK (0x2000)
71#define PHY_STATUS_100_X_H_OFST (13)
72#define PHY_STATUS_100_X_F_MSK (0x4000)
73#define PHY_STATUS_100_X_F_OFST (14)
74#define PHY_STATUS_100T4_MSK (0x8000)
75#define PHY_STATUS_100T4_OFST (15)
76
77#define PHY_ID1 (2)
78#define PHY_ID1_OUI_MSK (0xFFFF)
79#define PHY_ID1_OUI_OFST (0)
80
81#define PHY_ID2 (3)
82#define PHY_ID2_RN_MSK (0xF)
83#define PHY_ID2_RN_OFST (0)
84#define PHY_ID2_MN_MSK (0x3F0)
85#define PHY_ID2_MN_OFST (4)
86#define PHY_ID2_OUI_MSK (0xFC00)
87#define PHY_ID2_OUI_OFST (10)
88
89#define PHY_AUTO_NEG_ADVERTISEMENT (4)
90#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F)
91#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0)
92#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20)
93#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5)
94#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40)
95#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6)
96#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80)
97#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7)
98#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100)
99#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8)
100#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200)
101#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9)
102#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0)
103#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5)
104#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000)
105#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13)
106#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000)
107#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14)
108#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000)
109#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15)
110
111#define PHY_AUTO_NEG_LINK_PARTNER (5)
112#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F)
113#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0)
114#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0)
115#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5)
116#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000)
117#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13)
118#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000)
119#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14)
120#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000)
121#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15)
122
123#define PHY_AUTO_NEG_EXPANSION (6)
124#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1)
125#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0)
126#define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2)
127#define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1)
128#define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4)
129#define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2)
130#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8)
131#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3)
132#define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10)
133#define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4)
134
135#define PHY_VENDOR_SPECIFIC (16)
136#define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1)
137#define PHY_VENDOR_SPECIFIC_RXCC_OFST (0)
138#define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2)
139#define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1)
140#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10)
141#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4)
142#define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20)
143#define PHY_VENDOR_SPECIFIC_APOL_OFST (5)
144#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40)
145#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6)
146#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80)
147#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7)
148#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100)
149#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8)
150#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200)
151#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9)
152#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400)
153#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10)
154#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800)
155#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11)
156#define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000)
157#define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12)
158#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000)
159#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14)
160#define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000)
161#define PHY_VENDOR_SPECIFIC_RPTR_OFST (15)
162
163#define PHY_IRQ_CONTROL (17)
164#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1)
165#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0)
166#define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2)
167#define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1)
168#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4)
169#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2)
170#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8)
171#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3)
172#define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10)
173#define PHY_IRQ_CONTROL_PDF_INT_OFST (4)
174#define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20)
175#define PHY_IRQ_CONTROL_PRX_INT_OFST (5)
176#define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40)
177#define PHY_IRQ_CONTROL_RXER_INT_OFST (6)
178#define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80)
179#define PHY_IRQ_CONTROL_JABBER_INT_OFST (7)
180#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100)
181#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8)
182#define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200)
183#define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9)
184#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400)
185#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10)
186#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800)
187#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11)
188#define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000)
189#define PHY_IRQ_CONTROL_PDF_IE_OFST (12)
190#define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000)
191#define PHY_IRQ_CONTROL_PRX_IE_OFST (13)
192#define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000)
193#define PHY_IRQ_CONTROL_RXER_IE_OFST (14)
194#define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000)
195#define PHY_IRQ_CONTROL_JABBER_IE_OFST (15)
196
197#define PHY_DIAGNOSTIC (18)
198#define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100)
199#define PHY_DIAGNOSTIC_RX_LOCK_OFST (8)
200#define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200)
201#define PHY_DIAGNOSTIC_RX_PASS_OFST (9)
202#define PHY_DIAGNOSTIC_RATE_MSK (0x400)
203#define PHY_DIAGNOSTIC_RATE_OFST (10)
204#define PHY_DIAGNOSTIC_DPLX_MSK (0x800)
205#define PHY_DIAGNOSTIC_DPLX_OFST (11)
206#define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000)
207#define PHY_DIAGNOSTIC_ANEGF_OFST (12)
208
209#endif /* __TDKPHY_H */
diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h
deleted file mode 100644
index 52a3fb58b59d..000000000000
--- a/include/asm-arm/arch-epxa10db/timer00.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 *
3 * This file contains the register definitions for the Excalibur
4 * Timer TIMER00.
5 *
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#ifndef __TIMER00_H
23#define __TIMER00_H
24
25/*
26 * Register definitions for the timers
27 */
28
29
30#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
31#define TIMER0_CR_B_MSK (0x20)
32#define TIMER0_CR_B_OFST (0x5)
33#define TIMER0_CR_S_MSK (0x10)
34#define TIMER0_CR_S_OFST (0x4)
35#define TIMER0_CR_CI_MSK (0x08)
36#define TIMER0_CR_CI_OFST (0x3)
37#define TIMER0_CR_IE_MSK (0x04)
38#define TIMER0_CR_IE_OFST (0x2)
39#define TIMER0_CR_MODE_MSK (0x3)
40#define TIMER0_CR_MODE_OFST (0)
41#define TIMER0_CR_MODE_FREE (0)
42#define TIMER0_CR_MODE_ONE (1)
43#define TIMER0_CR_MODE_INTVL (2)
44
45#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
46#define TIMER0_SR_B_MSK (0x20)
47#define TIMER0_SR_B_OFST (0x5)
48#define TIMER0_SR_S_MSK (0x10)
49#define TIMER0_SR_S_OFST (0x4)
50#define TIMER0_SR_CI_MSK (0x08)
51#define TIMER0_SR_CI_OFST (0x3)
52#define TIMER0_SR_IE_MSK (0x04)
53#define TIMER0_SR_IE_OFST (0x2)
54#define TIMER0_SR_MODE_MSK (0x3)
55#define TIMER0_SR_MODE_OFST (0)
56#define TIMER0_SR_MODE_FREE (0)
57#define TIMER0_SR_MODE_ONE (1)
58#define TIMER0_SR_MODE_INTVL (2)
59
60#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 ))
61#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 ))
62#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 ))
63
64#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
65#define TIMER1_CR_B_MSK (0x20)
66#define TIMER1_CR_B_OFST (0x5)
67#define TIMER1_CR_S_MSK (0x10)
68#define TIMER1_CR_S_OFST (0x4)
69#define TIMER1_CR_CI_MSK (0x08)
70#define TIMER1_CR_CI_OFST (0x3)
71#define TIMER1_CR_IE_MSK (0x04)
72#define TIMER1_CR_IE_OFST (0x2)
73#define TIMER1_CR_MODE_MSK (0x3)
74#define TIMER1_CR_MODE_OFST (0)
75#define TIMER1_CR_MODE_FREE (0)
76#define TIMER1_CR_MODE_ONE (1)
77#define TIMER1_CR_MODE_INTVL (2)
78
79#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
80#define TIMER1_SR_B_MSK (0x20)
81#define TIMER1_SR_B_OFST (0x5)
82#define TIMER1_SR_S_MSK (0x10)
83#define TIMER1_SR_S_OFST (0x4)
84#define TIMER1_SR_CI_MSK (0x08)
85#define TIMER1_SR_CI_OFST (0x3)
86#define TIMER1_SR_IE_MSK (0x04)
87#define TIMER1_SR_IE_OFST (0x2)
88#define TIMER1_SR_MODE_MSK (0x3)
89#define TIMER1_SR_MODE_OFST (0)
90#define TIMER1_SR_MODE_FREE (0)
91#define TIMER1_SR_MODE_ONE (1)
92#define TIMER1_SR_MODE_INTVL (2)
93
94#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 ))
95#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 ))
96#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 ))
97
98#endif /* __TIMER00_H */
diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-epxa10db/timex.h
deleted file mode 100644
index b87a75fc9589..000000000000
--- a/include/asm-arm/arch-epxa10db/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/timex.h
3 *
4 * Excalibur timex specifications
5 *
6 * Copyright (C) 2001 Altera Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23/*
24 * ??
25 */
26#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h
deleted file mode 100644
index 5abd8914d68b..000000000000
--- a/include/asm-arm/arch-epxa10db/uart00.h
+++ /dev/null
@@ -1,181 +0,0 @@
1/* *
2 * Copyright (C) 2001 Altera Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef __UART00_H
19#define __UART00_H
20
21/*
22 * Register definitions for the UART
23 */
24
25#define UART_TX_FIFO_SIZE (15)
26
27#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 ))
28#define UART_RSR_RX_LEVEL_MSK (0x1f)
29#define UART_RSR_RX_LEVEL_OFST (0)
30#define UART_RSR_RE_MSK (0x80)
31#define UART_RSR_RE_OFST (7)
32
33#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 ))
34#define UART_RDS_BI_MSK (0x8)
35#define UART_RDS_BI_OFST (4)
36#define UART_RDS_FE_MSK (0x4)
37#define UART_RDS_FE_OFST (2)
38#define UART_RDS_PE_MSK (0x2)
39#define UART_RDS_PE_OFST (1)
40#define UART_RDS_OE_MSK (0x1)
41#define UART_RDS_OE_OFST (0)
42
43#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 ))
44#define UART_RD_RX_DATA_MSK (0xff)
45#define UART_RD_RX_DATA_OFST (0)
46
47#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c ))
48#define UART_TSR_TX_LEVEL_MSK (0x1f)
49#define UART_TSR_TX_LEVEL_OFST (0)
50#define UART_TSR_TXI_MSK (0x80)
51#define UART_TSR_TXI_OFST (7)
52
53#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 ))
54#define UART_TD_TX_DATA_MSK (0xff)
55#define UART_TD_TX_DATA_OFST (0)
56
57#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 ))
58#define UART_FCR_RX_THR_MSK (0xd0)
59#define UART_FCR_RX_THR_OFST (5)
60#define UART_FCR_RX_THR_1 (0x00)
61#define UART_FCR_RX_THR_2 (0x20)
62#define UART_FCR_RX_THR_4 (0x40)
63#define UART_FCR_RX_THR_6 (0x60)
64#define UART_FCR_RX_THR_8 (0x80)
65#define UART_FCR_RX_THR_10 (0xa0)
66#define UART_FCR_RX_THR_12 (0xc0)
67#define UART_FCR_RX_THR_14 (0xd0)
68#define UART_FCR_TX_THR_MSK (0x1c)
69#define UART_FCR_TX_THR_OFST (2)
70#define UART_FCR_TX_THR_0 (0x00)
71#define UART_FCR_TX_THR_2 (0x04)
72#define UART_FCR_TX_THR_4 (0x08)
73#define UART_FCR_TX_THR_8 (0x0c)
74#define UART_FCR_TX_THR_10 (0x10)
75#define UART_FCR_TX_THR_12 (0x14)
76#define UART_FCR_TX_THR_14 (0x18)
77#define UART_FCR_TX_THR_15 (0x1c)
78#define UART_FCR_RC_MSK (0x02)
79#define UART_FCR_RC_OFST (1)
80#define UART_FCR_TC_MSK (0x01)
81#define UART_FCR_TC_OFST (0)
82
83#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 ))
84#define UART_IES_ME_MSK (0x8)
85#define UART_IES_ME_OFST (3)
86#define UART_IES_TIE_MSK (0x4)
87#define UART_IES_TIE_OFST (2)
88#define UART_IES_TE_MSK (0x2)
89#define UART_IES_TE_OFST (1)
90#define UART_IES_RE_MSK (0x1)
91#define UART_IES_RE_OFST (0)
92
93#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c ))
94#define UART_IEC_ME_MSK (0x8)
95#define UART_IEC_ME_OFST (3)
96#define UART_IEC_TIE_MSK (0x4)
97#define UART_IEC_TIE_OFST (2)
98#define UART_IEC_TE_MSK (0x2)
99#define UART_IEC_TE_OFST (1)
100#define UART_IEC_RE_MSK (0x1)
101#define UART_IEC_RE_OFST (0)
102
103#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 ))
104#define UART_ISR_MI_MSK (0x8)
105#define UART_ISR_MI_OFST (3)
106#define UART_ISR_TII_MSK (0x4)
107#define UART_ISR_TII_OFST (2)
108#define UART_ISR_TI_MSK (0x2)
109#define UART_ISR_TI_OFST (1)
110#define UART_ISR_RI_MSK (0x1)
111#define UART_ISR_RI_OFST (0)
112
113#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 ))
114#define UART_IID_IID_MSK (0x7)
115#define UART_IID_IID_OFST (0)
116
117#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 ))
118#define UART_MC_OE_MSK (0x40)
119#define UART_MC_OE_OFST (6)
120#define UART_MC_SP_MSK (0x20)
121#define UART_MC_SP_OFST (5)
122#define UART_MC_EP_MSK (0x10)
123#define UART_MC_EP_OFST (4)
124#define UART_MC_PE_MSK (0x08)
125#define UART_MC_PE_OFST (3)
126#define UART_MC_ST_MSK (0x04)
127#define UART_MC_ST_ONE (0x0)
128#define UART_MC_ST_TWO (0x04)
129#define UART_MC_ST_OFST (2)
130#define UART_MC_CLS_MSK (0x03)
131#define UART_MC_CLS_OFST (0)
132#define UART_MC_CLS_CHARLEN_5 (0)
133#define UART_MC_CLS_CHARLEN_6 (1)
134#define UART_MC_CLS_CHARLEN_7 (2)
135#define UART_MC_CLS_CHARLEN_8 (3)
136
137#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c ))
138#define UART_MCR_AC_MSK (0x80)
139#define UART_MCR_AC_OFST (7)
140#define UART_MCR_AR_MSK (0x40)
141#define UART_MCR_AR_OFST (6)
142#define UART_MCR_BR_MSK (0x20)
143#define UART_MCR_BR_OFST (5)
144#define UART_MCR_LB_MSK (0x10)
145#define UART_MCR_LB_OFST (4)
146#define UART_MCR_DCD_MSK (0x08)
147#define UART_MCR_DCD_OFST (3)
148#define UART_MCR_RI_MSK (0x04)
149#define UART_MCR_RI_OFST (2)
150#define UART_MCR_DTR_MSK (0x02)
151#define UART_MCR_DTR_OFST (1)
152#define UART_MCR_RTS_MSK (0x01)
153#define UART_MCR_RTS_OFST (0)
154
155#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 ))
156#define UART_MSR_DCD_MSK (0x80)
157#define UART_MSR_DCD_OFST (7)
158#define UART_MSR_RI_MSK (0x40)
159#define UART_MSR_RI_OFST (6)
160#define UART_MSR_DSR_MSK (0x20)
161#define UART_MSR_DSR_OFST (5)
162#define UART_MSR_CTS_MSK (0x10)
163#define UART_MSR_CTS_OFST (4)
164#define UART_MSR_DDCD_MSK (0x08)
165#define UART_MSR_DDCD_OFST (3)
166#define UART_MSR_TERI_MSK (0x04)
167#define UART_MSR_TERI_OFST (2)
168#define UART_MSR_DDSR_MSK (0x02)
169#define UART_MSR_DDSR_OFST (1)
170#define UART_MSR_DCTS_MSK (0x01)
171#define UART_MSR_DCTS_OFST (0)
172
173#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 ))
174#define UART_DIV_LO_DIV_MSK (0xff)
175#define UART_DIV_LO_DIV_OFST (0)
176
177#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 ))
178#define UART_DIV_HI_DIV_MSK (0xff)
179#define UART_DIV_HI_DIV_OFST (0)
180
181#endif /* __UART00_H */
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h
deleted file mode 100644
index fdfe0e6848f8..000000000000
--- a/include/asm-arm/arch-epxa10db/uncompress.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2001 Altera Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include "asm/arch/platform.h"
22#include "asm/hardware.h"
23#define UART00_TYPE (volatile unsigned int*)
24#include "asm/arch/uart00.h"
25
26/*
27 * This does not append a newline
28 */
29static void putstr(const char *s)
30{
31 while (*s) {
32 while ((*UART_TSR(EXC_UART00_BASE) &
33 UART_TSR_TX_LEVEL_MSK)==15)
34 barrier();
35
36 *UART_TD(EXC_UART00_BASE) = *s;
37
38 if (*s == '\n') {
39 while ((*UART_TSR(EXC_UART00_BASE) &
40 UART_TSR_TX_LEVEL_MSK)==15)
41 barrier();
42
43 *UART_TD(EXC_UART00_BASE) = '\r';
44 }
45 s++;
46 }
47}
48
49/*
50 * nothing to do
51 */
52#define arch_decomp_setup()
53
54#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h
deleted file mode 100644
index 546fb7d2b6ad..000000000000
--- a/include/asm-arm/arch-epxa10db/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-epxa10db/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 17:52:03 -0500