diff options
-rw-r--r-- | drivers/net/tg3.c | 41 | ||||
-rw-r--r-- | drivers/net/tg3.h | 1 |
2 files changed, 24 insertions, 18 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 80fbb183f755..8411e0f4cb69 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -366,6 +366,12 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val) | |||
366 | } | 366 | } |
367 | } | 367 | } |
368 | 368 | ||
369 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) | ||
370 | { | ||
371 | tp->write32_mbox(tp, off, val); | ||
372 | tp->read32_mbox(tp, off); | ||
373 | } | ||
374 | |||
369 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) | 375 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
370 | { | 376 | { |
371 | void __iomem *mbox = tp->regs + off; | 377 | void __iomem *mbox = tp->regs + off; |
@@ -387,8 +393,10 @@ static u32 tg3_read32(struct tg3 *tp, u32 off) | |||
387 | } | 393 | } |
388 | 394 | ||
389 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) | 395 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
396 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) | ||
390 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) | 397 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
391 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | 398 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) |
399 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | ||
392 | 400 | ||
393 | #define tw32(reg,val) tp->write32(tp, reg, val) | 401 | #define tw32(reg,val) tp->write32(tp, reg, val) |
394 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val)) | 402 | #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val)) |
@@ -420,8 +428,7 @@ static void tg3_disable_ints(struct tg3 *tp) | |||
420 | { | 428 | { |
421 | tw32(TG3PCI_MISC_HOST_CTRL, | 429 | tw32(TG3PCI_MISC_HOST_CTRL, |
422 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | 430 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); |
423 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | 431 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
424 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
425 | } | 432 | } |
426 | 433 | ||
427 | static inline void tg3_cond_int(struct tg3 *tp) | 434 | static inline void tg3_cond_int(struct tg3 *tp) |
@@ -437,9 +444,8 @@ static void tg3_enable_ints(struct tg3 *tp) | |||
437 | 444 | ||
438 | tw32(TG3PCI_MISC_HOST_CTRL, | 445 | tw32(TG3PCI_MISC_HOST_CTRL, |
439 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | 446 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); |
440 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 447 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
441 | (tp->last_tag << 24)); | 448 | (tp->last_tag << 24)); |
442 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
443 | tg3_cond_int(tp); | 449 | tg3_cond_int(tp); |
444 | } | 450 | } |
445 | 451 | ||
@@ -3276,9 +3282,8 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
3276 | /* No work, shared interrupt perhaps? re-enable | 3282 | /* No work, shared interrupt perhaps? re-enable |
3277 | * interrupts, and flush that PCI write | 3283 | * interrupts, and flush that PCI write |
3278 | */ | 3284 | */ |
3279 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 3285 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
3280 | 0x00000000); | 3286 | 0x00000000); |
3281 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
3282 | } | 3287 | } |
3283 | } else { /* shared interrupt */ | 3288 | } else { /* shared interrupt */ |
3284 | handled = 0; | 3289 | handled = 0; |
@@ -3321,9 +3326,8 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *r | |||
3321 | /* no work, shared interrupt perhaps? re-enable | 3326 | /* no work, shared interrupt perhaps? re-enable |
3322 | * interrupts, and flush that PCI write | 3327 | * interrupts, and flush that PCI write |
3323 | */ | 3328 | */ |
3324 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 3329 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
3325 | tp->last_tag << 24); | 3330 | tp->last_tag << 24); |
3326 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
3327 | } | 3331 | } |
3328 | } else { /* shared interrupt */ | 3332 | } else { /* shared interrupt */ |
3329 | handled = 0; | 3333 | handled = 0; |
@@ -5800,8 +5804,7 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5800 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | 5804 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
5801 | udelay(100); | 5805 | udelay(100); |
5802 | 5806 | ||
5803 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); | 5807 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); |
5804 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
5805 | tp->last_tag = 0; | 5808 | tp->last_tag = 0; |
5806 | 5809 | ||
5807 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | 5810 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
@@ -6190,7 +6193,8 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
6190 | HOSTCC_MODE_NOW); | 6193 | HOSTCC_MODE_NOW); |
6191 | 6194 | ||
6192 | for (i = 0; i < 5; i++) { | 6195 | for (i = 0; i < 5; i++) { |
6193 | int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | 6196 | int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 + |
6197 | TG3_64BIT_REG_LOW); | ||
6194 | if (int_mbox != 0) | 6198 | if (int_mbox != 0) |
6195 | break; | 6199 | break; |
6196 | msleep(10); | 6200 | msleep(10); |
@@ -6590,10 +6594,10 @@ static int tg3_open(struct net_device *dev) | |||
6590 | 6594 | ||
6591 | /* Mailboxes */ | 6595 | /* Mailboxes */ |
6592 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", | 6596 | printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n", |
6593 | tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), | 6597 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0), |
6594 | tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), | 6598 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4), |
6595 | tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), | 6599 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0), |
6596 | tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); | 6600 | tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4)); |
6597 | 6601 | ||
6598 | /* NIC side send descriptors. */ | 6602 | /* NIC side send descriptors. */ |
6599 | for (i = 0; i < 6; i++) { | 6603 | for (i = 0; i < 6; i++) { |
@@ -7893,7 +7897,7 @@ static int tg3_test_loopback(struct tg3 *tp) | |||
7893 | num_pkts++; | 7897 | num_pkts++; |
7894 | 7898 | ||
7895 | tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx); | 7899 | tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx); |
7896 | tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW); | 7900 | tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW); |
7897 | 7901 | ||
7898 | udelay(10); | 7902 | udelay(10); |
7899 | 7903 | ||
@@ -9320,6 +9324,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
9320 | /* Default fast path register access methods */ | 9324 | /* Default fast path register access methods */ |
9321 | tp->read32 = tg3_read32; | 9325 | tp->read32 = tg3_read32; |
9322 | tp->write32 = tg3_write32; | 9326 | tp->write32 = tg3_write32; |
9327 | tp->read32_mbox = tg3_read32; | ||
9323 | tp->write32_mbox = tg3_write32; | 9328 | tp->write32_mbox = tg3_write32; |
9324 | tp->write32_tx_mbox = tg3_write32; | 9329 | tp->write32_tx_mbox = tg3_write32; |
9325 | tp->write32_rx_mbox = tg3_write32; | 9330 | tp->write32_rx_mbox = tg3_write32; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 394acddd53b3..c398b8478d62 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2051,6 +2051,7 @@ struct tg3 { | |||
2051 | 2051 | ||
2052 | u32 (*read32) (struct tg3 *, u32); | 2052 | u32 (*read32) (struct tg3 *, u32); |
2053 | void (*write32) (struct tg3 *, u32, u32); | 2053 | void (*write32) (struct tg3 *, u32, u32); |
2054 | u32 (*read32_mbox) (struct tg3 *, u32); | ||
2054 | void (*write32_mbox) (struct tg3 *, u32, | 2055 | void (*write32_mbox) (struct tg3 *, u32, |
2055 | u32); | 2056 | u32); |
2056 | void __iomem *regs; | 2057 | void __iomem *regs; |