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-rw-r--r--drivers/net/Kconfig20
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/sky2.c3038
-rw-r--r--drivers/net/sky2.h1910
-rw-r--r--include/linux/netdevice.h8
5 files changed, 4974 insertions, 3 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 1958d9e16a3a..e2d5b77764a2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2008,7 +2008,25 @@ config SKGE
2008 2008
2009 It does not support the link failover and network management 2009 It does not support the link failover and network management
2010 features that "portable" vendor supplied sk98lin driver does. 2010 features that "portable" vendor supplied sk98lin driver does.
2011 2011
2012
2013config SKY2
2014 tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
2015 depends on PCI && EXPERIMENTAL
2016 select CRC32
2017 ---help---
2018 This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
2019
2020 To compile this driver as a module, choose M here: the module
2021 will be called sky2. This is recommended.
2022
2023config SKY2_EC_A1
2024 bool "Support old Yukon-EC A1 chipset"
2025 depends on SKY2
2026 ---help---
2027 Include support for early revisions of the Yukon EC chipset
2028 that required extra workarounds. If in doubt, say N.
2029
2012config SK98LIN 2030config SK98LIN
2013 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support" 2031 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
2014 depends on PCI 2032 depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 7c313cb341b8..5dccac434d48 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,6 +59,7 @@ spidernet-y += spider_net.o spider_net_ethtool.o sungem_phy.o
59obj-$(CONFIG_SPIDER_NET) += spidernet.o 59obj-$(CONFIG_SPIDER_NET) += spidernet.o
60obj-$(CONFIG_TC35815) += tc35815.o 60obj-$(CONFIG_TC35815) += tc35815.o
61obj-$(CONFIG_SKGE) += skge.o 61obj-$(CONFIG_SKGE) += skge.o
62obj-$(CONFIG_SKY2) += sky2.o
62obj-$(CONFIG_SK98LIN) += sk98lin/ 63obj-$(CONFIG_SK98LIN) += sk98lin/
63obj-$(CONFIG_SKFP) += skfp/ 64obj-$(CONFIG_SKFP) += skfp/
64obj-$(CONFIG_VIA_RHINE) += via-rhine.o 65obj-$(CONFIG_VIA_RHINE) += via-rhine.o
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
new file mode 100644
index 000000000000..e08695a2ca5a
--- /dev/null
+++ b/drivers/net/sky2.c
@@ -0,0 +1,3038 @@
1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
29 *
30 * TOTEST
31 * - speed setting
32 * - suspend/resume
33 */
34
35#include <linux/config.h>
36#include <linux/crc32.h>
37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/pci.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/in.h>
47#include <linux/delay.h>
48#include <linux/if_vlan.h>
49
50#include <asm/irq.h>
51
52#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53#define SKY2_VLAN_TAG_USED 1
54#endif
55
56#include "sky2.h"
57
58#define DRV_NAME "sky2"
59#define DRV_VERSION "0.7"
60#define PFX DRV_NAME " "
61
62/*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
69#ifdef CONFIG_SKY2_EC_A1
70#define is_ec_a1(hw) \
71 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
73#else
74#define is_ec_a1(hw) 0
75#endif
76
77#define RX_LE_SIZE 256
78#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
79#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
80#define RX_DEF_PENDING 128
81#define RX_COPY_THRESHOLD 256
82
83#define TX_RING_SIZE 512
84#define TX_DEF_PENDING (TX_RING_SIZE - 1)
85#define TX_MIN_PENDING 64
86#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
87
88#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
89#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
90#define ETH_JUMBO_MTU 9000
91#define TX_WATCHDOG (5 * HZ)
92#define NAPI_WEIGHT 64
93#define PHY_RETRIES 1000
94
95static const u32 default_msg =
96 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
97 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
98 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
99
100static int debug = -1; /* defaults above */
101module_param(debug, int, 0);
102MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
103
104static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { 0 }
123};
124
125MODULE_DEVICE_TABLE(pci, sky2_id_table);
126
127/* Avoid conditionals by using array */
128static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
129static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
130
131static const char *yukon_name[] = {
132 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
133 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
134 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
135
136 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
137 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
138};
139
140
141/* Access to external PHY */
142static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 return;
153 udelay(1);
154 }
155 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
156}
157
158static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
163 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
167 goto ready;
168 udelay(1);
169 }
170
171 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
172ready:
173 return gma_read16(hw, port, GM_SMI_DATA);
174}
175
176static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
177{
178 u16 power_control;
179 u32 reg1;
180 int vaux;
181 int ret = 0;
182
183 pr_debug("sky2_set_power_state %d\n", state);
184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
185
186 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
187 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
188 (power_control & PCI_PM_CAP_PME_D3cold);
189
190 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
191
192 power_control |= PCI_PM_CTRL_PME_STATUS;
193 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
194
195 switch (state) {
196 case PCI_D0:
197 /* switch power to VCC (WA for VAUX problem) */
198 sky2_write8(hw, B0_POWER_CTRL,
199 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
200
201 /* disable Core Clock Division, */
202 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
203
204 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
205 /* enable bits are inverted */
206 sky2_write8(hw, B2_Y2_CLK_GATE,
207 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
208 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
209 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
210 else
211 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
212
213 /* Turn off phy power saving */
214 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
215 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
216
217 /* looks like this XL is back asswards .. */
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
219 reg1 |= PCI_Y2_PHY1_COMA;
220 if (hw->ports > 1)
221 reg1 |= PCI_Y2_PHY2_COMA;
222 }
223 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
224 break;
225
226 case PCI_D3hot:
227 case PCI_D3cold:
228 /* Turn on phy power saving */
229 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
231 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
232 else
233 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
235
236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
237 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
238 else
239 /* enable bits are inverted */
240 sky2_write8(hw, B2_Y2_CLK_GATE,
241 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
242 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
243 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
244
245 /* switch power to VAUX */
246 if (vaux && state != PCI_D3cold)
247 sky2_write8(hw, B0_POWER_CTRL,
248 (PC_VAUX_ENA | PC_VCC_ENA |
249 PC_VAUX_ON | PC_VCC_OFF));
250 break;
251 default:
252 printk(KERN_ERR PFX "Unknown power state %d\n", state);
253 ret = -1;
254 }
255
256 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
257 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
258 return ret;
259}
260
261static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
262{
263 u16 reg;
264
265 /* disable all GMAC IRQ's */
266 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
267 /* disable PHY IRQs */
268 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
269
270 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
271 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
272 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
274
275 reg = gma_read16(hw, port, GM_RX_CTRL);
276 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
277 gma_write16(hw, port, GM_RX_CTRL, reg);
278}
279
280static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
281{
282 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
283 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
284
285 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
286 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
287
288 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
289 PHY_M_EC_MAC_S_MSK);
290 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
291
292 if (hw->chip_id == CHIP_ID_YUKON_EC)
293 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
294 else
295 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
296
297 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
298 }
299
300 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
301 if (hw->copper) {
302 if (hw->chip_id == CHIP_ID_YUKON_FE) {
303 /* enable automatic crossover */
304 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
305 } else {
306 /* disable energy detect */
307 ctrl &= ~PHY_M_PC_EN_DET_MSK;
308
309 /* enable automatic crossover */
310 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
311
312 if (sky2->autoneg == AUTONEG_ENABLE &&
313 hw->chip_id == CHIP_ID_YUKON_XL) {
314 ctrl &= ~PHY_M_PC_DSC_MSK;
315 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
316 }
317 }
318 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
319 } else {
320 /* workaround for deviation #4.88 (CRC errors) */
321 /* disable Automatic Crossover */
322
323 ctrl &= ~PHY_M_PC_MDIX_MSK;
324 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
325
326 if (hw->chip_id == CHIP_ID_YUKON_XL) {
327 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
328 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
330 ctrl &= ~PHY_M_MAC_MD_MSK;
331 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333
334 /* select page 1 to access Fiber registers */
335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
336 }
337 }
338
339 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
340 if (sky2->autoneg == AUTONEG_DISABLE)
341 ctrl &= ~PHY_CT_ANE;
342 else
343 ctrl |= PHY_CT_ANE;
344
345 ctrl |= PHY_CT_RESET;
346 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
347
348 ctrl = 0;
349 ct1000 = 0;
350 adv = PHY_AN_CSMA;
351
352 if (sky2->autoneg == AUTONEG_ENABLE) {
353 if (hw->copper) {
354 if (sky2->advertising & ADVERTISED_1000baseT_Full)
355 ct1000 |= PHY_M_1000C_AFD;
356 if (sky2->advertising & ADVERTISED_1000baseT_Half)
357 ct1000 |= PHY_M_1000C_AHD;
358 if (sky2->advertising & ADVERTISED_100baseT_Full)
359 adv |= PHY_M_AN_100_FD;
360 if (sky2->advertising & ADVERTISED_100baseT_Half)
361 adv |= PHY_M_AN_100_HD;
362 if (sky2->advertising & ADVERTISED_10baseT_Full)
363 adv |= PHY_M_AN_10_FD;
364 if (sky2->advertising & ADVERTISED_10baseT_Half)
365 adv |= PHY_M_AN_10_HD;
366 } else /* special defines for FIBER (88E1011S only) */
367 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
368
369 /* Set Flow-control capabilities */
370 if (sky2->tx_pause && sky2->rx_pause)
371 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
372 else if (sky2->rx_pause && !sky2->tx_pause)
373 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
374 else if (!sky2->rx_pause && sky2->tx_pause)
375 adv |= PHY_AN_PAUSE_ASYM; /* local */
376
377 /* Restart Auto-negotiation */
378 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
379 } else {
380 /* forced speed/duplex settings */
381 ct1000 = PHY_M_1000C_MSE;
382
383 if (sky2->duplex == DUPLEX_FULL)
384 ctrl |= PHY_CT_DUP_MD;
385
386 switch (sky2->speed) {
387 case SPEED_1000:
388 ctrl |= PHY_CT_SP1000;
389 break;
390 case SPEED_100:
391 ctrl |= PHY_CT_SP100;
392 break;
393 }
394
395 ctrl |= PHY_CT_RESET;
396 }
397
398 if (hw->chip_id != CHIP_ID_YUKON_FE)
399 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
400
401 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
402 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
403
404 /* Setup Phy LED's */
405 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
406 ledover = 0;
407
408 switch (hw->chip_id) {
409 case CHIP_ID_YUKON_FE:
410 /* on 88E3082 these bits are at 11..9 (shifted left) */
411 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
412
413 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
414
415 /* delete ACT LED control bits */
416 ctrl &= ~PHY_M_FELP_LED1_MSK;
417 /* change ACT LED control to blink mode */
418 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
419 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
420 break;
421
422 case CHIP_ID_YUKON_XL:
423 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
424
425 /* select page 3 to access LED control register */
426 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
427
428 /* set LED Function Control register */
429 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
430 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
431 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
432 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
433
434 /* set Polarity Control register */
435 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
436 (PHY_M_POLC_LS1_P_MIX(4) |
437 PHY_M_POLC_IS0_P_MIX(4) |
438 PHY_M_POLC_LOS_CTRL(2) |
439 PHY_M_POLC_INIT_CTRL(2) |
440 PHY_M_POLC_STA1_CTRL(2) |
441 PHY_M_POLC_STA0_CTRL(2)));
442
443 /* restore page register */
444 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
445 break;
446
447 default:
448 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
449 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
450 /* turn off the Rx LED (LED_RX) */
451 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
452 }
453
454 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
455
456 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
457 /* turn on 100 Mbps LED (LED_LINK100) */
458 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
459 }
460
461 if (ledover)
462 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
463
464 /* Enable phy interrupt on auto-negotiation complete (or link up) */
465 if (sky2->autoneg == AUTONEG_ENABLE)
466 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
467 else
468 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
469}
470
471static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
472{
473 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
474 u16 reg;
475 int i;
476 const u8 *addr = hw->dev[port]->dev_addr;
477
478 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
479 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
480
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
482
483 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
484 /* WA DEV_472 -- looks like crossed wires on port 2 */
485 /* clear GMAC 1 Control reset */
486 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
487 do {
488 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
489 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
490 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
491 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
492 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
493 }
494
495 if (sky2->autoneg == AUTONEG_DISABLE) {
496 reg = gma_read16(hw, port, GM_GP_CTRL);
497 reg |= GM_GPCR_AU_ALL_DIS;
498 gma_write16(hw, port, GM_GP_CTRL, reg);
499 gma_read16(hw, port, GM_GP_CTRL);
500
501 switch (sky2->speed) {
502 case SPEED_1000:
503 reg |= GM_GPCR_SPEED_1000;
504 /* fallthru */
505 case SPEED_100:
506 reg |= GM_GPCR_SPEED_100;
507 }
508
509 if (sky2->duplex == DUPLEX_FULL)
510 reg |= GM_GPCR_DUP_FULL;
511 } else
512 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
513
514 if (!sky2->tx_pause && !sky2->rx_pause) {
515 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
516 reg |=
517 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
518 } else if (sky2->tx_pause && !sky2->rx_pause) {
519 /* disable Rx flow-control */
520 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
521 }
522
523 gma_write16(hw, port, GM_GP_CTRL, reg);
524
525 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
526
527 spin_lock_bh(&hw->phy_lock);
528 sky2_phy_init(hw, port);
529 spin_unlock_bh(&hw->phy_lock);
530
531 /* MIB clear */
532 reg = gma_read16(hw, port, GM_PHY_ADDR);
533 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
534
535 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
536 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
537 gma_write16(hw, port, GM_PHY_ADDR, reg);
538
539 /* transmit control */
540 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
541
542 /* receive control reg: unicast + multicast + no FCS */
543 gma_write16(hw, port, GM_RX_CTRL,
544 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
545
546 /* transmit flow control */
547 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
548
549 /* transmit parameter */
550 gma_write16(hw, port, GM_TX_PARAM,
551 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
552 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
553 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
554 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
555
556 /* serial mode register */
557 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
558 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
559
560 if (hw->dev[port]->mtu > ETH_DATA_LEN)
561 reg |= GM_SMOD_JUMBO_ENA;
562
563 gma_write16(hw, port, GM_SERIAL_MODE, reg);
564
565 /* virtual address for data */
566 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
567
568 /* physical address: used for pause frames */
569 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
570
571 /* ignore counter overflows */
572 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
573 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
574 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
575
576 /* Configure Rx MAC FIFO */
577 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
578 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
579 GMF_RX_CTRL_DEF);
580
581 /* Flush Rx MAC FIFO on any flow control or error */
582 reg = GMR_FS_ANY_ERR;
583 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
584 reg = 0; /* WA dev #4.115 */
585
586 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
587 /* Set threshold to 0xa (64 bytes)
588 * ASF disabled so no need to do WA dev #4.30
589 */
590 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
591
592 /* Configure Tx MAC FIFO */
593 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
594 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
595}
596
597static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
598{
599 u32 end;
600
601 start /= 8;
602 len /= 8;
603 end = start + len - 1;
604
605 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
606 sky2_write32(hw, RB_ADDR(q, RB_START), start);
607 sky2_write32(hw, RB_ADDR(q, RB_END), end);
608 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
609 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
610
611 if (q == Q_R1 || q == Q_R2) {
612 u32 rxup, rxlo;
613
614 rxlo = len/2;
615 rxup = rxlo + len/4;
616
617 /* Set thresholds on receive queue's */
618 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
619 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
620 } else {
621 /* Enable store & forward on Tx queue's because
622 * Tx FIFO is only 1K on Yukon
623 */
624 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
625 }
626
627 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
628 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
629}
630
631/* Setup Bus Memory Interface */
632static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
633{
634 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
635 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
636 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
637 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
638}
639
640/* Setup prefetch unit registers. This is the interface between
641 * hardware and driver list elements
642 */
643static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
644 u64 addr, u32 last)
645{
646 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
647 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
648 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
649 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
650 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
651 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
652
653 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
654}
655
656static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
657{
658 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
659
660 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
661 return le;
662}
663
664/*
665 * This is a workaround code taken from SysKonnect sk98lin driver
666 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
667 */
668static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
669 u16 idx, u16 *last, u16 size)
670{
671 if (is_ec_a1(hw) && idx < *last) {
672 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
673
674 if (hwget == 0) {
675 /* Start prefetching again */
676 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
677 goto setnew;
678 }
679
680 if (hwget == size - 1) {
681 /* set watermark to one list element */
682 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
683
684 /* set put index to first list element */
685 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
686 } else /* have hardware go to end of list */
687 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
688 size - 1);
689 } else {
690setnew:
691 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
692 }
693 *last = idx;
694}
695
696
697static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
698{
699 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
700 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
701 return le;
702}
703
704/* Build description to hardware about buffer */
705static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
706{
707 struct sky2_rx_le *le;
708 u32 hi = (re->mapaddr >> 16) >> 16;
709
710 re->idx = sky2->rx_put;
711 if (sky2->rx_addr64 != hi) {
712 le = sky2_next_rx(sky2);
713 le->addr = cpu_to_le32(hi);
714 le->ctrl = 0;
715 le->opcode = OP_ADDR64 | HW_OWNER;
716 sky2->rx_addr64 = hi;
717 }
718
719 le = sky2_next_rx(sky2);
720 le->addr = cpu_to_le32((u32) re->mapaddr);
721 le->length = cpu_to_le16(re->maplen);
722 le->ctrl = 0;
723 le->opcode = OP_PACKET | HW_OWNER;
724}
725
726
727/* Tell chip where to start receive checksum.
728 * Actually has two checksums, but set both same to avoid possible byte
729 * order problems.
730 */
731static void rx_set_checksum(struct sky2_port *sky2)
732{
733 struct sky2_rx_le *le;
734
735 le = sky2_next_rx(sky2);
736 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
737 le->ctrl = 0;
738 le->opcode = OP_TCPSTART | HW_OWNER;
739
740 sky2_write32(sky2->hw,
741 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
742 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
743
744}
745
746/*
747 * The RX Stop command will not work for Yukon-2 if the BMU does not
748 * reach the end of packet and since we can't make sure that we have
749 * incoming data, we must reset the BMU while it is not doing a DMA
750 * transfer. Since it is possible that the RX path is still active,
751 * the RX RAM buffer will be stopped first, so any possible incoming
752 * data will not trigger a DMA. After the RAM buffer is stopped, the
753 * BMU is polled until any DMA in progress is ended and only then it
754 * will be reset.
755 */
756static void sky2_rx_stop(struct sky2_port *sky2)
757{
758 struct sky2_hw *hw = sky2->hw;
759 unsigned rxq = rxqaddr[sky2->port];
760 int i;
761
762 /* disable the RAM Buffer receive queue */
763 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
764
765 for (i = 0; i < 0xffff; i++)
766 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
767 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
768 goto stopped;
769
770 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
771 sky2->netdev->name);
772stopped:
773 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
774
775 /* reset the Rx prefetch unit */
776 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
777}
778
779/* Clean out receive buffer area, assumes receiver hardware stopped */
780static void sky2_rx_clean(struct sky2_port *sky2)
781{
782 unsigned i;
783
784 memset(sky2->rx_le, 0, RX_LE_BYTES);
785 for (i = 0; i < sky2->rx_pending; i++) {
786 struct ring_info *re = sky2->rx_ring + i;
787
788 if (re->skb) {
789 pci_unmap_single(sky2->hw->pdev,
790 re->mapaddr, re->maplen,
791 PCI_DMA_FROMDEVICE);
792 kfree_skb(re->skb);
793 re->skb = NULL;
794 }
795 }
796}
797
798#ifdef SKY2_VLAN_TAG_USED
799static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
800{
801 struct sky2_port *sky2 = netdev_priv(dev);
802 struct sky2_hw *hw = sky2->hw;
803 u16 port = sky2->port;
804 unsigned long flags;
805
806 spin_lock_irqsave(&sky2->tx_lock, flags);
807
808 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
810 sky2->vlgrp = grp;
811
812 spin_unlock_irqrestore(&sky2->tx_lock, flags);
813}
814
815static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
816{
817 struct sky2_port *sky2 = netdev_priv(dev);
818 struct sky2_hw *hw = sky2->hw;
819 u16 port = sky2->port;
820 unsigned long flags;
821
822 spin_lock_irqsave(&sky2->tx_lock, flags);
823
824 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
825 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
826 if (sky2->vlgrp)
827 sky2->vlgrp->vlan_devices[vid] = NULL;
828
829 spin_unlock_irqrestore(&sky2->tx_lock, flags);
830}
831#endif
832
833#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
834static inline unsigned rx_size(const struct sky2_port *sky2)
835{
836 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
837}
838
839/*
840 * Allocate and setup receiver buffer pool.
841 * In case of 64 bit dma, there are 2X as many list elements
842 * available as ring entries
843 * and need to reserve one list element so we don't wrap around.
844 *
845 * It appears the hardware has a bug in the FIFO logic that
846 * cause it to hang if the FIFO gets overrun and the receive buffer
847 * is not aligned. This means we can't use skb_reserve to align
848 * the IP header.
849 */
850static int sky2_rx_start(struct sky2_port *sky2)
851{
852 struct sky2_hw *hw = sky2->hw;
853 unsigned size = rx_size(sky2);
854 unsigned rxq = rxqaddr[sky2->port];
855 int i;
856
857 sky2->rx_put = sky2->rx_next = 0;
858 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
859 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
860
861 rx_set_checksum(sky2);
862 for (i = 0; i < sky2->rx_pending; i++) {
863 struct ring_info *re = sky2->rx_ring + i;
864
865 re->skb = dev_alloc_skb(size);
866 if (!re->skb)
867 goto nomem;
868
869 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
870 size, PCI_DMA_FROMDEVICE);
871 re->maplen = size;
872 sky2_rx_add(sky2, re);
873 }
874
875 /* Tell chip about available buffers */
876 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
877 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
878 return 0;
879nomem:
880 sky2_rx_clean(sky2);
881 return -ENOMEM;
882}
883
884/* Bring up network interface. */
885static int sky2_up(struct net_device *dev)
886{
887 struct sky2_port *sky2 = netdev_priv(dev);
888 struct sky2_hw *hw = sky2->hw;
889 unsigned port = sky2->port;
890 u32 ramsize, rxspace;
891 int err = -ENOMEM;
892
893 if (netif_msg_ifup(sky2))
894 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
895
896 /* must be power of 2 */
897 sky2->tx_le = pci_alloc_consistent(hw->pdev,
898 TX_RING_SIZE *
899 sizeof(struct sky2_tx_le),
900 &sky2->tx_le_map);
901 if (!sky2->tx_le)
902 goto err_out;
903
904 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
905 GFP_KERNEL);
906 if (!sky2->tx_ring)
907 goto err_out;
908 sky2->tx_prod = sky2->tx_cons = 0;
909
910 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
911 &sky2->rx_le_map);
912 if (!sky2->rx_le)
913 goto err_out;
914 memset(sky2->rx_le, 0, RX_LE_BYTES);
915
916 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
917 GFP_KERNEL);
918 if (!sky2->rx_ring)
919 goto err_out;
920
921 sky2_mac_init(hw, port);
922
923 /* Configure RAM buffers */
924 if (hw->chip_id == CHIP_ID_YUKON_FE ||
925 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
926 ramsize = 4096;
927 else {
928 u8 e0 = sky2_read8(hw, B2_E_0);
929 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
930 }
931
932 /* 2/3 for Rx */
933 rxspace = (2 * ramsize) / 3;
934 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
935 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
936
937 /* Make sure SyncQ is disabled */
938 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
939 RB_RST_SET);
940
941 sky2_qset(hw, txqaddr[port], 0x600);
942 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
943 TX_RING_SIZE - 1);
944
945 err = sky2_rx_start(sky2);
946 if (err)
947 goto err_out;
948
949 /* Enable interrupts from phy/mac for port */
950 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
951 sky2_write32(hw, B0_IMSK, hw->intr_mask);
952 return 0;
953
954err_out:
955 if (sky2->rx_le)
956 pci_free_consistent(hw->pdev, RX_LE_BYTES,
957 sky2->rx_le, sky2->rx_le_map);
958 if (sky2->tx_le)
959 pci_free_consistent(hw->pdev,
960 TX_RING_SIZE * sizeof(struct sky2_tx_le),
961 sky2->tx_le, sky2->tx_le_map);
962 if (sky2->tx_ring)
963 kfree(sky2->tx_ring);
964 if (sky2->rx_ring)
965 kfree(sky2->rx_ring);
966
967 return err;
968}
969
970/* Modular subtraction in ring */
971static inline int tx_dist(unsigned tail, unsigned head)
972{
973 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
974}
975
976/* Number of list elements available for next tx */
977static inline int tx_avail(const struct sky2_port *sky2)
978{
979 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
980}
981
982/* Estimate of number of transmit list elements required */
983static inline unsigned tx_le_req(const struct sk_buff *skb)
984{
985 unsigned count;
986
987 count = sizeof(dma_addr_t) / sizeof(u32);
988 count += skb_shinfo(skb)->nr_frags * count;
989
990 if (skb_shinfo(skb)->tso_size)
991 ++count;
992
993 if (skb->ip_summed)
994 ++count;
995
996 return count;
997}
998
999/*
1000 * Put one packet in ring for transmit.
1001 * A single packet can generate multiple list elements, and
1002 * the number of ring elements will probably be less than the number
1003 * of list elements used.
1004 */
1005static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1006{
1007 struct sky2_port *sky2 = netdev_priv(dev);
1008 struct sky2_hw *hw = sky2->hw;
1009 struct sky2_tx_le *le = NULL;
1010 struct ring_info *re;
1011 unsigned long flags;
1012 unsigned i, len;
1013 dma_addr_t mapping;
1014 u32 addr64;
1015 u16 mss;
1016 u8 ctrl;
1017
1018 local_irq_save(flags);
1019 if (!spin_trylock(&sky2->tx_lock)) {
1020 local_irq_restore(flags);
1021 return NETDEV_TX_LOCKED;
1022 }
1023
1024 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1025 netif_stop_queue(dev);
1026 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1027
1028 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1029 dev->name);
1030 return NETDEV_TX_BUSY;
1031 }
1032
1033 if (unlikely(netif_msg_tx_queued(sky2)))
1034 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1035 dev->name, sky2->tx_prod, skb->len);
1036
1037 len = skb_headlen(skb);
1038 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1039 addr64 = (mapping >> 16) >> 16;
1040
1041 re = sky2->tx_ring + sky2->tx_prod;
1042
1043 /* Send high bits if changed */
1044 if (addr64 != sky2->tx_addr64) {
1045 le = get_tx_le(sky2);
1046 le->tx.addr = cpu_to_le32(addr64);
1047 le->ctrl = 0;
1048 le->opcode = OP_ADDR64 | HW_OWNER;
1049 sky2->tx_addr64 = addr64;
1050 }
1051
1052 /* Check for TCP Segmentation Offload */
1053 mss = skb_shinfo(skb)->tso_size;
1054 if (mss != 0) {
1055 /* just drop the packet if non-linear expansion fails */
1056 if (skb_header_cloned(skb) &&
1057 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1058 dev_kfree_skb_any(skb);
1059 goto out_unlock;
1060 }
1061
1062 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1063 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1064 mss += ETH_HLEN;
1065 }
1066
1067 if (mss != sky2->tx_last_mss) {
1068 le = get_tx_le(sky2);
1069 le->tx.tso.size = cpu_to_le16(mss);
1070 le->tx.tso.rsvd = 0;
1071 le->opcode = OP_LRGLEN | HW_OWNER;
1072 le->ctrl = 0;
1073 sky2->tx_last_mss = mss;
1074 }
1075
1076 ctrl = 0;
1077#ifdef SKY2_VLAN_TAG_USED
1078 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1079 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1080 if (!le) {
1081 le = get_tx_le(sky2);
1082 le->tx.addr = 0;
1083 le->opcode = OP_VLAN|HW_OWNER;
1084 le->ctrl = 0;
1085 } else
1086 le->opcode |= OP_VLAN;
1087 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1088 ctrl |= INS_VLAN;
1089 }
1090#endif
1091
1092 /* Handle TCP checksum offload */
1093 if (skb->ip_summed == CHECKSUM_HW) {
1094 u16 hdr = skb->h.raw - skb->data;
1095 u16 offset = hdr + skb->csum;
1096
1097 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1098 if (skb->nh.iph->protocol == IPPROTO_UDP)
1099 ctrl |= UDPTCP;
1100
1101 le = get_tx_le(sky2);
1102 le->tx.csum.start = cpu_to_le16(hdr);
1103 le->tx.csum.offset = cpu_to_le16(offset);
1104 le->length = 0; /* initial checksum value */
1105 le->ctrl = 1; /* one packet */
1106 le->opcode = OP_TCPLISW | HW_OWNER;
1107 }
1108
1109 le = get_tx_le(sky2);
1110 le->tx.addr = cpu_to_le32((u32) mapping);
1111 le->length = cpu_to_le16(len);
1112 le->ctrl = ctrl;
1113 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1114
1115 /* Record the transmit mapping info */
1116 re->skb = skb;
1117 re->mapaddr = mapping;
1118 re->maplen = len;
1119
1120 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1121 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1122 struct ring_info *fre;
1123
1124 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1125 frag->size, PCI_DMA_TODEVICE);
1126 addr64 = (mapping >> 16) >> 16;
1127 if (addr64 != sky2->tx_addr64) {
1128 le = get_tx_le(sky2);
1129 le->tx.addr = cpu_to_le32(addr64);
1130 le->ctrl = 0;
1131 le->opcode = OP_ADDR64 | HW_OWNER;
1132 sky2->tx_addr64 = addr64;
1133 }
1134
1135 le = get_tx_le(sky2);
1136 le->tx.addr = cpu_to_le32((u32) mapping);
1137 le->length = cpu_to_le16(frag->size);
1138 le->ctrl = ctrl;
1139 le->opcode = OP_BUFFER | HW_OWNER;
1140
1141 fre = sky2->tx_ring
1142 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1143 fre->skb = NULL;
1144 fre->mapaddr = mapping;
1145 fre->maplen = frag->size;
1146 }
1147 re->idx = sky2->tx_prod;
1148 le->ctrl |= EOP;
1149
1150 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1151 &sky2->tx_last_put, TX_RING_SIZE);
1152
1153 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1154 netif_stop_queue(dev);
1155
1156out_unlock:
1157 mmiowb();
1158 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1159
1160 dev->trans_start = jiffies;
1161 return NETDEV_TX_OK;
1162}
1163
1164/*
1165 * Free ring elements from starting at tx_cons until "done"
1166 *
1167 * NB: the hardware will tell us about partial completion of multi-part
1168 * buffers; these are deferred until completion.
1169 */
1170static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1171{
1172 struct net_device *dev = sky2->netdev;
1173 unsigned i;
1174
1175 if (unlikely(netif_msg_tx_done(sky2)))
1176 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1177 dev->name, done);
1178
1179 spin_lock(&sky2->tx_lock);
1180
1181 while (sky2->tx_cons != done) {
1182 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1183 struct sk_buff *skb;
1184
1185 /* Check for partial status */
1186 if (tx_dist(sky2->tx_cons, done)
1187 < tx_dist(sky2->tx_cons, re->idx))
1188 goto out;
1189
1190 skb = re->skb;
1191 pci_unmap_single(sky2->hw->pdev,
1192 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1193
1194 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1195 struct ring_info *fre;
1196 fre =
1197 sky2->tx_ring + (sky2->tx_cons + i +
1198 1) % TX_RING_SIZE;
1199 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1200 fre->maplen, PCI_DMA_TODEVICE);
1201 }
1202
1203 dev_kfree_skb_any(skb);
1204
1205 sky2->tx_cons = re->idx;
1206 }
1207out:
1208
1209 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1210 netif_wake_queue(dev);
1211 spin_unlock(&sky2->tx_lock);
1212}
1213
1214/* Cleanup all untransmitted buffers, assume transmitter not running */
1215static inline void sky2_tx_clean(struct sky2_port *sky2)
1216{
1217 sky2_tx_complete(sky2, sky2->tx_prod);
1218}
1219
1220/* Network shutdown */
1221static int sky2_down(struct net_device *dev)
1222{
1223 struct sky2_port *sky2 = netdev_priv(dev);
1224 struct sky2_hw *hw = sky2->hw;
1225 unsigned port = sky2->port;
1226 u16 ctrl;
1227
1228 if (netif_msg_ifdown(sky2))
1229 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1230
1231 netif_stop_queue(dev);
1232
1233 sky2_phy_reset(hw, port);
1234
1235 /* Stop transmitter */
1236 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1237 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1238
1239 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1240 RB_RST_SET | RB_DIS_OP_MD);
1241
1242 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1243 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1244 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1245
1246 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1247
1248 /* Workaround shared GMAC reset */
1249 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1250 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1251 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1252
1253 /* Disable Force Sync bit and Enable Alloc bit */
1254 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1255 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1256
1257 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1258 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1259 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1260
1261 /* Reset the PCI FIFO of the async Tx queue */
1262 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1263 BMU_RST_SET | BMU_FIFO_RST);
1264
1265 /* Reset the Tx prefetch units */
1266 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1267 PREF_UNIT_RST_SET);
1268
1269 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1270
1271 sky2_rx_stop(sky2);
1272
1273 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1274 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1275
1276 /* turn off LED's */
1277 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1278
1279 sky2_tx_clean(sky2);
1280 sky2_rx_clean(sky2);
1281
1282 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1283 sky2->rx_le, sky2->rx_le_map);
1284 kfree(sky2->rx_ring);
1285
1286 pci_free_consistent(hw->pdev,
1287 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1288 sky2->tx_le, sky2->tx_le_map);
1289 kfree(sky2->tx_ring);
1290
1291 return 0;
1292}
1293
1294static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1295{
1296 if (!hw->copper)
1297 return SPEED_1000;
1298
1299 if (hw->chip_id == CHIP_ID_YUKON_FE)
1300 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1301
1302 switch (aux & PHY_M_PS_SPEED_MSK) {
1303 case PHY_M_PS_SPEED_1000:
1304 return SPEED_1000;
1305 case PHY_M_PS_SPEED_100:
1306 return SPEED_100;
1307 default:
1308 return SPEED_10;
1309 }
1310}
1311
1312static void sky2_link_up(struct sky2_port *sky2)
1313{
1314 struct sky2_hw *hw = sky2->hw;
1315 unsigned port = sky2->port;
1316 u16 reg;
1317
1318 /* disable Rx GMAC FIFO flush mode */
1319 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1320
1321 /* Enable Transmit FIFO Underrun */
1322 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1323
1324 reg = gma_read16(hw, port, GM_GP_CTRL);
1325 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1326 reg |= GM_GPCR_DUP_FULL;
1327
1328 /* enable Rx/Tx */
1329 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1330 gma_write16(hw, port, GM_GP_CTRL, reg);
1331 gma_read16(hw, port, GM_GP_CTRL);
1332
1333 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1334
1335 netif_carrier_on(sky2->netdev);
1336 netif_wake_queue(sky2->netdev);
1337
1338 /* Turn on link LED */
1339 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1340 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1341
1342 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1343 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1344
1345 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1347 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1348 SPEED_10 ? 7 : 0) |
1349 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1350 SPEED_100 ? 7 : 0) |
1351 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1352 SPEED_1000 ? 7 : 0));
1353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1354 }
1355
1356 if (netif_msg_link(sky2))
1357 printk(KERN_INFO PFX
1358 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1359 sky2->netdev->name, sky2->speed,
1360 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1361 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1362 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1363}
1364
1365static void sky2_link_down(struct sky2_port *sky2)
1366{
1367 struct sky2_hw *hw = sky2->hw;
1368 unsigned port = sky2->port;
1369 u16 reg;
1370
1371 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1372
1373 reg = gma_read16(hw, port, GM_GP_CTRL);
1374 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1375 gma_write16(hw, port, GM_GP_CTRL, reg);
1376 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1377
1378 if (sky2->rx_pause && !sky2->tx_pause) {
1379 /* restore Asymmetric Pause bit */
1380 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1381 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1382 | PHY_M_AN_ASP);
1383 }
1384
1385 sky2_phy_reset(hw, port);
1386
1387 netif_carrier_off(sky2->netdev);
1388 netif_stop_queue(sky2->netdev);
1389
1390 /* Turn on link LED */
1391 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1392
1393 if (netif_msg_link(sky2))
1394 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1395 sky2_phy_init(hw, port);
1396}
1397
1398static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1399{
1400 struct sky2_hw *hw = sky2->hw;
1401 unsigned port = sky2->port;
1402 u16 lpa;
1403
1404 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1405
1406 if (lpa & PHY_M_AN_RF) {
1407 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1408 return -1;
1409 }
1410
1411 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1412 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1413 printk(KERN_ERR PFX "%s: master/slave fault",
1414 sky2->netdev->name);
1415 return -1;
1416 }
1417
1418 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1419 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1420 sky2->netdev->name);
1421 return -1;
1422 }
1423
1424 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1425
1426 sky2->speed = sky2_phy_speed(hw, aux);
1427
1428 /* Pause bits are offset (9..8) */
1429 if (hw->chip_id == CHIP_ID_YUKON_XL)
1430 aux >>= 6;
1431
1432 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1433 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1434
1435 if ((sky2->tx_pause || sky2->rx_pause)
1436 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1437 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1438 else
1439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1440
1441 return 0;
1442}
1443
1444/*
1445 * Interrupt from PHY are handled in tasklet (soft irq)
1446 * because accessing phy registers requires spin wait which might
1447 * cause excess interrupt latency.
1448 */
1449static void sky2_phy_task(unsigned long data)
1450{
1451 struct sky2_port *sky2 = (struct sky2_port *)data;
1452 struct sky2_hw *hw = sky2->hw;
1453 u16 istatus, phystat;
1454
1455 spin_lock(&hw->phy_lock);
1456 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1457 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1458
1459 if (netif_msg_intr(sky2))
1460 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1461 sky2->netdev->name, istatus, phystat);
1462
1463 if (istatus & PHY_M_IS_AN_COMPL) {
1464 if (sky2_autoneg_done(sky2, phystat) == 0)
1465 sky2_link_up(sky2);
1466 goto out;
1467 }
1468
1469 if (istatus & PHY_M_IS_LSP_CHANGE)
1470 sky2->speed = sky2_phy_speed(hw, phystat);
1471
1472 if (istatus & PHY_M_IS_DUP_CHANGE)
1473 sky2->duplex =
1474 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1475
1476 if (istatus & PHY_M_IS_LST_CHANGE) {
1477 if (phystat & PHY_M_PS_LINK_UP)
1478 sky2_link_up(sky2);
1479 else
1480 sky2_link_down(sky2);
1481 }
1482out:
1483 spin_unlock(&hw->phy_lock);
1484
1485 local_irq_disable();
1486 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1487 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1488 local_irq_enable();
1489}
1490
1491static void sky2_tx_timeout(struct net_device *dev)
1492{
1493 struct sky2_port *sky2 = netdev_priv(dev);
1494
1495 if (netif_msg_timer(sky2))
1496 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1497
1498 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1499 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1500
1501 sky2_tx_clean(sky2);
1502}
1503
1504static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1505{
1506 struct sky2_port *sky2 = netdev_priv(dev);
1507 struct sky2_hw *hw = sky2->hw;
1508 int err;
1509 u16 ctl, mode;
1510
1511 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1512 return -EINVAL;
1513
1514 if (!netif_running(dev)) {
1515 dev->mtu = new_mtu;
1516 return 0;
1517 }
1518
1519 local_irq_disable();
1520 sky2_write32(hw, B0_IMSK, 0);
1521
1522 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1523 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1524 sky2_rx_stop(sky2);
1525 sky2_rx_clean(sky2);
1526
1527 dev->mtu = new_mtu;
1528 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1529 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1530
1531 if (dev->mtu > ETH_DATA_LEN)
1532 mode |= GM_SMOD_JUMBO_ENA;
1533
1534 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1535
1536 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1537
1538 err = sky2_rx_start(sky2);
1539 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1540
1541 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1542 sky2_read32(hw, B0_IMSK);
1543 local_irq_enable();
1544 return err;
1545}
1546
1547/*
1548 * Receive one packet.
1549 * For small packets or errors, just reuse existing skb.
1550 * For larger packets, get new buffer.
1551 */
1552static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1553 u16 length, u32 status)
1554{
1555 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1556 struct sk_buff *skb = NULL;
1557 struct net_device *dev;
1558 const unsigned int bufsize = rx_size(sky2);
1559
1560 if (unlikely(netif_msg_rx_status(sky2)))
1561 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1562 sky2->netdev->name, sky2->rx_next, status, length);
1563
1564 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1565
1566 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
1567 goto error;
1568
1569 if (length < RX_COPY_THRESHOLD) {
1570 skb = alloc_skb(length + 2, GFP_ATOMIC);
1571 if (!skb)
1572 goto resubmit;
1573
1574 skb_reserve(skb, 2);
1575 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1576 length, PCI_DMA_FROMDEVICE);
1577 memcpy(skb->data, re->skb->data, length);
1578 skb->ip_summed = re->skb->ip_summed;
1579 skb->csum = re->skb->csum;
1580 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1581 length, PCI_DMA_FROMDEVICE);
1582 } else {
1583 struct sk_buff *nskb;
1584
1585 nskb = dev_alloc_skb(bufsize);
1586 if (!nskb)
1587 goto resubmit;
1588
1589 skb = re->skb;
1590 re->skb = nskb;
1591 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1592 re->maplen, PCI_DMA_FROMDEVICE);
1593 prefetch(skb->data);
1594
1595 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1596 bufsize, PCI_DMA_FROMDEVICE);
1597 re->maplen = bufsize;
1598 }
1599
1600 skb_put(skb, length);
1601 dev = sky2->netdev;
1602 skb->dev = dev;
1603 skb->protocol = eth_type_trans(skb, dev);
1604 dev->last_rx = jiffies;
1605
1606resubmit:
1607 re->skb->ip_summed = CHECKSUM_NONE;
1608 sky2_rx_add(sky2, re);
1609
1610 /* Tell receiver about new buffers. */
1611 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1612 &sky2->rx_last_put, RX_LE_SIZE);
1613
1614 return skb;
1615
1616error:
1617 if (status & GMR_FS_GOOD_FC)
1618 goto resubmit;
1619
1620 if (netif_msg_rx_err(sky2))
1621 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1622 sky2->netdev->name, status, length);
1623
1624 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1625 sky2->net_stats.rx_length_errors++;
1626 if (status & GMR_FS_FRAGMENT)
1627 sky2->net_stats.rx_frame_errors++;
1628 if (status & GMR_FS_CRC_ERR)
1629 sky2->net_stats.rx_crc_errors++;
1630 if (status & GMR_FS_RX_FF_OV)
1631 sky2->net_stats.rx_fifo_errors++;
1632
1633 goto resubmit;
1634}
1635
1636/* Transmit ring index in reported status block is encoded as:
1637 *
1638 * | TXS2 | TXA2 | TXS1 | TXA1
1639 */
1640static inline u16 tx_index(u8 port, u32 status, u16 len)
1641{
1642 if (port == 0)
1643 return status & 0xfff;
1644 else
1645 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1646}
1647
1648/*
1649 * Both ports share the same status interrupt, therefore there is only
1650 * one poll routine.
1651 */
1652static int sky2_poll(struct net_device *dev0, int *budget)
1653{
1654 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1655 unsigned int to_do = min(dev0->quota, *budget);
1656 unsigned int work_done = 0;
1657 u16 hwidx;
1658
1659 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1660 BUG_ON(hwidx >= STATUS_RING_SIZE);
1661 rmb();
1662
1663 do {
1664 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1665 struct sky2_port *sky2;
1666 struct sk_buff *skb;
1667 u32 status;
1668 u16 length;
1669
1670 /* Are we done yet? */
1671 if (hw->st_idx == hwidx) {
1672 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1673 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1674 if (hwidx == hw->st_idx)
1675 break;
1676 }
1677
1678 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1679 prefetch(&hw->st_le[hw->st_idx]);
1680
1681 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1682
1683 sky2 = netdev_priv(hw->dev[le->link]);
1684 status = le32_to_cpu(le->status);
1685 length = le16_to_cpu(le->length);
1686
1687 switch (le->opcode & ~HW_OWNER) {
1688 case OP_RXSTAT:
1689 skb = sky2_receive(sky2, length, status);
1690 if (!skb)
1691 break;
1692#ifdef SKY2_VLAN_TAG_USED
1693 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1694 vlan_hwaccel_receive_skb(skb,
1695 sky2->vlgrp,
1696 be16_to_cpu(sky2->rx_tag));
1697 } else
1698#endif
1699 netif_receive_skb(skb);
1700 ++work_done;
1701 break;
1702
1703#ifdef SKY2_VLAN_TAG_USED
1704 case OP_RXVLAN:
1705 sky2->rx_tag = length;
1706 break;
1707
1708 case OP_RXCHKSVLAN:
1709 sky2->rx_tag = length;
1710 /* fall through */
1711#endif
1712 case OP_RXCHKS:
1713 skb = sky2->rx_ring[sky2->rx_next].skb;
1714 skb->ip_summed = CHECKSUM_HW;
1715 skb->csum = le16_to_cpu(status);
1716 break;
1717
1718 case OP_TXINDEXLE:
1719 sky2_tx_complete(sky2,
1720 tx_index(sky2->port, status, length));
1721 break;
1722
1723 default:
1724 if (net_ratelimit())
1725 printk(KERN_WARNING PFX
1726 "unknown status opcode 0x%x\n",
1727 le->opcode);
1728 break;
1729 }
1730
1731 le->opcode = 0; /* paranoia */
1732 } while (work_done < to_do);
1733
1734 mmiowb();
1735
1736 *budget -= work_done;
1737 dev0->quota -= work_done;
1738 if (work_done < to_do) {
1739 /*
1740 * Another chip workaround, need to restart TX timer if status
1741 * LE was handled. WA_DEV_43_418
1742 */
1743 if (is_ec_a1(hw)) {
1744 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1745 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1746 }
1747
1748 netif_rx_complete(dev0);
1749 hw->intr_mask |= Y2_IS_STAT_BMU;
1750 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1751 sky2_read32(hw, B0_IMSK);
1752 }
1753
1754 return work_done >= to_do;
1755
1756}
1757
1758static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1759{
1760 struct net_device *dev = hw->dev[port];
1761
1762 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1763 dev->name, status);
1764
1765 if (status & Y2_IS_PAR_RD1) {
1766 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1767 dev->name);
1768 /* Clear IRQ */
1769 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1770 }
1771
1772 if (status & Y2_IS_PAR_WR1) {
1773 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1774 dev->name);
1775
1776 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1777 }
1778
1779 if (status & Y2_IS_PAR_MAC1) {
1780 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1781 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1782 }
1783
1784 if (status & Y2_IS_PAR_RX1) {
1785 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1786 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1787 }
1788
1789 if (status & Y2_IS_TCP_TXA1) {
1790 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1791 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1792 }
1793}
1794
1795static void sky2_hw_intr(struct sky2_hw *hw)
1796{
1797 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1798
1799 if (status & Y2_IS_TIST_OV)
1800 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1801
1802 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1803 u16 pci_err;
1804
1805 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1806 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1807 pci_name(hw->pdev), pci_err);
1808
1809 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1810 pci_write_config_word(hw->pdev, PCI_STATUS,
1811 pci_err | PCI_STATUS_ERROR_BITS);
1812 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1813 }
1814
1815 if (status & Y2_IS_PCI_EXP) {
1816 /* PCI-Express uncorrectable Error occurred */
1817 u32 pex_err;
1818
1819 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1820
1821 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1822 pci_name(hw->pdev), pex_err);
1823
1824 /* clear the interrupt */
1825 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1826 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1827 0xffffffffUL);
1828 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1829
1830 if (pex_err & PEX_FATAL_ERRORS) {
1831 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1832 hwmsk &= ~Y2_IS_PCI_EXP;
1833 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1834 }
1835 }
1836
1837 if (status & Y2_HWE_L1_MASK)
1838 sky2_hw_error(hw, 0, status);
1839 status >>= 8;
1840 if (status & Y2_HWE_L1_MASK)
1841 sky2_hw_error(hw, 1, status);
1842}
1843
1844static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1845{
1846 struct net_device *dev = hw->dev[port];
1847 struct sky2_port *sky2 = netdev_priv(dev);
1848 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1849
1850 if (netif_msg_intr(sky2))
1851 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1852 dev->name, status);
1853
1854 if (status & GM_IS_RX_FF_OR) {
1855 ++sky2->net_stats.rx_fifo_errors;
1856 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1857 }
1858
1859 if (status & GM_IS_TX_FF_UR) {
1860 ++sky2->net_stats.tx_fifo_errors;
1861 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1862 }
1863}
1864
1865static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1866{
1867 struct net_device *dev = hw->dev[port];
1868 struct sky2_port *sky2 = netdev_priv(dev);
1869
1870 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1871 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1872 tasklet_schedule(&sky2->phy_task);
1873}
1874
1875static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1876{
1877 struct sky2_hw *hw = dev_id;
1878 struct net_device *dev0 = hw->dev[0];
1879 u32 status;
1880
1881 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1882 if (status == 0 || status == ~0)
1883 return IRQ_NONE;
1884
1885 if (status & Y2_IS_HW_ERR)
1886 sky2_hw_intr(hw);
1887
1888 /* Do NAPI for Rx and Tx status */
1889 if (status & Y2_IS_STAT_BMU) {
1890 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1891 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1892 prefetch(&hw->st_le[hw->st_idx]);
1893
1894 if (netif_rx_schedule_test(dev0))
1895 __netif_rx_schedule(dev0);
1896 }
1897
1898 if (status & Y2_IS_IRQ_PHY1)
1899 sky2_phy_intr(hw, 0);
1900
1901 if (status & Y2_IS_IRQ_PHY2)
1902 sky2_phy_intr(hw, 1);
1903
1904 if (status & Y2_IS_IRQ_MAC1)
1905 sky2_mac_intr(hw, 0);
1906
1907 if (status & Y2_IS_IRQ_MAC2)
1908 sky2_mac_intr(hw, 1);
1909
1910 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1911
1912 sky2_read32(hw, B0_IMSK);
1913
1914 return IRQ_HANDLED;
1915}
1916
1917#ifdef CONFIG_NET_POLL_CONTROLLER
1918static void sky2_netpoll(struct net_device *dev)
1919{
1920 struct sky2_port *sky2 = netdev_priv(dev);
1921
1922 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1923}
1924#endif
1925
1926/* Chip internal frequency for clock calculations */
1927static inline u32 sky2_khz(const struct sky2_hw *hw)
1928{
1929 switch (hw->chip_id) {
1930 case CHIP_ID_YUKON_EC:
1931 return 125000; /* 125 Mhz */
1932 case CHIP_ID_YUKON_FE:
1933 return 100000; /* 100 Mhz */
1934 default: /* YUKON_XL */
1935 return 156000; /* 156 Mhz */
1936 }
1937}
1938
1939static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1940{
1941 return sky2_khz(hw) * ms;
1942}
1943
1944static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1945{
1946 return (sky2_khz(hw) * us) / 1000;
1947}
1948
1949static int sky2_reset(struct sky2_hw *hw)
1950{
1951 u32 ctst;
1952 u16 status;
1953 u8 t8, pmd_type;
1954 int i;
1955
1956 ctst = sky2_read32(hw, B0_CTST);
1957
1958 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1959 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1960 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1961 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1962 pci_name(hw->pdev), hw->chip_id);
1963 return -EOPNOTSUPP;
1964 }
1965
1966 /* ring for status responses */
1967 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1968 &hw->st_dma);
1969 if (!hw->st_le)
1970 return -ENOMEM;
1971
1972 /* disable ASF */
1973 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1974 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1975 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1976 }
1977
1978 /* do a SW reset */
1979 sky2_write8(hw, B0_CTST, CS_RST_SET);
1980 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1981
1982 /* clear PCI errors, if any */
1983 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1984 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1985 pci_write_config_word(hw->pdev, PCI_STATUS,
1986 status | PCI_STATUS_ERROR_BITS);
1987
1988 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1989
1990 /* clear any PEX errors */
1991 if (is_pciex(hw)) {
1992 u16 lstat;
1993 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1994 0xffffffffUL);
1995 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1996 }
1997
1998 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1999 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2000
2001 hw->ports = 1;
2002 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2003 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2004 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2005 ++hw->ports;
2006 }
2007 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2008
2009 sky2_set_power_state(hw, PCI_D0);
2010
2011 for (i = 0; i < hw->ports; i++) {
2012 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2013 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2014 }
2015
2016 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2017
2018 /* Clear I2C IRQ noise */
2019 sky2_write32(hw, B2_I2C_IRQ, 1);
2020
2021 /* turn off hardware timer (unused) */
2022 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2023 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2024
2025 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2026
2027 /* Turn on descriptor polling (every 75us) */
2028 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2029 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2030
2031 /* Turn off receive timestamp */
2032 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2033 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2034
2035 /* enable the Tx Arbiters */
2036 for (i = 0; i < hw->ports; i++)
2037 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2038
2039 /* Initialize ram interface */
2040 for (i = 0; i < hw->ports; i++) {
2041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2042
2043 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2052 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2053 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2054 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2055 }
2056
2057 if (is_pciex(hw)) {
2058 u16 pctrl;
2059
2060 /* change Max. Read Request Size to 2048 bytes */
2061 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2062 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2063 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2064
2065
2066 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2067 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2068 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2069 }
2070
2071 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2072
2073 spin_lock_bh(&hw->phy_lock);
2074 for (i = 0; i < hw->ports; i++)
2075 sky2_phy_reset(hw, i);
2076 spin_unlock_bh(&hw->phy_lock);
2077
2078 memset(hw->st_le, 0, STATUS_LE_BYTES);
2079 hw->st_idx = 0;
2080
2081 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2082 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2083
2084 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2085 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2086
2087 /* Set the list last index */
2088 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2089
2090 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2091
2092 /* These status setup values are copied from SysKonnect's driver */
2093 if (is_ec_a1(hw)) {
2094 /* WA for dev. #4.3 */
2095 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2096
2097 /* set Status-FIFO watermark */
2098 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2099
2100 /* set Status-FIFO ISR watermark */
2101 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2102
2103 } else {
2104 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2105
2106 /* set Status-FIFO watermark */
2107 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2108
2109 /* set Status-FIFO ISR watermark */
2110 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2111 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2112
2113 else /* WA dev 4.109 */
2114 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2115
2116 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2117 }
2118
2119 /* enable status unit */
2120 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2121
2122 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2123 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2124 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2125
2126 return 0;
2127}
2128
2129static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2130{
2131 u32 modes;
2132 if (hw->copper) {
2133 modes = SUPPORTED_10baseT_Half
2134 | SUPPORTED_10baseT_Full
2135 | SUPPORTED_100baseT_Half
2136 | SUPPORTED_100baseT_Full
2137 | SUPPORTED_Autoneg | SUPPORTED_TP;
2138
2139 if (hw->chip_id != CHIP_ID_YUKON_FE)
2140 modes |= SUPPORTED_1000baseT_Half
2141 | SUPPORTED_1000baseT_Full;
2142 } else
2143 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2144 | SUPPORTED_Autoneg;
2145 return modes;
2146}
2147
2148static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2149{
2150 struct sky2_port *sky2 = netdev_priv(dev);
2151 struct sky2_hw *hw = sky2->hw;
2152
2153 ecmd->transceiver = XCVR_INTERNAL;
2154 ecmd->supported = sky2_supported_modes(hw);
2155 ecmd->phy_address = PHY_ADDR_MARV;
2156 if (hw->copper) {
2157 ecmd->supported = SUPPORTED_10baseT_Half
2158 | SUPPORTED_10baseT_Full
2159 | SUPPORTED_100baseT_Half
2160 | SUPPORTED_100baseT_Full
2161 | SUPPORTED_1000baseT_Half
2162 | SUPPORTED_1000baseT_Full
2163 | SUPPORTED_Autoneg | SUPPORTED_TP;
2164 ecmd->port = PORT_TP;
2165 } else
2166 ecmd->port = PORT_FIBRE;
2167
2168 ecmd->advertising = sky2->advertising;
2169 ecmd->autoneg = sky2->autoneg;
2170 ecmd->speed = sky2->speed;
2171 ecmd->duplex = sky2->duplex;
2172 return 0;
2173}
2174
2175static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2176{
2177 struct sky2_port *sky2 = netdev_priv(dev);
2178 const struct sky2_hw *hw = sky2->hw;
2179 u32 supported = sky2_supported_modes(hw);
2180
2181 if (ecmd->autoneg == AUTONEG_ENABLE) {
2182 ecmd->advertising = supported;
2183 sky2->duplex = -1;
2184 sky2->speed = -1;
2185 } else {
2186 u32 setting;
2187
2188 switch (ecmd->speed) {
2189 case SPEED_1000:
2190 if (ecmd->duplex == DUPLEX_FULL)
2191 setting = SUPPORTED_1000baseT_Full;
2192 else if (ecmd->duplex == DUPLEX_HALF)
2193 setting = SUPPORTED_1000baseT_Half;
2194 else
2195 return -EINVAL;
2196 break;
2197 case SPEED_100:
2198 if (ecmd->duplex == DUPLEX_FULL)
2199 setting = SUPPORTED_100baseT_Full;
2200 else if (ecmd->duplex == DUPLEX_HALF)
2201 setting = SUPPORTED_100baseT_Half;
2202 else
2203 return -EINVAL;
2204 break;
2205
2206 case SPEED_10:
2207 if (ecmd->duplex == DUPLEX_FULL)
2208 setting = SUPPORTED_10baseT_Full;
2209 else if (ecmd->duplex == DUPLEX_HALF)
2210 setting = SUPPORTED_10baseT_Half;
2211 else
2212 return -EINVAL;
2213 break;
2214 default:
2215 return -EINVAL;
2216 }
2217
2218 if ((setting & supported) == 0)
2219 return -EINVAL;
2220
2221 sky2->speed = ecmd->speed;
2222 sky2->duplex = ecmd->duplex;
2223 }
2224
2225 sky2->autoneg = ecmd->autoneg;
2226 sky2->advertising = ecmd->advertising;
2227
2228 if (netif_running(dev)) {
2229 sky2_down(dev);
2230 sky2_up(dev);
2231 }
2232
2233 return 0;
2234}
2235
2236static void sky2_get_drvinfo(struct net_device *dev,
2237 struct ethtool_drvinfo *info)
2238{
2239 struct sky2_port *sky2 = netdev_priv(dev);
2240
2241 strcpy(info->driver, DRV_NAME);
2242 strcpy(info->version, DRV_VERSION);
2243 strcpy(info->fw_version, "N/A");
2244 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2245}
2246
2247static const struct sky2_stat {
2248 char name[ETH_GSTRING_LEN];
2249 u16 offset;
2250} sky2_stats[] = {
2251 { "tx_bytes", GM_TXO_OK_HI },
2252 { "rx_bytes", GM_RXO_OK_HI },
2253 { "tx_broadcast", GM_TXF_BC_OK },
2254 { "rx_broadcast", GM_RXF_BC_OK },
2255 { "tx_multicast", GM_TXF_MC_OK },
2256 { "rx_multicast", GM_RXF_MC_OK },
2257 { "tx_unicast", GM_TXF_UC_OK },
2258 { "rx_unicast", GM_RXF_UC_OK },
2259 { "tx_mac_pause", GM_TXF_MPAUSE },
2260 { "rx_mac_pause", GM_RXF_MPAUSE },
2261 { "collisions", GM_TXF_SNG_COL },
2262 { "late_collision",GM_TXF_LAT_COL },
2263 { "aborted", GM_TXF_ABO_COL },
2264 { "multi_collisions", GM_TXF_MUL_COL },
2265 { "fifo_underrun", GM_TXE_FIFO_UR },
2266 { "fifo_overflow", GM_RXE_FIFO_OV },
2267 { "rx_toolong", GM_RXF_LNG_ERR },
2268 { "rx_jabber", GM_RXF_JAB_PKT },
2269 { "rx_runt", GM_RXE_FRAG },
2270 { "rx_too_long", GM_RXF_LNG_ERR },
2271 { "rx_fcs_error", GM_RXF_FCS_ERR },
2272};
2273
2274static u32 sky2_get_rx_csum(struct net_device *dev)
2275{
2276 struct sky2_port *sky2 = netdev_priv(dev);
2277
2278 return sky2->rx_csum;
2279}
2280
2281static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2282{
2283 struct sky2_port *sky2 = netdev_priv(dev);
2284
2285 sky2->rx_csum = data;
2286
2287 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2288 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2289
2290 return 0;
2291}
2292
2293static u32 sky2_get_msglevel(struct net_device *netdev)
2294{
2295 struct sky2_port *sky2 = netdev_priv(netdev);
2296 return sky2->msg_enable;
2297}
2298
2299static int sky2_nway_reset(struct net_device *dev)
2300{
2301 struct sky2_port *sky2 = netdev_priv(dev);
2302 struct sky2_hw *hw = sky2->hw;
2303
2304 if (sky2->autoneg != AUTONEG_ENABLE)
2305 return -EINVAL;
2306
2307 netif_stop_queue(dev);
2308
2309 spin_lock_irq(&hw->phy_lock);
2310 sky2_phy_reset(hw, sky2->port);
2311 sky2_phy_init(hw, sky2->port);
2312 spin_unlock_irq(&hw->phy_lock);
2313
2314 return 0;
2315}
2316
2317static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2318{
2319 struct sky2_hw *hw = sky2->hw;
2320 unsigned port = sky2->port;
2321 int i;
2322
2323 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2324 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2325 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2326 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2327
2328 for (i = 2; i < count; i++)
2329 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2330}
2331
2332static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2333{
2334 struct sky2_port *sky2 = netdev_priv(netdev);
2335 sky2->msg_enable = value;
2336}
2337
2338static int sky2_get_stats_count(struct net_device *dev)
2339{
2340 return ARRAY_SIZE(sky2_stats);
2341}
2342
2343static void sky2_get_ethtool_stats(struct net_device *dev,
2344 struct ethtool_stats *stats, u64 * data)
2345{
2346 struct sky2_port *sky2 = netdev_priv(dev);
2347
2348 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2349}
2350
2351static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2352{
2353 int i;
2354
2355 switch (stringset) {
2356 case ETH_SS_STATS:
2357 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2358 memcpy(data + i * ETH_GSTRING_LEN,
2359 sky2_stats[i].name, ETH_GSTRING_LEN);
2360 break;
2361 }
2362}
2363
2364/* Use hardware MIB variables for critical path statistics and
2365 * transmit feedback not reported at interrupt.
2366 * Other errors are accounted for in interrupt handler.
2367 */
2368static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2369{
2370 struct sky2_port *sky2 = netdev_priv(dev);
2371 u64 data[13];
2372
2373 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2374
2375 sky2->net_stats.tx_bytes = data[0];
2376 sky2->net_stats.rx_bytes = data[1];
2377 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2378 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2379 sky2->net_stats.multicast = data[5] + data[7];
2380 sky2->net_stats.collisions = data[10];
2381 sky2->net_stats.tx_aborted_errors = data[12];
2382
2383 return &sky2->net_stats;
2384}
2385
2386static int sky2_set_mac_address(struct net_device *dev, void *p)
2387{
2388 struct sky2_port *sky2 = netdev_priv(dev);
2389 struct sockaddr *addr = p;
2390 int err = 0;
2391
2392 if (!is_valid_ether_addr(addr->sa_data))
2393 return -EADDRNOTAVAIL;
2394
2395 sky2_down(dev);
2396 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2397 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2398 dev->dev_addr, ETH_ALEN);
2399 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2400 dev->dev_addr, ETH_ALEN);
2401 if (dev->flags & IFF_UP)
2402 err = sky2_up(dev);
2403 return err;
2404}
2405
2406static void sky2_set_multicast(struct net_device *dev)
2407{
2408 struct sky2_port *sky2 = netdev_priv(dev);
2409 struct sky2_hw *hw = sky2->hw;
2410 unsigned port = sky2->port;
2411 struct dev_mc_list *list = dev->mc_list;
2412 u16 reg;
2413 u8 filter[8];
2414
2415 memset(filter, 0, sizeof(filter));
2416
2417 reg = gma_read16(hw, port, GM_RX_CTRL);
2418 reg |= GM_RXCR_UCF_ENA;
2419
2420 if (dev->flags & IFF_PROMISC) /* promiscuous */
2421 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2422 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2423 memset(filter, 0xff, sizeof(filter));
2424 else if (dev->mc_count == 0) /* no multicast */
2425 reg &= ~GM_RXCR_MCF_ENA;
2426 else {
2427 int i;
2428 reg |= GM_RXCR_MCF_ENA;
2429
2430 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2431 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2432 filter[bit / 8] |= 1 << (bit % 8);
2433 }
2434 }
2435
2436 gma_write16(hw, port, GM_MC_ADDR_H1,
2437 (u16) filter[0] | ((u16) filter[1] << 8));
2438 gma_write16(hw, port, GM_MC_ADDR_H2,
2439 (u16) filter[2] | ((u16) filter[3] << 8));
2440 gma_write16(hw, port, GM_MC_ADDR_H3,
2441 (u16) filter[4] | ((u16) filter[5] << 8));
2442 gma_write16(hw, port, GM_MC_ADDR_H4,
2443 (u16) filter[6] | ((u16) filter[7] << 8));
2444
2445 gma_write16(hw, port, GM_RX_CTRL, reg);
2446}
2447
2448/* Can have one global because blinking is controlled by
2449 * ethtool and that is always under RTNL mutex
2450 */
2451static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2452{
2453 u16 pg;
2454
2455 spin_lock_bh(&hw->phy_lock);
2456 switch (hw->chip_id) {
2457 case CHIP_ID_YUKON_XL:
2458 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2459 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2460 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2461 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2462 PHY_M_LEDC_INIT_CTRL(7) |
2463 PHY_M_LEDC_STA1_CTRL(7) |
2464 PHY_M_LEDC_STA0_CTRL(7))
2465 : 0);
2466
2467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2468 break;
2469
2470 default:
2471 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2472 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2473 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2474 PHY_M_LED_MO_10(MO_LED_ON) |
2475 PHY_M_LED_MO_100(MO_LED_ON) |
2476 PHY_M_LED_MO_1000(MO_LED_ON) |
2477 PHY_M_LED_MO_RX(MO_LED_ON)
2478 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2479 PHY_M_LED_MO_10(MO_LED_OFF) |
2480 PHY_M_LED_MO_100(MO_LED_OFF) |
2481 PHY_M_LED_MO_1000(MO_LED_OFF) |
2482 PHY_M_LED_MO_RX(MO_LED_OFF));
2483
2484 }
2485 spin_unlock_bh(&hw->phy_lock);
2486}
2487
2488/* blink LED's for finding board */
2489static int sky2_phys_id(struct net_device *dev, u32 data)
2490{
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492 struct sky2_hw *hw = sky2->hw;
2493 unsigned port = sky2->port;
2494 u16 ledctrl, ledover = 0;
2495 long ms;
2496 int onoff = 1;
2497
2498 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2499 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2500 else
2501 ms = data * 1000;
2502
2503 /* save initial values */
2504 spin_lock_bh(&hw->phy_lock);
2505 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2506 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2508 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2510 } else {
2511 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2512 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2513 }
2514 spin_unlock_bh(&hw->phy_lock);
2515
2516 while (ms > 0) {
2517 sky2_led(hw, port, onoff);
2518 onoff = !onoff;
2519
2520 if (msleep_interruptible(250))
2521 break; /* interrupted */
2522 ms -= 250;
2523 }
2524
2525 /* resume regularly scheduled programming */
2526 spin_lock_bh(&hw->phy_lock);
2527 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2528 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2532 } else {
2533 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2534 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2535 }
2536 spin_unlock_bh(&hw->phy_lock);
2537
2538 return 0;
2539}
2540
2541static void sky2_get_pauseparam(struct net_device *dev,
2542 struct ethtool_pauseparam *ecmd)
2543{
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545
2546 ecmd->tx_pause = sky2->tx_pause;
2547 ecmd->rx_pause = sky2->rx_pause;
2548 ecmd->autoneg = sky2->autoneg;
2549}
2550
2551static int sky2_set_pauseparam(struct net_device *dev,
2552 struct ethtool_pauseparam *ecmd)
2553{
2554 struct sky2_port *sky2 = netdev_priv(dev);
2555 int err = 0;
2556
2557 sky2->autoneg = ecmd->autoneg;
2558 sky2->tx_pause = ecmd->tx_pause != 0;
2559 sky2->rx_pause = ecmd->rx_pause != 0;
2560
2561 if (netif_running(dev)) {
2562 sky2_down(dev);
2563 err = sky2_up(dev);
2564 }
2565
2566 return err;
2567}
2568
2569#ifdef CONFIG_PM
2570static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2571{
2572 struct sky2_port *sky2 = netdev_priv(dev);
2573
2574 wol->supported = WAKE_MAGIC;
2575 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2576}
2577
2578static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2579{
2580 struct sky2_port *sky2 = netdev_priv(dev);
2581 struct sky2_hw *hw = sky2->hw;
2582
2583 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2584 return -EOPNOTSUPP;
2585
2586 sky2->wol = wol->wolopts == WAKE_MAGIC;
2587
2588 if (sky2->wol) {
2589 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2590
2591 sky2_write16(hw, WOL_CTRL_STAT,
2592 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2593 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2594 } else
2595 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2596
2597 return 0;
2598}
2599#endif
2600
2601static void sky2_get_ringparam(struct net_device *dev,
2602 struct ethtool_ringparam *ering)
2603{
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605
2606 ering->rx_max_pending = RX_MAX_PENDING;
2607 ering->rx_mini_max_pending = 0;
2608 ering->rx_jumbo_max_pending = 0;
2609 ering->tx_max_pending = TX_RING_SIZE - 1;
2610
2611 ering->rx_pending = sky2->rx_pending;
2612 ering->rx_mini_pending = 0;
2613 ering->rx_jumbo_pending = 0;
2614 ering->tx_pending = sky2->tx_pending;
2615}
2616
2617static int sky2_set_ringparam(struct net_device *dev,
2618 struct ethtool_ringparam *ering)
2619{
2620 struct sky2_port *sky2 = netdev_priv(dev);
2621 int err = 0;
2622
2623 if (ering->rx_pending > RX_MAX_PENDING ||
2624 ering->rx_pending < 8 ||
2625 ering->tx_pending < MAX_SKB_TX_LE ||
2626 ering->tx_pending > TX_RING_SIZE - 1)
2627 return -EINVAL;
2628
2629 if (netif_running(dev))
2630 sky2_down(dev);
2631
2632 sky2->rx_pending = ering->rx_pending;
2633 sky2->tx_pending = ering->tx_pending;
2634
2635 if (netif_running(dev))
2636 err = sky2_up(dev);
2637
2638 return err;
2639}
2640
2641static int sky2_get_regs_len(struct net_device *dev)
2642{
2643 return 0x4000;
2644}
2645
2646/*
2647 * Returns copy of control register region
2648 * Note: access to the RAM address register set will cause timeouts.
2649 */
2650static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2651 void *p)
2652{
2653 const struct sky2_port *sky2 = netdev_priv(dev);
2654 const void __iomem *io = sky2->hw->regs;
2655
2656 BUG_ON(regs->len < B3_RI_WTO_R1);
2657 regs->version = 1;
2658 memset(p, 0, regs->len);
2659
2660 memcpy_fromio(p, io, B3_RAM_ADDR);
2661
2662 memcpy_fromio(p + B3_RI_WTO_R1,
2663 io + B3_RI_WTO_R1,
2664 regs->len - B3_RI_WTO_R1);
2665}
2666
2667static struct ethtool_ops sky2_ethtool_ops = {
2668 .get_settings = sky2_get_settings,
2669 .set_settings = sky2_set_settings,
2670 .get_drvinfo = sky2_get_drvinfo,
2671 .get_msglevel = sky2_get_msglevel,
2672 .set_msglevel = sky2_set_msglevel,
2673 .nway_reset = sky2_nway_reset,
2674 .get_regs_len = sky2_get_regs_len,
2675 .get_regs = sky2_get_regs,
2676 .get_link = ethtool_op_get_link,
2677 .get_sg = ethtool_op_get_sg,
2678 .set_sg = ethtool_op_set_sg,
2679 .get_tx_csum = ethtool_op_get_tx_csum,
2680 .set_tx_csum = ethtool_op_set_tx_csum,
2681 .get_tso = ethtool_op_get_tso,
2682 .set_tso = ethtool_op_set_tso,
2683 .get_rx_csum = sky2_get_rx_csum,
2684 .set_rx_csum = sky2_set_rx_csum,
2685 .get_strings = sky2_get_strings,
2686 .get_ringparam = sky2_get_ringparam,
2687 .set_ringparam = sky2_set_ringparam,
2688 .get_pauseparam = sky2_get_pauseparam,
2689 .set_pauseparam = sky2_set_pauseparam,
2690#ifdef CONFIG_PM
2691 .get_wol = sky2_get_wol,
2692 .set_wol = sky2_set_wol,
2693#endif
2694 .phys_id = sky2_phys_id,
2695 .get_stats_count = sky2_get_stats_count,
2696 .get_ethtool_stats = sky2_get_ethtool_stats,
2697 .get_perm_addr = ethtool_op_get_perm_addr,
2698};
2699
2700/* Initialize network device */
2701static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2702 unsigned port, int highmem)
2703{
2704 struct sky2_port *sky2;
2705 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2706
2707 if (!dev) {
2708 printk(KERN_ERR "sky2 etherdev alloc failed");
2709 return NULL;
2710 }
2711
2712 SET_MODULE_OWNER(dev);
2713 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2714 dev->open = sky2_up;
2715 dev->stop = sky2_down;
2716 dev->hard_start_xmit = sky2_xmit_frame;
2717 dev->get_stats = sky2_get_stats;
2718 dev->set_multicast_list = sky2_set_multicast;
2719 dev->set_mac_address = sky2_set_mac_address;
2720 dev->change_mtu = sky2_change_mtu;
2721 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2722 dev->tx_timeout = sky2_tx_timeout;
2723 dev->watchdog_timeo = TX_WATCHDOG;
2724 if (port == 0)
2725 dev->poll = sky2_poll;
2726 dev->weight = NAPI_WEIGHT;
2727#ifdef CONFIG_NET_POLL_CONTROLLER
2728 dev->poll_controller = sky2_netpoll;
2729#endif
2730
2731 sky2 = netdev_priv(dev);
2732 sky2->netdev = dev;
2733 sky2->hw = hw;
2734 sky2->msg_enable = netif_msg_init(debug, default_msg);
2735
2736 spin_lock_init(&sky2->tx_lock);
2737 /* Auto speed and flow control */
2738 sky2->autoneg = AUTONEG_ENABLE;
2739 sky2->tx_pause = 0;
2740 sky2->rx_pause = 1;
2741 sky2->duplex = -1;
2742 sky2->speed = -1;
2743 sky2->advertising = sky2_supported_modes(hw);
2744 sky2->rx_csum = 1;
2745 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2746 sky2->tx_pending = TX_DEF_PENDING;
2747 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2748
2749 hw->dev[port] = dev;
2750
2751 sky2->port = port;
2752
2753 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2754 if (highmem)
2755 dev->features |= NETIF_F_HIGHDMA;
2756 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2757
2758#ifdef SKY2_VLAN_TAG_USED
2759 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2760 dev->vlan_rx_register = sky2_vlan_rx_register;
2761 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2762#endif
2763
2764 /* read the mac address */
2765 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2766 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2767
2768 /* device is off until link detection */
2769 netif_carrier_off(dev);
2770 netif_stop_queue(dev);
2771
2772 return dev;
2773}
2774
2775static inline void sky2_show_addr(struct net_device *dev)
2776{
2777 const struct sky2_port *sky2 = netdev_priv(dev);
2778
2779 if (netif_msg_probe(sky2))
2780 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2781 dev->name,
2782 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2783 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2784}
2785
2786static int __devinit sky2_probe(struct pci_dev *pdev,
2787 const struct pci_device_id *ent)
2788{
2789 struct net_device *dev, *dev1 = NULL;
2790 struct sky2_hw *hw;
2791 int err, pm_cap, using_dac = 0;
2792
2793 err = pci_enable_device(pdev);
2794 if (err) {
2795 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2796 pci_name(pdev));
2797 goto err_out;
2798 }
2799
2800 err = pci_request_regions(pdev, DRV_NAME);
2801 if (err) {
2802 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2803 pci_name(pdev));
2804 goto err_out;
2805 }
2806
2807 pci_set_master(pdev);
2808
2809 /* Find power-management capability. */
2810 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2811 if (pm_cap == 0) {
2812 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2813 "aborting.\n");
2814 err = -EIO;
2815 goto err_out_free_regions;
2816 }
2817
2818 if (sizeof(dma_addr_t) > sizeof(u32)) {
2819 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2820 if (!err)
2821 using_dac = 1;
2822 }
2823
2824 if (!using_dac) {
2825 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2826 if (err) {
2827 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2828 pci_name(pdev));
2829 goto err_out_free_regions;
2830 }
2831 }
2832#ifdef __BIG_ENDIAN
2833 /* byte swap descriptors in hardware */
2834 {
2835 u32 reg;
2836
2837 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2838 reg |= PCI_REV_DESC;
2839 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2840 }
2841#endif
2842
2843 err = -ENOMEM;
2844 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2845 if (!hw) {
2846 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2847 pci_name(pdev));
2848 goto err_out_free_regions;
2849 }
2850
2851 memset(hw, 0, sizeof(*hw));
2852 hw->pdev = pdev;
2853 spin_lock_init(&hw->phy_lock);
2854
2855 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2856 if (!hw->regs) {
2857 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2858 pci_name(pdev));
2859 goto err_out_free_hw;
2860 }
2861 hw->pm_cap = pm_cap;
2862
2863 err = sky2_reset(hw);
2864 if (err)
2865 goto err_out_iounmap;
2866
2867 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2868 pci_resource_start(pdev, 0), pdev->irq,
2869 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2870 hw->chip_id, hw->chip_rev);
2871
2872 dev = sky2_init_netdev(hw, 0, using_dac);
2873 if (!dev)
2874 goto err_out_free_pci;
2875
2876 err = register_netdev(dev);
2877 if (err) {
2878 printk(KERN_ERR PFX "%s: cannot register net device\n",
2879 pci_name(pdev));
2880 goto err_out_free_netdev;
2881 }
2882
2883 sky2_show_addr(dev);
2884
2885 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2886 if (register_netdev(dev1) == 0)
2887 sky2_show_addr(dev1);
2888 else {
2889 /* Failure to register second port need not be fatal */
2890 printk(KERN_WARNING PFX
2891 "register of second port failed\n");
2892 hw->dev[1] = NULL;
2893 free_netdev(dev1);
2894 }
2895 }
2896
2897 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2898 if (err) {
2899 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2900 pci_name(pdev), pdev->irq);
2901 goto err_out_unregister;
2902 }
2903
2904 hw->intr_mask = Y2_IS_BASE;
2905 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2906
2907 pci_set_drvdata(pdev, hw);
2908
2909 return 0;
2910
2911err_out_unregister:
2912 if (dev1) {
2913 unregister_netdev(dev1);
2914 free_netdev(dev1);
2915 }
2916 unregister_netdev(dev);
2917err_out_free_netdev:
2918 free_netdev(dev);
2919err_out_free_pci:
2920 sky2_write8(hw, B0_CTST, CS_RST_SET);
2921 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2922err_out_iounmap:
2923 iounmap(hw->regs);
2924err_out_free_hw:
2925 kfree(hw);
2926err_out_free_regions:
2927 pci_release_regions(pdev);
2928 pci_disable_device(pdev);
2929err_out:
2930 return err;
2931}
2932
2933static void __devexit sky2_remove(struct pci_dev *pdev)
2934{
2935 struct sky2_hw *hw = pci_get_drvdata(pdev);
2936 struct net_device *dev0, *dev1;
2937
2938 if (!hw)
2939 return;
2940
2941 dev0 = hw->dev[0];
2942 dev1 = hw->dev[1];
2943 if (dev1)
2944 unregister_netdev(dev1);
2945 unregister_netdev(dev0);
2946
2947 sky2_write32(hw, B0_IMSK, 0);
2948 sky2_set_power_state(hw, PCI_D3hot);
2949 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2950 sky2_write8(hw, B0_CTST, CS_RST_SET);
2951 sky2_read8(hw, B0_CTST);
2952
2953 free_irq(pdev->irq, hw);
2954 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2955 pci_release_regions(pdev);
2956 pci_disable_device(pdev);
2957
2958 if (dev1)
2959 free_netdev(dev1);
2960 free_netdev(dev0);
2961 iounmap(hw->regs);
2962 kfree(hw);
2963
2964 pci_set_drvdata(pdev, NULL);
2965}
2966
2967#ifdef CONFIG_PM
2968static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2969{
2970 struct sky2_hw *hw = pci_get_drvdata(pdev);
2971 int i;
2972
2973 for (i = 0; i < 2; i++) {
2974 struct net_device *dev = hw->dev[i];
2975
2976 if (dev) {
2977 if (!netif_running(dev))
2978 continue;
2979
2980 sky2_down(dev);
2981 netif_device_detach(dev);
2982 }
2983 }
2984
2985 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
2986}
2987
2988static int sky2_resume(struct pci_dev *pdev)
2989{
2990 struct sky2_hw *hw = pci_get_drvdata(pdev);
2991 int i;
2992
2993 pci_restore_state(pdev);
2994 pci_enable_wake(pdev, PCI_D0, 0);
2995 sky2_set_power_state(hw, PCI_D0);
2996
2997 sky2_reset(hw);
2998
2999 for (i = 0; i < 2; i++) {
3000 struct net_device *dev = hw->dev[i];
3001 if (dev) {
3002 if (netif_running(dev)) {
3003 netif_device_attach(dev);
3004 sky2_up(dev);
3005 }
3006 }
3007 }
3008 return 0;
3009}
3010#endif
3011
3012static struct pci_driver sky2_driver = {
3013 .name = DRV_NAME,
3014 .id_table = sky2_id_table,
3015 .probe = sky2_probe,
3016 .remove = __devexit_p(sky2_remove),
3017#ifdef CONFIG_PM
3018 .suspend = sky2_suspend,
3019 .resume = sky2_resume,
3020#endif
3021};
3022
3023static int __init sky2_init_module(void)
3024{
3025 return pci_module_init(&sky2_driver);
3026}
3027
3028static void __exit sky2_cleanup_module(void)
3029{
3030 pci_unregister_driver(&sky2_driver);
3031}
3032
3033module_init(sky2_init_module);
3034module_exit(sky2_cleanup_module);
3035
3036MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3037MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3038MODULE_LICENSE("GPL");
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
new file mode 100644
index 000000000000..629d08f170fd
--- /dev/null
+++ b/drivers/net/sky2.h
@@ -0,0 +1,1910 @@
1/*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4#ifndef _SKY2_H
5#define _SKY2_H
6
7/* PCI config registers */
8#define PCI_DEV_REG1 0x40
9#define PCI_DEV_REG2 0x44
10#define PCI_DEV_STATUS 0x7c
11#define PCI_OS_PCI_X (1<<26)
12
13#define PEX_LNK_STAT 0xf2
14#define PEX_UNC_ERR_STAT 0x104
15#define PEX_DEV_CTRL 0xe8
16
17/* Yukon-2 */
18enum pci_dev_reg_1 {
19 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
20 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
21 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
22 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
23 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
24 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
25};
26
27enum pci_dev_reg_2 {
28 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
29 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
30 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
31
32 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
33 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
34 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
35 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
36
37 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
38};
39
40
41#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
42 PCI_STATUS_SIG_SYSTEM_ERROR | \
43 PCI_STATUS_REC_MASTER_ABORT | \
44 PCI_STATUS_REC_TARGET_ABORT | \
45 PCI_STATUS_PARITY)
46
47enum pex_dev_ctrl {
48 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
49 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
50 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
51 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
52 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
53 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
54 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
55 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
56 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
57 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
58 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
59};
60#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
61
62/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
63enum pex_err {
64 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
65
66 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
67
68 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
69
70 PEX_COMP_TO = 1<<14, /* Completion Timeout */
71 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
72 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
73
74 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
75 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
76};
77
78
79enum csr_regs {
80 B0_RAP = 0x0000,
81 B0_CTST = 0x0004,
82 B0_Y2LED = 0x0005,
83 B0_POWER_CTRL = 0x0007,
84 B0_ISRC = 0x0008,
85 B0_IMSK = 0x000c,
86 B0_HWE_ISRC = 0x0010,
87 B0_HWE_IMSK = 0x0014,
88
89 /* Special ISR registers (Yukon-2 only) */
90 B0_Y2_SP_ISRC2 = 0x001c,
91 B0_Y2_SP_ISRC3 = 0x0020,
92 B0_Y2_SP_EISR = 0x0024,
93 B0_Y2_SP_LISR = 0x0028,
94 B0_Y2_SP_ICR = 0x002c,
95
96 B2_MAC_1 = 0x0100,
97 B2_MAC_2 = 0x0108,
98 B2_MAC_3 = 0x0110,
99 B2_CONN_TYP = 0x0118,
100 B2_PMD_TYP = 0x0119,
101 B2_MAC_CFG = 0x011a,
102 B2_CHIP_ID = 0x011b,
103 B2_E_0 = 0x011c,
104
105 B2_Y2_CLK_GATE = 0x011d,
106 B2_Y2_HW_RES = 0x011e,
107 B2_E_3 = 0x011f,
108 B2_Y2_CLK_CTRL = 0x0120,
109
110 B2_TI_INI = 0x0130,
111 B2_TI_VAL = 0x0134,
112 B2_TI_CTRL = 0x0138,
113 B2_TI_TEST = 0x0139,
114
115 B2_TST_CTRL1 = 0x0158,
116 B2_TST_CTRL2 = 0x0159,
117 B2_GP_IO = 0x015c,
118
119 B2_I2C_CTRL = 0x0160,
120 B2_I2C_DATA = 0x0164,
121 B2_I2C_IRQ = 0x0168,
122 B2_I2C_SW = 0x016c,
123
124 B3_RAM_ADDR = 0x0180,
125 B3_RAM_DATA_LO = 0x0184,
126 B3_RAM_DATA_HI = 0x0188,
127
128/* RAM Interface Registers */
129/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
130/*
131 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
132 * not usable in SW. Please notice these are NOT real timeouts, these are
133 * the number of qWords transferred continuously.
134 */
135#define RAM_BUFFER(port, reg) (reg | (port <<6))
136
137 B3_RI_WTO_R1 = 0x0190,
138 B3_RI_WTO_XA1 = 0x0191,
139 B3_RI_WTO_XS1 = 0x0192,
140 B3_RI_RTO_R1 = 0x0193,
141 B3_RI_RTO_XA1 = 0x0194,
142 B3_RI_RTO_XS1 = 0x0195,
143 B3_RI_WTO_R2 = 0x0196,
144 B3_RI_WTO_XA2 = 0x0197,
145 B3_RI_WTO_XS2 = 0x0198,
146 B3_RI_RTO_R2 = 0x0199,
147 B3_RI_RTO_XA2 = 0x019a,
148 B3_RI_RTO_XS2 = 0x019b,
149 B3_RI_TO_VAL = 0x019c,
150 B3_RI_CTRL = 0x01a0,
151 B3_RI_TEST = 0x01a2,
152 B3_MA_TOINI_RX1 = 0x01b0,
153 B3_MA_TOINI_RX2 = 0x01b1,
154 B3_MA_TOINI_TX1 = 0x01b2,
155 B3_MA_TOINI_TX2 = 0x01b3,
156 B3_MA_TOVAL_RX1 = 0x01b4,
157 B3_MA_TOVAL_RX2 = 0x01b5,
158 B3_MA_TOVAL_TX1 = 0x01b6,
159 B3_MA_TOVAL_TX2 = 0x01b7,
160 B3_MA_TO_CTRL = 0x01b8,
161 B3_MA_TO_TEST = 0x01ba,
162 B3_MA_RCINI_RX1 = 0x01c0,
163 B3_MA_RCINI_RX2 = 0x01c1,
164 B3_MA_RCINI_TX1 = 0x01c2,
165 B3_MA_RCINI_TX2 = 0x01c3,
166 B3_MA_RCVAL_RX1 = 0x01c4,
167 B3_MA_RCVAL_RX2 = 0x01c5,
168 B3_MA_RCVAL_TX1 = 0x01c6,
169 B3_MA_RCVAL_TX2 = 0x01c7,
170 B3_MA_RC_CTRL = 0x01c8,
171 B3_MA_RC_TEST = 0x01ca,
172 B3_PA_TOINI_RX1 = 0x01d0,
173 B3_PA_TOINI_RX2 = 0x01d4,
174 B3_PA_TOINI_TX1 = 0x01d8,
175 B3_PA_TOINI_TX2 = 0x01dc,
176 B3_PA_TOVAL_RX1 = 0x01e0,
177 B3_PA_TOVAL_RX2 = 0x01e4,
178 B3_PA_TOVAL_TX1 = 0x01e8,
179 B3_PA_TOVAL_TX2 = 0x01ec,
180 B3_PA_CTRL = 0x01f0,
181 B3_PA_TEST = 0x01f2,
182
183 Y2_CFG_SPC = 0x1c00,
184};
185
186/* B0_CTST 16 bit Control/Status register */
187enum {
188 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
189 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
190 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
191 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
192 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
193 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
194 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
195 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
196
197 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
198 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
199 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
200 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
201 CS_MRST_CLR = 1<<3, /* Clear Master reset */
202 CS_MRST_SET = 1<<2, /* Set Master reset */
203 CS_RST_CLR = 1<<1, /* Clear Software reset */
204 CS_RST_SET = 1, /* Set Software reset */
205};
206
207/* B0_LED 8 Bit LED register */
208enum {
209/* Bit 7.. 2: reserved */
210 LED_STAT_ON = 1<<1, /* Status LED on */
211 LED_STAT_OFF = 1, /* Status LED off */
212};
213
214/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
215enum {
216 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
217 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
218 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
219 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
220 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
221 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
222 PC_VCC_ON = 1<<1, /* Switch VCC On */
223 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
224};
225
226/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
227
228/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
229/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
230/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
231/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
232enum {
233 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
234 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
235 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
236
237 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
238 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
239 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
240 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
241
242 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
243 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
244 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
245 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
246 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
247
248 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
249 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
250 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
251 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
252 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
253
254 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
255 Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
256 Y2_IS_IRQ_SW | Y2_IS_TIMINT,
257 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
258 Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
259 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
260 Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
261};
262
263/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
264enum {
265 IS_ERR_MSK = 0x00003fff,/* All Error bits */
266
267 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
268 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
269 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
270 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
271 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
272 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
273 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
274 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
275 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
276 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
277 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
278 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
279 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
280 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
281};
282
283/* Hardware error interrupt mask for Yukon 2 */
284enum {
285 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
286 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
287 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
288 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
289 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
290 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
291 /* Link 2 */
292 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
293 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
294 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
295 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
296 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
297 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
298 /* Link 1 */
299 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
300 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
301 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
302 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
303 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
304 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
305
306 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
307 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
308 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
309 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
310
311 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
312 Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |
313 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
314};
315
316/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
317enum {
318 DPT_START = 1<<1,
319 DPT_STOP = 1<<0,
320};
321
322/* B2_TST_CTRL1 8 bit Test Control Register 1 */
323enum {
324 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
325 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
326 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
327 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
328 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
329 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
330 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
331 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
332};
333
334/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
335enum {
336 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
337 /* Bit 3.. 2: reserved */
338 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
339 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
340};
341
342/* B2_CHIP_ID 8 bit Chip Identification Number */
343enum {
344 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
345 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
346 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
347 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
348 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
349 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
350 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
351
352 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
353 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
354 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
355};
356
357/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
358enum {
359 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
360 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
361 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
362 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
363 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
364 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
365 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
366 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
367};
368
369/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
370enum {
371 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
372 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
373 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
374};
375#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
376#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
377
378
379/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
380enum {
381 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
382#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
383 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
384 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
385#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
386#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
387 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
388 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
389};
390
391/* B2_TI_CTRL 8 bit Timer control */
392/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
393enum {
394 TIM_START = 1<<2, /* Start Timer */
395 TIM_STOP = 1<<1, /* Stop Timer */
396 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
397};
398
399/* B2_TI_TEST 8 Bit Timer Test */
400/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
401/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
402enum {
403 TIM_T_ON = 1<<2, /* Test mode on */
404 TIM_T_OFF = 1<<1, /* Test mode off */
405 TIM_T_STEP = 1<<0, /* Test step */
406};
407
408/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
409 /* Bit 31..19: reserved */
410#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
411/* RAM Interface Registers */
412
413/* B3_RI_CTRL 16 bit RAM Interface Control Register */
414enum {
415 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
416 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
417
418 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
419 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
420};
421
422#define SK_RI_TO_53 36 /* RAM interface timeout */
423
424
425/* Port related registers FIFO, and Arbiter */
426#define SK_REG(port,reg) (((port)<<7)+(reg))
427
428/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
429/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
430/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
431/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
432/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
433
434#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
435
436/* TXA_CTRL 8 bit Tx Arbiter Control Register */
437enum {
438 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
439 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
440 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
441 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
442 TXA_START_RC = 1<<3, /* Start sync Rate Control */
443 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
444 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
445 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
446};
447
448/*
449 * Bank 4 - 5
450 */
451/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
452enum {
453 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
454 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
455 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
456 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
457 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
458 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
459 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
460};
461
462
463enum {
464 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
465 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
466 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
467 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
468 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
469 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
470 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
471 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
472 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
473};
474
475/* Queue Register Offsets, use Q_ADDR() to access */
476enum {
477 B8_Q_REGS = 0x0400, /* base of Queue registers */
478 Q_D = 0x00, /* 8*32 bit Current Descriptor */
479 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
480 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
481 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
482 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
483 Q_BC = 0x30, /* 32 bit Current Byte Counter */
484 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
485 Q_F = 0x38, /* 32 bit Flag Register */
486 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
487 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
488 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
489 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
490 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
491 Q_T2 = 0x40, /* 32 bit Test Register 2 */
492 Q_T3 = 0x44, /* 32 bit Test Register 3 */
493
494/* Yukon-2 */
495 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
496 Q_WM = 0x40, /* 16 bit FIFO Watermark */
497 Q_AL = 0x42, /* 8 bit FIFO Alignment */
498 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
499 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
500 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
501 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
502 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
503 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
504 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
505 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
506};
507#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
508
509
510/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
511enum {
512 Y2_B8_PREF_REGS = 0x0450,
513
514 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
515 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
516 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
517 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
518 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
519 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
520 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
521 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
522 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
523 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
524
525 PREF_UNIT_MASK_IDX = 0x0fff,
526};
527#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
528
529/* RAM Buffer Register Offsets */
530enum {
531
532 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
533 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
534 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
535 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
536 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
537 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
538 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
539 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
540 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
541 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
542 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
543 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
544 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
545 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
546};
547
548/* Receive and Transmit Queues */
549enum {
550 Q_R1 = 0x0000, /* Receive Queue 1 */
551 Q_R2 = 0x0080, /* Receive Queue 2 */
552 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
553 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
554 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
555 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
556};
557
558/* Different PHY Types */
559enum {
560 PHY_ADDR_MARV = 0,
561};
562
563#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
564
565
566enum {
567 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
568 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
569 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
570 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
571
572 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
573
574/* Receive GMAC FIFO (YUKON and Yukon-2) */
575
576 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
577 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
578 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
579 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
580 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
581 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
582
583 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
584 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
585
586 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
587
588 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
589
590 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
591};
592
593
594/* Q_BC 32 bit Current Byte Counter */
595
596/* BMU Control Status Registers */
597/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
598/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
599/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
600/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
601/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
602/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
603/* Q_CSR 32 bit BMU Control/Status Register */
604
605/* Rx BMU Control / Status Registers (Yukon-2) */
606enum {
607 BMU_IDLE = 1<<31, /* BMU Idle State */
608 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
609 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
610
611 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
612 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
613 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
614 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
615 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
616 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
617 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
618 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
619 BMU_START = 1<<8, /* Start Rx/Tx Queue */
620 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
621 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
622 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
623 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
624 BMU_OP_ON = 1<<3, /* BMU Operational On */
625 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
626 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
627 BMU_RST_SET = 1<<0, /* Set BMU Reset */
628
629 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
630 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
631 BMU_FIFO_ENA | BMU_OP_ON,
632};
633
634/* Tx BMU Control / Status Registers (Yukon-2) */
635 /* Bit 31: same as for Rx */
636enum {
637 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
638 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
639 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
640};
641
642/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
643/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
644enum {
645 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
646 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
647 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
648 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
649};
650
651/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
652/* RB_START 32 bit RAM Buffer Start Address */
653/* RB_END 32 bit RAM Buffer End Address */
654/* RB_WP 32 bit RAM Buffer Write Pointer */
655/* RB_RP 32 bit RAM Buffer Read Pointer */
656/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
657/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
658/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
659/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
660/* RB_PC 32 bit RAM Buffer Packet Counter */
661/* RB_LEV 32 bit RAM Buffer Level Register */
662
663#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
664/* RB_TST2 8 bit RAM Buffer Test Register 2 */
665/* RB_TST1 8 bit RAM Buffer Test Register 1 */
666
667/* RB_CTRL 8 bit RAM Buffer Control Register */
668enum {
669 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
670 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
671 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
672 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
673 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
674 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
675};
676
677
678/* Transmit GMAC FIFO (YUKON only) */
679enum {
680 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
681 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
682 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
683
684 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
685 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
686 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
687
688 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
689 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
690 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
691};
692
693/* Descriptor Poll Timer Registers */
694enum {
695 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
696 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
697 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
698
699 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
700};
701
702/* Time Stamp Timer Registers (YUKON only) */
703enum {
704 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
705 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
706 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
707};
708
709/* Polling Unit Registers (Yukon-2 only) */
710enum {
711 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
712 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
713
714 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
715 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
716};
717
718/* ASF Subsystem Registers (Yukon-2 only) */
719enum {
720 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
721 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
722 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
723
724 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
725 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
726 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
727 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
728 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
729 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
730};
731
732/* Status BMU Registers (Yukon-2 only)*/
733enum {
734 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
735 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
736
737 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
738 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
739 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
740 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
741 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
742 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
743 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
744 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
745
746/* FIFO Control/Status Registers (Yukon-2 only)*/
747 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
748 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
749 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
750 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
751 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
752 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
753 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
754
755/* Level and ISR Timer Registers (Yukon-2 only)*/
756 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
757 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
758 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
759 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
760 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
761 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
762 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
763 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
764 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
765 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
766 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
767 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
768};
769
770enum {
771 LINKLED_OFF = 0x01,
772 LINKLED_ON = 0x02,
773 LINKLED_LINKSYNC_OFF = 0x04,
774 LINKLED_LINKSYNC_ON = 0x08,
775 LINKLED_BLINK_OFF = 0x10,
776 LINKLED_BLINK_ON = 0x20,
777};
778
779/* GMAC and GPHY Control Registers (YUKON only) */
780enum {
781 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
782 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
783 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
784 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
785 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
786
787/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
788
789 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
790
791 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
792 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
793 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
794 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
795 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
796 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
797 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
798
799/* WOL Pattern Length Registers (YUKON only) */
800
801 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
802 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
803
804/* WOL Pattern Counter Registers (YUKON only) */
805
806
807 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
808 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
809};
810
811enum {
812 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
813 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
814};
815
816enum {
817 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
818 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
819};
820
821/*
822 * Marvel-PHY Registers, indirect addressed over GMAC
823 */
824enum {
825 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
826 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
827 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
828 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
829 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
830 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
831 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
832 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
833 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
834 /* Marvel-specific registers */
835 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
836 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
837 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
838 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
839 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
840 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
841 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
842 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
843 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
844 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
845 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
846 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
847 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
848 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
849 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
850 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
851 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
852 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
853
854/* for 10/100 Fast Ethernet PHY (88E3082 only) */
855 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
856 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
857 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
858 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
859 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
860};
861
862enum {
863 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
864 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
865 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
866 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
867 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
868 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
869 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
870 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
871 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
872 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
873};
874
875enum {
876 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
877 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
878 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
879};
880
881enum {
882 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
883
884 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
885 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
886 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
887 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
888 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
889 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
890 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
891};
892
893enum {
894 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
895 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
896 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
897};
898
899/* different Marvell PHY Ids */
900enum {
901 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
902
903 PHY_BCOM_ID1_A1 = 0x6041,
904 PHY_BCOM_ID1_B2 = 0x6043,
905 PHY_BCOM_ID1_C0 = 0x6044,
906 PHY_BCOM_ID1_C5 = 0x6047,
907
908 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
909 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
910 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
911 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
912};
913
914/* Advertisement register bits */
915enum {
916 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
917 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
918 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
919
920 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
921 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
922 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
923 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
924 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
925 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
926 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
927 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
928 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
929 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
930 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
931 PHY_AN_100HALF | PHY_AN_100FULL,
932};
933
934/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
935/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
936enum {
937 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
938 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
939 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
940 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
941 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
942 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
943 /* Bit 9..8: reserved */
944 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
945};
946
947/** Marvell-Specific */
948enum {
949 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
950 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
951 PHY_M_AN_RF = 1<<13, /* Remote Fault */
952
953 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
954 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
955 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
956 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
957 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
958 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
959 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
960 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
961};
962
963/* special defines for FIBER (88E1011S only) */
964enum {
965 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
966 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
967 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
968 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
969};
970
971/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
972enum {
973 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
974 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
975 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
976 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
977};
978
979/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
980enum {
981 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
982 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
983 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
984 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
985 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
986 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
987};
988
989/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
990enum {
991 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
992 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
993 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
994 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
995 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
996 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
997 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
998 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
999 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1000 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1001 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1002 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1003};
1004
1005enum {
1006 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1007 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1008};
1009
1010#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1011
1012enum {
1013 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1014 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1015 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1016};
1017
1018/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1019enum {
1020 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1021 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1022 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1023 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1024 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1025
1026 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1027 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1028
1029 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1030 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1031};
1032
1033/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1034enum {
1035 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1036 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1037 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1038 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1039 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1040 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1041 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1042 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1043 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1044 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1045 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1046 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1047 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1048 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1049 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1050 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1051};
1052
1053#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1054
1055/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1056enum {
1057 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1058 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1059};
1060
1061enum {
1062 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1063 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1064 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1065 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1066 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1067 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1068 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1069 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1070 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1071 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1072 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1073 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1074
1075 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1076 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1077 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1078
1079 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1080 | PHY_M_IS_FIFO_ERROR,
1081 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1082};
1083
1084
1085/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1086enum {
1087 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1088 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1089
1090 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1091 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1092 /* (88E1011 only) */
1093 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1094 /* (88E1011 only) */
1095 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1096 /* (88E1111 only) */
1097 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1098 /* !!! Errata in spec. (1 = disable) */
1099 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1100 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1101 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1102 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1103 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1104 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1105
1106#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1107 /* 00=1x; 01=2x; 10=3x; 11=4x */
1108#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1109 /* 00=dis; 01=1x; 10=2x; 11=3x */
1110#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1111 /* 000=1x; 001=2x; 010=3x; 011=4x */
1112#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1113 /* 01X=0; 110=2.5; 111=25 (MHz) */
1114
1115/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1116enum {
1117 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1118 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1119 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1120};
1121/* !!! Errata in spec. (1 = disable) */
1122
1123#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1124 /* 100=5x; 101=6x; 110=7x; 111=8x */
1125enum {
1126 MAC_TX_CLK_0_MHZ = 2,
1127 MAC_TX_CLK_2_5_MHZ = 6,
1128 MAC_TX_CLK_25_MHZ = 7,
1129};
1130
1131/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1132enum {
1133 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1134 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1135 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1136 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1137 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1138 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1139 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1140 /* (88E1111 only) */
1141};
1142
1143enum {
1144 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1145 /* (88E1011 only) */
1146 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1147 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1148 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1149 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1150 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1151};
1152
1153#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1154
1155/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1156enum {
1157 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1158 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1159 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1160 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1161 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1162 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1163};
1164
1165#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1166#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1167#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1168#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1169#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1170#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1171
1172enum {
1173 PULS_NO_STR = 0,/* no pulse stretching */
1174 PULS_21MS = 1,/* 21 ms to 42 ms */
1175 PULS_42MS = 2,/* 42 ms to 84 ms */
1176 PULS_84MS = 3,/* 84 ms to 170 ms */
1177 PULS_170MS = 4,/* 170 ms to 340 ms */
1178 PULS_340MS = 5,/* 340 ms to 670 ms */
1179 PULS_670MS = 6,/* 670 ms to 1.3 s */
1180 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1181};
1182
1183#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1184
1185enum {
1186 BLINK_42MS = 0,/* 42 ms */
1187 BLINK_84MS = 1,/* 84 ms */
1188 BLINK_170MS = 2,/* 170 ms */
1189 BLINK_340MS = 3,/* 340 ms */
1190 BLINK_670MS = 4,/* 670 ms */
1191};
1192
1193/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1194#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1195 /* Bit 13..12: reserved */
1196#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1197#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1198#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1199#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1200#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1201#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1202
1203enum {
1204 MO_LED_NORM = 0,
1205 MO_LED_BLINK = 1,
1206 MO_LED_OFF = 2,
1207 MO_LED_ON = 3,
1208};
1209
1210/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1211enum {
1212 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1213 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1214 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1215 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1216 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1217};
1218
1219/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1220enum {
1221 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1222 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1223 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1224 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1225 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1226 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1227 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1228 /* (88E1111 only) */
1229
1230 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1231 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1232 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1233};
1234
1235/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1236/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1237 /* Bit 15..12: reserved (used internally) */
1238enum {
1239 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1240 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1241 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1242};
1243
1244#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1245#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1246#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1247
1248enum {
1249 LED_PAR_CTRL_COLX = 0x00,
1250 LED_PAR_CTRL_ERROR = 0x01,
1251 LED_PAR_CTRL_DUPLEX = 0x02,
1252 LED_PAR_CTRL_DP_COL = 0x03,
1253 LED_PAR_CTRL_SPEED = 0x04,
1254 LED_PAR_CTRL_LINK = 0x05,
1255 LED_PAR_CTRL_TX = 0x06,
1256 LED_PAR_CTRL_RX = 0x07,
1257 LED_PAR_CTRL_ACT = 0x08,
1258 LED_PAR_CTRL_LNK_RX = 0x09,
1259 LED_PAR_CTRL_LNK_AC = 0x0a,
1260 LED_PAR_CTRL_ACT_BL = 0x0b,
1261 LED_PAR_CTRL_TX_BL = 0x0c,
1262 LED_PAR_CTRL_RX_BL = 0x0d,
1263 LED_PAR_CTRL_COL_BL = 0x0e,
1264 LED_PAR_CTRL_INACT = 0x0f
1265};
1266
1267/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1268enum {
1269 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1270 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1271 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1272};
1273
1274/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1275/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1276enum {
1277 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1278 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1279 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1280 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1281};
1282#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1283
1284/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1285enum {
1286 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1287 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1288 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1289 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1290};
1291
1292#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1293#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1294#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1295#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1296
1297/* GMAC registers */
1298/* Port Registers */
1299enum {
1300 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1301 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1302 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1303 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1304 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1305 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1306 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1307/* Source Address Registers */
1308 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1309 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1310 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1311 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1312 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1313 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1314
1315/* Multicast Address Hash Registers */
1316 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1317 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1318 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1319 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1320
1321/* Interrupt Source Registers */
1322 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1323 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1324 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1325
1326/* Interrupt Mask Registers */
1327 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1328 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1329 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1330
1331/* Serial Management Interface (SMI) Registers */
1332 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1333 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1334 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1335};
1336
1337/* MIB Counters */
1338#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1339#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1340
1341/*
1342 * MIB Counters base address definitions (low word) -
1343 * use offset 4 for access to high word (32 bit r/o)
1344 */
1345enum {
1346 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1347 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1348 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1349 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1350 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1351 /* GM_MIB_CNT_BASE + 40: reserved */
1352 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1353 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1354 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1355 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1356 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1357 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1358 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1359 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1360 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1361 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1362 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1363 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1364 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1365 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1366 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1367 /* GM_MIB_CNT_BASE + 168: reserved */
1368 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1369 /* GM_MIB_CNT_BASE + 184: reserved */
1370 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1371 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1372 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1373 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1374 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1375 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1376 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1377 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1378 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1379 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1380 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1381 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1382 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1383
1384 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1385 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1386 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1387 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1388 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1389 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1390};
1391
1392/* GMAC Bit Definitions */
1393/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1394enum {
1395 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1396 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1397 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1398 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1399 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1400 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1401 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1402 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1403
1404 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1405 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1406 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1407 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1408 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1409};
1410
1411/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1412enum {
1413 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1414 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1415 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1416 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1417 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1418 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1419 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1420 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1421 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1422 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1423 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1424 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1425 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1426 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1427 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1428};
1429
1430#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1431#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1432
1433/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1434enum {
1435 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1436 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1437 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1438 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1439};
1440
1441#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1442#define TX_COL_DEF 0x04
1443
1444/* GM_RX_CTRL 16 bit r/w Receive Control Register */
1445enum {
1446 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1447 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1448 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1449 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1450};
1451
1452/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1453enum {
1454 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1455 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1456 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1457 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1458
1459 TX_JAM_LEN_DEF = 0x03,
1460 TX_JAM_IPG_DEF = 0x0b,
1461 TX_IPG_JAM_DEF = 0x1c,
1462 TX_BOF_LIM_DEF = 0x04,
1463};
1464
1465#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1466#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1467#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1468#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1469
1470
1471/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1472enum {
1473 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1474 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1475 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1476 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1477 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1478};
1479
1480#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1481#define DATA_BLIND_DEF 0x04
1482
1483#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1484#define IPG_DATA_DEF 0x1e
1485
1486/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1487enum {
1488 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1489 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1490 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1491 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1492 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1493};
1494
1495#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1496#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1497
1498/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1499enum {
1500 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1501 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1502};
1503
1504/* Receive Frame Status Encoding */
1505enum {
1506 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1507 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1508 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1509 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1510 GMR_FS_MC = 1<<10, /* Multicast Packet */
1511 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1512 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1513 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1514 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1515 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1516 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1517 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1518
1519 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1520 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1521
1522 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1523 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1524 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1525 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1526};
1527
1528/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1529enum {
1530 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1531 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1532 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1533 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1534
1535 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1536 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1537 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1538
1539 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1540 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1541 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1542 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1543 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1544 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1545 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1546
1547 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1548 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1549 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1550 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1551
1552 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1553
1554 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1555};
1556
1557
1558/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1559enum {
1560 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1561 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1562
1563 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1564 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1565 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1566
1567 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1568 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1569 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1570};
1571
1572/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1573enum {
1574 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1575 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1576 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1577};
1578
1579/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1580enum {
1581 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1582 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1583 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1584 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1585 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1586
1587 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1588 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1589};
1590
1591/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1592enum {
1593 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1594 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1595};
1596
1597/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1598enum {
1599 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1600 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1601 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1602 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1603 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1604};
1605
1606/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1607enum {
1608 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1609 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1610 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1611 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1612 GMC_PAUSE_ON = 1<<3, /* Pause On */
1613 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1614 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1615 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1616};
1617
1618/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1619enum {
1620 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1621 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1622 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1623 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1624 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1625 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1626 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1627 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1628 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1629 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1630 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1631 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1632 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1633 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1634 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1635 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1636 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1637 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1638 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1639 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1640 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1641 /* Bits 7..2: reserved */
1642 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1643 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1644};
1645
1646/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1647/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1648enum {
1649 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1650 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1651 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1652 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1653 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1654 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1655
1656#define GMAC_DEF_MSK GM_IS_TX_FF_UR
1657
1658/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1659 /* Bits 15.. 2: reserved */
1660 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1661 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1662
1663
1664/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1665 WOL_CTL_LINK_CHG_OCC = 1<<15,
1666 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1667 WOL_CTL_PATTERN_OCC = 1<<13,
1668 WOL_CTL_CLEAR_RESULT = 1<<12,
1669 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1670 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1671 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1672 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1673 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1674 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1675 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1676 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1677 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1678 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1679 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1680 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1681};
1682
1683#define WOL_CTL_DEFAULT \
1684 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1685 WOL_CTL_DIS_PME_ON_PATTERN | \
1686 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1687 WOL_CTL_DIS_LINK_CHG_UNIT | \
1688 WOL_CTL_DIS_PATTERN_UNIT | \
1689 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1690
1691/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1692#define WOL_CTL_PATT_ENA(x) (1 << (x))
1693
1694
1695/* Control flags */
1696enum {
1697 UDPTCP = 1<<0,
1698 CALSUM = 1<<1,
1699 WR_SUM = 1<<2,
1700 INIT_SUM= 1<<3,
1701 LOCK_SUM= 1<<4,
1702 INS_VLAN= 1<<5,
1703 FRC_STAT= 1<<6,
1704 EOP = 1<<7,
1705};
1706
1707enum {
1708 HW_OWNER = 1<<7,
1709 OP_TCPWRITE = 0x11,
1710 OP_TCPSTART = 0x12,
1711 OP_TCPINIT = 0x14,
1712 OP_TCPLCK = 0x18,
1713 OP_TCPCHKSUM = OP_TCPSTART,
1714 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1715 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1716 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1717 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1718
1719 OP_ADDR64 = 0x21,
1720 OP_VLAN = 0x22,
1721 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1722 OP_LRGLEN = 0x24,
1723 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1724 OP_BUFFER = 0x40,
1725 OP_PACKET = 0x41,
1726 OP_LARGESEND = 0x43,
1727
1728/* YUKON-2 STATUS opcodes defines */
1729 OP_RXSTAT = 0x60,
1730 OP_RXTIMESTAMP = 0x61,
1731 OP_RXVLAN = 0x62,
1732 OP_RXCHKS = 0x64,
1733 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1734 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1735 OP_RSS_HASH = 0x65,
1736 OP_TXINDEXLE = 0x68,
1737};
1738
1739/* Yukon 2 hardware interface
1740 * Not tested on big endian
1741 */
1742struct sky2_tx_le {
1743 union {
1744 u32 addr;
1745 struct {
1746 u16 offset;
1747 u16 start;
1748 } csum __attribute((packed));
1749 struct {
1750 u16 size;
1751 u16 rsvd;
1752 } tso __attribute((packed));
1753 } tx;
1754 u16 length; /* also vlan tag or checksum start */
1755 u8 ctrl;
1756 u8 opcode;
1757} __attribute((packed));
1758
1759struct sky2_rx_le {
1760 u32 addr;
1761 u16 length;
1762 u8 ctrl;
1763 u8 opcode;
1764} __attribute((packed));;
1765
1766struct sky2_status_le {
1767 u32 status; /* also checksum */
1768 u16 length; /* also vlan tag */
1769 u8 link;
1770 u8 opcode;
1771} __attribute((packed));
1772
1773struct ring_info {
1774 struct sk_buff *skb;
1775 dma_addr_t mapaddr;
1776 u16 maplen;
1777 u16 idx;
1778};
1779
1780struct sky2_port {
1781 struct sky2_hw *hw;
1782 struct net_device *netdev;
1783 unsigned port;
1784 u32 msg_enable;
1785
1786 struct ring_info *tx_ring;
1787 struct sky2_tx_le *tx_le;
1788 spinlock_t tx_lock;
1789 u32 tx_addr64;
1790 u16 tx_cons; /* next le to check */
1791 u16 tx_prod; /* next le to use */
1792 u16 tx_pending;
1793 u16 tx_last_put;
1794 u16 tx_last_mss;
1795
1796 struct ring_info *rx_ring;
1797 struct sky2_rx_le *rx_le;
1798 u32 rx_addr64;
1799 u16 rx_next; /* next re to check */
1800 u16 rx_put; /* next le index to use */
1801 u16 rx_pending;
1802 u16 rx_last_put;
1803#ifdef SKY2_VLAN_TAG_USED
1804 u16 rx_tag;
1805 struct vlan_group *vlgrp;
1806#endif
1807
1808 dma_addr_t rx_le_map;
1809 dma_addr_t tx_le_map;
1810 u32 advertising; /* ADVERTISED_ bits */
1811 u16 speed; /* SPEED_1000, SPEED_100, ... */
1812 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1813 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1814 u8 rx_pause;
1815 u8 tx_pause;
1816 u8 rx_csum;
1817 u8 wol;
1818
1819 struct tasklet_struct phy_task;
1820 struct net_device_stats net_stats;
1821};
1822
1823struct sky2_hw {
1824 void __iomem *regs;
1825 struct pci_dev *pdev;
1826 u32 intr_mask;
1827 struct net_device *dev[2];
1828
1829 int pm_cap;
1830 u8 chip_id;
1831 u8 chip_rev;
1832 u8 copper;
1833 u8 ports;
1834
1835 struct sky2_status_le *st_le;
1836 u32 st_idx;
1837 dma_addr_t st_dma;
1838
1839 spinlock_t phy_lock;
1840};
1841
1842/* Register accessor for memory mapped device */
1843static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1844{
1845 return readl(hw->regs + reg);
1846}
1847
1848static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1849{
1850 return readw(hw->regs + reg);
1851}
1852
1853static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1854{
1855 return readb(hw->regs + reg);
1856}
1857
1858/* This should probably go away, bus based tweeks suck */
1859static inline int is_pciex(const struct sky2_hw *hw)
1860{
1861 u32 status;
1862 pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
1863 return (status & PCI_OS_PCI_X) == 0;
1864}
1865
1866static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1867{
1868 writel(val, hw->regs + reg);
1869}
1870
1871static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1872{
1873 writew(val, hw->regs + reg);
1874}
1875
1876static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1877{
1878 writeb(val, hw->regs + reg);
1879}
1880
1881/* Yukon PHY related registers */
1882#define SK_GMAC_REG(port,reg) \
1883 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1884#define GM_PHY_RETRIES 100
1885
1886static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1887{
1888 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1889}
1890
1891static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1892{
1893 unsigned base = SK_GMAC_REG(port, reg);
1894 return (u32) sky2_read16(hw, base)
1895 | (u32) sky2_read16(hw, base+4) << 16;
1896}
1897
1898static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1899{
1900 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1901}
1902
1903static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1904 const u8 *addr)
1905{
1906 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1907 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1908 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1909}
1910#endif
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index c6efce4a04a4..b72f756542d0 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -802,11 +802,15 @@ static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits)
802} 802}
803 803
804/* Schedule rx intr now? */ 804/* Schedule rx intr now? */
805static inline int netif_rx_schedule_test(struct net_device *dev)
806{
807 return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
808}
805 809
810/* Schedule only if device is up */
806static inline int netif_rx_schedule_prep(struct net_device *dev) 811static inline int netif_rx_schedule_prep(struct net_device *dev)
807{ 812{
808 return netif_running(dev) && 813 return netif_running(dev) && netif_rx_schedule_test(dev);
809 !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
810} 814}
811 815
812/* Add interface to tail of rx poll list. This assumes that _prep has 816/* Add interface to tail of rx poll list. This assumes that _prep has
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 11:11:24 -0500