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-rw-r--r--arch/x86/kernel/mpparse_32.c18
-rw-r--r--arch/x86/mach-visws/mpparse.c16
-rw-r--r--include/asm-x86/mach-bigsmp/mach_apic.h12
-rw-r--r--include/asm-x86/mach-default/mach_apic.h18
-rw-r--r--include/asm-x86/mach-es7000/mach_apic.h10
-rw-r--r--include/asm-x86/mach-numaq/mach_apic.h10
-rw-r--r--include/asm-x86/mach-summit/mach_apic.h18
-rw-r--r--include/asm-x86/mpspec_32.h49
-rw-r--r--include/asm-x86/mpspec_64.h196
-rw-r--r--include/asm-x86/mpspec_def.h87
10 files changed, 148 insertions, 286 deletions
diff --git a/arch/x86/kernel/mpparse_32.c b/arch/x86/kernel/mpparse_32.c
index 7a05a7f6099a..22fc8d7dec11 100644
--- a/arch/x86/kernel/mpparse_32.c
+++ b/arch/x86/kernel/mpparse_32.c
@@ -258,7 +258,7 @@ static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
258 if (!(m->mpc_flags & MPC_APIC_USABLE)) 258 if (!(m->mpc_flags & MPC_APIC_USABLE))
259 return; 259 return;
260 260
261 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n", 261 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
262 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); 262 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
263 if (nr_ioapics >= MAX_IO_APICS) { 263 if (nr_ioapics >= MAX_IO_APICS) {
264 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n", 264 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
@@ -405,9 +405,9 @@ static int __init smp_read_mpc(struct mp_config_table *mpc)
405 405
406 mps_oem_check(mpc, oem, str); 406 mps_oem_check(mpc, oem, str);
407 407
408 printk("APIC at: 0x%lX\n",mpc->mpc_lapic); 408 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
409 409
410 /* 410 /*
411 * Save the local APIC address (it might be non-default) -- but only 411 * Save the local APIC address (it might be non-default) -- but only
412 * if we're not using ACPI. 412 * if we're not using ACPI.
413 */ 413 */
@@ -918,14 +918,14 @@ void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
918 */ 918 */
919 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; 919 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
920 mp_ioapic_routing[idx].gsi_base = gsi_base; 920 mp_ioapic_routing[idx].gsi_base = gsi_base;
921 mp_ioapic_routing[idx].gsi_end = gsi_base + 921 mp_ioapic_routing[idx].gsi_end = gsi_base +
922 io_apic_get_redir_entries(idx); 922 io_apic_get_redir_entries(idx);
923 923
924 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, " 924 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
925 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 925 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
926 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, 926 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
927 mp_ioapic_routing[idx].gsi_base, 927 mp_ioapic_routing[idx].gsi_base,
928 mp_ioapic_routing[idx].gsi_end); 928 mp_ioapic_routing[idx].gsi_end);
929} 929}
930 930
931void __init 931void __init
diff --git a/arch/x86/mach-visws/mpparse.c b/arch/x86/mach-visws/mpparse.c
index f3c74fab8b95..2a8456a1f44f 100644
--- a/arch/x86/mach-visws/mpparse.c
+++ b/arch/x86/mach-visws/mpparse.c
@@ -36,19 +36,19 @@ unsigned int __initdata maxcpus = NR_CPUS;
36 36
37static void __init MP_processor_info (struct mpc_config_processor *m) 37static void __init MP_processor_info (struct mpc_config_processor *m)
38{ 38{
39 int ver, logical_apicid; 39 int ver, logical_apicid;
40 physid_mask_t apic_cpus; 40 physid_mask_t apic_cpus;
41 41
42 if (!(m->mpc_cpuflag & CPU_ENABLED)) 42 if (!(m->mpc_cpuflag & CPU_ENABLED))
43 return; 43 return;
44 44
45 logical_apicid = m->mpc_apicid; 45 logical_apicid = m->mpc_apicid;
46 printk(KERN_INFO "%sCPU #%d %ld:%ld APIC version %d\n", 46 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
47 m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "", 47 m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
48 m->mpc_apicid, 48 m->mpc_apicid,
49 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 49 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
50 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 50 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
51 m->mpc_apicver); 51 m->mpc_apicver);
52 52
53 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) 53 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
54 boot_cpu_physical_apicid = m->mpc_apicid; 54 boot_cpu_physical_apicid = m->mpc_apicid;
diff --git a/include/asm-x86/mach-bigsmp/mach_apic.h b/include/asm-x86/mach-bigsmp/mach_apic.h
index ebd319f838ab..6df235e8ea91 100644
--- a/include/asm-x86/mach-bigsmp/mach_apic.h
+++ b/include/asm-x86/mach-bigsmp/mach_apic.h
@@ -110,13 +110,13 @@ static inline int cpu_to_logical_apicid(int cpu)
110} 110}
111 111
112static inline int mpc_apic_id(struct mpc_config_processor *m, 112static inline int mpc_apic_id(struct mpc_config_processor *m,
113 struct mpc_config_translation *translation_record) 113 struct mpc_config_translation *translation_record)
114{ 114{
115 printk("Processor #%d %ld:%ld APIC version %d\n", 115 printk("Processor #%d %u:%u APIC version %d\n",
116 m->mpc_apicid, 116 m->mpc_apicid,
117 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 117 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
118 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 118 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
119 m->mpc_apicver); 119 m->mpc_apicver);
120 return m->mpc_apicid; 120 return m->mpc_apicid;
121} 121}
122 122
diff --git a/include/asm-x86/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h
index 6db1c3babe9a..e3c2c1012c1c 100644
--- a/include/asm-x86/mach-default/mach_apic.h
+++ b/include/asm-x86/mach-default/mach_apic.h
@@ -89,15 +89,15 @@ static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
89 return physid_mask_of_physid(phys_apicid); 89 return physid_mask_of_physid(phys_apicid);
90} 90}
91 91
92static inline int mpc_apic_id(struct mpc_config_processor *m, 92static inline int mpc_apic_id(struct mpc_config_processor *m,
93 struct mpc_config_translation *translation_record) 93 struct mpc_config_translation *translation_record)
94{ 94{
95 printk("Processor #%d %ld:%ld APIC version %d\n", 95 printk("Processor #%d %u:%u APIC version %d\n",
96 m->mpc_apicid, 96 m->mpc_apicid,
97 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 97 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
98 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 98 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
99 m->mpc_apicver); 99 m->mpc_apicver);
100 return (m->mpc_apicid); 100 return m->mpc_apicid;
101} 101}
102 102
103static inline void setup_portio_remap(void) 103static inline void setup_portio_remap(void)
diff --git a/include/asm-x86/mach-es7000/mach_apic.h b/include/asm-x86/mach-es7000/mach_apic.h
index caec64be516d..d23011fdf454 100644
--- a/include/asm-x86/mach-es7000/mach_apic.h
+++ b/include/asm-x86/mach-es7000/mach_apic.h
@@ -131,11 +131,11 @@ static inline int cpu_to_logical_apicid(int cpu)
131 131
132static inline int mpc_apic_id(struct mpc_config_processor *m, struct mpc_config_translation *unused) 132static inline int mpc_apic_id(struct mpc_config_processor *m, struct mpc_config_translation *unused)
133{ 133{
134 printk("Processor #%d %ld:%ld APIC version %d\n", 134 printk("Processor #%d %u:%u APIC version %d\n",
135 m->mpc_apicid, 135 m->mpc_apicid,
136 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 136 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
137 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 137 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
138 m->mpc_apicver); 138 m->mpc_apicver);
139 return (m->mpc_apicid); 139 return (m->mpc_apicid);
140} 140}
141 141
diff --git a/include/asm-x86/mach-numaq/mach_apic.h b/include/asm-x86/mach-numaq/mach_apic.h
index 5e5e7dd2692e..17e183bd39c1 100644
--- a/include/asm-x86/mach-numaq/mach_apic.h
+++ b/include/asm-x86/mach-numaq/mach_apic.h
@@ -101,11 +101,11 @@ static inline int mpc_apic_id(struct mpc_config_processor *m,
101 int quad = translation_record->trans_quad; 101 int quad = translation_record->trans_quad;
102 int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid); 102 int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid);
103 103
104 printk("Processor #%d %ld:%ld APIC version %d (quad %d, apic %d)\n", 104 printk("Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
105 m->mpc_apicid, 105 m->mpc_apicid,
106 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 106 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
107 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 107 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
108 m->mpc_apicver, quad, logical_apicid); 108 m->mpc_apicver, quad, logical_apicid);
109 return logical_apicid; 109 return logical_apicid;
110} 110}
111 111
diff --git a/include/asm-x86/mach-summit/mach_apic.h b/include/asm-x86/mach-summit/mach_apic.h
index 732f776aab8e..062c97f6100b 100644
--- a/include/asm-x86/mach-summit/mach_apic.h
+++ b/include/asm-x86/mach-summit/mach_apic.h
@@ -126,15 +126,15 @@ static inline physid_mask_t apicid_to_cpu_present(int apicid)
126 return physid_mask_of_physid(0); 126 return physid_mask_of_physid(0);
127} 127}
128 128
129static inline int mpc_apic_id(struct mpc_config_processor *m, 129static inline int mpc_apic_id(struct mpc_config_processor *m,
130 struct mpc_config_translation *translation_record) 130 struct mpc_config_translation *translation_record)
131{ 131{
132 printk("Processor #%d %ld:%ld APIC version %d\n", 132 printk("Processor #%d %u:%u APIC version %d\n",
133 m->mpc_apicid, 133 m->mpc_apicid,
134 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 134 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
135 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 135 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
136 m->mpc_apicver); 136 m->mpc_apicver);
137 return (m->mpc_apicid); 137 return m->mpc_apicid;
138} 138}
139 139
140static inline void setup_portio_remap(void) 140static inline void setup_portio_remap(void)
diff --git a/include/asm-x86/mpspec_32.h b/include/asm-x86/mpspec_32.h
index f21349399d14..bb73185e6a7d 100644
--- a/include/asm-x86/mpspec_32.h
+++ b/include/asm-x86/mpspec_32.h
@@ -1,34 +1,37 @@
1#ifndef __ASM_MPSPEC_H 1#ifndef __ASM_MPSPEC_H
2#define __ASM_MPSPEC_H 2#define __ASM_MPSPEC_H
3 3
4#include <linux/cpumask.h>
5#include <asm/mpspec_def.h> 4#include <asm/mpspec_def.h>
6#include <mach_mpspec.h> 5#include <mach_mpspec.h>
7 6
8extern int mp_bus_id_to_type [MAX_MP_BUSSES]; 7extern int mp_bus_id_to_type[MAX_MP_BUSSES];
9extern int mp_bus_id_to_node [MAX_MP_BUSSES]; 8extern int mp_bus_id_to_node[MAX_MP_BUSSES];
10extern int mp_bus_id_to_local [MAX_MP_BUSSES]; 9extern int mp_bus_id_to_local[MAX_MP_BUSSES];
11extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 10extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
12extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
13 11
14extern unsigned int def_to_bigsmp; 12extern unsigned int def_to_bigsmp;
13extern int apic_version[MAX_APICS];
14extern int pic_mode;
15
16extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
17
15extern unsigned int boot_cpu_physical_apicid; 18extern unsigned int boot_cpu_physical_apicid;
16extern int smp_found_config; 19extern int smp_found_config;
17extern void find_smp_config (void);
18extern void get_smp_config (void);
19extern int nr_ioapics; 20extern int nr_ioapics;
20extern int apic_version [MAX_APICS];
21extern int mp_irq_entries; 21extern int mp_irq_entries;
22extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; 22extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
23extern int mpc_default_type; 23extern int mpc_default_type;
24extern unsigned long mp_lapic_addr; 24extern unsigned long mp_lapic_addr;
25extern int pic_mode; 25
26extern void find_smp_config (void);
27extern void get_smp_config (void);
26 28
27#ifdef CONFIG_ACPI 29#ifdef CONFIG_ACPI
28extern void mp_register_lapic (u8 id, u8 enabled); 30extern void mp_register_lapic (u8 id, u8 enabled);
29extern void mp_register_lapic_address (u64 address); 31extern void mp_register_lapic_address (u64 address);
30extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); 32extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
31extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); 33extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
34 u32 gsi);
32extern void mp_config_acpi_legacy_irqs (void); 35extern void mp_config_acpi_legacy_irqs (void);
33extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low); 36extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
34#endif /* CONFIG_ACPI */ 37#endif /* CONFIG_ACPI */
@@ -50,7 +53,7 @@ typedef struct physid_mask physid_mask_t;
50#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 53#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
51#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 54#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
52#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) 55#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
53#define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS) 56#define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS)
54#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) 57#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
55#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) 58#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
56#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) 59#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
@@ -58,18 +61,18 @@ typedef struct physid_mask physid_mask_t;
58#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 61#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
59#define physids_coerce(map) ((map).mask[0]) 62#define physids_coerce(map) ((map).mask[0])
60 63
61#define physids_promote(physids) \ 64#define physids_promote(physids) \
62 ({ \ 65 ({ \
63 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 66 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
64 __physid_mask.mask[0] = physids; \ 67 __physid_mask.mask[0] = physids; \
65 __physid_mask; \ 68 __physid_mask; \
66 }) 69 })
67 70
68#define physid_mask_of_physid(physid) \ 71#define physid_mask_of_physid(physid) \
69 ({ \ 72 ({ \
70 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 73 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
71 physid_set(physid, __physid_mask); \ 74 physid_set(physid, __physid_mask); \
72 __physid_mask; \ 75 __physid_mask; \
73 }) 76 })
74 77
75#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 78#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
diff --git a/include/asm-x86/mpspec_64.h b/include/asm-x86/mpspec_64.h
index 017fddb61dc5..16eab20667cd 100644
--- a/include/asm-x86/mpspec_64.h
+++ b/include/asm-x86/mpspec_64.h
@@ -1,189 +1,35 @@
1#ifndef __ASM_MPSPEC_H 1#ifndef __ASM_MPSPEC_H
2#define __ASM_MPSPEC_H 2#define __ASM_MPSPEC_H
3 3
4/* 4#include <asm/mpspec_def.h>
5 * Structure definitions for SMP machines following the
6 * Intel Multiprocessing Specification 1.1 and 1.4.
7 */
8
9/*
10 * This tag identifies where the SMP configuration
11 * information is.
12 */
13
14#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
15
16/*
17 * A maximum of 255 APICs with the current APIC ID architecture.
18 */
19#define MAX_APICS 255
20
21struct intel_mp_floating
22{
23 char mpf_signature[4]; /* "_MP_" */
24 unsigned int mpf_physptr; /* Configuration table address */
25 unsigned char mpf_length; /* Our length (paragraphs) */
26 unsigned char mpf_specification;/* Specification version */
27 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
28 unsigned char mpf_feature1; /* Standard or configuration ? */
29 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
30 unsigned char mpf_feature3; /* Unused (0) */
31 unsigned char mpf_feature4; /* Unused (0) */
32 unsigned char mpf_feature5; /* Unused (0) */
33};
34
35struct mp_config_table
36{
37 char mpc_signature[4];
38#define MPC_SIGNATURE "PCMP"
39 unsigned short mpc_length; /* Size of table */
40 char mpc_spec; /* 0x01 */
41 char mpc_checksum;
42 char mpc_oem[8];
43 char mpc_productid[12];
44 unsigned int mpc_oemptr; /* 0 if not present */
45 unsigned short mpc_oemsize; /* 0 if not present */
46 unsigned short mpc_oemcount;
47 unsigned int mpc_lapic; /* APIC address */
48 unsigned int reserved;
49};
50
51/* Followed by entries */
52
53#define MP_PROCESSOR 0
54#define MP_BUS 1
55#define MP_IOAPIC 2
56#define MP_INTSRC 3
57#define MP_LINTSRC 4
58
59struct mpc_config_processor
60{
61 unsigned char mpc_type;
62 unsigned char mpc_apicid; /* Local APIC number */
63 unsigned char mpc_apicver; /* Its versions */
64 unsigned char mpc_cpuflag;
65#define CPU_ENABLED 1 /* Processor is available */
66#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
67 unsigned int mpc_cpufeature;
68#define CPU_STEPPING_MASK 0x0F
69#define CPU_MODEL_MASK 0xF0
70#define CPU_FAMILY_MASK 0xF00
71 unsigned int mpc_featureflag; /* CPUID feature value */
72 unsigned int mpc_reserved[2];
73};
74
75struct mpc_config_bus
76{
77 unsigned char mpc_type;
78 unsigned char mpc_busid;
79 unsigned char mpc_bustype[6];
80};
81
82/* List of Bus Type string values, Intel MP Spec. */
83#define BUSTYPE_EISA "EISA"
84#define BUSTYPE_ISA "ISA"
85#define BUSTYPE_INTERN "INTERN" /* Internal BUS */
86#define BUSTYPE_MCA "MCA"
87#define BUSTYPE_VL "VL" /* Local bus */
88#define BUSTYPE_PCI "PCI"
89#define BUSTYPE_PCMCIA "PCMCIA"
90#define BUSTYPE_CBUS "CBUS"
91#define BUSTYPE_CBUSII "CBUSII"
92#define BUSTYPE_FUTURE "FUTURE"
93#define BUSTYPE_MBI "MBI"
94#define BUSTYPE_MBII "MBII"
95#define BUSTYPE_MPI "MPI"
96#define BUSTYPE_MPSA "MPSA"
97#define BUSTYPE_NUBUS "NUBUS"
98#define BUSTYPE_TC "TC"
99#define BUSTYPE_VME "VME"
100#define BUSTYPE_XPRESS "XPRESS"
101
102struct mpc_config_ioapic
103{
104 unsigned char mpc_type;
105 unsigned char mpc_apicid;
106 unsigned char mpc_apicver;
107 unsigned char mpc_flags;
108#define MPC_APIC_USABLE 0x01
109 unsigned int mpc_apicaddr;
110};
111
112struct mpc_config_intsrc
113{
114 unsigned char mpc_type;
115 unsigned char mpc_irqtype;
116 unsigned short mpc_irqflag;
117 unsigned char mpc_srcbus;
118 unsigned char mpc_srcbusirq;
119 unsigned char mpc_dstapic;
120 unsigned char mpc_dstirq;
121};
122
123enum mp_irq_source_types {
124 mp_INT = 0,
125 mp_NMI = 1,
126 mp_SMI = 2,
127 mp_ExtINT = 3
128};
129
130#define MP_IRQDIR_DEFAULT 0
131#define MP_IRQDIR_HIGH 1
132#define MP_IRQDIR_LOW 3
133
134
135struct mpc_config_lintsrc
136{
137 unsigned char mpc_type;
138 unsigned char mpc_irqtype;
139 unsigned short mpc_irqflag;
140 unsigned char mpc_srcbusid;
141 unsigned char mpc_srcbusirq;
142 unsigned char mpc_destapic;
143#define MP_APIC_ALL 0xFF
144 unsigned char mpc_destapiclint;
145};
146
147/*
148 * Default configurations
149 *
150 * 1 2 CPU ISA 82489DX
151 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
152 * 3 2 CPU EISA 82489DX
153 * 4 2 CPU MCA 82489DX
154 * 5 2 CPU ISA+PCI
155 * 6 2 CPU EISA+PCI
156 * 7 2 CPU MCA+PCI
157 */
158 5
159#define MAX_MP_BUSSES 256 6#define MAX_MP_BUSSES 256
160/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 7/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
161#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 8#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
162extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 9extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
163extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; 10
11extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
164 12
165extern unsigned int boot_cpu_physical_apicid; 13extern unsigned int boot_cpu_physical_apicid;
166extern int smp_found_config; 14extern int smp_found_config;
167extern void find_smp_config (void);
168extern void get_smp_config (void);
169extern int nr_ioapics; 15extern int nr_ioapics;
170extern unsigned char apic_version [MAX_APICS];
171extern int mp_irq_entries; 16extern int mp_irq_entries;
172extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; 17extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
173extern int mpc_default_type; 18extern int mpc_default_type;
174extern unsigned long mp_lapic_addr; 19extern unsigned long mp_lapic_addr;
175 20
21extern void find_smp_config (void);
22extern void get_smp_config (void);
23
176#ifdef CONFIG_ACPI 24#ifdef CONFIG_ACPI
177extern void mp_register_lapic (u8 id, u8 enabled); 25extern void mp_register_lapic (u8 id, u8 enabled);
178extern void mp_register_lapic_address (u64 address); 26extern void mp_register_lapic_address (u64 address);
179
180extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); 27extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
181extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); 28extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
29 u32 gsi);
182extern void mp_config_acpi_legacy_irqs (void); 30extern void mp_config_acpi_legacy_irqs (void);
183extern int mp_register_gsi (u32 gsi, int triggering, int polarity); 31extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
184#endif 32#endif /* CONFIG_ACPI */
185
186extern int using_apic_timer;
187 33
188#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 34#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
189 35
@@ -210,18 +56,18 @@ typedef struct physid_mask physid_mask_t;
210#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 56#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
211#define physids_coerce(map) ((map).mask[0]) 57#define physids_coerce(map) ((map).mask[0])
212 58
213#define physids_promote(physids) \ 59#define physids_promote(physids) \
214 ({ \ 60 ({ \
215 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 61 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
216 __physid_mask.mask[0] = physids; \ 62 __physid_mask.mask[0] = physids; \
217 __physid_mask; \ 63 __physid_mask; \
218 }) 64 })
219 65
220#define physid_mask_of_physid(physid) \ 66#define physid_mask_of_physid(physid) \
221 ({ \ 67 ({ \
222 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 68 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
223 physid_set(physid, __physid_mask); \ 69 physid_set(physid, __physid_mask); \
224 __physid_mask; \ 70 __physid_mask; \
225 }) 71 })
226 72
227#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 73#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
diff --git a/include/asm-x86/mpspec_def.h b/include/asm-x86/mpspec_def.h
index 13bafb16e7af..3504617fe648 100644
--- a/include/asm-x86/mpspec_def.h
+++ b/include/asm-x86/mpspec_def.h
@@ -8,52 +8,68 @@
8 8
9/* 9/*
10 * This tag identifies where the SMP configuration 10 * This tag identifies where the SMP configuration
11 * information is. 11 * information is.
12 */ 12 */
13 13
14#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') 14#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
15 15
16#define MAX_MPC_ENTRY 1024 16#ifdef CONFIG_X86_32
17#define MAX_APICS 256 17# define MAX_MPC_ENTRY 1024
18# define MAX_APICS 256
19#else
20/*
21 * A maximum of 255 APICs with the current APIC ID architecture.
22 */
23# define MAX_APICS 255
24#endif
18 25
19struct intel_mp_floating 26struct intel_mp_floating
20{ 27{
21 char mpf_signature[4]; /* "_MP_" */ 28 char mpf_signature[4]; /* "_MP_" */
22 unsigned long mpf_physptr; /* Configuration table address */ 29 unsigned int mpf_physptr; /* Configuration table address */
23 unsigned char mpf_length; /* Our length (paragraphs) */ 30 unsigned char mpf_length; /* Our length (paragraphs) */
24 unsigned char mpf_specification;/* Specification version */ 31 unsigned char mpf_specification;/* Specification version */
25 unsigned char mpf_checksum; /* Checksum (makes sum 0) */ 32 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
26 unsigned char mpf_feature1; /* Standard or configuration ? */ 33 unsigned char mpf_feature1; /* Standard or configuration ? */
27 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ 34 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
28 unsigned char mpf_feature3; /* Unused (0) */ 35 unsigned char mpf_feature3; /* Unused (0) */
29 unsigned char mpf_feature4; /* Unused (0) */ 36 unsigned char mpf_feature4; /* Unused (0) */
30 unsigned char mpf_feature5; /* Unused (0) */ 37 unsigned char mpf_feature5; /* Unused (0) */
31}; 38};
32 39
40#define MPC_SIGNATURE "PCMP"
41
33struct mp_config_table 42struct mp_config_table
34{ 43{
35 char mpc_signature[4]; 44 char mpc_signature[4];
36#define MPC_SIGNATURE "PCMP"
37 unsigned short mpc_length; /* Size of table */ 45 unsigned short mpc_length; /* Size of table */
38 char mpc_spec; /* 0x01 */ 46 char mpc_spec; /* 0x01 */
39 char mpc_checksum; 47 char mpc_checksum;
40 char mpc_oem[8]; 48 char mpc_oem[8];
41 char mpc_productid[12]; 49 char mpc_productid[12];
42 unsigned long mpc_oemptr; /* 0 if not present */ 50 unsigned int mpc_oemptr; /* 0 if not present */
43 unsigned short mpc_oemsize; /* 0 if not present */ 51 unsigned short mpc_oemsize; /* 0 if not present */
44 unsigned short mpc_oemcount; 52 unsigned short mpc_oemcount;
45 unsigned long mpc_lapic; /* APIC address */ 53 unsigned int mpc_lapic; /* APIC address */
46 unsigned long reserved; 54 unsigned int reserved;
47}; 55};
48 56
49/* Followed by entries */ 57/* Followed by entries */
50 58
51#define MP_PROCESSOR 0 59#define MP_PROCESSOR 0
52#define MP_BUS 1 60#define MP_BUS 1
53#define MP_IOAPIC 2 61#define MP_IOAPIC 2
54#define MP_INTSRC 3 62#define MP_INTSRC 3
55#define MP_LINTSRC 4 63#define MP_LINTSRC 4
56#define MP_TRANSLATION 192 /* Used by IBM NUMA-Q to describe node locality */ 64/* Used by IBM NUMA-Q to describe node locality */
65#define MP_TRANSLATION 192
66
67#define CPU_ENABLED 1 /* Processor is available */
68#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
69
70#define CPU_STEPPING_MASK 0x000F
71#define CPU_MODEL_MASK 0x00F0
72#define CPU_FAMILY_MASK 0x0F00
57 73
58struct mpc_config_processor 74struct mpc_config_processor
59{ 75{
@@ -61,14 +77,9 @@ struct mpc_config_processor
61 unsigned char mpc_apicid; /* Local APIC number */ 77 unsigned char mpc_apicid; /* Local APIC number */
62 unsigned char mpc_apicver; /* Its versions */ 78 unsigned char mpc_apicver; /* Its versions */
63 unsigned char mpc_cpuflag; 79 unsigned char mpc_cpuflag;
64#define CPU_ENABLED 1 /* Processor is available */ 80 unsigned int mpc_cpufeature;
65#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ 81 unsigned int mpc_featureflag; /* CPUID feature value */
66 unsigned long mpc_cpufeature; 82 unsigned int mpc_reserved[2];
67#define CPU_STEPPING_MASK 0x0F
68#define CPU_MODEL_MASK 0xF0
69#define CPU_FAMILY_MASK 0xF00
70 unsigned long mpc_featureflag; /* CPUID feature value */
71 unsigned long mpc_reserved[2];
72}; 83};
73 84
74struct mpc_config_bus 85struct mpc_config_bus
@@ -98,14 +109,15 @@ struct mpc_config_bus
98#define BUSTYPE_VME "VME" 109#define BUSTYPE_VME "VME"
99#define BUSTYPE_XPRESS "XPRESS" 110#define BUSTYPE_XPRESS "XPRESS"
100 111
112#define MPC_APIC_USABLE 0x01
113
101struct mpc_config_ioapic 114struct mpc_config_ioapic
102{ 115{
103 unsigned char mpc_type; 116 unsigned char mpc_type;
104 unsigned char mpc_apicid; 117 unsigned char mpc_apicid;
105 unsigned char mpc_apicver; 118 unsigned char mpc_apicver;
106 unsigned char mpc_flags; 119 unsigned char mpc_flags;
107#define MPC_APIC_USABLE 0x01 120 unsigned int mpc_apicaddr;
108 unsigned long mpc_apicaddr;
109}; 121};
110 122
111struct mpc_config_intsrc 123struct mpc_config_intsrc
@@ -130,6 +142,7 @@ enum mp_irq_source_types {
130#define MP_IRQDIR_HIGH 1 142#define MP_IRQDIR_HIGH 1
131#define MP_IRQDIR_LOW 3 143#define MP_IRQDIR_LOW 3
132 144
145#define MP_APIC_ALL 0xFF
133 146
134struct mpc_config_lintsrc 147struct mpc_config_lintsrc
135{ 148{
@@ -138,15 +151,15 @@ struct mpc_config_lintsrc
138 unsigned short mpc_irqflag; 151 unsigned short mpc_irqflag;
139 unsigned char mpc_srcbusid; 152 unsigned char mpc_srcbusid;
140 unsigned char mpc_srcbusirq; 153 unsigned char mpc_srcbusirq;
141 unsigned char mpc_destapic; 154 unsigned char mpc_destapic;
142#define MP_APIC_ALL 0xFF
143 unsigned char mpc_destapiclint; 155 unsigned char mpc_destapiclint;
144}; 156};
145 157
158#define MPC_OEM_SIGNATURE "_OEM"
159
146struct mp_config_oemtable 160struct mp_config_oemtable
147{ 161{
148 char oem_signature[4]; 162 char oem_signature[4];
149#define MPC_OEM_SIGNATURE "_OEM"
150 unsigned short oem_length; /* Size of table */ 163 unsigned short oem_length; /* Size of table */
151 char oem_rev; /* 0x01 */ 164 char oem_rev; /* 0x01 */
152 char oem_checksum; 165 char oem_checksum;
@@ -155,13 +168,13 @@ struct mp_config_oemtable
155 168
156struct mpc_config_translation 169struct mpc_config_translation
157{ 170{
158 unsigned char mpc_type; 171 unsigned char mpc_type;
159 unsigned char trans_len; 172 unsigned char trans_len;
160 unsigned char trans_type; 173 unsigned char trans_type;
161 unsigned char trans_quad; 174 unsigned char trans_quad;
162 unsigned char trans_global; 175 unsigned char trans_global;
163 unsigned char trans_local; 176 unsigned char trans_local;
164 unsigned short trans_reserved; 177 unsigned short trans_reserved;
165}; 178};
166 179
167/* 180/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:30:35 -0500