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-rw-r--r--drivers/net/myri10ge/myri10ge.c54
1 files changed, 3 insertions, 51 deletions
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index b3981ed972bf..3305ce3c5b3f 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -125,7 +125,6 @@ struct myri10ge_cmd {
125 125
126struct myri10ge_rx_buf { 126struct myri10ge_rx_buf {
127 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */ 127 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
128 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */ 128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info; 129 struct myri10ge_rx_buffer_state *info;
131 struct page *page; 130 struct page *page;
@@ -140,7 +139,6 @@ struct myri10ge_rx_buf {
140 139
141struct myri10ge_tx_buf { 140struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */ 141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
143 u8 __iomem *wc_fifo; /* w/c send fifo address */
144 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */ 142 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
145 char *req_bytes; 143 char *req_bytes;
146 struct myri10ge_tx_buffer_state *info; 144 struct myri10ge_tx_buffer_state *info;
@@ -332,10 +330,6 @@ MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
332 330
333static int myri10ge_reset_recover = 1; 331static int myri10ge_reset_recover = 1;
334 332
335static int myri10ge_wcfifo = 0;
336module_param(myri10ge_wcfifo, int, S_IRUGO);
337MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
338
339static int myri10ge_max_slices = 1; 333static int myri10ge_max_slices = 1;
340module_param(myri10ge_max_slices, int, S_IRUGO); 334module_param(myri10ge_max_slices, int, S_IRUGO);
341MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues"); 335MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
@@ -1218,14 +1212,8 @@ myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1218 1212
1219 /* copy 8 descriptors to the firmware at a time */ 1213 /* copy 8 descriptors to the firmware at a time */
1220 if ((idx & 7) == 7) { 1214 if ((idx & 7) == 7) {
1221 if (rx->wc_fifo == NULL) 1215 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1222 myri10ge_submit_8rx(&rx->lanai[idx - 7], 1216 &rx->shadow[idx - 7]);
1223 &rx->shadow[idx - 7]);
1224 else {
1225 mb();
1226 myri10ge_pio_copy(rx->wc_fifo,
1227 &rx->shadow[idx - 7], 64);
1228 }
1229 } 1217 }
1230 } 1218 }
1231} 1219}
@@ -2229,18 +2217,6 @@ static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2229 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *) 2217 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2230 (mgp->sram + cmd.data0); 2218 (mgp->sram + cmd.data0);
2231 2219
2232 if (myri10ge_wcfifo && mgp->wc_enabled) {
2233 ss->tx.wc_fifo = (u8 __iomem *)
2234 mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
2235 ss->rx_small.wc_fifo = (u8 __iomem *)
2236 mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
2237 ss->rx_big.wc_fifo = (u8 __iomem *)
2238 mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
2239 } else {
2240 ss->tx.wc_fifo = NULL;
2241 ss->rx_small.wc_fifo = NULL;
2242 ss->rx_big.wc_fifo = NULL;
2243 }
2244 return status; 2220 return status;
2245 2221
2246} 2222}
@@ -2573,27 +2549,6 @@ myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2573 mb(); 2549 mb();
2574} 2550}
2575 2551
2576static inline void
2577myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2578 struct mcp_kreq_ether_send *src, int cnt)
2579{
2580 tx->req += cnt;
2581 mb();
2582 while (cnt >= 4) {
2583 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2584 mb();
2585 src += 4;
2586 cnt -= 4;
2587 }
2588 if (cnt > 0) {
2589 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2590 * needs to be so that we don't overrun it */
2591 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2592 src, 64);
2593 mb();
2594 }
2595}
2596
2597/* 2552/*
2598 * Transmit a packet. We need to split the packet so that a single 2553 * Transmit a packet. We need to split the packet so that a single
2599 * segment does not cross myri10ge->tx_boundary, so this makes segment 2554 * segment does not cross myri10ge->tx_boundary, so this makes segment
@@ -2830,10 +2785,7 @@ again:
2830 MXGEFW_FLAGS_FIRST))); 2785 MXGEFW_FLAGS_FIRST)));
2831 idx = ((count - 1) + tx->req) & tx->mask; 2786 idx = ((count - 1) + tx->req) & tx->mask;
2832 tx->info[idx].last = 1; 2787 tx->info[idx].last = 1;
2833 if (tx->wc_fifo == NULL) 2788 myri10ge_submit_req(tx, tx->req_list, count);
2834 myri10ge_submit_req(tx, tx->req_list, count);
2835 else
2836 myri10ge_submit_req_wc(tx, tx->req_list, count);
2837 tx->pkt_start++; 2789 tx->pkt_start++;
2838 if ((avail - count) < MXGEFW_MAX_SEND_DESC) { 2790 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2839 tx->stop_queue++; 2791 tx->stop_queue++;