diff options
-rw-r--r-- | drivers/pci/intel-iommu.c | 22 | ||||
-rw-r--r-- | include/linux/dma_remapping.h | 22 |
2 files changed, 22 insertions, 22 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index 9d06f4bb6b5e..26c5402b6f7c 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c | |||
@@ -128,6 +128,28 @@ struct context_entry { | |||
128 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) | 128 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) |
129 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) | 129 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) |
130 | 130 | ||
131 | /* | ||
132 | * 0: readable | ||
133 | * 1: writable | ||
134 | * 2-6: reserved | ||
135 | * 7: super page | ||
136 | * 8-11: available | ||
137 | * 12-63: Host physcial address | ||
138 | */ | ||
139 | struct dma_pte { | ||
140 | u64 val; | ||
141 | }; | ||
142 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | ||
143 | |||
144 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | ||
145 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | ||
146 | #define dma_set_pte_prot(p, prot) \ | ||
147 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | ||
148 | #define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) | ||
149 | #define dma_set_pte_addr(p, addr) do {\ | ||
150 | (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) | ||
151 | #define dma_pte_present(p) (((p).val & 3) != 0) | ||
152 | |||
131 | static void flush_unmaps_timeout(unsigned long data); | 153 | static void flush_unmaps_timeout(unsigned long data); |
132 | 154 | ||
133 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); | 155 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
diff --git a/include/linux/dma_remapping.h b/include/linux/dma_remapping.h index 9a88f7d0262f..9d5874e3bec9 100644 --- a/include/linux/dma_remapping.h +++ b/include/linux/dma_remapping.h | |||
@@ -11,31 +11,9 @@ | |||
11 | 11 | ||
12 | struct root_entry; | 12 | struct root_entry; |
13 | 13 | ||
14 | /* | ||
15 | * 0: readable | ||
16 | * 1: writable | ||
17 | * 2-6: reserved | ||
18 | * 7: super page | ||
19 | * 8-11: available | ||
20 | * 12-63: Host physcial address | ||
21 | */ | ||
22 | struct dma_pte { | ||
23 | u64 val; | ||
24 | }; | ||
25 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | ||
26 | |||
27 | #define DMA_PTE_READ (1) | 14 | #define DMA_PTE_READ (1) |
28 | #define DMA_PTE_WRITE (2) | 15 | #define DMA_PTE_WRITE (2) |
29 | 16 | ||
30 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | ||
31 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | ||
32 | #define dma_set_pte_prot(p, prot) \ | ||
33 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | ||
34 | #define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK) | ||
35 | #define dma_set_pte_addr(p, addr) do {\ | ||
36 | (p).val |= ((addr) & VTD_PAGE_MASK); } while (0) | ||
37 | #define dma_pte_present(p) (((p).val & 3) != 0) | ||
38 | |||
39 | struct intel_iommu; | 17 | struct intel_iommu; |
40 | 18 | ||
41 | struct dmar_domain { | 19 | struct dmar_domain { |