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-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/mach-mx3/Kconfig12
-rw-r--r--arch/arm/mach-mx3/Makefile8
-rw-r--r--arch/arm/mach-mx3/Makefile.boot3
-rw-r--r--arch/arm/mach-mx3/mm.c64
-rw-r--r--arch/arm/mach-mx3/mx31ads.c142
-rw-r--r--arch/arm/mach-mx3/time.c152
-rw-r--r--arch/arm/mm/Kconfig5
-rw-r--r--arch/arm/plat-mxc/Kconfig20
-rw-r--r--arch/arm/plat-mxc/Makefile10
-rw-r--r--arch/arm/plat-mxc/irq.c83
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h142
-rw-r--r--include/asm-arm/arch-mxc/common.h20
-rw-r--r--include/asm-arm/arch-mxc/dma.h21
-rw-r--r--include/asm-arm/arch-mxc/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mxc/hardware.h52
-rw-r--r--include/asm-arm/arch-mxc/io.h33
-rw-r--r--include/asm-arm/arch-mxc/irqs.h38
-rw-r--r--include/asm-arm/arch-mxc/memory.h36
-rw-r--r--include/asm-arm/arch-mxc/mx31.h335
-rw-r--r--include/asm-arm/arch-mxc/mxc.h149
-rw-r--r--include/asm-arm/arch-mxc/system.h50
-rw-r--r--include/asm-arm/arch-mxc/timex.h25
-rw-r--r--include/asm-arm/arch-mxc/uncompress.h79
-rw-r--r--include/asm-arm/arch-mxc/vmalloc.h36
26 files changed, 1563 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a44c6da9bf83..0658e5d85131 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -324,6 +324,12 @@ config ARCH_NS9XXX
324 324
325 <http://www.digi.com/products/microprocessors/index.jsp> 325 <http://www.digi.com/products/microprocessors/index.jsp>
326 326
327config ARCH_MXC
328 bool "Freescale MXC/iMX-based"
329 select ARCH_MTD_XIP
330 help
331 Support for Freescale MXC/iMX-based family of processors
332
327config ARCH_PNX4008 333config ARCH_PNX4008
328 bool "Philips Nexperia PNX4008 Mobile" 334 bool "Philips Nexperia PNX4008 Mobile"
329 help 335 help
@@ -456,6 +462,8 @@ source "arch/arm/mach-realview/Kconfig"
456 462
457source "arch/arm/mach-at91/Kconfig" 463source "arch/arm/mach-at91/Kconfig"
458 464
465source "arch/arm/plat-mxc/Kconfig"
466
459source "arch/arm/mach-netx/Kconfig" 467source "arch/arm/mach-netx/Kconfig"
460 468
461source "arch/arm/mach-ns9xxx/Kconfig" 469source "arch/arm/mach-ns9xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index cbd5010d3bc3..fa4ea9ff0797 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -137,6 +137,8 @@ endif
137 textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000 137 textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
138 machine-$(CONFIG_ARCH_DAVINCI) := davinci 138 machine-$(CONFIG_ARCH_DAVINCI) := davinci
139 machine-$(CONFIG_ARCH_KS8695) := ks8695 139 machine-$(CONFIG_ARCH_KS8695) := ks8695
140 incdir-$(CONFIG_ARCH_MXC) := mxc
141 machine-$(CONFIG_ARCH_MX3) := mx3
140 142
141ifeq ($(CONFIG_ARCH_EBSA110),y) 143ifeq ($(CONFIG_ARCH_EBSA110),y)
142# This is what happens if you forget the IOCS16 line. 144# This is what happens if you forget the IOCS16 line.
@@ -183,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
183core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ 185core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
184core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ 186core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
185core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ 187core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
188core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
186 189
187drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ 190drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
188drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/ 191drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
new file mode 100644
index 000000000000..5fe8606cac08
--- /dev/null
+++ b/arch/arm/mach-mx3/Kconfig
@@ -0,0 +1,12 @@
1menu "MX3 Options"
2 depends on ARCH_MX3
3
4config MACH_MX31ADS
5 bool "Support MX31ADS platforms"
6 default y
7 help
8 Include support for MX31ADS platform. This includes specific
9 configurations for the board and its peripherals.
10
11endmenu
12
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
new file mode 100644
index 000000000000..cbec997f332a
--- /dev/null
+++ b/arch/arm/mach-mx3/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := mm.o time.o
8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
new file mode 100644
index 000000000000..e1dd366f836b
--- /dev/null
+++ b/arch/arm/mach-mx3/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
new file mode 100644
index 000000000000..41dad485ded9
--- /dev/null
+++ b/arch/arm/mach-mx3/mm.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/mm.h>
24#include <linux/init.h>
25#include <asm/hardware.h>
26#include <asm/pgtable.h>
27#include <asm/mach/map.h>
28#include <asm/arch/common.h>
29
30/*!
31 * @file mm.c
32 *
33 * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
34 *
35 * @ingroup Memory
36 */
37
38/*!
39 * This table defines static virtual address mappings for I/O regions.
40 * These are the mappings common across all MX3 boards.
41 */
42static struct map_desc mxc_io_desc[] __initdata = {
43 {
44 .virtual = X_MEMC_BASE_ADDR_VIRT,
45 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
46 .length = X_MEMC_SIZE,
47 .type = MT_DEVICE
48 }, {
49 .virtual = AVIC_BASE_ADDR_VIRT,
50 .pfn = __phys_to_pfn(AVIC_BASE_ADDR),
51 .length = AVIC_SIZE,
52 .type = MT_NONSHARED_DEVICE
53 },
54};
55
56/*!
57 * This function initializes the memory map. It is called during the
58 * system startup to create static physical to virtual memory mappings
59 * for the IO modules.
60 */
61void __init mxc_map_io(void)
62{
63 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
64}
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
new file mode 100644
index 000000000000..7e89bdc23a9f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -0,0 +1,142 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/serial_8250.h>
25
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/memory.h>
30#include <asm/mach/map.h>
31#include <asm/arch/common.h>
32
33/*!
34 * @file mx31ads.c
35 *
36 * @brief This file contains the board-specific initialization routines.
37 *
38 * @ingroup System
39 */
40
41#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
42/*!
43 * The serial port definition structure.
44 */
45static struct plat_serial8250_port serial_platform_data[] = {
46 {
47 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
48 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
49 .irq = EXPIO_INT_XUART_INTA,
50 .uartclk = 14745600,
51 .regshift = 0,
52 .iotype = UPIO_MEM,
53 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
54 }, {
55 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
56 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
57 .irq = EXPIO_INT_XUART_INTB,
58 .uartclk = 14745600,
59 .regshift = 0,
60 .iotype = UPIO_MEM,
61 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
62 },
63 {},
64};
65
66static struct platform_device serial_device = {
67 .name = "serial8250",
68 .id = 0,
69 .dev = {
70 .platform_data = serial_platform_data,
71 },
72};
73
74static int __init mxc_init_extuart(void)
75{
76 return platform_device_register(&serial_device);
77}
78#else
79static inline int mxc_init_extuart(void)
80{
81 return 0;
82}
83#endif
84
85/*!
86 * This structure defines static mappings for the i.MX31ADS board.
87 */
88static struct map_desc mx31ads_io_desc[] __initdata = {
89 {
90 .virtual = AIPS1_BASE_ADDR_VIRT,
91 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
92 .length = AIPS1_SIZE,
93 .type = MT_NONSHARED_DEVICE
94 }, {
95 .virtual = SPBA0_BASE_ADDR_VIRT,
96 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
97 .length = SPBA0_SIZE,
98 .type = MT_NONSHARED_DEVICE
99 }, {
100 .virtual = AIPS2_BASE_ADDR_VIRT,
101 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
102 .length = AIPS2_SIZE,
103 .type = MT_NONSHARED_DEVICE
104 }, {
105 .virtual = CS4_BASE_ADDR_VIRT,
106 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
107 .length = CS4_SIZE / 2,
108 .type = MT_DEVICE
109 },
110};
111
112/*!
113 * Set up static virtual mappings.
114 */
115void __init mx31ads_map_io(void)
116{
117 mxc_map_io();
118 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
119}
120
121/*!
122 * Board specific initialization.
123 */
124static void __init mxc_board_init(void)
125{
126 mxc_init_extuart();
127}
128
129/*
130 * The following uses standard kernel macros defined in arch.h in order to
131 * initialize __mach_desc_MX31ADS data structure.
132 */
133MACHINE_START(MX31ADS, "Freescale MX31ADS")
134 /* Maintainer: Freescale Semiconductor, Inc. */
135 .phys_io = AIPS1_BASE_ADDR,
136 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
137 .boot_params = PHYS_OFFSET + 0x100,
138 .map_io = mx31ads_map_io,
139 .init_irq = mxc_init_irq,
140 .init_machine = mxc_board_init,
141 .timer = &mxc_timer,
142MACHINE_END
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
new file mode 100644
index 000000000000..e81fb5c5d7c3
--- /dev/null
+++ b/arch/arm/mach-mx3/time.c
@@ -0,0 +1,152 @@
1/*
2 * System Timer Interrupt reconfigured to run in free-run mode.
3 * Author: Vitaly Wool
4 * Copyright 2004 MontaVista Software Inc.
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 */
7
8/*
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/*!
15 * @file time.c
16 * @brief This file contains OS tick and wdog timer implementations.
17 *
18 * This file contains OS tick and wdog timer implementations.
19 *
20 * @ingroup Timers
21 */
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <asm/hardware.h>
28#include <asm/mach/time.h>
29#include <asm/io.h>
30#include <asm/arch/common.h>
31
32/*!
33 * This is the timer interrupt service routine to do required tasks.
34 * It also services the WDOG timer at the frequency of twice per WDOG
35 * timeout value. For example, if the WDOG's timeout value is 4 (2
36 * seconds since the WDOG runs at 0.5Hz), it will be serviced once
37 * every 2/2=1 second.
38 *
39 * @param irq GPT interrupt source number (not used)
40 * @param dev_id this parameter is not used
41 * @return always returns \b IRQ_HANDLED as defined in
42 * include/linux/interrupt.h.
43 */
44static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
45{
46 unsigned int next_match;
47
48 write_seqlock(&xtime_lock);
49
50 if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
51 do {
52 timer_tick();
53 next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
54 __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
55 __raw_writel(next_match, MXC_GPT_GPTOCR1);
56 } while ((signed long)(next_match -
57 __raw_readl(MXC_GPT_GPTCNT)) <= 0);
58 }
59
60 write_sequnlock(&xtime_lock);
61
62 return IRQ_HANDLED;
63}
64
65/*!
66 * This function is used to obtain the number of microseconds since the last
67 * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
68 *
69 * @return the number of microseconds since the last timer interrupt.
70 */
71static unsigned long mxc_gettimeoffset(void)
72{
73 unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
74
75 /* Get ticks before next timer match */
76 ticks_to_match =
77 __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
78
79 /* We need elapsed ticks since last match */
80 elapsed = LATCH - ticks_to_match;
81
82 /* Now convert them to usec */
83 /* Insure no overflow when calculating the usec below */
84 for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
85 tick_usec /= i;
86 if ((0xFFFFFFFF / tick_usec) > elapsed)
87 break;
88 }
89 usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
90
91 return usec;
92}
93
94/*!
95 * The OS tick timer interrupt structure.
96 */
97static struct irqaction timer_irq = {
98 .name = "MXC Timer Tick",
99 .flags = IRQF_DISABLED | IRQF_TIMER,
100 .handler = mxc_timer_interrupt
101};
102
103/*!
104 * This function is used to initialize the GPT to produce an interrupt
105 * based on HZ. It is called by start_kernel() during system startup.
106 */
107void __init mxc_init_time(void)
108{
109 u32 reg, v;
110 reg = __raw_readl(MXC_GPT_GPTCR);
111 reg &= ~GPTCR_ENABLE;
112 __raw_writel(reg, MXC_GPT_GPTCR);
113 reg |= GPTCR_SWR;
114 __raw_writel(reg, MXC_GPT_GPTCR);
115
116 while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
117 cpu_relax();
118
119 reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
120 __raw_writel(reg, MXC_GPT_GPTCR);
121
122 /* TODO: get timer rate from clk driver */
123 v = 66500000;
124
125 __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
126
127 if ((v % CLOCK_TICK_RATE) != 0) {
128 pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
129 CLOCK_TICK_RATE);
130 }
131 pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
132 v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
133
134 reg = __raw_readl(MXC_GPT_GPTCNT);
135 reg += LATCH;
136 __raw_writel(reg, MXC_GPT_GPTOCR1);
137
138 setup_irq(MXC_INT_GPT, &timer_irq);
139
140 reg = __raw_readl(MXC_GPT_GPTCR);
141 reg =
142 GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
143 GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
144 __raw_writel(reg, MXC_GPT_GPTCR);
145
146 __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
147}
148
149struct sys_timer mxc_timer = {
150 .init = mxc_init_time,
151 .offset = mxc_gettimeoffset,
152};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e7904bc92c73..699b899214ae 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -345,7 +345,8 @@ config CPU_XSC3
345# ARMv6 345# ARMv6
346config CPU_V6 346config CPU_V6
347 bool "Support ARM V6 processor" 347 bool "Support ARM V6 processor"
348 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 348 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
349 default y if ARCH_MX3
349 select CPU_32v6 350 select CPU_32v6
350 select CPU_ABRT_EV6 351 select CPU_ABRT_EV6
351 select CPU_CACHE_V6 352 select CPU_CACHE_V6
@@ -359,7 +360,7 @@ config CPU_V6
359config CPU_32v6K 360config CPU_32v6K
360 bool "Support ARM V6K processor extensions" if !SMP 361 bool "Support ARM V6K processor extensions" if !SMP
361 depends on CPU_V6 362 depends on CPU_V6
362 default y if SMP 363 default y if SMP && !ARCH_MX3
363 help 364 help
364 Say Y here if your ARMv6 processor supports the 'K' extension. 365 Say Y here if your ARMv6 processor supports the 'K' extension.
365 This enables the kernel to use some instructions not present 366 This enables the kernel to use some instructions not present
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
new file mode 100644
index 000000000000..03a65c0dfb60
--- /dev/null
+++ b/arch/arm/plat-mxc/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_MXC
2
3menu "Freescale MXC Implementations"
4
5choice
6 prompt "MXC/iMX System Type"
7 default 0
8
9config ARCH_MX3
10 bool "MX3-based"
11 help
12 This enables support for systems based on the Freescale i.MX3 family
13
14endchoice
15
16source "arch/arm/mach-mx3/Kconfig"
17
18endmenu
19
20endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
new file mode 100644
index 000000000000..66ad9c2b6d64
--- /dev/null
+++ b/arch/arm/plat-mxc/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support
6obj-y := irq.o
7
8obj-m :=
9obj-n :=
10obj- :=
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
new file mode 100644
index 000000000000..87d253bc3d3c
--- /dev/null
+++ b/arch/arm/plat-mxc/irq.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <asm/hardware.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/mach/irq.h>
20#include <asm/arch/common.h>
21
22/*!
23 * Disable interrupt number "irq" in the AVIC
24 *
25 * @param irq interrupt source number
26 */
27static void mxc_mask_irq(unsigned int irq)
28{
29 __raw_writel(irq, AVIC_INTDISNUM);
30}
31
32/*!
33 * Enable interrupt number "irq" in the AVIC
34 *
35 * @param irq interrupt source number
36 */
37static void mxc_unmask_irq(unsigned int irq)
38{
39 __raw_writel(irq, AVIC_INTENNUM);
40}
41
42static struct irq_chip mxc_avic_chip = {
43 .mask_ack = mxc_mask_irq,
44 .mask = mxc_mask_irq,
45 .unmask = mxc_unmask_irq,
46};
47
48/*!
49 * This function initializes the AVIC hardware and disables all the
50 * interrupts. It registers the interrupt enable and disable functions
51 * to the kernel for each interrupt source.
52 */
53void __init mxc_init_irq(void)
54{
55 int i;
56 u32 reg;
57
58 /* put the AVIC into the reset value with
59 * all interrupts disabled
60 */
61 __raw_writel(0, AVIC_INTCNTL);
62 __raw_writel(0x1f, AVIC_NIMASK);
63
64 /* disable all interrupts */
65 __raw_writel(0, AVIC_INTENABLEH);
66 __raw_writel(0, AVIC_INTENABLEL);
67
68 /* all IRQ no FIQ */
69 __raw_writel(0, AVIC_INTTYPEH);
70 __raw_writel(0, AVIC_INTTYPEL);
71 for (i = 0; i < MXC_MAX_INT_LINES; i++) {
72 set_irq_chip(i, &mxc_avic_chip);
73 set_irq_handler(i, handle_level_irq);
74 set_irq_flags(i, IRQF_VALID);
75 }
76
77 /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
78 reg = __raw_readl(AVIC_NIPRIORITY6);
79 reg |= (0xF << 28);
80 __raw_writel(reg, AVIC_NIPRIORITY6);
81
82 printk(KERN_INFO "MXC IRQ initialized\n");
83}
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644
index 000000000000..be29b83ad4ae
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -0,0 +1,142 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14/*!
15 * @name PBC Controller parameters
16 */
17/*! @{ */
18/*!
19 * Base address of PBC controller
20 */
21#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
22/* Offsets for the PBC Controller register */
23/*!
24 * PBC Board status register offset
25 */
26#define PBC_BSTAT 0x000002
27/*!
28 * PBC Board control register 1 set address.
29 */
30#define PBC_BCTRL1_SET 0x000004
31/*!
32 * PBC Board control register 1 clear address.
33 */
34#define PBC_BCTRL1_CLEAR 0x000006
35/*!
36 * PBC Board control register 2 set address.
37 */
38#define PBC_BCTRL2_SET 0x000008
39/*!
40 * PBC Board control register 2 clear address.
41 */
42#define PBC_BCTRL2_CLEAR 0x00000A
43/*!
44 * PBC Board control register 3 set address.
45 */
46#define PBC_BCTRL3_SET 0x00000C
47/*!
48 * PBC Board control register 3 clear address.
49 */
50#define PBC_BCTRL3_CLEAR 0x00000E
51/*!
52 * PBC Board control register 4 set address.
53 */
54#define PBC_BCTRL4_SET 0x000010
55/*!
56 * PBC Board control register 4 clear address.
57 */
58#define PBC_BCTRL4_CLEAR 0x000012
59/*!
60 * PBC Board status register 1.
61 */
62#define PBC_BSTAT1 0x000014
63/*!
64 * PBC Board interrupt status register.
65 */
66#define PBC_INTSTATUS 0x000016
67/*!
68 * PBC Board interrupt current status register.
69 */
70#define PBC_INTCURR_STATUS 0x000018
71/*!
72 * PBC Interrupt mask register set address.
73 */
74#define PBC_INTMASK_SET 0x00001A
75/*!
76 * PBC Interrupt mask register clear address.
77 */
78#define PBC_INTMASK_CLEAR 0x00001C
79
80/*!
81 * External UART A.
82 */
83#define PBC_SC16C652_UARTA 0x010000
84/*!
85 * External UART B.
86 */
87#define PBC_SC16C652_UARTB 0x010010
88/*!
89 * Ethernet Controller IO base address.
90 */
91#define PBC_CS8900A_IOBASE 0x020000
92/*!
93 * Ethernet Controller Memory base address.
94 */
95#define PBC_CS8900A_MEMBASE 0x021000
96/*!
97 * Ethernet Controller DMA base address.
98 */
99#define PBC_CS8900A_DMABASE 0x022000
100/*!
101 * External chip select 0.
102 */
103#define PBC_XCS0 0x040000
104/*!
105 * LCD Display enable.
106 */
107#define PBC_LCD_EN_B 0x060000
108/*!
109 * Code test debug enable.
110 */
111#define PBC_CODE_B 0x070000
112/*!
113 * PSRAM memory select.
114 */
115#define PBC_PSRAM_B 0x5000000
116
117#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
118#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
119#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
120#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
121#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
122
123#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
124#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
125#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
126#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
127#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
128#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
129#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
130#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
131#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
132#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
133#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
134#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
135#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
136#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
137#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
138#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
139
140#define MXC_MAX_EXP_IO_LINES 16
141
142#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644
index 000000000000..23b4350edbd6
--- /dev/null
+++ b/include/asm-arm/arch-mxc/common.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
14struct sys_timer;
15
16extern void mxc_map_io(void);
17extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer;
19
20#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644
index 000000000000..65e639d51d2b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_DMA_H__
12#define __ASM_ARCH_MXC_DMA_H__
13
14/*!
15 * @file dma.h
16 * @brief This file contains Unified DMA API for all MXC platforms.
17 * The API is platform independent.
18 *
19 * @ingroup SDMA
20 */
21#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644
index 000000000000..b542433afb1b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 @ this macro disables fast irq (not implemented)
13 .macro disable_fiq
14 .endm
15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
22 @ this macro checks which interrupt occured
23 @ and returns its number in irqnr
24 @ and returns if an interrupt occured in irqstat
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26 ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
27 @ Load offset & priority of the highest priority
28 @ interrupt pending from AVIC_NIVECSR
29 ldr \irqstat, [\base, #0x40]
30 @ Shift to get the decoded IRQ number, using ASR so
31 @ 'no interrupt pending' becomes 0xffffffff
32 mov \irqnr, \irqstat, asr #16
33 @ set zero flag if IRQ + 1 == 0
34 adds \tmp, \irqnr, #1
35 .endm
36
37 @ irq priority table (not used)
38 .macro irq_prio_table
39 .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644
index 000000000000..3c09b92fef0d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*!
12 * @file hardware.h
13 * @brief This file contains the hardware definitions of the board.
14 *
15 * @ingroup System
16 */
17#ifndef __ASM_ARCH_MXC_HARDWARE_H__
18#define __ASM_ARCH_MXC_HARDWARE_H__
19
20#include <asm/sizes.h>
21
22#include <asm/arch/mx31.h>
23
24#include <asm/arch/mxc.h>
25
26#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
27
28/*
29 * ---------------------------------------------------------------------------
30 * Board specific defines
31 * ---------------------------------------------------------------------------
32 */
33#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
34
35#include <asm/arch/board-mx31ads.h>
36
37#ifndef MXC_MAX_EXP_IO_LINES
38#define MXC_MAX_EXP_IO_LINES 0
39#endif
40
41#define MXC_MAX_VIRTUAL_INTS 16
42#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
43#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
44#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
45#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
46
47#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \
48 MXC_MAX_GPIO_LINES + \
49 MXC_MAX_EXP_IO_LINES + \
50 MXC_MAX_VIRTUAL_INTS)
51
52#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644
index 000000000000..cf6c83a4b9f7
--- /dev/null
+++ b/include/asm-arm/arch-mxc/io.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*!
12 * @file io.h
13 * @brief This file contains some memory mapping macros.
14 * @note There is no real ISA or PCI buses. But have to define these macros
15 * for some drivers to compile.
16 *
17 * @ingroup System
18 */
19
20#ifndef __ASM_ARCH_MXC_IO_H__
21#define __ASM_ARCH_MXC_IO_H__
22
23/*! Allow IO space to be anywhere in the memory */
24#define IO_SPACE_LIMIT 0xffffffff
25
26/*!
27 * io address mapping macro
28 */
29#define __io(a) ((void __iomem *)(a))
30
31#define __mem_pci(a) (a)
32
33#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644
index 000000000000..e4686c6bc4bf
--- /dev/null
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_IRQS_H__
12#define __ASM_ARCH_MXC_IRQS_H__
13
14#include <asm/hardware.h>
15
16/*!
17 * @file irqs.h
18 * @brief This file defines the number of normal interrupts and fast interrupts
19 *
20 * @ingroup Interrupt
21 */
22
23#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
24
25#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
26#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
27
28/*!
29 * Number of normal interrupts
30 */
31#define NR_IRQS MXC_MAX_INTS
32
33/*!
34 * Number of fast interrupts
35 */
36#define NR_FIQS MXC_MAX_INTS
37
38#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644
index 000000000000..c89aac83a407
--- /dev/null
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__
13
14#include <asm/hardware.h>
15
16/*!
17 * @file memory.h
18 * @brief This file contains macros needed by the Linux kernel and drivers.
19 *
20 * @ingroup Memory
21 */
22
23/*!
24 * Virtual view <-> DMA view memory address translations
25 * This macro is used to translate the virtual address to an address
26 * suitable to be passed to set_dma_addr()
27 */
28#define __virt_to_bus(a) __virt_to_phys(a)
29
30/*!
31 * Used to convert an address for DMA operations to an address that the
32 * kernel can use.
33 */
34#define __bus_to_virt(a) __phys_to_virt(a)
35
36#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644
index 000000000000..85c49c9e5d15
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -0,0 +1,335 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*!
19 * defines the hardware clock tick rate
20 */
21#define CLOCK_TICK_RATE 16625000
22
23/*
24 * MX31 memory map:
25 *
26 * Virt Phys Size What
27 * ---------------------------------------------------------------------------
28 * F8000000 1FFC0000 16K IRAM
29 * F9000000 30000000 256M L2CC
30 * FC000000 43F00000 1M AIPS 1
31 * FC100000 50000000 1M SPBA
32 * FC200000 53F00000 1M AIPS 2
33 * FC500000 60000000 128M ROMPATCH
34 * FC400000 68000000 128M AVIC
35 * 70000000 256M IPU (MAX M2)
36 * 80000000 256M CSD0 SDRAM/DDR
37 * 90000000 256M CSD1 SDRAM/DDR
38 * A0000000 128M CS0 Flash
39 * A8000000 128M CS1 Flash
40 * B0000000 32M CS2
41 * B2000000 32M CS3
42 * F4000000 B4000000 32M CS4
43 * B6000000 32M CS5
44 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
45 * C0000000 64M PCMCIA/CF
46 */
47
48#define CS0_BASE_ADDR 0xA0000000
49#define CS1_BASE_ADDR 0xA8000000
50#define CS2_BASE_ADDR 0xB0000000
51#define CS3_BASE_ADDR 0xB2000000
52
53#define CS4_BASE_ADDR 0xB4000000
54#define CS4_BASE_ADDR_VIRT 0xF4000000
55#define CS4_SIZE SZ_32M
56
57#define CS5_BASE_ADDR 0xB6000000
58#define PCMCIA_MEM_BASE_ADDR 0xBC000000
59
60/*
61 * IRAM
62 */
63#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
64#define IRAM_BASE_ADDR_VIRT 0xF8000000
65#define IRAM_SIZE SZ_16K
66
67/*
68 * L2CC
69 */
70#define L2CC_BASE_ADDR 0x30000000
71#define L2CC_BASE_ADDR_VIRT 0xF9000000
72#define L2CC_SIZE SZ_1M
73
74/*
75 * AIPS 1
76 */
77#define AIPS1_BASE_ADDR 0x43F00000
78#define AIPS1_BASE_ADDR_VIRT 0xFC000000
79#define AIPS1_SIZE SZ_1M
80
81#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
82#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
83#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
84#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
85#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
86#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
87#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
88#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
89#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
90#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
91#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
92#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
93#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
94#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
95#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
96#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
97#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
98#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
99#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
100#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
101#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
102#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
103
104/*
105 * SPBA global module enabled #0
106 */
107#define SPBA0_BASE_ADDR 0x50000000
108#define SPBA0_BASE_ADDR_VIRT 0xFC100000
109#define SPBA0_SIZE SZ_1M
110
111#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
112#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
113#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
114#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
115#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
116#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
117#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
118#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
119#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
120#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
121#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
122
123/*
124 * AIPS 2
125 */
126#define AIPS2_BASE_ADDR 0x53F00000
127#define AIPS2_BASE_ADDR_VIRT 0xFC200000
128#define AIPS2_SIZE SZ_1M
129#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
130#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
131#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
132#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
133#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
134#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
135#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
136#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
137#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
138#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
139#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
140#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
141#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
142#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
143#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
144#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
145#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
146#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
147#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
148#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
149#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
150
151/*
152 * ROMP and AVIC
153 */
154#define ROMP_BASE_ADDR 0x60000000
155#define ROMP_BASE_ADDR_VIRT 0xFC500000
156#define ROMP_SIZE SZ_1M
157
158#define AVIC_BASE_ADDR 0x68000000
159#define AVIC_BASE_ADDR_VIRT 0xFC400000
160#define AVIC_SIZE SZ_1M
161
162/*
163 * NAND, SDRAM, WEIM, M3IF, EMI controllers
164 */
165#define X_MEMC_BASE_ADDR 0xB8000000
166#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
167#define X_MEMC_SIZE SZ_64K
168
169#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
170#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
171#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
172#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
173#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
174#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
175
176/*
177 * Memory regions and CS
178 */
179#define IPU_MEM_BASE_ADDR 0x70000000
180#define CSD0_BASE_ADDR 0x80000000
181#define CSD1_BASE_ADDR 0x90000000
182#define CS0_BASE_ADDR 0xA0000000
183#define CS1_BASE_ADDR 0xA8000000
184#define CS2_BASE_ADDR 0xB0000000
185#define CS3_BASE_ADDR 0xB2000000
186
187#define CS4_BASE_ADDR 0xB4000000
188#define CS4_BASE_ADDR_VIRT 0xF4000000
189#define CS4_SIZE SZ_32M
190
191#define CS5_BASE_ADDR 0xB6000000
192#define PCMCIA_MEM_BASE_ADDR 0xBC000000
193
194/*!
195 * This macro defines the physical to virtual address mapping for all the
196 * peripheral modules. It is used by passing in the physical address as x
197 * and returning the virtual address. If the physical address is not mapped,
198 * it returns 0xDEADBEEF
199 */
200#define IO_ADDRESS(x) \
201 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
202 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
203 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
204 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
205 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
206 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
207 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
208 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
209 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
210 0xDEADBEEF)
211
212/*
213 * define the address mapping macros: in physical address order
214 */
215
216#define IRAM_IO_ADDRESS(x) \
217 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
218
219#define L2CC_IO_ADDRESS(x) \
220 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
221
222#define AIPS1_IO_ADDRESS(x) \
223 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
224
225#define SPBA0_IO_ADDRESS(x) \
226 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
227
228#define AIPS2_IO_ADDRESS(x) \
229 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
230
231#define ROMP_IO_ADDRESS(x) \
232 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
233
234#define AVIC_IO_ADDRESS(x) \
235 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
236
237#define CS4_IO_ADDRESS(x) \
238 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
239
240#define X_MEMC_IO_ADDRESS(x) \
241 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
242
243#define PCMCIA_IO_ADDRESS(x) \
244 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
245
246/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
247#define PHYS_OFFSET CSD0_BASE_ADDR
248
249/*
250 * Interrupt numbers
251 */
252#define MXC_INT_PEN_ADS7843 0
253#define MXC_INT_RESV1 1
254#define MXC_INT_CS8900A 2
255#define MXC_INT_I2C3 3
256#define MXC_INT_I2C2 4
257#define MXC_INT_MPEG4_ENCODER 5
258#define MXC_INT_RTIC 6
259#define MXC_INT_FIRI 7
260#define MXC_INT_MMC_SDHC2 8
261#define MXC_INT_MMC_SDHC1 9
262#define MXC_INT_I2C 10
263#define MXC_INT_SSI2 11
264#define MXC_INT_SSI1 12
265#define MXC_INT_CSPI2 13
266#define MXC_INT_CSPI1 14
267#define MXC_INT_ATA 15
268#define MXC_INT_MBX 16
269#define MXC_INT_CSPI3 17
270#define MXC_INT_UART3 18
271#define MXC_INT_IIM 19
272#define MXC_INT_SIM2 20
273#define MXC_INT_SIM1 21
274#define MXC_INT_RNGA 22
275#define MXC_INT_EVTMON 23
276#define MXC_INT_KPP 24
277#define MXC_INT_RTC 25
278#define MXC_INT_PWM 26
279#define MXC_INT_EPIT2 27
280#define MXC_INT_EPIT1 28
281#define MXC_INT_GPT 29
282#define MXC_INT_RESV30 30
283#define MXC_INT_RESV31 31
284#define MXC_INT_UART2 32
285#define MXC_INT_NANDFC 33
286#define MXC_INT_SDMA 34
287#define MXC_INT_USB1 35
288#define MXC_INT_USB2 36
289#define MXC_INT_USB3 37
290#define MXC_INT_USB4 38
291#define MXC_INT_MSHC1 39
292#define MXC_INT_MSHC2 40
293#define MXC_INT_IPU_ERR 41
294#define MXC_INT_IPU_SYN 42
295#define MXC_INT_RESV43 43
296#define MXC_INT_RESV44 44
297#define MXC_INT_UART1 45
298#define MXC_INT_UART4 46
299#define MXC_INT_UART5 47
300#define MXC_INT_ECT 48
301#define MXC_INT_SCC_SCM 49
302#define MXC_INT_SCC_SMN 50
303#define MXC_INT_GPIO2 51
304#define MXC_INT_GPIO1 52
305#define MXC_INT_CCM 53
306#define MXC_INT_PCMCIA 54
307#define MXC_INT_WDOG 55
308#define MXC_INT_GPIO3 56
309#define MXC_INT_RESV57 57
310#define MXC_INT_EXT_POWER 58
311#define MXC_INT_EXT_TEMPER 59
312#define MXC_INT_EXT_SENSOR60 60
313#define MXC_INT_EXT_SENSOR61 61
314#define MXC_INT_EXT_WDOG 62
315#define MXC_INT_EXT_TV 63
316
317#define MXC_MAX_INT_LINES 64
318
319#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
320
321/*!
322 * Number of GPIO port as defined in the IC Spec
323 */
324#define GPIO_PORT_NUM 3
325/*!
326 * Number of GPIO pins per port
327 */
328#define GPIO_NUM_PIN 32
329
330#define PROD_SIGNATURE 0x1 /* For MX31 */
331
332#define SYSTEM_REV_MIN CHIP_REV_1_0
333#define SYSTEM_REV_NUM 3
334
335#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644
index 000000000000..0837f1f9ca31
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -0,0 +1,149 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_H__
12#define __ASM_ARCH_MXC_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 *****************************************
20 * GPT Register definitions *
21 *****************************************
22 */
23#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
24#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
25#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
26#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
27#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
28#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
29#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
30#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
31#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
32#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
33
34/*!
35 * GPT Control register bit definitions
36 */
37#define GPTCR_FO3 (1 << 31)
38#define GPTCR_FO2 (1 << 30)
39#define GPTCR_FO1 (1 << 29)
40
41#define GPTCR_OM3_SHIFT 26
42#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
43#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
44#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
45#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
48
49#define GPTCR_OM2_SHIFT 23
50#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
51#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
52#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
53#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
56
57#define GPTCR_OM1_SHIFT 20
58#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
59#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
60#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
61#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
64
65#define GPTCR_IM2_SHIFT 18
66#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
67#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
68#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
69#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
71
72#define GPTCR_IM1_SHIFT 16
73#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
74#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
75#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
76#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
78
79#define GPTCR_SWR (1 << 15)
80#define GPTCR_FRR (1 << 9)
81
82#define GPTCR_CLKSRC_SHIFT 6
83#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
84#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
85#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
86#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
88
89#define GPTCR_STOPEN (1 << 5)
90#define GPTCR_DOZEN (1 << 4)
91#define GPTCR_WAITEN (1 << 3)
92#define GPTCR_DBGEN (1 << 2)
93
94#define GPTCR_ENMOD (1 << 1)
95#define GPTCR_ENABLE (1 << 0)
96
97#define GPTSR_OF1 (1 << 0)
98#define GPTSR_OF2 (1 << 1)
99#define GPTSR_OF3 (1 << 2)
100#define GPTSR_IF1 (1 << 3)
101#define GPTSR_IF2 (1 << 4)
102#define GPTSR_ROV (1 << 5)
103
104#define GPTIR_OF1IE GPTSR_OF1
105#define GPTIR_OF2IE GPTSR_OF2
106#define GPTIR_OF3IE GPTSR_OF3
107#define GPTIR_IF1IE GPTSR_IF1
108#define GPTIR_IF2IE GPTSR_IF2
109#define GPTIR_ROVIE GPTSR_ROV
110
111/*
112 *****************************************
113 * AVIC Registers *
114 *****************************************
115 */
116#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
117#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
118#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
119#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
120#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
121#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
122#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
123#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
124#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
125#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
126#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
127#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
128#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
129#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
130#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
131#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
132#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
133#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
134#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
135#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
136#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
137#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
138#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
139#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
140#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
141#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
142#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
143
144#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
145#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
146#define IIM_PROD_REV_SH 3
147#define IIM_PROD_REV_LEN 5
148
149#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644
index 000000000000..109956b41aca
--- /dev/null
+++ b/include/asm-arm/arch-mxc/system.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__
22#define __ASM_ARCH_MXC_SYSTEM_H__
23
24/*!
25 * @file system.h
26 * @brief This file contains idle and reset functions.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * This function puts the CPU into idle mode. It is called by default_idle()
33 * in process.c file.
34 */
35static inline void arch_idle(void)
36{
37 cpu_do_idle();
38}
39
40/*
41 * This function resets the system. It is called by machine_restart().
42 *
43 * @param mode indicates different kinds of resets
44 */
45static inline void arch_reset(char mode)
46{
47 cpu_reset(0);
48}
49
50#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644
index 000000000000..59019fa58f82
--- /dev/null
+++ b/include/asm-arm/arch-mxc/timex.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_MXC_TIMEX_H__
21#define __ASM_ARCH_MXC_TIMEX_H__
22
23#include <asm/hardware.h> /* for CLOCK_TICK_RATE */
24
25#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644
index 000000000000..ec5787d0e78c
--- /dev/null
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -0,0 +1,79 @@
1/*
2 * include/asm-arm/arch-mxc/uncompress.h
3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
24#define __ASM_ARCH_MXC_UNCOMPRESS_H__
25
26#define __MXC_BOOT_UNCOMPRESS
27
28#include <asm/hardware.h>
29#include <asm/processor.h>
30
31#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
32
33#define USR2 0x98
34#define USR2_TXFE (1<<14)
35#define TXR 0x40
36#define UCR1 0x80
37#define UCR1_UARTEN 1
38
39/*
40 * The following code assumes the serial port has already been
41 * initialized by the bootloader. We search for the first enabled
42 * port in the most probable order. If you didn't setup a port in
43 * your bootloader then nothing will appear (which might be desired).
44 *
45 * This does not append a newline
46 */
47
48static void putc(int ch)
49{
50 static unsigned long serial_port = 0;
51
52 if (unlikely(serial_port == 0)) {
53 do {
54 serial_port = UART1_BASE_ADDR;
55 if (UART(UCR1) & UCR1_UARTEN)
56 break;
57 serial_port = UART2_BASE_ADDR;
58 if (UART(UCR1) & UCR1_UARTEN)
59 break;
60 return;
61 } while (0);
62 }
63
64 while (!(UART(USR2) & USR2_TXFE))
65 cpu_relax();
66
67 UART(TXR) = ch;
68}
69
70#define flush() do { } while (0)
71
72/*
73 * nothing to do
74 */
75#define arch_decomp_setup()
76
77#define arch_decomp_wdog()
78
79#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644
index 000000000000..83a73da895eb
--- /dev/null
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2000 Russell King.
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__
21#define __ASM_ARCH_MXC_VMALLOC_H__
22
23/*!
24 * @file vmalloc.h
25 *
26 * @brief This file contains platform specific macros for vmalloc.
27 *
28 * @ingroup System
29 */
30
31/*!
32 * vmalloc ending address
33 */
34#define VMALLOC_END 0xF4000000
35
36#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 02:20:20 -0500