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-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c614
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h14
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c497
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c541
4 files changed, 609 insertions, 1057 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index ba88d643edd3..ddd53c02be7a 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -31,8 +31,12 @@
31#include <linux/module.h> 31#include <linux/module.h>
32 32
33#include "rt2x00.h" 33#include "rt2x00.h"
34#ifdef CONFIG_RT2800USB
35#include "rt2x00usb.h"
36#endif
34#include "rt2800lib.h" 37#include "rt2800lib.h"
35#include "rt2800.h" 38#include "rt2800.h"
39#include "rt2800usb.h"
36 40
37MODULE_AUTHOR("Bartlomiej Zolnierkiewicz"); 41MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
38MODULE_DESCRIPTION("rt2800 library"); 42MODULE_DESCRIPTION("rt2800 library");
@@ -62,8 +66,8 @@ MODULE_LICENSE("GPL");
62 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 66 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
63 H2M_MAILBOX_CSR_OWNER, (__reg)) 67 H2M_MAILBOX_CSR_OWNER, (__reg))
64 68
65void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 69static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value) 70 const unsigned int word, const u8 value)
67{ 71{
68 u32 reg; 72 u32 reg;
69 73
@@ -87,10 +91,9 @@ void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
87 91
88 mutex_unlock(&rt2x00dev->csr_mutex); 92 mutex_unlock(&rt2x00dev->csr_mutex);
89} 93}
90EXPORT_SYMBOL_GPL(rt2800_bbp_write);
91 94
92void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, 95static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
93 const unsigned int word, u8 *value) 96 const unsigned int word, u8 *value)
94{ 97{
95 u32 reg; 98 u32 reg;
96 99
@@ -121,10 +124,9 @@ void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
121 124
122 mutex_unlock(&rt2x00dev->csr_mutex); 125 mutex_unlock(&rt2x00dev->csr_mutex);
123} 126}
124EXPORT_SYMBOL_GPL(rt2800_bbp_read);
125 127
126void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 128static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
127 const unsigned int word, const u8 value) 129 const unsigned int word, const u8 value)
128{ 130{
129 u32 reg; 131 u32 reg;
130 132
@@ -146,10 +148,9 @@ void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
146 148
147 mutex_unlock(&rt2x00dev->csr_mutex); 149 mutex_unlock(&rt2x00dev->csr_mutex);
148} 150}
149EXPORT_SYMBOL_GPL(rt2800_rfcsr_write);
150 151
151void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 152static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
152 const unsigned int word, u8 *value) 153 const unsigned int word, u8 *value)
153{ 154{
154 u32 reg; 155 u32 reg;
155 156
@@ -178,10 +179,9 @@ void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
178 179
179 mutex_unlock(&rt2x00dev->csr_mutex); 180 mutex_unlock(&rt2x00dev->csr_mutex);
180} 181}
181EXPORT_SYMBOL_GPL(rt2800_rfcsr_read);
182 182
183void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 183static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
184 const unsigned int word, const u32 value) 184 const unsigned int word, const u32 value)
185{ 185{
186 u32 reg; 186 u32 reg;
187 187
@@ -204,7 +204,6 @@ void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
204 204
205 mutex_unlock(&rt2x00dev->csr_mutex); 205 mutex_unlock(&rt2x00dev->csr_mutex);
206} 206}
207EXPORT_SYMBOL_GPL(rt2800_rf_write);
208 207
209void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 208void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
210 const u8 command, const u8 token, 209 const u8 command, const u8 token,
@@ -1074,3 +1073,588 @@ void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1074 ((qual->rssi > -80) * 0x10)); 1073 ((qual->rssi > -80) * 0x10));
1075} 1074}
1076EXPORT_SYMBOL_GPL(rt2800_link_tuner); 1075EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1076
1077/*
1078 * Initialization functions.
1079 */
1080int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1081{
1082 u32 reg;
1083 unsigned int i;
1084
1085 if (rt2x00_intf_is_usb(rt2x00dev)) {
1086 /*
1087 * Wait untill BBP and RF are ready.
1088 */
1089 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1090 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1091 if (reg && reg != ~0)
1092 break;
1093 msleep(1);
1094 }
1095
1096 if (i == REGISTER_BUSY_COUNT) {
1097 ERROR(rt2x00dev, "Unstable hardware.\n");
1098 return -EBUSY;
1099 }
1100
1101 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1102 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1103 reg & ~0x00002000);
1104 } else if (rt2x00_intf_is_pci(rt2x00dev))
1105 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1106
1107 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1108 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1109 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1110 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1111
1112 if (rt2x00_intf_is_usb(rt2x00dev)) {
1113 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1114#ifdef CONFIG_RT2800USB
1115 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1116 USB_MODE_RESET, REGISTER_TIMEOUT);
1117#endif
1118 }
1119
1120 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1121
1122 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1123 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1124 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1125 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1126 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1127 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1128
1129 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1130 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1131 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1132 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1133 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1134 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1135
1136 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1137 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1138
1139 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1140
1141 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1142 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1143 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1144 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1145 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1146 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1147 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1148 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149
1150 if (rt2x00_intf_is_usb(rt2x00dev) &&
1151 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1152 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1153 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1154 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1155 } else {
1156 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1157 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1158 }
1159
1160 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1161 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1162 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1163 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1164 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1165 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1166 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1167 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1168 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1169 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1170
1171 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1172 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1173 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1174 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1175
1176 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1177 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1178 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1179 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1180 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1181 else
1182 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1183 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1184 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1185 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1186
1187 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1188
1189 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1190 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1191 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1192 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1193 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1194 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1195 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1196
1197 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1198 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1199 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1200 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1201 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1202 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1203 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1204 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1205 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1206 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1207 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1208
1209 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1210 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1211 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1212 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1213 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1214 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1215 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1216 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1217 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1218 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1219 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1220
1221 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1222 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1223 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1224 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1225 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1226 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1227 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1228 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1229 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1230 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1231 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1232
1233 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1234 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1235 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1236 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1237 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1238 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1239 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1240 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1241 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1242 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1243 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1244
1245 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1246 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1247 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1248 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1249 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1250 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1251 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1252 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1253 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1254 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1255 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1256
1257 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1258 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1259 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1260 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1261 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1262 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1263 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1264 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1265 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1266 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1267 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1268
1269 if (rt2x00_intf_is_usb(rt2x00dev)) {
1270 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1271
1272 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1273 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1274 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1275 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1282 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1283 }
1284
1285 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1286 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1287
1288 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1289 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1290 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1291 IEEE80211_MAX_RTS_THRESHOLD);
1292 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1293 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1294
1295 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1296 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1297
1298 /*
1299 * ASIC will keep garbage value after boot, clear encryption keys.
1300 */
1301 for (i = 0; i < 4; i++)
1302 rt2800_register_write(rt2x00dev,
1303 SHARED_KEY_MODE_ENTRY(i), 0);
1304
1305 for (i = 0; i < 256; i++) {
1306 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1307 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1308 wcid, sizeof(wcid));
1309
1310 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1311 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1312 }
1313
1314 /*
1315 * Clear all beacons
1316 * For the Beacon base registers we only need to clear
1317 * the first byte since that byte contains the VALID and OWNER
1318 * bits which (when set to 0) will invalidate the entire beacon.
1319 */
1320 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1321 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1322 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1323 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1324 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1325 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1326 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1327 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1328
1329 if (rt2x00_intf_is_usb(rt2x00dev)) {
1330 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1331 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1332 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1333 }
1334
1335 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1336 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1337 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1338 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1339 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1340 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1341 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1342 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1343 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1344 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1345
1346 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1347 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1348 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1349 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1350 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1351 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1352 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1353 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1354 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1355 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1356
1357 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1358 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1359 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1360 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1361 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1362 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1363 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1364 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1365 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1366 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1367
1368 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1369 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1370 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1371 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1372 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1373 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1374
1375 /*
1376 * We must clear the error counters.
1377 * These registers are cleared on read,
1378 * so we may pass a useless variable to store the value.
1379 */
1380 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1381 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1382 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1383 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1384 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1385 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1386
1387 return 0;
1388}
1389EXPORT_SYMBOL_GPL(rt2800_init_registers);
1390
1391static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1392{
1393 unsigned int i;
1394 u32 reg;
1395
1396 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1397 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1398 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1399 return 0;
1400
1401 udelay(REGISTER_BUSY_DELAY);
1402 }
1403
1404 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1405 return -EACCES;
1406}
1407
1408static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1409{
1410 unsigned int i;
1411 u8 value;
1412
1413 /*
1414 * BBP was enabled after firmware was loaded,
1415 * but we need to reactivate it now.
1416 */
1417 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1418 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1419 msleep(1);
1420
1421 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1422 rt2800_bbp_read(rt2x00dev, 0, &value);
1423 if ((value != 0xff) && (value != 0x00))
1424 return 0;
1425 udelay(REGISTER_BUSY_DELAY);
1426 }
1427
1428 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1429 return -EACCES;
1430}
1431
1432int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1433{
1434 unsigned int i;
1435 u16 eeprom;
1436 u8 reg_id;
1437 u8 value;
1438
1439 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1440 rt2800_wait_bbp_ready(rt2x00dev)))
1441 return -EACCES;
1442
1443 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1444 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1445 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1446 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1447 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1448 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1449 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1450 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1451 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1452 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1453 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1454 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1455 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1456 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1457
1458 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1459 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1460 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1461 }
1462
1463 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1464 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1465
1466 if (rt2x00_intf_is_usb(rt2x00dev) &&
1467 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1468 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1469 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1470 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1471 }
1472
1473 if (rt2x00_intf_is_pci(rt2x00dev) &&
1474 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1475 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1476 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1477 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1478 }
1479
1480 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1482
1483 if (eeprom != 0xffff && eeprom != 0x0000) {
1484 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1485 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1486 rt2800_bbp_write(rt2x00dev, reg_id, value);
1487 }
1488 }
1489
1490 return 0;
1491}
1492EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1493
1494static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1495 bool bw40, u8 rfcsr24, u8 filter_target)
1496{
1497 unsigned int i;
1498 u8 bbp;
1499 u8 rfcsr;
1500 u8 passband;
1501 u8 stopband;
1502 u8 overtuned = 0;
1503
1504 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1505
1506 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1507 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1508 rt2800_bbp_write(rt2x00dev, 4, bbp);
1509
1510 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1511 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1512 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1513
1514 /*
1515 * Set power & frequency of passband test tone
1516 */
1517 rt2800_bbp_write(rt2x00dev, 24, 0);
1518
1519 for (i = 0; i < 100; i++) {
1520 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1521 msleep(1);
1522
1523 rt2800_bbp_read(rt2x00dev, 55, &passband);
1524 if (passband)
1525 break;
1526 }
1527
1528 /*
1529 * Set power & frequency of stopband test tone
1530 */
1531 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1532
1533 for (i = 0; i < 100; i++) {
1534 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1535 msleep(1);
1536
1537 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1538
1539 if ((passband - stopband) <= filter_target) {
1540 rfcsr24++;
1541 overtuned += ((passband - stopband) == filter_target);
1542 } else
1543 break;
1544
1545 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1546 }
1547
1548 rfcsr24 -= !!overtuned;
1549
1550 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1551 return rfcsr24;
1552}
1553
1554int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1555{
1556 u8 rfcsr;
1557 u8 bbp;
1558
1559 if (rt2x00_intf_is_usb(rt2x00dev) &&
1560 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1561 return 0;
1562
1563 if (rt2x00_intf_is_pci(rt2x00dev)) {
1564 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1565 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1566 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1567 return 0;
1568 }
1569
1570 /*
1571 * Init RF calibration.
1572 */
1573 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1574 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1575 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1576 msleep(1);
1577 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1578 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1579
1580 if (rt2x00_intf_is_usb(rt2x00dev)) {
1581 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1582 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1583 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1584 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1585 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1586 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1587 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1588 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1589 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1590 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1591 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1592 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1593 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1594 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1595 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1596 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1597 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1598 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1599 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1600 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1601 } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1602 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1603 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1604 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1605 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1606 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1607 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1608 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1609 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1610 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1611 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1612 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1613 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1614 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1615 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1616 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1617 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1618 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1619 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1620 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1621 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1622 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1623 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1624 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1625 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1626 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1627 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1628 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1629 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1630 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1631 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1632 }
1633
1634 /*
1635 * Set RX Filter calibration for 20MHz and 40MHz
1636 */
1637 rt2x00dev->calibration[0] =
1638 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1639 rt2x00dev->calibration[1] =
1640 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1641
1642 /*
1643 * Set back to initial state
1644 */
1645 rt2800_bbp_write(rt2x00dev, 24, 0);
1646
1647 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1648 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1649 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1650
1651 /*
1652 * set BBP back to BW20
1653 */
1654 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1655 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1656 rt2800_bbp_write(rt2x00dev, 4, bbp);
1657
1658 return 0;
1659}
1660EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index b07caba37817..2da8f79215fd 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -96,16 +96,6 @@ static inline int rt2800_regbusy_read(struct rt2x00_dev *rt2x00dev,
96 return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg); 96 return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg);
97} 97}
98 98
99void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
100 const unsigned int word, const u8 value);
101void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
102 const unsigned int word, u8 *value);
103void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, const u8 value);
105void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
106 const unsigned int word, u8 *value);
107void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
108 const unsigned int word, const u32 value);
109void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 99void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
110 const u8 command, const u8 token, 100 const u8 command, const u8 token,
111 const u8 arg0, const u8 arg1); 101 const u8 arg0, const u8 arg1);
@@ -135,4 +125,8 @@ void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
135void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 125void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
136 const u32 count); 126 const u32 count);
137 127
128int rt2800_init_registers(struct rt2x00_dev *rt2x00dev);
129int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev);
130int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
131
138#endif /* RT2800LIB_H */ 132#endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index cbf8be3057ef..78086cce55ee 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -420,497 +420,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
420 return 0; 420 return 0;
421} 421}
422 422
423static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
424{
425 u32 reg;
426 unsigned int i;
427
428 if (rt2x00_intf_is_pci(rt2x00dev))
429 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
430
431 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
432 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
433 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
434 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
435
436 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
437
438 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
439 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
440 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
441 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
442 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
443 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
444
445 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
446 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
447 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
448 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
449 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
450 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
451
452 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
453 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
454
455 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
456
457 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
458 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
459 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
460 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
461 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
462 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
463 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
464 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
465
466 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
467 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
468
469 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
470 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
471 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
472 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
473 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
474 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
475 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
476 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
477 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
478 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
479
480 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
481 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
482 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
483 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
484
485 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
486 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
487 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
488 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
489 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
490 else
491 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
492 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
493 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
494 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
495
496 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
497
498 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
499 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
500 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
501 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
502 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
503 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
504 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
505
506 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
507 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
508 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
509 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
510 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
511 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
512 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
513 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
514 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
515 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
516 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
517
518 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
519 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
520 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
521 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
522 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
523 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
524 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
525 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
526 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
527 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
528 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
529
530 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
531 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
532 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
533 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
534 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
535 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
536 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
537 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
538 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
539 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
540 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
541
542 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
543 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
544 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
545 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
546 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
547 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
548 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
549 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
550 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
551 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
552 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
553
554 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
555 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
556 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
557 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
558 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
559 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
560 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
561 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
562 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
563 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
564 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
565
566 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
567 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
568 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
569 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
570 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
571 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
572 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
573 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
574 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
575 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
576 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
577
578 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
579 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
580
581 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
582 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
583 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
584 IEEE80211_MAX_RTS_THRESHOLD);
585 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
586 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
587
588 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
589 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
590
591 /*
592 * ASIC will keep garbage value after boot, clear encryption keys.
593 */
594 for (i = 0; i < 4; i++)
595 rt2800_register_write(rt2x00dev,
596 SHARED_KEY_MODE_ENTRY(i), 0);
597
598 for (i = 0; i < 256; i++) {
599 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
600 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
601 wcid, sizeof(wcid));
602
603 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
604 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
605 }
606
607 /*
608 * Clear all beacons
609 * For the Beacon base registers we only need to clear
610 * the first byte since that byte contains the VALID and OWNER
611 * bits which (when set to 0) will invalidate the entire beacon.
612 */
613 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
614 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
615 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
616 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
617 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
618 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
619 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
620 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
621
622 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
623 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
624 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
625 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
626 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
627 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
628 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
629 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
630 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
631 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
632
633 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
634 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
635 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
636 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
637 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
638 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
639 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
640 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
641 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
642 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
643
644 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
645 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
646 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
647 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
648 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
649 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
650 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
651 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
652 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
653 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
654
655 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
656 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
657 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
658 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
659 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
660 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
661
662 /*
663 * We must clear the error counters.
664 * These registers are cleared on read,
665 * so we may pass a useless variable to store the value.
666 */
667 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
668 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
669 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
670 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
671 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
672 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
673
674 return 0;
675}
676
677static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
678{
679 unsigned int i;
680 u32 reg;
681
682 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
683 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
684 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
685 return 0;
686
687 udelay(REGISTER_BUSY_DELAY);
688 }
689
690 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
691 return -EACCES;
692}
693
694static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
695{
696 unsigned int i;
697 u8 value;
698
699 /*
700 * BBP was enabled after firmware was loaded,
701 * but we need to reactivate it now.
702 */
703 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
704 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
705 msleep(1);
706
707 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
708 rt2800_bbp_read(rt2x00dev, 0, &value);
709 if ((value != 0xff) && (value != 0x00))
710 return 0;
711 udelay(REGISTER_BUSY_DELAY);
712 }
713
714 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
715 return -EACCES;
716}
717
718static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
719{
720 unsigned int i;
721 u16 eeprom;
722 u8 reg_id;
723 u8 value;
724
725 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
726 rt2800pci_wait_bbp_ready(rt2x00dev)))
727 return -EACCES;
728
729 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
730 rt2800_bbp_write(rt2x00dev, 66, 0x38);
731 rt2800_bbp_write(rt2x00dev, 69, 0x12);
732 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
733 rt2800_bbp_write(rt2x00dev, 73, 0x10);
734 rt2800_bbp_write(rt2x00dev, 81, 0x37);
735 rt2800_bbp_write(rt2x00dev, 82, 0x62);
736 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
737 rt2800_bbp_write(rt2x00dev, 84, 0x99);
738 rt2800_bbp_write(rt2x00dev, 86, 0x00);
739 rt2800_bbp_write(rt2x00dev, 91, 0x04);
740 rt2800_bbp_write(rt2x00dev, 92, 0x00);
741 rt2800_bbp_write(rt2x00dev, 103, 0x00);
742 rt2800_bbp_write(rt2x00dev, 105, 0x05);
743
744 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
745 rt2800_bbp_write(rt2x00dev, 69, 0x16);
746 rt2800_bbp_write(rt2x00dev, 73, 0x12);
747 }
748
749 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
750 rt2800_bbp_write(rt2x00dev, 84, 0x19);
751
752 if (rt2x00_intf_is_pci(rt2x00dev) &&
753 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
754 rt2800_bbp_write(rt2x00dev, 31, 0x08);
755 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
756 rt2800_bbp_write(rt2x00dev, 80, 0x08);
757 }
758
759 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
760 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
761
762 if (eeprom != 0xffff && eeprom != 0x0000) {
763 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
764 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
765 rt2800_bbp_write(rt2x00dev, reg_id, value);
766 }
767 }
768
769 return 0;
770}
771
772static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
773 bool bw40, u8 rfcsr24, u8 filter_target)
774{
775 unsigned int i;
776 u8 bbp;
777 u8 rfcsr;
778 u8 passband;
779 u8 stopband;
780 u8 overtuned = 0;
781
782 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
783
784 rt2800_bbp_read(rt2x00dev, 4, &bbp);
785 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
786 rt2800_bbp_write(rt2x00dev, 4, bbp);
787
788 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
789 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
790 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
791
792 /*
793 * Set power & frequency of passband test tone
794 */
795 rt2800_bbp_write(rt2x00dev, 24, 0);
796
797 for (i = 0; i < 100; i++) {
798 rt2800_bbp_write(rt2x00dev, 25, 0x90);
799 msleep(1);
800
801 rt2800_bbp_read(rt2x00dev, 55, &passband);
802 if (passband)
803 break;
804 }
805
806 /*
807 * Set power & frequency of stopband test tone
808 */
809 rt2800_bbp_write(rt2x00dev, 24, 0x06);
810
811 for (i = 0; i < 100; i++) {
812 rt2800_bbp_write(rt2x00dev, 25, 0x90);
813 msleep(1);
814
815 rt2800_bbp_read(rt2x00dev, 55, &stopband);
816
817 if ((passband - stopband) <= filter_target) {
818 rfcsr24++;
819 overtuned += ((passband - stopband) == filter_target);
820 } else
821 break;
822
823 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
824 }
825
826 rfcsr24 -= !!overtuned;
827
828 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
829 return rfcsr24;
830}
831
832static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
833{
834 u8 rfcsr;
835 u8 bbp;
836
837 if (rt2x00_intf_is_pci(rt2x00dev)) {
838 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
839 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
840 !rt2x00_rf(&rt2x00dev->chip, RF3022))
841 return 0;
842 }
843
844 /*
845 * Init RF calibration.
846 */
847 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
848 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
849 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
850 msleep(1);
851 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
852 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
853
854 if (rt2x00_intf_is_pci(rt2x00dev)) {
855 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
856 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
857 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
858 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
859 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
860 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
861 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
862 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
863 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
864 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
865 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
866 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
867 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
868 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
869 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
870 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
871 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
872 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
873 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
874 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
875 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
876 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
877 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
878 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
879 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
880 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
881 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
882 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
883 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
884 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
885 }
886
887 /*
888 * Set RX Filter calibration for 20MHz and 40MHz
889 */
890 rt2x00dev->calibration[0] =
891 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
892 rt2x00dev->calibration[1] =
893 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
894
895 /*
896 * Set back to initial state
897 */
898 rt2800_bbp_write(rt2x00dev, 24, 0);
899
900 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
901 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
902 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
903
904 /*
905 * set BBP back to BW20
906 */
907 rt2800_bbp_read(rt2x00dev, 4, &bbp);
908 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
909 rt2800_bbp_write(rt2x00dev, 4, bbp);
910
911 return 0;
912}
913
914/* 423/*
915 * Device state switch handlers. 424 * Device state switch handlers.
916 */ 425 */
@@ -991,10 +500,10 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
991 */ 500 */
992 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) || 501 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
993 rt2800pci_init_queues(rt2x00dev) || 502 rt2800pci_init_queues(rt2x00dev) ||
994 rt2800pci_init_registers(rt2x00dev) || 503 rt2800_init_registers(rt2x00dev) ||
995 rt2800pci_wait_wpdma_ready(rt2x00dev) || 504 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
996 rt2800pci_init_bbp(rt2x00dev) || 505 rt2800_init_bbp(rt2x00dev) ||
997 rt2800pci_init_rfcsr(rt2x00dev))) 506 rt2800_init_rfcsr(rt2x00dev)))
998 return -EIO; 507 return -EIO;
999 508
1000 /* 509 /*
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 365f66fe7c68..f5b864b1a55d 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -230,541 +230,6 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
230} 230}
231 231
232/* 232/*
233 * Initialization functions.
234 */
235static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238 unsigned int i;
239
240 if (rt2x00_intf_is_usb(rt2x00dev)) {
241 /*
242 * Wait untill BBP and RF are ready.
243 */
244 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
245 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
246 if (reg && reg != ~0)
247 break;
248 msleep(1);
249 }
250
251 if (i == REGISTER_BUSY_COUNT) {
252 ERROR(rt2x00dev, "Unstable hardware.\n");
253 return -EBUSY;
254 }
255
256 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
257 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
258 reg & ~0x00002000);
259 }
260
261 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
262 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
263 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
264 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
265
266 if (rt2x00_intf_is_usb(rt2x00dev)) {
267 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
268
269 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
270 USB_MODE_RESET, REGISTER_TIMEOUT);
271 }
272
273 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
274
275 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
276 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
277 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
278 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
279 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
280 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
281
282 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
283 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
284 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
285 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
286 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
287 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
288
289 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
290 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
291
292 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
293
294 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
295 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
296 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
297 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
298 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
299 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
301 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
302
303 if (rt2x00_intf_is_usb(rt2x00dev) &&
304 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
305 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
306 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
307 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
308 } else {
309 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
310 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
311 }
312
313 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
314 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
315 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
316 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
317 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
318 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
319 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
320 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
321 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
322 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
323
324 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
325 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
326 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
327 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
328
329 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
330 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
331 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
332 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
333 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
334 else
335 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
336 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
337 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
338 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
339
340 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
341
342 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
343 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
344 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
345 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
346 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
347 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
348 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
349
350 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
351 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
352 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
353 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
354 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
355 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
356 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
357 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
358 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
359 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
360 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
361
362 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
363 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
364 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
365 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
366 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
367 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
368 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
369 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
370 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
371 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
372 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
373
374 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
375 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
376 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
377 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
378 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
379 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
380 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
381 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
382 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
383 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
384 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
385
386 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
387 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
388 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
389 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
390 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
391 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
392 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
393 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
394 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
395 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
396 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
397
398 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
399 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
400 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
401 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
402 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
403 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
404 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
405 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
406 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
407 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
408 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
409
410 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
411 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
412 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
413 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
414 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
415 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
416 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
417 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
418 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
419 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
420 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
421
422 if (rt2x00_intf_is_usb(rt2x00dev)) {
423 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
424
425 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
429 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
434 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
435 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
436 }
437
438 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
439 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
440
441 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
442 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
443 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
444 IEEE80211_MAX_RTS_THRESHOLD);
445 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
446 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
447
448 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
449 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
450
451 /*
452 * ASIC will keep garbage value after boot, clear encryption keys.
453 */
454 for (i = 0; i < 4; i++)
455 rt2800_register_write(rt2x00dev,
456 SHARED_KEY_MODE_ENTRY(i), 0);
457
458 for (i = 0; i < 256; i++) {
459 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
460 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
461 wcid, sizeof(wcid));
462
463 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
464 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
465 }
466
467 /*
468 * Clear all beacons
469 * For the Beacon base registers we only need to clear
470 * the first byte since that byte contains the VALID and OWNER
471 * bits which (when set to 0) will invalidate the entire beacon.
472 */
473 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
474 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
475 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
476 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
477 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
478 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
479 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
480 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
481
482 if (rt2x00_intf_is_usb(rt2x00dev)) {
483 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
484 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
485 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
486 }
487
488 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
489 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
490 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
491 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
492 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
493 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
494 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
495 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
496 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
497 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
498
499 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
500 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
501 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
502 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
503 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
504 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
505 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
506 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
507 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
508 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
509
510 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
511 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
512 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
513 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
514 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
515 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
516 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
517 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
518 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
519 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
520
521 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
522 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
523 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
524 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
525 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
526 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
527
528 /*
529 * We must clear the error counters.
530 * These registers are cleared on read,
531 * so we may pass a useless variable to store the value.
532 */
533 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
534 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
535 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
536 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
537 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
538 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
539
540 return 0;
541}
542
543static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
544{
545 unsigned int i;
546 u32 reg;
547
548 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
549 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
550 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
551 return 0;
552
553 udelay(REGISTER_BUSY_DELAY);
554 }
555
556 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
557 return -EACCES;
558}
559
560static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
561{
562 unsigned int i;
563 u8 value;
564
565 /*
566 * BBP was enabled after firmware was loaded,
567 * but we need to reactivate it now.
568 */
569 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
570 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
571 msleep(1);
572
573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
574 rt2800_bbp_read(rt2x00dev, 0, &value);
575 if ((value != 0xff) && (value != 0x00))
576 return 0;
577 udelay(REGISTER_BUSY_DELAY);
578 }
579
580 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
581 return -EACCES;
582}
583
584static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
585{
586 unsigned int i;
587 u16 eeprom;
588 u8 reg_id;
589 u8 value;
590
591 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
592 rt2800usb_wait_bbp_ready(rt2x00dev)))
593 return -EACCES;
594
595 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
596 rt2800_bbp_write(rt2x00dev, 66, 0x38);
597 rt2800_bbp_write(rt2x00dev, 69, 0x12);
598 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
599 rt2800_bbp_write(rt2x00dev, 73, 0x10);
600 rt2800_bbp_write(rt2x00dev, 81, 0x37);
601 rt2800_bbp_write(rt2x00dev, 82, 0x62);
602 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
603 rt2800_bbp_write(rt2x00dev, 84, 0x99);
604 rt2800_bbp_write(rt2x00dev, 86, 0x00);
605 rt2800_bbp_write(rt2x00dev, 91, 0x04);
606 rt2800_bbp_write(rt2x00dev, 92, 0x00);
607 rt2800_bbp_write(rt2x00dev, 103, 0x00);
608 rt2800_bbp_write(rt2x00dev, 105, 0x05);
609
610 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
611 rt2800_bbp_write(rt2x00dev, 69, 0x16);
612 rt2800_bbp_write(rt2x00dev, 73, 0x12);
613 }
614
615 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
616 rt2800_bbp_write(rt2x00dev, 84, 0x19);
617
618 if (rt2x00_intf_is_usb(rt2x00dev) &&
619 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
620 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
621 rt2800_bbp_write(rt2x00dev, 84, 0x99);
622 rt2800_bbp_write(rt2x00dev, 105, 0x05);
623 }
624
625 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
626 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
627
628 if (eeprom != 0xffff && eeprom != 0x0000) {
629 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
630 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
631 rt2800_bbp_write(rt2x00dev, reg_id, value);
632 }
633 }
634
635 return 0;
636}
637
638static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
639 bool bw40, u8 rfcsr24, u8 filter_target)
640{
641 unsigned int i;
642 u8 bbp;
643 u8 rfcsr;
644 u8 passband;
645 u8 stopband;
646 u8 overtuned = 0;
647
648 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
649
650 rt2800_bbp_read(rt2x00dev, 4, &bbp);
651 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
652 rt2800_bbp_write(rt2x00dev, 4, bbp);
653
654 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
655 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
656 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
657
658 /*
659 * Set power & frequency of passband test tone
660 */
661 rt2800_bbp_write(rt2x00dev, 24, 0);
662
663 for (i = 0; i < 100; i++) {
664 rt2800_bbp_write(rt2x00dev, 25, 0x90);
665 msleep(1);
666
667 rt2800_bbp_read(rt2x00dev, 55, &passband);
668 if (passband)
669 break;
670 }
671
672 /*
673 * Set power & frequency of stopband test tone
674 */
675 rt2800_bbp_write(rt2x00dev, 24, 0x06);
676
677 for (i = 0; i < 100; i++) {
678 rt2800_bbp_write(rt2x00dev, 25, 0x90);
679 msleep(1);
680
681 rt2800_bbp_read(rt2x00dev, 55, &stopband);
682
683 if ((passband - stopband) <= filter_target) {
684 rfcsr24++;
685 overtuned += ((passband - stopband) == filter_target);
686 } else
687 break;
688
689 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
690 }
691
692 rfcsr24 -= !!overtuned;
693
694 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
695 return rfcsr24;
696}
697
698static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
699{
700 u8 rfcsr;
701 u8 bbp;
702
703 if (rt2x00_intf_is_usb(rt2x00dev) &&
704 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
705 return 0;
706
707 /*
708 * Init RF calibration.
709 */
710 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
711 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
712 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
713 msleep(1);
714 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
715 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
716
717 if (rt2x00_intf_is_usb(rt2x00dev)) {
718 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
719 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
720 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
721 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
722 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
723 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
724 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
725 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
726 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
727 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
728 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
729 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
730 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
731 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
732 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
733 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
734 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
735 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
736 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
737 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
738 }
739
740 /*
741 * Set RX Filter calibration for 20MHz and 40MHz
742 */
743 rt2x00dev->calibration[0] =
744 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
745 rt2x00dev->calibration[1] =
746 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
747
748 /*
749 * Set back to initial state
750 */
751 rt2800_bbp_write(rt2x00dev, 24, 0);
752
753 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
754 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
755 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
756
757 /*
758 * set BBP back to BW20
759 */
760 rt2800_bbp_read(rt2x00dev, 4, &bbp);
761 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
762 rt2800_bbp_write(rt2x00dev, 4, bbp);
763
764 return 0;
765}
766
767/*
768 * Device state switch handlers. 233 * Device state switch handlers.
769 */ 234 */
770static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev, 235static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
@@ -806,9 +271,9 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
806 * Initialize all registers. 271 * Initialize all registers.
807 */ 272 */
808 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) || 273 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
809 rt2800usb_init_registers(rt2x00dev) || 274 rt2800_init_registers(rt2x00dev) ||
810 rt2800usb_init_bbp(rt2x00dev) || 275 rt2800_init_bbp(rt2x00dev) ||
811 rt2800usb_init_rfcsr(rt2x00dev))) 276 rt2800_init_rfcsr(rt2x00dev)))
812 return -EIO; 277 return -EIO;
813 278
814 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 279 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 11:00:49 -0500