aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--include/asm-mips/mach-excite/excite_fpga.h2
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h2
-rw-r--r--include/asm-mips/sgi/ip22.h2
-rw-r--r--include/asm-mips/sn/sn0/hubio.h2
4 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h
index 38fcda703a0b..0a1ef69bece7 100644
--- a/include/asm-mips/mach-excite/excite_fpga.h
+++ b/include/asm-mips/mach-excite/excite_fpga.h
@@ -3,7 +3,7 @@
3 3
4 4
5/** 5/**
6 * Adress alignment of the individual FPGA bytes. 6 * Address alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two 7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform. 8 * byte aligned at the embedded MK2 platform.
9 */ 9 */
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
index 00d8bf6164a9..83746b84a5ec 100644
--- a/include/asm-mips/mach-wrppmc/mach-gt64120.h
+++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h
@@ -45,7 +45,7 @@
45#define GT_PCI_IO_SIZE 0x02000000UL 45#define GT_PCI_IO_SIZE 0x02000000UL
46 46
47/* 47/*
48 * PCI interrupts will come in on either the INTA or INTD interrups lines, 48 * PCI interrupts will come in on either the INTA or INTD interrupt lines,
49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our 49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
50 * boards, they all either come in on IntD or they all come in on IntA, they 50 * boards, they all either come in on IntD or they all come in on IntA, they
51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the 51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index f4981c4f16bb..c0501f91719b 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -15,7 +15,7 @@
15/* 15/*
16 * These are the virtual IRQ numbers, we divide all IRQ's into 16 * These are the virtual IRQ numbers, we divide all IRQ's into
17 * 'spaces', the 'space' determines where and how to enable/disable 17 * 'spaces', the 'space' determines where and how to enable/disable
18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups 18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
19 * are not supported this way. Driver is supposed to allocate HPC/MC 19 * are not supported this way. Driver is supposed to allocate HPC/MC
20 * interrupt as shareable and then look to proper status bit (see 20 * interrupt as shareable and then look to proper status bit (see
21 * HAL2 driver). This will prevent many complications, trust me ;-) 21 * HAL2 driver). This will prevent many complications, trust me ;-)
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
index ef91b3363554..0187895e556c 100644
--- a/include/asm-mips/sn/sn0/hubio.h
+++ b/include/asm-mips/sn/sn0/hubio.h
@@ -338,7 +338,7 @@ typedef union io_perf_cnt {
338#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ 338#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
339#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ 339#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
340#define IIO_IMMR IIO_IIAP 340#define IIO_IMMR IIO_IIAP
341#define IIO_ICMR 0x4003a8 /* CRB Managment Register */ 341#define IIO_ICMR 0x4003a8 /* CRB Management Register */
342#define IIO_ICCR 0x4003b0 /* CRB Control Register */ 342#define IIO_ICCR 0x4003b0 /* CRB Control Register */
343#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ 343#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
344#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ 344#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */