aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h9
-rw-r--r--drivers/spi/pxa2xx_spi.c14
2 files changed, 8 insertions, 15 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index 6a2ed35acd59..dd15dc35a240 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -33,14 +33,7 @@
33#define SSCR0_National (0x2 << 4) /* National Microwire */ 33#define SSCR0_National (0x2 << 4) /* National Microwire */
34#define SSCR0_ECS (1 << 6) /* External clock select */ 34#define SSCR0_ECS (1 << 6) /* External clock select */
35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36 36#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
42#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
43#endif
44 37
45#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 38#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
46#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 39#define SSCR0_EDSS (1 << 20) /* Extended data size select */
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 36828358a4d8..35d4e5cdb631 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -1318,14 +1318,14 @@ static int setup(struct spi_device *spi)
1318 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1318 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1319 if (drv_data->ssp_type != PXA25x_SSP) 1319 if (drv_data->ssp_type != PXA25x_SSP)
1320 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1320 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1321 clk_get_rate(ssp->clk) 1321 clk_get_rate(ssp->clk)
1322 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1322 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1323 chip->enable_dma ? "DMA" : "PIO"); 1323 chip->enable_dma ? "DMA" : "PIO");
1324 else 1324 else
1325 dev_dbg(&spi->dev, "%ld Hz actual, %s\n", 1325 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1326 clk_get_rate(ssp->clk) / 2 1326 clk_get_rate(ssp->clk) / 2
1327 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), 1327 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1328 chip->enable_dma ? "DMA" : "PIO"); 1328 chip->enable_dma ? "DMA" : "PIO");
1329 1329
1330 if (spi->bits_per_word <= 8) { 1330 if (spi->bits_per_word <= 8) {
1331 chip->n_bytes = 1; 1331 chip->n_bytes = 1;
@@ -1558,7 +1558,7 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1558 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | 1558 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1559 SSCR1_TxTresh(TX_THRESH_DFLT), 1559 SSCR1_TxTresh(TX_THRESH_DFLT),
1560 drv_data->ioaddr); 1560 drv_data->ioaddr);
1561 write_SSCR0(SSCR0_SerClkDiv(2) 1561 write_SSCR0(SSCR0_SCR(2)
1562 | SSCR0_Motorola 1562 | SSCR0_Motorola
1563 | SSCR0_DataSize(8), 1563 | SSCR0_DataSize(8),
1564 drv_data->ioaddr); 1564 drv_data->ioaddr);