diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 20eb66dbb3a4..ac7d93e2d5d5 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
| @@ -380,7 +380,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
| 380 | return -EINVAL; | 380 | return -EINVAL; |
| 381 | } | 381 | } |
| 382 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 382 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
| 383 | ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 383 | ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
| 384 | break; | 384 | break; |
| 385 | case PACKET3_DRAW_INDEX_AUTO: | 385 | case PACKET3_DRAW_INDEX_AUTO: |
| 386 | if (pkt->count != 1) { | 386 | if (pkt->count != 1) { |
| @@ -408,7 +408,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
| 408 | return -EINVAL; | 408 | return -EINVAL; |
| 409 | } | 409 | } |
| 410 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 410 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
| 411 | ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 411 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
| 412 | } | 412 | } |
| 413 | break; | 413 | break; |
| 414 | case PACKET3_SURFACE_SYNC: | 414 | case PACKET3_SURFACE_SYNC: |
| @@ -439,7 +439,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
| 439 | return -EINVAL; | 439 | return -EINVAL; |
| 440 | } | 440 | } |
| 441 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 441 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
| 442 | ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 442 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
| 443 | } | 443 | } |
| 444 | break; | 444 | break; |
| 445 | case PACKET3_EVENT_WRITE_EOP: | 445 | case PACKET3_EVENT_WRITE_EOP: |
| @@ -453,7 +453,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
| 453 | return -EINVAL; | 453 | return -EINVAL; |
| 454 | } | 454 | } |
| 455 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 455 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
| 456 | ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 456 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
| 457 | break; | 457 | break; |
| 458 | case PACKET3_SET_CONFIG_REG: | 458 | case PACKET3_SET_CONFIG_REG: |
| 459 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; | 459 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; |
| @@ -575,7 +575,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
| 575 | return -EINVAL; | 575 | return -EINVAL; |
| 576 | } | 576 | } |
| 577 | ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); | 577 | ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); |
| 578 | ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 578 | ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
| 579 | break; | 579 | break; |
| 580 | case SQ_TEX_VTX_INVALID_TEXTURE: | 580 | case SQ_TEX_VTX_INVALID_TEXTURE: |
| 581 | case SQ_TEX_VTX_INVALID_BUFFER: | 581 | case SQ_TEX_VTX_INVALID_BUFFER: |