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-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clockdomain.c3
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
3 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 456e2ad5f621..f2a92d614f0f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1043,5 +1043,7 @@ void omap2_clk_disable_unused(struct clk *clk)
1043 omap2_clk_disable(clk); 1043 omap2_clk_disable(clk);
1044 } else 1044 } else
1045 _omap2_clk_disable(clk); 1045 _omap2_clk_disable(clk);
1046 if (clk->clkdm != NULL)
1047 pwrdm_clkdm_state_switch(clk->clkdm);
1046} 1048}
1047#endif 1049#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 26912a95dc18..5b0b90b76e13 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -574,6 +574,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
574 omap2_clkdm_wakeup(clkdm); 574 omap2_clkdm_wakeup(clkdm);
575 575
576 pwrdm_wait_transition(clkdm->pwrdm.ptr); 576 pwrdm_wait_transition(clkdm->pwrdm.ptr);
577 pwrdm_clkdm_state_switch(clkdm);
577 578
578 return 0; 579 return 0;
579} 580}
@@ -626,6 +627,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
626 else 627 else
627 omap2_clkdm_sleep(clkdm); 628 omap2_clkdm_sleep(clkdm);
628 629
630 pwrdm_clkdm_state_switch(clkdm);
631
629 return 0; 632 return 0;
630} 633}
631 634
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 488d595d8e4b..f1976242f997 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
170 printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 170 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
171 return; 171 return;
172 } 172 }
173 pwrdm_pre_transition();
174
173 omap2_gpio_prepare_for_retention(); 175 omap2_gpio_prepare_for_retention();
174 omap_uart_prepare_idle(0); 176 omap_uart_prepare_idle(0);
175 omap_uart_prepare_idle(1); 177 omap_uart_prepare_idle(1);
@@ -182,6 +184,9 @@ static void omap_sram_idle(void)
182 omap_uart_resume_idle(1); 184 omap_uart_resume_idle(1);
183 omap_uart_resume_idle(0); 185 omap_uart_resume_idle(0);
184 omap2_gpio_resume_after_retention(); 186 omap2_gpio_resume_after_retention();
187
188 pwrdm_post_transition();
189
185} 190}
186 191
187/* 192/*
@@ -271,6 +276,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
271 if (sleep_switch) { 276 if (sleep_switch) {
272 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); 277 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
273 pwrdm_wait_transition(pwrdm); 278 pwrdm_wait_transition(pwrdm);
279 pwrdm_state_switch(pwrdm);
274 } 280 }
275 281
276err: 282err: