diff options
63 files changed, 3 insertions, 1233 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 43ab119963d5..8fa7a384f250 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt | |||
@@ -212,7 +212,7 @@ Who: Greg Kroah-Hartman <gregkh@suse.de> | |||
212 | 212 | ||
213 | --------------------------- | 213 | --------------------------- |
214 | 214 | ||
215 | What: Support for NEC DDB5074 and DDB5476 evaluation boards. | 215 | What: Support for NEC DDB5476 evaluation boards. |
216 | When: June 2006 | 216 | When: June 2006 |
217 | Why: Board specific code doesn't build anymore since ~2.6.0 and no | 217 | Why: Board specific code doesn't build anymore since ~2.6.0 and no |
218 | users have complained indicating there is no more need for these | 218 | users have complained indicating there is no more need for these |
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ae33e0a4c18d..c3c8e7a15af3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -469,24 +469,6 @@ config PNX8550_JBS | |||
469 | select PNX8550 | 469 | select PNX8550 |
470 | select SYS_SUPPORTS_LITTLE_ENDIAN | 470 | select SYS_SUPPORTS_LITTLE_ENDIAN |
471 | 471 | ||
472 | config DDB5074 | ||
473 | bool "NEC DDB Vrc-5074 (EXPERIMENTAL)" | ||
474 | depends on EXPERIMENTAL | ||
475 | select DDB5XXX_COMMON | ||
476 | select DMA_NONCOHERENT | ||
477 | select HAVE_STD_PC_SERIAL_PORT | ||
478 | select HW_HAS_PCI | ||
479 | select IRQ_CPU | ||
480 | select I8259 | ||
481 | select ISA | ||
482 | select SYS_HAS_CPU_R5000 | ||
483 | select SYS_SUPPORTS_32BIT_KERNEL | ||
484 | select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL | ||
485 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
486 | help | ||
487 | This enables support for the VR5000-based NEC DDB Vrc-5074 | ||
488 | evaluation board. | ||
489 | |||
490 | config DDB5476 | 472 | config DDB5476 |
491 | bool "NEC DDB Vrc-5476" | 473 | bool "NEC DDB Vrc-5476" |
492 | select DDB5XXX_COMMON | 474 | select DDB5XXX_COMMON |
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 24a901cf5a45..8d1026cd0738 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
@@ -404,12 +404,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000 | |||
404 | core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ | 404 | core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ |
405 | 405 | ||
406 | # | 406 | # |
407 | # NEC DDB Vrc-5074 | ||
408 | # | ||
409 | core-$(CONFIG_DDB5074) += arch/mips/ddb5xxx/ddb5074/ | ||
410 | load-$(CONFIG_DDB5074) += 0xffffffff80080000 | ||
411 | |||
412 | # | ||
413 | # NEC DDB Vrc-5476 | 407 | # NEC DDB Vrc-5476 |
414 | # | 408 | # |
415 | core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/ | 409 | core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/ |
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 4b080bcb258f..7b6de36e5b74 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_ATLAS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index d85cda58d650..633cafe20418 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index ca0af1683a00..bd150ec8559f 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 7d269e609282..ad83025420ec 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_COBALT=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 579b665e3339..ba3c7b9464bf 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1000=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index e5eb53867422..321a4d00ce94 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1100=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index a43fb2329fd5..97471008f3ae 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1200=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index ad632d87c4ef..fbcc1738ff90 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1500=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 8130e23dc255..d014cdd3e705 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1550=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig index 8d88ac1bbfeb..90cabf5419ad 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/ddb5476_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | CONFIG_DDB5476=y | 44 | CONFIG_DDB5476=y |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 8c911b671415..fc30ace3d737 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | CONFIG_DDB5477=y | 45 | CONFIG_DDB5477=y |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index d838496e114f..0775d7364cab 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MACH_DECSTATION=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 0760f4318910..8f9de1c3bf1e 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 7067f608b22c..b97c90fa5491 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_EV64120=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 00b56ed0e638..708b0d6896d8 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_EV96100=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 607e2985ffe3..f7b0beb5752f 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 87d27cd3d2cf..b4ae9cd15ba3 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 8f11d3565b2d..a95c2e847f68 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 757adf23853d..87c5cde49e59 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_ITE8172=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index 021761a8a237..1346b683b287 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_IVR=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 08f6c30b0abc..d2d1a7776362 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 38b1e026e10d..ba23db03ba95 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 4d25990a0a05..7500332c9b5c 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_LASAT=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 977f52be51dc..1aac4901c57e 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_MALTA=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 00560e0143f1..011120c5033e 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_SIM=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 286a018375b2..ca0baa29483c 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index 1ce4310fd92a..a8d26596ca8e 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_3=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index 8a6aa5012f89..a1d6d7ff93fb 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_C=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index f9ee35eeb762..4b72b0a2fb4b 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index b48bdee2411f..232f13a41938 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_G=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 01aac40634b4..55da4eb76f7b 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1100=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 398c3c265b9f..348581d91b52 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1500=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index ea282a53bb66..897f76c0c8ab 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1550=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 4c57e564db0b..6289dfa73f2f 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | CONFIG_PNX8550_JBS=y | 43 | CONFIG_PNX8550_JBS=y |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig index 3c8f35162fec..d8448fdb2514 100644 --- a/arch/mips/configs/pnx8550-v2pci_defconfig +++ b/arch/mips/configs/pnx8550-v2pci_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | CONFIG_PNX8550_V2PCI=y | 42 | CONFIG_PNX8550_V2PCI=y |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index 4bcc01dea041..99c43c9f1595 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 3d441932e43a..c55e8e6ff207 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index edfb9679a25a..6013c6533ca5 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index e388a3dae0a9..6b8441e18843 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 6b8a6a416a25..94d04f7a5e6b 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS_SEAD=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index dba0bdcdcf29..f84864d8ec33 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index 5a924c1a5803..aeb1e85f9ce7 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 9f215ea350dc..5f1ee08d9851 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index ac7765eb8da7..ebc25edbf73d 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | CONFIG_MACH_VR41XX=y | 46 | CONFIG_MACH_VR41XX=y |
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index 1997b7c11ab4..03c880792163 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig | |||
@@ -42,7 +42,6 @@ CONFIG_WR_PPMC=y | |||
42 | # CONFIG_MIPS_XXS1500 is not set | 42 | # CONFIG_MIPS_XXS1500 is not set |
43 | # CONFIG_PNX8550_V2PCI is not set | 43 | # CONFIG_PNX8550_V2PCI is not set |
44 | # CONFIG_PNX8550_JBS is not set | 44 | # CONFIG_PNX8550_JBS is not set |
45 | # CONFIG_DDB5074 is not set | ||
46 | # CONFIG_DDB5476 is not set | 45 | # CONFIG_DDB5476 is not set |
47 | # CONFIG_DDB5477 is not set | 46 | # CONFIG_DDB5477 is not set |
48 | # CONFIG_MACH_VR41XX is not set | 47 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index b52d709de962..1c728f216fbd 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c index b8d1f7489f3b..18eecbcdfca8 100644 --- a/arch/mips/ddb5xxx/common/prom.c +++ b/arch/mips/ddb5xxx/common/prom.c | |||
@@ -56,10 +56,7 @@ void __init prom_init(void) | |||
56 | 56 | ||
57 | mips_machgroup = MACH_GROUP_NEC_DDB; | 57 | mips_machgroup = MACH_GROUP_NEC_DDB; |
58 | 58 | ||
59 | #if defined(CONFIG_DDB5074) | 59 | #if defined(CONFIG_DDB5476) |
60 | mips_machtype = MACH_NEC_DDB5074; | ||
61 | add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); | ||
62 | #elif defined(CONFIG_DDB5476) | ||
63 | mips_machtype = MACH_NEC_DDB5476; | 60 | mips_machtype = MACH_NEC_DDB5476; |
64 | add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); | 61 | add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); |
65 | #elif defined(CONFIG_DDB5477) | 62 | #elif defined(CONFIG_DDB5477) |
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile deleted file mode 100644 index 304c02107b46..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/Makefile +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the NEC DDB Vrc-5074 specific kernel interface routines | ||
3 | # under Linux. | ||
4 | # | ||
5 | |||
6 | obj-y += setup.o irq.o nile4_pic.o | ||
7 | |||
8 | EXTRA_AFLAGS := $(CFLAGS) | ||
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c deleted file mode 100644 index 60c087b7738c..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/irq.c +++ /dev/null | |||
@@ -1,169 +0,0 @@ | |||
1 | /* | ||
2 | * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | */ | ||
7 | #include <linux/init.h> | ||
8 | #include <linux/irq.h> | ||
9 | #include <linux/signal.h> | ||
10 | #include <linux/sched.h> | ||
11 | #include <linux/types.h> | ||
12 | #include <linux/interrupt.h> | ||
13 | #include <linux/ioport.h> | ||
14 | |||
15 | #include <asm/i8259.h> | ||
16 | #include <asm/io.h> | ||
17 | #include <asm/irq_cpu.h> | ||
18 | #include <asm/ptrace.h> | ||
19 | #include <asm/nile4.h> | ||
20 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
21 | #include <asm/ddb5xxx/ddb5074.h> | ||
22 | |||
23 | |||
24 | static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; | ||
25 | |||
26 | #define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ | ||
27 | #define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ | ||
28 | #define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ | ||
29 | |||
30 | #define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ | ||
31 | #define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ | ||
32 | #define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ | ||
33 | |||
34 | #define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ | ||
35 | #define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ | ||
36 | |||
37 | #define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ | ||
38 | #define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ | ||
39 | |||
40 | #define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ | ||
41 | #define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ | ||
42 | |||
43 | |||
44 | static void m1543_irq_setup(void) | ||
45 | { | ||
46 | /* | ||
47 | * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all | ||
48 | * the possible IO sources in the M1543 are in use by us. We will | ||
49 | * use the following mapping: | ||
50 | * | ||
51 | * IRQ1 - keyboard (default set by M1543) | ||
52 | * IRQ3 - reserved for UART B (default set by M1543) (note that | ||
53 | * the schematics for the DDB Vrc-5074 board seem to | ||
54 | * indicate that IRQ3 is connected to the DS1386 | ||
55 | * watchdog timer interrupt output so we might have | ||
56 | * a conflict) | ||
57 | * IRQ4 - reserved for UART A (default set by M1543) | ||
58 | * IRQ5 - parallel (default set by M1543) | ||
59 | * IRQ8 - DS1386 time of day (RTC) interrupt | ||
60 | * IRQ12 - mouse | ||
61 | */ | ||
62 | |||
63 | /* | ||
64 | * Assing mouse interrupt to IRQ12 | ||
65 | */ | ||
66 | |||
67 | /* Enter configuration mode */ | ||
68 | outb(0x51, M1543_PNP_CONFIG); | ||
69 | outb(0x23, M1543_PNP_CONFIG); | ||
70 | |||
71 | /* Select logical device 7 (Keyboard) */ | ||
72 | outb(0x07, M1543_PNP_INDEX); | ||
73 | outb(0x07, M1543_PNP_DATA); | ||
74 | |||
75 | /* Select IRQ12 */ | ||
76 | outb(0x72, M1543_PNP_INDEX); | ||
77 | outb(0x0c, M1543_PNP_DATA); | ||
78 | |||
79 | outb(0x30, M1543_PNP_INDEX); | ||
80 | printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA)); | ||
81 | |||
82 | outb(0x70, M1543_PNP_INDEX); | ||
83 | printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA)); | ||
84 | |||
85 | /* Leave configration mode */ | ||
86 | outb(0xbb, M1543_PNP_CONFIG); | ||
87 | |||
88 | |||
89 | } | ||
90 | |||
91 | static void ddb_local0_irqdispatch(struct pt_regs *regs) | ||
92 | { | ||
93 | u32 mask; | ||
94 | int nile4_irq; | ||
95 | |||
96 | mask = nile4_get_irq_stat(0); | ||
97 | |||
98 | /* Handle the timer interrupt first */ | ||
99 | #if 0 | ||
100 | if (mask & (1 << NILE4_INT_GPT)) { | ||
101 | do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs); | ||
102 | mask &= ~(1 << NILE4_INT_GPT); | ||
103 | } | ||
104 | #endif | ||
105 | for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) | ||
106 | if (mask & 1) { | ||
107 | if (nile4_irq == NILE4_INT_INTE) { | ||
108 | int i8259_irq; | ||
109 | |||
110 | nile4_clear_irq(NILE4_INT_INTE); | ||
111 | i8259_irq = nile4_i8259_iack(); | ||
112 | do_IRQ(i8259_irq, regs); | ||
113 | } else | ||
114 | do_IRQ(nile4_to_irq(nile4_irq), regs); | ||
115 | |||
116 | } | ||
117 | } | ||
118 | |||
119 | static void ddb_local1_irqdispatch(void) | ||
120 | { | ||
121 | printk("ddb_local1_irqdispatch called\n"); | ||
122 | } | ||
123 | |||
124 | static void ddb_buserror_irq(void) | ||
125 | { | ||
126 | printk("ddb_buserror_irq called\n"); | ||
127 | } | ||
128 | |||
129 | static void ddb_8254timer_irq(void) | ||
130 | { | ||
131 | printk("ddb_8254timer_irq called\n"); | ||
132 | } | ||
133 | |||
134 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | ||
135 | { | ||
136 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
137 | |||
138 | if (pending & CAUSEF_IP2) | ||
139 | ddb_local0_irqdispatch(regs); | ||
140 | else if (pending & CAUSEF_IP3) | ||
141 | ddb_local1_irqdispatch(); | ||
142 | else if (pending & CAUSEF_IP6) | ||
143 | ddb_buserror_irq(); | ||
144 | else if (pending & (CAUSEF_IP4 | CAUSEF_IP5)) | ||
145 | ddb_8254timer_irq(); | ||
146 | } | ||
147 | |||
148 | void __init arch_init_irq(void) | ||
149 | { | ||
150 | /* setup cascade interrupts */ | ||
151 | setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); | ||
152 | setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); | ||
153 | |||
154 | nile4_irq_setup(NILE4_IRQ_BASE); | ||
155 | m1543_irq_setup(); | ||
156 | init_i8259_irqs(); | ||
157 | |||
158 | |||
159 | printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE); | ||
160 | |||
161 | mips_cpu_irq_init(CPU_IRQ_BASE); | ||
162 | |||
163 | printk("enabling 8259 cascade\n"); | ||
164 | |||
165 | ddb5074_led_hex(0); | ||
166 | |||
167 | /* Enable the interrupt cascade */ | ||
168 | nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE); | ||
169 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c deleted file mode 100644 index 8743ffce8653..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c +++ /dev/null | |||
@@ -1,286 +0,0 @@ | |||
1 | /* | ||
2 | * arch/mips/ddb5476/nile4.c -- | ||
3 | * low-level PIC code for NEC Vrc-5476 (Nile 4) | ||
4 | * | ||
5 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
6 | * Sony Software Development Center Europe (SDCE), Brussels | ||
7 | * | ||
8 | * Copyright 2001 MontaVista Software Inc. | ||
9 | * Author: jsun@mvista.com or jsun@junsun.net | ||
10 | * | ||
11 | */ | ||
12 | #include <linux/config.h> | ||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/ioport.h> | ||
17 | |||
18 | #include <asm/addrspace.h> | ||
19 | |||
20 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
21 | |||
22 | static int irq_base; | ||
23 | |||
24 | /* | ||
25 | * Interrupt Programming | ||
26 | */ | ||
27 | void nile4_map_irq(int nile4_irq, int cpu_irq) | ||
28 | { | ||
29 | u32 offset, t; | ||
30 | |||
31 | offset = DDB_INTCTRL; | ||
32 | if (nile4_irq >= 8) { | ||
33 | offset += 4; | ||
34 | nile4_irq -= 8; | ||
35 | } | ||
36 | t = ddb_in32(offset); | ||
37 | t &= ~(7 << (nile4_irq * 4)); | ||
38 | t |= cpu_irq << (nile4_irq * 4); | ||
39 | ddb_out32(offset, t); | ||
40 | } | ||
41 | |||
42 | void nile4_map_irq_all(int cpu_irq) | ||
43 | { | ||
44 | u32 all, t; | ||
45 | |||
46 | all = cpu_irq; | ||
47 | all |= all << 4; | ||
48 | all |= all << 8; | ||
49 | all |= all << 16; | ||
50 | t = ddb_in32(DDB_INTCTRL); | ||
51 | t &= 0x88888888; | ||
52 | t |= all; | ||
53 | ddb_out32(DDB_INTCTRL, t); | ||
54 | t = ddb_in32(DDB_INTCTRL + 4); | ||
55 | t &= 0x88888888; | ||
56 | t |= all; | ||
57 | ddb_out32(DDB_INTCTRL + 4, t); | ||
58 | } | ||
59 | |||
60 | void nile4_enable_irq(unsigned int nile4_irq) | ||
61 | { | ||
62 | u32 offset, t; | ||
63 | |||
64 | nile4_irq-=irq_base; | ||
65 | |||
66 | ddb5074_led_hex(8); | ||
67 | |||
68 | offset = DDB_INTCTRL; | ||
69 | if (nile4_irq >= 8) { | ||
70 | offset += 4; | ||
71 | nile4_irq -= 8; | ||
72 | } | ||
73 | ddb5074_led_hex(9); | ||
74 | t = ddb_in32(offset); | ||
75 | ddb5074_led_hex(0xa); | ||
76 | t |= 8 << (nile4_irq * 4); | ||
77 | ddb_out32(offset, t); | ||
78 | ddb5074_led_hex(0xb); | ||
79 | } | ||
80 | |||
81 | void nile4_disable_irq(unsigned int nile4_irq) | ||
82 | { | ||
83 | u32 offset, t; | ||
84 | |||
85 | nile4_irq-=irq_base; | ||
86 | |||
87 | offset = DDB_INTCTRL; | ||
88 | if (nile4_irq >= 8) { | ||
89 | offset += 4; | ||
90 | nile4_irq -= 8; | ||
91 | } | ||
92 | t = ddb_in32(offset); | ||
93 | t &= ~(8 << (nile4_irq * 4)); | ||
94 | ddb_out32(offset, t); | ||
95 | } | ||
96 | |||
97 | void nile4_disable_irq_all(void) | ||
98 | { | ||
99 | ddb_out32(DDB_INTCTRL, 0); | ||
100 | ddb_out32(DDB_INTCTRL + 4, 0); | ||
101 | } | ||
102 | |||
103 | u16 nile4_get_irq_stat(int cpu_irq) | ||
104 | { | ||
105 | return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); | ||
106 | } | ||
107 | |||
108 | void nile4_enable_irq_output(int cpu_irq) | ||
109 | { | ||
110 | u32 t; | ||
111 | |||
112 | t = ddb_in32(DDB_INTSTAT1 + 4); | ||
113 | t |= 1 << (16 + cpu_irq); | ||
114 | ddb_out32(DDB_INTSTAT1, t); | ||
115 | } | ||
116 | |||
117 | void nile4_disable_irq_output(int cpu_irq) | ||
118 | { | ||
119 | u32 t; | ||
120 | |||
121 | t = ddb_in32(DDB_INTSTAT1 + 4); | ||
122 | t &= ~(1 << (16 + cpu_irq)); | ||
123 | ddb_out32(DDB_INTSTAT1, t); | ||
124 | } | ||
125 | |||
126 | void nile4_set_pci_irq_polarity(int pci_irq, int high) | ||
127 | { | ||
128 | u32 t; | ||
129 | |||
130 | t = ddb_in32(DDB_INTPPES); | ||
131 | if (high) | ||
132 | t &= ~(1 << (pci_irq * 2)); | ||
133 | else | ||
134 | t |= 1 << (pci_irq * 2); | ||
135 | ddb_out32(DDB_INTPPES, t); | ||
136 | } | ||
137 | |||
138 | void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) | ||
139 | { | ||
140 | u32 t; | ||
141 | |||
142 | t = ddb_in32(DDB_INTPPES); | ||
143 | if (level) | ||
144 | t |= 2 << (pci_irq * 2); | ||
145 | else | ||
146 | t &= ~(2 << (pci_irq * 2)); | ||
147 | ddb_out32(DDB_INTPPES, t); | ||
148 | } | ||
149 | |||
150 | void nile4_clear_irq(int nile4_irq) | ||
151 | { | ||
152 | nile4_irq-=irq_base; | ||
153 | ddb_out32(DDB_INTCLR, 1 << nile4_irq); | ||
154 | } | ||
155 | |||
156 | void nile4_clear_irq_mask(u32 mask) | ||
157 | { | ||
158 | ddb_out32(DDB_INTCLR, mask); | ||
159 | } | ||
160 | |||
161 | u8 nile4_i8259_iack(void) | ||
162 | { | ||
163 | u8 irq; | ||
164 | u32 reg; | ||
165 | |||
166 | /* Set window 0 for interrupt acknowledge */ | ||
167 | reg = ddb_in32(DDB_PCIINIT0); | ||
168 | |||
169 | ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); | ||
170 | irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); | ||
171 | /* restore window 0 for PCI I/O space */ | ||
172 | // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); | ||
173 | ddb_out32(DDB_PCIINIT0, reg); | ||
174 | |||
175 | /* i8269.c set the base vector to be 0x0 */ | ||
176 | return irq ; | ||
177 | } | ||
178 | |||
179 | static unsigned int nile4_irq_startup(unsigned int irq) { | ||
180 | |||
181 | nile4_enable_irq(irq); | ||
182 | return 0; | ||
183 | |||
184 | } | ||
185 | |||
186 | static void nile4_ack_irq(unsigned int irq) { | ||
187 | |||
188 | ddb5074_led_hex(4); | ||
189 | |||
190 | nile4_clear_irq(irq); | ||
191 | ddb5074_led_hex(2); | ||
192 | nile4_disable_irq(irq); | ||
193 | |||
194 | ddb5074_led_hex(0); | ||
195 | } | ||
196 | |||
197 | static void nile4_irq_end(unsigned int irq) { | ||
198 | |||
199 | ddb5074_led_hex(3); | ||
200 | if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { | ||
201 | ddb5074_led_hex(5); | ||
202 | nile4_enable_irq(irq); | ||
203 | ddb5074_led_hex(7); | ||
204 | } | ||
205 | |||
206 | ddb5074_led_hex(1); | ||
207 | } | ||
208 | |||
209 | #define nile4_irq_shutdown nile4_disable_irq | ||
210 | |||
211 | static hw_irq_controller nile4_irq_controller = { | ||
212 | .typename = "nile4", | ||
213 | .startup = nile4_irq_startup, | ||
214 | .shutdown = nile4_irq_shutdown, | ||
215 | .enable = nile4_enable_irq, | ||
216 | .disable = nile4_disable_irq, | ||
217 | .ack = nile4_ack_irq, | ||
218 | .end = nile4_irq_end, | ||
219 | }; | ||
220 | |||
221 | void nile4_irq_setup(u32 base) { | ||
222 | |||
223 | int i; | ||
224 | |||
225 | irq_base=base; | ||
226 | |||
227 | /* Map all interrupts to CPU int #0 */ | ||
228 | nile4_map_irq_all(0); | ||
229 | |||
230 | /* PCI INTA#-E# must be level triggered */ | ||
231 | nile4_set_pci_irq_level_or_edge(0, 1); | ||
232 | nile4_set_pci_irq_level_or_edge(1, 1); | ||
233 | nile4_set_pci_irq_level_or_edge(2, 1); | ||
234 | nile4_set_pci_irq_level_or_edge(3, 1); | ||
235 | nile4_set_pci_irq_level_or_edge(4, 1); | ||
236 | |||
237 | /* PCI INTA#-D# must be active low, INTE# must be active high */ | ||
238 | nile4_set_pci_irq_polarity(0, 0); | ||
239 | nile4_set_pci_irq_polarity(1, 0); | ||
240 | nile4_set_pci_irq_polarity(2, 0); | ||
241 | nile4_set_pci_irq_polarity(3, 0); | ||
242 | nile4_set_pci_irq_polarity(4, 1); | ||
243 | |||
244 | |||
245 | for (i = 0; i < 16; i++) { | ||
246 | nile4_clear_irq(i); | ||
247 | nile4_disable_irq(i); | ||
248 | } | ||
249 | |||
250 | /* Enable CPU int #0 */ | ||
251 | nile4_enable_irq_output(0); | ||
252 | |||
253 | for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) { | ||
254 | irq_desc[i].status = IRQ_DISABLED; | ||
255 | irq_desc[i].action = NULL; | ||
256 | irq_desc[i].depth = 1; | ||
257 | irq_desc[i].handler = &nile4_irq_controller; | ||
258 | } | ||
259 | } | ||
260 | |||
261 | #if defined(CONFIG_RUNTIME_DEBUG) | ||
262 | void nile4_dump_irq_status(void) | ||
263 | { | ||
264 | printk(KERN_DEBUG " | ||
265 | CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), | ||
266 | (void *) ddb_in32(DDB_CPUSTAT)); | ||
267 | printk(KERN_DEBUG " | ||
268 | INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), | ||
269 | (void *) ddb_in32(DDB_INTCTRL)); | ||
270 | printk(KERN_DEBUG | ||
271 | "INTSTAT0 = %p:%p\n", | ||
272 | (void *) ddb_in32(DDB_INTSTAT0 + 4), | ||
273 | (void *) ddb_in32(DDB_INTSTAT0)); | ||
274 | printk(KERN_DEBUG | ||
275 | "INTSTAT1 = %p:%p\n", | ||
276 | (void *) ddb_in32(DDB_INTSTAT1 + 4), | ||
277 | (void *) ddb_in32(DDB_INTSTAT1)); | ||
278 | printk(KERN_DEBUG | ||
279 | "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), | ||
280 | (void *) ddb_in32(DDB_INTCLR)); | ||
281 | printk(KERN_DEBUG | ||
282 | "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), | ||
283 | (void *) ddb_in32(DDB_INTPPES)); | ||
284 | } | ||
285 | |||
286 | #endif | ||
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c deleted file mode 100644 index 4882ad1052e7..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/setup.c +++ /dev/null | |||
@@ -1,234 +0,0 @@ | |||
1 | /* | ||
2 | * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | */ | ||
7 | #include <linux/init.h> | ||
8 | #include <linux/kbd_ll.h> | ||
9 | #include <linux/kernel.h> | ||
10 | #include <linux/kdev_t.h> | ||
11 | #include <linux/types.h> | ||
12 | #include <linux/sched.h> | ||
13 | #include <linux/pci.h> | ||
14 | #include <linux/ide.h> | ||
15 | #include <linux/ioport.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/pm.h> | ||
18 | |||
19 | #include <asm/addrspace.h> | ||
20 | #include <asm/bcache.h> | ||
21 | #include <asm/irq.h> | ||
22 | #include <asm/reboot.h> | ||
23 | #include <asm/gdb-stub.h> | ||
24 | #include <asm/time.h> | ||
25 | #include <asm/nile4.h> | ||
26 | #include <asm/ddb5xxx/ddb5074.h> | ||
27 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
28 | |||
29 | static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; | ||
30 | |||
31 | static void ddb_machine_restart(char *command) | ||
32 | { | ||
33 | u32 t; | ||
34 | |||
35 | /* PCI cold reset */ | ||
36 | t = nile4_in32(NILE4_PCICTRL + 4); | ||
37 | t |= 0x40000000; | ||
38 | nile4_out32(NILE4_PCICTRL + 4, t); | ||
39 | /* CPU cold reset */ | ||
40 | t = nile4_in32(NILE4_CPUSTAT); | ||
41 | t |= 1; | ||
42 | nile4_out32(NILE4_CPUSTAT, t); | ||
43 | /* Call the PROM */ | ||
44 | back_to_prom(); | ||
45 | } | ||
46 | |||
47 | static void ddb_machine_halt(void) | ||
48 | { | ||
49 | printk("DDB Vrc-5074 halted.\n"); | ||
50 | do { | ||
51 | } while (1); | ||
52 | } | ||
53 | |||
54 | static void ddb_machine_power_off(void) | ||
55 | { | ||
56 | printk("DDB Vrc-5074 halted. Please turn off the power.\n"); | ||
57 | do { | ||
58 | } while (1); | ||
59 | } | ||
60 | |||
61 | extern void rtc_ds1386_init(unsigned long base); | ||
62 | |||
63 | extern void (*board_timer_setup) (struct irqaction * irq); | ||
64 | |||
65 | static void __init ddb_timer_init(struct irqaction *irq) | ||
66 | { | ||
67 | /* set the clock to 1 Hz */ | ||
68 | nile4_out32(NILE4_T2CTRL, 1000000); | ||
69 | /* enable the General-Purpose Timer */ | ||
70 | nile4_out32(NILE4_T2CTRL + 4, 0x00000001); | ||
71 | /* reset timer */ | ||
72 | nile4_out32(NILE4_T2CNTR, 0); | ||
73 | /* enable interrupt */ | ||
74 | setup_irq(nile4_to_irq(NILE4_INT_GPT), irq); | ||
75 | nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT)); | ||
76 | change_c0_status(ST0_IM, | ||
77 | IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); | ||
78 | |||
79 | } | ||
80 | |||
81 | static void __init ddb_time_init(void) | ||
82 | { | ||
83 | /* we have ds1396 RTC chip */ | ||
84 | rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); | ||
85 | } | ||
86 | |||
87 | |||
88 | |||
89 | void __init plat_mem_setup(void) | ||
90 | { | ||
91 | set_io_port_base(NILE4_PCI_IO_BASE); | ||
92 | isa_slot_offset = NILE4_PCI_MEM_BASE; | ||
93 | board_timer_setup = ddb_timer_init; | ||
94 | board_time_init = ddb_time_init; | ||
95 | |||
96 | |||
97 | _machine_restart = ddb_machine_restart; | ||
98 | _machine_halt = ddb_machine_halt; | ||
99 | pm_power_off = ddb_machine_power_off; | ||
100 | |||
101 | ddb_out32(DDB_BAR0, 0); | ||
102 | |||
103 | ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10); | ||
104 | ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10); | ||
105 | |||
106 | /* Reboot on panic */ | ||
107 | panic_timeout = 180; | ||
108 | } | ||
109 | |||
110 | #define USE_NILE4_SERIAL 0 | ||
111 | |||
112 | #if USE_NILE4_SERIAL | ||
113 | #define ns16550_in(reg) nile4_in8((reg)*8) | ||
114 | #define ns16550_out(reg, val) nile4_out8((reg)*8, (val)) | ||
115 | #else | ||
116 | #define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8) | ||
117 | static inline u8 ns16550_in(u32 reg) | ||
118 | { | ||
119 | return *(volatile u8 *) (NS16550_BASE + reg); | ||
120 | } | ||
121 | |||
122 | static inline void ns16550_out(u32 reg, u8 val) | ||
123 | { | ||
124 | *(volatile u8 *) (NS16550_BASE + reg) = val; | ||
125 | } | ||
126 | #endif | ||
127 | |||
128 | #define NS16550_RBR 0 | ||
129 | #define NS16550_THR 0 | ||
130 | #define NS16550_DLL 0 | ||
131 | #define NS16550_IER 1 | ||
132 | #define NS16550_DLM 1 | ||
133 | #define NS16550_FCR 2 | ||
134 | #define NS16550_IIR 2 | ||
135 | #define NS16550_LCR 3 | ||
136 | #define NS16550_MCR 4 | ||
137 | #define NS16550_LSR 5 | ||
138 | #define NS16550_MSR 6 | ||
139 | #define NS16550_SCR 7 | ||
140 | |||
141 | #define NS16550_LSR_DR 0x01 /* Data ready */ | ||
142 | #define NS16550_LSR_OE 0x02 /* Overrun */ | ||
143 | #define NS16550_LSR_PE 0x04 /* Parity error */ | ||
144 | #define NS16550_LSR_FE 0x08 /* Framing error */ | ||
145 | #define NS16550_LSR_BI 0x10 /* Break */ | ||
146 | #define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */ | ||
147 | #define NS16550_LSR_TEMT 0x40 /* Xmitter empty */ | ||
148 | #define NS16550_LSR_ERR 0x80 /* Error */ | ||
149 | |||
150 | |||
151 | void _serinit(void) | ||
152 | { | ||
153 | #if USE_NILE4_SERIAL | ||
154 | ns16550_out(NS16550_LCR, 0x80); | ||
155 | ns16550_out(NS16550_DLM, 0x00); | ||
156 | ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */ | ||
157 | ns16550_out(NS16550_LCR, 0x00); | ||
158 | ns16550_out(NS16550_LCR, 0x03); | ||
159 | ns16550_out(NS16550_FCR, 0x47); | ||
160 | #else | ||
161 | /* done by PMON */ | ||
162 | #endif | ||
163 | } | ||
164 | |||
165 | void _putc(char c) | ||
166 | { | ||
167 | while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); | ||
168 | ns16550_out(NS16550_THR, c); | ||
169 | if (c == '\n') { | ||
170 | while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); | ||
171 | ns16550_out(NS16550_THR, '\r'); | ||
172 | } | ||
173 | } | ||
174 | |||
175 | void _puts(const char *s) | ||
176 | { | ||
177 | char c; | ||
178 | while ((c = *s++)) | ||
179 | _putc(c); | ||
180 | } | ||
181 | |||
182 | char _getc(void) | ||
183 | { | ||
184 | while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR)); | ||
185 | return ns16550_in(NS16550_RBR); | ||
186 | } | ||
187 | |||
188 | int _testc(void) | ||
189 | { | ||
190 | return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0; | ||
191 | } | ||
192 | |||
193 | |||
194 | /* | ||
195 | * Hexadecimal 7-segment LED | ||
196 | */ | ||
197 | void ddb5074_led_hex(int hex) | ||
198 | { | ||
199 | outb(hex, 0x80); | ||
200 | } | ||
201 | |||
202 | |||
203 | /* | ||
204 | * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543 | ||
205 | */ | ||
206 | struct pci_dev *pci_pmu = NULL; | ||
207 | |||
208 | void ddb5074_led_d2(int on) | ||
209 | { | ||
210 | u8 t; | ||
211 | |||
212 | if (pci_pmu) { | ||
213 | pci_read_config_byte(pci_pmu, 0x7e, &t); | ||
214 | if (on) | ||
215 | t &= 0x7f; | ||
216 | else | ||
217 | t |= 0x80; | ||
218 | pci_write_config_byte(pci_pmu, 0x7e, t); | ||
219 | } | ||
220 | } | ||
221 | |||
222 | void ddb5074_led_d3(int on) | ||
223 | { | ||
224 | u8 t; | ||
225 | |||
226 | if (pci_pmu) { | ||
227 | pci_read_config_byte(pci_pmu, 0x7e, &t); | ||
228 | if (on) | ||
229 | t &= 0xbf; | ||
230 | else | ||
231 | t |= 0x40; | ||
232 | pci_write_config_byte(pci_pmu, 0x7e, t); | ||
233 | } | ||
234 | } | ||
diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 607e2985ffe3..f7b0beb5752f 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig | |||
@@ -41,7 +41,6 @@ CONFIG_MIPS=y | |||
41 | # CONFIG_MIPS_XXS1500 is not set | 41 | # CONFIG_MIPS_XXS1500 is not set |
42 | # CONFIG_PNX8550_V2PCI is not set | 42 | # CONFIG_PNX8550_V2PCI is not set |
43 | # CONFIG_PNX8550_JBS is not set | 43 | # CONFIG_PNX8550_JBS is not set |
44 | # CONFIG_DDB5074 is not set | ||
45 | # CONFIG_DDB5476 is not set | 44 | # CONFIG_DDB5476 is not set |
46 | # CONFIG_DDB5477 is not set | 45 | # CONFIG_DDB5477 is not set |
47 | # CONFIG_MACH_VR41XX is not set | 46 | # CONFIG_MACH_VR41XX is not set |
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index bb6b6226a57a..d028197d8326 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile | |||
@@ -22,7 +22,6 @@ obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o | |||
22 | # | 22 | # |
23 | # These are still pretty much in the old state, watch, go blind. | 23 | # These are still pretty much in the old state, watch, go blind. |
24 | # | 24 | # |
25 | obj-$(CONFIG_DDB5074) += fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o | ||
26 | obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o | 25 | obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o |
27 | obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o | 26 | obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o |
28 | obj-$(CONFIG_LASAT) += pci-lasat.o | 27 | obj-$(CONFIG_LASAT) += pci-lasat.o |
diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c deleted file mode 100644 index 5a4a7c239c42..000000000000 --- a/arch/mips/pci/fixup-ddb5074.c +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * It's nice to have the LEDs on the GPIO pins available for debugging | ||
3 | */ | ||
4 | static void ddb5074_fixup(struct pci_dev *dev) | ||
5 | { | ||
6 | extern struct pci_dev *pci_pmu; | ||
7 | u8 t8; | ||
8 | |||
9 | pci_pmu = dev; /* for LEDs D2 and D3 */ | ||
10 | /* Program the lines for LEDs D2 and D3 to output */ | ||
11 | pci_read_config_byte(dev, 0x7d, &t8); | ||
12 | t8 |= 0xc0; | ||
13 | pci_write_config_byte(dev, 0x7d, t8); | ||
14 | /* Turn LEDs D2 and D3 off */ | ||
15 | pci_read_config_byte(dev, 0x7e, &t8); | ||
16 | t8 |= 0xc0; | ||
17 | pci_write_config_byte(dev, 0x7e, t8); | ||
18 | } | ||
19 | |||
20 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, | ||
21 | ddb5074_fixup); | ||
diff --git a/arch/mips/pci/ops-ddb5074.c b/arch/mips/pci/ops-ddb5074.c deleted file mode 100644 index 89f97bef4fc4..000000000000 --- a/arch/mips/pci/ops-ddb5074.c +++ /dev/null | |||
@@ -1,271 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2001 MontaVista Software Inc. | ||
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
4 | * | ||
5 | * arch/mips/ddb5xxx/ddb5476/pci_ops.c | ||
6 | * Define the pci_ops for DB5477. | ||
7 | * | ||
8 | * Much of the code is derived from the original DDB5074 port by | ||
9 | * Geert Uytterhoeven <geert@sonycom.com> | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify it | ||
12 | * under the terms of the GNU General Public License as published by the | ||
13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
14 | * option) any later version. | ||
15 | * | ||
16 | */ | ||
17 | #include <linux/pci.h> | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/types.h> | ||
20 | |||
21 | #include <asm/addrspace.h> | ||
22 | #include <asm/debug.h> | ||
23 | |||
24 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
25 | |||
26 | /* | ||
27 | * config_swap structure records what set of pdar/pmr are used | ||
28 | * to access pci config space. It also provides a place hold the | ||
29 | * original values for future restoring. | ||
30 | */ | ||
31 | struct pci_config_swap { | ||
32 | u32 pdar; | ||
33 | u32 pmr; | ||
34 | u32 config_base; | ||
35 | u32 config_size; | ||
36 | u32 pdar_backup; | ||
37 | u32 pmr_backup; | ||
38 | }; | ||
39 | |||
40 | /* | ||
41 | * On DDB5476, we have one set of swap registers | ||
42 | */ | ||
43 | struct pci_config_swap ext_pci_swap = { | ||
44 | DDB_PCIW0, | ||
45 | DDB_PCIINIT0, | ||
46 | DDB_PCI_CONFIG_BASE, | ||
47 | DDB_PCI_CONFIG_SIZE | ||
48 | }; | ||
49 | |||
50 | static int pci_config_workaround = 1; | ||
51 | |||
52 | /* | ||
53 | * access config space | ||
54 | */ | ||
55 | static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ | ||
56 | u32 slot_num) | ||
57 | { | ||
58 | u32 pci_addr = 0; | ||
59 | u32 pciinit_offset = 0; | ||
60 | u32 virt_addr = swap->config_base; | ||
61 | u32 option; | ||
62 | |||
63 | if (pci_config_workaround) { | ||
64 | if (slot_num == 5) | ||
65 | slot_num = 14; | ||
66 | } else { | ||
67 | if (slot_num == 5) | ||
68 | return DDB_BASE + DDB_PCI_BASE; | ||
69 | } | ||
70 | |||
71 | /* minimum pdar (window) size is 2MB */ | ||
72 | db_assert(swap->config_size >= (2 << 20)); | ||
73 | |||
74 | db_assert(slot_num < (1 << 5)); | ||
75 | db_assert(bus < (1 << 8)); | ||
76 | |||
77 | /* backup registers */ | ||
78 | swap->pdar_backup = ddb_in32(swap->pdar); | ||
79 | swap->pmr_backup = ddb_in32(swap->pmr); | ||
80 | |||
81 | /* set the pdar (pci window) register */ | ||
82 | ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ | ||
83 | 0, /* not on local memory bus */ | ||
84 | 0); /* not visible from PCI bus (N/A) */ | ||
85 | |||
86 | /* | ||
87 | * calcuate the absolute pci config addr; | ||
88 | * according to the spec, we start scanning from adr:11 (0x800) | ||
89 | */ | ||
90 | if (bus == 0) { | ||
91 | /* type 0 config */ | ||
92 | pci_addr = 0x00040000 << slot_num; | ||
93 | } else { | ||
94 | /* type 1 config */ | ||
95 | pci_addr = 0x00040000 << slot_num; | ||
96 | panic | ||
97 | ("ddb_access_config_base: we don't support type 1 config Yet"); | ||
98 | } | ||
99 | |||
100 | /* | ||
101 | * if pci_addr is less than pci config window size, we set | ||
102 | * pciinit_offset to 0 and adjust the virt_address. | ||
103 | * Otherwise we will try to adjust pciinit_offset. | ||
104 | */ | ||
105 | if (pci_addr < swap->config_size) { | ||
106 | virt_addr = KSEG1ADDR(swap->config_base + pci_addr); | ||
107 | pciinit_offset = 0; | ||
108 | } else { | ||
109 | db_assert((pci_addr & (swap->config_size - 1)) == 0); | ||
110 | virt_addr = KSEG1ADDR(swap->config_base); | ||
111 | pciinit_offset = pci_addr; | ||
112 | } | ||
113 | |||
114 | /* set the pmr register */ | ||
115 | option = DDB_PCI_ACCESS_32; | ||
116 | if (bus != 0) | ||
117 | option |= DDB_PCI_CFGTYPE1; | ||
118 | ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); | ||
119 | |||
120 | return virt_addr; | ||
121 | } | ||
122 | |||
123 | static inline void ddb_close_config_base(struct pci_config_swap *swap) | ||
124 | { | ||
125 | ddb_out32(swap->pdar, swap->pdar_backup); | ||
126 | ddb_out32(swap->pmr, swap->pmr_backup); | ||
127 | } | ||
128 | |||
129 | static int read_config_dword(struct pci_config_swap *swap, | ||
130 | struct pci_dev *dev, u32 where, u32 * val) | ||
131 | { | ||
132 | u32 bus, slot_num, func_num; | ||
133 | u32 base; | ||
134 | |||
135 | db_assert((where & 3) == 0); | ||
136 | db_assert(where < (1 << 8)); | ||
137 | |||
138 | /* check if the bus is top-level */ | ||
139 | if (dev->bus->parent != NULL) { | ||
140 | bus = dev->bus->number; | ||
141 | db_assert(bus != 0); | ||
142 | } else { | ||
143 | bus = 0; | ||
144 | } | ||
145 | |||
146 | slot_num = PCI_SLOT(dev->devfn); | ||
147 | func_num = PCI_FUNC(dev->devfn); | ||
148 | base = ddb_access_config_base(swap, bus, slot_num); | ||
149 | *val = *(volatile u32 *) (base + (func_num << 8) + where); | ||
150 | ddb_close_config_base(swap); | ||
151 | return PCIBIOS_SUCCESSFUL; | ||
152 | } | ||
153 | |||
154 | static int read_config_word(struct pci_config_swap *swap, | ||
155 | struct pci_dev *dev, u32 where, u16 * val) | ||
156 | { | ||
157 | int status; | ||
158 | u32 result; | ||
159 | |||
160 | db_assert((where & 1) == 0); | ||
161 | |||
162 | status = read_config_dword(swap, dev, where & ~3, &result); | ||
163 | if (where & 2) | ||
164 | result >>= 16; | ||
165 | *val = result & 0xffff; | ||
166 | return status; | ||
167 | } | ||
168 | |||
169 | static int read_config_byte(struct pci_config_swap *swap, | ||
170 | struct pci_dev *dev, u32 where, u8 * val) | ||
171 | { | ||
172 | int status; | ||
173 | u32 result; | ||
174 | |||
175 | status = read_config_dword(swap, dev, where & ~3, &result); | ||
176 | if (where & 1) | ||
177 | result >>= 8; | ||
178 | if (where & 2) | ||
179 | result >>= 16; | ||
180 | *val = result & 0xff; | ||
181 | return status; | ||
182 | } | ||
183 | |||
184 | static int write_config_dword(struct pci_config_swap *swap, | ||
185 | struct pci_dev *dev, u32 where, u32 val) | ||
186 | { | ||
187 | u32 bus, slot_num, func_num; | ||
188 | u32 base; | ||
189 | |||
190 | db_assert((where & 3) == 0); | ||
191 | db_assert(where < (1 << 8)); | ||
192 | |||
193 | /* check if the bus is top-level */ | ||
194 | if (dev->bus->parent != NULL) { | ||
195 | bus = dev->bus->number; | ||
196 | db_assert(bus != 0); | ||
197 | } else { | ||
198 | bus = 0; | ||
199 | } | ||
200 | |||
201 | slot_num = PCI_SLOT(dev->devfn); | ||
202 | func_num = PCI_FUNC(dev->devfn); | ||
203 | base = ddb_access_config_base(swap, bus, slot_num); | ||
204 | *(volatile u32 *) (base + (func_num << 8) + where) = val; | ||
205 | ddb_close_config_base(swap); | ||
206 | return PCIBIOS_SUCCESSFUL; | ||
207 | } | ||
208 | |||
209 | static int write_config_word(struct pci_config_swap *swap, | ||
210 | struct pci_dev *dev, u32 where, u16 val) | ||
211 | { | ||
212 | int status, shift = 0; | ||
213 | u32 result; | ||
214 | |||
215 | db_assert((where & 1) == 0); | ||
216 | |||
217 | status = read_config_dword(swap, dev, where & ~3, &result); | ||
218 | if (status != PCIBIOS_SUCCESSFUL) | ||
219 | return status; | ||
220 | |||
221 | if (where & 2) | ||
222 | shift += 16; | ||
223 | result &= ~(0xffff << shift); | ||
224 | result |= val << shift; | ||
225 | return write_config_dword(swap, dev, where & ~3, result); | ||
226 | } | ||
227 | |||
228 | static int write_config_byte(struct pci_config_swap *swap, | ||
229 | struct pci_dev *dev, u32 where, u8 val) | ||
230 | { | ||
231 | int status, shift = 0; | ||
232 | u32 result; | ||
233 | |||
234 | status = read_config_dword(swap, dev, where & ~3, &result); | ||
235 | if (status != PCIBIOS_SUCCESSFUL) | ||
236 | return status; | ||
237 | |||
238 | if (where & 2) | ||
239 | shift += 16; | ||
240 | if (where & 1) | ||
241 | shift += 8; | ||
242 | result &= ~(0xff << shift); | ||
243 | result |= val << shift; | ||
244 | return write_config_dword(swap, dev, where & ~3, result); | ||
245 | } | ||
246 | |||
247 | #define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ | ||
248 | static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \ | ||
249 | { \ | ||
250 | return rw##_config_##unitname(pciswap, \ | ||
251 | dev, \ | ||
252 | where, \ | ||
253 | val); \ | ||
254 | } | ||
255 | |||
256 | MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) | ||
257 | MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) | ||
258 | MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) | ||
259 | |||
260 | MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) | ||
261 | MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) | ||
262 | MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) | ||
263 | |||
264 | struct pci_ops ddb5476_ext_pci_ops = { | ||
265 | extpci_read_config_byte, | ||
266 | extpci_read_config_word, | ||
267 | extpci_read_config_dword, | ||
268 | extpci_write_config_byte, | ||
269 | extpci_write_config_word, | ||
270 | extpci_write_config_dword | ||
271 | }; | ||
diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c deleted file mode 100644 index b74158d9b4b1..000000000000 --- a/arch/mips/pci/pci-ddb5074.c +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | #include <linux/kernel.h> | ||
2 | #include <linux/init.h> | ||
3 | #include <linux/types.h> | ||
4 | #include <linux/pci.h> | ||
5 | |||
6 | #include <asm/debug.h> | ||
7 | |||
8 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
9 | |||
10 | static struct resource extpci_io_resource = { | ||
11 | .start = 0x1000, /* leave some room for ISA bus */ | ||
12 | .end = DDB_PCI_IO_SIZE - 1, | ||
13 | .name = "pci IO space", | ||
14 | .flags = IORESOURCE_IO | ||
15 | }; | ||
16 | |||
17 | static struct resource extpci_mem_resource = { | ||
18 | .start = DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ | ||
19 | .end = DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, | ||
20 | .name = "pci memory space", | ||
21 | .flags = IORESOURCE_MEM | ||
22 | }; | ||
23 | |||
24 | extern struct pci_ops ddb5476_ext_pci_ops; | ||
25 | |||
26 | struct pci_controller ddb5476_controller = { | ||
27 | .pci_ops = &ddb5476_ext_pci_ops, | ||
28 | .io_resource = &extpci_io_resource, | ||
29 | .mem_resource = &extpci_mem_resource, | ||
30 | }; | ||
31 | |||
32 | #define PCI_EXT_INTA 8 | ||
33 | #define PCI_EXT_INTB 9 | ||
34 | #define PCI_EXT_INTC 10 | ||
35 | #define PCI_EXT_INTD 11 | ||
36 | #define PCI_EXT_INTE 12 | ||
37 | |||
38 | #define MAX_SLOT_NUM 14 | ||
39 | |||
40 | static unsigned char irq_map[MAX_SLOT_NUM] = { | ||
41 | [ 0] = nile4_to_irq(PCI_EXT_INTE), | ||
42 | [ 1] = nile4_to_irq(PCI_EXT_INTA), | ||
43 | [ 2] = nile4_to_irq(PCI_EXT_INTA), | ||
44 | [ 3] = nile4_to_irq(PCI_EXT_INTB), | ||
45 | [ 4] = nile4_to_irq(PCI_EXT_INTC), | ||
46 | [ 5] = nile4_to_irq(NILE4_INT_UART), | ||
47 | [10] = nile4_to_irq(PCI_EXT_INTE), | ||
48 | [13] = nile4_to_irq(PCI_EXT_INTE), | ||
49 | }; | ||
50 | |||
51 | int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
52 | { | ||
53 | return irq_map[slot]; | ||
54 | } | ||
55 | |||
56 | /* Do platform specific device initialization at pci_enable_device() time */ | ||
57 | int pcibios_plat_dev_init(struct pci_dev *dev) | ||
58 | { | ||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | void __init ddb_pci_reset_bus(void) | ||
63 | { | ||
64 | u32 temp; | ||
65 | |||
66 | /* | ||
67 | * I am not sure about the "official" procedure, the following | ||
68 | * steps work as far as I know: | ||
69 | * We first set PCI cold reset bit (bit 31) in PCICTRL-H. | ||
70 | * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. | ||
71 | * The same is true for both PCI channels. | ||
72 | */ | ||
73 | temp = ddb_in32(DDB_PCICTRL + 4); | ||
74 | temp |= 0x80000000; | ||
75 | ddb_out32(DDB_PCICTRL + 4, temp); | ||
76 | temp &= ~0xc0000000; | ||
77 | ddb_out32(DDB_PCICTRL + 4, temp); | ||
78 | |||
79 | } | ||
diff --git a/include/asm-mips/ddb5074.h b/include/asm-mips/ddb5074.h deleted file mode 100644 index 0d09ac27f9a5..000000000000 --- a/include/asm-mips/ddb5074.h +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | */ | ||
7 | |||
8 | extern void ddb5074_led_hex(int hex); | ||
9 | extern void ddb5074_led_d2(int on); | ||
10 | extern void ddb5074_led_d3(int on); | ||
11 | |||
diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h deleted file mode 100644 index 58d88306af65..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5074.h +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | */ | ||
7 | |||
8 | #ifndef _ASM_DDB5XXX_DDB5074_H | ||
9 | #define _ASM_DDB5XXX_DDB5074_H | ||
10 | |||
11 | #include <asm/nile4.h> | ||
12 | |||
13 | #define DDB_SDRAM_SIZE 0x04000000 /* 64MB */ | ||
14 | |||
15 | #define DDB_PCI_IO_BASE 0x06000000 | ||
16 | #define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */ | ||
17 | |||
18 | #define DDB_PCI_MEM_BASE 0x08000000 | ||
19 | #define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */ | ||
20 | |||
21 | #define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE | ||
22 | #define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE | ||
23 | |||
24 | #define NILE4_PCI_IO_BASE 0xa6000000 | ||
25 | #define NILE4_PCI_MEM_BASE 0xa8000000 | ||
26 | #define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE | ||
27 | #define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE | ||
28 | |||
29 | #define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS | ||
30 | #define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE) | ||
31 | #define CPU_NILE4_CASCADE 2 | ||
32 | |||
33 | extern void ddb5074_led_hex(int hex); | ||
34 | extern void ddb5074_led_d2(int on); | ||
35 | extern void ddb5074_led_d3(int on); | ||
36 | |||
37 | extern void nile4_irq_setup(u32 base); | ||
38 | #endif | ||
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h index 873c03f2c5fe..2c8c93430c1c 100644 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ b/include/asm-mips/ddb5xxx/ddb5xxx.h | |||
@@ -174,13 +174,8 @@ | |||
174 | 174 | ||
175 | static inline void ddb_sync(void) | 175 | static inline void ddb_sync(void) |
176 | { | 176 | { |
177 | /* The DDB5074 doesn't seem to like these accesses. They kill the board on | ||
178 | * interrupt load | ||
179 | */ | ||
180 | #ifndef CONFIG_DDB5074 | ||
181 | volatile u32 *p = (volatile u32 *)0xbfc00000; | 177 | volatile u32 *p = (volatile u32 *)0xbfc00000; |
182 | (void)(*p); | 178 | (void)(*p); |
183 | #endif | ||
184 | } | 179 | } |
185 | 180 | ||
186 | static inline void ddb_out32(u32 offset, u32 val) | 181 | static inline void ddb_out32(u32 offset, u32 val) |
@@ -260,9 +255,7 @@ extern void ddb_pci_reset_bus(void); | |||
260 | /* | 255 | /* |
261 | * include the board dependent part | 256 | * include the board dependent part |
262 | */ | 257 | */ |
263 | #if defined(CONFIG_DDB5074) | 258 | #if defined(CONFIG_DDB5476) |
264 | #include <asm/ddb5xxx/ddb5074.h> | ||
265 | #elif defined(CONFIG_DDB5476) | ||
266 | #include <asm/ddb5xxx/ddb5476.h> | 259 | #include <asm/ddb5xxx/ddb5476.h> |
267 | #elif defined(CONFIG_DDB5477) | 260 | #elif defined(CONFIG_DDB5477) |
268 | #include <asm/ddb5xxx/ddb5477.h> | 261 | #include <asm/ddb5xxx/ddb5477.h> |
diff --git a/include/asm-mips/mach-ddb5074/mc146818rtc.h b/include/asm-mips/mach-ddb5074/mc146818rtc.h deleted file mode 100644 index 2eb9acb10a5a..000000000000 --- a/include/asm-mips/mach-ddb5074/mc146818rtc.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1998, 2001, 03 by Ralf Baechle | ||
7 | * | ||
8 | * RTC routines for PC style attached Dallas chip. | ||
9 | */ | ||
10 | #ifndef __ASM_MACH_DDB5074_MC146818RTC_H | ||
11 | #define __ASM_MACH_DDB5074_MC146818RTC_H | ||
12 | |||
13 | #include <asm/ddb5xxx/ddb5074.h> | ||
14 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
15 | |||
16 | #define RTC_PORT(x) (0x70 + (x)) | ||
17 | #define RTC_IRQ 8 | ||
18 | |||
19 | static inline unsigned char CMOS_READ(unsigned long addr) | ||
20 | { | ||
21 | return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr); | ||
22 | } | ||
23 | |||
24 | static inline void CMOS_WRITE(unsigned char data, unsigned long addr) | ||
25 | { | ||
26 | *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data; | ||
27 | } | ||
28 | |||
29 | #define RTC_ALWAYS_BCD 1 | ||
30 | |||
31 | #endif /* __ASM_MACH_DDB5074_MC146818RTC_H */ | ||