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-rw-r--r--drivers/net/tg3.c69
-rw-r--r--drivers/net/tg3.h1
2 files changed, 43 insertions, 27 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 376d8e776936..73e271e59c6a 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -497,21 +497,20 @@ static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 unsigned long flags; 497 unsigned long flags;
498 498
499 spin_lock_irqsave(&tp->indirect_lock, flags); 499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
502 503
503 /* Always leave this as zero. */ 504 /* Always leave this as zero. */
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
505 spin_unlock_irqrestore(&tp->indirect_lock, flags); 506 } else {
506} 507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 tw32_f(TG3PCI_MEM_WIN_DATA, val);
507 509
508static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val) 510 /* Always leave this as zero. */
509{ 511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
510 /* If no workaround is needed, write to mem space directly */ 512 }
511 if (tp->write32 != tg3_write_indirect_reg32) 513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
512 tw32(NIC_SRAM_WIN_BASE + off, val);
513 else
514 tg3_write_mem(tp, off, val);
515} 514}
516 515
517static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) 516static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
@@ -519,11 +518,19 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
519 unsigned long flags; 518 unsigned long flags;
520 519
521 spin_lock_irqsave(&tp->indirect_lock, flags); 520 spin_lock_irqsave(&tp->indirect_lock, flags);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524 524
525 /* Always leave this as zero. */ 525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
527 spin_unlock_irqrestore(&tp->indirect_lock, flags); 534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
528} 535}
529 536
@@ -1367,12 +1374,12 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1367 } 1374 }
1368 } 1375 }
1369 1376
1377 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1378
1370 /* Finally, set the new power state. */ 1379 /* Finally, set the new power state. */
1371 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control); 1380 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1372 udelay(100); /* Delay after power state change */ 1381 udelay(100); /* Delay after power state change */
1373 1382
1374 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1375
1376 return 0; 1383 return 0;
1377} 1384}
1378 1385
@@ -6539,11 +6546,11 @@ static void tg3_timer(unsigned long __opaque)
6539 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 6546 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6540 u32 val; 6547 u32 val;
6541 6548
6542 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX, 6549 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6543 FWCMD_NICDRV_ALIVE2); 6550 FWCMD_NICDRV_ALIVE2);
6544 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); 6551 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6545 /* 5 seconds timeout */ 6552 /* 5 seconds timeout */
6546 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); 6553 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6547 val = tr32(GRC_RX_CPU_EVENT); 6554 val = tr32(GRC_RX_CPU_EVENT);
6548 val |= (1 << 14); 6555 val |= (1 << 14);
6549 tw32(GRC_RX_CPU_EVENT, val); 6556 tw32(GRC_RX_CPU_EVENT, val);
@@ -9539,8 +9546,11 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9539 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 9546 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9540 9547
9541 /* Do not even try poking around in here on Sun parts. */ 9548 /* Do not even try poking around in here on Sun parts. */
9542 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) 9549 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9550 /* All SUN chips are built-in LOMs. */
9551 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9543 return; 9552 return;
9553 }
9544 9554
9545 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 9555 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9546 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 9556 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
@@ -9638,9 +9648,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9638 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) 9648 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9639 tp->led_ctrl = LED_CTRL_MODE_PHY_2; 9649 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9640 9650
9641 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && 9651 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9642 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9643 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9644 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 9652 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9645 9653
9646 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 9654 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
@@ -10265,6 +10273,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10265 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); 10273 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10266 } 10274 }
10267 10275
10276 if (tp->write32 == tg3_write_indirect_reg32 ||
10277 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10278 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10279 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
10280 (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
10281 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10282
10268 /* Get eeprom hw config before calling tg3_set_power_state(). 10283 /* Get eeprom hw config before calling tg3_set_power_state().
10269 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be 10284 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10270 * determined before calling tg3_set_power_state() so that 10285 * determined before calling tg3_set_power_state() so that
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index b6484420e874..8c8b987d1250 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2171,6 +2171,7 @@ struct tg3 {
2171#define TG3_FLAG_PCIX_MODE 0x00020000 2171#define TG3_FLAG_PCIX_MODE 0x00020000
2172#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2172#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2173#define TG3_FLAG_PCI_32BIT 0x00080000 2173#define TG3_FLAG_PCI_32BIT 0x00080000
2174#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2174#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2175#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2175#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 2176#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2176#define TG3_FLAG_10_100_ONLY 0x01000000 2177#define TG3_FLAG_10_100_ONLY 0x01000000